User's Guide Using the UCD3138PSFBEVM-027 Literature Number: SLUUAK4 August 2013

Using the UCD3138PSFBEVM-027

User's Guide

Literature Number: SLUUAK4

August 2013

www.ti.com

WARNING

Always follow TI’s set-up and application instructions, including use of all interface components within their recommended electrical rated voltage and power limits. Always use electrical safety precautions to help ensure your personal safety and the safety of those working around you. Contact TI’s Product Information

Center http://support/ti./com for further information.

Save all warnings and instructions for future reference.

Failure to follow warnings and instructions may result in personal injury, property damage, or death due to electrical shock and/or burn hazards.

The term TI HV EVM refers to an electronic device typically provided as an open framed, unenclosed printed circuit board assembly. It is intended strictly for use in development laboratory environments, solely for qualified professional users having training, expertise, and knowledge of electrical safety risks in development and application of high-voltage electrical circuits. Any other use and/or application are strictly prohibited by Texas Instruments. If you are not suitably qualified, you should immediately stop from further use of the HV EVM.

1. Work Area Safety:

(a) Keep work area clean and orderly.

(b) Qualified observer(s) must be present anytime circuits are energized.

(c) Effective barriers and signage must be present in the area where the TI HV EVM and its interface electronics are energized, indicating operation of accessible high voltages may be present, for the purpose of protecting inadvertent access.

(d) All interface circuits, power supplies, evaluation modules, instruments, meters, scopes and other related apparatus used in a development environment exceeding 50 V

RMS

/75 VDC must be electrically located within a protected Emergency Power Off (EPO) protected power strip.

(e) Use a stable and non-conductive work surface.

(f) Use adequately insulated clamps and wires to attach measurement probes and instruments. No freehand testing whenever possible.

2. Electrical Safety:

(a) De-energize the TI HV EVM and all its inputs, outputs, and electrical loads before performing any electrical or other diagnostic measurements. Revalidate that TI HV EVM power has been safely deenergized.

(b) With the EVM confirmed de-energized, proceed with required electrical circuit configurations, wiring, measurement equipment hook-ups and other application needs, while still assuming the EVM circuit and measuring instruments are electrically live.

(c) Once EVM readiness is complete, energize the EVM as intended.

WARNING: while the EVM is energized, never touch the EVM or its electrical circuits as they could be at high voltages capable of causing electrical shock hazard.

3. Personal Safety:

(a) Wear personal protective equipment e.g. latex gloves and/or safety glasses with side shields or protect EVM in an adequate lucent plastic box with interlocks from accidental touch.

4. Limitation for Safe Use:

(a) EVMs are not to be used as all or part of a production unit.

Fusion Digital Power is a trademark of Texas Instruments.

2

Copyright © 2013, Texas Instruments Incorporated

SLUUAK4 – August 2013

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User's Guide

SLUUAK4 – August 2013

Using the UCD3138PSFBEVM-027

1 Introduction

This evaluation model (EVM), the UCD3138PSFBEVM-027, is used to evaluate the UCD3138 64-pin digital control IC in an off-line power-converter application and then to aid in its design. The EVM is a standalone phase-shifted full-bridge DC-DC power converter. The EVM is used together with a control card, the UCD3138CC64EVM-030, which is an EVM placed on the UCD3138RGC.

The UCD3138PSFBEVM-027, together with the UCD3138CC64EVM-030, evaluates a phase-shifted fullbridge DC-DC converter. Each EVM is delivered without requiring additional work, from either hardware or firmware. This EVM combination allows for some of the design parameters to be retuned using Texas

Instruments' graphical user interface (GUI) based tool, Fusion Digital Power™ Designer. Loading custom firmware with user-designed definition and development is also possible.

Three EVMs are included in the kit: the UCD3138PSFBEVM-027, UCD3138CC64EVM-030, and USB-TO-

GPIO.

This user’s guide provides basic evaluation instruction with a focus on system operation in a standalone phase-shifted full-bridge DC-DC power converter.

WARNING

High voltages are present on this evaluation module during operation and for a a time period after power off. This module should only be tested by skilled personnel in a controlled laboratory environment.

An isolated DC voltage source meeting IEC61010 reinforced insulation standards is recommended for evaluating this EVM.

High temperature exceeding 60°C may be found during EVM operation and for a time period after power off.

The purpose of this EVM is to facilitate the evaluation of digital control in a phase-shifted full-bridge DC-DC converter using the

UCD3138, and cannot be tested and treated as a final product.

Extreme caution should be taken to eliminate the possibility of

electric shock and heat burn. Please refer to the page Evaluation

Module Electrical Safety Guideline after the cover page for your

safety concerns and precautions.

Read and understand this user’s guide thoroughly before starting any physical evaluation.




Using the UCD3138PSFBEVM-027

3

Description

2 Description

www.ti.com

The UCD3138PSFBEVM-027, along with the UCD3138CC64EVM-030, demonstrates a phase-shifted fullbridge DC-DC power converter with digital control using the UCD3138 device. The UCD3138 device is located on the UCD3138CC64EVM-030 board. The UCD3138CC64EVM-030 is a daughter-card with preloaded firmware providing the required control functions for an phase-shifted full-bridge converter.

Please contact TI for details on the firmware. The UCD3138PSFBEVM-027 accepts a DC input from 370 to 400 VDC, and outputs a typical 12 VDC with full-load output power at 360 W, or full output current of 30

A.

NOTE:

This EVM does not have an input fuse. It relies on the input current limit from the input voltage source that is used.

2.1

Typical Applications

• Offline DC-DC power conversions

• Servers

• Telecommunication systems

2.2

Features

• Digitally-controlled phase-shifted full-bridge DC-DC power conversion

• DC input from 370 to 400 VDC

• 12-VDC regulated output from no load to full load

• Full-load power at 360 W, or full-load current at 30 A

• High efficiency

• Constant soft-start time

• Overvoltage, overcurrent, and brownout protection

• Test points to facilitate device and topology evaluation

4





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3 Performance Specifications

Performance Specifications

Table 1. UCD3138PSFBEVM-027 Performance Specifications

(1)

PARAMETER

Input Characteristics

Voltage operation range

Input UVLO On

Input UVLO Off

TEST CONDITIONS

Input current

Input = 370 VDC, full load = 30 A


Output Characteristics


Output voltage, VOUT No load to full load

Output over voltage

Output load current,

IOUT

(1)

370 to 400 VDC

Output voltage ripple 385 VDC and full load = 30 A

Output over current

MIN

370

TYP

350

330

12

13.5

MAX

400

1.2

1.1

1

30

UNITS

VDC

VDC

VDC

A

VDC

VDC

A

30

90 mVpp

A

Systems Characteristics

Switching frequency

Peak efficiency

Full-load efficiency

Operating temperature

Firmware

385 VDC, full load = 30 A

385 VDC, load = 30 A

400-LFM forced air flow cooling

140

93.5

93.5

25 kHz

(1)

Device ID (Version)

Filename

UCD3100ISO1 | 0.0.01.0001|130315

UCD3138PSFBPWR027_03152013.x0

The load current and load power are commanded using the designer GUI. See

Section 12

for more information on CPCC operation. See

Section 13

for more information on GUI application.

%

%

°C





5

Schematics

4 Schematics

www.ti.com

R5

100

C43

J1

9

TP1

+VIN

+400-V Input

10

T4

1:1:1

6

R34

100

C28

VAUXS

VAUXS

1

2

5

TP2

J11

400-V Return

R4

C66

47µF

+

D21

STPS130A

R6

2.43

DPWM3B

7.50

2.43

DPWM3A

10

9

C18

µ

C25

R2

T3

+VIN

J9

1

1:1:1

6

2

5

D24

TP3

STPS130A

R7

7.50

C36

µ

R1

5.11k

D22

BAV70-V

2.43

8

7

U4

UCC27424DGN

1

ENBB ENBA

OUTA

INA

2

6

VDD GND

3

5 4

OUTB

PWPD

INB

8

7

U5

UCC27424DGN

1

ENBB ENBA

OUTA

INA

2

6 3

VDD GND

5

OUTB

PWPD

INB

4

D20

C56

0.1uF

D8

R35

C44

D23

BAV70-V

C61

4700pF

C50

4700pF

TP26

TP27

D19

TP33

R3

5.11k

STPS130A

R36

7.50

DPWM2A

R9

2.43

DPWM2B

OVP_LATCH

DPWM2B

DPWM2A

OVP_LATCH

DPWM3A

DPWM3B

BUS+

BUS_ITRAN

QT1

D10

L2

QB1

D9

TP34

C53

TP28

0.1uF

D27

D16

R46

7.50

R8

5.11k

D25

TP36

D18

BAV70-V

C54

+VIN

VAUXPRI

D17

QB2

BAV70-V

Isolation Boundary

Primary

R32

0

R19

0

C59

C60

2

HS1

1 2

BUS_ITRAN

2

BUS+

QT2

TP29

R10

5.11k

TP4

TP5

1

HS2

6

T1

2

T2

1

3

TP35

1 2

Secondary

12

11

10

9

8

7

4

2

T5

1

1

3

U6

PWR050

1

VIN+

2

VAUX_P

3

-VAUX_-VIN

4

-VIN

R20

15.0k

80mH

Auxiliary Bias Supply

C46

4

D6

MBRS1100

D5

MBRS1100

R21

15.0k

HS3

TP6

VAUX_S

7

VIN_MONITOR

6

5

GND

TP7

D7

C21

100pF

R23

2.49k

TP25

D12

BAT54S

D14

R12

51.1

TP8

D1

BAT54S

C19

10nF

MMBD914

R100

1.0k

R93

1.0k

R11

51.1

Current Doubler Rectifier and Filter

C20

100pF

QSYN1

QSYN2

R28

150

R71

150

L1

TP17

TP19

Q10

SI7866ADP

C7

+RS

1nF

QSYN3

R47

R48

1.00

10.0k

TP20

HS4

1 2

IS-

DPWM1B

Q6

SI7866ADP

R55

15.0

+VO

R25

1.00

VAUXS

R24

10.0k

TP22

C22

8

U3

UCC27424DGN

1

ENBB ENBA

7

OUTA

6

VDD

5

OUTB

PWPD

2

INA

GND

3

4

INB

R90

10.0k

R104

0.003

R52

1.21k

R51

1.21k

C1

47 F

ORING_GATE

C2

µ

C3

µ

TP14

QSYN4

R73

1

TP24

R26

10.0k

R27

1.00

C55

µ

TP21

R29

1

I_PRI

VAUXS

R66

10.0k

R70

1.00

R31

3.32k

C23

220pF

C17

100pF

8

7

U8

UCC27424DGN

1

ENBB

ENBA

2

OUTA INA

6

VDD

5

OUTB

PWPD

GND

3

4

INB

AD_06

VAUXS

R53

0.003

R105

0.003

IS-

IS-

DPWM0B

R88

10.0k

R39

10.0k

R40

10.0

AGND

Primary Current Sense

TP9

TP12

R72

1

C64

220pF

GPIO/ORING_CTRL

R42

10.0k

R41

100k

C11

10nF

C5

1nF

R54

15.0

R50

1.21k

R49

1.21k

R37

TP16

TP15

C65

µ

10.0k

R38

549

1

2

3

4

5

6

7

C8

U1

TPS2411PW

100pF

14

VDD PG

13

RSET BYP

12

STAT FLTR

11

FLTB A

10

OV C

9

UV RSVD

8

GND

GATE

+VO1

-RS

R103

5.11k

C9

0.1uF

C71

C10

0.1 F

J8

100pF

C63

µ

+

C4

C16

4700pF

AGND

P3

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

DPWM_0A

DPWM_0B

DPWM_1A

DPWM_1B

DPWM_2A

DPWM_2B

DPWM_3A

DPWM_3B

ORing Control

DPWM0A

DPWM0B

DPWM1A

DPWM3A

DPWM3B

EAP2

DPWM1B

DPWM2A

3.3V_EXT

DPWM2B

AGND

C58

µ

R77

2.05k

AD_02/I_SHARE

ORING_GATE

R87

1

R17

36.5k

C67

330pF

1

0

C24

+12-V Output

+VO1

+

C62

AGND

R30

J3

J4

12-V Return

+VO

C6

4700pF

+RS

-RS

30A

J2

1

2

3

R91

220

C12

10nF

TP23

R78

1.24k

I_PRI

VINSCALED

VAUXS

VAUXS

R43

1.00

C13

µ

1

2

IN

3.3V_EXT

U9

TPS715A33

8

OUT

7

NC NC

3

NC

4

GND

PWPD

9

6

NC

FB/NC

5

R45

100k

R44

1

C14

10nF

TP32

DPWM0A

R22

0.5

DPWM1A

C15

Q2

1

Q8

1

Q4

1

External Slope Compensation

AGND

Q1

1

2200pF

1 Parts not populated

IS-

Figure 1. UCD3138PSFBEVM-027 Schematics, Sheet 1 of 2

6





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Schematics

ISEC

R74

0.0343 x Iout

EAP1

2.00k

R75

3.32k

C42

100pF

R76

EAN1

AGND

0

Current buffer and noise filter

3.3V_EXT

C37

0.1uF

U10

LM60C

Temp = 0.5 + .01*T

1

+VS

GND

VOUT

2

AD_07

C38

10nF

AGND

AGND

Temperature sensor

TP41

3.3V_EXT

R65

10.0k

S1

C39

10nF

ON/OFF

ON/OFF Manual Switching and noise conditioning

OV threshold at 15.6 V

+VO

R81

499

D15

15V

Q7-A

MMDT3946

R89

4.99k

C51

2200pF

+VO1

+VO

R79

16.2k

C45

1nF

R80

1.82k

AD_03

AGND

R82

16.2k

C47

1nF

0.1 x Vout

R83

1.82k

AD_09

AGND

3.3V_EXT

AGND

D13

BAT54S

VINSCALED

ISEC

R84

1.00k

AD_08

C48

1nF

AGND

R85

AD_13

1.00k

C49

1nF

R15 R16

PWM0

1

C57

10nF

1

AGND

AGND

Noise reducing low pass filtering

C31

0.1µF

C29

C32

0.1 F

CHASSIS

1

2

3

4

5

6

7

8

U7

EN

SN75C3221

FORCEOFF

16

C1+

V+

C1-

C2+

C2-

V-

R1IN

VCC

15

GND

14

T1OUT

13

FORCEON

12

T1IN

11

INVALID

10

R1OUT

9

C33

C30

µ

SCI_RX1

SCI_TX1

3.3V_EXT

J6

8

4

9

7

3

1

6

2

5

J7

GPIO/ACFAIL_IN

1

2

3

4

5

6

3.3V_EXT

SCI_RX0

SCI_TX0

Serial UART Interface

C69

C70

EMI Control

R92

10.0k

R86

499

Q7-B

MMDT3946

3.3V_EXT

R18

10.0k

C26

1500pF

OVP Latch

OVP_LATCH

IS-

3.3V_EXT

R102

1

R68

1.00k

R67

1.00k

U2

OPA345NA

C34

220pF

R69

49.9K

3.3V_EXT

R13

10.0

TP37

0.0549 x Iout

ISEC

C35

0.1uF

AGND

Current Sense Amplifier (Low Offset/ X66.5)

1 Parts not populated

R14

0

AGND

Ground connection

P1

+RS

R94

549

R95

549

R96

549

D11

R97

16.2k

0.1 x Vout

EAP0

+VO1

R98

1.82k

C52

1nF

-RS

R99

1.62k

C27

100pF

Output voltage divider and noise filter

AGND

EAN0

3.3V_EXT

GPIO/P_GOOD

R56

3.32k

R58

10.0k

3.3V_EXT

3.3V_EXT

R60

301

301

R63

D3

LTST-C190GKT

Q3

MMBT3904LT1G

GPIO/FAILURE

D2

LTST-C190CKT

R62

3.32k

Q9

MMBT3904LT1G

R64

10.0k

GPIO/ACFAIL_OUT

R59

3.32k

R61

10.0k

R57

301

VAUXPRI

R33

1.00k

D4

LTST-C190GKT

D26

LTST-C190CKT

Q5

MMBT3904LT1G

Power On

LED Status indicators

Figure 2. UCD3138PSFBEVM-027 Schematics Sheet, 2 of 2

26

27

28

29

30

31

32

33

34

35

36

37

38

39

40

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

C68

10nF

R101

100k

P2

TP13

DPWM_0A

DPWM_0B

DPWM_1A

DPWM_1B

DPWM_2A

DPWM_2B

DPWM_3A

DPWM_3B

GPIO/ACFAIL_IN

GPIO/ACFAIL_OUT

ON/OFF

GPIO/FAILURE

24

25

26

27

28

29

30

31

32

33

34

35

36

37

38

39

40

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

17

18

19

20

21

22

23

AGND

AD00

AD_02/I_SHARE

AD_03

AD_04

AD_05

AD_06

AD_07

AD_08

AD_09

AD_13

EAP2

EAN1

EAP1

EAN0

EAP0

GPIO/P_GOOD

SCI_TX1

SCI_RX1

PWM0

GPIO/ORING_CTRL

SCI_TX0

SCI_RX0

VAUXS

1

2

3

J5

3.3V_EXT

C40

0.1µF

C41




7


Schematics

www.ti.com

TP1

3.3VA

3.3VD

/RESET

DGND

AD-09

AD-10

AD-11

AD-12

AD-13

R1

1

R2

1

R3

1

R4

1

R6

0

R39

10

J1

3.3VD

TP6

R12

1.65K

R21

R27

5

6

7

8

3

4

1

2

9

10

TP5

2K

R29 2K

S1

C13

RESET

C14

1000pF

AGND

2K

TP34

1

R22

R28

2K

2K

R5 100

D1

BAT54A

PMBUS-CTRL

PMBUS-ALERT

3.3VD

R14

1.5K

R13

1.5K

C2 C1

AGND

C3

0.1µF

C4

R7

100

R8 100

PMBUS-DATA

TP4

C10 33pF

J2

DGND

R15

100K

AD-00

AD-00

AD-01

AD-02

TP32

1

DGND

AD-03

AD-04

AD-05

AD-06

AD-07

AD-08

R9

R17

R19

R23

R24

100

D2

BAT54A

TP10

1

EADC-P0

EADC-N0

EADC-P1

EADC-N1

EADC-P2

EADC-N2

100

100

100

2K

R16

TP8

R25

R26

1

PMBUS-CLK

TP9

1

TP21

100

R18 100

R20

100

100

100

1

TP24

1

TP11

1

TP23

1

TP22

1

TP25

1

PWM-0

PWM-1

TP26

1

C17

33pF

C15

33pF

TP27

1

TP7

TP28

1

C16

33pF

C9

TP29

1

33pF

DGND

TP30

1

TP31

1

TP33 TP35 TP36

1

1

1

C19

C18

C21

C20 C23 C22

C25

C24

C27

C26

C29

C28 C30 C31

1000pF 1000pF 1000pF

1000pF 1000pF

1000pF 1000pF 1000pF

1000pF 1000pF 1000pF 1000pF

1000pF

1000pF

31

60

8

7

32

28

27

16

15

53

54

55

59

58

61

6

5

62

63

4

64

3

2

50

51

52

PWM0

PWM1

PMBUS_CTRL

PMBUS_ALERT

PMBUS_DATA

PMBUS_CLK

EAP0

EAN0

EAP1

TCK

TDO

37

38

TDI

TMS

RESET

39

40

11

U1

UCD3138RGC

TCAP

41

EAN1

EAP2

EAN2

AD01

AD00

AD02

AD03

AD04

AD05

AD06

AD07

AD08

AD09

AD10

AD11

AD12

AD13

65

PWPD

DPWM0A

17

DPWM0B

18

DPWM1A

DPWM1B

19

20

DPWM2A

21

DPWM2B

22

DPWM3A

DPWM3B

23

24

INT_EXT

34

ADC_EXT

12

SCI_RX0

SCI_TX0

SYNC

13

14

26

FAULT0

35

FAULT1

FAULT2

36

42

FAULT3

43

SCI_TX1

29

SCI_RX1

30

NS1

AGND

1

DGND

1

C11

C5

DGND

C12

DGND

TCK

TDO

TDI

TMS

/RESET

TP16

TP12 TP13

TP14 TP15

TP17 TP18

TP19 TP20

INT-EXT

EXT-TRIG

SCI-RX0

SCI-TX0

SYNC

FAULT-0

FAULT-1

FAULT-2

FAULT-3

SCI-TX1

SCI-RX1

3.3VD

C6

Parts not used

R11 16K

C8

1000pF

DGND

TCAP

DPWM-0A

DPWM-0B

DPWM-1A

DPWM-1B

DPWM-2A

DPWM-2B

R10

10K

DPWM-3A

DPWM-3B

TP2

TP3

C7

100pF

DGND

Figure 3. UCD3138CC64EVM-030 Schematics, Sheet 1 of 2

8





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Schematics



J3

PPPN202FJFN

25

26

27

28

29

30

31

32

17

18

19

20

21

22

23

24

33

34

35

36

37

38

39

40

9

10

11

12

13

14

15

16

5

6

7

8

1

2

3

4

AGND

AD-05

AD-06

AD-07

AD-08

AD-09

AD-00

AD-01

AD-02

AD-03

AD-04

AD-10

AD-11

AD-12

AD-13

EADC-N2

EADC-P2

EADC-N0

EADC-P0

EADC-N1

EADC-P1

J4

PPPN202FJFN

25

26

27

28

29

30

31

32

17

18

19

20

21

22

23

24

33

34

35

36

37

38

39

40

9

10

11

12

13

14

15

16

7

8

5

6

3

4

1

2

DGND

3.3VD

J6

If needed, use this jumper to provide 3.3VD to application board

DPWM-0A

DPWM-0B

DPWM-1A

DPWM-1B

DPWM-2A

DPWM-2B

DPWM-3A

DPWM-3B

SCI-TX1

SCI-RX1

PWM-0

PWM-1

SYNC

FAULT-0

FAULT-1

FAULT-2

FAULT-3

TCAP

SCI-TX0

SCI-RX0

INT-EXT

EXT-TRIG

/RESET

+12V_EXT

TMS

TDI

TDO

TCK

3.3VD

R33

10K

R36

0

R32

10K

R35

10K

R34

0

R37 10K

3.3VD

9

10

11

12

13

14

5

6

7

8

3

4

1

2

J5

3.3VD

R30

0.5

D3

R31

301

C33

10µF

C34

0.1µF

U2

TPS715A33DRBR

8 OUT

IN

1

7 NC

6 NC

5 FB/NC

NC

2

NC

3

GND

4

R38 10K

DGND

Figure 4. UCD3138CC64EVM-030 Schematics, Sheet 2 of 2

TP37

+12V_EXT

C32

1µF

DGND


9


Test Setup

5 Test Setup

www.ti.com

5.1

Test Equipment

DC voltage source: This source is capable of 350 to 400 VDC. The source is adjustable, with a minimum power rating of 400 W, or current rating no less than 1.5 A, and has a current limit function. The DC voltage source used should meet IEC61010 safety requirements.

DC multi-meter: The multi-meter has two units, one is capable of a 0 to 400 VDC input range and preferred four-digit display. The other unit is capable of a 0 to 15 VDC input range and a preferred fourdigit display.

Output load: This DC load is capable of receiving 0 to 15 VDC, 0 to 30 A, and 0 to 360-W or greater, with display such as load current and load power.

Current meter: If the load does not have a display, this DC current-meter is optional. This unit is capable of 0 to 30 A. A low-ohmic shunt and DMM are recommended.

Oscilloscope: The oscilloscope is capable of 500-MHz full bandwidth, digital or analog. If choosing a digital oscilloscope, TI recommends 5 Gs/s or better.

Fan: A fan with 400-LFM forced-air cooling is required.

Recommended wire gauge: The recommended gauge must be capable of 30 A, or better than No. 14

AWG, with the total wire length less than 8 ft (4-ft input and 4-ft return).

5.2

Recommended Test Setup

P2

P3

1 2

3 4

5 6

7 8

9 10

11 12

13 14

15 16

PWR030 P1

S1

D2

D3

D4

J6

+VIN

J1

TP1

-VIN

J11

TP2

TP17

J3

+VOUT

TP15

J4

-VOUT

D26

PWR050

Figure 5. UCD3138PSFBEVM-027 Recommended Test Setup

10





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Test Points

Figure 6. Orientation of the UCD3138CC64EVM-030 Board on the UCD3138PSFBEVM-027 Board

6 Test Points

TP11

TP12

TP13

TP14

TP15

TP16

TP17

TP18

TP19

TP20

TP21

TP22

TP23

TP24

Test Points

TP1

TP2

TP3

TP4

TP5

TP6

TP7

TP8

TP9

TP10



Not used

FLTB

PGND

+VO1

PGND

–RS

VO

Not used

+RS

SR1-3

SR2-4

IS–

AGND

Ipri

Table 2. UCD3138PSFBEVM-027 List of Test Points

Name

+VIN

–VIN

BUS+

VAUXPRI

PWRGND

VAUX_S

PGND

VINSCALED

Ipri

Description

Positive input voltage

Input voltage return

Primary high-side current-sense input

Primary 12-V bias

Primary 12-V bias return

Secondary 12-V bias

Secondary 12-V bias return

VIN sense on the secondary side

Primary current sense

Control-card mechanical-guide pin

Oring control

Secondary 12-V bias return

Output before oring FETs

Secondary 12-V bias return

Remote sense of the output voltage

Output voltage positive terminal

Remote sense of the output voltage

QSYN 1 and 3 drive

QSYN 2 and 4 drive

Load current sense

Analog ground

Primary current sense (AD_06)


11


Terminals

Test Points

TP25

TP26

TP27

TP28

TP29

TP30

TP31

TP32

TP33

TP34

TP35

TP36

TP37

TP38

TP39

TP40

TP41

7 Terminals

Table 2. UCD3138PSFBEVM-027 List of Test Points (continued)

Description Name

AGND

QT1_Gate

QB1_Gate

QT2_Gate

QB2_Gate

Not used

Not used

3.3V

SW1

PWRGND

SW2

CASS

ISEC

Not used

Not used

Not used

S1

Analog ground

QT1 gate

QB1 gate

QT2 gate

QB2 gate

3.3 V

Switch node

Primary 12-V bias return

Switch Node

Primary commutation-assist junction

IOUT sensing output (EADC1 Input)

S1 status

Terminal

J1

J2

J3

J4

J5

J6

J7

J8

J9

J10

J11

Table 3. List of Terminals

Name

Input_P

Remote Sense

12VO

–12VO

Bias

UART1

UART0

VO_RIPPLE

Jumper

Jumper

Input_N

Description

Input voltage positive terminal

Remote sense and I_SHARE

+12-V output

12-V output return

VAUX_S and 3.3V_EXT

Standard UART connection, RS232, 9-pin

UART0 and ACFAIL_IN (communication with PFC)

BNC VO_Ripple

Jumper (reserved to an input-fuse substitution)

Used when T5 not populated

Input voltage return terminal www.ti.com

12





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8 Test Procedure

8.1

Efficiency Measurement Procedure

WARNING

Danger of electrical shock!

High voltage present during measurement!

Test Procedure

CAUTION

Do not leave the EVM powered when unattended.

CAUTION

Danger of heat burn from high temperature.

1. See

Figure 4

for basic setup to measure power-conversion efficiency. The required equipment for this measurement is listed in

Figure 5 .

2. Check the boards visually before making electrical connections to ensure that no shipping damage occurred.

3. Use the UCD3138PSFBEVM-027 and UCD3138CC64EVM-030 for this measurement which are included this EVM package along with the USB-TO-GPIO.

4. Install the UCD3138CC64EVM-030 board onto the UCD3138PSFBEVM-027 first. Take care with the alignment and orientation of the two boards to avoid damage.

• See

Figure 6

for the UCD3138PFCEVM-030 board orientation.

5. Connect the DC-voltage source to J1 (+) and J11 (–). The DC-voltage source should be isolated and meet IEC61010 requirements.

• Set up the DC-output voltage in the range specified in

Table 1

, between 370 VDC and 400V DC; set the DC-source current limit at 1.2 A.

NOTE:

A fuse is not installed on the board and, therefore, the board relies on the current limit of the external voltage source for circuit protection.

6. Connect an electronic load with either a constant-current mode or constant-resistance mode. The load range is from 0 to 30 A.

7. Ensure a jumper is installed on J6 of the UCD3138CC64EVM-030

8. Use the switch S1 to turn on the board output after the input voltage is applied to the board. Before applying input voltage, ensure that the switch, S1, is in the OFF position.

9. Use a current meter or low-ohmic shunt and DMM between the load and the board for current measurements if the load does not have a current or a power display.

10. Connect a volt-meter across the output connector and set the volt-meter scale at 0 to 15 V (DC).

11. Turn on the DC-voltage source output. Flip S1 to ON and vary the load.

12. Record output voltage and current measurements.

8.2

Equipment Shutdown Procedure

1. Shut down the DC-voltage source

2. Shut down the electronic load.





13

Performance Data and Typical Characteristics Curves

9 Performance Data and Typical Characteristics Curves

www.ti.com

Figure 7

,

Figure 8

,

Figure 9

,

Figure 10

,

Figure 11 ,

Figure 9 , Figure 10 ,

Figure 12 ,

Figure 13

,

Figure 14 ,

and

Figure 15

present typical performance curves for the UCD3138PSFBEVM-027.

9.1

Efficiency

100

95

90

85

80

75

70

65

60

5 10 15 20

Load Current (A)

25

370 VDC

385 VDC

400 VDC

30

C001

Figure 7. UCD3138PSFBEVM-027 Efficiency

9.2

Load Regulation

12.3

12.1

11.9

11.7

11.5

11.3

5 10 15 20

Load Current (A)

25

370 VDC

385 VDC

400 VDC

30

C002

Figure 8. UCD3138PSFBEVM-027 Load Regulation

14





www.ti.com

9.3

Switching Waveforms


Figure 9. Gate-Drive Signals at No Load

Figure 10. Gate-Drive Signals at Full Load

Ch1 = QT1 gate to GND (TP26)

Ch3 = QSYN1 Vgs (TP20)

Ch2 = QB2 Vgs (TP29)

Ch4 = QSYN2 Vgs (TP21)





15


www.ti.com

Ch1 = QB1 Vgs

Ch3 = QB2 Vgs

9.4

Output Voltage Ripple

Figure 11. Primary-Side Switching

Ch2 = QB1 Vds

Ch4 = QB2 Vds

Figure 12. Output Voltage Ripple, 385 VDC and Full Load

16





www.ti.com


9.5

Output Turnon

Figure 13. Output Voltage Ripple, 385 VDC and Half Load

Figure 14. Output Turnon, 385 VDC With Load Range





17

EVM Assembly Drawing and PCB layout

9.6

Bode Plots

www.ti.com

Figure 15. Control-Loop Bode Plots at 385 VDC Across Load Range

10 EVM Assembly Drawing and PCB layout

Figure 16 ,

Figure 17 , Figure 18

,

Figure 19

,

Figure 20

and

Figure 21

show the design of the

UCD3138PSFBEVM-027 printed circuit board (PCB). The PCB dimensions are L × W = 8 × 6 in, the PCB material is FR4, or compatible, four layers with 2-oz copper on each layer.

Figure 16. UCD3138PSFBEVM-027 Top-Layer Assembly Drawing (Top view)

18





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Figure 17. UCD3138PSFBEVM-027 Bottom-Layer Assembly Drawing (Bottom view)

Figure 18. UCD3138PSFBEVM-027 Top Copper (Top View)





19


Figure 19. UCD3138PSFBEVM-027 Internal Layer, One (Top View)

www.ti.com

Figure 20. UCD3138PSFBEVM-027 Internal Layer, Two (Top View)

20





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Bill of Materials

Figure 21. UCD3138PSFBCEVM-027 Bottom Copper (Top View)

11 Bill of Materials

Table 4. Component List Based on the Schematics of Figure 1 and Figure 2

(1)

7

2

1

0

2

1

1

1

1

2

3

0

1

1

3

2

1

1

QTY RefDes

4 C1, C2, C3, C63

7

C11, C12, C14, C38,

C39, C57, C68

C13

C15

C17, C27, C42

C18, C25

Value

47 µF

10 nF

4.7 µF

10 µF

100 pF

1 µF

1 C19 10 nF

2 C20, C21 100 pF

C22, C28, C36, C43,

10 C53, C54, C55, C56, 0.1 µF

C69, C70

C23, C34, C64

C24

C26

C33

C4, C62

220 pF

Open

1500 pF

1 µF

1000 µF

1.5 µF

2200 pF

C44

C46

C5, C7, C45, C47,

C48, C49, C52

C50, C61

C51

C59, C60

C6, C16

C65

C66

1 nF

4700 pF

2200 pF

Open

4700 pF

0.1 µF

47 µF

Description

Capacitor, Ceramic, 16 V, X5R, 20%



Capacitor, Ceramic, 6.3 V, X7R, 10%




Capacitor, Ceramic, 100 V, NP0, 10%






Capacitor, Aluminum, SM, 25 V,

Capacitor, Polyester, 450 V, ±10%

Capacitor, Ceramic Disc, Y1, 250 V, Y5U ±20%




Capacitor



Capacitor, Alum Electrolytic, 450 V, ±20%

Size

1210

0603

0805

0805

0603

0805

0805

1206

0805

0603

0603

0603

0603

12,5 × 20 mm

1.012 × 0.322 in

.5 × .31 in

0603

1210

0603

1210

1206

1206

10 × 20 mm

Part Number

STD

STD

STD

STD

STD

STD

STD

STD

STD

STD

STD

STD

STD

EEUFM1E102

ECQ-E2W155KH

CD12-E2GA222MYGS

STD

STD

STD

STD

STD

STD

LGU2W470MELY

MFR

STD

STD

STD

STD

STD

STD

STD

STD

STD

STD

STD

STD

STD

Panasonic

Panasonic

TDK

STD

STD

STD

STD

STD

STD

NichiCon

(1)

STD = standard




21


Bill of Materials

www.ti.com

Table 4. Component List Based on the Schematics of

Figure 1

and

Figure 2

(1)

(continued)

2

1

1

1

4

1

2

4

2

1

1

2

4

1

2

2

1

0

3

2

1

2

2

1

1

1

4

4

3

1

2

2

2

1

QTY RefDes

1 C67

Value

330 pF

2 C8, C71 100 pF

C9, C10, C29, C30,

11 C31, C32, C35, C37, 0.1 µF

C40, C41, C58

2 D1, D11 MMBD914

D12, D13, D14

D15

D16, D19, D21, D24

D17, D18, D22, D23

D2, D26

D3, D4

D5, D6

D7

Description




BAT54S

15 V

STPS130A

BAV70-V

Diode, Switching, 100 V, 200 mA

Diode, Dual Schottky, 30 V, 200 mA

Diode, Zener, 15 V, 8. 5mA

Diode, Power Schottky, 30 V, 1 A

Diode, Switching, Dual, 70 V, 250 mA

LTST-C190CKT Diode, LED, Red, 2.1-V, 20-mA, 6-mcd

LTST-C190GKT Diode, LED, Green, 2.1-V, 20-mA, 6-mcd

MBRS1100 Diode, Schottky, 100 V, 1 A

SMCJ43A TVS 1500-W 43-V UNIDIRECTIONAL

4

2

4

1

4

0

1

15

5

2

D8, D20, D25, D27

D9, D10

MMSZ5222BT3

G/2.5 V

STTH5R06B

Diode, Zener, 2.5 V, 20 mA

Diode, Ultra-Fast High-Power Rectifier, 600 V, 5 A

HS1, HS2, HS3, HS4

J1, J3, J4, J11

J10

J2, J5

J6

531002B02500G

Heatsink, TO-220, Vertical-mount with Solderable pins

Terminal Block, 2-pin, 15 A, 5,1 mm ED120/2DS

923345-04-C

PEC03SAAN

Jumper, 0.400-in length, PVC Insulation, AWG 22,

Header, Male 3-pin, 100-mil spacing,

182-009-212-171 Connector, 9-pin D, Right Angle, Female

J7

J8

PEC03DAAN

131-4244-00

J9

L1

L2

8021

2.2 µH

22 µH

Header, Male 2- × 3-pin, 100 mil spacing

Adaptor, 3,5-mm probe clip (or 131-5031-00)

Jumper, 1.2-in length, Solid Tinned Copper, AWG

22, Noninsulated

Inductor, 1.83 m

Ω, 100 A

Inductor, 1.83 m Ω, 100 A

P1, P2

P3

Q1, Q2, Q4, Q8

Q3, Q5, Q9

Q6, Q10

87758-4016

PEC08DAAN

Open

MMBT3904LT1G Trans, NPN, 40 V, 20 0mA, 225 mW

SI7866ADP

MMDT3946

STP12NM50

Header, 40-pin, 2-mm Pitch

Header, Male 2- × 8-pin, 100-mil spacing

MOSFET, Nch, 25 V, 220 mA, 5

MOSFET, NCh, 20 V, 40 A, 3 m

Ω

Ω

Transistor, Dual NPN, 60V, 200mA, 200mW

MOSFET, N-ch, 550-V, 12-A, 0.35-ohms

Q7

QB1, QB2

QSYN1, QSYN2,

QSYN3, QSYN4

QT1, QT2

R1, R3, R8, R10

R103

R11, R12

R13, R40

R14

R15, R16, R44, R87,

R102

R15, R16, R44, R87,

R102

R18, R24, R26, R37,

R39, R42, R48, R58,

R61, R64, R65, R66,

R88, R90, R92

R19, R32

R2, R4, R9, R35

R20, R21

R22

R23

R25, R27, R43, R47,

R70

R28, R71

CSD18532KCS

STP12NM50

5.11k

5.11k

51.1

10

0

Open

35k

10.0k

0

2.43

15.0k

0.5

2.49k

1

150

NexFET, N-ch, 60V, 100A, 3.3milliohm

MOSFET, N-ch, 550-V, 12-A, 0.35-ohms

Resistor, Chip, 1/8 W, 1%


Resistor, Chip, ½ W, 1%


Resistor, Chip, 1/8 W




Resistor, Chip, ¼ W

Resistor, Chip, ¼ W, 1%

Resistor, Chip, ½ W, 1%





Size

0603

0603

0603

SOT23

SOT23

SOT23

SMA

SOT23

0603

0603

SMB

SMC

SOD123

DPAK

0.5 × 1.38 in

0.4 × 0.35 in

0.035-in Dia.

0.1 × 3 in

1.213 × 0.51

0.2 × 0.3 in

0.2 in

AWG 22

1206

1206

1210

0603

0603

Part Number

STD

STD

STD

MMBD914

BAT54S

MMBZ5245BLT1G

STPS130A

BAV70-V-GS08

LTST-C190CKT

LTST-C190GKT

MBRS1100T3G

SMCJ43A

MMSZ5222BT1G

STTH5R06B-TR

531002B02500G

ED120/2DS

923345-04-C

PEC03SAAN

182-009-213R171

PEC03DAAN

131-4244-00

8021

1.1 × 1.1 in

.863 × .453 in

4 × 40 mm

.1 in X2X8

SER2814H-222KL

PCH-45X-223_LT

87758-4016

PEC08DAAN

SOT23

SOT23

PWRPAK S0-8

FDV301N

MMBT3904LT1G

SI7866ADP-T1-E3

SC-70 (SOT-363) MMDT3946-7-F

TO-220V STP12NM50

TO-220

TO-220V

0805

0603

1210

0805

0805

0603

0603

0603

0805

1206

CSD18532KCS

STP12NM50

STD

STD

STD

STD

STD

STD

STD

STD

STD

STD

STD

STD

STD

STD

STD

MFR

STD

STD

STD

Belden

STM

STD

STD

STD

STD

STD

STD

STD

STD

STD

STD

Fairchild

Vishay

Diodes

ST

Zetex

Lite On

Lite On

On Semi

Diodes

On Semi

ST

Aavid

OST

3M

Sullins

Norcomp

Sullins

Tektronix

Coilcraft

Coilcraft

Molex

Sullins

Fairchild

On Semi

Vishay-Siliconix

Diodes

STM

TI

STD

STD

STD

STD

STD

22





www.ti.com

Bill of Materials

Table 4. Component List Based on the Schematics of

Figure 1

and

Figure 2

(1)

(continued)

1

1

1

1

2

1

1

1

1

1

2

3

1

1

1

3

3

2

1

4

4

1

2

3

1

1

3

4

2

3

1

1

QTY RefDes

0 R29, R72, R73

2 R30, R76

5

R31, R56, R59, R62,

R75

R33

R38

R41, R45, R101

R49, R50, R51, R52

R5, R34

R53, R104, R105

R54, R55

R57, R60, R63

R6, R7, R36, R46

R67, R68, R84, R85

R69

R74

R77

R78

R79, R82, R97

R80, R83, R98

R81, R86

R89

R91

R93, R100

R94, R95, R96

R99

S1

(2)

1

4

T1

Value

Open

0

3.32k

1.24k

16.2k

1.82k

499

4.99k

220

1.0k

549

1.62k

G12AP-RO

15

301

7.5

1.00k

49.9k

2.00k

2.05k

1.00k

549

100k

1.12k

100

0.003

1.2 mH

Description


Resistor, Chip, 1/10 W







Resistor, 1 W, 1%







Resistor, Chip, 1/16W, 1%







Resistor, Chip, 1/2W,1%



Switch, ON-NONE-ON

Transformer, Phase Shifted Full Bridge

Size

1206

0603

0603

0805

0603

1206

0603

0603

0603

0603

1206

0603

0603

1206

0805

1210

0603

0603

0603

0805

0603

0603

1210

1206

0603

0.28 × 0.18 in

35,5 × 39,1 mm

Part Number

STD

STD

STD

STD

STD

STD

STD

STD

STD

STD

STD

STD

G12AP-RO

STD

STD

STD

STD

STD

STD

STD

STD

STD

STD

STD

STD

STD

7840-08-0015

MFR

STD

STD

STD

U3, U4, U5, U8

U6

U7

U9

U11

T2

T3, T4

U1

U10

U2

80 mH

460 µH

TPS2411PW

LM60C

OPA345NA

UCC27424DGN

PWR050

(2)

SN75C3221

TPS715A33

PWR030

Transformer, Current Sense, 1:200

Transformer, Gate Drive, ±25%

IC, N+1 and Oring Power Rail Controller

IC, 2.7V Temperature Sensor

IC, R-R Op Amp, Single Supply,

0.57 × 0.77 in

0.685 × 0.95 in

TSSOP-14

SOT23

SOT23-5

IC, Dual Non-Inverting 4A High Speed Low-Side

MOSFET Driver w/ Enable

Module, 5W, Auxiliary Bias PS

HTSSOP

IC, RS-232 Transceivers with Auto Shutdown

IC LDO REG

1.2 × 2.2 in

SSOP-16

QFN-8

Control Card, UCD3138 control card, PCB assembly 3.4 × 1.8 in

CS4200V-01L

GA3550-BL

TPS2411PW

LM60CIM3/NOPB

OPA345NA/250

UCC27424DGN TI

PWR050

SN75C3221DBR

TI

TI

TPS715A33DRBT TI

UCD3138CC64EVM-030 TI

PWR050 is a bias board and the design documents are found in the UCD3138PSFBEVM-027 product folder on www.ti.com

.

STD

STD

STD

STD

STD

STD

STD

STD

STD

STD

STD

STD

STD

STD

STD

STD

STD

STD

STD

STD

STD

STD

NKK

Nova Magnetics

Inc

Coilcraft

Coilcraft

TI

TI

TI





23

Description of the Digital Phase-Shifted Full-Bridge Converter

12 Description of the Digital Phase-Shifted Full-Bridge Converter

www.ti.com

12.1 Block Diagram of the Phase-Shifted Full-Bridge Converter

Figure 22

shows the block diagram of the phase-shifted full-bridge converter used in the EVM. The signals used for control and for detection are defined in

Section 12.2

in connection with the UCD3138 pins.

T1

L1

Q10

+12 V

I_pri

PRI

CURRENT

T2

BUS+

QSYNC1,3

QSYNC2,4

R53

C2

ORING

CTL

RL

+VO

FAULT0 = ACFAIL_IN

FAULT1 = ACFAIL_OUT

FAULT2 = FAILURE

GPIO1 = ORING_CTRL

GPIO2 = ON / OFF

GPIO3 = P_GOOD

Vo1

QT1

L2

D1 QT2

T1

Current

Sensing

PGND

QB1

D2

QB2

+VO

Vref

EADC0

Duty for mode switching

CLA0

CPCC

<

DPWM0

DPWM1

ISEC

EADC1 CLA1

DPWM2

SYNCHRONOUS

GATE DRIVE

ISOLATED

GATE Transformer

I_pri

I_SHARE

+VO1

I_ pri temp

Vin_Scale

0.1x Vo

ISEC

EADC2

AD00

AD01

AD02

AD03

AD06

AD07

AD08

AD09

AD13

UART1

PCM

DPWM3

FAULT

UCD3138

CBC

ARM7 WD

OSC

RST

Memory

FAULT0

FAULT1

FAULT2

GPIO1

GPIO2

GPIO3

PMBus

UART0

Figure 22. Phase-Shifted Full-Bridge Converter Block Diagram

24





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12.2 UCD3138 Pin Definitions

The UCD3138 pins are defined according to

Figure 23 . The definitions shown in Figure 23

are for the pins used in the EVM to control a phase-shifted full-bridge converter. See

Figure 21

for how the signals on these pin signals are used.

Voltage

Feedback

EAP0

EAN0

Current

Feedback

EAP1

EAN1

DAC0

Front End 0

EADC

Soft Start Control

Filter 1 or 2 (Loop Nesting)

CPCC Module

Front End

1

Front End

2

Advanced Power Control

Mode Switching, Burst Mode, IDE,

Synchronous Rectification soft on & off

PID

Filter 0

PID

Filter 1

PID

Filter 2

Constant Power Constant

Current

Front End Averaging

Digital Comparators

Input Voltage Feed Forward

DPWM0

DPWM1

DPWM2

DPWM3

ADC12

ADC12 Control

Sequencing, Averaging,

Digital Compare, Dual

Sample and hold

PMBus

AD00

AD01

Internal Temperature

Sensor

ISHARE

+VO1

Ipri

TEMP

VIN_Scale

0.1x Vo

ISEC

V33D

V33DIO

VREG

DGND

V33A

AGND

AGND

AD02

AD03

AD06

AD07

AD08

AD09

AD13

Power and

1.8-V

Voltage

Regulator

AD02

AD13

AD02

AD03

AD04

AD13

AD06

AD07

Current Share

Analog, Average, Master/Slave

Analog

Comparators

A

B

E

F

G

C

D

Fault MUX &

Control

Cycle by Cycle

Current Limit

Digital

Comparators

Oscillator

ARM7TDMI-S

32 bit, 31.25 MHz

Memory

PFLASH 32 kB

DFLASH 2 kB

RAM 4 kB

ROM 4 kB

Power On Reset

Brown Out Detection

Timers

4

±

16 bit (PWM)

1

±

24 bit

Figure 23. UCD3138 Pin Definition in Phase-Shifted Full-Bridge Control

UART0

UART1

GPIO

Control

JTAG





25


12.3 EVM Hardware — Introduction

This section describes the EVM hardware functions.

www.ti.com

12.3.1

Power Stage

This EVM implements topology for a phase-shifted full-bridge DC-DC converter. The key waveforms generated by the UCD3138 to control the phased-shifted power stage are shown in

Figure 24

. See

Section 4

for the complete schematics. On the primary side, QT1, QB1, QT2, and QB2 are the power switches, L2 is a resonant inductor (often called shim inductor), and T1 is the main transformer. D9 and

D10 are clamping diodes. T2 is a current transformer for sensing primary-side current and is located on the high side. T5 is not used and is shorted by jumper J10.

The secondary side is configured as a central-tap synchronous rectifier comprised of an output choke

(L1), output capacitor (C4 and C62), and synchronous MOSFETS (QSYN1, QSYN2, QSYN3 and

QSYN4). Q6 and Q10 are oring FETS for hot swap. T3 and T4 are gate transformers to drive primary-side power MOSFETs and provide isolation boundary. Two gate drivers (U4 and U5) are used for driving the gate transformers. Two low-side drivers, U3 and U8, are used for driving the secondary-side synchronous

MOSFETs.

DPWM3A

(QB1)

DPWM3B

(QT1)

DPWM2A

(QT2)

DPWM2B

(QB2)

VTran s

DPWM1B

(QSYN1,3)

DPWM0B

(QSYN2,4)

IPRI

Figure 24. Driving Scheme of Phase-Shifted Full-Bridge Control

The following lists the DPWM configuration for the phase-shift full bridge converter:

DPWM3A to VGS_QB1

DPWM2A to VGS_QT2

DPWM1B to VGS_QSYN2 and QGS_QSYN4

DPWM3B to VGS_QT1

DPWM2B to VGS_QB2

DPWM0B to VGS_QSYN1 and QGS_QSYN3

26





www.ti.com


spacer

When both QB1 and QT2 turn on, the input voltage Vbus is applied to the power transformer and energy is transferred to the output. During this period, QSYN1 and QSYN3 are turned off and power is transferred through L1 to the output. The return current flows through QSYN2 and QSYN4, which are turned on, and then the current flows back to the secondary side of the main transformer. When QB2 and QT1 are both on, the bus voltage is applied to the power transformer in the opposite direction. In this case, QSYN2 and

QSYN4 are turned off and power is transferred through L1 to the output. The return current flows through

QSYN1 and QSYN3, which are turned on, and then flows back to the main transformer. When all four switches on the primary side are turned off, the secondary side works in a freewheeling mode, meaning all sync FETs are turned on and the inductor current flows through the switches. See

Section 15

for a list of references containing additional details about the phase-shift full-bridge converter.

Because the digital controller generating the six DPWMs in on the secondary side and four of the power switches are on the primary side, the converter requires an isolation component to cross the boundary.

Pulse transformers, T3 and T4, transmit the gate signal and drive the primary-side power MOSFETs.

These transformers are used because they are simple and low cost although they typically require more space than digital isolators. Two drives, U5 and U6, drive the gate-drive transformers from the secondary side. The leakage inductance of the gate transformer oscillates with other capacitors in the gate-drive circuit during dead time. If the leakage inductance oscillates with other capacitors, a glitch can occur. A negative voltage is provided by the components D20 and C36 for QT1. Other switches use the same circuit that generates negative current. The secondary-side switches do not require isolation. Two ICs, U3 and U8, directly drive these switches.

The dead time between all switches is important to achieve zero-voltage switching based on different operation conditions such as load current and input voltage.

For peak-current-mode control, slope compensation is important to stabilize the loop and avoid the nonperiodic ripple of the output voltage. The slope is generated either internally or externally. If the slope compensation is generated externally, DPWM0A and DPWM1A are used. In this case, install the jumpers between Pin1 to Pin2 and between Pin5 and Pin6 for proper operation. Install Q1, Q2, Q4, and Q8 to generate the slope.

External slope-compensation circuits require many external components. In default, internal slope compensation is used. The controller generates the slope and adds the slope on the filter output of the voltage loop. EAP2 requires a pullup resistor to provide over 100-mV DC offset voltage, which is important to stabilize the loop at the small duty.

12.3.2

Bias Power Supply

The bias supply is a flyback converter using the UCC28600 controller from TI. The bias is an independent daughter-card, the PWR050. The design files ( SLUR924 ) are located in the UCD3138PSFBEVM-027 product folder on www.ti.com

.

Figure 25

shows the schematic of the PWR050.

There is one 12-V output (PN3-PN4) on the primary side and one 12-V output (PN5-PN7) on the secondary side. The feedback signal is taken from the secondary 12-V output. The controller requires +3.3

V, which is derived from the secondary 12-V output through a LDO regulator (U2).





27


www.ti.com

12.3.3

Sensing Input Voltage on Secondary-Side

In

Figure 25

there is sample-and-hold circuit on the secondary side of the PWR050, which senses the primary-side voltage. When the Q2 switch turns on, D5 turns on. The voltage on the winding (6, 7) of the bias transformer T1 charges capacitor C9 to a voltage equal to VIN / N after the divider of R16 and R14, where N is the turns ratio of T1. When Q2 turns off, D5 turns off, and the voltage on C9 is held until the next switching period. The voltage on C9 is proportional to the input voltage. U4 is used to scale the sampled voltage to the application.

PIN3

R3

100

C1

100pF

R12

4.99

D5

PIN4

+

C7

330 µF

PIN1

-VIN/VAUX RETURN

+VIN

R48

150k

R5

150k

R13

3.01k

C2

10µF

PWRGND

R6

150k

R7

150k

+

C3

10uF

PIN2

PWRGND

-VIN

PWRGND

+

C6

47 uF

C21

100nF

C15

100nF

D3

3

T1

7

C11

10nF

4

1

6

8

GND

D2

VAUXSEC

+VSS

GND

R10

4.99

C8

150pF

2 5

R47

100

R45

165k

R4

499

R11

100k

GND

MMBD1204

D1

U1

UCC28600D

6 VDD

OVP

8 STATUS

1 SS

7

OUT

5

CS

3

C5

220pF

2 FB

GND

4

UCC28600D

PWRGND

R1

47.5k

D4

R2

10

MUR1100ERLG

Q2

FQD3N60

R56

1.5k

C12

220pF

R46

2.4

R43

4.99k

U2

C20

100pF

R52

12.1k

C13

220pF

4 1

R41

33.2k

3 2

U3

TL431AQDBZ

1

3

2

GND

R9

4.42k

GND

C18

100nF

GND

C19

10µF

R8

16.9k

C9

220pF

+

C4

330 µF

R16

20k

3

4

R14

1.37k

GND

+VSS

R15

3.01k

C10

100nF

U4

GND

R17

1k

1

GND

VAUX SECONDARY

12Vout

PIN5

R18

22.1

GND

PIN7

400-V monitor

400V = 1.5V

PIN6

Figure 25. PWR050 Bias Board Schematics

28





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12.3.4

Load Current Sensing

Figure 26

and

Figure 27

show how the load current is sensed and fed back to the UCD3138. A 1-m Ω sense-resistance value (R53 // R104 // R105) senses the load current. A differential amplifier circuit amplifies and filters this signal. The result is supplied to EADC1 and AD13. The sensed current is also used in constant-current and constant-power (CPCC) operation. The AD13 monitors the current. The

AD13 also has a mechanism for a fast latch-off over current and the means to implement either masterand-slave or average-mode current sharing.

Figure 26. Load-Current Sensing Connections

Figure 27. Load-Current-Sensing Conditioning Circuit





29


www.ti.com

12.3.5

Serial Port Interface

The schematic of the interface for the serial port (UART) is shown in

Figure 28

. The UART provides realtime debug and subsequently reduces code-development time. This serial port also monitors for fastchanging internal variables.

Figure 28. Serial Port Interface in the Converter

12.3.6

LED Indicators

Ref. Designator

D26

D2

D3

D5

Table 5. LED Status Lights

Silk Screen Text

12VP_ON

Function

This LED turns green when 12 V is present on the primary side.

FAILURE

P_GOOD

This LED turns red when a fault is detected.

This LED turns green when the output voltage is within the thresholds defined by PMBUS_CMD_POWER_GOOD_ON and

PMBUS_CMD_POWER_GOOD_OFF[1].

AC_P_FAIL_OUT This LED is not used.

30





Header Pin No.

P1-31

P1-32

P1-33

P1-34

P1-35

P1-36

P1-37

P1-38

P1-39

P1-21

P1-22

P1-23

P1-24

P1-25

P1-26

P1-27

P1-28

P1-29

P1-30

P1-11

P1-12

P1-13

P1-14

P1-15

P1-16

P1-17

P1-18

P1-19

P1-20

P1-1

P1-2

P1-3

P1-4

P1-5

P1-6

P1-7

P1-8

P1-9

P1-10

P1-40

P201

P2-02 www.ti.com


12.3.7

EVM Resource Allocation

The UCD3138PSFBEVM-027 is controlled by a control card, the UCD3138CC64EVM-030, through two

40-pin connectors, P1 and P2.

Table 6

lists the definitions of P1 and P2 on the UCD3138PSFBEVM-027 board.

Table 6. P1 and P2 Pin Assignment

GPIO29

GPIO30

GPIO31

GPIO32/FLT4A

GPIO33/ FLT4B

GPIO26

GPIO22

GPIO24

GPIO23

GPIO18/PWM1

GPIO19/PWM2

GPIO20

GPIO21

GPIO34

GPIO35

GPIO16/SCI_TX

GPIO17/SCI_RX

GPIO25

GPIO27

GPIO27

RESET*

DGND

DGND

VauxS

Not connected to

UCD3040

AGND

ADCREFin

UCD3138 Pin

Name

DPWM_0A

DPWM_0B

DPWM_1A

DPWM_1B

DPWM_2A

DPWM_2B

DPWM_3A

DPWM_3B

DGND

DGND

GPIO08

GPIO09/FLT1B

GPIO10

GPIO11/FLT2B

GPIO28

DPWM0A, slope generation

DPWM0B, controls the secondary-sync FET, QSYN1, 3.

DPWM1A, slope generation

DPWM1B, controls the secondary-sync FET, QSYN2, 4.

DPWM2A, controls the primary-side FET, QT2.

DPWM2B, controls the primary-side FET, QB2.

DPWM3A, controls the primary-side FET, QB1.

DPWM3B, controls the primary-side FET, QT1.

Digital ground (GND)


ON/OFF

GPIO_ORING_CTR

Failure

P_GOOD

Not used

Not used

Not used

Not used

I_FAULT

LATCH_ENABLE

Not used

Not used

Not used

Not used

AC_FAIL

ACFAILIN

Not used

Not used

Not used

Not used

SCI transmit

SCI receive

Not used

Not used

Not used

Not used



External 12-V DC supply

Not used

Analog ground (GND)

Not used

Usage Description




31


Header Pin No.

P2-32

P2-33

P2-34

P2-35

P2-36

P2-37

P2-38

P2-39

P2-40

P2-22

P2-23

P2-24

P2-25

P2-26

P2-27

P2-28

P2-29

P2-30

P2-31

P2-12

P2-13

P2-14

P2-15

P2-16

P2-17

P2-18

P2-19

P2-20

P2-21

P2-03

P2-04

P2-05

P2-06

P2-07

P2-08

P2-09

P2-10

P2-11


Table 6. P1 and P2 Pin Assignment (continued)

AD_14

EAN4

EAP4

EAN3

EAP3

EAN2

EAP2

EAN1

EAP1

AD_09

AGND

AD_10

AGND

AD_11

AGND

AD_12

AGND

AD_13

AGND

AD_04

AGND

AD_05

AGND

AD_06

AGND

AD_07

AGND

AD_08

AGND

UCD3138 Pin

Name

AGND

AD_00

AGND

AD_01

AGND

AD_02

AGND

AD_03

AGND

Usage Description

Analog ground (GND)

PMBus ADDR

Analog ground (GND)

PMBus ADDR

Analog ground (GND)

AD_02, output current sensing

Analog ground (GND)

AD_03, primary current sensing

Analog ground (GND)

AD_04, current-sharing bus sensing

Analog ground (GND)

AD_05, inside-oring FETs voltage sensing

Analog ground (GND)

AD_06, outside-oring FETs voltage sensing

Analog ground (GND)

AD_07, temperature sensing

Analog ground (GND)

AD_08, VINSCALED sensing

Analog ground (GND)

I_SHARE

Analog ground (GND)

Not used

Analog ground (GND)

Not used

Analog ground (GND)

Not used

Analog ground (GND)

Not used

Analog ground (GND)

Not used

Analog ground (GND)

I_PRI

Analog ground (GND)

Output voltage sensing, or I_PRI

Analog ground (GND)

Output current sensing

Analog ground GND2 (-RS)

Output voltage sensing (+RS) www.ti.com

32





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12.4 EVM Firmware — Introduction

The reference firmware that is provided with the EVM is intended to demonstrate basic phase-shifted fullbridge DC-DC converter functionality, as well as some basic PMBus communication and primary-tosecondary communication. The firmware is used as an initial platform for particular applications. This section provides a brief introduction to the firmware.

12.4.1

Firmware Infrastructure overview

The firmware includes one startup routine and three program threads. The startup routine initializes the controller setup for the targeted operation functions or status. Please contact TI for detailed initialization information.

As shown in

Figure 34 , the three program threads are (1) the fast-interrupt request (FIQ); (2) the timer-

interrupt request (IRQ); and (3) the background loop. These threads are described as:

1. Fast Interrupt (FIQ)

• Critical or time-sensitive tasks are within the FIQ. Functionally, FIQ events are the highest priority and are addressed as soon as possible.

2. Timer Interrupt (IRQ)

• The majority of the firmware tasks occur during the IRQ. IRQ events occur synchronously every

100 µs.

3. Background Loop

• Non time-sensitive tasks are implemented in the background loop. Background Loop items are addressed whenever FIQ and IRQ events are not handled.

FIQ

4 Switching

Cycle Timer

FIQ

Complete

4 Switching

Cycle Timer

100

Û

s

Timer

Background

Loop

IRQ

Complete

Figure 29. Firmware Structure Overview

FIQ

Complete

IRQ

12.4.2

Tasks Within FIQ

FIQ events have the highest priority and are addressed as soon as possible. The FIQ includes critical and time-sensitive tasks. The firmware included with the EVM includes two functions called by the FIQ:

• Constant Power and Constant Current

• Cycle-by-cycle current limit

The FIQ interrupt is called to respond every four switching cycles.





33


www.ti.com

12.4.3

Tasks Within IRQ and State Machine

Almost all firmware tasks occur during the IRQ. The exceptions are the serial interface and PMBus tasks, which occur in the Background Loop; and the overcurrent protection (OCP), which is handled by the FIQ.

The IRQ is called to respond every 100 µs.

At the heart of the IRQ function is the power-supply State Machine implemented with switch command.

Figure 30

shows the structure of the State Machine. At a higher level, this State Machine allows the digital controller to optimize the performance of the power supply based on the exact State Machine functions of the digital controller.

PS O N O N

Id le

P SO N a n d N o F a u lt s

F a u l t s C l e ar

R a m p u p

F a u lt s

F A U L T

V o lt m o d e

R a m p u p O v er

F a u l ts

Pe a k C u r r e n t M o d e

R am p U p D o n e

S Y N F E T _

R a m p _ u p

F a u l t s

R a m p u p O v er

R e g u la te d

Figure 30. State Machine

12.4.4

Tasks Within Background Loop

The background loop handles all PMBus communication as well as processing and transmitting data through the UART. The data flash is managed with a dual-bank approach. This provides redundancy in the event of a power interruption during the programming of data flash. Once new data-flash values have been written, a function called erase_task() initiates in the background loop to erase the old values. The erase_task() is called until all of the old DFLASH segments are erased. Erasing the data flash in segments allows the processor to handle other tasks instead of waiting for the entire data flash to be erased before completing other tasks.

12.4.5

System Normal Operation

The EVM is designed to operate in peak-current-mode control under normal operation conditions. The

EVM operates with output voltage in regulation across the load range. If the load power continues to increase beyond the rated value, then an overload condition occurs. In such a case, the system enters protection operation by entering CPCC mode. If load power still continues to increase, output shutdown is triggered.

34





www.ti.com


12.4.5.1

Peak-Current-Mode Control

Peak-current-mode control is used in this EVM. The primary-side peak current is used to create control, and is sensed through current transformer T2. The slope compensation is realized within the digitalcontroller internal setup which is re-programmable to adapt to required applications. External slope compensation is also used with component place-holders in place. Please contact TI for information on how to re-program the internal slope compensation and how to set up the external slope compensation.

12.4.5.2

Other Possible Control Modes

Voltage-Mode Control and Average Current-Mode Control are also possible. To change the EVM into these controls, both hardware and firmware require modifications. Please contact TI for more information on how to make these modifications.

12.4.6

System Operation in Protection

12.4.6.1

Faults and Warnings

The system is equipped with a variety of programmable fault and warning options.

Table 5

lists the LEDs used to indicate a fault.

Table 7

lists the basic faults and warnings available in the EVM along with the corresponding action required by these events. Each of these parameters is modified through the GUI.

Signal

VOUT

VIN

IOUT

IIN

SR (QSYN3)

Temperature

Table 7. Faults and Warnings

Type

Over

Under

Over

Under

Over

Over

Warning

Report

Report

Report

Report

Report

Report

Over Report

Fault Response

Report and latch off

Report




Cycle-by-cycle limiting






35


www.ti.com

Reporting a fault includes the appropriate setting of the PMBus alert line, status byte, and status word.

Faults and warnings are reset by toggling the unit off and then on. Alternatively, as long as the system does not latch off, the Clear Faults button clears any faults or warnings (see

Figure 31

). Faults and warnings are also cleared by toggling the control line the on-off switch.

Figure 31. Faults and Warnings

12.4.6.2

Cycle-By-Cycle Current Limit

Current transformer T2 senses the primary-side current.

Figure 32

shows the sensing circuit. This current is used for cycle-by-cycle current limit, peak-current-mode control, or flux balancing of the main transformer. The primary-peak current is limited within the primary MOSFET current ratings by the cycleby-cycle current limit. R31 and C17 are used as a low-pass filter before the current signal feeds to the

UCD3138. The current signal is sent into UCD3138 through AD06 to create cycle-by-cycle current-limit control. To prevent switching spikes from triggering the comparator, a blanking time is programmed.

Figure 32. Cycle-by-cycle Current-Limit Sensing Circuit

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12.4.6.3

Constant Power and Constant Current Operation

Both hardware and firmware in this EVM support CPCC operation.

Figure 33

illustrates the behavior of the output voltage and output current (V

OUT versus I

OUT

). The dashed lines represent an extended view.

The EVM is delivered already programmed with a constant-power threshold of a few watts over 360 W and a constant-current threshold of 33 A (typical). These limits are adjustable through the GUI and a new setting can be saved to data flash. The maximum hardware capability limits the current within 35 A. The dashed lines represent exceeding the constant power to a higher current, although the maximum current of this EVM is limited to 35 A.

Figure 34

shows the GUI default values of these controls.

In addition to setting the previously described thresholds, enabling or disabling the CPCC feature and configuring a fault timer is also possible. Whenever the State Machine detects CPCC operation a timer starts. If the timer reaches the time limit specified in

Figure 34 , the system latches off until the on

command toggles off and on again, or recycles the input power.

Figure 33. CCPCC Operation

Figure 34. CPCC Default Values Adjusted Through GUI





37


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12.4.6.4

Output Over Voltage

When the output voltage exceeds 15.6 V, Q7-B turns on then Q7-A turns on because the Q7-A base is low. OVP_LATCH is pulled low, which is detected by the controller. The output voltage is shut down and latched.

Figure 35

shows the circuit.

Figure 35. Redundant-Output Overvoltage Protection

12.4.6.5

Input Over Voltage

The input over voltage is detected based on the winding on the auxiliary power supply as described in

Section 12.3.3

. The detected signal is sent to AD08 to create a fault process.

12.4.6.6

Over Temperature

Over temperature includes UCD3138 internal-temperature sensing and external added-temperature sensing. A temperature-sensing element on U10, LM60C, determines the external overtemperature condition. The temperature signal feeds into the controller through AD07. U10 is located on the top-side of the board next to the QSYNC3 heat sink. At this location U10 senses the temperature of the secondaryside MOSFETs.

Figure 36. Temperature Detection Circuit

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12.5 Special Operation Modes


12.5.1

Light Load Operation

At light load, the burst operation enables when the switching duty cycle is small. The significant benefit of this operation is the reduction of power loss. The associated disadvantage is higher output voltage-ripple and larger output voltage-dip when the load has a sudden demand. But the higher ripple and the larger dip disadvantages are corrected by the convenience and flexibility of the digital control. For example, nonlinear control from digital control solves the large dip during load transient. The higher ripple is also reduced by narrowed duty cycle on and off-limit for burst operation control.

Figure 37

shows the burst operation timing diagram.

NOTE:

The burst operation mode is still in development for this EVM. Please contact TI for the latest development information.

Figure 37. Burst Operation Timing Diagram





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12.5.2

Current-Sharing Operation

The UCD3138 supports three major current-sharing techniques:

• Average current-sharing, or PWMbus current-sharing

• Master and slave current-sharing

• Droop-Mode Current-Sharing, or Analog bus current-sharing

This EVM uses average current-sharing. The average-current-sharing technique uses a share bus to balance and evenly distribute the current on each paralleled converter as shown in

Figure 38 . The share

bus is called ISHARE in this EVM design. Therfore, when making load current sharing, ISHARE from each board must be connected together. ISHARE connection is located on J2 terminal pin 3 and through R91 and C12 fed into AD02. The load current is connected to AD13 after a low-pass filter (R85 and C49) from

ISEC. The current-sharing module is integrated in the UCD3138, and the ISHARE bus is controlled properly by UCD3138 internal functions.

This current-sharing-operation feature is used for normal operation in steady state with average-currentsharing approach. In CPCC, the current sharing is inherently valid and does not rely on the averagecurrent-sharing approach. This feature is not available during start, burst operation, or cycle-by-cycle current limit.

Ishare Bus

Iout1

AD02

PS1

AD13

ISHARE1

ISHARE2

AD02

PS2

AD13

Iout2

Figure 38. Current-Sharing Operation

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12.5.3

Oring FETs Control

The oring control circuit is shown in

Figure 39

. Q6 and Q10 are oring FETs used for hot-swapping operation. Less power-conduction loss occurs when using oring MOSFETs instead of oring diodes. The oring MOSFETs are controlled by the oring-control IC U1, TPS2411. By sensing the voltage between the drain and source of the oring FETs, U1 quickly turns off the oring FETs to avoid reverse current drawn from the output voltage bus. Pull down the gate-drive signal to turn off oring FETs by pulling Pin5 high, which is controlled by the UCD3138. Through output voltage remote sensing, the voltage drop on the load wire is compensated to ensure the voltage at the load point is accurate. +RS and –RS are connected to

+VO and 12V_RETURN through the resistors, R55 and R54, respectively.

Figure 39. Oring Control





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12.6 Loop Compensation Using PID Control

Proportional, integral, and derivative (PID) control is usually used in the feedback-loop compensation in digitally-controlled power converters. This section describes several aspects of how to use PID control.

12.6.1

Transformation of Digital-PID Coefficients to Poles and Zeros in the s-Domain

PID control in the UCD3138 control-law algorithm (CLA) for control loop is formed in the z-domain using

Equation 1

.

G c

( )

=

K

P

+

K

I

1 + z

1

1

z

-

1

1 z

1

+

K

D

1

- a ´ z

-

1

(1)

Converting

Equation 1

to the s-domain equivalent using the bilinear transform results in two forms. One form is with two real zeros and one real pole as shown in

Equation 2

.

G cz

( )

=

K

0

æ

ç

è s w z1

+

1

öæ

÷ç

øè s

æ

ç s w p1 w z2

+ s

1

ö

ø

+

1

ö

÷

ø

(2)

K

0 is the gain of the frequency domain pole at the origin, and K

0 is also represented as the angular frequency when the integrator Bode-plot gain crosses over with 0 dB. K

0 is also used as a method for initially designing feedback-loop compensation (see reference 5 in

Section 15

for more details).

The second form is when the two zeros are presented with complex conjugates as shown in

Equation 3

.

G cz

( )

=

K

0

æ

ç s

2 w

2 r

+ s

æ

ç

Q s w p1 s

´ w r

+

1

ö

ø

+

1

ö

ø

(3)

Two complex conjugate zeros are expressed as, w z1, z2

= w r

(

± ´

2

-

1

) and j

= -

1

(4) w = w ´ w r z1 z2 (5)

Q

= w ´ w z1 z2 w + w z1 z2

(6)

The factor of Q is in the range of 0 to infinite. The two complex conjugate zeros become the two real zeros when Q is less than or equal to 0.5 (Q ≤ 0.5). Therefore,

Equation 2

is a unique form of

Equation 3 . In this

sense,

Equation 3

can be used in either case across the range of Q.

A low-pass filter usually exists in a control loop of its feedback path. The low-pass filter adds a pole to the loop as shown in

Equation 7

.

1

H (s)

=

K cs s

+

1 w pcs

(7)

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The close-loop transfer function is shown in

Equation 8 .

´

PID

(s)

=

+ ´

PID

´ where

• GM(s) is the control plant transfer function (8)

For example, GM(s) is the transfer function associated to the phase-shifted full-bridge power-modulator circuit.

The parameters are calculated with the assumption that the sensor-sampling cycle, T s

, is much smaller than the time constant in relation to the converter-voltage feedback-loop bandwidth, TLC. As a general rule, choose the sampling frequency as shown in

Equation 9

.

T s

≤ 0.05 × T

LC

(9)

When the above assumption is true, the delayed effect from the sampling is ignored and the parameters are determined after the position of the poles and zeros is known.

Table 8

summarizes the poles and zeros in a form relating the z-domain to the s-domain.

( p1

´ w z1

+ w p1

´ w z2

- w z1

´ w z2

)

K

P

=

K

0 w p1

´ w z1

´ w z2

(10)

K

I

=

K

0

´

T s

2

(11)

K

D

=

2 K

0

( p1

- w z1

) ( p1

- w z2

) w p1

´ w z1

´ w z2

(

T s

´ w p1

+ 2

)

(12) a =

2

-

T s

´ w p1

2

+

T s

´ w p1

(13)

System Name

Complex Zeros

(K

0

, ƒ z

, Q z

, ƒ p

)

Real Zeros

(K

0

, ƒ z1

, ƒ z2

, ƒ p

)

Device PID

(K p

, K i

, K d

, α)

Table 8. Poles and Zeros from PID Coefficients

1000

´

æ

ç

K p

+

K i

´

Transfer Functions

s

2

(

2

´ p ´

ƒ z

)

2

+ s

2

´ p ´

ƒ z

´

Q z s

2

´ p ´

K

0

´

æ

ç s

2

´ p ´

ƒ p

+

1

ö

÷

ø

+

1

æ

ç

è s

2

´ p ´

ƒ z1 s

2

´ p ´

K

0

+

1

ö æ

´

ø è

´

æ

ç s

2

´ p ´

ƒ z2 s

+

1

ö

÷

2

´ p ´

ƒ p

+

1

ö

÷

ø

-

1

-

1

-

1

+

K d

´

1

- a ´

2

-

8

´ z

-

1

ö

÷

´

2

sc

´

-

19

´

1

2

4

´

(

+

)





43

Evaluating the EVM with GUI

www.ti.com

12.6.2

Tuning PID Coefficients for Loop Compensation

When making fine-tuned adjustments to the feedback control loop, knowing how each PID parameter affects the control loop characteristics without using the complicated equations in

Table 8

is beneficial.

Use

Table 9

and

Figure 40

as a quick reference for tuning PID coefficients.

Control Parameters

K p

K i

K d

α

T s

= 1 / ƒ s

Table 9. Tuning PID Coefficients

Impact on Bode Plot

Increasing K p pushes up the minimum gain between the two zeros, moving the two zeros apart.

Increasing K i pushes up the integration curve at low frequencies, provides a higher low-frequency gain, and moves the first zero to the right.

Increasing K d shifts the second zero left with no impact on the second pole.

Increasing α shifts the second pole and the second zero to the right.

Increasing the sampling frequency ƒ s shifts the whole Bode plot to the right.

Increasing fs causes the whole Bode plots to shift to right

Pole 1

Pole 2

K

I

K

D

K

P

Zero 1

Zero 2

Frequency

Figure 40. Tuning PID Parameters

13 Evaluating the EVM with GUI

The collective graphical user interface (GUI) is called TI's Fusion Digital Power Designer (FDPD). The GUI serves as the interface for several families of TI's digital-control ICs including the UCD31xx family, (such as UCD3138). The GUI is divided into two main categories, Designer GUI and Device GUI. Each

UCD31xx EVM relates to a particular Designer GUI allowing users to re-tune and re-configure a particular

EVM with existing hardware and firmware. Device GUI relates to the accessing of internal registers and memories of a particular device.

The UCD3138PSFBEVM-027 is used with the UCD3138CC64EVM-030 control card where the UCD3138 device is placed. The firmware for control is loaded onto UCD3138CC64EVM-030 board through the

Device GUI. The user’s guide, Using the UCD3138CC64EVM-030 ( SLUU886 ), describes the GUI installation. The Designer GUI is installed at the same time as installing the Device GUI.

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13.1 Graphical User Interface (GUI)

As previously mentioned, there are two types of GUI: Device GUI and Designer GUI. The Device GUI is categorized as low-level GUI. From the Device GUI, device registers are accessed if the device is in ROM mode and the PMBus communication is established. This GUI is used to download the code when the device is blank during the initial programming. Also, at the flash mode, a designer can send PMBus commands to read or write the data. The Designer GUI is an interface between a host and a user. It supports some of the PMBus commands to configure, monitor, and design the loop compensator contained in the UCD3138 digital controller.

13.1.1

Hardware Setup

Figure 41. Test Setup

In

Section 5.2

,

Figure 5

and

Figure 6

show a basic setup for a power stage test with the EVM. To evaluate the EVM with GUI, the control card must first connect to a GPIO-to-USB adapter card, HPA172, then to a host computer. The following lists the steps for an evaluation:

1. Connect the input voltage source to the input connectors shown in

Figure 5 . Use 14 AWG wire or

equivalent.

2. Connect the output load to the board. Use a 14-AWG wire or equivalent.

3. Plug the control card UCD3138CC64EVM-030 (PWR030) into UCD3138PSFBEVM-027 with the orientation in

Figure 5

and

Figure 6 .

4. Confirm that the control card does not have a jumper on J2, and install a jumper on J6.

5. Connect the USB-to-GPIO (HPA172) adaptor to the control card as shown in

Figure 41

, and connect the other end of USB-to-GPIO adapter to the host computer

6. Move the ON/OFF control switch, S1, on the phase-shifted full-bridge board, to the OFF position. See

Figure 5

to locate S1 on the phase-shifted full-bridge board.

7. Configure the load to draw 1 A.

8. Apply 380 V to the input with a 2-A current limit set on the input source.





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9. Launch the Fusion Digital Power Designer GUI. See

Section 13.1.2

for instructions on how to install the GUI.

10. Turn on the board output by switching S1 to the ON position

13.1.2

GUI Installation

Download the GUI software from www.ti.com

. Before the GUI is executed, install the software on the host

PC. More details about the TI GUI, FDPD, can be found in the user’s guide or manual. Please contact TI for the FDPD document. The GUI contains manuals for use with the UCD3138. To find the manuals, use the following sequence:

Help > Documentation and Help Center > UCD3138

Copy over the TI Fusion Digital Power Designer zipped file onto the host computer and unzip the file (TI-

Fusion-Digital-Power-Designer-xx.zip) to open the installer file, TI-Fusion-Digital-Power-Designer-xxx.exe.

The xxx in the file name refers to the GUI release version.

Double click the executable installer file and follow the instructions to complete installation. In general, accept all the installation defaults. In order to have all of the GUI functions available, check all the boxes under Select Additional Tasks as shown in

Figure 42 .

Figure 42. GUI Installation

After the installation, a quick launch button appears next to the start menu in the taskbar section containing shortcuts to commonly-used applications.

Figure 43

shows the TI FDPD icon after the installation. Other icons, such as UCD3K Device GUI, are displayed on the desktop. For more information on the GUI installation, see the UCD3138CC64EVM-030 user’s guide ( SLUU886 ).

Figure 43. GUI Shortcut Location

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13.1.3

USB-to-GPIO Adaptor Connection


CAUTION

Turn off the DC power source before connecting the USB-to-GPIO adaptor to avoid electrical shock.

Connect one end of the ribbon cable to the module, and connect the other end to the USB-to-GPIO

(HPA172) interface adapter. Connect the mini connector of the USB cable to the USB interface adapter.

Then connect the other end to the USB port on the host computer, as shown in

Figure 41 .

13.1.4

Launch the Designer GUI

Click the quick-launch shortcut icon located in the taskbar next to the start menu. When launched, the GUI searches for a device attached to the PMBus. If the attached device is found and communication between the GUI and device is successful, a similar-looking screen as shown in

Figure 44

is seen. The following sections describes how to evaluate the module using the GUI.



Figure 44. Designer GUI Overview



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13.1.5

Designer GUI Overview

The Designer GUI has four tabs on the left side of the workspace, as shown in

Figure 44 : Configure,

Design, Monitor, and Status. After launching the GUI, the default tab is the Monitor tab. To open one of the three tabs, simply click on the desired tab.

Each tab of the EVM GUI has a different role. Configure configures the EVM settings through PMBus command. Design creates tuning control-loop parameters. Monitor monitors the board operation. Status shows faults and warnings that may occur.

13.2 Operation Monitoring

When the designer GUI launches, the Monitor tab is presented by default as shown in

Figure 44

. This tab provides a quick overview of operation status with some changeable settings. This tab also provides an oscilloscope-type plot view in real-time operation. The number of scope windows is adjusted by checking or un-checking the square boxes in the upper-left of the Monitor tab. Click on a box to show or hide the selected scope-plot windows.

Figure 45. Designer GUI Status

13.3 Operation Status

Click the Status tab below the Monitor tab (see

Figure 44 ) to view the EVM operation status shown as in

Figure 45 . All grayed entries are candidates that can be implemented. Those candidates in black

represent current-operation status which indicate potential operation issues with either warning or fault indications. If a fault occurred, the corresponding entry is highlighted in red. Warnings, although not considered faults, remind the user that those entries could require attention.

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13.4 Configuring EVM

The Configure tab allows the user to conveniently adjust the EVM feature setup without directly accessing the firmware. This tab also navigates the user through the various features of the converter within the GUI.

Figure 46. GUI Supported PMBus Commands

13.4.1

GUI Supported PMBus Commands

Figure 47

shows the various GUI-based PMBus commands supported by the current version of the firmware. Use the built-in Isolated Bit mask generator to easily add additional standard commands. This tool generates a coded index that the GUI reads from the device to determine which PMBus commands are supported. To add a standard command, modify the bit mask and the GUI automatically displays the new command. For additional details on using this tool, please contact TI.





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13.4.2

Configuring the EVM With GUI

In the Configure tab, changing the configuration is simple. For example, to configure CPCC, access the

CPCC control by clicking the drop-down arrow next to the Value/Edit box on the CPCC[MFR 36] line as shown in

Figure 47 . As previously mentioned, the maximum current is 35 A and the maximum power is

360 W. Please contact TI if any uncertainty exists that must be resolved. The CPCC feature is disabled by default.

Figure 47. Configure CPCC

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Firmware Development for Phase-Shifted Full-Bridge Power Converter

13.5 Tuning the Control Loop Using GUI Design

The GUI is equipped with 3 different ways to program the UCD3138 digital control-loop compensator.

Table 10

lists the three options, (a) complex zeros using K

0

, f z

, Q z

, and f p and f p

; (c) device PID using K p

, K i

, K d

, and α.

; (b) real zeros using K

0

, f z1

, f z2

,

In option (c), the compensator is described by device PID. In this context, K p

, K i

, K d and α are the raw register values used to configure the positions of the poles and zeros of the compensator. SC is a gain scaling term. Although SC is normally set to zero, it provides additional gain for situations where the power-stage gain is low. PRD is used to configure the minimum operating period, and KCOMP is used to configure the maximum operating period. In the context of the compensator they are gain terms modifing the overall transfer function by a fixed value. Knowing the proper way to configure PRD and KCOMP varies based on the control topology implemented is important.

System Name

Complex zeros

(K

0

, ƒ z

, Q z

, ƒ p

)

Real zeros

(K

0

, ƒ z1

, ƒ z2

, ƒ p

)

Device PID

(K p

, K i

, Kd, α)

Table 10. Programming Digital Control Loop

1000

´

æ

ç

K p

+

K i

´

Transfer Functions

s

2

(

2

´ p ´

ƒ z

)

2

+ s

2

´ p ´

ƒ z

´

Q z s

2

´ p ´

K

0

´

æ

ç s

2

´ p ´

ƒ p

+

1

ö

÷

ø

+

1

æ

ç

è

2 s

´ p ´

ƒ s z1

2

´ p ´

K

0

+

1

ö æ

´

ø è

´

ç

è

æ

ç

2

2 s

´ p ´

ƒ z2 s

´ p ´

ƒ p

+

1

ö

÷

÷

ø

+

1

ö

÷

ø

-

1

-

1

-

1

+

K d

´

1

- a ´

2

-

8

´ z

-

1

ö

÷

´

2

sc

´

-

19

´

1

2

4

´

(

+

)

14 Firmware Development for Phase-Shifted Full-Bridge Power Converter

Please contact TI for additional information regarding the UCD3138 firmware development for a digital phase-shifted full-bridge converter control.

15 References

1. UCD3138 Datamanual, Highly Integrated Digital Controller for Isolated Power ( SLUSAP2 )

2. UCD3138CC64EVM-030 Evaluation Module and User’s Guide, Programmable Digital Power Controller

Control Card Evaluation Module ( SLUU886 )

3. Reference Guide, UCD3138 Digital Power Peripherals Programmer’s Manual ( SLUU995 )

4. Reference Guide, UCD3138 Monitoring and Communications Programmer’s Manual ( SLUU996 )

5. Reference Guide, UCD3138 ARM and Digital System Programmer’s Manual ( SLUU994 )

6. User's Guide, UCD3138 Isolated Power Fusion GUI, (please contact TI)





51

EVALUATION BOARD/KIT/MODULE (EVM) ADDITIONAL TERMS

Texas Instruments (TI) provides the enclosed Evaluation Board/Kit/Module (EVM) under the following conditions:

The user assumes all responsibility and liability for proper and safe handling of the goods. Further, the user indemnifies TI from all claims arising from the handling or use of the goods.

Should this evaluation board/kit not meet the specifications indicated in the User’s Guide, the board/kit may be returned within 30 days from the date of delivery for a full refund. THE FOREGOING LIMITED WARRANTY IS THE EXCLUSIVE WARRANTY MADE BY SELLER TO

BUYER AND IS IN LIEU OF ALL OTHER WARRANTIES, EXPRESSED, IMPLIED, OR STATUTORY, INCLUDING ANY WARRANTY OF

MERCHANTABILITY OR FITNESS FOR ANY PARTICULAR PURPOSE. EXCEPT TO THE EXTENT OF THE INDEMNITY SET FORTH

ABOVE, NEITHER PARTY SHALL BE LIABLE TO THE OTHER FOR ANY INDIRECT, SPECIAL, INCIDENTAL, OR CONSEQUENTIAL

DAMAGES.

Please read the User's Guide and, specifically, the Warnings and Restrictions notice in the User's Guide prior to handling the product. This notice contains important safety information about temperatures and voltages. For additional information on TI's environmental and/or safety programs, please visit www.ti.com/esh or contact TI.

No license is granted under any patent right or other intellectual property right of TI covering or relating to any machine, process, or combination in which such TI products or services might be or are used. TI currently deals with a variety of customers for products, and therefore our arrangement with the user is not exclusive. TI assumes no liability for applications assistance, customer product design, software performance, or infringement of patents or services described herein.

REGULATORY COMPLIANCE INFORMATION

As noted in the EVM User’s Guide and/or EVM itself, this EVM and/or accompanying hardware may or may not be subject to the Federal

Communications Commission (FCC) and Industry Canada (IC) rules.

For EVMs not subject to the above rules, this evaluation board/kit/module is intended for use for ENGINEERING DEVELOPMENT,

DEMONSTRATION OR EVALUATION PURPOSES ONLY and is not considered by TI to be a finished end product fit for general consumer use. It generates, uses, and can radiate radio frequency energy and has not been tested for compliance with the limits of computing devices pursuant to part 15 of FCC or ICES-003 rules, which are designed to provide reasonable protection against radio frequency interference. Operation of the equipment may cause interference with radio communications, in which case the user at his own expense will be required to take whatever measures may be required to correct this interference.

General Statement for EVMs including a radio

User Power/Frequency Use Obligations: This radio is intended for development/professional use only in legally allocated frequency and power limits. Any use of radio frequencies and/or power availability of this EVM and its development application(s) must comply with local laws governing radio spectrum allocation and power limits for this evaluation module. It is the user’s sole responsibility to only operate this radio in legally acceptable frequency space and within legally mandated power limitations. Any exceptions to this are strictly prohibited and unauthorized by Texas Instruments unless user has obtained appropriate experimental/development licenses from local regulatory authorities, which is responsibility of user including its acceptable authorization.

For EVMs annotated as FCC – FEDERAL COMMUNICATIONS COMMISSION Part 15 Compliant

Caution

This device complies with part 15 of the FCC Rules. Operation is subject to the following two conditions: (1) This device may not cause harmful interference, and (2) this device must accept any interference received, including interference that may cause undesired operation.

Changes or modifications not expressly approved by the party responsible for compliance could void the user's authority to operate the equipment.

FCC Interference Statement for Class A EVM devices

This equipment has been tested and found to comply with the limits for a Class A digital device, pursuant to part 15 of the FCC Rules.

These limits are designed to provide reasonable protection against harmful interference when the equipment is operated in a commercial environment. This equipment generates, uses, and can radiate radio frequency energy and, if not installed and used in accordance with the instruction manual, may cause harmful interference to radio communications. Operation of this equipment in a residential area is likely to cause harmful interference in which case the user will be required to correct the interference at his own expense.

FCC Interference Statement for Class B EVM devices

This equipment has been tested and found to comply with the limits for a Class B digital device, pursuant to part 15 of the FCC Rules.

These limits are designed to provide reasonable protection against harmful interference in a residential installation. This equipment generates, uses and can radiate radio frequency energy and, if not installed and used in accordance with the instructions, may cause harmful interference to radio communications. However, there is no guarantee that interference will not occur in a particular installation. If this equipment does cause harmful interference to radio or television reception, which can be determined by turning the equipment off and on, the user is encouraged to try to correct the interference by one or more of the following measures:

• Reorient or relocate the receiving antenna.

• Increase the separation between the equipment and receiver.

• Connect the equipment into an outlet on a circuit different from that to which the receiver is connected.

• Consult the dealer or an experienced radio/TV technician for help.

For EVMs annotated as IC – INDUSTRY CANADA Compliant

This Class A or B digital apparatus complies with Canadian ICES-003.

Changes or modifications not expressly approved by the party responsible for compliance could void the user’s authority to operate the equipment.

Concerning EVMs including radio transmitters

This device complies with Industry Canada licence-exempt RSS standard(s). Operation is subject to the following two conditions: (1) this device may not cause interference, and (2) this device must accept any interference, including interference that may cause undesired operation of the device.

Concerning EVMs including detachable antennas

Under Industry Canada regulations, this radio transmitter may only operate using an antenna of a type and maximum (or lesser) gain approved for the transmitter by Industry Canada. To reduce potential radio interference to other users, the antenna type and its gain should be so chosen that the equivalent isotropically radiated power (e.i.r.p.) is not more than that necessary for successful communication.

This radio transmitter has been approved by Industry Canada to operate with the antenna types listed in the user guide with the maximum permissible gain and required antenna impedance for each antenna type indicated. Antenna types not included in this list, having a gain greater than the maximum gain indicated for that type, are strictly prohibited for use with this device.

Cet appareil numérique de la classe A ou B est conforme à la norme NMB-003 du Canada.

Les changements ou les modifications pas expressément approuvés par la partie responsable de la conformité ont pu vider l’autorité de l'utilisateur pour actionner l'équipement.

Concernant les EVMs avec appareils radio

Le présent appareil est conforme aux CNR d'Industrie Canada applicables aux appareils radio exempts de licence. L'exploitation est autorisée aux deux conditions suivantes : (1) l'appareil ne doit pas produire de brouillage, et (2) l'utilisateur de l'appareil doit accepter tout brouillage radioélectrique subi, même si le brouillage est susceptible d'en compromettre le fonctionnement.

Concernant les EVMs avec antennes détachables

Conformément à la réglementation d'Industrie Canada, le présent émetteur radio peut fonctionner avec une antenne d'un type et d'un gain maximal (ou inférieur) approuvé pour l'émetteur par Industrie Canada. Dans le but de réduire les risques de brouillage radioélectrique à l'intention des autres utilisateurs, il faut choisir le type d'antenne et son gain de sorte que la puissance isotrope rayonnée équivalente

(p.i.r.e.) ne dépasse pas l'intensité nécessaire à l'établissement d'une communication satisfaisante.

Le présent émetteur radio a été approuvé par Industrie Canada pour fonctionner avec les types d'antenne énumérés dans le manuel d’usage et ayant un gain admissible maximal et l'impédance requise pour chaque type d'antenne. Les types d'antenne non inclus dans cette liste, ou dont le gain est supérieur au gain maximal indiqué, sont strictement interdits pour l'exploitation de l'émetteur.

SPACER

SPACER

SPACER

SPACER

SPACER

SPACER

SPACER

SPACER

SPACER

SPACER

SPACER

SPACER

SPACER

SPACER

SPACER

SPACER

SPACER

SPACER

SPACER

SPACER

SPACER

SPACER

SPACER

SPACER

SPACER

【

Important Notice for Users of EVMs for RF Products in Japan

】

This development kit is NOT certified as Confirming to Technical Regulations of Radio Law of Japan

If you use this product in Japan, you are required by Radio Law of Japan to follow the instructions below with respect to this product:

1.

Use this product in a shielded room or any other test facility as defined in the notification #173 issued by Ministry of Internal Affairs and

Communications on March 28, 2006, based on Sub-section 1.1 of Article 6 of the Ministry’s Rule for Enforcement of Radio Law of

Japan,

2.

Use this product only after you obtained the license of Test Radio Station as provided in Radio Law of Japan with respect to this product, or

3.

Use of this product only after you obtained the Technical Regulations Conformity Certification as provided in Radio Law of Japan with respect to this product. Also, please do not transfer this product, unless you give the same notice above to the transferee. Please note that if you could not follow the instructions above, you will be subject to penalties of Radio Law of Japan.

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【無線電波を送信する製品の開発キットをお使いになる際の注意事項】

本開発キットは技術基準適合証明を受けておりません。

本製品のご使用に際しては、電波法遵守のため、以下のいずれかの措置を取っていただく必要がありますのでご注意ください。

1.

電波法施行規則第 6 条第 1 項第 1 号に基づく平成 18 年 3 月 28 日総務省告示第 173 号で定められた電波暗室等の試験設備でご使用いただく。

2.

実験局の免許を取得後ご使用いただく。

3.

技術基準適合証明を取得後ご使用いただく。

なお、本製品は、上記の「ご使用にあたっての注意」を譲渡先、移転先に通知しない限り、譲渡、移転できないものとします。

　　　上記を遵守頂けない場合は、電波法の罰則が適用される可能性があることをご留意ください。

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EVALUATION BOARD/KIT/MODULE (EVM)

WARNINGS, RESTRICTIONS AND DISCLAIMERS

For Feasibility Evaluation Only, in Laboratory/Development Environments. Unless otherwise indicated, this EVM is not a finished electrical equipment and not intended for consumer use. It is intended solely for use for preliminary feasibility evaluation in laboratory/development environments by technically qualified electronics experts who are familiar with the dangers and application risks associated with handling electrical mechanical components, systems and subsystems. It should not be used as all or part of a finished end product.

Your Sole Responsibility and Risk. You acknowledge, represent and agree that:

1.

You have unique knowledge concerning Federal, State and local regulatory requirements (including but not limited to Food and Drug

Administration regulations, if applicable) which relate to your products and which relate to your use (and/or that of your employees, affiliates, contractors or designees) of the EVM for evaluation, testing and other purposes.

2.

You have full and exclusive responsibility to assure the safety and compliance of your products with all such laws and other applicable regulatory requirements, and also to assure the safety of any activities to be conducted by you and/or your employees, affiliates, contractors or designees, using the EVM. Further, you are responsible to assure that any interfaces (electronic and/or mechanical) between the EVM and any human body are designed with suitable isolation and means to safely limit accessible leakage currents to minimize the risk of electrical shock hazard.

3.

Since the EVM is not a completed product, it may not meet all applicable regulatory and safety compliance standards (such as UL,

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4.

You will take care of proper disposal and recycling of the EVM’s electronic components and packing materials.

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UCD3138PSFBEVM-027

User's Guide Using the UCD3138PSFBEVM-027 Literature Number: SLUUAK4 August 2013

User's Guide

User's Guide

1 Introduction

High voltages are present on this evaluation module during operation and for a a time period after power off. This module should only be tested by skilled personnel in a controlled laboratory environment.

An isolated DC voltage source meeting IEC61010 reinforced insulation standards is recommended for evaluating this EVM.

High temperature exceeding 60°C may be found during EVM operation and for a time period after power off.

The purpose of this EVM is to facilitate the evaluation of digital control in a phase-shifted full-bridge DC-DC converter using the

UCD3138, and cannot be tested and treated as a final product.

Extreme caution should be taken to eliminate the possibility of

electric shock and heat burn. Please refer to the page Evaluation

Module Electrical Safety Guideline after the cover page for your

safety concerns and precautions.

Read and understand this user’s guide thoroughly before starting any physical evaluation.

2 Description

2.1

Typical Applications

2.2

Features

3 Performance Specifications

4 Schematics

5 Test Setup

5.1

Test Equipment

5.2

Recommended Test Setup

6 Test Points

7 Terminals

8 Test Procedure

8.1

Efficiency Measurement Procedure

Danger of electrical shock!

High voltage present during measurement!

8.2

Equipment Shutdown Procedure

9 Performance Data and Typical Characteristics Curves

9.1

Efficiency

9.2

Load Regulation

9.3

Switching Waveforms

9.4

Output Voltage Ripple

9.5

Output Turnon

9.6

Bode Plots

10 EVM Assembly Drawing and PCB layout

11 Bill of Materials

12 Description of the Digital Phase-Shifted Full-Bridge Converter

12.1 Block Diagram of the Phase-Shifted Full-Bridge Converter

12.2 UCD3138 Pin Definitions

12.3 EVM Hardware — Introduction

12.4 EVM Firmware — Introduction

12.5 Special Operation Modes

12.6 Loop Compensation Using PID Control

Increasing fs causes the whole Bode plots to shift to right

Pole 1

Pole 2

K

K

K

Zero 1

Zero 2

Frequency

13 Evaluating the EVM with GUI

13.1 Graphical User Interface (GUI)

13.2 Operation Monitoring

13.3 Operation Status

13.4 Configuring EVM

13.5 Tuning the Control Loop Using GUI Design

14 Firmware Development for Phase-Shifted Full-Bridge Power Converter

15 References

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