Philips 42PF9966/98 Repair manual

Colour Television
Chassis
LC 4.7, FM 242 (FTV2.1), FTP 1.1, FTP 2.2 X
Supplement SDI PDP Repair Manual
Contents
Page
1
2
3
4
5
6
7
8
9
10
2
6
8
9
16
27
33
34
44
45
Technical Specifications
Safety Instructions, Warnings and Notes
Directions for Use
Mechanical Instructions
Diagnostic Software
Block Diagrams
Circuit Diagrams and PWB Layouts
Alignments
Circuit Descriptions
Spare Parts List
©
Copyright 2004 Philips Consumer Electronics B.V. Eindhoven, The Netherlands.
All rights reserved. No part of this publication may be reproduced, stored in a
retrieval system or transmitted, in any form or by any means, electronic,
mechanical, photocopying, or otherwise without the prior permission of Philips.
Published by MW
Service PaCE
Printed in the Netherlands
Subject to modification
EN 3122 785 14990
EN 2
1.
S/SD/HD 3.1 PDP
Technical Specifications
1. Technical Specifications
1.1
Model / Chassis overview
42" SDv3
PDP Type
Model Name
H x V Pixel
Chassis
37”SDv4
S37SD-YD02 (*)
S37SD-YB01
852 x 480
LC4.7
42”SDv2
S42SD-YD06 (*)
S42SD-YB04
852 x 480
FM242
(FTV2.1)
FTP1.1
42”SDv3
S42SD-YD05 (*)
S42SD-YB03
852 x 480
LC4.7
FTP2.2x
42”HDv3
S42AX-XD03 (*)
S42AX-XB01
1024 x 768
FTP2.2U
50HDv3
S50HW-XD03 (*)
S50HW-XB02
1366 x 768
FTP2.2E
External View
M3 = X Board + Y Board + Logic Board + PSU + SUB PSU
Serial number label
Model label
(*) are Model names with PSU, but only PDP model without
PSU will be delivered as spare part
42" SDv2
Figure 1-2
External View
M3 = X Board + Y Board + Logic Board + PSU + SUB PSU
Serial number
Model label
Points of Screw Mount
Voltage label
Figure 1-3
Figure 1-1
Voltage label
Technical Specifications
42"HDv3
S/SD/HD 3.1 PDP
1.
EN 3
Points of Screw Mount
External View
M3 = X Board + Y Board + Logic Board + PSU + SUB PSU
Serial number label
Voltage label
Panel model label
Figure 1-7
50" HDv3
External View
M3 = X Board + Y Board + Logic Board + PSU + SUB PSU
Voltage label
Serial Number
Figure 1-4
Points of Screw Mount
Figure 1-8
Points of Screw Mount
Figure 1-5
37" SDv4
External View
M3 = X Board + Y Board + Logic Board + PSU + SUB PSU ‘
Serial number label
Voltage label
Panel module label
Figure 1-9
Figure 1-6
Panel module label
EN 4
1.2
1.
S/SD/HD 3.1 PDP
Technical Specifications
Serial Number
2 6 1 4 0 8 07 0 8 6 5
Serial No : 0001~9999
Date : 01~31
Month : 01~12
Year : 00(2000)
~99(2099)
Line No : 1 ~ 9
(0:Pilot Line)
Type : 02~48 (ex.50HDv3:26)
(Step of even)
Figure 1-10
1.3
Specifications
No
Item
Specification 37” SDV4
Specification 42” SDV2 (ypo6)
1
Pixel
852 (H) x 480 (V) pixels (1 pixel = 1 R,G,B cells)
852 (H) x 480 (V) pixels (1 pixel = 1 R,G,B cells)
2
Number of Cells
2556 (H) x 480 (V)
2556 (H) x 480 (V)
3
Pixel Pitch
0.960 (H) mm x 0.960 (V) mm
1.095 (H) mm x 1.110 (V) mm
4
Cell Pitch
5
Display size
R
0.320 (H) mm x 0.960 (V) mm
R
0.324 (H) mm x 1.110 (V) mm
G
0.320 (H) mm x 0.960 (V) mm
G
0.365 (H) mm x 1.110 (V) mm
B
0.320 (H) mm x 0.960 (V) mm
B
0.406 (H) mm x 1.110 (V) mm
Horizontal 817.92mm x Vertical 460.80mm[ 32.30 inch 932.940 (H) mm x 532.800(V) mm[ 36.73 inch x 20.98
x 18.14 inch ]
inch ]
6
Screen size
Diagonal 37" Color Plasma Display Module
7
Screen aspect
16 : 9
16 : 9
8
Display color
16.77 million colors
16.77 million colors
9
Viewing angle
10
Dimensions
11
Weight
Module 1
About 15.5 kg
Module 1
About 16.6 kg
12
Broadcasting receptionVertical frequencyandVideo/Logic Interface
PL42SD003C
60Hz/ 50Hz, LVDS
PL42SD003C
60Hz/ 50Hz, LVDS
Over 160×(Angle with 50% and greater brightness per- Over 160×(Angle with 50% and greater brightness perpendicular to PDP module)
pendicular to PDP module)
982 (W) x 582 (H) x 52.9 (D) mm
No
Item
Specification 42” SDV3
1
Pixel
852 (H) x 480 (V) pixels (1 pixel = 1 R,G,B cells)
2
Number of Cells
2556 (H) x 480 (V)
3
Pixel Pitch
1.095 (H) mm x 1.110 (V) mm
4
Cell Pitch
R
0.365 (H) mm x 1.110 (V) mm
G
0.365 (H) mm x 1.110 (V) mm
B
0.365 (H) mm x 1.110 (V) mm
Display size
932.940 (H) mm x 532.800(V) mm[ 36.73 inch x 20.98
inch ]
6
Screen size
Diagonal 42" Color Plasma Display Module
7
Screen aspect
16 : 9
8
Display color
16.77 million colors
9
Viewing angle
Over 160×(Angle with 50% and greater brightness perpendicular to PDP module)
10
Dimensions
11
Weight
Module 1
About 16.6 kg
12
Broadcasting receptionVertical frequencyandVideo/Logic Interface
PL42SD003C
60Hz/ 50Hz, LVDS
5
Diagonal 42" Color Plasma Display Module
982 (W) x 582 (H) x 52.9 (D) mm
982 (W) x 582 (H) x 52.9 (D) mm
Technical Specifications
No
Item
S/SD/HD 3.1 PDP
Specification 42” HDV3
1.
Specification 50” HDV3
Horizontal 1.024 xVertical 768 pixels(1 pixel = 1 R,G,B Horizontal 1366 x Vertical 768 pixels(1 pixel = 1 R,G,B
cells)
cells)
1
Pixel
2
Number of Cells
3072 (H) x 768 (V)
Horizontal 4,098 x Vertical 768 cells
3
Pixel Pitch
Horizontal 912mm x Vertical 693mm
Horizontal 810mm x mmVertical 810mm
4
Cell Pitch
R
Horizontal 0.304mm x Vertical 693mm
R
Horizontal 270mm x Vertical 810mm
G
Horizontal 0.304mm x Vertical 693mm
G
Horizontal 270mm x Vertical 810mm
B
Horizontal 0.304mm x Vertical 693mm
B
Horizontal 270mm x Vertical 810mm
Display size
932.940 (H) mm x 532.800(V) mm[ 36.73 inch x 20.98
inch ]
Horizontal 1106.46mm x Vertical 622.08mm
6
Screen size
Diagonal 42" Color Plasma Display Module
Diagonal 50" Color Plasma Display Module
7
Screen aspect
16 : 9
16 : 9
8
Display color
16.77 million colors
16.77 million colors
9
Viewing angle
10
Dimensions
11
Weight
Module 1
About 18.0 kg
Module 1
About 18.0 kg
12
Broadcasting receptionVertical frequencyandVideo/Logic Interface
PL42SD003C
60Hz/ 50Hz, LVDS
PL42SD003C
60Hz/ 50Hz, LVDS
5
EN 5
Over 160×(Angle with 50% and greater brightness per- Over 160×(Angle with 50% and greater brightness perpendicular to PDP module)
pendicular to PDP module)
982 (W) x 582 (H) x 52.9 (D) mm
1184(W) x 700 (H) x 60.1 (D) mm
EN 6
2.
S/SD/HD 3.1 PDP
Safety Instructions, Warnings and Notes
2. Safety Instructions, Warnings and Notes
** To prevent the risks of unit damage, electrical shock and radiation, take the following safety, service, and ESD precautions.
2.1
Safety instructions 
It is not allowed to operate the FTV-set without glass plate. One
function of this glass plate is to absorb Infrared Radiation.
Without this glass plate the level of Infrared Radiation produced
by the plasma display could damage your eyes.
1. Safety regulations require that during a repair:
– the set should be connected to the mains via an
isolating transformer ( in this particular case a
transformer of ≥ 800 VA);
– safety components, indicated by the symbol 
should be replaced by components identical to the
original ones;
2. Safety regulations require that after a repair the set must
be returned in its original condition. In particular attention
should be paid to the following points.
– Note: The wire trees should be routed correctly and
fixed with the mounted cable clamps.
– The insulation of the mains lead should be checked for
external damage.
– The electrical DC resistance between the mains plug
and the secondary side should be checked (only for
sets that have mains isolated power supply). This
check can be done as follows:
– unplug the mains cord and connect a wire between the
two pins of the mains plug;
– set the mains switch to the on position (keep the mains
cord unplugged!);
– measure the resistance value between the pins of the
mains plug and the metal shielding of the tuner or the
aerial connection on the set. The reading should be
between 4.5 MΩ and 12 MΩ;
– switch off the TV and remove the wire between the two
pins of the mains plug.
– The cabinet should be checked for defects to avoid
touching of any inner parts by the customer.
2.2
•
•
•
2.4
Safety Precautions for Service (Handling,
prevention of a electrical shock)
2.4.1
(Safety Precautions)
•
•
•
•
•
•
•
•
•
Warnings
•
1. ESD 
All ICs and many other semiconductors are susceptible to
electrostatic discharges (ESD ). Careless handling
during repair can reduce life drastically. When repairing,
make sure that you are connected with the same potential
as the mass of the set by a wristband with resistance.
Keep components and tools also at this same potential.
2. Available ESD protection equipment:
– complete kit ESD3 (combining all 6 prior products small table mat) 4822 310 10671
– wristband tester 4822 344 13999
3. Never replace modules or other components while the unit
is switched on.
4. When making settings, use plastic rather than metal tools.
This will prevent any short circuits and the danger of a
circuit becoming unstable.
2.3
Handling Precautions for Plasma Display
•
•
PDP module use high voltage that is dangerous to human.
Before operating PDP, always check the dust to prevent
short circuit. Be careful touching the circuit device when
power is on.
PDP module is sensitive to dust and humidity. Therefore,
assembling and disassembling must be done in no dust
place.
PDP module has a lot of electric devices. Service engineer
must wear equipment(for example, earth ring) to prevent
electric shock and working clothes to prevent electrostatic.
PDP module use a fine pitch connector which is only
working by exactly connecting with flat cable. Operator
must pay attention to a complete connection when
connector is reconnected after repairing.
The capacitor’s remaining voltage in the PDP module’s
circuit board temporarily remains after power is off.
Operator must wait for discharging of remaining voltage
during at least 1 minute.
•
•
•
•
2.4.2
Before replacing a board, discharge forcibly
The remaining electricity from board.
When connecting FFC and TCPs to the module, recheck
that they are perfectly connected.
To prevent electrical shock, be careful not to touch leads
during circuit operations.
To prevent the Logic circuit from being damaged due to
wrong working, do not connect/disconnect signal cables
during circuit operations.
Do thoroughly adjustment of a voltage label and voltageinsulation.
Before reinstalling the chassis and the chassis assembly,
be sure to use all protective stuffs including a nonmetal
controlling handle and the covering of partitioning type.
Caution for design change : Do not install any additional
devices to the module, and do not change the electrical
circuit design.
For example: Do not insert a subsidiary audio or video
connector. If you insert It, It cause danger on safety. And,
If you change the design or insert, Manufactor guarantee
will be not effect. .
If any parts of wire is overheats of damaged, replace it with
a new specified one immediately, and identify the cause of
the problem and remove the possible dangerous factors.
Examine carefully the cable status if it is twisted or
damaged or displaced. Do not change the space between
parts and circuit board. Check the cord of AC power
preparing damage.
Product Safety Mark: Some of electric or implement
material have special characteristics invisible that was
related on safety. In case of the parts are changed with new
one, even though the Voltage and Watt is higher than
before, the Safety and Protection function will be lost.
The AC power always should be turned off, before next
repair..
Check assembly condition of screw, parts and wire
arrangement after repairing. Check whether the material
around the parts get damaged.
(Precaution when repairing ESD)
•
•
There is ESD which is easily damaged by
electrostatics.(for example Integrated circuit, FET)
Electrostatic damage rate of product will be reduced by the
following technics
Before handling semiconductor parts/assembly, must
remove positive electric by ground connection, or must
wear the antistatic wrist-belt and ring. (It must be operated
after removing dust on it - It comes under precaution of
electric shock.)
Safety Instructions, Warnings and Notes
•
•
•
•
•
•
•
2.5
After removing ESD assembly, put on it with aluminum stuff
on the conductive surface to prevent charging.
Do not use chemical stuff using Freon. It generates positive
electric that can damage ESD.
Must use a soldering device for ground-tip when soldering
or de-soldering ESD.
Must use anti-static solder removal device. Most removal
device do not have antistatic which can charge a enough
positive electric enough damaging ESD.
Before removeing the protective material from the lead of a
new ESD, bring the protective material into contact with the
chassis or assembly that the ESD is to be installed on.
When handing an unpacked ESD for replacement, do not
move around too much. Moving (legs on the carpet, for
example) generates enough electrostatic to damage the
ESD.
Do not take a new ESD from the protective case until the
ESD is ready to be installed. Most ESD have a lead, which
is easily short-circuited by conductive materials (such as
conductive foam and aluminum)
Notes
A glass plate is positioned before the plasma display. This
glass plate can be cleaned with a slightly humid cloth. If
due to circumstances there is some dirt between the glass
plate and the plasma display panel it is recommended to do
some maintenance by a qualified service employee only.
2.5.1
Notes on safe handling of the plasma display
Notes to follow during service
• The work procedures shown with the Note indication are
important for ensuring the safety of the product and the
servicing work. Be sure to follow these instructions.
• Before starting the work, secure a sufficient working space.
• At all times other than when adjusting and checking the
product, be sure to turn OFF the main POWER switch and
disconnect the power cable from the power source of the
display (jig or the display itself) during servicing.
• To prevent electric shock and breakage of pwb, start the
servicing work at least 30 seconds after the main power
bas been turned off. Especially when installing and
removing the power supply pwb and the SUS pwb in which
high voltages are applied, start servicing at least 2 minutes
after the main power bas been turned off.
• While the main power is on, do not touch any parts or
circuits other than the ones specified. The high voltage
power supply block within the PDP module has a floating
ground. If any connection other than the one specified is
made between the measuring equipment and the high
voltage power supply block, it can result in electric shock or
activation of the leakage-detection circuit breaker.
• When installing the PDP module in, and removing it from
the packing carton, be sure to have at least two persons
• perform the work white being careful to ensure that the
flexible printed-circuit cable of the PDP module does not
• get caught by the packing carton.
• When the surface of the panel comes into contact with the
cushioning materials, be sure to confirm that there is no
foreign matter on top of the cushioning materials before the
surface of the panel comes into contact with the cushioning
materials. Failure to observe this precaution may result in,
the surface of the panel being scratched by foreign matter.
• When handling the circuit pwb, be sure to remove static
electricity from your body before handling the circuit pwb.
• Be sure to handle the circuit pwb by holding the large parts
as the heat sink or transformer. Failure to observe this
precaution may result in the occurrence of an abnormality
in the soldered areas.
• Do not stack the circuit pwb. Failure to observe this
precaution may result in problems resulting from scratches
on the parts, the deformation of parts, and short-circuits
due to residual electric charge.
•
•
S/SD/HD 3.1 PDP
2.
EN 7
Routing of the wires and fixing them in position must be
done in accordance with the original routing and fixing
configuration when servicing is completed. All the wires are
routed far away from the areas that become hot (such as
the heat sink). These wires are fixed in position with the
wire clamps so that the wires do not move, thereby
ensuring that they are not damaged and their materials do
not deteriorate over long periods of time. Therefore, route
the cables and fix the cables to the original position and
states using the wire clamps.
Perform a safety check when servicing is completed. Verify
that the peripherals of the serviced points have not
undergone any deterioration during servicing. Also verify
that the screws, parts and cables removed for servicing
purposes have all been returned to their proper locations in
accordance with the original
EN 8
3.
3.
S/SD/HD 3.1 PDP
Directions For Use
Not applicable
Directions For Use
Mechanical Instruction
S/SD/HD 3.1 PDP
4. Mechanical Instruction
4.1
Disassembling / Re-asssembling
4.1.1
Disassembling & Re-assembling of FPC (Flexible Printed Circuit) and Y-Buffer (Upper and Lower)
1. Removal procedure
•
Pull out the FPC from Connector by holding the lead of the
FPC with both hands.
2. Assembling procedures
•
Push the lead of FPC with same force on both sides into
the connector.
Notice: Be careful do not get a damage on the connector pin
during connecting by mistake.
4.1.2
Assembling & Disassembling of Flat Cable Connector of X-main Board
1. Disassembling Procedure
•
Pull out the clamp of connector.
•
Pull Flat cable out press down lightly.
•
Turn the Flat cable reversely.
4.
EN 9
EN 10
4.
S/SD/HD 3.1 PDP
Mechanical Instruction
2. Assembling Procedures
•
4.1.3
Put the Flat cable into the connector press down lightly until
locking sound (“Click.“) comes out.
Assembling & Disassembling the FFC and TCP form Connector
1. Disassembling of TCP
•
Open the clamp carefully.
2. Assembling of TCP
•
•
Put the TCP into the Connector carefully
Close the clamp completely.
(The sound “Click.” comes out.)
Notice:
•
1) Checking whether the foreign material is on the
Connector inside before assembling of TCP.
•
2) Be careful do not get a damage on the board by ESD
during handling of TCP.
•
Pull the TCP out from connector.
Mechanical Instruction
3. Misassembling of TCP
•
The misassembling of TCP is the cause of defect.
4. Assembling & Disassembling of FFC
The procedure of
assembling and disassembling of
FFC is same as TCP
•
This is the photo of the assembling of FFC.
4.1.4Exchange of LBE, LBF, LBG board
Photo 1
S/SD/HD 3.1 PDP
4.
EN 11
EN 12
4.
S/SD/HD 3.1 PDP
Mechanical Instruction
Photo 2 - 42" SDv2
2
4
6
1
7
5
3
6
1
7
5
3
Photo 2 - 42" SDv3
2
4
Mechanical Instruction
S/SD/HD 3.1 PDP
Photo 2 - 42" HDv3
YG
[G
]G
X
_
^
\G
Z
YY
XW
XY
Photo 2 - S37" SDv4
X[G
`
X]
X\
XZ
XX
4.
EN 13
EN 14
4.
S/SD/HD 3.1 PDP
Mechanical Instruction
Photo 2 - 50" HDv3
1. 42" SDv3 - Remove the screws in order of 2-3-5-7-1-4-6 and
10-11-13-16-9-12-14 for HD from heat sink and then get rid
of heat sink. (Photo 1)
42" HDv3, S37" SDv4, 50" HDv3
- Remove the screws in order of Center - Left Side - Right
Side from heat sink and then get rid of heat sink. (Photo 1)
2. Remove the TPC, FFC and power cable from the connectors.
3. Remove all the screws from defected board.
4. Remove the defected board.
5. Replace the new board and then screw tightly.
6. Get rid of the foreign material from the connector.
7. Connect the TCP, FFC and power cable to the connector.
8. Reassemble the TCP heat sink.
9. 42" SDv3 - Screw in order of 4-1-7-6-5-3-2 and 12-9-15-1413-11-10 for HD. (Photo 2) 42" HDv3, S37" SDv4, 50" HDv3
- Screw in order of Right Side - Left Side - Center (Photo 2)
If you screw too tightly, it is possible to get damage on the
Driver IC of TCP.
4.1.5
Exchange YBU, YBL and YM board
1. Separate all the FPC connector of YBU (Y-Buffer upper)
and YBL (Lower). (Photo 1)
2. Separate all the connector of CN5001 and CN5008 from YMain.
3. Loosen all the screws of YBU, YBL and YM.
4. Remove the board from chassis.
5. Remove the connector of CN5006 and CN5007 among
YBU, YBL and YM.
6. Remove the YBL and YBU from Y-main.
7. Replace the defected board.
Mechanical Instruction
8. Reassemble the YBU and YBL to the Y-Main.
9. Connect the connector of CN5006 and CN5007 among
YBU, YBL and YM.
10. Arrange the board on the chassis and then screw to fix.
S/SD/HD 3.1 PDP
4.
EN 15
11. Connect the FPC and YM of panel to the connector.
12. Supply the electric power to the module and then check the
waveform of board.
13. Turn off the power after the waveform is adjusted.
EN 16
5.
S/SD/HD 3.1 PDP
5. Diagnostic software
5.1
Repair tools
1.) 3122 785 90581 = Foam buffers
2.) Compair connector: 3122 785 90800
3.) V2 jig
3122 785 90760
4.) V3 jig
3122 785 90770
Figure 5-1 Foam buffers for PDP
3122 785 90760
Figure 5-2 3122 785 90760
Figure 5-3 3122 785 90770
Diagnostic software
Diagnostic software
5.2
S/SD/HD 3.1 PDP
5.
Repair Scenario
Repair Scenario FTV with SDI PDP
First check complete set
Fault Symptom?
Power Supply
is working ?
No
Power supply is not working
No voltage output
Check if LVDS from SCAVIO
or SSB board is OK
Use LVDS Tool when possible
Go to Power Supply Check
& repair scenario
With Philips application
or PDP as stand alone check
Output of SSB / SCAVIO
is OK?
No
Repair Philips application
Scavio = FM242
SSB EMG = FTP1.1
SSB EMG 2004 = FTP2.2 with LVDS Tool
SDI repair Scenario
Fault finding; Display fault
Set Type ?
42FD9925/01
42FD9935/17/93S
42FD9945/01/12/69/79/98
42FD9953/17/69C/69S/93S
42FD9936/37
SD
FM242
42PF9945
37PF9946/12
37PF9936/37
42PF9966/37/
79/93/98
42PF9976/37
42PF9936D/37
42PF9946/12/79/93/98
42PF9956/12/93
50PF9956/37
50PF9966/12/37/69/
93
50PF9986/37
SD
SD
HD
SD
HD
FTP1.1
LC4.7
FTP2.2
FTP2..2
LC4.7
FTP2..2
Repair Scenario 42SDV2
Repair Scenario SDV4
Figure 5-4
Repair Scenario SDV3
EN 17
EN 18
5.
S/SD/HD 3.1 PDP
Diagnostic software
Power Supply Check for 42SDV2
No Voltage output
Operating voltages don´t exist V2 Versions
Check F8002
Fuse 250V/8A
Connect set to mains.
Switch on On/Off switch (vacation switch)
Check CN8004 / 2pin
connector 220V AC
LED8003
Stby is on?
NO
Stanby supply is defective.
Replace PSU
Yes
On/Off relay
RLY8001/8002 acts?
Switch on via 1 or 2
Switch from standby to on;
1 Via RC when Philips application is in.
2 Via Switch on Jig connector when Philips
application is removed
Check Protection Red
LED8004
Green LED´s
8001, 8002
are on?
No
SMPS shutsdown?
Red LED8004 is on.
Protection
Yes
Green LED 8001,
8002
& Red LED are off
Check Stanby Line pin 11
on CN8002 must be low.
Yes
LED on Logic
main board ?
Disconnect mains cord
No switch on of PSU
Disconnect Y-main CN8008
Off
Blinking
On
Go to repair scenario
as stand-alone
Reconnect mains. Switch on via 1 or 2
Check Power supply
on Logic-Main board.
3,3V and 5V
No
SMPS is working?
Disconnect mains cord
Disconnect X-main CN8007
Data communication
from Philips
application to Logic
mains is OK.
Reconnect mains. Switch on via 1 or 2
Continous on, means no
data communication over
LVDS Cable.
No
SMPS is
working?
Yes
Call SAM
or SDM
Check SMPS outputs
Vs, Va, Vset, Ve, Vsc
see Sticker
Disconnect mains
Disconnect VA Logic Buffer
CN8010 / CN8011
Yes
Go to repair scenario
as stand-alone
Reconnect mains. Switch on via 1 or 2
Replace
Y-Main board
SMPS is
working?
No
Replace
X-Main board
Yes
If Power supply on Logic
mains is not OK, change PSU
or Logic main board
Discharge capacitors on Power supply, before
reconnecting X, Y or Logic Buffer board, use
2K4/10W discharge resistor
Figure 5-5
Replace defective
Logic Buffer board
Replace PSU
Diagnostic software
S/SD/HD 3.1 PDP
EN 19
Power Supply Check for SDV3
No Voltage output
Operating voltages don´t exist V3 Versions
Check CN8001 / 2pin connector 220V AC
Connect set to mains.
Check Fuse F800 / F8002 / F8003
LED8003
Stby is on?
NO
Stanby supply is defective.
Replace PSU
Yes
On/Off relay
RLY8001/8002 acts?
Switch on via 1 or 2
Check Protection Red
LED8004
Green LED´s
8001, 8002
are on?
Switch from standby to on;
1 Via RC when Philips application is in.
2 Via Switch on Jig connector when Philips
application is removed
No
SMPS shutsdown?
Red LED8004 is on.
Protection
Yes
Green LED 8001,
8002
& Red LED are off
Check Stanby Line pin 13
on CN8004 must be low.
Yes
LEDs 3,3V and 5V
on Logic main board?
Off
5.
Disconnect mains cord
No switch on of PSU
Disconnect Y-main CN8003
Check Power
supply on LogicMain board..
On
Go to repair scenario
as stand-alone
Reconnect mains. Switch on via 1 or 2
No
Disconnect mains cord
Data LED on
Logic Main ?
SMPS is
working?
On
Disconnect X-main CN8002
Continous on, means no
data communication over
LVDS Cable.
Reconnect mains. Switch on via 1 or 2
No
Blinking
Yes
Disconnect mains
SMPS is
working?
Disconnect VA Logic Buffer
CN8005 / CN800x
Data communication from
Philips application to Logic
mains is OK.
Replace
Y-Main board
Call SAM
or SDM
Yes
Reconnect mains. Switch on 1 or 2
SMPS is
working?
Go to repair
scenario
as stand-alone
No
Replace
X-Main board
Yes
Check SMPS outputs
Vs, Va, Vset, Ve, Vsc
see Sticker
Discharge capacitors on Power supply,
before reconnecting X, Y or Logic Buffer
board, use 2K4/10W discharge resistor
Figure 5-6
Replace defective
Logic Buffer board
Replace PSU
EN 20
5.
S/SD/HD 3.1 PDP
Diagnostic software
Repair Scenario SDI PDP panels as stand alone
V2 versions
Repair 42SDV2
Check PDP Type number
PDP identification =
S42SD-YD06
S42SD-YD05
No
Y
Go to V3 or V4 repair scenario
For FM242 disconnect and remove SCAVIO Board
For FTP1.1 disconnect and remove SSB and Audio Board
3122 785 90760
Connect Jig connector to CN8002 (13 pins)
Short circuit between pin 1 & 2 = On/Off switch (vacation switch)
Switch between pin 8 & 11 standby line switch
Short the Jumper J8002
Set the DIP Switch 2 on
the Logic main board to Off
Plug in the Power cord
Green Stby LED
8003 is on ?
Yes
Switch Jig connector switch on
No
Standby Supply
is defective
Green LED 8001
& 8002 are on?
No
Yes
Protection
LED8004 is on?
Go to fault finding part
Yes
No Display
Abnormal Display
Some horizontal or
Vertical Lines don´t exist
Figure 5-7
Go to operating voltages
don´t exist repair procedure for
V2 versions.
Switch on via Jig connector
switch.
Replace Power
supply board
Diagnostic software
Repair Scenario SDI PDP panels as stand alone
S/SD/HD 3.1 PDP
5.
EN 21
V3 & V4 versions
Repair 42" & 50" SDV3
as Stand alone
Check PDP type number
PDP identification =
S37SD-YD02 or YB01?
S42SD-YD05 or YB03?
S42AX-XD02 or XB01?
S50HW-XD03 or XB02?
Other PDP
type
3122 785 90770
Disconnect and remove SSB FTP2.2
or LC4.7 board.
Remove plastic Frame to have acces to all boards
Go to V2 repair scenario
Connect Jig connector with switch to Sub Supply
CN9004 / CN9005
Set DIP switch 3 to internal mode
Position of DIP Switch Int or Ext is indicated on board
1
Connect set to Mains
CN8001 on Power Supply (use mains filter)
2
3
4
Internal
Green Stby LED
8003 is on ?
1
2
3
4
External
No
Yes
Standby Supply
is defective
Switch Jig connector switch on
Green LED 8001
& 8002 are on?
Yes
No
Protection
LED8004 is on?
Go to fault finding part
Yes
No Display
Abnormal Display
Some horizontal or
Vertical Lines don´t exist
Figure 5-8
Go to operating voltages
don´t exist repair procedure for V3/V4
Versions.
Switch on via Jig connector switch.
Replace Power
supply board
EN 22
5.
S/SD/HD 3.1 PDP
Diagnostic software
Fault Symptoms
First check complete set.
Fault Symptom?
No Voltage output
Operating Voltages don´t exist
Operating Voltages exist,
but No Display
Go to
Operating voltages don´t exist.
Version V2 or V3 / V4
Go to
No Display
Abnormal Display, not
open or short Lines
Some horizontal or Vertical
Lines don´t exist on the
Display.
Sustain open
Go to
Abnormal Display
Vertical
Horizontal or
Vertical Lines?
Horizontal
Is related to Logic adress Buffer.
Go to Adress Open /
Adress Short
Figure 5-9
Is related to X-Main, Y-Main and Ybuffer.
Go to Sustain open /
Sustain short
Diagnostic software
S/SD/HD 3.1 PDP
5.
EN 23
No Display
Operating voltages exist, but there
is no Display.
No Display is related with Y-Main,
X-Main or Logic-main board
No Display
Scavio or SSB is
disconnected and removed.
Power supply will be startedup with Jig connector and
DIp swithc on Logic main is
on internal mode.
Bring set in
repair set-up as standalone
Check Logic Main
Dip switch is on
Internal mode!
Check Y-Main board
Check X-Main board
Waveform
on Y Buffer
test point ?
LED blinks?
Yes
Waveform
on X-board
test point ?
OK
Not OK
Not OK
Check V-Sync
on test point logic
main board
OK
Check Fuse ?
OK
Check Fuse ?
No
OK
OK
Logic main
normal state
Check FET
Short?
No
OK
OK
OK
Check FET
Short?
Check
Y Buffer Uper
and Lower?
Open
Check Power
supply on Logic mains.
3V3 & 5V.
Yes
Open
OK
No
Yes
Y-Main & Y-buffer
normal state
Not OK
Not OK
X-Main
normal State
Replace the Logicmain board
Replace the
Y-main board
Replace Y buffer
Figure 5-10
Replace PDP Panel
Replace the
X-main board
EN 24
5.
Diagnostic software
S/SD/HD 3.1 PDP
Abnormal Display
Abnormal Display
Exept horizontal or Vertical Lines
Check FFC
Flat Foil Connections
between Logic-main, X-main and Ymain
1
3
2
Logic-Main
Observation of
abnormal Display
Y-Main Check
Check Fuses and FET
Regular abnormal
pattern
Yes
X-Main Check
Check Fuses and FET
No
Logic main
normal state
Check Ramp
waveform on Y-board
(buffer)
Check X
Waveform
Replace the Logicmain board
Replace PDP
Not
correct
Waveform?
No
waveform
Waveform is
OK
Check voltages.
Adjust Y waveform
Go to X-Main board
Check
Check voltages.
Replace Y-Main
board
Not
correct
Waveform?
Waveform is
OK
Check supply voltages or
replace X-Main board.
Waveform not
OK
X main board seems to be OK.
Replace X-Main
board
Replace PDP
Figure 5-11
Diagnostic software
S/SD/HD 3.1 PDP
Some horizontal lines don´t exist on the Display.
Sustain open or short
Sustain Open
or Sustain Short
Horizontal Lines
Some horizontal lines don´t
exist on Display
Horizontal lines
Some horizontal lines appear
to be linked on Video
Y-FPC
Sustain open
Y-FPC
Sustain Short
Check connections
Y-buffer up & Low
Check FFC
OK
Nok
Change Y-Buffer
Upper or Lower
FPC damaged or connection
to PDP
After changing buffer,
recheck the status
Not OK
OK
Replace the panel (PDP)
There is a defect on FPC
Done
Defect is from buffer
Figure 5-12
5.
EN 25
EN 26
5.
Diagnostic software
S/SD/HD 3.1 PDP
Some Vertical Lines don´t exists or are always on,
Adress Open or Adress Short.
A part of the Display is not addressed
Adress Open
Adress Short
Adress open is related with
Logic Main, Logic Buffer
, FFC, TCP and so on.
Adress short is related with
Logic Main, Logic Buffer,
FFC, TCP and so on.
Line Open
Data Block Open
1/2 or 1/4 of Display is missing
COF Block Open
Line short
Data Block short
Logic Main / FFC
Check or change
interconnections
Logic Buffer
Check Va Supply
Logic Main / FFC
Check or change
interconnections
Logic Buffer
Check Va supply
What is the status of
open?
Check and / or
change E / F / G
Buffer
What is the status of
Short?
Check and / or
change E / F / G
Buffer
1 Line
or 1 Block
1 Line
or 1 Block
No
No
Half Block /
Half of Screen
Yes
Yes
Yes
Replace PDP
Half Block /
Half of Screen
NOK
Yes
Replace Logic-Main/
Adress Buffer E or F or G/
FFC
Replace PDP
Done
Figure 5-13
NOK
Replace Logic-Main/
Adress Buffer E or F or G/
FFC
Block Diagrams, Testpoint Overview, and Waveforms
S/SD/HD 3.1 PDP
6. Block Diagrams, Testpoint Overview, and Waveforms
6.1
Block Diagram for Logic circuit
42" SDv2
LOGIC CONTROL
LVDS
DRIVER CIRCUIT & PANEL
Data
Row
Driver
852× 480 Pixels
852× 3× 480 Cells
Timing
Y Pulse
Generator
Scan
Timing
Column Driver
V5 Vdd Va Vs
Vset Vsc Ve V3.3
Reference
- V3.3
- V5
- Vdd
- Va
- Vs
- Vsc
- Ve
- Vset
42" SDv3
:
:
:
:
:
:
:
:
Voltage for LOGIC Control
Voltage for COF driver
Voltage for FET driver
Voltage for address pulse
Voltage for sustain driver
Voltage for scan pulse
Voltage for X ramppulse
Voltage for Y ramppulse
X Pulse
Generator
Driver
Driver
Timing Cont roller
Enable
DRAM
Vs ync
Hsync
Data Controller
DCLK
Display
Input Data Proc essor
DATA_R
8Bits
DATA_G
8Bits
DATA_B
8Bits
6.
EN 27
EN 28
6.
Block Diagrams, Testpoint Overview, and Waveforms
S/SD/HD 3.1 PDP
42" HDv3
LOGIC CONTROL
Display
Driver
Timing
1024× 768 Pixels
Y Pulse
Generator
LVDS
Interface
Scan
Column Driver
X Pulse
Generator
Timing
DRIVER CIRCUIT & PANEL
Row
Driver
Enable
Data
Driver
Timing Controller
Hsync
DRAM
Vsync
Data Controller
DCLK
Input Data Processor
DATA_R
8Bits
DATA_G
8Bits
DATA_B
8Bits
1024× 3× 768 Cells
Column Driver
Vcc Vdd Va Vs
Vset Vsc Ve
Reference
- Vcc : Voltage for Logic Control
- Vdd : Voltage for Fet driver
- Va : Voltage for address pulse
- Vs : Voltage sustain pulse
- Vsc : Voltage for scan pulse
- Ve : Voltage for X ramp pulse
- Vset : Voltage for Y ramp pulse
S37" SDv4
LOGIC CONTROL
kš—“ˆ zŠˆ•
{”•Ž
852 x 480 Pixels
852 x 3 x 480 Cells
Column Driver
}ŠŠ }‹‹ }ˆ }š
}šŒ› }šŠ }Œ
Reference
- Vcc : Voltage for Logic Control
- Vdd : Voltage for FET driver
- Va : Voltage for address pulse
- Vs : Voltage sustain pulse
- Vsc : Voltage for scan pulse
- Ve : Voltage for X ramp pulse
- Vset : Voltage for Y ramp pulse
X Pulse
Generator
k™Œ™
Y Pulse
Generator
{”•Ž
DRIVER CIRCUIT & PANEL
Row
Driver
kˆ›ˆ
Driver
Timing Controller
LVDS
Interface
DRAM
Enable
Data Controller
Hsync
Input Data Processor
DATA_R
8 Bits
DATA_G
8 Bits
DATA_B
8 Bits
DCLK
Vsync
Block Diagrams, Testpoint Overview, and Waveforms
S/SD/HD 3.1 PDP
6.
EN 29
50" HDv3
LOGIC CONTROL
Display
Row
Driver
X Pulse
Generator
Driver
1366× 768 Pixels
1366× 3× 768 Cells
Scan
Y Pulse
Generator
LVDS
Interface
Column Driver
Timing
Driver
Timing Controller
Enable
DRAM
Vsync
Hsync
Data Controller
DCLK
DRIVER CIRCUIT & PANEL
Data
Input Data Processor
DATA_R
8(9)Bits
DATA_G
8(9)Bits
DATA_B
8(9)Bits
Timing
Vb
Column Driver
Vset
Vsc_l
Vscan
Vcc
Vdd
Va
Vs
Reference
- Vcc
- Vdd
- Va
- Vsc_l
- Vscan
- Vb
- Vset
6.2
: Voltage for Logic Control
: Voltage for FET driver
: Voltage for address pulse
: Voltage sustain low
: Voltage for scan high
: Voltage for X bias
: Voltage for Y ramp pulse
PSU Board diagram
42" SDv2
HOT COLD
3
1 3
8006
1
8005
PFC
8007 1
2
P8
P9
5
P10
8
P11
9
VS
8003
VE
8008
1
9
1
4
5
P12
P13
VA
Vcc
VSCAN
10
8010 1
8V6
8004
3
GREEN
GREEN
8001
8002
1
5V_STBY_S
HOT
COLD
DV5
8009
10
5
1
VSET
Protection
Board
RED
8004
8002
5
P7
COLD HOT
8011
5
GREEN
8003
3V3_VSB_S
VFAN
1
13
P6
8001
43 1
P5
P4
12
P3
8
P2
1
P1
CL 36532011_009.eps
050303
P14
EN 30
6.
Block Diagrams, Testpoint Overview, and Waveforms
S/SD/HD 3.1 PDP
D5VL
VCC
GND
GND
VE
GND
GND
VS
VS
PFC
VCC
0V
42" SDv3
CN8002
T-VS
COLD
CN8003
VS
GND
VSET
GND
VSCAN
GND
VCC
D5VL
HOT
UP
CN8009
T-VCC-S
T-VPFC
VR8008
VE
T-0V
VR8004
VS
DOW N
T-VE
T-VSCAN
T-VCC
GND
HIC8001
PFC sub B/D
CN8005
VA
HIC8003
VS sub B/D
T-PFC_VCC
CN8006
GND
VA
T-VSET
9V_Standby
GND
8V6
GND
5V_SW
GND
12V
GND
POWER OK
5V_Relay Io_2
GND
T-VA
HIC8002
alarm B/D
CN8004
CN8007
DC Prot
PIPQ
GND
GND
VR8009
D5VL
VR8002
VSB
VR8005
VSCAN
FAIL
RED
LED8004
GND
Temp Sensor
GND
5V2
VR8007
VA
VR8003
VSET
CN8008
GND
VR8006
D3V3
CN8001
AC INPUT
GREEN
LED8003
T-5V
T-3V3
GREEN
LED8001
GREEN
LED8002
9V_Standby
5V2
D3V3
D3V3
GND
GND
D5VL
GND
VS_ON
5V2
D5VL
VCC
GND
GND
VE
GND
GND
VS
VS
PFC
VCC
0V
42" HDv3
CN8002
T-VS
COLD
CN8003
VS
GND
VSET
GND
VSCAN
GND
VCC
D5VL
HOT
UP
CN8009
T-VCC-S
VR8004
VS
T-VPFC
VR8008
VE
T-0V
DOW N
T-VE
T-VSCAN
T-VCC
GND
HIC8001
PFC sub B/D
CN8005
VA
HIC8003
VS sub B/D
T-PFC_VCC
CN8006
GND
VA
T-VSET
9V_Standby
GND
8V6
GND
5V_SW
GND
12V
GND
POWER OK
5V_Relay Io_2
GND
T-VA
CN8004
CN8007
DC Prot
PIPQ
GND
GND
FAIL
RED
LED8004
GND
Temp Sensor
GND
5V2
GND
HIC8002
alarm B/D
VR8003
VSET
VR8007
VA
VR8009
D5VL
VR8002
VSB
VR8005
VSCAN
CN8008
T-3V3
T-5V
VR8006
D3V3
GREEN
LED8001
GREEN
LED8002
GREEN
LED8003
9V_Standby
5V2
CN8001
AC INPUT
D3V3
D3V3
GND
GND
D5VL
GND
VS_ON
5V2
Block Diagrams, Testpoint Overview, and Waveforms
S/SD/HD 3.1 PDP
Voltage Setting
(Nominal Load λ)
6.
EN 31
No
Output
voltage(V)
Output Voltage
Variable Point
1
PFC
370V ~ 400V
2
VS
160V ~ 185V
3
VA
65V ~ 80V
4
VE
150V ~ 170V
5
VSET
6
VSCAN
160V ~ 180V
7
D5VL
8
D3V3
9
VCC
Fixed
10
5V2
3.5V ~ 6.0V
11
9V_Standby
Fixed
Check voltage label on the PDP
for correct values.
-55V ~ -75V
4.0V ~ 6.0V
2.8V ~ 4.0V
S37" SDv4
D5VL
VG
GND
GND
VE
GND
GND
VS
VS
HOT(LIVE)
CN8002
VPFC
0V
0V
DC_VCC
VPFC
SX
SY
D5VL
VG
GND
Vscan
GND
Vset
GND
GND
VS
VS
0V
CN8008
CN8003
BUFFER
VA
D5VL
GND
V5
VR8005
VPFC
VR8009
VR8001
VG
CN8005
HIC8002
HIC8001
VR8002
VSCAN
CN8004
VA8008
VR8004 VR8006
PBA Flev
A B C D E F
1 2 3 4 5 6
VSET
D5VL
VA
G H
7 8
I
9
VA8003
VE
POWER_OK
DC_PR07
PIRO
GND
PFC_OK
+6V2
VA8007
SERIAL NO.
A5SY CODE
LJ44-00084A
Vedj
L D8003
Vuo
L D8001
+5V2
A
CN8007
L D8004
K
D3V3
CN8006
A
D5VL D3V3
GND
CN8001
K
PS-374-PH 20040420 ED05
N AC INPUT L
100-240V ~ 50/60Hz 6.3 A
STANDBY
VS_ON
AC_DET
RELAY
GND
D5VL
GND
GND
D3V3
D3V3
IN-3
PIRO
GND
GND
GND
GND
THEM_SEN
+5V2
HIC8003
VA8208
DC_PR07
VA
VSCAN
D5VL
V9
VE
VSET
VG
+8.6V
+ 6.2V
+12V
D3V3
GND
AC_DET
K A
IN-2
8V_STBY
GND
+8.8 V
GND
+5.2V
GND
+12V
GND
POWER_OK
5V_Relay
GND
STANDBY
No
Output
voltage(V)
Voltage Setting
(Nominal Load λ)
Output Voltage
Variable Point
2
VS
3
VA
60V ~ 80V
4
VE
165V ~ 195V
160V ~ 185V
5
VSET
6
VSCAN
7
D5VL
5.0V ~ 6.0V
8
D3V3
2.8V ~ 3.8V
9
VCC
Fixed
10
5V2
4.5V ~ 5.6V
11
9V_Standby
Fixed
Check voltage label on the PDP for
correct values.
160V ~ 180V
-145V ~ -175V
EN 32
6.
Block Diagrams, Testpoint Overview, and Waveforms
S/SD/HD 3.1 PDP
50" HDv3
DONGAH ELECOMM
VPFC
DC_VCC
CN8003
SY
TOP
H8002
CAUTION
VS
VA
VR8009
H8004
VR8004
H8008
CN8004
IV-2
VR8001
VPFC
D3V3
VR8007
HJC8003
+5VSB
VR8208
PBA Rev HOT (LIVE)
A B C D E F G H I
1 2 3 4 5 6 7 7 9
COLD (ISOLATED)
CN8007
IV-3
1
WARNING
FOR CONTINUED PROTECTION AGAINST RISK OF FIRE,
REPLACE ONLY WITH SAME TYPE AND RATING OF FUSE.
VR8005
+5V2
VR8006
I
D5V
1
S/N
SL
L CN8001 N
CN8008
Vedj
Vuo
P5-503-PH
GND
VS_ON
GND
GND
GND
D3V3
D3V3
DC_PROT_IN
PIRO
GND
GND
GND
THERMAL_DET
GND
+5V2
CN8009
VG
V0
V6
D3V3
V0
D6V
GND
+9V_STBY
GND
8V8
GND
D5V_5W
GND
12V
GND
POWER_OK
+5V_RELAY_IDZ
GND
STAND_BY
APPROVE
H8001
1
VA
VA
CHECK
HC8001
GND
GND
DESIGN
CN8006
VA
VA
P5-503-PHINZI
00M5510408191
1 OF 6
P5-503-PHINZ1 .PCB
UL6500:E240806.UL60950:E166582 00MS5510408191
DIPPING
H8003
IV - 1
H8005
SX
BUFFER
GND
GND
CN8006
V5
V9
GND
GND
Vset
GND
Yscan
GND
V6
D6V
HOT (LIVE)
GND
GND
V5
V5
GND
GND
V0
GND
GND
V6
D5VL
COMP.SILK SCREEN -P 1/6 COLD (ISOLATED)
CN8002
PCB NAME
VER. NO.
SHEET
FILE NAME
AC INPUT
100-240V ~ 50/60Hz BA
A55V CODE : LJ44-00065A
No
Output
voltage(V)
Voltage Setting
(Nominal Load λ)
Output Voltage
Variable Point
1
PFC
370V ~ 400V
2
VS
160V ~ 185V
3
VA
65V ~ 80V
4
VE
150V ~ 170V
5
VSET
6
VSCAN
7
D5VL
8
D3V3
9
VCC
Fixed
10
5V2
3.5V ~ 6.0V
11
9V_Standby
Fixed
Check voltage label on the PDP
for correct values.
160V ~ 180V
-55V ~ -75V
4.0V ~ 6.0V
2.8V ~ 4.0V
Circuit Diagrams and PWB Layouts
7. Circuit Diagrams and PWB Layouts
Not aplicable.
S/SD/HD 3.1 PDP
7.
EN 33
EN 34
8.
S/SD/HD 3.1 PDP
Aligments
8. Aligments
8.1
Adjustment Specification, Checking Position etc.
8.1.1
42" SDv2
1) Preparation
Insert Short Bar (J8002) in SMPS
Connect Relay Jig S/W JIG
Change Logic B’d S/W
into internal mode
external Mode
1
2
3
4
Internal Mode
1
2
3
4
Insert Jig AC socket
Oscilloscope
CH1: V-SYNC (CN201)
CH2: Y-output (OUT4)
CH3: X-output (TP OUT)
Connect Key-scan B’d
2) Turn-On.
- Turn on Power S/W
- Check LED in Logic B’d ()
- Check waveform of X-B’d nad Y-B’d
(Refer to Picture 1)
Vsync
Y-Output
X-Output
[Picture 1] Waveform of X-Board, Y-Board
Aligments
S/SD/HD 3.1 PDP
8.
EN 35
How to adjust waveform
Procedure
1) Make Full White on Screen.
2) Observe waveform using Oscilloscope.
check OUT4 TP in Y-buffer(upper).
Observe the waveform of the third waveform of 1TV-Field.
Adjust the division of oscilloscope like the left picture
Adjust the period of Vset as 10µS,
that of -Vsc(1) as 20µs,
that of -Vsc(2) as 5µs,
turning VR (Variable Resistor)
(only,when you adjust each period of -Vsc(1) & -Vsc(2)
adjust Vertical Division of oscilloscope as '2V or 5V')
VR for Vset : VR5003 (Y_main)
VR for -Vsc(1) : VR5001 (Y_main)
VR for -Vsc(2) : VR5002 (Y_main)
8.1.2
42" SDv3
V3.1 TCP Ramp Waveform Inclination Adjustment (Y-Board)
rising maintance time
falling maintance time
Adjust VR5002 to set the time of
Yrr (Rising Ramp) 10 ㎲
Adjust VR5004 to set the voltage of
Vsch (Scan high voltage) 40 V
Adjust VR5003 to set the time of
Yfr (Falling Ramp_1st) 30 ㎲
Adjust VR5001 to set the time of
Yfr (Falling Ramp_3rd) 30 ㎲
EN 36
8.
Aligments
S/SD/HD 3.1 PDP
Rising Ramp
Falling Ramp
(V)
(V)
50V/div.
20V/div.
40V
DC=0V
50µs/div.
20µs/div.
(t)
(t)
VR5004
1. VR5004 Adjustment: Vsch TP => 40volt
2. VR5002 Adjustment: Rising Ramp flat time: Typ. 10 µsec
TP:Vsch
3. VR5003 Adjustment: Falling Ramp flat time => Typ. 30 µsec
4. VR5001 Adjustment: 3th SF Falling Ramp flat time => Typ. 30 µsec
* Pay close attention to above adjustment
* Dip Switch Mode
External
Internal
1
1
2
3
4
2
3
4
Aligments
8.1.3
S/SD/HD 3.1 PDP
8.
EN 37
42" HDv3
V3.1 TCP Ramp Waveform Inclination Adjustment (Y-Board)
rising maintance time
falling maintance time
Adjust VR5002 to set the time of
Yrr (Rising Ramp) 20 ㎲
Adjust VR5004 to set the voltage of
Vsch (Scan high voltage) 40 V
Adjust VR5003 to set the time of
Yfr (Falling Ramp_1st) 20 ㎲
Adjust VR5001 to set the time of
Yfr (Falling Ramp_3rd) 10 ㎲
Rising Ramp
Falling Ramp
(V)
(V)
50V/div.
20V/div.
40V
DC=0V
20µs/div.
(t)
50µs/div.
(t)
EN 38
8.
S/SD/HD 3.1 PDP
Aligments
VR5004
1. VR5004 / Adjustment; Clock-wise to max
2. VR5005/ Adiustment; Clock-wise to max
3. VR5001/ Adiustment; Clock-wise to 4
th
division
4. VR5002 Adjustment: Rising Ramp flat time:
=> Typ. 20usec
VR5003
5. VR5006 Adjustment: Falling Ramp flat time
=> Typ. 20usec
VR5001
6. VR5003 Adjustment: 3th SF Falling Ramp flat time
=> Typ. 10usec
VR5005
VR5006
VR5002
* Pay close attention to above adjustment
* Dip Switch Mode
External
Internal
1
1
2
3
4
2
3
4
Aligments
8.1.4
S/SD/HD 3.1 PDP
8.
EN 39
S37" SDv4
V3.1 TCP Ramp Waveform Inclination Adjustment (Y-Board)
40 µs
16 µs
Adjust VR5001 to set the time of
Yrr( Rising Ramp) 40 µs
Adjust VR5000 to set the time of
38 V
Adjust VR5002 to set the time of Yfr
(Falling Ramp_1st) 16 µs
Rising Ramp
Falling Ramp
(V)
(V)
50V/div.
20V/div.
40V
DC=0V
20µs/div.
(t)
50µs/div.
(t)
EN 40
8.
S/SD/HD 3.1 PDP
Aligments
VR5004
1. VR5004 / Adjustment; Clock-wise to max
2. VR5005/ Adiustment; Clock-wise to max
3. VR5001/ Adiustment; Clock-wise to 4
th
division
4. VR5002 Adjustment: Rising Ramp flat time:
=> Typ. 20usec
VR5003
5. VR5006 Adjustment: Falling Ramp flat time
=> Typ. 20usec
VR5001
6. VR5003 Adjustment: 3th SF Falling Ramp flat time
=> Typ. 10usec
VR5005
VR5006
VR5002
* Pay close attention to above adjustment
* Dip Switch Mode
External
Internal
1
1
2
3
4
2
3
4
Aligments
8.1.5
S/SD/HD 3.1 PDP
8.
EN 41
50" HDv3
V3.1 TCP Ramp Waveform Inclination Adjustment (Y-Board)
Adjust VR5000 to set the time of
Yrr( Rising Ramp) 50 µs
Adjust VR5901 to set the voltage of
Vsch [Scan high voltage ] 25V
Adjust VR5001 to set the time of Yfr
(Falling Ramp_1st) 35 µs
Adjust VR5002 to set the time of
Yfr (Falling Ramp_3rd) 20 µs
Rising Ramp
Falling Ramp
(V)
(V)
50V/div.
20V/div.
40V
DC=0V
20µs/div.
(t)
50µs/div.
(t)
EN 42
8.
S/SD/HD 3.1 PDP
Aligments
1. VR5901(Vscan_h) / Adjustment; 25V
2. VR5901/(Vscan) / Adjustment; -90V
3. VR5901/ Adiustment; Fix
4. VR5000 Adjustment: Rising Ramp flat time:
=> Typ. 50 µsec
5. VR5001 Adjustment : Falling Ramp flat time
=> Typ. 35 µsec
VR5000
VR5001
6. VR5002 Adjustment : 3th SF Falling Ramp flat time
=> Typ. 20 µsec
VR5002
VR5004
VR5005
VR5006
* Pay close attention to above adjustment
* Dip Switch Mode
External
Internal
1
1
2
3
4
2
3
4
Aligments
8.2
Adjusting procedure
42" SDv3 (SDv2)
1. Get Pattern to be Full White.
2. Adjust Vsch to 40V with VR5004.
3. Check the waveform with an Oscilloscope.
• Triggering through V-sync of LOGIC Board.
• Connect the OUT 4 Test Point at the center of Y_buffer
to other channel, and then check the first SF operating
waveform of 1TV-Field.
• Check the waveform as before by adjusting Horizontal
Division. Check the Reset waveform when the
V_TOGG Level is changed.
• Set the Vset to 10µsby adjusting VR5002.
• Set the Falling maintenance time to 30µs by adjusting
R5003.
• Change the waveform position of Oscilloscope to 3SF
and then set the Falling maintenance time to 30µsby
adjusting the VR5001. GND maintenance section
should be checked after the Vertical Division is
readjusted to '2V or 5V'.
Special Notice: When you adjust the inclination of waveform,
do check and adjustment being based on the Reset waveform
of 1st Sub-field of 1st Frame and then move to 3rd Sub-field for
adjusting.
42" HDv3
1. Get Pattern to be Full White.
2. Adjust Vsch to Clock-wise max by using VR5004 (Vsch
should be connected to "+" unit of DMM).
3. Check the waveform using Oscilloscope.
• Triggering through V_TOGG of LOGIC Board.
• Connect the OUT 4 Test Point at the center of Y_buffer
to other channel, and then check the first SF operating
waveform of 1TV-Field.
• Check the waveform as before by adjusting Horizontal
Division. Check the Reset waveform when the
V_TOGG Level is changed.
• Set the Vset to 20µs by adjusting VR5002. GND
maintenance section should be checked after the
Vertical Division is readjusted to '2V or 5V'.
• Set the Falling maintenance time to 20µs by adjusting
R5006.
• Change the waveform position of Oscilloscope to 3SF
and then set the Falling maintenance time to 10µs by
adjusting the VR5003. GND maintenance section
should be checked after the Vertical Division is
readjusted to '2V or 5V'.
Special Notice: When you adjust the inclination of waveform,
do check and adjustment being based on the Reset waveform
of 1st Sub-field of 1st Frame and then move to 3rd Sub-field for
adjusting.
S37" SDv4
1. Get Pattern to be Full White.
2. Adjust Vsch to 40V by using VR5004 (Vsch should be
connected to "+" unit of DMM). Vsch is over 95V than
Vsc_l.
3. Check the waveform using Oscilloscope.
• Triggering through V_TOGG of LOGIC Board.
• Connect the OUT 4 Test Point at the center of Y_buffer
to other channel, and then check the first SF operating
waveform of 1TV-Field.
• Check the waveform as before by adjusting Horizontal
Division. Check the Reset waveform when the
V_TOGG Level is changed.
• Set the Vset to 40µs by adjusting VR5001. GND
maintenance section should be checked after the
Vertical Division is readjusted to '2V or 5V'.
• Set the Falling maintenance time to 16µs by adjusting
R5002.
•
S/SD/HD 3.1 PDP
8.
EN 43
Change the waveform voltage GND to 38V by
adjusting the VR5000.
Special Notice: When you adjust the inclination of waveform,
do check and adjustment being based on the Reset waveform
of 1st Sub-field of 1st Frame and then move to 3rd Sub-field for
adjusting.
50" HDv3
1. Get Pattern to be Full White.
2. Adjust Vsch to 25V by using VR5901_VSC_h (Vsc_h
should be connected to "+" unit of DMM).
3. Check the waveform using Oscilloscope.
• Triggering through V_TOGG of LOGIC Board.
• Connect the OUT 4 Test Point at the center of Y_buffer
to other channel, and then check the first SF operating
waveform of 1TV-Field.
• Check the waveform as before by adjusting Horizontal
Division. Check the Reset waveform when the
V_TOGG Level is changed.
• Set the Rising Ramp Flat Time to 50µs by adjusting
VR5000. GND maintenance section should be
checked after the Vertical Division is readjusted to '2V
or 5V'.
• Set the Falling maintenance time to 35µs by adjusting
R5001.
• Change the waveform position of Oscilloscope to 3SF
and then set the Falling maintenance time to 20µs by
adjusting the VR5002.
• GND maintenance section should be checked after the
Vertical Division is readjusted to '2V or 5V'.
Special Notice: When you adjust the inclination of waveform,
do check and adjustment being based on the Reset waveform
of 1st Sub-field of 1st Frame and then move to 3rd Sub-field for
adjusting.
Alignment table Y PWB
Wave Form
37SDV4
42SDV2
42SDV3
42HDV3
Adjusting
Location
No
Rising_Ramp
VR5001
30 µs (30 ~ 40)
Falling_Ramp_1st
VR5002
16 µs (10 ~ 20)
Vsch
VR5000
38V
Rising_Ramp (Vset) VR5003
10 µs
-Vsc 1
20 µs
VR5001
-Vsc 2
VR5002
5 µs
Rising_Ramp
VR5002
10 µs
Falling_Ramp_1st
VR5003
30 µs
Falling_Ramp_3rd
VR5001
30 µs
Vsch
VR5004
40V
Rising_Ramp
VR5002
10 µs
Falling_Ramp_1st
VR5003
20 µs
Falling_Ramp_3rd
VR5001
10 µs
Vsch Scan high volt- VR5004
age
50HDV3
Default
40V
Rising_Ramp
VR5000
50 µs
Falling_Ramp_1st
VR5001
35 µs
Falling_Ramp_3rd
VR5002
Vsch Scan high volt- VR5901
age
20 µs
25V
EN 44
9.
S/SD/HD 3.1 PDP
Circuit Descriptions
9. Circuit Descriptions
9.1
Main function of Each Assembly
9.1.1
X-main board
The X-main board generate a drive signal by switching the FET
in synchronization with logic
main board timing and supplies the X electrode of the panel
with the drive signal through the
connector.
1. Maintain voltage waveforms (including ERC)
2. Generate X rising ramp signal
3. Maintain Ve bias between Scan intervals
9.1.2
Y-main board
9.2
Abbrevitation
TCP
Tape Carrier Package
FFC
Flat Foil Cable (connection)
COF
Circuit on Foil
FPC
Flexible Printed Circuit
Vsc H or Vsc L
V Scan High or Low
SF
Sub Frame
Vset RR
Vset Raising Ramp (Flat time)
Vset FR
Vset Falling Ramp (flat time)
VR
Variable resistor
YBU & YBL
YBM
The Y-main board generate a drive signal by switching the FET
in synchronization with the logic
Main Board timing and sequentially supplies the Y electrode of
the panel with the drive signal
through the scan driver IC on the Y-buffer board. This board
connected to the panel’s
Y terminal has the following main functions.
1. Maintain voltage waveforms (including ERC)
2. Generate Y-rising Falling Ramp
3. Maintain V scan bias
9.1.3
Logic main board
The logic main board generates and outputs the address drive
output signal and the X ,Y drive signal by processing the video
signals. This Board buffers the address dirve output signal and
feeds it to the address drive IC (COF module, video signal- X Y
drive signal generation , frame memory circuit / address data
rearrangement).
9.1.4
Logic buffer(E,F)
The logic buffer transmits data signal and control signal.
9.1.5
Y-buffer board (Upper, Lower)
The Y-buffer board consisting of the upper and lower boards
supplies the Y-terminal with scan waveforms. The board
comprises 8 scan driver IC’s (ST microelectronics STV 7617 :
64 or 65 output pins) , but 4 ICs for the SD class.
9.1.6
AC Noise Filter
The AC Noise filter has function for removing noise(low
Frequency) and blocking surge. It effects Safety standards
(EMC,EMI).
9.1.7
TCP( Tape Carrier Package )
The TCP applies Va pulse to the address electrode and
constitutes address discharge by the potential difference
between the Va pulse and the pulse applied to the Y electrode.
The TCP comprise 4 data driver Ics(STV7610A :96 pins output
pins) 7 TCPs are required for signal scan.
Spare Parts List
10. Spare Parts List
42"SDv2
50"HDv3
PDP type
PDP type
S42SD-YD06
9322 195 45682
S42SD-YB04
9965 000 17797
PDP model name
(non spare)
PDP without PSU
S50HW-XD03 9322 215 26682
S50HW-XB02 9966 000 26017
PDP model name
(non spare)
PDP without PSU
BOARDS
BOARDS
LJ92-00632A
LJ92-00633A
LJ92-00634A
LJ92-00751A
LJ92-00750A
LJ92-00818A
LJ92-00998A
LJ92-00999A
LJ44-00049A
9965 000 17726
9965 000 17725
9965 000 17724
9965 000 17727
9965 000 17728
9965 000 17729
9965 000 17720
9965 000 17731
9965 000 17730
Logic-Buffer(E)
Logic-Buffer(F)
Logic-Buffer(G)
Y-Buffer(up)
Y-Buffer(down)
Logic-Board
X-Board
Y-Board
SMPS(PSU)
S42SD-YD05
9322 215 27682
S42SD-YB03
9965 000 25997
PDP model name
(non spare)
PDP without PSU
9965 000 25109
9965 000 25110
9965 000 25111
9965 000 25112
9965 000 25113
9965 000 25114
9965 000 25115
9965 000 25116
9965 000 25108
9965 000 25131
Logic-Buffer(E)
Logic-Buffer(F)
Logic-Buffer(G)
Y-Buffer(up)
Y-Buffer(down)
Logic-Board
X-Board
Y-Board
SMPS(PSU)
SUB PSU
S37SD-YD02
8204 000 77261
S37SD-YB01
9965 000 26018
PDP model name
(non spare)
PDP without PSU
9965 000 26187
9965 000 26188
9965 000 26189
9965 000 26190
9965 000 26191
9965 000 26192
9965 000 26193
9965 000 26194
9965 000 25131
Logic-Buffer(E)
Logic-Buffer(F)
Logic-Buffer(G)
Y-Buffer(up)
Logic-Board
X-Board
Y-Board
SMPS(PSU)
SUB PSU
42"SDv3
PDP type
BOARDS
LJ92-00811A
LJ92-00812A
LJ92-00813A
LJ92-00796A
LJ92-00797A
LJ92-00975D
LJ92-00943A
LJ92-00944B
LJ44-00058A
LJ44-00075A
37"SDv4
PDP type
BOARDS
LJ92-00976A
LJ92-00977A
LJ92-01002A
LG92-01022A
LJ92-01056A
LJ92-01020A
LJ92-01021A
LJ44-00084A
LJ44-00075A
42"HDv3 *not used in Eu sets
PDP type
S42AX-XD02
9322 215 25682
S42AX-XB01
9965 000 26016
PDP model name
(non spare)
PDP without PSU
9965 000 25101
9965 000 25102
9965 000 25103
9965 000 25104
9965 000 25105
9965 000 25106
9965 000 25107
9965 000 25108
9965 000 25131
Logic-Buffer(E)
Logic-Buffer(F)
Y-Buffer(up)
Y-Buffer(down)
Logic-Board
X-Board
Y-Board
SMPS(PSU)
SUB PSU
BOARDS
LJ92-00895A
LJ92-00896A
LJ92-00994A
LJ92-00993A
LJ92-00990E
LJ92-00980A
LJ92-00981A
LJ44-00058A
LJ44-00075A
LJ92-00917A
LJ92-00918A
LJ92-00919A
LJ92-00920A
LJ92-00921A
LJ92-00922A
LJ92-00880A
LJ92-00881A
LJ92-00949C
LJ92-00923A
LJ92-00959A
LJ92-00852A
LJ92-00853A
LJ44-00065A
LJ44-00099A
9965 000 25117
9965 000 25118
9965 000 25119
9965 000 25120
9965 000 25121
9965 000 25122
9965 000 25123
9965 000 25124
9965 000 25125
9965 000 25126
9965 000 25127
9965 000 25128
9965 000 25129
9965 000 25130
9965 000 26195
Logic-Buffer(E)
Logic-Buffer(F)
Logic-Buffer(G)
Logic-Buffer(H)
Logic-Buffer(I)
Logic-Buffer(J)
Y-Buffer(up)
Y-Buffer(down)
Logic-Board
SUBL
SUBR
X-Board
Y-Board
SMPS(PSU)
SUB PSU
S/SD/HD 3.1 PDP
10.
EN 45
EN 46
10.
S/SD/HD 3.1 PDP
Spare Parts List