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[AK4432]
AK4432
108dB 192kHz 32bit 2-Channel Audio DAC
1. General Description
The AK4432 is a 32-bit Stereo DAC which corresponds to digital audio systems. An internal circuit includes newly developed 32-bit Digital Filter achieving short group delay and high quality sound. The
AK4432 has single end SCF outputs, increasing performance for systems with excessive clock jitter. The
AK4432 is ideal for a wide range of applications that demands high sound quality including Home Theater and Car audio surround systems. It is housed in a 16-pin TSSOP package, saving more board space.
2. Features
1. 2ch 32bit DAC
- 128 times Oversampling
- 32-bit High Quality Sound Low Group Delay Digital Filter
- Single Ended Output, Smoothing Filter
- THD+N: 91dB
- DR, S/N: 108dB
- Channel Isolation Digital Volume (12dB～-115dB, 0.5dB Step, Mute)
- Soft Mute
- De-emphasis Filter (32kHz, 44.1kHz, 48kHz)
- I/F Format: MSB justified, LSB justified, I
2
S, TDM
- Zero Detection
2. Sampling Frequency
- Normal Speed Mode: 8kHz to 48kHz
- Double Speed Mode: 64kHz to 96kHz
- Quad Speed Mode: 128kHz to 192kHz
3. Master Clock
256fs, 384fs, 512fs or 768fs (Normal Speed Mode: fs=8kHz
48kHz)
256fs or 384fs (Double Speed Mode: fs=48kHz
96kHz)
128fs or 192fs (Quad Speed Mode: fs=96kHz
4.
P Interface: 3-wire Serial (7MHz max)/ I
192kHz)
2
C bus (400kHz Mode, 1MHz Mode)
5. Power Supply
- Analog: AVDD = 3.0
3.6V
- Input/Output Buffer: LVDD = 3.0
3.6V
- Integrated LDO for Digital Power Supply
6. Power Consumptions: 7.8mA (fs=48kHz)
7. Operational Temperature: Ta = - 40
105°C
8. Package: 16-pin TSSOP (0.65mm pitch)
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[AK4432]
3. Table of Contents
1.
General Description .................................................................................................................. 1
2.
Features ................................................................................................................................... 1
3.
Table of Contents ..................................................................................................................... 2
4.
Block Diagram .......................................................................................................................... 3
■ Block Diagram .................................................................................................................................... 3
■ Compatibility with AK4438, AK4452 and AK4458 .............................................................................. 4
5.
Pin Configurations and Functions ............................................................................................. 5
■ Ordering Guide ................................................................................................................................... 5
■ Pin Layout .......................................................................................................................................... 5
■ Pin Functions ...................................................................................................................................... 6
■ Handling of Unused Pin ..................................................................................................................... 6
6.
Absolute Maximum Ratings ...................................................................................................... 7
7.
Recommended Operation Conditions ....................................................................................... 7
8.
Analog Characteristics .............................................................................................................. 8
9.
Filter Characteristics (fs=48kHz) ............................................................................................... 9
■ Sharp Roll-Off Filter (DASD bit = “0”, DASL bit = “0”) ....................................................................... 9
■ Slow Roll-Off Filter (DASD bit = “0”, DASL bit = “1”) ....................................................................... 10
■ Short Delay Sharp Roll-Off Filter (DASD bit = “1”, DASL bit = “0”) ................................................. 11
■ Short Delay Slow Roll-Off Filter (DASD bit = “1”, DASL bit = “1”) ................................................... 12
10.
DC Characteristics .............................................................................................................. 13
11.
Switching Characteristics .................................................................................................... 14
■ Timing Diagram ................................................................................................................................ 17
12.
Functional Descriptions ....................................................................................................... 21
■ System Clock ................................................................................................................................... 21
■ Audio Interface Format ..................................................................................................................... 23
■ Digital Volume Function ................................................................................................................... 30
■ Soft Mute Operation ......................................................................................................................... 31
■ Error Detection ................................................................................................................................. 32
■ System Reset ................................................................................................................................... 32
■ Power Down Function ...................................................................................................................... 33
■ Power Off and Reset Functions ....................................................................................................... 34
■ Clock Synchronization ..................................................................................................................... 35
■ Parallel Mode ................................................................................................................................... 36
■ Audio Interface ................................................................................................................................. 36
■ Soft Mute .......................................................................................................................................... 36
■ System Clock ................................................................................................................................... 36
■ Serial Control Interface .................................................................................................................... 37
■ Register Map .................................................................................................................................... 43
■ Register Definitions .......................................................................................................................... 44
13.
Recommended External Circuits ......................................................................................... 46
14.
Package .............................................................................................................................. 48
■ Outline Dimensions .......................................................................................................................... 48
■ Material & Lead Finish ..................................................................................................................... 48
■ Marking ............................................................................................................................................. 49
15.
Revision History .................................................................................................................. 49
IMPORTANT NOTICE ................................................................................................................ 50
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■
Block Diagram
4. Block Diagram
[AK4432]
AOUTL
AOUTR
VSS
AVDD
VCOM
SMF
SMF
SCF
SCF
DAC
DAC
Audio
I/F
MCLK
LRCK
BICK
SDIN
PDN
MCLK
LRCK
BICK
SDTI
LDO
LVDD
Figure 1. Block Diagram
LDOO uP I/F
(I2C/SPI)
SMUTE/CSN/I2CFIL
ACKS/CCLK/SCL
DIF/CDTI/SDA
P/S
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[AK4432]
■
Compatibility with AK4438, AK4452 and AK4458
Channel fs
S/(N+D)
DR
AVDD (Analog Supply)
TVDD or LVDD (I/O Buffer)
Digital
Filter
SA(Sharp)
GD(Sharp)
GD (SD Slow)
Super Slow Roll-off
OSR Doubler
(Over Sampling)
Zero Detection
Digital Volume
ATT Speed (*Default)
AK4432
2ch
8k to 192kHz
91dB
108dB
3.0 to 3.6V
3.0 to 3.6V
69.9dB
AK4436 / 38
6ch / 8ch
8k to 768kHz
91dB
108dB
3.0 to 3.6V
1.7 to 3.6V
80dB
26.4/fs
5.2/fs
No
No
(128x)
No
+12 to -115.0dB +0 to -127.0dB
1020/fs (*)
4080
No
26.8/fs
4.8/fs
Yes
Yes
(256x)
Yes
4080/fs (*)
2040、510、255
Yes
AK4452 / 54 / 56 / 58
2ch / 4ch / 6ch / 8ch
8k to 768kHz
107dB
115dB
3.0 to 5.5V
1.7 to 3.6V
80dB
26.8/fs
4.8/fs
Yes
Yes
(256x)
Yes
+0 to -127.0dB
4080/fs (*)
2040、510、255
Yes LR Ch Output Select
Reset Function
(MCLK detect)
Clock Synchronization
No Yes Yes
Package
Yes (Note)
16-pin TSSOP
Yes
32-pin QFN
Yes
AK4452/54: 32-pin QFN
AK4456/58: 48-pin QFN
Note. MSB justified and 32-bit I format is not available.
2 S compatible formats are available for audio interface but LSB justified
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5. Pin Configurations and Functions
■
Ordering Guide
AK4432VT -40 +105 C 16-pin TSSOP (0.65mm pitch)
AKD4432 Evaluation Board for the AK4432
■
Pin Layout
MCLK 1 16 LDOO
BICK 2 15
SDTI 3 14
LVDD
AVDD
LRCK
PDN
SMUTE/CSN/I2CFIL
6
7
4
5
AK4432
Top
View
13
12
11
10
VSS
VCOM
AOUTL
AOUTR ACKS/CCLK/SCL
DIF/CDTI/SDA 9 P/S 8
Figure 2. Pin Layout
[AK4432]
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[AK4432]
■
Pin Functions
No. Pin Name I/O PD state Function
1
2
3
4
5
6
7
8
MCLK
BICK
SDTI
LRCK
PDN
SMUTE
CSN
I2CFIL
ACKS
CCLK
SCL
DIF
CDTI
SDA
9 P/S
10 AOUTR
11 AOUTL
12 VCOM
13 VSS
14 AVDD
15 LVDD
I
I
I
I
I
I
I
I
I
I
I
I
I
I/O
I
O
O
O
-
-
-
-
-
-
-
-
-
-
-
-
Hi-z
Hi-z
500ohm
Pull-down
-
-
-
580ohm
External Master Clock Input Pin
Audio Serial Data Clock Pin
Audio Serial Data Input
Input Channel Clock Pin
Power-Down & Reset Pin
When “L”, the AK4432 is powered -down and the control registers are reset to default state.
Soft Mute Pin in Parallel control mode.
When this pin is changed to “H”, soft mute cycle is initiated.
When returning “L”, the output mute releases.
Chip Select Pin in 3-wire serial control mode
I2C Interface Mode Select Pin
“L”: Fast Mode (400kHz), “H”: Fast Mode Plus (1MHz).
Do not change this pin during PDN pin = “H”.
Auto Setting Mode in Parallel control mode
“L”: Manual Setting Mode, “H”: Auto Setting Mode
Control Data Clock Pin in 3-wire serial control mode
Control Data Clock Pin in I2C Bus serial control mode
Audio Data Format Select in Parallel control mode.
“L” : 32bit MSB, “H”: 32bit I2S
Control Data Input Pin in 3-wire serial control mode
Control Data Input Pin in I2C Bus serial control mode
Parallel/Serial Mode Select Pin
“L”: Serial Mode, “H”: Parallel Mode
Do not change this pin during PDN pin = “H”.
Rch Analog Output Pin
Lch Analog Output Pin
Common Voltage Output Pin, AVDDx1/2
Large external capacitor around 2.2µF is used to reduce power-supply noise.
Ground Pin
Analog Power Supply Pin, 3.0V
3.6V
LDO Power Supply / Digital I/F Power Supply Pin, 3.0V
3.6V
LDO Output Pin
16 LDOO O
Pull-down This pin should be connected to ground with 1.0uF.
Note 1. All digital input pins must not be allowed to float.
■
Handling of Unused Pin
Unused I/O pins must be connected appropriately.
Classification
Analog
Pin Name
AOUTL, AOUTR
Setting
Open
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6. Absolute Maximum Ratings
Parameter Symbol Min. Max. Unit
Power Supply
Power Supply
Input Current (any pins except for supplies)
Storage Temperature
Ambient Temperature (power applied)
AVDD
LVDD
IIN
VIN
Ta
Tstg
-0.3
-0.3
-
-0.3
-40
-65
4.3
4.3
10
(LVDD+0.3) or 4.3
105
150
V
V mA
V
C
C
Note 2. All voltages with respect to ground. VSS must be connected to the same analog ground plane.
Note 3. The maximum Digital input voltage is smaller value between (LVDD+0.3)V and 4.3V.
WARNING: Operation at or beyond these limits may result in permanent damage to the device.
Normal operation is not guaranteed at these extremes.
7. Recommended Operation Conditions
Parameter Symbol Min. Typ. Max. Unit
Power Supplies Analog AVDD 3.0 3.3 3.6 V
LDO, Digital (I/F) LVDD 3.0 3.3 3.6 V
Note 4. Do not turn off the power supply of the AK4432 with the power supply of the peripheral device turned on. When using the I 2 C interface, pull-up resistors of SDA and SCL pins should be connected to LVDD or less voltage.
* AKM assumes no responsibility for the usage beyond the conditions in this data sheet.
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8. Analog Characteristics
(Ta=25 C; AVDD = LVDD=3.3V; VSS =0V; fs=48kHz, 96kHz, 192kHz; BICK=64fs; Signal
Frequency=1kHz; 32bit Data; Measurement Frequency=20Hz 20kHz at fs=48kHz, 20Hz~40kHz at fs=96kHz, 20Hz~40kHz at fs=192kHz, unless otherwise specified.)
Parameter
DAC Analog Output Characteristics
Min. Typ. Max. Unit
Resolution
S/(N+D)
(0dBFS)
Dynamic Range
(-60dBFS)
S/N
Interchannel Isolation
Interchannel Gain Mismatch
Load Capacitance fs=48kHz fs=96kHz fs=192kHz fs=48kHz (A-weighted) fs=96kHz fs=192kHz fs=48kHz (A-weighted) fs=96kHz fs=192kHz
2.55
80
90
10
2.83
91
89
89
108
101
101
108
101
101
110
0
32
3.11
0.7
30
Note 5. Full-scale output voltage. The output voltage is always proportional to AVDD (AVDD x 0.86).
Note 6. AC Load dB dB dB k pF bit
Vpp dB dB dB dB
Parameter Min. Typ. Max. Unit
Power Supplies
Power Supply Current
Normal Operation (PDN pin = “H”)
AVDD fs=48kHz, 96kHz, 192kHz
LVDD fs=48kHz
fs=96kHz
fs=192kHz
Power-down mode (PDN pin = “L”) ( Note 7 )
6.5
1.3
1.6
2.1
10
Note 7. Quiescent Current. All digital input pins including clock pins are fixed to VSS.
9.0
2
2.5
3.0
200 mA mA mA mA
µA
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9. Filter Characteristics (fs=48kHz)
(Ta= -40 +105 C; AVDD =3.0
3.6V, LVDD=3.0
3.6V; DEM=OFF)
■
Sharp RollOff Filter (DASD bit = “0”, DASL bit = “0”) fs=48kHz
Parameter
Passband
-0.08dB~+0.08dB
-6.0dB
Passband Ripple
Stopband Attenuation
Digital Filter + SCF + SMF
Frequency Response: 0Hz 20kHz fs=96kHz
Parameter
Passband
-0.08dB~+0.08dB
-6.0dB
Passband Ripple
Stopband Attenuation
Digital Filter + SCF + SMF
Frequency Response: 0Hz 40kHz fs=192kHz
Parameter
Passband
-0.08dB~+0.08dB
-6.0dB
Passband Ripple
Stopband Attenuation
Digital Filter + SCF + SMF
Frequency Response: 0Hz 80kHz
Symbol
PB
PB
PR
SB
SA
GD
FR
Symbol
PB
PB
PR
SB
SA
GD
FR
Symbol
PB
PB
PR
SB
SA
GD
FR
Min.
0
-
-0.08
26.2
69.9
-
-0.20
Min.
0
-
-0.08
52.5
69.8
-
-0.50
Min.
0
-
-0.08
104.9
69.8
-
-2.00
Typ.
-
23.99
26.4
Typ.
-
48.00
26.4
Typ.
-
96.00
26.4
[AK4432]
Unit kHz kHz dB kHz dB
1/fs dB
Unit kHz kHz dB kHz dB
1/fs dB
Unit kHz kHz dB kHz dB
1/fs dB
Max.
88.8
-
+0.08
-
0.00
Max.
44.4
-
+0.08
-
-0.10
Max.
22.2
-
+0.08
-
-0.10
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Slow Roll-Off Filter (DASD bit = “0”, DASL bit = “1”) fs=48kHz
Parameter
Passband
-0.07dB~+0.021dB
-3.0dB
Passband Ripple
Stopband Attenuation
Digital Filter + SCF + SMF
Frequency Response: 0Hz 20kHz fs=96kHz
Parameter
Passband
-0.07dB~+0.023dB
-3.0dB
Passband Ripple
Stopband Attenuation
Digital Filter + SCF + SMF
Frequency Response: 0Hz 40kHz fs=192kHz
Parameter
Passband
-0.07dB~+0.023dB
-3.0dB
Passband Ripple
Stopband Attenuation
Digital Filter + SCF + SMF
Frequency Response: 0Hz 80kHz
Symbol
PB
PB
PR
SB
SA
GD
FR
Symbol
PB
PB
PR
SB
SA
GD
FR
Symbol
PB
PB
PR
SB
SA
GD
FR
Min.
0
-
-0.07
42.6
72.6
-
-3.75
Min.
0
-
-0.07
85.1
72.6
-
-4.25
Min.
0
-
-0.07
170.3
72.6
-
-5.00
[AK4432]
Typ.
-
39.6
26.4
Typ.
-
79.3
26.4
Typ.
-
19.75
26.4
Unit kHz kHz dB kHz dB
1/fs dB
Unit kHz kHz dB kHz dB
1/fs dB
Unit kHz kHz dB kHz dB
1/fs dB
Max.
9.0
-
+0.021
-
-2.75
Max.
18.1
-
+0.023
-
-2.75
Max.
36.1
-
+0.023
-
-3.00
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■
Short Delay Sharp Roll-Off Filter (DASD bit = “1”, DASL bit = “0”) fs=48kHz
Parameter
Passband
-0.07dB~+0.07dB
-6.0dB
Passband Ripple
Stopband Attenuation
Digital Filter + SCF + SMF
Frequency Response: 0Hz 20kHz fs=96kHz
Parameter
Passband
-0.08dB~+0.08dB
-6.0dB
Passband Ripple
Stopband Attenuation
Digital Filter + SCF + SMF
Frequency Response: 0Hz 40kHz fs=192kHz
Parameter
Passband
-0.08dB~+0.08dB
-6.0dB
Passband Ripple
Stopband Attenuation
Digital Filter + SCF + SMF
Frequency Response: 0Hz 80kHz
Symbol
PB
PB
PR
SB
SA
GD
FR
Symbol
PB
PB
PR
SB
SA
GD
FR
Symbol
PB
PB
PR
SB
SA
GD
FR
Min.
0
-
-0.07
26.2
56.6
-
-0.20
Min.
0
-
-0.08
52.5
56.4
-
-0.50
Min.
0
-
-0.08
104.9
56.4
-
-2.00
Typ.
-
24.11
5.9
Typ.
-
48.25
5.9
Typ.
-
96.50
5.9
Max.
44.3
-
+0.08
-
-0.10
Max.
88.6
-
+0.08
-
0.00
Max.
22.0
-
+0.07
-
-0.10
[AK4432]
Unit kHz kHz dB kHz dB
1/fs dB
Unit kHz kHz dB kHz dB
1/fs dB
Unit kHz kHz dB kHz dB
1/fs dB
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[AK4432]
■
Short Delay Slow Roll-Off Filter (DASD bit = “1”, DASL bit = “1”) fs=48kHz
Parameter
Passband
-0.07dB~+0.05dB
-3.0dB
Passband Ripple
Stopband Attenuation
Digital Filter + SCF + SMF
Frequency Response: 0Hz 20kHz fs=96kHz
Symbol
PB
PB
PR
SB
SA
GD
FR
Min.
0
-
-0.07
43.0
74.9
-
-3.50
Typ.
-
20.24
5.2
Max.
10.1
-
+0.05
-
-2.50
Unit kHz kHz dB kHz dB
1/fs dB
Parameter
Passband
-0.07dB~+0.05dB
-3.0dB
Passband Ripple
Stopband Attenuation
Digital Filter + SCF + SMF
Frequency Response: 0Hz 40kHz fs=192kH
Symbol
PB
PB
PR
SB
SA
GD
FR
Min.
0
-
-0.07
86.0
74.9
-
-4.00
Typ.
-
40.50
5.2
Max.
20.3
-
+0.05
-
-2.50
Unit kHz kHz dB kHz dB
1/fs dB
Parameter
Passband
-0.07dB~+0.05dB
-3.0dB
Passband Ripple
Stopband Attenuation
Digital Filter + SCF + SMF
Frequency Response: 0Hz 80kHz
Symbol
PB
PB
PR
SB
SA
GD
Min.
0
-
-0.07
172.0
74.9
-
Typ.
-
81.00
5.2
Max.
40.6
-
+0.05
-
Unit kHz kHz dB kHz dB
1/fs
FR -4.75 -2.75 dB
Note 8. The passband and stopband frequencies are proportional to “fs” (system sampling rate). Each frequency response refers to that of 1kHz.
Note 9. The calculated delay time caused by digital filtering. The digital filter’s delay is calculated as the time from setting 16/24/32bit impulse data into the input register until an analog peak signal is output.
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10. DC Characteristics
(Ta= -40 +105 C; AVDD =3.0
3.6V, LVDD =3.0
3.6V, VSS=0V)
Parameter
All digital input pins except SCL and SDA pins
High-Level Input Voltage
Low-Level Input Voltage
SCL, SDA Pin
High-Level Input Voltage
Low-Level Input Voltage
SDA Pin
Low-Level Output Voltage
Fast Mode (Iout= 3mA)
Fast Mode Plus (Iout= 20mA)
Input Leakage Current
Symbol
VIH1
VIL1
VIH2
VIL2
VOL1
VOL2
Iin
Min.
80%LVDD
-
70%LVDD
-
-
-
-
[AK4432]
Typ.
-
-
-
-
-
Max.
-
20%LVDD
-
30%LVDD
0.4
0.4
10
Unit
V
V
V
V
V
V
A
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[AK4432]
11. Switching Characteristics
(Ta=-40 105 C; AVDD=LVDD=3.0 3.6V; C
L
=20pF, unless otherwise specified)
Parameter
Master Clock Timing
External Clock
256fsn:
Pulse Width Low
Pulse Width High
384fsn:
Pulse Width Low
Pulse Width High
512fsn, 256fsd, 128fsq:
Pulse Width Low
Pulse Width High
768fsn, 384fsd, 192fsq:
Pulse Width Low
Pulse Width High
LRCK Timing (Slave Mode)
Stereo mode
(TDM1-0 bits = “00”)
Normal Speed Mode
Double Speed Mode
Quad Speed Mode
Duty Cycle
TDM128 mode
(TDM1-0 bits = “01”)
LRCK frequency
I 2 S compatible: Pulse Width Low
MSB or LSB justified: Pulse Width High
TDM256 mode
(TDM1-0 bits = “10”)
LRCK frequency
I 2 S compatible: Pulse Width Low
MSB or LSB justified: Pulse Width High
fsn
fsd
fsq
Duty
fsn
fsd
fsq
tLRL
tLRH
fsn fsd
tLRL tLRH
Symbol
fCLK
tCLKL
tCLKH
fCLK
tCLKL
tCLKH
fCLK
tCLKL
tCLKH
fCLK
tCLKL
tCLKH
96
-
8
48
8
48
96
1/(128fsq)
1/(128fsq)
8
48
1/(256fsd)
1/(256fsd)
Min.
2.048
32
32
3.072
22
22
4.096
16
16
16.384
11
11
Typ.
50
48
96
192
-
48
96
192
127/(128fsq)
127/(128fsq)
48
96
255/(256fsd)
255/(256fsd)
Max.
12.288
18.432
24.576
36.864
Unit
MHz ns ns
MHz ns ns
MHz ns ns
MHz ns ns kHz kHz kHz s s kHz kHz kHz kHz
% kHz s s
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[AK4432]
Parameter
Audio Interface Timing
Normal Mode (TDM10 bits = “00”)
BICK Period
Normal Speed Mode
Double Speed Mode
Quad Speed Mode
BICK Pulse Width Low
BICK Pulse Width High
BICK “ ” to LRCK Edge
LRCK Edge to BICK “ ”
SDTI Hold Time
SDTI Setup Time
TDM128 mode (TDM1-0 bi ts = “01”)
BICK Period
Normal Speed Mode
Double Speed Mode
Quad Speed Mode
BICK Pulse Width Low
BICK Pulse Width High
BICK “ ” to LRCK Edge
LRCK Edge to BICK “
SDTI Hold Time
SDTI Setup Time
TDM256 mode (TDM1-
BICK Period
0 bits = “10”)
Normal Speed Mode
Double Speed Mode
BICK Pulse Width Low
BICK Pulse Width High
BICK “ ” to LRCK Edge
LRCK Edge to BICK “ ”
SDTI Hold Time
SDTI Setup Time
”
Symbol tBCK tBCK tBCK tBCKL tBCKH tBLR tLRB tSDH tSDS tBCK tBCK tBCK tBCKL tBCKH tBLR tLRB tSDH tSDS tBCK tBCK tBCKL tBCKH tBLR tLRB tSDH tSDS
1/128fsn
1/128fsd
1/128fsq
18
18
5
5
5
5
1/256fsn
1/256fsd
18
18
5
5
5
5
Note 10. BICK rising edge must not occur at the same time as LRCK edge.
Min.
1/256fsn
1/256fsd
1/128fsq
18
18
5
5
5
5
Typ. Max. Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
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[AK4432]
Parameter Symbol Min. Typ. Max. Unit
Control Interface Timing (3-wire Serial mode):
CCLK frequency
CCLK Pulse Width Low
Pulse Width High
CDTI Setup Time
CDTI Hold Time
CSN “H” Time
CSN “ ” to CCLK “ ”
CCLK “ ” to CSN “ ”
Control Interface Timing (I
2
C Fast mode):
SCL Clock Frequency
Bus Free Time Between Transmissions
Start Condition Hold Time (prior to first clock pulse)
Clock Low Time
Clock High Time
Setup Time for Repeated Start Condition
SDA Hold Time from SCL Falling ( Note 11 )
SDA Setup Time from SCL Rising
Rise Time of Both SDA and SCL Lines
Fall Time of Both SDA and SCL Lines
Setup Time for Stop Condition
Pulse Width of Spike Noise Suppressed by Input Filter
Capacitive load on bus
Control Interface Timing (I
2
C Fast mode Plus):
SCL Clock Frequency
Bus Free Time Between Transmissions
Start Condition Hold Time (prior to first clock pulse)
Clock Low Time
fCCK
tCCKL
tCCKH
tCDS
tCDH
tCSW
tCSS
tCSH
fSCL
tBUF
tHD:STA
tLOW
tHIGH
tSU:STA
tHD:DAT
tSU:DAT
tR
tF
tSU:STO
tSP
Cb
fSCL
tBUF
tHD:STA
tLOW
tHIGH
tSU:STA
tHD:DAT
tSU:DAT
tR
60
60
60
60
150
150
240
0
-
-
0.1
-
-
0.6
-
1.3
0.6
1.3
0.6
0.6
0
0.5
0.26
0.5
0.26
0.26
0
0.05
-
7
Clock High Time
Setup Time for Repeated Start Condition
SDA Hold Time from SCL Falling ( Note 12 )
SDA Setup Time from SCL Rising
Rise Time of Both SDA and SCL Lines
Fall Time of Both SDA and SCL Lines
Setup Time for Stop Condition
Pulse Width of Spike Noise Suppressed by Input Filter
Capacitive load on bus
tF
tSU:STO
tSP
Cb
-
0.26
0
-
Power-down & Reset Timing
tPD 800
Note 11. Data must be held for sufficient time to bridge the 300 ns transition time of SCL.
Note 12. Data must be held for sufficient time to bridge the 120ns transition time of SCL.
Note 13. The AK4432 can be reset by setting the PDN pin to “L” upon power-up. The PDN pin must held
“L” for more than 800ns for a certain reset. The AK4432 is not reset by the “L” pulse less than
Note 14. I
50ns.
2 C is a trademark of NXP B.V.
s
s
s
s ns
MHz
s
s
s
s
s
s pF ns kHz
s
s
s
s
s
s
s
s
s
s ns pF
-
-
-
-
-
-
-
0.12
0.12
-
50
550
-
1.0
0.3
-
50
400
1
-
-
-
-
400
-
-
MHz ns ns ns ns ns ns ns
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■
Timing Diagram
MCLK
LRCK
BICK
MCLK
LRCK
BICK
1/fCLK tCLKH tCLKL
1/fsn, 1/fsd, 1/fsq tdLRKH tBCK tdLRKL
VIH
VIL
Duty
= tdLRKH (or tdLRKL) x fs x 100
VIH
VIL tBCKH tBCKL
Figure 3. Clock Timing (TDM1-0 bits = “00”)
1/fCLK
VIH
VIL tCLKH tCLKL
VIH
VIL
1/fs
VIH
VIL tLRH tLRL tBCK
VIH
VIL tBCKH tBCKL
Figure 4. Clock Timing (Except TDM1-0 bits = “00”)
[AK4432]
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LRCK
BICK
SDTI
LRCK
BICK
SDTI
VIH
VIL tBLR tLRB
VIH
VIL tSDS tSDH
VIH
VIL
Figure 5. Audio Interface Timing (TDM1-0 bits = “00”)
VIH
VIL tBLR tLRB
VIH
VIL tSDS tSDH
VIH
VIL
Figure 6. Audio Interface Timing (Except TDM1-0 bits = “00”)
[AK4432]
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CCLK
VIH
VIL tCCKL
1/fCCK tCCKH
1/fCCK
Figure 7. 3-wire Serial Mode Interface Timing tCSW CSN
CDTI
CCLK tCDS tCDH tCSS tCSH tCSS tCSH
Figure 8. WRITE Data Input Timing (3-wire Serial mode)
[AK4432]
VIH
VIL
VIH
VIL
VIH
VIL
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SDA tBUF tLOW tR
SCL tHD:STA
Stop Start tHIGH tF tHD:DAT tSU:DAT tSU:STA
Start
Figure 9. I 2 C Bus Mode Timing tPD
PDN
Figure 10. Power-down & Reset Timing
VIH
VIL tSP tSU:STO
Stop
VIH
VIL
VIH
VIL
[AK4432]
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[AK4432]
12. Functional Descriptions
■
System Clock
The external clocks which are required to operate the AK4432 are MCLK, LRCK and BICK. MCLK should be synchronized with LRCK and BICK but the phase is not critical. There are two methods to set MCLK frequency. In Manual Setting Mode (ACKS bit= “0”: Default), the sampling speed is set by DFS0, DFS1
The AK4432 exits system reset (power-down mode) by inputting MCLK and LRCK after the PDN pin=“H”.
If the clock is stopped, a click noise occurs when restarting the clock. Mute the digital output externally if the click noise affects system applications.
DFS1
0
0
1
1
DFS0
0
1
0
1
Sampling Speed Mode (fs)
Normal Speed Mode 8kHz~48kHz
Double Speed Mode 48kHz~96kHz
Quad Speed Mode 96kHz~192kHz
N/A -
(default)
LRCK fs
8.0kHz
44.1kHz
48.0kHz
11.2896
12.2880
Table 2. System Clock Example (Normal Speed Mode @Manual Setting Mode) fs
(N/A: Not available)
Table 1. Sampling Speed (Manual Setting Mode)
256fs
2.0480
LRCK
88.2kHz
96.0kHz
MCLK (MHz)
384fs
3.0720
16.9344
18.4320
22.5792
24.5760
512fs
4.0960
22.5792
24.5760
MCLK (MHz)
256fs 384fs
33.8688
36.8640
768fs
6.1440
33.8688
36.8640
BICK (MHz)
2.8224
3.0720
BICK (MHz)
64fs
5.6448
6.1440
64fs
0.512
Table 3. System Clock Example (Double Speed Mode @Manual Setting Mode)
LRCK fs
176.4kHz
192.0kHz
MCLK (MHz)
128fs
22.5792
24.5760
192fs
33.8688
36.8640
BICK (MHz)
64fs
11.2896
12.2880
Table 4. System Clock Example (Quad Speed Mode @Manual Setting Mode)
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[AK4432]
512fs
MCLK
256fs
128fs
768fs
384fs
192fs
Sampling Speed Mode
Normal Speed Mode
Double Speed Mode
Quad Speed Mode
Table 5. Sampling Speed (Auto Setting Mode)
LRCK fs
8.0kHz
44.1kHz
48.0kHz
88.2kHz
96.0kHz
128fs
-
-
-
-
-
192fs
-
-
-
-
-
176.4kHz 22.5792 33.8688
192.0kHz 24.5760 36.8640
MCLK (MHz)
256fs
-
-
-
384fs
-
-
-
22.5792 33.8688
24.5760 36.8640
-
-
-
-
512fs
4.0960
768fs
22.5792 33.8688
24.5760 36.8640
Sampling
Speed Mode
6.1440 Normal Speed
Mode
-
-
-
-
-
-
-
-
Double Speed
Mode
Quad Speed
Mode
Table 6. System Clock Example (Auto Setting Mode)
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[AK4432]
■
Audio Interface Format
TDM1-0 bits, DIF2-0 bits, SDS2-0 bits, TDM1-0 pins and DIF pin settings should not be changed during operation. MSB justified and I 2
SYNCE bit = “1” (default).
S formats are available but LSB justified format is not available when
Normal Mode (TDM1-0 bit= “00”)
Two channels audio data is shifted in via the SDTI pin using BICK and LRCK inputs. Eight data formats
first, 2's complement format and is latched on the rising edge of BICK.
Input “0” data to unused bits if the data does not use maximum bits when MSB justified, I 2
16-bit MSB justified by zeroing the unused 8bits LSB).
S format is selected. (e.g. Mode2 can be used in
TDM128 Mode (TDM1-0 bit= “01”)
Four channels audio data is shifted in via the SDTI pin using BICK and LRCK inputs. Data is selected by
SDS1-0 bits. BICK is fixed to 128fs. Six data formats are supported and selected by the DIF2-0 bits as
rising edge of BICK.
TDM256 Mode (TDM1-0 bit= “1X”)
Eight channels audio data is shifted in via the SDTI pin using BICK and LRCK inputs. Data is selected by
SDS1-0 bits. BICK is fixed to 256fs. Six data formats are supported and selected by the DIF2-0 bits as
rising edge of BICK.
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[AK4432]
Mode
Normal
TDM128
TDM256
0
1
2
3
4
5
6
7
-
-
8
9
10
11
12
13
-
-
14
15
16
17
TDM1 TDM0 DIF2 DIF1 DIF0 SDTI Format
0
0
1
0
1
0
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
0
1
0
1
0 24-bit LSB justified
1
16-bit LSB justified
20-bit LSB justified
24-bit MSB justified
16-bit I
24-bit I
0 N/A
1 N/A
24-bit I
2
2
S compatible L/H 32fs
S compatible L/H 48fs
1 32-bit LSB justified
0 32-bit MSB justified
1 32-bit I 2
0 24-bit MSB justified
2
0 24-bit LSB justified
1 32-bit LSB justified
0 32-bit MSB justified
1 32-bit I 2
0 N/A
1 N/A
S compatible
S compatible
0 24-bit MSB justified
1 24-bit I 2 S compatible
0 24-bit LSB justified
1 32-bit LSB justified
LRCK BICK
H/L 32fs
H/L 40fs
H/L 48fs
H/L 48fs
H/L 64fs
H/L 64fs
S compatible L/H 64fs
128fs
128fs
128fs
128fs
128fs
128fs
128fs
128fs
256fs
256fs
256fs
256fs
256fs
256fs
18
19
1
1
1
1
0
1
32-bit MSB justified
32-bit I 2 S compatible
Table 7. Audio Data Format (N/A: Not available)
256fs
256fs
Note 15. BICK that is input to each channel must be longer than the bit length of setting format.
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[AK4432]
LRCK
BICK
(64fs)
SDTI
Mode 1
SDTI
Mode 4
LRCK
BICK
(32fs)
SDTI
Mode 0
BICK
(64fs)
SDTI
Mode 0
0 1
15 14
0 1
Don ’t care
15:MSB, 0:LSB
10 11 12 13 14 15 0 1
6 5 4 3 2 1 0 15 14
14 15 16 17 31 0 1
15 14 0 Don ’t care
Lch Data
Figure 11. Mode 0 Timing
10 11 12 13 14 15 0 1
6 5 4 3 2 1 0 15 14
14 15 16 17 31 0 1
Rch Data
15 14 0
0 1 8 9 10 11 12
Don ’t care
19:MSB, 0:LSB
19
31 0 1
0 Don ’t care
8 9 10 11 12
19
Don ’t care
23:MSB, 0:LSB
23 22 21 20 19 0 Don
’t care
Lch Data
Figure 12. Mode 1/4 Timing
23 22 21 20 19
Rch Data
31 0 1
0
0
LRCK
0 1 2 22 23 24 30 31 0 1 2 22 23 24 30 31 0 1
BICK
(64fs)
SDTI
23 22 23 22
23:MSB, 0:LSB
1 0 Don
’t care
23 22 1 0 Don
’t care
Lch Data
Figure 13. Mode 2 Timing
Rch Data
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[AK4432]
LRCK
BICK
(64fs)
SDTI
0 1 2 3
31 30
32:MSB, 0:LSB
23 24 25 31 0 1 2 3
1 0 31 30
23 24 25 31 0 1
BICK
(64fs)
SDTI
23 22
23:MSB, 0:LSB
1 0 Don ’t care 23 22
Lch Data
Figure 14. Mode 3 Timing
1 0 Don ’t care
Rch Data
LRCK
0 1 2
BICK
(64fs)
SDTI
Mode 5,6
31 30
32:MSB, 0:LSB
22 23 24
1 0 31 30
22 23 24
Lch Data
Figure 15. Mode 5/6 Timing
Rch Data
LRCK
30 31 0 1 2
0 1 2 3 23 24 25 31 0 1 2 3 23 24 25
30 31 0 1
31 0 1
23
1 0 31 30
1 0 31 30
Lch Data Rch Data
Figure 16. Mode 7 Timing
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[AK4432]
LRCK
BICK(128fs)
SDTI
Mode8
23 22
SDTI
Mode11,12
31 30
0 23 22
128 BICK
0 23 22 0 23 22 0 23 22
0 31 30 0 31 30
2
0 31 30 0 31 30
L1
32 BICK
R1
32 BICK
L2
32 BICK
R2
32 BICK
LRCK
BICK(128fs)
SDTI
Mode9
SDTI
Mode13
23 22
31 30
L1
32 BICK
0
Figure 17. Mode 8/11/12 Timing
128 BICK
23 22
0 31 30
R1
32 BICK
0 23 22
0 31 30
2
L2
32 BICK
0 23 22
0 31 30
R2
32 BICK
0 23
0 31 30
Figure 18. Mode 9/13 Timing
128 BICK
LRCK
BICK(128fs)
SDTI
23 22
L1
32 BICK
0 23 22 0 23 22
R1
32 BICK
L2
32 BICK
Figure 19. Mode 10 Timing
0 23 22
R2
32 BICK
0 23
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[AK4432]
LRCK
BICK (256fs)
SDTI
Mode14
SDTI
Mode17,18
256 BICK
23 22 0 23 22 0 23 22 0 23 22 0 23 22 0 23 22 0 23 22 0 23 22 0 23 22
LRCK
BICK (256fs)
SDTI
Mode15
SDTI
Mode19
31 30
L1
32 BICK
0 31 30 0 31 30 0 31 30 0 31 30 0 31 30
R1
32 BICK
L2
32 BICK
R2
32 BICK
L3
32 BICK
R3
32 BICK
Figure 20. Mode 14/17/18 Timing
256 BICK
0 31 30
L4
32 BICK
0 31 30
R4
32 BICK
0 31 30
23 0 23 0 23 0 23 0 23 0 23 0 23 0 23 0 23
31 30
L1
32 BICK
0 31 30 0 31 30 0 31 30 0 31 30 0 31 30
R1
32 BICK
L2
32 BICK
R2
32 BICK
L3
32 BICK
Figure 21. Mode 15/19 Timing
256 BICK
R3
32 BICK
0 31 30
L4
32 BICK
0 31 30
R4
32 BICK
0 31
LRCK
BICK(256fs)
SDTI
23 22
L1
32 BICK
0 23 22
R1
32 BICK
0 23 22 0 23 22 0 23 22 0 23 22
L2
32 BICK
R2
32 BICK
L3
32 BICK
Figure 22. Mode 16 Timing
R3
32 BICK
0 23 22
L4
32 BICK
0 23 22
R4
32 BICK
0 23
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[2] Data Select
SDS1-0 bits control the playback channel of each DAC.
LRCK
SDTI L1 R1
Figure 23. Data Slot in Normal Mode
LRCK
SDTI L1
128 BICK
R1 L2
Figure 24. Data Slot in TDM128 Mode
LRCK
SDTI L1
256 BICK
R1 L2 R2 L3 R3
Figure 25. Data Slot in TDM256 Mode
L4
Normal
TDM128
TDM256
SDS1 x x x
SDS0 x
0
1
DAC1
Lch Rch
L1 R1
L1 R1
L2 R2
0
0
0
1
L1 R1
L2 R2
1 0 L3 R3
1 1 L4 R4
( x : don’t care)
Table 8. Data Select
R2
R4
[AK4432]
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[AK4432]
■
Digital Volume Function
The AK4432 has a channel-independent digital attenuator (256 levels, 0.5dB steps). Attenuation level of
each channel of the DAC can be set by ATT7-0 bits (register 04-05H), respectively ( Table 9 ).
DAC Lch
ATTL7-0bits
00h
01h
02h
:
17h
18h
19h
:
FDh
FEh
FFh
DAC Rch
ATTR7-0bits
00h
01h
02h
:
17h
18h
19h
:
FDh
FEh
FFh
Attenuation Level
+12.0dB
+11.5dB
+11.0dB
:
+0.5dB
0.0dB
-0.5dB
:
-114.5dB
-115.0dB
MUTE (-∞)
(default)
Table 9. Attenuation level of Digital Attenuator
Transition time between set values of ATT7-0 bits can be selected by the ATS bit ( Table 10 ). When
changing output levels, transitions are executed via soft changes (0.125dB steps by every 1/4 ATT speed); thus not switching noise occurs during these transitions.
Mode ATS
0
1
0
1
ATT speed(Transition Time)
1 step(0.5dB) Soft Transition(0.125dB)
4/fs
16/fs
1/fs
4/fs
(default)
Table 10. Digital Volume Transition Time
In Mode0, it takes 255step*4/fs+1/fs(mute)=1020/fs (21.3ms @fs=48kHz) from FFH to 00H and in
Mode1, it takes 255step*16/fs+4/fs(mute)=4084/fs (85.1ms @fs=48kHz).
Mode ATS
00h ⇔ FFh Transition Time
0
1
0
1
Transition Time(fs) fs=48kHz fs=44.1kHz fs=8kHz
1021/fs
4084/fs
21.3ms
85.1ms
23.2ms
92.6ms 510.5ms
127.6ms (default)
Table 11. Digital Volume Transition Time 00h ⇔ FFh
Just after power up the DAC, the digital volume level is at MUTE. Then, the volume changes to the value set by registers in soft transition after releasing the power-down state.
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[AK4432]
■
Soft Mute Operation
The soft mute operation is performed at digital domain. When the SMUTE pin goes to “H” or set SMUTE bit to “1”, the output signal is attenuated by during ATT_DATA ATT transition time from the current
ATT level. When the SMUTE pin is returned to “L” or the SMUTE bit is returned to “0”, the mute is cancelled and the output attenuation gradually changes to the ATT level during ATT_DATA ATT transition time. If the soft mute is cancelled before attenuating , the attenuation is discontinued and returned to ATT level by the same cycle. The soft mute is effective for changing the signal source without stopping the signal transmission.
SMUTE pin or
SMUTE bit
(1) (1)
ATT_Level
(3)
Attenuation
-
GD
(2)
GD
(2)
AOUT
Note:
(1) ATT_DATA ATT transition time. For example, this time is 1020LRCK cycles (1020/fs) at
ATT_DATA=255 in Normal Speed Mode.
(2) The analog output corresponding to the digital input has group delay (GD).
(3) If the soft mute is cancelled before attenuating after starting the operation, the attenuation is discontinued and returned to ATT level by the same cycle.
Figure 26. Soft Mute Function and Zero Detection
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[AK4432]
■
Error Detection
and register access will be disabled when an error is detected. Once an error is detected, the AK4432 will not return to normal operation automatically even if all error conditions are removed. Reset the AK4432 once by bringing the PDN pin = “L” and start up again. In I 2 C mode, errors can be detected by monitoring
Acknowledge. If an error occurs, the AK4432 stops sending Acknowledge.
No Error Error Condition
1 Internal Reference Voltage Error Internal reference voltage is not powered up.
2 LDO Over Voltage Detection LDO voltage > 1.6V (Typ)
3 LDO Over Current Detection LDO current < 100mA (Typ)
Table 12. ERROR Detection
■
System Reset
The AK4432 should be reset once by bringing the PDN pin = “L” upon power-up. Power-down state of the reference voltage such as LDO and VCOM will be released by the PDN pin = “H”, and then after 1ms register writing becomes available. The internal DAC will be powered up after MCLK and LRCK are input.
The AK4432 is in power-down state until MCLK and LRCK are input.
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[AK4432]
■
Power Down Function
The AK4432 is placed in power-down mode by bringing the PDN pin “L” and the analog outputs become
floating (Hi-Z) state. Power-up and power-down timings are shown in Figure 27 .
Power
PDN pin
LDOO pin
Internal PDN
Internal
State
(1)
(2)
Normal Operation (Register Write and DAC input are available) Reset
DAC In
(Digital)
DAC Out
(Analog)
(4)
Clock In
MCLK,LRCK,BICK
Don ’t care
External
Mute
(7)
(5)
Mute ON
“0”data
GD
(3)
“0”data
GD
(5)
(6)
Don ’t care
(4)
Mute ON
Note:
(1) After AVDD and LVDD are powered-up, the PDN pin should be “L” for 800ns.
(2) After PDN pin = “H”, the LDO circuit (internal digital block driving power supply) and REF generating circuit (analog reference voltage source) are powered up, and control registers are initialized. Control register settings should be made after 1ms from the PDN pin = “H”.
(3) The analog output corresponding to digital input has group delay (GD).
(4) Analog outputs are floating (Hi-Z) in power down mode.
(5) Click noise occurs at an edge of PDN signal. This noise is output even if “0” data is input.
(6) MCLK, BICK and LRCK clocks can be stopped in power-down mode (PDN pin= “L”).
(7) Mute the analog output externally if click noise (5) adversely affect system performance.
The timing example is shown in this figure.
Figure 27. Pin Power Down/Up Sequence Example
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[AK4432]
■
Power Off and Reset Functions
PMDA DAC Register Digital Analog Output
0
1
OFF
ON
Keep
Keep
OFF
ON
Hi-Z normal
Table 13. Power OFF and Reset Function
(default)
(1) Power OFF Function (PMDA bit)
All DACs will be powered down immediately by setting PMDA bit to “0”. In this time, all internal circuits
except register are powered down and the analog output goes to floating state (Hi-z). Figure 28
shows a timing example of power-on and power-down.
PMDA bit
Internal
State
D/A In
(Digital)
D/A Out
(Analog)
Clock In
MCLK, BICK, LRCK
Normal Operation
GD (1)
(3)
Power-off
“0” data
(2)
(4)
Don
’t care
(3)
Normal Operation
GD (1)
External
MUTE
(5)
Mute ON
Note:
(1) The analog output corresponding to digital input has group delay (GD).
(2) Analog outputs are floating (Hi-Z) in power down mode.
(3) Click noise occurs at the edges (“ ” ) of the internal timing of PMDA bit. This noise is output even if “ 0” data is input.
(4) Each clock input (MCLK, BICK, LRCK) can be stopped in power down mode (PMDA bit = “0”).
(5) Mute the analog output externally if the click noise (3) adversely affects system performance.
Figure 28. Power-off/on Sequence Example 1
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[AK4432]
■
Clock Synchronization
The AK4432 has a reset function of internal counter that keeps the phase difference of the DAC outputs between the AK7738 less than 13/256fs. Clock synchronization function is enabled by SYNCE bit = “1”
(default = “1”). SYNCE bit setting must be changed when data is all “0” (no data input). When SYNCE bit
= “1” (default) MSB justified and 32-bit I 2 available.
S compatible formats are available but LSB justified format is not
(1) Synchronization with AK7738
In the use cases shown below ( Figure 29 ), the phase difference of DAC output between the AK7738
and the AK4432 can be kept less than 13/256fs by clock synchronization function.
Use Case1
Use Case2
Figure 29. Available Use Cases for Synchronization with the AK7738
Note: When synchronizing with the AK7738, both the AK7738 and the AK4432 should be set as BICK
=64fs, 32-bit MSB justified (DIF2-0 bits = “110”).
Normal
Double
Quad
LRCK[kHz] BICK[fs] MCLK[fs]
48
96
192
64
64
64
256
256
128
MCLK[MHz] Phase Diff. [1/MCLK] Phase Diff. [µs]
12.288
24.576
24.576
Note 16. Phase difference to a 20 kHz signal.
7 ~ 13
9 ~ 12
7 ~ 10
0.57 ~ 1.06
0.37 ~ 0.49
0.29 ~ 0.41
Phase Diff. [deg] *1
Table 14. Phase Difference Relationship between the AK7738 and the AK4432
4.1 ~ 7.6
2.6 ~ 3.5
2.1 ~ 2.9
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[AK4432]
■
Parallel Mode
The AK4432 will be in parallel control mode (pin control mode) by bringing the PS pin= “H”. In parallel mode, functions that need to set by registers are not available except three followings that can be used by pin settings.
Functions that cannot be controlled by pin settings are operated in their default register settings.
■
Audio Interface
“ L”) and 32-bit I2C compatible (DIF pin = “H”).
DIF pin
L
Mode
H
Table 15. Audio Interface Forma (Parallel Mode)
■
Soft Mute
Soft mute function can be used by controlling SUMTE signal by the SMUTE pin. ( Figure 26 )
■
System Clock
Auto setting mode becomes available by setting the ACKS pin to “H”. The AK4432 is in Manual setting
16 ). Input MCKI frequency shown in Table 16 .
ACKS pin
L
H
H
H
MCKI
768fs, 512fs, 384fs, 256fs
512fs, 768fs
256fs, 384fs
Sampling Speed Mode
Normal Speed Mode
Normal Speed Mode
Double Speed Mode
128fs, 192fs Quad Speed Mode
Table 16. System Clock (Parallel Mode)
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[AK4432]
■
Serial Control Interface
The AK4432 corresponds to both 3-wire serial and I 2 C bus interfaces. After releasing power-down mode, the AK4432 is in I 2 C interface mode. 3-wire serial mode will be enabled by writing a dummy command
four times continuously following power-up when the CSN pin = “H”. ( Figure 30 )
Input “0cDE → 0xADDA → 0x7A” to the CDTI pin during the CSN pin = “L” is defined as a dummy
command. The data format is MSB first. ( Figure 30 )
CSN
CCLK
CDTI Dummy Command Dummy Command Dummy Command Dummy Command
CSN
CCLK
CDTI don’tcare
(L/H)
0xDE (8bit) 0xADDA (16bit)
Figure 30. Dummy Comand Format
0x7A(8bit) don’tcare
(L/H)
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[AK4432]
(1) 3-wire Serial Control Mode (I2C pin = “L”)
The internal registers may be written through the 3-wire µP interface pins (CSN, CCLK and CDTI). The data on this interface consists of a Command code (8bits, the most significant bit is R/W flag and fixed to
“ 1” (write only) and other 7bits are fixed to “1000000”), Register address (MSB first, 16bits) and Control
data (MSB first, 8bits) ( Figure 31 )
.
Address and data are clocked in on the rising edge of CCLK and data is clocked out on the falling edge.
For write operations, data is latched on the 8th rising edge of CCLK.
The clock speed of CCLK is 7MHz (max).
The AK4432 can perform more than one byte write operation per sequence ( Figure 35 ). The master can
transmit more than one byte instead of terminating the write cycle after the first data byte is transferred.
After receiving each data packet the internal 16-bit address counter is incremented by one, and the next data is automatically taken into the next address. If the address exceeds 05H prior to generating a stop condition, the address counter will “roll over” to 0 0H and the previous data will be overwritten.
Internal registers are initialized by setting the PDN pin = “L”.
CSN
CCLK
CDTI don’tcare
(L/H)
Command Code (8bit) Register Address (16bit) Control Data (8bit) don’tcare
(L/H)
Figure 31. Control I/F Timing
R/W 1 0 0 0 0
R/W: READ/WRITE (Fixed to “1”, Write onl y)
Figure 32. Command Code
0 0
0 0 0 0 0 0 0 0 0 0 0
Figure 33. Register Address
0 0 A2 A1 A0
D7 D6 D5 D4 D3 D2 D1 D0
Figure 34. Control Data
* The AK4432 does not support data read in 3-wire serial mode.
* Control register write is not possible when the PDN pin = “L”.
* Data will not be written if there are 17times or more CCLK rising edges, or 15times or less CCLK rising edges while the CSN pin is “L”.
CSN
CCLK
CDTI don’t care
(L/H)
Command Address DATA DATA DATA DATA
Figure 35. Continuous Write of Control Data
DATA don’t care
(L/H)
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[AK4432]
(2) I 2 C-bus Control Mode
The I 2
C-bus in the AK4432 can run in fast-mode (max: 400kHz) and fast-mode plus (max: 1MHz) ( Table
I 2 C-bus mode should be fixed to either mode during operation. The PDN pin must be “L” when changing the I 2 C-bus mode.
SMUTE/CSN/I2CFIL pin
L
H
Table 17. I
Bus Mode
Fast Mode
2
Fast Mode Plus
C-Bus Mode Setting
(1) WRITE Operation
Figure 36 shows the data transfer sequence of the I
2 C-bus mode. All commands are preceded by a
START condition. A High to Low transition on the SDA line while SCL is HIGH indicates a START
followed by the eighth bit that is a data direction bit (R/W). The most significant seven bits of the slave
generates an acknowledge and the operation is executed. The master must generate the acknowledge-related clock pulse and release the SDA line (HIGH) during the acknowledge clock pulse
operation is to be executed.
The second byte is an 8-bit command code. The format is MSB first, and it is fixed to “11000000”
The third byte and fourth byte consist of the control register address of the AK4432. The format is MSB first, the third byte is fixed to zeros and the most significant 5bits of the fourth byte are fixed to zeros
terminated by a STOP condition generated by the master. A LOW to HIGH transition on the SDA line
while SCL is HIGH defines STOP condition ( Figure 44 ).
The AK4432 can perform more than one byte write operation per sequence. The master can transmit more than one byte instead of terminating the write cycle after the first data byte is transferred. After receiving each data packet the internal 16-bit address counter is incremented by one, and the next data is automatically taken into the next address. If the address exceeds “ 05H” prior to generating a stop condition, the address counter will “roll over” to “00H” and the previous data will be overwritten.
The data on the SDA line must remain stable during the HIGH period of the clock. The HIGH or LOW state
the START and STOP conditions.
S
T
A
R/W= ”0”
S
T
R
T
O
P
SDA S
Slave
Address
Command
Code
Address(0) Address(1) Data(0) Data(1) Data(n) P
A
C
K
A
C
K
A
C
K
A
C
K
A
C
K
A
C
K
A
C
K
A
C
K
Figure 36. Data Transfer Sequence in I 2 C-bus Mode
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0
1
0
0
0 1 1 0 0
R/W: READ/WRITE (“0”: Write, “1”: Read)
Figure 37. The First Byte
1
0
0 0 0 0
Figure 38. The Second Byte
0 0 0 0
1
0
0
0
Figure 39. The Third Byte
0 0 0 A2
Figure 40. The Fourth Byte
A1
R/W
0
0
A0
D7 D6 D5 D4 D3 D2 D1
Figure 41. Byte Structure of The Fifth and Succeeding Bytes
D0
[AK4432]
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[AK4432]
(2) READ Operation
In the AK4432, when a “write- slave-address assignment” (R/W bit = “0”) is received at the first
), the command code “01000000”( Figure 44 ) at the second byte and the address at the
acknowledgement is transmitted, the read command waits for the next restart condition. After receiving the restart condition, if a “read slave-address assignment” is received at the first byte, data is transferred at the second and succeeding bytes. When the master does not generate an acknowledge but generates a stop condition instead, the AK4432 ceases transmission.
R
E
S
S
T
A
R/W= ”0” T
R/W= ”1”
R
T
A
R
T
SDA S
Slave
Address
Command
Code
Address(0) Address(1) S
Slave
Address
Data(0) Data(1) Data(n)
S
T
O
P
P
A
C
K
A
C
K
A
C
K
A
C
K
A
C
K
M
A
A
C
S K
T
E
R
M
A
A
C
S K
T
E
R
T
E
R
M
A
A
C
S K
M N
A
S
A
C
T K
E
R
Figure 42. Random Address Read
0 0 0 1 0 0 0 0
Figure 43. The Second Byte (READ)
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[AK4432]
SDA
DATA
OUTPUT BY
TRANSMITTER
SCL
S start condition
Figure 44. START and STOP Conditions
P stop condition not acknowledge
DATA
OUTPUT BY
RECEIVER
SCL FROM
MASTER
S
START
CONDITION
SDA
1
2
Figure 45. Acknowledge on the I 2 C-Bus
8 acknowledge
9 clock pulse for acknowledgement
SCL data line stable; data valid change of data allowed
Figure 46. Bit Transfer on the I 2 C-Bus
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[AK4432]
■
Register Map
Addr Register Name
00H Power Management
01H Control 1
02H Data interface
03H Control 2
D7
0
0
0
0
D6
0
0
SDS1
0
D5
0
0
SDS0
0
D4
0
0
TDM1
D3
0
0
TDM0
D2
0
DFS1
DIF2
D1
PMDA
DFS0
DIF1
D0
0
ACKS
DIF0
DASL DASD ATS SMUTE SYNCE
04H AOUTL Volume Control ATTL7 ATTL6 ATTL5 ATTL4 ATTL3 ATTL2 ATTL1 ATTL0
05H AOUTR Volume Control ATTR7 ATTR6 ATTR5 ATTR4 ATTR3 ATTR2 ATTR1 ATTR0
Note 17. Data must not be written into addresses from 06H to FFH.
Note 18. The bit defined as 0 must contain a “0” value.
Note 19. When the PDN pin goes to “L”, the registers are initialized to their default values.
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[AK4432]
■
Register Definitions
Addr Register Name
00H Power Management
R/W
Default
D7
0
RMDA: DAC Power Management
0: Power Down
1: Normal Operation
D6
0
D5
0
D4
0
R/W R/W R/W R/W
0 0 0 0
D3
0
R/W
0
D2
0
R/W
0
D1
PMDA
R/W
1
D0
0
R/W
0
Addr Register Name
01H Control 1
R/W
Default
D7
0
R/W
0
D6
0
R/W
0
D5
0
R/W
0
D4
0
D3
0
R/W R/W
0 0
ACKS: Master Clock Frequency Auto Setting Mode Enable
0: Disable, Manual Setting Mode
1: Enable, Auto Setting Mode
DFS1-0: Sampling Speed Mode ( Table 1 )
The setting of DFS bits is ignored at ACKS bit =“1”.
Addr Register Name
02H Data interface
R/W
Default
D7
0
R/W
0
D6
R/W
0
DIF2-0: Audio Interface Mode Select ( Table 7 )
Default: “11 0” (32-bit MSB justified)
D5
R/W
0
D4
R/W
0
D3
R/W
0
D2
R/W
0
D2
R/W
1
TDM1-0: TDM Format Select
Default: “00” (Stereo Mode)
Mode TDM1 TDM0
0
Sampling Speed Mode
0 Stereo mode (Normal, Double, Quad Speed Mode)
1
2
3
0
0
1
1
1 TDM128 mode (Normal, Double, Quad Speed Mode)
0 TDM256 mode (Double, Quad Speed Mode)
1 TDM256 mode (Double, Quad Speed Mode)
SDS1-0: DAC Data Select
Default: “00” (Stereo Mode)
0: Normal Operation
1: Output Other Slot Data ( Table 8 )
D1
DFS1 DFS0 ACKS
R/W
1
0
D1
R/W
D0
R/W
When ACKS bit = “1”, the MCLK frequency is detected automatically. In this case, the setting of DFS bits is ignored. When this bit is “0”, DFS1-0 bits set the sampling speed mode and MCLK frequency for each mode is detected automatically.
0
D0
SDS1 SDS0 TDM1 TDM0 DIF2 DIF1 DIF0
R/W
0
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[AK4432]
Addr Register Name
03H Control 2
R/W
Default
D7
0
R/W
0
D6
0
R/W
0
D5
0
R/W
0
D4 D3 D2 D1 D0
DASL DASD ATS SMUTE SYNCE
R/W
0
R/W
0
R/W
0
R/W
0
R/W
1
SYNCE: SYNC Mode Enable
0: OFF
1: ON (default)
SMUTE: Soft Mute Enable
0: Normal Operation
1: All DAC outputs are soft muted
ATS: Transition Time Setting of Digital Attenuator ( Table 10 )
Default: “00”
DASD: Digital Filter Setting for DAC Block
0: Sharp roll off filter or Slow roll off filter (default)
1: Short delay Sharp roll off filter or Short delay Slow roll off filter
DASL: Slow Roll-off Filter Enable for DAC Block
0: Sharp Roll-off Filter (default)
1: Slow Roll-off Filter
DASD bit DASL bit
0
0
1
1
0
1
0
1
Mode
Sharp roll-off filter
Slow roll-off filter
Short delay Sharp roll-off filter
Short delay Slow roll-off filter
Table 18 Digital Filter setting for DAC Block
(default)
Addr Register Name
04H AOUTL Volume Control
05H AOUTR Volume Control ATTR7 ATTR6 ATTR5 ATTR4 ATTR3 ATTR2 ATTR1 ATTR0
R/W
Default
D7 D6 D5 D4 D3 D2 D1 D0
ATTL7 ATTL6 ATTL5 ATTL4 ATTL3 ATTL2 ATTL1 ATTL0
R/W
0
R/W
0
R/W
0
R/W
1
R/W
1
R/W
0
R/W
0
R/W
0
ATTL7-0: DAC Lch Attenuation Level
Default:18(0dB)
ATTR7-0: DAC Rch Attenuation Level
Default:18(0dB)
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[AK4432]
13. Recommended External Circuits
Audio
Controller
μP
Digital Ground
Audio
Controller
μP
Digital Ground
7
8
5
6
1
2
3
4
MCLK LDOO 16
1.0u
BICK
SDTI
LVDD 15
AVDD 14
LRCK
PDN
AK4432
VSS 13
VCOM 12
AOUTL 11 SMUTE/CSN/I2CFIL
ACKS/CCLK/SCL AOUTR 10
0.1u
+
10u
2.2u
1.0u
1.0u
DIF/CDTI/SDA PS 9
0.1u
+
10u
Lch Out
MUTE
Rch Out
LDO Supply
3.0 to 3.6V
Analog Supply
3.0 to 3.6V
Connect to AVDD or VSS
Analog Ground
Figure 47. System Connection Diagram (P/S pin = “H”)
6
7
8
4
5
1
2
3
MCLK
BICK
LDOO 16
SDTI AVDD 14
LRCK
AK4432
PDN
SMUTE/CSN/I2CFIL
VSS 13
VCOM 12
AOUTL 11
ACKS/CCLK/SCL
LVDD 15
DIF/CDTI/SDA
AOUTR 10
PS 9
1.0u
0.1u
+
10u
2.2u
1.0u
1.0u
0.1u
+
10u
Lch Out
MUTE
Rch Out
LDO Supply
3.0 to 3.6V
Analog Supply
3.0 to 3.6V
Analog Ground
Figure 48. System Connection Diagram (P/S pin = “L”)
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[AK4432]
1. Grounding and Power Supply Decoupling
The AK4432 requires careful attention to power supply and grounding arrangements. VSS must be connected to the same analog ground plane.
Decoupling capacitors should be as near to the
AK4432 as possible.
2. Voltage Reference
VCOM is a signal ground of this chip and output the voltage AVDDx1/2. A 2.2
F (±50% includes temperature characteristics) ceramic capacitor attached between the VCOM pin and VSS eliminates the effects of high frequency noise. This capacitor should be as close to the pin as possible. No load current may be drawn from the VCOM pin. All signals, especially clocks, should be kept away from the VCOM pin in order to avoid unwanted coupling into the AK4432.
The LDOO pin is a power supply for internal digital circuit and outputs 1.2V. A 1 F (±50% includes temperature characteristics) ceramic capacitor attached between the LDOO pin and VSS eliminates the effects of high frequency noise. This capacitor should be connected as close as possible to the pin. No load current may be drawn from the LDOO pin.
3. Analog Output
The output signal range is nominally 0.86 x AVDD Vpp (typ.) centered around the VCOM voltage. The
DAC input data format is 2’s complement. The output voltage is a positive full scale for
7FFFFFFFH(@32bit) and a negative full scale for 80000000H(@32bit). The ideal output is VCOM voltage for 00000000H(@32bit). The internal analog filters remove most of the noise generated by the delta-sigma modulator of DAC beyond the audio passband, in single-ended input mode.
DC offsets on analog outputs are eliminated by AC coupling since DAC outputs have DC offsets of a few mV.
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■
Outline Dimensions
16-pin TSSOP (Unit: mm)
14. Package
[AK4432]
■
Material & Lead Finish
Package molding compound: Epoxy, Halogen (Br and Cl) free
Lead frame material: Cu
Lead frame surface treatment: Solder (Pb free) plate
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■
Marking
AKM
4432
XXYYY
1) Pin #1 indication
2) Date Code: XXXX (4 digits)
3) Marking Code: 4432
15. Revision History
Date (Y/M/D) Revision Reason
15/02/18 00 First Edition
Page Contents
[AK4432]
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[AK4432]
IMPORTANT NOTICE
0. Asahi Kasei Microdevices Corporation (“AKM”) reserves the right to make changes to the information contained in this document without notice. When you consider any use or application of AKM product stipulated in this document (“Product”), please make inquiries the sales office of
AKM or authorized distributors as to current status of the Products.
1. All information included in this document are provided only to illustrate the operation and application examples of AKM Products. AKM neither makes warranties or representations with respect to the accuracy or completeness of the information contained in this document nor grants any license to any intellectual property rights or any other rights of AKM or any third party with respect to the information in this document. You are fully responsible for use of such information contained in this document in your product design or applications. AKM ASSUMES
NO LIABILITY FOR ANY LOSSES INCURRED BY YOU OR THIRD PARTIES ARISING FROM
THE USE OF SUCH INFORMATION IN YOUR PRODUCT DESIGN OR APPLICATIONS.
2. The Product is neither intended nor warranted for use in equipment or systems that require extraordinarily high levels of quality and/or reliability and/or a malfunction or failure of which may cause loss of human life, bodily injury, serious property damage or serious public impact, including but not limited to, equipment used in nuclear facilities, equipment used in the aerospace industry, medical equipment, equipment used for automobiles, trains, ships and other transportation, traffic signaling equipment, equipment used to control combustions or explosions, safety devices, elevators and escalators, devices related to electric power, and equipment used in finance-related fields. Do not use Product for the above use unless specifically agreed by AKM in writing.
3. Though AKM works continually to improve the Product’s quality and reliability, you are responsible for complying with safety standards and for providing adequate designs and safeguards for your hardware, software and systems which minimize risk and avoid situations in which a malfunction or failure of the Product could cause loss of human life, bodily injury or damage to property, including data loss or corruption.
4. Do not use or otherwise make available the Product or related technology or any information contained in this document for any military purposes, including without limitation, for the design, development, use, stockpiling or manufacturing of nuclear, chemical, or biological weapons or missile technology products (mass destruction weapons). When exporting the Products or related technology or any information contained in this document, you should comply with the applicable export control laws and regulations and follow the procedures required by such laws and regulations. The Products and related technology may not be used for or incorporated into any products or systems whose manufacture, use, or sale is prohibited under any applicable domestic or foreign laws or regulations.
5. Please contact AKM sales representative for details as to environmental matters such as the
RoHS compatibility of the Product. Please use the Product in compliance with all applicable laws and regulations that regulate the inclusion or use of controlled substances, including without limitation, the EU RoHS Directive. AKM assumes no liability for damages or losses occurring as a result of noncompliance with applicable laws and regulations.
6. Resale of the Product with provisions different from the statement and/or technical features set forth in this document shall immediately void any warranty granted by AKM for the Product and shall not create or extend in any manner whatsoever, any liability of AKM.
7. This document may not be reproduced or duplicated, in any form, in whole or in part, without prior written consent of AKM.
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