HCTL-2001-A00, HCTL-2017-A00 / PLC,

HCTL-2021-A00 / PLC

Quadrature Decoder/Counter Interface ICs

Data Sheet

Description

The HCTL-2xx1(7)-A00/PLC is CMOS ICs that performs the quadrature decoder, counter, and bus interface function. The HCTL-2xx1(7)-A00/PLC is designed to improve system performance in digital closed loop motion control systems and digital data input systems.

It does this by shifting time intensive quadrature decoder functions to a cost effective hardware solution.

The HCTL-2xx1(7)-A00/PLC consists of a quadrature decoder logic, a binary up/down state counter, and an

8-bit bus interface. The use of Schmitt-triggered CMOS inputs and input noise filters allows reliable operation in noisy environments. The HCTL-2001-A00 contains

12-bit counter and HCTL-2017-A00/PLC or HCTL-2021-

A00/PLC contains 16-bit counter and provides TLL/

CMOS compatible tri-state output buffers. Operation is specified for a temperature range from –40 to +85°C at clock frequencies up to 14MHz.

The HCTL-2021-A00/PLC provides quadrature decoder output signals and cascade signals for use with many standard computer ICs.

Part Number

HCTL-2001-A00

HCTL-2017-A00

HCTL-2017-PLC

HCTL-2021-A00

HCTL-2021-PLC

Features

• Interfaces Encoder to Microprocessor

• 14 MHz Clock Operation

• High Noise Immunity:

• Schmitt Trigger Inputs and Digital Noise Filter

• 16-Bit Binary Up/Down Counter

• Latched Outputs

• 8-Bit Tristate Interface

• 8, 12 or 16-Bit Operating Modes

• Quadrature Decoder Output Signals, Up/Down and

Count

• Cascade Output Signals, Up/Down and Count

• Substantially Reduced System Software

• 5V Operation (V

DD

– V

SS

)

• TTL/CMOS Compatible I/O

• Operating Temperature: -40°C to 85°C

• 16-Pin PDIP, 20-Pin PDIP, 20-Pin PLCC

Applications

• Interface Quadrature Incremental Encoders to

Microprocessors

• Interface Digital Potentiometers to Digital Data

Input Buses

Description

14 MHz clock operation. 12-bit counter.

14 MHz clock operation. 16-bit counter.

14 MHz clock operation. 16-bit counter.

14 MHz clock operation. 16-bit counter.

Quadrature decoder output signals. Cascade output signals.

14 MHz clock operation. 16-bit counter.

Quadrature decoder output signals. Cascade output signals.

Pinout Package

PINOUT A PACKAGE A

PINOUT A PACKAGE A

PINOUT C PACKAGE C

PINOUT B PACKAGE B

PINOUT D PACKAGE C

Devices

PINOUT A

1 D0

2 CLK

3 SEL

4 OE

5 RST

6 CH B

7 CH A

8 VSS

PINOUT C

VDD 16

D1 15

D2 14

D3 13

D4 12

D5 11

D6 10

D7 9

PINOUT B

1 D0

2 CLK

3

4

SEL

OE

5 U/D

6 NC

7 RST

8

9

CH B

CH A

10 VSS

VDD 20

D1 19

CNTdec

CNTcas

D2 18

D3 17

16

15

D4 14

D5 13

D6 12

D7 11

PINOUT D

Package Dimensions

(dimension in mm)

See Appendix A.

2

Operating Characteristics

Table 1. Absolute Maximum Ratings

(All voltages below are referenced to V

SS

)

Parameter

DC Supply Voltage

Input Voltage

Storage Temperature

Operating Temperature [1]

Symbol Limits

V

DD

V

IN

T

S

T

A

-0.3 to +6.0

-0.3 to (VDD +0.3)

-55 to +150

-40 to +85

Table 2. Recommended Operating Conditions

Parameter

DC Supply Voltage

Ambient Temperature [1]

Symbol

V

DD

T

A

Limits

4.5 to 5.5

-40 to +85

Units

V

C

Units

C

C

V

V

Table 3. DC Characteristics V

DD

= 5V ± 5%; T

A

= -40 to 85°C

Symbol Parameter

VIL [2] Low-Level Input Voltage

VIH [2]

VT+

VT-

VH

IIN

IDD

CIN [3]

High-Level Input Voltage

Schmitt-Trigger Positive-Going Threshold

Schmitt-Trigger Negative-Going Threshold

Schmitt-Trigger Hysteresis

Input Current

VOH [2] High-Level Output Voltage

VOL [2] Low-Level Output Voltage

IOZ High-Z Output Leakage Current

Quiescent Supply Current

Input Capacitance

COUT [3] Output Capacitance

Condition

IOH = -3.75 mA

IOL = +3.75mA

VO=VSS or VDD

VIN=Vss or VDD

Any Input

Any Output

Min

3.5

1.0

1.0

VIN=VSS or VDD -10

2.4

-10

Typ

3.5

1.5

2.0

1

4.5

0.2

1

1

5

5

Max

1.5

4.0

+10

0.4

+10

100

V

µ

A

µ

A pF pF

V

V

µ

A

V

V

V

Unit

V

Notes:

1. Free Air

2. In general, for any V

DD

between the allowable limits (+4.5V to +5.5V), V

IL

= 0.3V

DD

and V

IH

= 0.7V

DD

; typical values are V

OH

= V

DD

– 0.5V

and V

OL

= V

SS

+ 0.2V

3. Including package capacitance

3

CNT

DCDR

NA

U/D NA

CNTCAS NA

D4

D5

D6

D7

NC

D0

D1

D2

D3

Functional Pin Description

Table 4a. Functional Pin Descriptions (PDIP Package)

VDD

VSS

CLK

CHA

CHB

Symbol Pin

8

2

HCTL-

2001-

A00

16

7 6

RST

OE

SEL

5

4

3

8

2

HCTL-

2017-

A00

16

7 6

5

4

3

HCTL-

2021-

A00

20

10

2

9 8

7

4

3

Description

Power Supply

Ground

CLK is a Schmitt-trigger input for the external clock signal.

CHA and CHB are Schmitt-trigger inputs that accept the outputs from a quadrature-encoded source, such as incremental optical shaft encoder. Two channels, A and B, nominally 90 degrees out of phase, are required.

This active low Schmitt-trigger input clears the internal position counter and the position latch. It also resets the inhibit logic. RST is asynchronous with respect to any other input signals.

This CMOS active low input enables the tri-state output buffers. The OE/ and SEL inputs are sampled by the internal inhibit logic on the falling edge of the clock to control the loading of the internal position data latch.

These CMOS inputs directly controls which data byte from the position latch is enabled into the 8-bit tri-state output buffer. As in OE/ above, SEL also control the internal inhibit logic.

SEL

0

1

BYTE SELECTED

High

Low

12

11

10

9

NA

1

15

14

13

NA

NA

NA

12

11

10

9

NA

1

15

14

13

16

5

15

14

13

12

11

6

1

19

18

17

A pulse is presented on this LSTTL-compatible output when the quadrature decoder has detected a state transition. CNT

This LSTTL-compatible output allows the user to determine whether the IC is counting up or down and is intended to be used with the CNTDCDR and

CNTCAS outputs. The proper signal U (high level) or D/ (low level) will be present before the rising edge of the CNTDCDR and CNTCAS outputs.

A pulse is presented on this LSTTL-compatible output when the HCTL-2021-

A00 internal counter overflows or underflows. The rising edge on this waveform may be used to trigger an external counter.

These LSTTL-compatible tri-state outputs form an 8-bit output ports through which the contents of the 16-bit position latch may be read in 2 sequential bytes. The High byte is read first followed by the Low bytes.

Not connected - this pin should be left floating.

4

VDD

VSS

CLK

CHA

CHB

Table 4b. Functional Pin Descriptions (PLCC Package)

Symbol

RST

OE

SEL

2

9

8

20

10

Pin

HCTL

2017-PLC

HCTL

2021-PLC

Description

20

10

2

9

8

Power Supply

Ground

CLK is a Schmitt-trigger input for the external clock signal.

CHA and CHB are Schmitt-trigger inputs that accept the outputs from a quadrature-encoded source, such as incremental optical shaft encoder. Two channels, A and B, nominally 90 degrees out of phase, are required.

7

4

3

7

4

3

This active low Schmitt-trigger input clears the internal position counter and the position latch. It also resets the inhibit logic. RST is asynchronous with respect to any other input signals.

This CMOS active low input enables the tri-state output buffers. The OE/ and SEL inputs are sampled by the internal inhibit logic on the falling edge of the clock to control the loading of the internal position data latch.

These CMOS inputs directly controls which data byte from the position latch is enabled into the 8-bit tri-state output buffer. As in OE/ above, SEL also control the internal inhibit logic.

SEL

0

1

BYTE SELECTED

High

Low

CNTDCDR NA

U/D NA

CNTCAS NA

D4

D5

D6

D7

D0

D1

D2

D3

14

13

12

11

1

19

18

17

16

5

15

14

13

12

11

1

19

18

17

A pulse is presented on this LSTTL-compatible output when the quadrature decoder has detected a state transition.

This LSTTL-compatible output allows the user to determine whether the IC is counting up or down and is intended to be used with the CNTDCDR and CNTCAS outputs. The proper signal U (high level) or D/ (low level) will be present before the rising edge of the CNTDCDR and CNTCAS outputs.

A pulse is presented on this LSTTL-compatible output when the HCTL-2021-PLC internal counter overflows or underflows. The rising edge on this waveform may be used to trigger an external counter.

These LSTTL-compatible tri-state outputs form an 8-bit output ports through which the contents of the 16-bit position latch may be read in 2 sequential bytes. The

High byte is read first followed by the Low bytes.

5

Switching Characteristics

Table 5. Switching Characteristics Max/Min specifications at V

DD

= 5.0 ± 5%, T

A

= -40 to +85 O C, C

L

= 40 pf

Symbol Description

1 tCLK Clock Period

2 tCHH Pulse width, clock high

3 tCD Delay time, rising edge of clock to valid, updated count information on

D0-7

4 tODE Delay time, OE fall to valid data

5 tODZ Delay time, OE rise to Hi-Z state on D0-7

6 tSDV Delay time, SEL valid to stable, selected data byte (delay to High Byte

= delay to Low Byte)

7 tCLH Pulse width, clock low

8 tSS Setup time, SEL before clock fall

9 tOS

10 tSH

Setup time, OEN before clock fall

Hold time, SEL after clock fall

11 tOH Hold time, OE after clock fall

12 tRST Pulse width, RST low

13 tDCD Hold time, last position count stable on D0-7 after clock rise

14 tDSD Hold time, last data byte stable after next SEL state change

15 tDOD Hold time, data byte stable after OE rise

16 tUDD Delay time, U/D valid after clock rise

17 tCHD Delay time, CNTDCDR or CNTCAS high after clock rise

18 tCLD Delay time, CNTDCDRor CNTCAS low after clock fall

19 tUDH Hold time, U/D stable after clock rise

20 tUDCS Setup time, U/D valid before CNTDCDR or CNTCAS rise

21 tUDCH Hold time, U/D stable after CNTDCDR or CNTCAS rise

0

28

10

10

10

28

20

20

0

Min.

70

28

10 tCLK-45 tCLK-45

Max.

65

65

40

65

45

45

45 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns

Units ns ns ns

Figure 1. Reset Waveform

Figure 2: Waveforms for Positive Clock Edge Related Delays

6

Figure 3: Tri-State Output Timing

Figure 4: Bus Control Timing

Figure 5: Decoder, Cascade Output Timing

7

Figure 6. Simplified Logic Diagram

Digital Noise Filter

The digital noise filter section is responsible for rejecting noise on the incoming quadrature signals. The input section uses two techniques to implement improved noise rejection. Schmitt-trigger inputs and a three-clock-cycle delay filter combine to reject low level noise and large, short duration noise spikes that typically occur in motor system applications. Both common mode and differential mode noise are rejected. The user benefits from these techniques by improved integrity of the data in the counter. False counts triggered by noise are avoided.

Figure 7 shows the simplified schematic of the input section. The signals are first passed through a Schmitttrigger buffer to address the problem of input signals with slow rise times and low-level noise (approximately

< 1V). The cleaned up signals are then passed to a four-bit delay filter. The signals on each channel are sampled on rising clock edges. A time history of the signals is stored in the four-bit shift register. Any change on the input is tested for a stable level being present for three consecutive rising clock edges.

Therefore, the filtered output waveforms can change only after an input level has the same value for three consecutive rising clock edges.

Refer to Figure 8, which shows the timing diagram.

The result of this circuitry is that short noise spikes between rising clock edges are ignored and pulses shorter than two clock periods are rejected.

8

CHA

CK

D Q D Q D Q D Q

CHB

D Q D Q D Q D Q

CK

Figure 7. Simplified Digital Noise Filter Logic

3 t

CLK

CLK

CHA

CHB

CHA filtered

CHB filtered

CHI filtered

Noise Spike t

E t

E t

E t

ES t

ES t

ES t

ES t

E

Figure 8. Signal Propagation through Digital Noise Filter

J

CK

K

Q

CHA filtered

J

CK

K

Q

CHB filtered

9

clk state chA chB

Quadrature Decoder

The quadrature decoder decodes the incoming filtered signals into count information. This circuitry multiplies the resolution of the input signals by a factor of four

(4X decoding).

The quadrature decoder samples the outputs of the

CHA and CHB filters. Based on the past binary state of the two signals and the present state, it outputs a count signal and a direction signal to the integral position counter.

Figure 9 shows the quadrature states of Channel A and

Channel B signals. The 4x decoder will output a count signal for every state transition (count up and count down). Figure 9 shows the valid state transitions for 4x decoder. The 4x decoder will output a count signal at respective state transition, depending on the counting direction. Channel A leading channel B results in counting up. Channel B leading channel A results in counting down. Illegal state transitions, caused by faulty encoders or noise severe enough to pass through the filter, will produce an erroneous count.

1 2 3 4

Tes

Te

Telp count up

1

4

Valid State

Transitions

2

3

CHA

0

0

1

1

CHB

1

0

0

1

Figure 9. 4x Decoder Mode

STATE

3

4

1

2

10 count down

4X Decoder

(Count Up &

Count Down)

Pulse

Pulse

Pulse

Pulse

Design Considerations

The designer should be aware that the operation of the digital filter places a timing constraint on the relationship between incoming quadrature signals and the external clock. Figure 8 shows the timing waveform with an incremental encoder input. Since an input has to be stable for three rising clock edges, the encoder pulse width (t

E

- low or high) has to be greater than three clock periods (3t

CLK

). This guarantees that the asynchronous input will be stable during three consecutive rising clock edges. A realistic design also has to take into account finite rise time of the waveforms, asymmetry of the waveforms, and noise.

In the presence of large amounts of noise, t

E

should be much greater than 3t

CLK—

to allow for the interruption of the consecutive level sampling by the three-bit delay filter. It should be noted that a change on the inputs that is qualified by the filter will internally propagate in a maximum of seven clock periods.

The quadrature decoder circuitry imposes a second timing constraint between the external clock and the input signals. There must be at least one clock period between consecutive quadrature states. As shown in

Figure 8, a quadrature state is defined by consecutive edges on both channels. Therefore, t

ES

(encoder state period) > t

CLK-

. The designer must account for deviations from the nominal 90 degree phasing of input signals to guarantee that t

ES

> t

CLK

.

Position Counter

This section consists of a 16-bit binary up/down counter which counts on rising clock edges as explained in the Quadrature Decoder Section. All 16bit of data are passed to the position data latch. The system can use this count data in several ways:

A. System total range is £ 16 bits, so the count represents “absolute” position.

B. The system is cyclic with £ 16 bits of count per cycle. RSTN (or CHI) is used to reset the counter every cycle and the system uses the data to interpolate within the cycle.

C. System count is > 8 or 16 bits, so the count data is used as a relative or incremental position input for a system software computation of absolute position. In this case counter rollover occurs. In order to prevent loss of position information, the processor must read the outputs of the IC before the count increments one-half of the maximum count capability. Two’s-complement arithmetic is normally used to compute position from these periodic position updates.

D. The system count is >16 bits so the HCTL-2021-

A00/PLC can be cascaded with other standard counter ICs to give absolute position.

Position Data Latch

The position data latch is a 16-bit latch which captures the position counter output data on each rising clock edge, except when its inputs are disabled by the inhibit logic section during two-byte read operations. The output data is passed to the bus interface section.

When active, a signal from the inhibit logic section prevents new data from being captured by the latch, keeping the data stable while successive reads are made through the bus section. The latch is automatically re-enabled at the end of these reads. The latch is cleared to 0 asynchronously by the RST signal.

Inhibit Logic

The Inhibit Logic Section samples the OE and SEL signals on the falling edge of the clock and, in response to certain conditions (see Figure 10), inhibits the position data latch. The RST signal asynchronously clears the inhibit logic, enabling the latch.

Bus Interface

The bus interface section consists of a 16 to 8 line multiplexer and an 8-bit, three-state output buffer. The multiplexer allows independent access to the low and high bytes of the position data latch. The SEL and OE signals determine which byte is output and whether or not the output bus is in the high-Z state.

Quadrature Decoder Output

The quadrature decoder output section consists of count and up/down outputs derived from the 4x decoder mode of the HCTL-2021-A00/PLC. When the decoder has detected a count, a pulse, one-half clock cycle long, will be output on the CNT

DCDR

pin. This output will occur during the clock cycle in which the internal counter is updated. The U/D pin will be set to the proper voltage level one clock cycle before the rising edge of the CNT

DCDR

pulse, and held one clock cycle after the rising edge of the CNT

DCDR

pulse. These outputs are not affected by the inhibit logic.

Cascade Output (HCTL-2021-A00/PLC only!)

The cascade output also consists of count and up/down outputs. When the HCTL-2021-A00/PLC internal counter overflows or underflows, a pulse, one-half clock cycle long, will be output on the CNT

CAS

pin. This output will occur during the clock cycle in which the internal counter is updated. The U/D pin will be set to the proper voltage level one clock cycle before the rising edge of the CNT

CAS

pulse, and held one clock cycle after the rising edge of the CNT

CAS

pulse. These outputs are not affected by the inhibit logic.

Step

1

2

3

SEL

L

H

X

OE

L

L

H

Figure 10. Two Bytes Read Sequence

CLK Inhibit Signal Action

Falling 1

Falling 1

Falling 0

Set inhibit; read high byte

Read low byte; starts reset

Complete inhibit logic reset

Figure 11. Simplified Inhibit Logic

11

Cascade Considerations (HCTL-2021-A00/PLC only!)

The HCTL-2021-A00/PLC cascading system allows for position reads of more than two bytes. These reads can be accomplished by latching all the bytes and then reading the bytes sequentially over the 8-bit bus. It is assumed here that, externally, a counter followed by a latch is used to count any count that exceeds 16 bits.

This configuration is compatible with the HCTL-2021-

A00/PLC internal counter/latch combination.

Consider the sequence of events for a read cycle that starts as the HCTL-2021-A00/PLC internal counter rolls over. On the rising clock edge, count data is updated in the internal counter, rolling it over. A count-cascade pulse (CNT

CAS

) will be generated with some delay after the rising clock edge (t

CHD

). There will be additional propagation delays through the external counters and registers. Meanwhile, with SEL and OE low to start the read, the internal latches are inhibited at the falling edge and do not update again till the inhibit is reset.

If the CNT

CAS

pulse now toggles the external counter and this count gets latched a major count error will occur. The count error is because the external latches get updated when the internal latch is inhibited.

Valid data can be ensured by latching the external counter data when the high byte read is started (SEL and OE low). This latched external byte corresponds to the count in the inhibited internal latch. The cascade pulse that occurs during the clock cycle when the read begins gets counted by the external counter and is not lost.

For example, suppose the HCTL-2021-A00/PLC count is at FFFFh and an external counter is at F0h, with the count going up. A count occurring in the HCTL-2021-

A00/PLC will cause the counter to roll over and a cascade pulse will be generated. A read starting on this clock cycle will show FFFFh from the HCTL-2021-

A00/PLC. The external latch should read F0h, but if the host latches the count after the cascade signal propagates through, the external latch will read F1h.

Figure 12. Decode and Cascade Output Diagram (4x)

12

General Interfacing

The 16-bit latch and inhibit logic allows access to 16 bits of count with an 8-bit bus. When only 8-bits of count are required, a simple 8-bit (1-byte) mode is available by holding SEL high continuously. This disables the inhibit logic. OE provides control of the tri-state bus, and read timing is shown in Figure 2 and

3.

For proper operation of the inhibit logic during a twobyte read, OE and SEL must be synchronous with CLK due to the falling edge sampling of OE and SEL.

The internal inhibit logic on the HCTL-2021-A00/PLC inhibits the transfer of data from the counter to the position data latch during the time that the latch outputs are being read. The inhibit logic allows the microprocessor / microcontroller to first read the high order 4 or 8 bits from the latch and then read the low order 8 bits from the latch. Meanwhile, the counter can continue to keep track of the quadrature states from the CHA and CHB input signals.

Figure 11 shows the simplified inhibit logic circuit. The operation of the circuitry is illustrated in the read timing shown in Figure 13.

Actions

1. On the rising edge of the clock, counter data is transferred to the position data latch, provided the inhibit signal is low.

2. When OE goes low, the outputs of the multiplexer are enabled onto the data lines. If SEL is low, then the high order data bytes are enabled onto the data lines. If SEL is high, then the low order data bytes are enabled onto the data lines.

3. When the IC detects a low on OE and SEL during a falling clock edge, the internal inhibit signal is activated. This blocks new data from being transferred from the counter to the position data latch.

4. When SEL goes high, the data outputs change from the high byte to the low byte.

5. The first of two reset conditions for the inhibit logic is met when the IC detects a logic high on SEL and a logic low on OE during a falling clock edge.

6. When OE goes high, the data lines change to a high impedance state.

7. The IC detects a logic high on OE during a falling clock edge. This satisfies the second reset condition for the inhibit logic.

Figure 13. Typical Interface Timing

13

APPENDIX A

PACKAGE A

PIN 1

IDENT.

C

L

PIN #1

OPTIONAL EJECTOR

PIN INDENTION SHOWN

FOR CONVENTIONAL

MOLD ONLY

D

B

B

B2 e

SECTION A-A

A

A

BASE PLANE

SEATING PLANE

SYMBOL

A

A1

A2

B

B1

B2

C

C1

D

E

E1 e

L

MIN.

-

0.015

0.115

0.014

0.014

0.550

0.008

0.008

0.740

NOM.

-

-

0.130

-

0.018

0.600

-

0.010

0.750

0.295

0.240

0.125

0.310

0.250

0.100 BSC.

-

ALL DIMENSIONS ARE IN INCHES

MAX.

.175

-

0.195

0.022

0.020

0.650

0.014

0.012

0.760

0.325

0.260

0.150

14

PACKAGE B

OPTIONAL EJECTOR

PIN INDENTION SHOWN

FOR CONVENTIONAL

MOLD ONLY

C

L

PIN #1

PIN 1

IDENT.

D

B

B

B2 e

SECTION A-A

A

A

BASE PLANE

SEATING PLANE

SYMBOL

A

A1

A2

B

B1

B2

C

C1

D

E

E1 e

L

MIN.

-

0.015

0.115

0.014

0.014

0.550

0.008

0.008

1.010

NOM.

-

-

0.130

-

0.018

0.600

-

0.010

1.030

0.295

0.240

0.125

0.310

0.250

0.100 BSC.

-

ALL DIMENSIONS ARE IN INCHES

MAX.

.175

-

0.195

0.022

0.020

0.650

0.014

0.012

1.035

0.325

0.260

0.150

15

PACKAGE C

PIN 1

IDENTIFIER & ZONE

D

D1

TOP VIEW

B1

BOTTOM VIEW e

B

D2/E2

SIDE VIEW

D2/E2

R .045/.025

SEATING PLANE

SYMBOL

A

A1

A2

B

B1

C

D

D1

D2

E

E1

E2 e

MIN

0.165

0.090

0.146

0.013

0.026

NOM MAX

0.172

0.105

0.152

0.180

0.120

0.156

0.017

0.021

0.029

0.032

0.008

0.010

0.012

0.385

0.390

0.395

0.350

0.352

0.355

0.145

0.385

0.160

0.390

0.165

0.395

0.350

0.352

0.355

0.145

0.160

0.165

0.050 REF.

ALL DIMENSIONS ARE IN INCHES.

For product information and a complete list of distributors, please go to our web site: www.avagotech.com

Avago, Avago Technologies, and the A logo are trademarks of Avago Technologies, Pte. in the United States and other countries.

Data subject to change. Copyright © 2006 Avago Technologies Pte. All rights reserved.

AV01-0041EN - February 27, 2006