Application Note (AN241)
PCI-FRM01 Register Level Application Guide
PCI-FRM01 Register Level
Application Guide (Ver1.1)
Windows, Windows2000, Windows NT and Windows XP are trademarks of Microsoft. We acknowledge that the
trademarks or service names of all other organizations mentioned in this document as their own property.
Information furnished by DAQ system is believed to be accurate and reliable. However, no responsibility is assumed by DAQ
system for its use, nor for any infringements of patents or other rights of third parties which may result from its use. No license is
granted by implication or otherwise under any patent or copyrights of DAQ system.
The information in this document is subject to change without notice and no part of this document may be copied or
reproduced without the prior written consent.
Copyrights  2005 DAQ system, All rights reserved.
 2005 DAQ system, all rights reserved.
http://www.daqsystem.com
Application Note (AN241)
PCI-FRM01 Register Level Application Guide
-- Contents --
1. PCI BUS Address Space
2. PCI-FRM01 Functional Block Diagram
3. I/O Address Usage
4. Memory Address Usage
5. UART Usage
6. Interrupt Controller Usage
7. LVDS(Camera Link) Interface Usage
8. DIO(Digital Input/Output) Usage
References
 2005 DAQ system, all rights reserved.
http://www.daqsystem.com
Application Note (AN241)
PCI-FRM01 Register Level Application Guide
1. PCI BUS Address Space
As it uses CPU of the x86 system which we use mainly, it can classify greatly it to memory and I/O
area. In order to support Plug & Play in case of PCI bus that has a special configuration. It can make
the resource and device state control register etc.
4G
Memory
Area
64K
I/O Area
64DWORD
Configuration
Area
The PCI-FRM01 use a memory and I/O that have been assigned to system for operation, the
contents are as follows that they required.
Address Area
Requirements
Memory
Maximum 64MByte
I/O
256 Byte
Configuration
128 Byte
 2005 DAQ system, all rights reserved.
Remark
http://www.daqsystem.com
Application Note (AN241)
PCI-FRM01 Register Level Application Guide
2. PCI-FRM01 Functional Block Diagram
The address area assigned by the system in the PCI-FRM01 division is shown in the figure below.
Most peripheral control and status register is in the I/O area, only SDR SRAM is in the memory area.
The configuration area can not be used in the most application because of only using resources for the
system boot time.
PCI BUS
PCI-FRM01 INTERNAL BLOCK - FPGA
Local BUS
Local Bus
Address
Data(Mem,I/O)
Reserved
(0x00 ? 0x5F)
PCI Target
UART
(0x60)
BUS Mux
MEM Decoder
To each IO
Module
Reserved
(0x70 ? 0xAF)
IO Decoder
Interrupt controller
DPRAM
CLOCK syn.
Camera Link(LVDS)
(0xC0)
DIO
(0xD0)
Reserved
(0xE0 ? 0xFF)
Interrupt
Controller
(0xb0)
Ext. Address, Data, Control
INT sources in Chip
MEM Decoder
From Ext.
PCI-FRM01 of the figure shows the function block, which features the dotted area is reserved for
future feature additions.
 2005 DAQ system, all rights reserved.
http://www.daqsystem.com
Application Note (AN241)
PCI-FRM01 Register Level Application Guide
3. I/O Address Usage
The below table indicates the base address of the peripheral device that is located I/O area address.
The table below the I / O area is located at the address indicates the base address of the peripheral
device. All I / O registers are 32-bit input / output processing.
I/O Address
Offset Base
00h-5Fh
Function
Description
Comment
Reserved
Reserved area for future use
UART
Universal asynchronous receiver transmitter (RS232C)
70h-AFh
Reserved
Reserved area for future use
B0h
Interrupt
Interrupt controller
C0h
Camera Link
Frame grabber LVDS interface
D0h
DIO
Photo-coupler isolated Digital input/Output
Reserved
Reserved area for future use
60h
E0h-FFh
 2005 DAQ system, all rights reserved.
http://www.daqsystem.com
Application Note (AN241)
PCI-FRM01 Register Level Application Guide
4. Memory Address Usage
SDR SRAM for future enhancements can be used.
Memory Address
Space
0h - 4000000h
Model
Undefined
Description
Comment
SDR SDRAM 64M Byte
Reserved
Memory region
I/O region
3FFFFFFh
FFh
Reserved
DIO (0xD0)
LVDS (0xC0)
Interrupt (0xB0)
Reserved
64M Byte
Reserved
UART (0x60)
Reserved
00h
000000h
 2005 DAQ system, all rights reserved.
http://www.daqsystem.com
Application Note (AN241)
PCI-FRM01 Register Level Application Guide
5. UART Usage
The PCI-FRM01 has UART (9600BPS, 1 stop, 1 start, 8 data bit, no parity).
Function
UART
I/O Address
Offset
Register
Description
60h
Data Buffer
Transmit Data(Write) / Received Data(Read)
64h
Baud
Baud generator x”82"
68h
Control
Control Register
6Ch
Status
Status Register
(1) Data Buffer
(2) Baud rate generator
40Mhz
Initial Value : x”82”
(3) Control
UART Control Register Bit Position & Usage
31
8 7
6
5
4
3
2
Reserved
1
0
TE RE
Bit
Name
Description
Default Value
0
RE
Receiver Interrupt Enable
‘0’
1
TE
Transmitter Interrupt Enable
‘0’
31 - 2
Reserved
All ‘0’
For future use
(4) STATUS
UART STATUS Register Bit Position & Usage
31
8
Reserved
7
6
5
4
3
2
1
0
TB TI FE PE RB RI
Bit
Name
Description
0
RI
Receive Interrupt
‘0’
1
RB
Receive Busy
‘0’
2
PE
Parity Error(Unused)
‘0’
 2005 DAQ system, all rights reserved.
Default Value
http://www.daqsystem.com
Application Note (AN241)
PCI-FRM01 Register Level Application Guide
3
FE
Frame Error
‘0’
4
TI
Transmit Interrupt
‘0’
5
TB
Transmit Busy
‘0’
31 - 2
Reserved
For future use
All ‘0’
 2005 DAQ system, all rights reserved.
http://www.daqsystem.com
Application Note (AN241)
PCI-FRM01 Register Level Application Guide
6. Interrupt Controller Usage
PCI-FRM01 has interrupt controller to handle the hardware interrupt for each I/O device.
When you use these interrupts, eliminating the use of polling overhead of the process can be reduced.
Function
INTERRUPT
I/O Address
Offset
Register
Description
B0h
INT_STA
Interrupt Status Register (Read Only)
B4h
INT_SEL
Interrupt Status Clear (Write Only)
B8h
INT_EN
Interrupt Enable Register (Read/Write)
BCh
INT_SRC
Interrupt Source Indicatior(Read Only)
To control 82C55 ports, first the mode have to set up through the control register. To all setup, most
significant bit(MSB) is set to high “1” and write to the control register. If the MSB is “0”, it will be
command of PORTC. (For more information, refer 82C55 manual)
When the first time power is applied, all ports will be the input and operation modes will be 0.
(1) INT_STA (Interrupt Status)
Indicates the current interrupt device that requires. To appear in the status register will have to make
the handle. When the write operation, status bits are cleared.
INTERRUPT Status Register Bit Position & meaning
31
16
Reserved
Bit
Name
15 14 13 12 11 10 9
G
S14
Description
8
7
6
5
4
3
2
Status
Default Value
Reserved
‘0’
1
Reserved
‘0’
2
Reserved
‘0’
3
Reserved
‘0’
4
Reserved
‘0’
5
Reserved
‘0’
Differential RS232C interface
‘0’
7
Reserved
‘0’
8
Reserved
‘0’
9
Reserved
‘0’
10
Reserved
‘0’
UART
 2005 DAQ system, all rights reserved.
0
S0
0
6
1
http://www.daqsystem.com
Application Note (AN241)
PCI-FRM01 Register Level Application Guide
11
Interrupt
Reserved
‘0’
12
LVDS
Reserved
‘0’
13
Reserved
‘0’
14
Reserved
‘0’
15
Global
When any of the above interrupt sources
‘0’
need
the processing, it will be changed '1'.
31-16
Reserved
All ‘0’
For future use
For more information, refer AD5324 manual.
(2) INT_SEL
Select the Level Trigger and Edge Trigger of Interrup Input.
INTERRUPT Clear Register Bit Position & meaning
31
16 15 14 13 12 11 10 9
Reserved
R
C14
8
7
6
5
4
3
2
1
Status Clear
0
C0
If it is “0”, it is a Level Trigger. If it is “1”, it is a Rising Edge Trigger.
(3) INT_EN
Each interrupt source is to enable the interrupt.
INTERRUPT Enable Register Bit Position & meaning
31
16
15 14 13 12 11 10 9
Reserved
G
E14
8
7
6
5
4
3
2
1
Enable
0
E0
If each bit is ‘1’, the device interrupt for corresponding bit will be enabled.
The bit 15 is Global Interrupt Enable. This bit is set to '1' to enable all interrupts.
(4) INT_SRC
INT_STA appear on the register, the interrupt request output of the device is latched at the rising
edge of the signal. Thus, it is not Level Trigger, it is an indication of Edge Triggere.
So, it can be cleared and requested the interrupt. On the other hand, in the INT_SRN, it represents
current output signal state of the current device.
INTERRUPT Source Indicator Bit Position & meaning
31
15 14 13 12 11 10 9
Reserved
S14
 2005 DAQ system, all rights reserved.
8
7
6
5
Interrupt Source
4
3
2
1
0
S0
http://www.daqsystem.com
Application Note (AN241)
PCI-FRM01 Register Level Application Guide
7. LVDS(Camera Link) Interface Usage
LVDS(Low Voltage Differential Signal) Interface control
Function
LVDS
I/O Address
Offset
Register
Description
C0h
LVDS_DATA
LVDS Data register
C4h
LVDS_CMD
LVDS Command register
C8h
LVDS_CNT
LVDS Internal counter register
CCh
LVDS_STA
LVDS Status register
LVDS Data Register Bit Position & meaning
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9
D31
8
7
6
5
4
3
2
1
Data
0
D0
LVDS Command Register Bit Position & meaning
31
5
Reserved
Bit
Name
4
3
2
1
0
S
I
D
R
E
1
0
Description
Default
Value
‘0’
0
Enable
Used for simulation
1
Reset
‘0’
2
Data
‘0’
Enable
3
‘0’
Interrupt
Enable
4
‘0’
Start
LVDS Internal counter Register Bit Position & meaning
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9
P15
Pixel Counter
P0
L15
 2005 DAQ system, all rights reserved.
8
7
6
Line Counter
5
4
3
2
L0
http://www.daqsystem.com
Application Note (AN241)
PCI-FRM01 Register Level Application Guide
LVDS Status Register Bit Position & meaning
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9
V
H
R
Bit
LVDS Address
Name
I
F
L
R
D
Description
A10
8
7
6
5
4
3
2
PC Address
1
0
A0
Default
Value
10-0
PC address
Dual port ram address
11
Done
‘0’
12
Data
‘0’
Ready
13
Lvalid
‘0’
14
Fvalid
‘0’
15
Interrupt
‘0’
27-16
LVDS
Dual port ram address
address
28
Reserved
29
Data
‘0’
ready
30
Hsync
‘0’
31
Vsync
‘0’
 2005 DAQ system, all rights reserved.
http://www.daqsystem.com
Application Note (AN241)
PCI-FRM01 Register Level Application Guide
8. DIO(Digital Input/Output) Usage
The PCI-FRM01 has 16 Input port and 8 Output port at the Photo-coupler isolated DIO(Digital
Input/Output) function.
Function
DIO
I/O Address
Offset
Register
Description
D0h
Out Port
4Bit Photo-coupler output, 4Bit LVDS output Port
D4h
In Port
6Bit Photo-coupler input , 10Bit LVDS input Port
D8h
Reserved
For future use
DCh
Reserved
For future use
DIO Out Port Register Bit Position & Usage
31
4
7
6
5
Reserved
4
3
2
1
0
Used
Bits 3-0 are the Photo-coupler isolated Digital outputs, bits 7-4 are the LVDS outputs. Please refer to
the manual for the circuit configuration.
DIO In Port Register Bit Position & Usage
31
16 15 14 13 12 11 10 9
Reserved
8
7
6
5
4
3
2
1
0
Used
Bits 5-0 are the Photo-coupler isolated Digital Inputs, bits 15-8 are the LVDS Inputs. Please refer to
the manual for the circuit configuration.
 2005 DAQ system, all rights reserved.
http://www.daqsystem.com
Application Note (AN241)
PCI-FRM01 Register Level Application Guide
References
1. Specifications of the Camera Link Interface Standard for Digital Cameras and Frame Grabbers
-- PULNix America, Inc.
2. Channel Link Design Guide
-- National Semiconductor
3. PCI-EK01(A/B) User’s Manual
-- DAQ system
4. DS90CR285/286 chip manual
-- National Semiconductor
5. PCI-FRM01 User’s manual
-- DAQ system
 2005 DAQ system, all rights reserved.
http://www.daqsystem.com