TDA1311

INTEGRATED CIRCUITS

DATA SHEET

TDA1311A

Stereo Continuous Calibration DAC

(CC-DAC)

1995 Dec 18 Preliminary specification

Supersedes data of July 1993

File under Integrated Circuits, IC01

Philips Semiconductors

Stereo Continuous Calibration DAC

(CC-DAC)

Preliminary specification

TDA1311A

FEATURES

•

Voltage output

•

Space saving packages SO8 or DIP8

•

Low power consumption

•

Wide dynamic range (16-bit resolution)

•

Continuous Calibration (CC) concept

•

Easy application:

– single 4 to 5.5 V rail supply

– output current and bias current are proportional to the supply voltage

– integrated current-to-voltage converter

•

Fast settling time permits 2, 4 and 8

× oversampling

(serial input) or double-speed operation at

4

× oversampling

•

Internal bias current ensures maximum dynamic range

•

Wide operating temperature range (

−

40

°

C to +85

°

C)

•

Compatible with most current Japanese input formats: time multiplexed, two's complement, TTL

•

No zero-crossing distortion

•

Cost efficient.

GENERAL DESCRIPTION

The TDA1311A; AT is a voltage-driven digital-to-analog converter and is new generation of DAC devices which embodies the innovative technique of Continuous

Calibration (CC). The largest bit-currents are repeatedly generated by one single current reference source. This duplication is based upon an internal charge storage principle which has an accuracy insensitive to ageing, temperature matching and process variations.

The TDA1311A; AT is fabricated in a 1.0

µ m CMOS process and features an extremely low-power dissipation, small package size and easy application. Furthermore, the accuracy of the intrinsic high coarse-current combined with the implemented symmetrical offset decoding method preclude zero-crossing distortion and ensures high quality audio reproduction. Therefore, the CC-DAC is eminently suitable for use in (portable) digital audio equipment.

ORDERING INFORMATION

TYPE

NUMBER

TDA1311A

TDA1311AT

NAME

DIP8

SO8

PACKAGE

DESCRIPTION plastic dual in-line package; 8 leads (300 mil) plastic small outline package; 8 leads; body width 3.9 mm

VERSION

SOT97-1

SOT96-1

1995 Dec 18 2

Philips Semiconductors


(CC-DAC)

Preliminary specification

TDA1311A

QUICK REFERENCE DATA f t

SYMBOL

V

DD

I

DD

S/N cs

BR

BCK

TC

T

P tot

FS amb

PARAMETER supply voltage supply current

V

FS full scale output voltage

(THD+N)/S total harmonic distortion plus noise

CONDITIONS MIN.

V

DD

= 5 V at code 0000H

4

−

V

DD

= 5 V at 0 dB signal level at at

−

−

60 dB signal level

60 dB signal level;

A-weighted

1.8

−

−

−

−

−

−

A-weighted at code 0000H 86 signal-to-noise ratio at bipolar zero current settling time to

±

1

LSB input bit rate at data input clock frequency at clock input full scale temperature coefficient at analog outputs

(I

OL

; I

OR

) operating ambient temperature total power dissipation V

DD

= 5 V at code 0000H

−

−

−

−

−

−

40

TYP.

5

3.4

2.0

−

68

0.04

−

30

3

−

33

2

92

0.2

−

−

±

400

−

17

+85

30

MAX.

5.5

6.0

6

−

−

−

2.2

−

63

0.07

−

24

UNIT

V mA

% dB

% dB

V dB

% dB

− µ s

18.4

18.4

−

Mbits/s

MHz ppm

°

C mW

1995 Dec 18 3



(CC-DAC)

BLOCK DIAGRAM


TDA1311A handbook, full pagewidth

LEFT INPUT REGISTER

LEFT OUTPUT REGISTER

LEFT BIT SWITCHES VOL

6

I/V

IOL

11-BIT

PASSIVE

DIVIDER

32 (5-BIT)

CALIBRATED

CURRENT

SOURCES

1 CALIBRATED

SPARE SOURCE

BCK

WS

DATA

1

2

3

CONTROL

AND TIMING

RIGHT INPUT REGISTER

RIGHT OUTPUT REGISTER

RIGHT BIT SWITCHES

32 (5-BIT)

CALIBRATED

CURRENT

SOURCES

1 CALIBRATED

SPARE SOURCE

11-BIT

PASSIVE

DIVIDER

IOR

I/V

8

VOR

REFERENCE

SOURCE

TDA1311A

TDA1311AT

5

VDD

4

C2

100 nF

MBG858

GND

Fig.1 Block diagram.

PINNING

SYMBOL

BCK

WS

DATA

GND

V

DD

V

OL n.c.

V

OR

PIN

3

4

1

2

5

6

7

8

DESCRIPTION bit clock input word select input data input ground supply voltage left channel output not connected right channel output handbook, halfpage

BCK 1

GND 4

8 VOR

WS

DATA

2

3

TDA1311A

TDA1311AT

7

6 n.c.

VOL

5 VDD

MBG859

Fig.2 Pin configuration.

1995 Dec 18 4



(CC-DAC)


TDA1311A

FUNCTIONAL DESCRIPTION

The basic operation of the continuous calibration DAC is illustrated in Fig.3. The figure shows the calibration and operation cycle. During calibration of the MOS current source (see Fig.3a) transistor M1 is connected as a diode by applying a reference current. The voltage V gs

on the intrinsic gate-source capacitance C gs

of M1 is then determined by the transistor characteristics. After calibration of the drain current to the reference value I

REF

, the switch S1 is opened and S2 is switched to the other position (see Fig.3b). The gate-to-source voltage V gs

of

M1 is not changed because the charge on C gs

is preserved. Therefore, the drain current of M1 will still be equal to I

REF

and this exact duplicate of I

REF

is now available at the OUT terminal.

The 32 current sources and the spare current source of the

TDA1311A; AT are continuously calibrated (see Fig.1).

The spare current source is included to allow continuous converter operation. The output of one calibrated source is connected to an 11-bit binary current divider consisting of

2048 transistors.

A symmetrical offset decoding principle is incorporated that arranges the bit switching in such a way that the zero-crossing is performed only by switching the LSB currents.

The TDA1311A; AT (CC-DAC) accepts serial input data formats of 16-bit word length. Left and right data words are time multiplexed. The most significant bit (bit 1) must always be first. The input data format is shown in Figs 4 and 5.

With a HIGH level on the word select input (WS), data is placed in the left input register and with a LOW level on the

WS input, data is placed in the right input register (see

Fig.1). The data in the input registers are simultaneously latched in the output registers which control the bit switches.

An internal offset voltage V

OS

is added to the full scale output voltage V

FS

; V

OS

and V

FS

are proportional to V

DD

:

V

DD1

/V

DD2

= V

FS1

/V

FS2

= V

OS1

/V

OS2

.

handbook, full pagewidth out

S2

S1

Cgs Vgs

M1

(a)

Iref out

Iref Iref

S2

S1

Cgs

(b)

Vgs

M1

MBG860

(a) = calibration.

(b) = operation.

Fig.3 Calibration principle.

1995 Dec 18 5



(CC-DAC)


TDA1311A

LIMITING VALUES

In accordance with the Absolute Maximum Rating System (IEC 134).

SYMBOL

V

DD

T stg

T

XTAL

T amb

V es

PARAMETER supply voltage storage temperature maximum crystal temperature operating ambient temperature electrostatic handling

CONDITIONS note 1 note 2

MIN.

−

−

55

−

−

40

−

2000

−

200

MAX.

6.0

+150

+150

+85

+2000

+200

Note

1. Human body model: C = 100 pF, R = 1500

Ω

, 3 pulses positive and 3 pulses negative.

2. Machine model: C = 200 pF, L = 0.5

µ

H, R = 10

Ω

, 3 pulses positive and 3 pulses negative.

THERMAL RESISTANCE

SYMBOL

R th j-a

PARAMETER thermal resistance from junction to ambient in free air

DIL8

SO8

VALUE

100

210

V

°

C

°

C

°

C

V

V

UNIT

UNIT

K/W

K/W

QUALITY SPECIFICATION

In accordance with SNW-FQ-0611.

CHARACTERISTICS

V

DD

= 5 V; T amb

= 25

°

C; measured in Fig.1; unless otherwise specified.

SYMBOL PARAMETER CONDITIONS

Supply

V

DD

I

DD supply voltage supply current

Digital inputs; pins WS, BCK and DATA

|

I

IL

|

|

I

IH

| input leakage current LOW input leakage current HIGH f

BCK

BR clock frequency bit rate data input f

WS word select input frequency at code 0000H

V

V

I

I

= 0.8 V

= 2.4 V

MIN.

4.0

−

−

−

−

−

−

5.0

3.4

−

−

−

−

−

TYP.

5.5

6.0

10

MAX.

10

18.4

18.4

384

UNIT

V mA

µ

A

µ

A

MHz

Mbits/s kHz

1995 Dec 18 6



(CC-DAC)


TDA1311A

SYMBOL PARAMETER CONDITIONS MIN.

Timing (see Fig.4) t r t f t

CY t

BCKH t

BCKL t

SU;DAT t

HD:DAT t

HD:WS t

SU;WS rise time fall time bit clock cycle time bit clock pulse width HIGH bit clock pulse width LOW data set-up time data hold time to bit clock word select hold time word select set-up time

Analog outputs; pins V

OL

and V

OR

V

FS

TC

FS full-scale voltage full-scale temperature coefficient

1.8

−

V os

(THD+N)/S total harmonic distortion plus noise t cs

α cs

|δ

I

O

|

| t d

|

S/N offset voltage current settling time to channel separation

±

1 LSB unbalance between outputs time delay between outputs signal-to-noise ratio at bipolar zero

V

DD

= V

OL/ORmax

0.45

at 0 dB signal level; note 1

−

− at

−

60 dB signal level; note 1

− at

−

60 dB signal level;

A-weighted; note 1 at 0 dB signal level; f = 20 Hz to 20 kHz

−

−

−

−

−

− note 1

A-weighted at code 0000H

75

−

−

86

12

2

2

12

−

−

54

15

15

Note

1. Measured with 1 kHz sinewave generated at sampling rate of 192 kHz.

−

−

−

−

−

−

−

−

−

TYP.

2.0

±

400

0.50

−

68

0.04

−

30

3

−

33

2

−

65

0.05

0.2

80

0.2

±

0.2

92

12

12

−

−

−

−

−

−

−

MAX.

2.2

−

0.55

−

63

0.07

−

24

6

−

−

−

61

0.09

−

−

0.3

−

− ns ns ns ns ns ns ns ns ns

UNIT

V ppm dB

% dB

% dB

%

µ s dB dB

µ s dB

V dB

%

1995 Dec 18 7



(CC-DAC)


TDA1311A handbook, full pagewidth

WS tr

<

12 tBCKH

>

15 tf

<

12

RIGHT tBCKL

>

15

BCK tCY

>

54

DATA LSB tHD; WS

>

2

MSB

>

12 tSU; WS sample out

LEFT tSU; DAT

>

12 tHD; DAT

>

2

MBG861

Fig.4 Timing and input signals.

1995 Dec 18 8

DATA

BCK

WS sample out

MSB

LEFT

LSB MSB

RIGHT

LSB

MBG862

Fig.5 Format of input signals.



(CC-DAC)


TDA1311A

APPLICATION INFORMATION

Basic application example

A typical example of a CD-application with the TDA1311A; AT is shown in Fig.6. It features typical decoupling components and a third-order analog post-filter stage providing a line output.

handbook, full pagewidth

VDD

10

Ω

47

µ

F

100 nF

5

8

BCK

WS

DATA

1

2

TDA1311A

TDA1311AT

3

7

6

4

420 pF

22 k

Ω

22 k

Ω

2.2 nF 100 pF

420 pF

22 k

Ω

22 k

Ω

2.2 nF 100 pF

MBG863

Fig.6 Example of a 3rd order filter application.

Attention to printed circuit board layout

The TDA1311A and even more so the TDA1311AT offers great ease in designing-in to printed-circuit boards due to its small size and low pin count. The TDA1311A; AT being a mixed-signal IC in CMOS, some attention needs to be paid to layout and topology of the application PCB.

Following some basic rules will yield the desired performance. The most important considerations are:

1. Supply: care should be taken to supply the

TDA1311A; AT with a clean, noiseless V

DD

, for a good noise performance of the analog parts of the DAC.

Supply purity can easily be achieved by using an

RC-filtered supply.

2. Grounding: preferably a ground plane should be used, in order to have a low-impedance return available at any point in the layout. It is advantageous to make a partitioning of the ground plane according to the nature of the expected return currents (digital input returns separate from supply returns and separate from the analog section).

3. Topology: the capacitor decoupling high-frequency supply interference from V

DD

to GND should be placed as close as is physically possible to the IC body, ensuring a low-inductance path to ground. The digital input conductors may be shielded by ground leads running alongside. The placement of a passive ground plane underside the entire IC surface gives `free` additional decoupling from the IC body to ground as well as providing a shield between the digital input pins and the analog output pins.

Figure 7 shows recommended layouts for printed-circuit boards for the SO8 and DIL8 versions respectively. Both layouts use a single-interconnect layer.

1995 Dec 18 10



(CC-DAC) handbook, full pagewidth


TDA1311A

C1

C2

V DD

R

V DD

MSA739

Fig.7 Recommended printed-circuit board layouts.

Interface examples

The following figures (Figs 8 to 14) show examples of connections to commonly used decoder and digital filter ICs. The digital interface part is shown only, for clarity. The diagrams are for guidance purposes only - no guarantee for industrial exploitation is implied.

1995 Dec 18 handbook, halfpage

BCKO

15

SM5807 LRCOn

14

1

DOUT

12

MBG864

1

BCK

2

WS

TDA1311A

TDA1311AT

3

DATA remark: SCSLn

−

signal SM5807 both "L" and "H" supported by TDA1311A and TDA1311AT

Fig.8 NPC SM5807 digital filter (4FS).

11



(CC-DAC) handbook, halfpage

DOL

14

SM5840

(1)

DOR

13

BCKO

12

MBG865

1

BCK

2

WS

TDA1311A

TDA1311AT

3

DATA

OMODn pin 19: "L" for 4FS operation

(1)

versions A/B/G

Fig.9 NPC SM5840 digital filter (4FS).

handbook, halfpage

C2IOn

76

CXD1125 LRCK

80

DATA

78

MBG866

1

BCK

2

WS

TDA1311A

TDA1311AT

3

DATA

MODE SELECT:

MD1 pin 55: "L"

MD2 pin 56: "L" to use DOTX function

MD3 pin 57: "H"

PSSL pin 59: "L"

SLOB pin 58: "L"

Fig.10 Sony CXD1125 decoder (1FS).


TDA1311A


9

BCK C2IOn

3

7

LRCK CXD1125 LRD

1

8

DATA DATA

4

MBG867

1

BCK

2

WS

TDA1311A

TDA1311AT

3

DATA remark: CXD1162 input connectable to CXD1125 in the same way as for TDA1311A; AT to CXD1125

Fig.11 Sony CXD1162 digital filter (4FS).

12



(CC-DAC) handbook, halfpage

DA14

76

CXD1135 LRCK

80

DA16

78

MBG868

1

BCK

2

WS

TDA1311A

TDA1311AT

3

DATA

MODE SELECT:

MD1 pin 55: "L"

MD2 pin 56: "L" to use DOTX function

MD3 pin 57: "H" for 1FS; "L" for 2FS

PSSL pin 59: "L"

SLOB pin 58: "L"

Fig.12 Sony CXD1135 decoder (1FS) and digital filter (2FS).


TDA1311A handbook, halfpage

DSCK

74

M50423 LRCK

75

DO1

72

MBG869

1

BCK

2

WS

TDA1311A

TDA1311AT

3

DATA

MODE SELECT:

DOBSEL pin 7: "L"

DASEL1 pin 8: "H"

DASEL2 pin 9: "L"

DASEL3 pin 10: "H"

DASEL4 pin 11: "L"

Fig.13 Mitsubishi M50423 decoder (1FS) and digital filter (4FS).


DACLK

35

LC7863 LRCLK

30

DFOUT

34

MBG870

1

BCK

2

WS

TDA1311A

TDA1311AT

3

DATA

MODE SELECT:

DFOFF pin 27: "L"

MSBF pin 38: "H"

Fig.14 Sanyo LC7863 decoder (1FS).

13



(CC-DAC)


TDA1311A

Evaluation of audio parameters

The following measurement graphs are performed on singular engineering samples; therefore no guarantee of typical parameter values is implied. Measurement conditions are typical, as stated in the section Characteristics, unless otherwise indicated. The normal measurement set-up includes a 20 kHz band-limiting filter for bandwidth definition, and an A-weighting filter where indicated.

MBG871

−

100 handbook, halfpage

THD

(dB)

−

80

−

60

−

40

−

20

0

−

100

−

80

−

60

−

40

−

20 signal level (dB)

0

Fig.15 Total harmonic distortion plus noise as a function of signal level (4FS).

−


THD

(dB)

−

40

(1)

MBG873

10

THD

(%)

1

−

60 0.1

(2)

−

80 0.01

−

100

10 10

2

10

3

10

4

10 frequency (Hz)

5

0.001

(1) Measured including all distortion plus noise at a signal level of

−

60 dB.

(2) Measured including all distortion plus noise at a signal level of 0 dB.

Fig.16 Total harmonic distortion plus noises as a function of frequency (4FS).

1995 Dec 18 14



(CC-DAC)


−


THD

(dB)

−

60

(2)

−

70

(3)

MBG872

20

THD

(%)

0

(1)

−

20

−

80

3 4 5 VDD (V) 6

−

40

(1) Measured including all distortion plus noise within the specified operating supply voltage range.

(2) Measured including all distortion plus noise outside the specified operating supply voltage range.

(3) V

FS

relative to nominal.

Fig.17 Total harmonic distortion plus noise as a function of supply voltage (4FS).

TDA1311A

1995 Dec 18 15



(CC-DAC)

PACKAGE OUTLINES

DIP8: plastic dual in-line package; 8 leads (300 mil)


TDA1311A

SOT97-1

D

L

Z

8 b e

A

2 A

A

1 b

1 w M

5 b

2 pin 1 index

E c

M

E

M

H

1 4

0 5 scale

10 mm

DIMENSIONS (inch dimensions are derived from the original mm dimensions)

UNIT

A max.

A min.

A max.

b b

1 b

2 c D

(1)

E

(1) mm inches

4.2

0.17

0.51

0.020

3.2

0.13

1.73

1.14

0.068

0.045

0.53

0.38

0.021

0.015

1.07

0.89

0.042

0.035

0.36

0.23

0.014

0.009

9.8

9.2

0.39

0.36

6.48

6.20

0.26

0.24

Note

1. Plastic or metal protrusions of 0.25 mm maximum per side are not included.

OUTLINE

VERSION

SOT97-1

IEC

050G01

REFERENCES

JEDEC EIAJ

MO-001AN e

2.54

0.10

e

1

7.62

0.30

L

3.60

3.05

0.14

0.12

M

E

8.25

7.80

0.32

0.31

M

H

10.0

8.3

0.39

0.33

w

0.254

0.01

Z

(1) max.

1.15

0.045

EUROPEAN

PROJECTION

ISSUE DATE

92-11-17

95-02-04

1995 Dec 18 16



(CC-DAC)

SO8: plastic small outline package; 8 leads; body width 3.9 mm


TDA1311A

SOT96-1

8

Z y pin 1 index

1 e

D E A

X c

H

E

5 b p

4 w M

A

2

A

1

L

L p detail X

Q

θ

A v M A

0 2.5

scale

5 mm

DIMENSIONS (inch dimensions are derived from the original mm dimensions)

UNIT

A max.

A

1

A

2

A

3 b p c D

(1)

E

(2) e H

E mm inches

1.75

0.069

0.25

0.10

0.010

0.004

1.45

1.25

0.057

0.049

0.25

0.01

0.49

0.36

0.019

0.014

0.25

0.19

0.0100

0.0075

5.0

4.8

0.20

0.19

4.0

3.8

0.16

0.15

1.27

0.050

6.2

5.8

0.244

0.228

L

1.05

0.041

L p

Q

1.0

0.4

0.039

0.016

0.7

0.6

0.028

0.024

v

0.25

0.01

w y Z

(1)

0.25

0.01

0.1

0.004

0.7

0.3

0.028

0.012

Notes



OUTLINE

VERSION

SOT96-1

IEC

076E03S

REFERENCES

JEDEC EIAJ

MS-012AA

EUROPEAN

PROJECTION

ISSUE DATE

95-02-04

97-05-22

θ

8 o

0 o

1995 Dec 18 17



(CC-DAC)


TDA1311A

SOLDERING

Introduction

There is no soldering method that is ideal for all IC packages. Wave soldering is often preferred when through-hole and surface mounted components are mixed on one printed-circuit board. However, wave soldering is not always suitable for surface mounted ICs, or for printed-circuits with high population densities. In these situations reflow soldering is often used.

This text gives a very brief insight to a complex technology.

A more in-depth account of soldering ICs can be found in our “IC Package Databook” (order code 9398 652 90011).

DIP

S OLDERING BY DIPPING OR BY WAVE

The maximum permissible temperature of the solder is

260

°

C; solder at this temperature must not be in contact with the joint for more than 5 seconds. The total contact time of successive solder waves must not exceed

5 seconds.

The device may be mounted up to the seating plane, but the temperature of the plastic body must not exceed the specified maximum storage temperature (T stg max

). If the printed-circuit board has been pre-heated, forced cooling may be necessary immediately after soldering to keep the temperature within the permissible limit.

Several techniques exist for reflowing; for example, thermal conduction by heated belt. Dwell times vary between 50 and 300 seconds depending on heating method. Typical reflow temperatures range from

215 to 250

°

C.

Preheating is necessary to dry the paste and evaporate the binding agent. Preheating duration: 45 minutes at

45

°

C.

W AVE SOLDERING

Wave soldering techniques can be used for all SO packages if the following conditions are observed:

•

A double-wave (a turbulent wave with high upward pressure followed by a smooth laminar wave) soldering technique should be used.

•

The longitudinal axis of the package footprint must be parallel to the solder flow.

•

The package footprint must incorporate solder thieves at the downstream end.

During placement and before soldering, the package must be fixed with a droplet of adhesive. The adhesive can be applied by screen printing, pin transfer or syringe dispensing. The package can be soldered after the adhesive is cured.

Maximum permissible solder temperature is 260

°

C, and maximum duration of package immersion in solder is

10 seconds, if cooled to less than 150

°

C within

6 seconds. Typical dwell time is 4 seconds at 250

°

C.

A mildly-activated flux will eliminate the need for removal of corrosive residues in most applications.

R EPAIRING SOLDERED JOINTS

Apply a low voltage soldering iron (less than 24 V) to the lead(s) of the package, below the seating plane or not more than 2 mm above it. If the temperature of the soldering iron bit is less than 300

°

C it may remain in contact for up to 10 seconds. If the bit temperature is between 300 and 400

°

C, contact may be up to 5 seconds.

SO

R EFLOW SOLDERING

Reflow soldering techniques are suitable for all SO packages.

Reflow soldering requires solder paste (a suspension of fine solder particles, flux and binding agent) to be applied to the printed-circuit board by screen printing, stencilling or pressure-syringe dispensing before package placement.

R EPAIRING SOLDERED JOINTS

Fix the component by first soldering two diagonallyopposite end leads. Use only a low voltage soldering iron

(less than 24 V) applied to the flat part of the lead. Contact time must be limited to 10 seconds at up to 300

°

C. When using a dedicated tool, all other leads can be soldered in one operation within 2 to 5 seconds between

270 and 320

°

C.

1995 Dec 18 18



(CC-DAC)


TDA1311A

DEFINITIONS

Data sheet status

Objective specification


Product specification

This data sheet contains target or goal specifications for product development.

This data sheet contains preliminary data; supplementary data may be published later.

This data sheet contains final product specifications.

Limiting values

Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended periods may affect device reliability.

Application information

Where application information is given, it is advisory and does not form part of the specification.

LIFE SUPPORT APPLICATIONS

These products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. Philips customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting from such improper use or sale.

1995 Dec 18 19

Philips Semiconductors – a worldwide company

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SCD47 © Philips Electronics N.V. 1995

All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner.

The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license under patent- or other industrial or intellectual property rights.

Printed in The Netherlands

513061/50/02/pp20

Document order number:

Date of release: 1995 Dec 18

9397 750 00532

TDA1311

INTEGRATED CIRCUITS

DATA SHEET

Stereo Continuous Calibration DAC

(CC-DAC)

Stereo Continuous Calibration DAC

(CC-DAC)

TDA1311A

Philips Semiconductors – a worldwide company

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