Chapter 1 MC9S12C and MC9S12GC Device Overview - Sun-Pec

Chapter 1
MC9S12C and MC9S12GC Device Overview (MC9S12C128)
1.1
Introduction
The MC9S12C-Family / MC9S12GC-Family are 48/52/80 pin Flash-based MCU families, which deliver
the power and flexibility of the 16-bit core to a whole new range of cost and space sensitive, general
purpose industrial and automotive network applications. All MC9S12C-Family / MC9S12GC-Family
members feature standard on-chip peripherals including a 16-bit central processing unit (CPU12), up to
128K bytes of Flash EEPROM, up to 4K bytes of RAM, an asynchronous serial communications interface
(SCI), a serial peripheral interface (SPI), an 8-channel 16-bit timer module (TIM), a 6-channel 8-bit pulse
width modulator (PWM), an 8-channel, 10-bit analog-to-digital converter (ADC).
The MC9S12C128-Family members also feature a CAN 2.0 A, B software compatible module
(MSCAN12).
All MC9S12C-Family / MC9S12GC-Family devices feature full 16-bit data paths throughout. The
inclusion of a PLL circuit allows power consumption and performance to be adjusted to suit operational
requirements. In addition to the I/O ports available in each module, up to 10 dedicated I/O port bits are
available with wake-up capability from stop or wait mode. The devices are available in 48-, 52-, and 80pin QFP packages, with the 80-pin version pin compatible to the HCS12 A, B, and D Family derivatives.
1.1.1
•
•
Features
16-bit HCS12 core:
— HCS12 CPU
– Upward compatible with M68HC11 instruction set
– Interrupt stacking and programmer’s model identical to M68HC11
– Instruction queue
– Enhanced indexed addressing
— MMC (memory map and interface)
— INT (interrupt control)
— BDM (background debug mode)
— DBG12 (enhanced debug12 module, including breakpoints and change-of-flow trace buffer)
— MEBI (multiplexed expansion bus interface) available only in 80-pin package version
Wake-up interrupt inputs:
— Up to 12 port bits available for wake up interrupt function with digital filtering
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Chapter 1 MC9S12C and MC9S12GC Device Overview (MC9S12C128)
•
•
•
•
1.1.2
Operating frequency:
— 32MHz equivalent to 16MHz bus speed for single chip
— 32MHz equivalent to 16MHz bus speed in expanded bus modes
— Option of 9S12C Family: 50MHz equivalent to 25MHz bus speed
— All 9S12GC Family members allow a 50MHz operating frequency.
Internal 2.5V regulator:
— Supports an input voltage range from 2.97V to 5.5V
— Low power mode capability
— Includes low voltage reset (LVR) circuitry
— Includes low voltage interrupt (LVI) circuitry
48-pin LQFP, 52-pin LQFP, or 80-pin QFP package:
— Up to 58 I/O lines with 5V input and drive capability (80-pin package)
— Up to 2 dedicated 5V input only lines (IRQ, XIRQ)
— 5V 8 A/D converter inputs and 5V I/O
Development support:
— Single-wire background debug™ mode (BDM)
— On-chip hardware breakpoints
— Enhanced DBG12 debug features
Modes of Operation
User modes (expanded modes are only available in the 80-pin package version).
• Normal and emulation operating modes:
— Normal single-chip mode
— Normal expanded wide mode
— Normal expanded narrow mode
— Emulation expanded wide mode
— Emulation expanded narrow mode
• Special operating modes:
— Special single-chip mode with active background debug mode
— Special test mode (Freescale use only)
— Special peripheral mode (Freescale use only)
• Low power modes:
— Stop mode
— Pseudo stop mode
— Wait mode
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Chapter 1 MC9S12C and MC9S12GC Device Overview (MC9S12C128)
1.2
1.2.1
Memory Map and Registers
Device Memory Map
Table 1-1 shows the device register map after reset. Figure 1-2 through Figure 1-6 illustrate the full device
memory map.
Table 1-1. Device Register Map Overview
Address
0x0000–0x0017
Module
Size
Core (ports A, B, E, modes, inits, test)
24
0x0018
Reserved
1
0x0019
Voltage regulator (VREG)
1
0x001A–0x001B
Device ID register
2
0x001C–0x001F
Core (MEMSIZ, IRQ, HPRIO)
4
0x0020–0x002F
Core (DBG)
16
0x0030–0x0033
Core (PPAGE(1))
4
0x0034–0x003F
Clock and reset generator (CRG)
12
0x0040–0x006F
Standard timer module (TIM)
48
0x0070–0x007F
Reserved
16
0x0080–0x009F
Analog-to-digital converter (ATD)
32
0x00A0–0x00C7
Reserved
40
0x00C8–0x00CF Serial communications interface (SCI)
8
0x00D0–0x00D7
8
Reserved
0x00D8–0x00DF Serial peripheral interface (SPI)
8
0x00E0–0x00FF
Pulse width modulator (PWM)
32
0x0100–0x010F
Flash control register
16
0x0110–0x013F
Reserved
48
(MSCAN)(2)
0x0140–0x017F
Scalable controller area network
0x0180–0x023F
Reserved
192
0x0240–0x027F
Port integration module (PIM)
64
64
0x0280–0x03FF Reserved
384
1. External memory paging is not supported on this device (Section 1.7.1, “PPAGE”).
2. Not available on MC9S12GC Family devices
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Chapter 1 MC9S12C and MC9S12GC Device Overview (MC9S12C128)
1.2.2
Detailed Register Map
The detailed register map of the MC9S12C128
is listed in address order below.
0x0000–0x000F
Address
Name
0x0000
PORTA
0x0001
PORTB
0x0002
DDRA
0x0003
DDRB
0x0004
Reserved
0x0005
Reserved
0x0006
Reserved
0x0007
Reserved
0x0008
PORTE
0x0009
DDRE
0x000A
PEAR
0x000B
MODE
0x000C
PUCR
0x000D
RDRIV
0x000E
EBICTL
0x000F
Reserved
Freescale Semiconductor
MEBI Map 1 of 3 (HCS12 Multiplexed External Bus Interface)
Bit 7
Read:
Bit 7
Write:
Read:
Bit 7
Write:
Read:
Bit 7
Write:
Read:
Bit 7
Write:
Read:
0
Write:
Read:
0
Write:
Read:
0
Write:
Read:
0
Write:
Read:
Bit 7
Write:
Read:
Bit 7
Write:
Read:
NOACCE
Write:
Read:
MODC
Write:
Read:
PUPKE
Write:
Read:
RDPK
Write:
Read:
0
Write:
Read:
0
Write:
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
6
5
4
3
2
1
Bit 0
6
5
4
3
2
1
Bit 0
6
5
4
3
2
1
Bit 0
6
5
4
3
2
1
Bit 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
6
5
4
3
2
Bit 1
Bit 0
6
5
4
3
Bit 2
0
0
PIPOE
NECLK
LSTRE
RDWE
0
0
EMK
EME
PUPBE
PUPAE
RDPB
RDPA
0
MODB
MODA
0
0
0
0
0
0
0
0
0
IVIS
0
0
0
0
0
0
0
0
0
0
0
0
0
PUPEE
RDPE
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Chapter 1 MC9S12C and MC9S12GC Device Overview (MC9S12C128)
1.2.3
Part ID Assignments
The part ID is located in two 8-bit registers PARTIDH and PARTIDL (addresses 0x001A and ox001B after
reset). The read-only value is a unique part ID for each revision of the chip. Table 1-3 shows the assigned
part ID numbers for production mask sets.
Table 1-3. Assigned Part ID Numbers
Device
Mask Set Number
Part ID(1)
MC9S12C32
1L45J
$3300
MC9S12C32
2L45J
$3302
MC9S12C32
1M34C
$3311
MC9S12GC16
2L45J
$3302
MC9S12GC32
2L45J
$3302
MC9S12GC32
1M34C
$3311
MC9S12C64,MC9S12C96,MC9S12C128
2L09S
$3102
MC9S12GC64,MC9S12GC96,MC9S12GC128
2L09S
$3102
MC9S12C64,MC9S12C96,MC9S12C128
0M66G
$3103
MC9S12GC64,MC9S12GC96,MC9S12GC128
0M66G
1. The coding is as follows:
Bit 15–12: Major family identifier
Bit 11–8: Minor family identifier
Bit 7–4: Major mask set revision number including FAB transfers
Bit 3–0: Minor — non full — mask set revision
$3103
The device memory sizes are located in two 8-bit registers MEMSIZ0 and MEMSIZ1 (addresses 0x001C
and 0x001D after reset). Table 1-4 shows the read-only values of these registers. Refer to Module Mapping
and Control (MMC) Block Guide for further details.
Table 1-4. Memory Size Registers
Device
MC9S12GC16
MC9S12C32, MC9S12GC32
MC9S12C64, MC9S12GC64
MC9S12C96,MC9S12GC96
MC9S12C128, MC9S12GC128
44
Register Name
Value
MEMSIZ0
$00
MEMSIZ1
$80
MEMSIZ0
$00
MEMSIZ1
$80
MEMSIZ0
$01
MEMSIZ1
$C0
MEMSIZ0
$01
MEMSIZ1
$C0
MEMSIZ0
$01
MEMSIZ1
$C0
MC9S12C-Family / MC9S12GC-Family
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Chapter 1 MC9S12C and MC9S12GC Device Overview (MC9S12C128)
1.3.2
Signal Properties Summary
Table 1-5. Signal Properties
Pin Name
Function 1
EXTAL
48
Pin Name
Function 2
—
Pin Name
Function 3
Power
Domain
—
VDDPLL
Internal Pull
Resistor
Description
CTRL
Reset
State
NA
NA
Oscillator pins
XTAL
—
—
VDDPLL
NA
NA
RESET
—
—
VDDX
None
None
External reset pin
XFC
—
—
VDDPLL
NA
NA
PLL loop filter pin
TEST
VPP
—
VSSX
NA
NA
Test pin only
BKGD
MODC
TAGHI
VDDX
Up
Up
Background debug, mode pin, tag signal high
PE7
NOACC
XCLKS
VDDX
PUCR
Up
Port E I/O pin, access, clock select
PE6
IPIPE1
MODB
VDDX
While RESET
pin is low: Down
Port E I/O pin and pipe status
PE5
IPIPE0
MODA
VDDX
While RESET
pin is low: Down
Port E I/O pin and pipe status
PE4
ECLK
—
VDDX
PUCR
Mode
Dep(1)
Port E I/O pin, bus clock output
PE3
LSTRB
TAGLO
VDDX
PUCR
Mode
Dep1
Port E I/O pin, low strobe, tag signal low
PE2
R/W
—
VDDX
PUCR
Mode
Dep1
Port E I/O pin, R/W in expanded modes
PE1
IRQ
—
VDDX
PUCR
Up
PE0
XIRQ
—
VDDX
PUCR
Up
PA[7:3]
ADDR[15:1/
DATA[15:1]
—
VDDX
PUCR
Disabled
PA[2:1]
ADDR[10:9/
DATA[10:9]
—
VDDX
PUCR
Disabled
PA[0]
ADDR[8]/
DATA[8]
—
VDDX
PUCR
Disabled
PB[7:5]
ADDR[7:5]/
DATA[7:5]
—
VDDX
PUCR
Disabled
PB[4]
ADDR[4]/
DATA[4]
—
VDDX
PUCR
Disabled
PB[3:0]
ADDR[3:0]/
DATA[3:0]
—
VDDX
PUCR
Disabled
PAD[7:0]
AN[7:0]
—
VDDA
PP[7]
KWP[7]
—
VDDX
PERP/
PPSP
Disabled
PP[6]
KWP[6]
ROMCTL
VDDX
PERP/
PPSP
Disabled
PP[5]
KWP[5]
PW5
VDDX
PERP/
PPSP
Disabled
PP[4:3]
KWP[4:3]
PW[4:3]
VDDX
PERP/
PPSP
Disabled
Port E input, external interrupt pin
Port E input, non-maskable interrupt pin
Port A I/O pin and multiplexed address/data
Port A I/O pin and multiplexed address/data
Port A I/O pin and multiplexed address/data
Port B I/O pin and multiplexed address/data
Port B I/O pin and multiplexed address/data
Port B I/O pin and multiplexed address/data
PERAD/P
Port AD I/O pins and ATD inputs
Disabled
PSAD
Port P I/O pins and keypad wake-up
Port P I/O pins, keypad wake-up, and ROMON
enable.
Port P I/O pin, keypad wake-up, PW5 output
Port P I/O pin, keypad wake-up, PWM output
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Chapter 1 MC9S12C and MC9S12GC Device Overview (MC9S12C128)
1.3.4
1.3.4.1
Detailed Signal Descriptions
EXTAL, XTAL — Oscillator Pins
EXTAL and XTAL are the crystal driver and external clock pins. On reset all the device clocks are derived
from the EXTAL input frequency. XTAL is the crystal output.
1.3.4.2
RESET — External Reset Pin
RESET is an active low bidirectional control signal that acts as an input to initialize the MCU to a known
start-up state. It also acts as an open-drain output to indicate that an internal failure has been detected in
either the clock monitor or COP watchdog circuit. External circuitry connected to the RESET pin should
not include a large capacitance that would interfere with the ability of this signal to rise to a valid logic one
within 32 ECLK cycles after the low drive is released. Upon detection of any reset, an internal circuit
drives the RESET pin low and a clocked reset sequence controls when the MCU can begin normal
processing.
1.3.4.3
TEST / VPP — Test Pin
This pin is reserved for test and must be tied to VSS in all applications.
1.3.4.4
XFC — PLL Loop Filter Pin
Dedicated pin used to create the PLL loop filter. See CRG BUG for more detailed information.PLL loop
filter. Please ask your Motorola representative for the interactive application note to compute PLL loop
filter elements. Any current leakage on this pin must be avoided.
XFC
R0
CP
MCU
CS
VDDPLL
VDDPLL
Figure 1-10. PLL Loop Filter Connections
1.3.4.5
BKGD / TAGHI / MODC — Background Debug, Tag High, and Mode Pin
The BKGD / TAGHI / MODC pin is used as a pseudo-open-drain pin for the background debug
communication. In MCU expanded modes of operation when instruction tagging is on, an input low on
this pin during the falling edge of E-clock tags the high half of the instruction word being read into the
instruction queue. It is also used as a MCU operating mode select pin at the rising edge during reset, when
the state of this pin is latched to the MODC bit.
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Chapter 1 MC9S12C and MC9S12GC Device Overview (MC9S12C128)
1.3.4.27
PS[3:2] — Port S I/O Pins [3:2]
PS3 and PS2 are general purpose input or output pins. These pins are not available in the 48- / 52-pin
package versions.
1.3.4.28
PS1 / TXD — Port S I/O Pin 1
PS1 is a general purpose input or output pin and the transmit pin, TXD, of serial communication interface
(SCI).
1.3.4.29
PS0 / RXD — Port S I/O Pin 0
PS0 is a general purpose input or output pin and the receive pin, RXD, of serial communication interface
(SCI).
1.3.4.30
PT[7:5] / IOC[7:5] — Port T I/O Pins [7:5]
PT7–PT5 are general purpose input or output pins. They can also be configured as the timer system input
capture or output compare pins IOC7-IOC5.
1.3.4.31
PT[4:0] / IOC[4:0] / PW[4:0]— Port T I/O Pins [4:0]
PT4–PT0 are general purpose input or output pins. They can also be configured as the timer system input
capture or output compare pins IOC[n] or as the PWM outputs PW[n].
1.3.5
1.3.5.1
Power Supply Pins
VDDX,VSSX — Power and Ground Pins for I/O Drivers
External power and ground for I/O drivers. Bypass requirements depend on how heavily the MCU pins are
loaded.
1.3.5.2
VDDR, VSSR — Power and Ground Pins for I/O Drivers and for Internal
Voltage Regulator
External power and ground for the internal voltage regulator. Connecting VDDR to ground disables the
internal voltage regulator.
1.3.5.3
VDD1, VDD2, VSS1, VSS2 — Internal Logic Power Pins
Power is supplied to the MCU through VDD and VSS. This 2.5V supply is derived from the internal voltage
regulator. There is no static load on those pins allowed. The internal voltage regulator is turned off, if VDDR
is tied to ground.
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1.4
System Clock Description
The clock and reset generator provides the internal clock signals for the core and all peripheral modules.
Figure 1-14 shows the clock connections from the CRG to all modules. Consult the CRG Block User
Guide for details on clock generation.
S12_CORE
Core Clock
Flash
RAM
TIM
ATD
PIM
EXTAL
SCI
Bus Clock
CRG
Oscillator Clock
SPI
MSCAN
Not on 9S12GC
XTAL
VREG
TPM
Figure 1-14. Clock Connections
1.5
Modes of Operation
Eight possible modes determine the device operating configuration. Each mode has an associated default
memory map and external bus configuration controlled by a further pin.
Three low power modes exist for the device.
1.5.1
Chip Configuration Summary
The operating mode out of reset is determined by the states of the MODC, MODB, and MODA pins during
reset. The MODC, MODB, and MODA bits in the MODE register show the current operating mode and
provide limited mode switching during operation. The states of the MODC, MODB, and MODA pins are
latched into these bits on the rising edge of the reset signal. The ROMCTL signal allows the setting of the
ROMON bit in the MISC register thus controlling whether the internal Flash is visible in the memory map.
ROMON = 1 mean the Flash is visible in the memory map. The state of the ROMCTL pin is latched into
the ROMON bit in the MISC register on the rising edge of the reset signal.
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Chapter 1 MC9S12C and MC9S12GC Device Overview (MC9S12C128)
The security byte resides in a portion of the Flash array.
Check the Flash Block User Guide for more details on the security configuration.
1.5.2.2
1.5.2.2.1
Operation of the Secured Microcontroller
Normal Single Chip Mode
This will be the most common usage of the secured part. Everything will appear the same as if the part was
not secured with the exception of BDM operation. The BDM operation will be blocked.
1.5.2.2.2
Executing from External Memory
The user may wish to execute from external space with a secured microcontroller. This is accomplished
by resetting directly into expanded mode. The internal FLASH will be disabled. BDM operations will be
blocked.
1.5.2.3
Unsecuring the Microcontroller
In order to unsecure the microcontroller, the internal FLASH must be erased. This can be done through an
external program in expanded mode or via a sequence of BDM commands. Unsecuring is also possible via
the Backdoor Key Access. Refer to Flash Block Guide for details.
Once the user has erased the FLASH, the part can be reset into special single chip mode. This invokes a
program that verifies the erasure of the internal FLASH. Once this program completes, the user can erase
and program the FLASH security bits to the unsecured state. This is generally done through the BDM, but
the user could also change to expanded mode (by writing the mode bits through the BDM) and jumping to
an external program (again through BDM commands). Note that if the part goes through a reset before the
security bits are reprogrammed to the unsecure state, the part will be secured again.
1.5.3
Low-Power Modes
The microcontroller features three main low power modes. Consult the respective Block User Guide for
information on the module behavior in stop, pseudo stop, and wait mode. An important source of
information about the clock system is the Clock and Reset Generator User Guide (CRG).
1.5.3.1
Stop
Executing the CPU STOP instruction stops all clocks and the oscillator thus putting the chip in fully static
mode. Wake up from this mode can be done via reset or external interrupts.
1.5.3.2
Pseudo Stop
This mode is entered by executing the CPU STOP instruction. In this mode the oscillator is still running
and the real time interrupt (RTI) or watchdog (COP) sub module can stay active. Other peripherals are
turned off. This mode consumes more current than the full stop mode, but the wake up time from this mode
is significantly shorter.
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Chapter 1 MC9S12C and MC9S12GC Device Overview (MC9S12C128)
1.6.2
Resets
Resets are a subset of the interrupts featured in Table 1-9. The different sources capable of generating a
system reset are summarized in Table 1-10. When a reset occurs, MCU registers and control bits are
changed to known start-up states. Refer to the respective module Block User Guides for register reset
states.
1.6.2.1
Reset Summary Table
Table 1-10. Reset Summary
1.6.2.2
Reset
Priority
Source
Vector
Power-on Reset
1
CRG module
0xFFFE, 0xFFFF
External Reset
1
RESET pin
0xFFFE, 0xFFFF
Low Voltage Reset
1
VREG module
0xFFFE, 0xFFFF
Clock Monitor Reset
2
CRG module
0xFFFC, 0xFFFD
COP Watchdog Reset
3
CRG module
0xFFFA, 0xFFFB
Effects of Reset
When a reset occurs, MCU registers and control bits are changed to known start-up states. Refer to the
respective module Block User Guides for register reset states. Refer to the HCS12 Multiplexed External
Bus Interface (MEBI) Block Guide for mode dependent pin configuration of port A, B and E out of reset.
Refer to the PIM Block User Guide for reset configurations of all peripheral module ports.
Refer to Figure 1-2 to Figure 1-6 footnotes for locations of the memories depending on the operating mode
after reset.
The RAM array is not automatically initialized out of reset.
NOTE
For devices assembled in 48-pin or 52-pin LQFP packages all non-bonded
out pins should be configured as outputs after reset in order to avoid current
drawn from floating inputs. Refer to Table 1-5 for affected pins.
1.7
1.7.1
Device Specific Information and Module Dependencies
PPAGE
External paging is not supported on these devices. In order to access the 16K flash blocks in the address
range 0x8000–0xBFFF the PPAGE register must be loaded with the corresponding value for this range.
Refer to Table 1-11 for device specific page mapping.
For all devices Flash Page 3F is visible in the 0xC000–0xFFFF range if ROMON is set. For all devices
(except MC9S12GC16) Page 3E is also visible in the 0x4000–0x7FFF range if ROMHM is cleared and
ROMON is set. For all devices apart from MC9S12C32 Flash Page 3D is visible in the 0x0000–0x3FFF
range if ROMON is set...
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Chapter 1 MC9S12C and MC9S12GC Device Overview (MC9S12C128)
1.7.4
VREGEN
The VREGEN input mentioned in the VREG section is device internal, connected internally to VDDR.
1.7.5
VDD1, VDD2, VSS1, VSS2
In the 80-pin QFP package versions, both internal VDD and VSS of the 2.5V domain are bonded out on 2
sides of the device as two pin pairs (VDD1, VSS1 & VDD2, VSS2). VDD1 and VDD2 are connected together
internally. VSS1 and VSS2 are connected together internally. The extra pin pair enables systems using the
80-pin package to employ better supply routing and further decoupling.
1.7.6
Clock Reset Generator And VREG Interface
The low voltage reset feature uses the low voltage reset signal from the VREG module as an input to the
CRG module. When the regulator output voltage supply to the internal chip logic falls below a specified
threshold the LVR signal from the VREG module causes the CRG module to generate a reset.
NOTE
If the voltage regulator is shut down by connecting VDDR to ground then the
LVRF flag in the CRG flags register (CRGFLG) is undefined.
1.7.7
Analog-to-Digital Converter
In the 48- and 52-pin package versions, the VRL pad is bonded internally to the VSSA pin.
1.7.8
MODRR Register Port T And Port P Mapping
The MODRR register within the PIM allows for mapping of PWM channels to port T in the absence of
port P pins for the low pin count packages. For the 80QFP package option it is recommended not to use
MODRR since this is intended to support PWM channel availability in low pin count packages. Note that
when mapping PWM channels to port T in an 80QFP option, the associated PWM channels are then
mapped to both port P and port T. .
1.7.9
Port AD Dependency On PIM And ATD Registers
The port AD pins interface to the PIM module. However, the port pin digital state can be read from either
the PORTAD register in the ATD register map or from the PTAD register in the PIM register map.
In order to read a digital pin value from PORTAD the corresponding ATDDIEN bit must be set and the
corresponding DDRDA bit cleared. If the corresponding ATDDIEN bit is cleared then the pin is configured
as an analog input and the PORTAD bit reads back as "1".
In order to read a digital pin value from PTAD, the corresponding DDRAD bit must be cleared, to
configure the pin as an input.
Furthermore in order to use a port AD pin as an analog input, the corresponding DDRAD bit must be
cleared to configure the pin as an input
64
MC9S12C-Family / MC9S12GC-Family
Rev 01.24
Freescale Semiconductor