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MC68302/D
Rev. 3
Microprocessor and Memory
Technologies Group
MC68302
Product Brief
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Integrated Multiprotocol Processor (IMP)
The IMP is a VLSI device incorporating the main building blocks needed for the design of a wide variety of
controllers. The device is especially suited to applications in the communications industry. The IMP is the first
device to offer the benefits of a closely coupled, industry-standard, MC68000/MC68008 microprocessor core
and a flexible communications architecture. This multichannel communications device may be configured to
support a number of popular industry-standard interfaces, including those for the Integrated Services Digital
Network (ISDN) basic rate and terminal adapter applications. Through a combination of architectural and
programmable features, concurrent operation of different protocols is easily achieved using the IMP. Data
concentrators, modems, line cards, bridges, and gateways are examples of suitable applications for this
versatile device. The IMP is an HCMOS device consisting of an MC68000/MC68008 microprocessor core, a
system integration block (SIB), and a communications processor (CP).
The main features of the IMP are as follows:
• MC68000/MC68008 Microprocessor Core (May Be Disabled to Use the IMP As a Peripheral)
• SIB Including:
— Independent Direct Memory Access (IDMA) Controller
— Interrupt Controller with Two Modes of Operation
— Parallel I/O Ports, Some with Interrupt Capability
— On-Chip 1152 Bytes of Dual-Port RAM
— Three Timers, Including a Software Watchdog Timer
— Four Programmable Chip-Select Lines with Wait-State Logic
— Programmable Address Mapping of Dual-Port RAM and IMP Registers
— On-Chip Clock Generator with an Output Clock Signal
— System Control
–System Control Register
–Bus Arbitration Logic with Low Interrupt Latency Support
–Hardware Watchdog for Monitoring Bus Activity
–Low Power (Standby) Modes
–Disable CPU Logic (M68000)
–Freeze Control for Debugging Selected On-Chip Peripherals
–DRAM Refresh Controller
• CP Including:
— Main Controller (RISC Processor)
— Three Full-Duplex Serial Communication Controllers (SCCs) with the Following Protocols:
–HDLC/SDLC
–Bisync
–UART
–DDCMP
–Totally Transparent
–V.110
This document contains information on a product under development. Motorola reserves the right to change or discontinue this product without notice.
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— Six Serial DMA Channels Dedicated to the Three SCCs
— Capability To Send /Receive Up to Eight Buffers/Frames without M68000 Core Intervention
— Flexible Physical Interface Accessible by SCCs for Interchip Digital Link (IDL), General Circuit
Interface (GCI, also called IOM2), Pulse Code Modulation (PCM), and Nonmultiplexed Serial Interface (NMSI) Operation
— Serial Communication Port (SCP) for Synchronous Communication
— Serial Management Controllers (SMCs) for IDL and GCI Channels
MC68000/MC68008 CORE
M68000 BUS
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MC68000 / MC68008 CORE
ON-CHIP PERIPHERALS BUS INTERFACE UNIT
INTERRUPT
CONTROLLER
BUS ARBITER
1 CHANNEL
IDMA
3 TIMERS
DRAM
REFRESH
CONTROLLER
PARALLEL I/O
1152 BYTES
DUAL-PORT
STATIC RAM
CHIP-SELECT
AND WAITSTATE LOGIC
SYSTEM
CONTROL
CLOCK
GENERATOR
SYSTEM INTEGRATION BLOCK
PERIPHERAL BUS
6 CHANNELS
SDMA
SMC (2)
SCC1
SCC2
SCC3
SCP
MAIN
CONTROLLER
(RISC)
SERIAL CHANNELS PHYSICAL INTERFACE
COMMUNICATIONS PROCESSOR
I/O PORTS AND PIN ASSIGNMENTS
MC68302 Block Diagram
2
MC68302 PRODUCT INFORMATION
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The MC68302 uses a microprocessor architecture that has serial channels connected to the system bus
through a dual-port memory. Various parameters, counters, and all memory buffer descriptor tables reside in
the dual-port RAM. The receive and transmit data buffers may be located in this on-chip RAM or in the off-chip
system RAM. Six DMA channels are dedicated to the six serial ports (receive and transmit for each of the three
SCC channels). If an SCC channel's data is programmed to be located in the external RAM, the CP main
controller (RISC processor) will automatically program the corresponding DMA channel to perform the required
accesses. If the data resides in the on-chip dual-port RAM, then the CP main controller accesses the RAM with
one clock cycle access and no arbitration delays.
The buffer memory structure of the MC68302 can be configured by software to closely match I/O channel
requirements. The interrupt structure is also programmable to relieve the on-chip MC68000/MC68008 core
from bit manipulation functions for peripherals, allowing the processor more time to perform application
software or protocol processing. In some cases, the interface to equipment or proprietary networks may
require the use of standard control and data signals. For these signals, the MC68302 can be programmed to
use the NMSI mode. This mode is available for one, two, or all three SCC ports; remaining ports may then
optionally use one of the multiplexed interface modes: IDL, GCI, or PCM.
The main controller is a microcoded RISC processor that services all the serial channels. The main controller
transfers data between the serial channels and internal/external RAM, executes host commands, and
generates interrupts to the interrupt controller. The MC68302 core processor allows operation either in the full
MC68000 mode with a 16-bit data bus or in the MC68008 mode with an 8-bit data bus.
The MC68302 has an SIB that simplifies the task of hardware and software design. The IDMA controller
eliminates the need for an external DMA controller on the system board. In addition, there is an interrupt
controller that can be used in a dedicated mode to generate interrupt acknowledge signals without external
logic. Similarly, the chip-select signals and wait-state logic eliminate the need to generate these signals
externally. The SIB includes the IDMA controller, interrupt controller, parallel I/O ports, dual-port RAM, three
timers, chip-select logic, clock generator, and system control.
The MC68302 has one IDMA channel and six serial DMA channels that operate concurrently with other CPU
operations. The IDMA can operate in different modes of data transfer as programmed by the user. The six
serial DMA channels for the three full-duplex SCC channels are transparent to the user, implementing buscycle-stealing data transfers controlled by the MC68302 internal RISC controller. These six channels have
priority over the separate IDMA channel. The IDMA controller can transfer data between any combination of
memory and I/O devices.
The interrupt controller, which manages the priority of internal and external interrupt requests, generates a
vector number during the CPU interrupt acknowledge cycle. Nested interrupts are fully supported.
The IMP has 1152 bytes of RAM configured as a dual-port memory. The RAM can be accessed by the internal
RISC controller or one of three bus masters: the M68000 core, an external bus master, or the IDMA. All internal
bus masters synchronously access the RAM with no wait states. External bus masters can access the RAM
and registers synchronously or asynchronously. The RAM is divided into two parts. There are 576 bytes used
as a parameter RAM, which includes pointers, counters, and registers for the serial ports. The other 576 bytes
may be used for system RAM, which may include data buffers, or may be used for other purposes such as
RAM for downloadable microcode packages provided by Motorola.
Port A and port B are two general-purpose I/O ports, with 16 and 12 pins, respectively.
There are three timer units. Two units are identical, general-purpose timers; the third unit can be used to
implement a watchdog timer function.
The MC68302 has a set of four programmable chip-select signals. Each chip select has an identical structure.
For each memory area, an internally generated cycle-termination signal (DTACK) may be defined with up to
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six wait states to avoid using board space for cycle-termination logic. The four signals may each support four
different classes of memory, such as high-speed static RAM, slower dynamic RAM, EPROM, and nonvolatile
RAM. The chip-select and wait-state generation logic is active for all potential bus masters.
The MC68302 has an on-chip clock generator that supplies internal and external high-speed clocks (up to 20
MHz).
NMSI1 / ISDN I / F
CLOCKS
RXD1 / L1RXD
TXD1 / L1TXD
RCLK1 / L1CLK
EXTAL
XTAL
CLKO
TCLK1 / L1SY0 / SDS1
CD1 / L1SY1
ADDRESS BUS
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CTS1 / L1GR
RTS1 / L1RQ / GCIDCL
BRG1/AMUX
A23–A1
DATA BUS
D15–D0
NMSI2 / PIO
RXD2 / PA0
TXD2 / PA1
BUS CONTROL
AS
R/W
UDS / A0
LDS / DS
DTACK
RMC / IOUT1
IAC
BCLR
RCLK2 / PA2
TCLK2 / PA3
CTS2 / PA4
RTS2 / PA5
CD2 / PA6
BRG2 / SDS2 / PA7/RAS0
NMSI3 / SCP / PIO
BUS ARBITRATON
BR
BG
BGACK
RXD3 / PA8
TXD3 / PA9
RCLK3 / PA10
TCLK3 / PA11
CTS3 / SPRXD
RTS3 / SPTXD
CD3 / SPCLK
MC68EN302
144-LEAD
BRG3 / PA12/RAS1
IDMA / PAIO
SYSTEM CONTROL
RESET
HALT
BERR
BUSW
DISCPU
INTERRUPT CONTROL
IPL0 / IRQ1
IPL1 / IRQ6
DREQ / PA13/WEL
DACK / PA14/WEH
DONE / PA15/OE
IPL2 / IRQ7
FC0
FC1
FC2
AVEC / IOUT0
IACK / PBIO
IACK7 / PB0/CAS0
IACK6 / PB1/C AS1
IACK1 / PB2/DRAM_RW
TIMER / PBIO
CHIP SELECT
TIN1 / PB3
CS0 / IOUT2
TOUT1 / PB4/A0
TIN2 / PB5
CS3–CS1
TESTING
TOUT2 / PB6
WDOG / PB7
TEST302
PBIO (INTERRUPT)
PB8
PB9
PB10
PB11
N.C.(2)
GND(15)
V DD (10)
Functional Signal Groups
4
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The following table identifies the packages and operating frequencies available for the MC68302.
MC68302 Package/Frequency Availability
Package
Surface Mount
Pin Grid Array
Frequency
16.67 MHz
20 MHz
•
•
•
•
The documents listed in the following table contain information on the MC68302. These documents may be
obtained from the Literature Distribution Centers at the addresses listed at the bottom of the last page of this
document.
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Related Documentation
Document Title
Order Number
MC68302 User's Manual
M68000 Family Programmer's Reference Manual
M68000 8-/16-/32-Bit Microprocessors User's Manual
MC68195 LocalTalk Adapter Product Brief
MC68302 Development Support
The 68K Source
MOTOROLA
Contents
MC68302UM/AD
Detailed information for design
M68000PM/AD
M68000 Family Instruction Set
MC68000UM/AD
MC68195/D
BR469
BR729/D, Rev 1
Detailed information for design
Related Product Information
Development Support for MC68302
Independent vendor listing supporting
software and development tools
MC68302 PRODUCT INFORMATION
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Motorola reserves the right to make changes without further notice to any products herein. Motorola makes no warranty, representation or guarantee regarding
the suitability of its products for any particular purpose, nor does Motorola assume any liability arising out of the application or use of any product or circuit, and
specifically disclaims any and all liability, including without limitation consequential or incidental damages. "Typical" parameters can and do vary in different
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unintended or unauthorized use, even if such claim alleges that Motorola was negligent regarding the design or manufacture of the part. Motorola and
are
registered trademarks of Motorola, Inc. Motorola, Inc. is an Equal Opportunity/Affirmative Action Employer.
Literature Distribution Centers:
USA: Motorola Literature Distribution; P.O. Box 20912, Arizona 85036.
EUROPE: Motorola Ltd.; European Literature Centre; 88 Tanners Drive, Blakelands, Milton Keynes, MK14 5BP, England.
JAPAN: Nippon Motorola Ltd.; 4-32-1, Nishi-Gotanda, Shinagawa-ku, Tokyo 141 Japan.
ASIA-PACIFIC: Motorola Semiconductors H.K. Ltd.; Silicon Harbour Center, No. 2 Dai King Street, Tai Po Industrial Estate,
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