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DS2484
Single-Channel 1-Wire Master with Adjustable Timing and Sleep Mode
General Description
The DS2484 is an I
2
C-to-1-Wire
M
bridge device that interfaces directly to standard (100kHz max) or fast
(400kHz max) I
2
C masters to perform protocol conversion between the I
2
C master and any downstream
1-Wire slave devices. Relative to any attached 1-Wire slave device, the DS2484 is a 1-Wire master. Internal, user-adjustable timers relieve the system host processor from generating time-critical 1-Wire waveforms, supporting both standard and overdrive 1-Wire communication speeds. In addition, the 1-Wire bus can be powered down under software control. The dual-voltage operation allows different operating voltages on the I
2
C and 1-Wire side. Strong pullup features support 1-Wire power delivery to 1-Wire devices such as EEPROMs and sensors.
When not in use, the DS2484 can be put in sleep mode where power consumption is minimal.
Applications
Printers
Medical Instruments
Industrial Sensors
Cell Phones
Benefits and Features
S
I
2
C Host Interface Supports 100kHz and 400kHz
I
2
C Communication Speeds
S
Standard and Overdrive 1-Wire Communication
Speeds
S
Adjustable 1-Wire Timing for t and t
REC0
RSTL
, t
MSP
, t
W0L
,
S
1-Wire Port Can Be Powered Down Under
Software Control
S
Supports Power-Saving Sleep Mode (SLPZ Pin),
Where the 1-Wire Port is in High Impedance
S
I
2
C Operating Voltages: 1.8V ±5%, 3.3V ±10%, and
5.0V +5/-10%
S
Built-In Level Translator: 1-Wire Operating Voltage from 1.8V -5% to 5.0V +5%, Independent of I
2
C
Voltage
S
Built-In ESD Protection Level of ±8kV Human
Body Model (HBM) Contact Discharge on IO Pin
S
-40NC to +85NC Operating Temperature Range
S
8-Pin TDFN and 6-Pin SOT23 Packages
Ordering Information appears at end of data sheet.
Typical Application Circuit
3V
(I
2
C PORT)
µC
R
P
*
SDA
SCL
5V
V
CC
DS2484
SLPZ IO
1-Wire BUS
1-Wire
DEVICE #1
1-Wire
DEVICE #2
1-Wire
DEVICE #n
*R
P
= I
2
C PULLUP RESISTOR (SEE THE
SECTION FOR R
P
SIZING)
1-Wire is a registered trademark of Maxim Integrated Products, Inc.
For pricing, delivery, and ordering information, please contact Maxim Direct at
1-888-629-4642, or visit Maxim Integrated’s website at www.maximintegrated.com.
19-6701; Rev 1; 7/15
DS2484
Single-Channel 1-Wire Master with Adjustable Timing and Sleep Mode
ABSOLUTE MAXIMUM RATINGS
Voltage Range on Any Pin Relative to Ground .......-0.5V to +6V
Maximum Current into Any Pin ...........................................20mA
Continuous Power Dissipation (T
A
= +70NC)
SOT23 (derate 8.7mW/NC above +70NC) .................695.7mW
TDFN (derate 16.7mW/NC above +70NC) ...............1333.3mW
Operating Temperature Range .......................... -40NC to +85NC
Junction Temperature .....................................................+150NC
Storage Temperature Range ............................ -55NC to +125NC
Lead Temperature (soldering, 10s) ................................+300NC
Soldering Temperature (reflow) ......................................+260NC
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
ELECTRICAL CHARACTERISTICS
(T
A
= -40NC to +85NC, unless otherwise noted.) (Note 1)
PARAMETER
Supply Voltage
SYMBOL
V
CC
I
2
C Voltage (Note 2)
Supply Current
Power-On-Reset Trip Point
IO PIN: GENERAL DATA
V
CI2C
I
CC
V
POR
CONDITIONS
1.8V
3.3V
5V
No communication, V
CC
= full range
Sleep mode, V
CC
= 5.25V
Sleep mode, V
CC
= 3.6V
V
CC
= full range
1-Wire Input High Voltage V
IH1
V
CC
= full range
MIN
1.71
1.71
2.97
4.5
TYP
1.8
3.3
5.0
1.0
MAX
5.25
1.89
3.63
5.25
300
4
3.0
1.5
UNITS
V
V
F
A
V
V
1-Wire Input Low Voltage
1-Wire Weak Pullup Resistor
1-Wire Output Low Voltage
Active Pullup On-Threshold
Active Pullup On-Time (Note 3)
Active Pullup Impedance
V
IL1
R
WPU
V
OL1
V
IAPO t
APU
R
APU t
F1
V
CC
= full range
Low range
High range
I
OL
= 8mA sink current
V
CC
= full range
1-Wire time slot
1-Wire reset standard speed
1-Wire reset overdrive speed
V
CC
= 1.71V, 4mA load
V
CC
= 3.0V, 4mA load
V
CC
= 4.5V, 4mA load
Standard, 10pF < C
LOAD
< 400pF
Overdrive, 10pF < C
LOAD
< 400pF
0.6 O
V
CC
375
700
2.375
0.475
500
1000
0.2 O
V
CC
815
1375
0.2
0.6
0.95
1.2
See APU bit description
2.5
0.5
2.625
0.525
100
0.25
0.05
60
40
1
0.2
V
I
V
V
F s
I
F s 1-Wire Output Fall Time (Note 4)
IO PIN: 1-Wire TIMING (Note 5)
Reset Low Time
Reset High Time
Maxim Integrated t
RSTL t
RSTH
Standard
Overdrive
Standard and overdrive
-5%
See
Table 7
Equal to t
RSTL
+5%
F s
F s
2
Write-Zero Recovery Time
1-Wire Time Slot
SLPZ PIN
Low-Level Input Voltage
High-Level Input Voltage
DS2484
Single-Channel 1-Wire Master with Adjustable Timing and Sleep Mode
ELECTRICAL CHARACTERISTICS (continued)
(T
A
= -40NC to +85NC, unless otherwise noted.) (Note 1)
PARAMETER SYMBOL
Presence-Detect Sample Time
Sampling for Short and Interrupt
Write-One/Read Low Time
Read Sample Time
Write-Zero Low Time t
MSP t
SI t
W1L t
MSR t
W0L
CONDITIONS
Standard
Overdrive
Standard
Overdrive
Standard
Overdrive (Note 6)
Standard
Overdrive
Standard
Overdrive
Input Leakage Current (Note 2)
Wake-Up Time from Sleep Mode
I
2
C SCL AND SDA PINS (Note 9) t
REC0 t
SLOT
V
IL
V
IH
I
I t
SWUP
Standard and overdrive
Standard and overdrive
V
CC
= full range
(Note 7)
V
CI2C
< 1.89V
V
CI2C
< 3.63V
V
CI2C
< 5.25V
(Notes 4, 8)
MIN
-5%
7.6
0.71
7.6
0.71
11.4
1.66
TYP
See
Table 7
8
0.75
8
0.75
12
1.75
MAX
+5%
-5%
See
Table 7
+5%
-5%
See
Table 7
+5%
Equal to t
W0L
+ t
REC0
8.4
0.79
8.4
0.79
12.6
1.84
-0.5
1.3
+0.5
V
CCACT
6
15
32
2
UNITS
F s
F s
F s
F s
F s
F s
F s
V
V
F
A ms
Low-Level Input Voltage
High-Level Input Voltage
V
IL
V
IH
V
CI2C
= full range -0.5
0.3 O
V
CI2C
V
CI2C
0.5V
+
V
V
Hysteresis of Schmitt Trigger
Inputs (Note 4)
Low-Level Output Voltage at
3mA Sink Current
V
HYS
V
OL
V
CI2C
> 2.0V
V
CI2C
< 2.0V
V
CI2C
> 2.0V
V
CI2C
< 2.0V
0.7 O
V
CI2C
0.05 O
V
CI2C
0.1 O
V
CI2C
0.4
0.2 O
V
CI2C
V
V
Output Fall Time from V
IH(MIN)
V
IL(MAX) from 10pF to 400pF
to
with a Bus Capacitance
Pulse Width of Spikes
Suppressed by Input Filter t
OF t
SP
(Note 4) 60 250
50 ns ns
Maxim Integrated 3
DS2484
Single-Channel 1-Wire Master with Adjustable Timing and Sleep Mode
ELECTRICAL CHARACTERISTICS (continued)
(T
A
= -40NC to +85NC, unless otherwise noted.) (Note 1)
SYMBOL CONDITIONS PARAMETER
Input Current with Input Voltage
Between 0.1 O V
CC(MAX)
and 0.9
O
V
CC(MAX)
Input Capacitance
SCL Clock Frequency
Hold Time (Repeated) START
Condition (After this period, the first clock pulse is generated.)
Low Period of the SCL Clock
High Period of the SCL Clock
Setup Time for a Repeated
START Condition
Data Hold Time
Data Setup Time
Setup Time for STOP Condition
Bus Free Time Between a STOP and START Condition
Capacitive Load for Each Bus
Line
Oscillator Warmup Time
I
I
C
I f
SCL t
HD:STA t
LOW t
HIGH t
SU:STA t
HD:DAT t
SU:DAT t
SU:STO t
BUF
C
B t
OSCWUP
(Note 10)
(Note 4)
(Notes 11, 12)
(Note 13)
(Notes 4, 14)
(Notes 4, 8)
MIN
-10
0
0.6
1.3
0.6
0.6
250
0.6
1.3
TYP MAX
+10
10
400
0.9
400
2
UNITS
F
A pF kHz
F s
F s
F s
F s
F s ns
F s
F s pF ms
Note 1: Limits are 100% production tested at T
A
= +25°C. Limits over the operating temperature range and relevant supply voltage range are guaranteed by design and characterization. Typical values are at +25°C.
Note 2: The V
CI2C measure V
voltage is applied at the SLPZ pin. V
(wakeup from sleep mode) or after t
OSCWUP
CI2C
.
CI2C
must always be < V
Note 5: Except for t
F1
Note 6: Although 1-Wire slave data sheets specify a t
W1L
and t t
W1L
and t
RL
CC
. The DS2484 measures V
CI2C
after t
SWUP
command does not cause the DS2484 to
Note 3: The active pullup does not apply to the rising edge of a presence pulse outside of a
1-Wire Reset command or during the
recovery after a short on the 1-Wire line.
Note 4: Guaranteed design and not production tested.
, all 1-Wire timing specifications are derived from the same timing circuit.
Note 7: V
Note 8: I
2
CCACT
of the DS2484.
refers to the V
CC
C communication should not take place for the max t from sleep mode.
Note 9: All I
2
C timing values are referenced to V
IH(MIN)
and V
RL
minimum of 1µs, 1-Wire slaves will accept the shorter 0.71µs
level being applied in the application.
OSCWUP
IL(MAX)
or t
levels.
SWUP
time following a power-on reset or a wake-up
Note 10: The DS2484 does not obstruct the SDA and SCL lines if SLPZ is at 0V or if V
of the SCL signal) to
CC
is switched off.
Note 11: The DS2484 provides a hold time of at least 300ns for the SDA signal (referenced to the V
IH(MIN) bridge the undefined region of the falling edge of SCL.
Note 12: The maximum t
HD:DAT
must only be met if the device does not stretch the low period (t
Note 13: A fast mode I
2
C bus device can be used in a standard mode I
2
LOW
) of the SCL signal.
C bus system, but the requirement t acknowledge timing must meet this setup time (I
2
C bus specification Rev. 03, 19 June 2007).
SU:DAT
R 250ns must then be met. This requirement is met since the DS2484 does not stretch the low period of the SCL signal. Also the
Note 14: C
B
= Total capacitance of one bus line in pF. The maximum bus capacitance allowable can vary from this value depending on the actual operating voltage and frequency of the application (I
2
C bus specification Rev. 03, 19 June 2007).
Maxim Integrated 4
SCL 1
SDA 2
SLPZ 3
N.C.
4
DS2484
Single-Channel 1-Wire Master with Adjustable Timing and Sleep Mode
Pin Configurations
TOP MARK TOP VIEW
DS2484
EP
8 GND
7 IO
6
V
CC
5
N.C.
TDFN
(2mm x 3mm)
2484
YMrr
V
CC
6
TOP VIEW
IO
5
GND
4
DS2484
1
SLPZ
2
SDA
3
SCL
SOT23
“rr” = REVISION CODE
TOP MARK
3Hrr
Pin Description
PIN
TDFN-EP SOT23
1 3
2
3
4, 5
6
7
8
—
2
1
—
6
5
4
—
N.C.
V
CC
IO
GND
EP
NAME
SCL
SDA
SLPZ
FUNCTION
I
2
C Serial-Clock Input. Must be connected to the I
2
C bus supply voltage through a pullup resistor.
I
2
C Serial-Data Input/Output. Must be connected to the I
2
C bus supply voltage through a pullup resistor.
Power Supply for I
2
C Port and Active-Low Control Input to Activate the Low-Power Sleep
Mode. This pin can be driven directly by a push-pull port or by an open-drain port with a
2.2kI pullup resistor to the I
2
C voltage (V
CI2C
) over the entire operating voltage range.
No Connection. Not internally connected.
Power-Supply Input
Input/Output Driver for 1-Wire Line
Ground Reference
Exposed Pad (TDFN Only). Solder evenly to the board’s ground plane for proper operation.
Refer to Application Note 3273: Exposed Pads: A Brief Introduction for additional information.
Maxim Integrated 5
DS2484
Single-Channel 1-Wire Master with Adjustable Timing and Sleep Mode
V
CC
CONFIGURATION AND
TIMING REGISTER
T-TIME OSC
SDA
SCL
SLPZ
GND
I
2
C
INTERFACE
CONTROLLER
INPUT/OUTPUT
CONTROLLER
STATUS
REGISTER
READ DATA
REGISTER
LINE
XCVR
DS2484
IO
Figure 1. Block Diagram
Table 1. Device Configuration Register Bit Assignment
BIT 7
1WS
BIT 6
SPU
BIT 5
PDN
BIT 4
APU
BIT 3
1WS
BIT 2
SPU
BIT 1
PDN
BIT 0
APU
Detailed Description
The DS2484 is a self-timed 1-Wire master that supports advanced 1-Wire waveform features including standard and overdrive speeds, active pullup, and strong pullup for power delivery. The active pullup affects rising edges on the 1-Wire side. The strong pullup function uses the same pullup transistor as the active pullup, but with a different control algorithm. Once supplied with command and data, the input/output controller of the DS2484 performs time-critical 1-Wire communication functions such as reset/presence-detect cycle, read-byte, write-byte, single bit R/W, and triplet for ROM Search, without requiring interaction with the host processor. The host obtains feedback (completion of a 1-Wire function, presence pulse, 1-Wire short, search direction taken) through the
Status register and data through the Read Data register. The DS2484 communicates with a host processor through its I
2
C bus interface in standard mode or in fast mode. See
for a block diagram.
Device Registers
The DS2484 has four registers that the I
2
C host can read: Device Configuration, Status, Read Data, and Port
Configuration. These registers are addressed by a read
Maxim Integrated pointer. The position of the read pointer, i.e., the register that the host reads in a subsequent read access, is defined by the instruction the DS2484 executed last.
To enable certain 1-Wire features, the host has read- and write-access to the Device Configuration and Port
Configuration registers.
Device Configuration Register
The DS2484 supports four 1-Wire features that are enabled or selected through the Device Configuration register (
Table 1 ). These features are as follows:
• Active Pullup (APU)
• 1-Wire Power-Down (PDN)
• Strong Pullup (SPU)
• 1-Wire Speed (1WS)
APU, SPU, and 1WS can be selected in any combination.
While APU and 1WS maintain their states, SPU returns to its inactive state as soon as the strong pullup has ended.
After a device reset (power-up cycle or initiated by the
Device Reset command), the Device Configuration reg-
ister reads 00h. When writing to the Device Configuration register, the new data is accepted only if the upper nibble
(bits 7 to 4) is the one’s complement of the lower nibble
(bits 3 to 0). When read, the upper nibble is always 0h.
6
DS2484
Single-Channel 1-Wire Master with Adjustable Timing and Sleep Mode
Active Pullup (APU)
The APU bit controls whether an active pullup (low impedance transistor) or a passive pullup (R
WPU
resistor) is used to drive a 1-Wire line from low to high. When
APU = 0, active pullup is disabled (resistor mode).
Enabling active pullup is generally recommended for best 1-Wire bus performance. The active pullup does not apply to the rising edge of a recovery after a short on the 1-Wire line. If enabled, a fixed-duration active pullup (typically 2.5Fs standard speed, 0.5Fs overdrive speed) also applies in a reset/presence detect cycle on the rising edges after t
RSTL
and after t
PDL
.
The circuit that controls rising edges operates as follows
(
): At t
1
, the pulldown (from DS2484 or 1-Wire slave) ends. From this point on the 1-Wire bus is pulled high through R
WPU
internal to the DS2484. V
CC
and the capacitive load of the 1-Wire line determine the slope. In case that active pullup is disabled (APU = 0), the resistive pullup continues, as represented by the solid line.
With active pullup enabled (APU = 1), and when at t
2 voltage has reached the V
IAPO
the
threshold, the DS2484 activates a low-impedance pullup transistor, as represented by the dashed line. The active pullup remains active until the end of the time slot (t
3 resistive pullup continues. The shortest duration of the active pullup is t
REC0
- (t
2
- t
1
) in a write-zero time slot and the longest duration is t
W0L
+ t
), after which the
REC0
- t
W1L
- (t
2
- t
1
) in a write-one time slot. In a read-data time slot, the active pullup duration is slave dependent. See the
section for a way to keep the pullup transistor con-
ducting beyond t
3
.
1-Wire Power Down (PDN)
The PDN bit is used to remove power from the 1-Wire port, e.g., to force a 1-Wire slave to perform a power-on reset. PDN can as well be used in conjunction with the
for details). While PDN is 1, no 1-Wire communication is possible. To end the 1-Wire power-down state, the PDN bit must be changed to 0.
Writing both the PDN bit and the SPU bit to 1 forces the
SPU bit to 0. With the DS2483, both bits can be written to 1, which can be used to logically distinguish between both parts.
Table 2. Effects of PDN and SLPZ
PDN =
0
1
SLPZ IS LOGIC 0
• R
WPU
is connected.
• IO is at V
CC
, keeping the slaves powered.
• The DS2484 is powered down (sleep mode).
• R
WPU
is disconnected.
• IO is at 0V, causing the slaves to lose power.
• The DS2484 is powered down (sleep mode).
SLPZ IS LOGIC 1
• R
WPU
is connected.
• IO is at V
CC
, keeping the slaves powered.
• The DS2484 is powered up (normal operation).
• R
WPU
is disconnected.
• IO is at 0V, causing the slaves to lose power.
• The DS2484 is powered up.
V
CC
APU = 1
V
IAPO
V
IL1MAX
APU = 0
0V
1-Wire BUS IS
DISCHARGED t
REC0 t
1 t
2
Figure 2. Rising Edge Pullup as Seen at the End of a Write-Zero Time Slot
t
3
NEXT TIME SLOT
Maxim Integrated 7
DS2484
Single-Channel 1-Wire Master with Adjustable Timing and Sleep Mode
Strong Pullup (SPU)
The SPU bit is used to activate the strong pullup func-
tion prior to a 1-Wire Write Byte or
command. Strong pullup is commonly used with 1-Wire
EEPROM devices when copying scratchpad data to the main memory or when performing a SHA computation and with parasitically powered temperature sensors or
A/D converters. The respective Maxim 1-Wire IC data sheets specify the location in the communications protocol after which the strong pullup should be applied. The
SPU bit must be set immediately prior to issuing the command that puts the 1-Wire device into the state where it needs the extra power. The strong pullup uses the same internal pullup transistor as the active pullup feature.
See the R
APU
to determine whether the voltage drop is low enough to maintain the required 1-Wire voltage at a given load current and 1-Wire supply voltage.
If SPU is 1 and APU is 0, the DS2484 treats the rising edge of the time slot as if the active pullup was activated, but uses V
IH1
as the threshold to enable the strong pullup. If SPU is 1 and APU is 1, the threshold voltage to enable the strong pullup is V
IAPO
. Once enabled, in contrast to the active pullup, the internal pullup transis-
tor remains conducting, as shown in Figure 3 , until one
of three events occurs: the DS2484 receives a command that generates 1-Wire communication (the typical case), the SPU bit in the Device Configuration register is written to 0, or the DS2484 receives the
command. When the strong pullup ends, the SPU bit is automatically reset to 0. Using the strong pullup feature does not change the state of the APU bit in the Device
Configuration register.
1-Wire Speed (1WS)
The 1WS bit determines the timing of any 1-Wire communication generated by the DS2484. All 1-Wire slave devices support standard speed (1WS = 0). Many
1-Wire devices can also communicate at a higher data rate, called overdrive speed. To change from standard to overdrive speed, a 1-Wire device needs to receive an Overdrive-Skip ROM or Overdrive-Match ROM command, as explained in the Maxim 1-Wire IC data sheets.
The change in speed occurs immediately after the 1-Wire device has received the speed-changing command code. The DS2484 must take part in this speed change to stay synchronized. This is accomplished by writing to the Device Configuration register with the 1WS bit as 1 immediately after the 1-Wire Byte command that changes the speed of a 1-Wire device. Writing to the Device
Configuration register with the 1WS bit as 0, followed by a
1-Wire Reset command, changes the DS2484 and any
1-Wire devices on the active 1-Wire line back to standard speed.
V
CC
SEE TEXT
0V
LAST BIT OF 1-Wire WRITE BYTE OR 1-Wire SINGLE BIT FUNCTION
WRITE-ONE CASE
WRITE-ZERO CASE t
SLOT
DS2484 PULLDOWN DS2484 RESISTIVE PULLUP
Figure 3. Low-Impedance Pullup Timing
NEXT
TIME SLOT
OR 1-Wire
RESET
DS2484 STRONG PULLUP
Maxim Integrated 8
DS2484
Single-Channel 1-Wire Master with Adjustable Timing and Sleep Mode
Table 3. Status Register Bit Assignment
BIT 7
DIR
BIT 6
TSB
BIT 5
SBR
BIT 4
RST
BIT 3
LL
BIT 2
SD
BIT 1
PPD
BIT 0
1WB
Status Register
The read-only Status register is the general means for the DS2484 to report bit-type data from the 1-Wire side,
1-Wire busy status, and its own reset status to the host processor (
). All 1-Wire communication com-
mands and the Device Reset command position the read
pointer at the Status register for the host processor to read with minimal protocol overhead. Status information is updated during the execution of certain commands only. Bit details are given in the following descriptions.
1-Wire Busy (1WB)
The 1WB bit reports to the host processor whether the
1-Wire line is busy. During 1-Wire communication 1WB is 1; once the command is completed, 1WB returns to its default 0. Details on when 1WB changes state and
for how long it remains at 1 are found in the
Presence-Pulse Detect (PPD)
The PPD bit is updated with every 1-Wire Reset com-
mand. If the DS2484 detects a logic 0 on the 1-Wire line at t
MSP
during the presence-detect cycle, the PPD bit is set to 1. This bit returns to its default 0 if there is no presence pulse during a subsequent
command.
Short Detected (SD)
The SD bit is updated with every 1-Wire Reset com-
mand. If the DS2484 detects a logic 0 on the 1-Wire line at t
SI
during the presence-detect cycle, the SD bit is set to 1. This bit returns to its default 0 with a subsequent
command, provided that the short has been removed. If the 1-Wire line is shorted at t
MSP
, the PPD bit is also set. The DS2484 cannot distinguish between a short and a DS1994 or DS2404 signaling a 1-Wire interrupt. For this reason, if a DS2404 or DS1994 is used in the application, the interrupt function must be disabled.
The interrupt signaling is explained in the respective
Maxim 1-Wire IC data sheets.
Logic Level (LL)
The LL bit reports the logic state of the active 1-Wire line without initiating any 1-Wire communication. The 1-Wire line is sampled for this purpose every time the Status register is read. The sampling and updating of the LL bit takes place when the host processor has addressed the
DS2484 in read mode (during the acknowledge cycle), provided that the read pointer is positioned at the Status register.
Device Reset (RST)
If the RST bit is 1, the DS2484 has performed an internal reset cycle, either caused by a power-on reset or from
executing the Device Reset command. The RST bit is
cleared automatically when the DS2484 executes a
Device Configuration command to restore the selection
of the desired 1-Wire features.
Single Bit Result (SBR)
The SBR bit reports the logic state of the active 1-Wire line sampled at t
MSR
of a
the first bit of a
command. The power-on
default of SBR is 0. If the 1-Wire Single Bit
command sends a 0 bit, SBR should be 0. With a
command, SBR could be 0 as well as 1, depending on the response of the 1-Wire devices connected. The same result applies to a
command that sends a 1 bit.
Triplet Second Bit (TSB)
The TSB bit reports the logic state of the active 1-Wire line sampled at t
MSR
of the second bit of a 1-Wire Triplet
command. The power-on default of TSB is 0. This bit is
updated only with a 1-Wire Triplet command and has no
function with other commands.
Branch Direction Taken (DIR)
Whenever a
command is executed, this bit reports to the host processor the search direction that was chosen by the third bit of the triplet. The power-on default of DIR is 0. This bit is updated only with a
Triplet command and has no function with other com-
mands. For additional information, see the description of the
Application Note 187:
1-Wire Search Algorithm .
Maxim Integrated 9
DS2484
Single-Channel 1-Wire Master with Adjustable Timing and Sleep Mode
Table 4. Port Configuration Register Bit Assignment
BIT 7
0
BIT 6
0
BIT 5
0
BIT 4
0
BIT 3
VAL3
BIT 2
VAL2
BIT 1
VAL1
BIT 0
VAL0
BITS 3:0
VAL[3:0]: Parameter Value Code
See Table 7 for the conversion between binary code and parameter value.
Port Configuration Register
The Port Configuration register allows verifying the set-
tings for the 1-Wire port ( Table 4 ). The
command positions the read pointer to the Port
Configuration register for the host processor to read with minimal protocol overhead. When reading the Port
Configuration register, the parameter values are reported in this sequence:
Parameter 000 (t
RSTL
) standard speed, overdrive speed
Parameter 001 (t
MSP
) standard speed, overdrive speed
Parameter 010 (t
W0L
) standard speed, overdrive speed
Parameter 011 (t
REC0
)
Parameter 100 (R
WPU
)
If one continues reading, the parameter number rolls over to 000 and one receives the same data again.
Note that the upper 4 bits read from the port configuration register are always 0. See Table 7 for the conversion between parameter value code and actual parameter value.
Function Commands
The DS2484 understands nine function commands that fall into four categories: device control, I
2
C communication, 1-Wire setup, and 1-Wire communication. The feedback path to the host is controlled by a read pointer, which is set automatically by each function command for the host to efficiently access relevant information.
The host processor sends these commands and appli-
I cable parameters as strings of 1 or 2 bytes using the
2
C interface. The I
2
C protocol requires that each byte be acknowledged by the receiving party to confirm acceptance or not be acknowledged to indicate an error condition (invalid code or parameter) or to end the communication. See the
the I
2
C protocol including acknowledge.
The function commands are as follows:
1) Device Reset
2) Set Read Pointer
3) Write Device Configuration
4) Adjust 1-Wire Port
5) 1-Wire Reset
6) 1-Wire Single Bit
7) 1-Wire Write Byte
8) 1-Wire Read Byte
9) 1-Wire Triplet
Maxim Integrated 10
DS2484
Single-Channel 1-Wire Master with Adjustable Timing and Sleep Mode
Device Reset
Command Code
Command Parameter
Description
F0h
None
Performs a global reset of device state machine logic. Terminates any ongoing 1-Wire communication.
Typical Use
Restriction
Error Response
Device initialization after power-up; reinitialization (reset) as desired.
None (can be executed at any time)
None
Command Duration
1-Wire Activity
Maximum 525ns. Counted from falling SCL edge of the command code acknowledge bit.
Ends maximum 262.5ns after the falling SCL edge of the command code acknowledge bit.
Read Pointer Position
Status Bits Affected
Status register (for busy polling).
RST set to 1; 1WB, PPD, SD, SBR, TSB, DIR set to 0.
Device Configurations Affected 1WS, APU, PDN, SPU set to 0.
Port Configurations Affected t
RSTL
, t
MSP
, t
W0L
, t
REC0
, and R
WPU
default values apply.
Set Read Pointer
Command Code
Command Parameter
Description
E1h
Pointer Code (see Table 5)
Sets the read pointer to the specified register. Overwrites the read pointer position of any
1-Wire communication command in progress.
Typical Use
Restriction
Error Response
To prepare reading the result from a 1-Wire Read Byte command; random read access of registers.
None (can be executed at any time).
If the pointer code is not valid, the pointer code is not acknowledged and the command is ignored.
Command Duration None. The read pointer is updated on the rising SCL edge of the pointer code acknowledge bit.
1-Wire Activity
Read Pointer Position
Not affected.
As specified by the pointer code.
Status Bits Affected
None
Device Configurations Affected None
Port Configurations Affected None
Table 5. Valid Read Pointer Codes
REGISTER
Device Configuration Register
Status Register
Read Data Register
Port Configuration Register
CODE
C3h
F0h
E1h
B4h
Maxim Integrated 11
DS2484
Single-Channel 1-Wire Master with Adjustable Timing and Sleep Mode
Write Device Configuration
Command Code
Command Parameter
Description
D2h
Configuration Byte
Writes a new device configuration byte. The new settings take effect immediately. Note:
When writing to the Device Configuration register, the new data is accepted only if the upper nibble (bits 7 to 4) is the one’s complement of the lower nibble (bits 3 to 0). When read, the upper nibble is always 0h.
Typical Use
Restriction
Error Response
Defining the features for subsequent 1-Wire communication.
1-Wire activity must have ended before the DS2484 can process this command.
Command code and parameter are not acknowledged if 1WB = 1 at the time the command code is received and the command is ignored.
Command Duration
None. The Device Configuration register is updated on the rising SCL edge of the configuration-byte acknowledge bit.
1-Wire Activity
Read Pointer Position
Status Bits Affected
None
Device Configuration register (to verify write).
RST set to 0.
Device Configurations Affected 1WS, SPU, PDN, APU updated.
Port Configurations Affected None
Adjust 1-Wire Port
Command Code
Command Parameter
Description
C3h
Control Byte
Updates the selected 1-Wire port parameter, which affects the 1-Wire timing or pullup resistor selection. See Table 6 for the control byte format. Note: Upon a power-on reset or after a Device Reset command, the parameter default values apply.
Typical Use
Restriction
Error Response
To adapt the 1-Wire port to the needs of the application. This can be necessary to accommodate the slave timing requirements, which are different at lower pullup voltage.
1-Wire activity must have ended before this command can be processed.
Command code and data byte are not acknowledged if 1WB = 1 at the time the command code is received and the command is ignored.
Command Duration
None. The selected port parameter is updated on the rising SCL edge of the control-byte acknowledge bit.
1-Wire Activity None
Read Pointer Position
Status Bits Affected
Port Configuration register (for verification).
None
Device Configurations Affected
None
Port Configurations Affected As specified by the control byte.
Maxim Integrated 12
DS2484
Single-Channel 1-Wire Master with Adjustable Timing and Sleep Mode
Table 6. Bit Allocation in the Control Byte
BIT 7
P2
BIT 6
P1
BIT 5
P0
BIT 4
OD
BIT 3
VAL3
BIT 2
VAL2
BIT 1
VAL1
BIT 0
VAL0
BITS 7:5
BIT 4
BITS 3:0
P[2:0]: Parameter Selection
000: selects t
RSTL
001: selects t
MSP
010: selects t
W0L
011: selects t
REC0
100: selects R
WPU
; the OD flag does not apply (don’t care)
; the OD flag does not apply (don’t care)
OD: Overdrive Control
0: the value provided applies to the standard speed setting
1: the value provided applies to the overdrive speed setting
VAL[3:0]: Parameter Value Code
See Table 7 for the conversion between binary code and parameter value.
Table 7. Conversion Between Parameter Code and Typical Parameter Value
PARAMETER
VALUE
CODE
1000
1001
1010
1011
1100
1101
1110
1111
0000
0001
0010
0011
0100
0101
0110
0111
PARAMETER 000 t
RSTL
(µs)
OD = 0 OD = 1
440
460
480
500
520
540
560
580
600
620
640
660
680
700
720
740
44
46
48
50
52
54
56
58
60
62
64
66
68
70
72
74
Note: The power-on default values are bold.
76
76
76
72
74
76
76
76
PARAMETER 001 t
MSP (
µs)
OD = 0 OD = 1
62
64
66
58
58
60
68
70
5.5
5.5
6.0
6.5
7.0
7.5
8.0
8.5
9.0
9.5
10.0
10.5
11.0
11.0
11.0
11.0
70
70
70
68
70
70
70
70
PARAMETER 010 t
W0L
(µs)
OD = 0 OD = 1
58
60
62
52
54
56
64
66
5.0
5.5
6.0
6.5
7.0
7.5
8.0
8.5
10
10
10
9.0
9.5
10
10
10
PARAMETER 011 t
REC0
(µs)
OD = N/A
2.75
2.75
2.75
2.75
2.75
2.75
5.25
7.75
10.25
12.75
15.25
17.75
20.25
22.75
25.25
25.25
PARAMETER 100
R
WPU
(W)
OD = N/A
500
500
500
500
500
500
1000
1000
1000
1000
1000
1000
1000
1000
1000
1000
Maxim Integrated 13
DS2484
Single-Channel 1-Wire Master with Adjustable Timing and Sleep Mode
1-Wire Reset
Command Code
Command Parameter
B4h
None
Description
Typical Use
Restriction
Error Response
Generates a 1-Wire reset/presence-detect cycle at the 1-Wire line (Figure 4). The state of the 1-Wire line is sampled at t
SI
and t
MSP
and the result is reported to the host processor through the Status register bits PPD and SD.
To initiate or end any 1-Wire communication sequence.
1-Wire activity must have ended before the DS2484 can process this command.
Command code is not acknowledged if 1WB = 1 at the time the command code is received and the command is ignored.
Command Duration
1-Wire Activity
Read Pointer Position
2 O t
RSTL
+ maximum 262.5ns, counted from the falling SCL edge of the command code acknowledge bit.
Begins maximum 262.5ns after the falling SCL edge of the command code acknowledge bit.
Status register (for busy polling).
Status Bits Affected 1WB (set to 1 for 2 O t
RSTL
), PPD is updated at t
RSTL
+ t
MSP
, SD is updated at t
RSTL
+ t
SI
.
Device Configurations Affected
1WS, APU apply.
Port Configurations Affected t
RSTL
, t
MSP
, t
W0L
, t
REC0
, and R
WPU
current values apply.
RESET PULSE
V
CC
V
IH1
V
IL1
0V
APU CONTROLLED
EDGE t
F1 t
RSTL
PULLUP (SEE FIGURE 2)
Figure 4. 1-Wire Reset/Presence-Detect Cycle
t
SI
PRESENCE/SHORT DETECT t
MSP
PRESENCE PULSE t
RSTH
DS2484 PULLDOWN 1-Wire SLAVE PULLDOWN
Maxim Integrated 14
DS2484
Single-Channel 1-Wire Master with Adjustable Timing and Sleep Mode
1-Wire Single Bit
Command Code
Command Parameter
87h
Bit Byte
Description
Generates a single 1-Wire time slot with a bit value “V” as specified by the bit byte at the
1-Wire line (Table 8). A V value of 0b generates a write-zero time slot (Figure 5); a V value of
1b generates a write-one time slot, which also functions as a read-data time slot (Figure 6). In either case, the logic level at the 1-Wire line is tested at t
MSR
and SBR is updated.
Typical Use
Restriction
Error Response
Command Duration
To perform single-bit writes or reads at the 1-Wire line when single bit communication is necessary (the exception).
1-Wire activity must have ended before the DS2484 can process this command.
Command code and bit byte are not acknowledged if 1WB = 1 at the time the command code is received and the command is ignored. t
SLOT byte.
+ maximum 262.5ns, counted from the falling SCL edge of the first bit (MSB) of the bit
1-Wire Activity
Read Pointer Position
Begins maximum 262.5ns after the falling SCL edge of the MSB of the bit byte.
Status register (for busy polling and data reading).
Status Bits Affected 1WB (set to 1 for t
SLOT
), SBR is updated at t
MSR
, DIR (may change its state).
Device Configurations Affected 1WS, APU, SPU apply.
Port Configurations Affected t
RSTL
, t
MSP
, t
W0L
, t
REC0
, and R
WPU
current values apply.
Table 8. Bit Allocation in the Bit Byte
BIT 7
V
X = Don’t care
BIT 6
X
BIT 5
X
BIT 4
X
BIT 3
X
BIT 2
X
BIT 1
X
BIT 0
X
Maxim Integrated 15
DS2484
Single-Channel 1-Wire Master with Adjustable Timing and Sleep Mode t
WOL t
MSR
V
CC
V
IH1
V
IL1
0V t
F1
Figure 5. Write-Zero Time Slot
PULLUP (SEE FIGURE 2) t
SLOT
DS2484 PULLDOWN t
R EC0 t
MSR t
W1L
V
CC
V
IH1
V
IL1
0V t
F1 t
SLOT
PULLUP (SEE FIGURE 2) DS2484 PULLDOWN 1-Wire SLAVE PULLDOWN
NOTE: DEPENDING ON ITS INTERNAL STATE, A 1-Wire SLAVE DEVICE TRANSMITS DATA TO ITS MASTER (e.g., THE DS2484). WHEN RESPONDING WITH A 0,
A 1-Wire SLAVE STARTS PULLING THE LINE LOW DURING t
W1L
. ITS INTERNAL TIMING GENERATOR DETERMINES WHEN THIS PULLDOWN ENDS AND THE VOLTAGE
STARTS RISING AGAIN. WHEN RESPONDING WITH A 1, A 1-Wire SLAVE DOES NOT HOLD THE LINE LOW AT ALL, AND THE VOLTAGE STARTS RISING AS SOON AS t
IS OVER. 1-Wire DEVICE DATA SHEETS USE THE TERM t
RL
INSTEAD OF t
SPECIFICATIONS AND CANNOT BE DISTINGUISHED FROM EACH OTHER.
W1L
TO DESCRIBE A READ-DATA TIME SLOT. TECHNICALLY, t
RL
AND t
W1L
W1L
HAVE IDENTICAL
Figure 6. Write-One and Read-Data Time Slot
Maxim Integrated 16
DS2484
Single-Channel 1-Wire Master with Adjustable Timing and Sleep Mode
Command Code
Command Parameter
Description
Typical Use
Restriction
Error Response
Command Duration
1-Wire Write Byte
A5h
Data Byte
Writes a single data byte to the 1-Wire line.
To write commands or data to the 1-Wire line. Equivalent to executing eight 1-Wire Single Bit commands, but faster due to less I
2
C traffic.
1-Wire activity must have ended before the DS2484 can process this command.
Command code and data byte are not acknowledged if 1WB = 1 at the time the command code is received and the command is ignored.
8 x t
SLOT byte.
+ maximum 262.5ns, counted from falling edge of the last bit (LSB) of the data
1-Wire Activity
Begins maximum 262.5ns after falling SCL edge of the LSB of the data byte (i.e., before the data-byte acknowledge). Note: The bit order on the I
2
C bus and the 1-Wire line is different
(1-Wire: LSB first; I
2
C: MSB first). Therefore, 1-Wire activity cannot begin before the DS2484 has received the full data byte.
Read Pointer Position Status register (for busy polling).
Status Bits Affected 1WB (set to 1 for 8 x t
SLOT
).
Device Configurations Affected 1WS, SPU, APU apply.
Port Configurations Affected t
RSTL
, t
MSP
, t
W0L
, t
REC0
, and R
WPU
current values apply.
1-Wire Read Byte
Command Code
Command Parameter
Description
Typical Use
Restriction
Error Response
Command Duration
1-Wire Activity
Read Pointer Position
96h
None
Generates eight read-data time slots on the 1-Wire line and stores result in the Read Data register.
To read data from the 1-Wire line. Equivalent to executing eight 1-Wire Single Bit commands with V = 1 (write-one time slot), but faster due to less I
2
C traffic.
1-Wire activity must have ended before the DS2484 can process this command.
Command code is not acknowledged if 1WB = 1 at the time the command code is received and the command is ignored.
8 x t
SLOT
+ maximum 262.5ns, counted from the falling SCL edge of the command code acknowledge bit.
Begins maximum 262.5ns after the falling SCL edge of the command code acknowledge bit.
Status register (for busy polling). Note: To read the data byte received from the 1-Wire line, issue the Set Read Pointer command and select the Read Data register. Then access the
DS2484 in read mode.
Status Bits Affected
1WB (set to 1 for 8 x t
SLOT
).
Device Configurations Affected 1WS, APU apply.
Port Configurations Affected t
RSTL
, t
MSP
, t
W0L
, t
REC0
, and R
WPU
current values apply.
Maxim Integrated 17
DS2484
Single-Channel 1-Wire Master with Adjustable Timing and Sleep Mode
Command Code
Command Parameter
Description
1-Wire Triplet
78h
Direction Byte
Generates three time slots: two read time slots and one write time slot at the 1-Wire line.
The type of write time slot depends on the result of the read time slots and the direction byte. The direction byte determines the type of write time slot if both read time slots are 0 (a typical case). In this case, the DS2484 generates a write-one time slot if V = 1 and a writezero time slot if V = 0. See Table 9.
If the read time slots are 0 and 1, they are followed by a write-zero time slot.
If the read time slots are 1 and 0, they are followed by a write-one time slot.
If the read time slots are both 1 (error case), the subsequent write time slot is a write-one.
Typical Use
Restriction
Error Response
To perform a 1-Wire Search ROM sequence; a full sequence requires this command to be executed 64 times to identify and address one device.
1-Wire activity must have ended before the DS2484 can process this command.
Command code and direction byte is not acknowledged if 1WB = 1 at the time the command code is received and the command is ignored.
Command Duration
Port Configurations Affected
3 x t
SLOT
+ maximum 262.5ns, counted from the falling SCL edge of the first bit (MSB) of the direction byte.
1-Wire Activity
Read Pointer Position
Begins maximum 262.5ns after the falling SCL edge of the MSB of the direction byte.
Status Register (for busy polling).
Status Bits Affected
1WB (set to 1 for 3 x t
SLOT the second t
MSR
(i.e., at t
), SBR is updated at the first t
MSR
SLOT
+ t
MSR
).
, TSB and DIR are updated at
Device Configurations Affected 1WS, APU apply. t
RSTL
, t
MSP
, t
W0L
, t
REC0
, and R
WPU
current values apply.
Table 9. Bit Allocation in the Direction Byte
BIT 7
V
X = Don’t care
BIT 6
X
BIT 5
X
BIT 4
X
BIT 3
X
BIT 2
X
BIT 1
X
BIT 0
X
Maxim Integrated 18
DS2484
Single-Channel 1-Wire Master with Adjustable Timing and Sleep Mode
MSB FIRST MSB LSB MSB LSB
SDA
SLAVE
ADDRESS
R/W ACK DATA ACK DATA ACK/
NACK
SCL 1–7 8 9 1–7 8 9 1–7 8 9
IDLE START
CONDITION
REPEATED IF MORE BYTES
ARE TRANSFERRED
STOP CONDITION
REPEATED START
Figure 7. I
2
C Protocol Overview
A6
0
A5
0
7-BIT SLAVE ADDRESS
A4
1
A3
1
A2
0
A1
0
A0
0 R/W
MSB DETERMINES
READ OR WRITE
Figure 8. DS2484 Slave Address
I
2
C Interface
General Characteristics
The I
2
C bus uses a data line (SDA) and a clock signal
(SCL) for communication. Both SDA and SCL are bidirectional lines connected to a positive supply voltage through a pullup resistor. When there is no communication, both lines are high. The output stages of devices connected to the bus must have an open drain or open collector to perform the wired-AND function. Data on the
I
2
C bus can be transferred at rates of up to 100kbps in standard mode and up to 400kbps in fast mode. The
DS2484 works in both modes.
A device that sends data on the bus is defined as a transmitter, and a device receiving data is defined as a receiver. The device that controls the communication is called a master. The devices that are controlled by the master are slaves. To be individually accessed, each device must have a slave address that does not conflict with other devices on the bus.
Data transfers can be initiated only when the bus is not busy. The master generates the serial clock (SCL), controls the bus access, generates the START and STOP conditions, and determines the number of data bytes
transferred between START and STOP ( Figure 7
). Data is transferred in bytes with the most significant bit being transmitted first. After each byte follows an acknowledge bit to allow synchronization between master and slave.
Slave Address
shows the slave address to which the DS2484 responds. The slave address is part of the slave address/ control byte. The last bit of the slave address/control byte (R/W) defines the data direction. When set to 0, subsequent data flows from master to slave (write access mode); when set to 1, data flows from slave to master
(read access mode).
Maxim Integrated 19
DS2484
Single-Channel 1-Wire Master with Adjustable Timing and Sleep Mode
I
2
C Definitions
I
The following terminology is commonly used to describe
2
C data transfers. See
for a timing diagram.
Bus Idle or Not Busy: Both SDA and SCL are inactive and in their logic-high states.
START Condition: To initiate communication with a slave, the master must generate a START condition.
A START condition is defined as a change in state of
SDA from high to low while SCL remains high.
STOP Condition: To end communication with a slave, the master must generate a STOP condition. A
STOP condition is defined as a change in state of SDA from low to high while SCL remains high.
Repeated START Condition: Repeated STARTs are commonly used for read accesses to select a specific data source or address from which to read. The master can use a repeated START condition at the end of a data transfer to immediately initiate a new data transfer following the current one. A repeated START condition is generated the same way as a normal
START condition, but without leaving the bus idle after a STOP condition.
Data Valid: With the exception of the START and
STOP condition, transitions of SDA can occur only during the low state of SCL. The data on SDA must remain valid and unchanged during the entire high pulse of SCL plus the required setup and hold time
(t
HD:DAT
after the falling edge of SCL and t
SU:DAT
before the rising edge of SCL; see Figure 9
). There is one clock pulse per bit of data. Data is shifted into the receiving device during the rising edge of SCL pulse.
When finished with writing, the master must release the SDA line for a sufficient amount of setup time
(minimum t
SU:DAT
+ t
R
) before the next rising edge of SCL to start reading. The slave shifts out each data bit on SDA at the falling edge of the previous SCL pulse and the data bit is valid at the rising edge of the current SCL pulse. The master generates all SCL clock pulses, including those needed to read from a slave.
Acknowledge: Typically a receiving device, when addressed, is obliged to generate an acknowledge after the receipt of each byte. The master must generate a clock pulse that is associated with this acknowledge bit. A device that acknowledges must pull SDA low during the acknowledge clock pulse in such a way that SDA is stable low during the high period of the acknowledge-related clock pulse plus the required setup and hold time (t falling edge of SCL and t edge of SCL).
SU:DAT
HD:DAT
after the
before the rising
SDA t
BUF t
LOW
SCL t
HD:STA t
R
STOP START
NOTE: TIMING IS REFERENCED TO V
IL(MAX)
AND V
IH(MIN)
.
Figure 9. I
2
C Timing Diagram
t
HD:DAT t
HIGH t
F t
SU:DAT
REPEATED
START t
SU:STA t
HD:STA
Maxim Integrated
SPIKE
SUPPRESSION t
SP t
SU:STO
20
DS2484
Single-Channel 1-Wire Master with Adjustable Timing and Sleep Mode
Not Acknowledged by Slave: A slave device could be unable to receive or transmit data, e.g., because it is busy performing a real-time function or is in sleep mode. In this case, the slave device does not acknowledge its slave address and leaves the SDA line high. A slave device that is ready to communicate acknowledges at least its slave address. However, some time later the slave can refuse to accept data, e.g., because of an invalid command or parameter.
In this case, the slave device does not acknowledge any of the bytes that it refuses and leaves SDA high.
In either case, after a slave has failed to acknowledge, the master first should generate a repeated START condition or a STOP condition followed by a START condition to begin a new data transfer.
Not Acknowledged by Master: At some time when receiving data, the master must signal an end of data to the slave device. To achieve this, the master does not acknowledge the last byte that it has received from the slave. In response, the slave releases SDA, allowing the master to generate the STOP condition.
Writing to the DS2484
To write to the DS2484, the master must access the device in write mode, i.e., the slave address must be sent with the direction bit set to 0. The next byte to be sent is a command code, which, depending on the command, may be followed by a command parameter. The DS2484 acknowledges valid command codes and expected/ valid command parameters. Additional bytes or invalid command parameters are never acknowledged.
Reading from the DS2484
To read from the DS2484, the master must access the device in read mode, i.e., the slave address must be sent with the direction bit set to 1. The read pointer determines the register that the master reads from. The master can continue reading the same register over and over again, without having to readdress the device, e.g., to watch the 1WB changing from 1 to 0. To read from a different
register, the master must issue the Set Read Pointer
command and then access the DS2484 again in read mode.
I
2
C Communication Examples
See
Table 10 and Table 11 for the I
2 legend and data direction codes.
C communication
Table 10. I
2
C Communication—Legend
SYMBOL
S
AD, 0
AD, 1
Sr
P
A
A\
(Idle)
<byte>
DRST
SRP
WCFG
ADJP
1WRS
1WSB
1WWB
1WRB
1WT
DESCRIPTION
START Condition
Select DS2484 for Write Access
Select DS2484 for Read Access
Repeated START Condition
STOP Condition
Acknowledged
Not Acknowledged
Bus Not Busy
Transfer of One Byte
Command “Device Reset” (F0h)
Command “Set Read Pointer” (E1h)
Command “Write Device Configuration” (D2h)
Command “Adjust 1-Wire Port” C3h)
Command “1-Wire Reset” (B4h)
Command “1-Wire Single Bit” (87h)
Command “1-Wire Write Byte” (A5h)
Command “1-Wire Read Byte” (96h)
Command “1-Wire Triplet” (78h)
Table 11. Data Direction Codes
Master-to-Slave Slave-to-Master
Maxim Integrated 21
DS2484
Single-Channel 1-Wire Master with Adjustable Timing and Sleep Mode
I
2
C Communication Examples (continued)
Device Reset (After Power-Up)
S AD,0 A DRST A Sr AD,1 A <byte> A\ P
Activities that are underlined denote an optional read access to verify the success of the command.
Set Read Pointer (To Read from Another Register)
Case A: Valid Read Pointer Code
S AD,0 A SRP A C3h A P
C3h is the read pointer code for the Device Configuration register.
Case B: Invalid Read Pointer Code
S AD,0 A SRP A E5h
E5h is an invalid read pointer code.
A\ P
Write Device Configuration (Before Starting 1-Wire Activity)
Case A: 1-Wire Idle (1WB = 0)
S AD,0 A WCFG A <byte> A Sr AD,1 A <byte> A\ P
Activities that are underlined denote an optional read access to verify the success of the command.
Case B: 1-Wire Busy (1WB = 1)
S AD,0 A WCFG A\ P
The master should stop and restart as soon as the DS2484 does not acknowledge the command code.
Adjust 1-Wire Port (after power-up, e.g., to select a 1-Wire timing other than the default)
Case A: 1-Wire Idle (1WB = 0)
S AD,0 A ADJP A <byte> A <byte> A P
Repeat to set additional port parameters
for the format of the control byte.
Case B: 1-Wire Busy (1WB = 1)
S AD,0 A ADJP A\ P
The master should stop and restart as soon as the DS2484 does not acknowledge the command code.
Maxim Integrated 22
DS2484
Single-Channel 1-Wire Master with Adjustable Timing and Sleep Mode
I
2
C Communication Examples (continued)
Verifying the 1-Wire port configuration
The
command sets the read pointer to the Port Configuration register. If other commands were issued to the DS2484 since then, use the
command first to position the read pointer to the Port
Configuration register.
Condition: 1-Wire Idle (1WB = 0), Read Pointer at Port Configuration Register
S AD,1 A <byte> A <byte> A <byte> A\ P
Repeat to read additional port parameters
1-Wire Reset (To Begin or End 1-Wire Communication)
Case A: 1-Wire Idle (1WB = 0), No Busy Polling to Read the Result
S AD,0 A 1WRS A P (Idle) S AD,1 A <byte> A\ P
In the first cycle, the master sends the command. Then the master waits (Idle) for the 1-Wire reset to complete. In the second cycle, the DS2484 is accessed to read the result of the 1-Wire reset from the Status register.
Case B: 1-Wire Idle (1WB = 0), Busy Polling Until the 1-Wire Command is Completed, then Read the Result
S AD,0 A 1WRS A Sr AD,1 A <byte> A <byte> A \ P
Repeat until the 1WB bit has changed to 0.
Case C: 1-Wire Busy (1WB = 1)
S AD,0 A 1WRS A\ P
The master should stop and restart as soon as the DS2484 does not acknowledge the command code.
Maxim Integrated 23
DS2484
Single-Channel 1-Wire Master with Adjustable Timing and Sleep Mode
I
2
C Communication Examples (continued)
1-Wire Single Bit (To Generate a Single Time Slot on the 1-Wire Line)
Case A: 1-Wire Idle (1WB = 0), No Busy Polling
S AD,0 A 1WSB A <byte> A P (Idle)
S AD,1 A <byte> A\ P
The idle time is needed for the 1-Wire function to complete. Then access the device in read mode to get the result
command.
Case B: 1-Wire Idle (1WB = 0), Busy Polling Until the 1-Wire Command is Completed
S AD,0 A 1WSB A <byte> A
Repeat until the 1WB bit has changed to 0.
Sr AD,1 A <byte> A <byte> A\ P
When 1WB has changed from 1 to 0, the Status register holds the valid result of the
Case C: 1-Wire Busy (1WB = 1)
S AD,0 A 1WSB A\ P
The master should stop and restart as soon as the DS2484 does not acknowledge the command code.
1-Wire Write Byte (To Send a Command Code or Data Byte to the 1-Wire Line)
Case A: 1-Wire Idle (1WB = 0), No Busy Polling
S AD,0 A 1WWB A 33h A P (Idle)
33h is the valid 1-Wire ROM function command for Read ROM. The idle time is needed for the 1-Wire function to complete. There is no data read back from the 1-Wire line with this command.
Case B: 1-Wire Idle (1WB = 0), Busy Polling Until the 1-Wire Command is Completed.
S AD,0 A 1WWB A 33h A
Repeat until the 1WB bit has changed to 0.
Sr AD,1 A <byte> A <byte> A\ P
When 1WB has changed from 1 to 0, the
1-Wire Write Byte command is completed.
Case C: 1-Wire Busy (1WB = 1)
S AD,0 A 1WWB A\ P
The master should stop and restart as soon as the DS2484 does not acknowledge the command code.
Maxim Integrated 24
DS2484
Single-Channel 1-Wire Master with Adjustable Timing and Sleep Mode
I
2
C Communication Examples (continued)
1-Wire Read Byte (To Read a Byte from the 1-Wire Line)
Case A: 1-Wire Idle (1WB = 0), No Busy Polling, Set Read Pointer After Idle Time
S AD,0 A 1WRB A P (Idle)
S AD,0 A SRP A E1h A Sr AD,1 A <byte> A\ P
The idle time is needed for the 1-Wire function to complete. Then set the read pointer to the Read Data register
(code E1h) and access the device again to read the data byte that was obtained from the 1-Wire line.
Case B: 1-Wire Idle (1WB = 0), No Busy Polling, Set Read Pointer Before Idle Time
S AD,0 A 1WRB A Sr AD,0 A SRP A E1h A P
(Idle) S AD,1 A <byte> A\ P
ress. Then, after the 1-Wire function is completed, the device is accessed to read the data byte that was obtained from the 1-Wire line.
Case C: 1-Wire Idle (1WB = 0), Busy Polling Until the 1-Wire Command is Completed
S AD,0 A 1WRB A
Repeat until the 1WB bit has changed to 0.
Sr AD,1 A <byte> A <byte> A\
Sr AD,0 A SRP A E1h A Sr AD,1 A <byte> A\ P
Poll the Status segister until the 1WB bit has changed from 1 to 0. Then set the read pointer to the Read Data register (code E1h) and access the device again to read the data byte that was obtained from the 1-Wire line.
Case D: 1-Wire Busy (1WB = 1)
S AD,0 A 1WRB A\ P
The master should stop and restart as soon as the DS2484 does not acknowledge the command code.
Maxim Integrated 25
DS2484
Single-Channel 1-Wire Master with Adjustable Timing and Sleep Mode
I
2
C Communication Examples (continued)
1-Wire Triplet (To Perform a Search ROM Function on 1-Wire Line)
Case A: 1-Wire Idle (1WB = 0), No Busy Polling
S AD,0 A 1WT A <byte> A P (Idle)
S AD,1 A <byte> A\ P
The idle time is needed for the 1-Wire function to complete. Then access the device in read mode to get the result
command.
Case B: 1-Wire Idle (1WB = 0), Busy Polling Until the 1-Wire Command is Completed
S AD,0 A 1WT A <byte> A
Repeat until the 1WB bit has changed to 0.
Sr AD,1 A <byte> A <byte> A\ P
When 1WB has changed from 1 to 0, the Status register holds the valid result of the
Case C: 1-Wire Busy (1WB = 1)
S AD,0 A 1WT A\ P
The master should stop and restart as soon as the DS2484 does not acknowledge the command code.
Maxim Integrated 26
DS2484
Single-Channel 1-Wire Master with Adjustable Timing and Sleep Mode
Applications Information
SDA and SCL Pullup Resistors
SDA is an open-drain output on the DS2484 that requires a pullup resistor to realize high-logic levels. Because the
DS2484 uses SCL only as input (no clock stretching), the master can drive SCL either through an open-drain/collector output with a pullup resistor or a push-pull output.
Pullup Resistor R
P
Sizing
According to the I
2
C specification, a slave device must be able to sink at least 3mA at a V
OL
of 0.4V. This DC condition determines the minimum value of the pullup resistor: R
P(MIN)
= (V lup voltage V
CI2C
CI2C
- 0.4V)/3mA. With an I
2
C pul-
of 5.5V, the minimum value for the pullup resistor is 1.7kI. The “Minimum R operating (pullup) voltage.
P
shows how the minimum pullup resistor changes with the
For I
2
C systems, the rise time and fall time are measured from 30% to 70% of the pullup voltage. The maximum bus capacitance, C
B
, is 400pF. The maximum rise time must not exceed 300ns. Assuming maximum rise time, the maximum resistor value at any given capacitance C
B is calculated as: R
P(MAX)
= 300ns/(C
B would be 885I.
x ln(7/3)). For a bus capacitance of 400pF, the maximum pullup resistor
Because an 885I pullup resistor, as would be required to meet the rise time specification at 400pF bus capacitance, is lower than R
P(MIN)
at 5.5V, a different approach is necessary. The “Maximum Load at Minimum R
P
Fast
Mode” line in
is generated by first calculating the minimum pullup resistor at any given operating voltage (“Minimum R
P
” line) and then calculating the respective bus capacitance that yields a 300ns rise time.
Only for pullup voltages of 3V and lower can the maximum permissible 400pF bus capacitance be maintained.
A reduced 300pF bus capacitance is acceptable for 4V and lower pullup voltages. For fast mode operation at any pullup voltage, the bus capacitance must not exceed
200pF. The corresponding pullup resistor value at the voltage is indicated by the “Minimum R
P
” line.
2000
1600
1200
800
400
0
1
MINIMUM R
P
2 3
PULLUP VOLTAGE (V)
MAXIMUM LOAD AT MINIMUM R
P
FAST MODE
500
400
300
200
100
0
4 5
Figure 10. I
2
C Fast Mode Pullup Resistor Selection Chart
Maxim Integrated 27
DS2484
Single-Channel 1-Wire Master with Adjustable Timing and Sleep Mode
Ordering Information
PART TEMP RANGE PIN-PACKAGE
DS2484R+T -40NC to +85NC 6 SOT23 (3k pieces)
DS2484Q+T -40NC to +85NC 8 TDFN-EP* (2.5k pieces)
+Denotes a lead(Pb)-free/RoHS-compliant package.
T = Tape and reel.
*EP = Exposed pad.
Package Information
For the latest package outline information and land patterns (footprints), go to www.maximintegrated.com/packages
. Note that a
“+”, “#”, or “-” in the package code indicates RoHS status only.
Package drawings may show a different suffix character, but the drawing pertains to the package regardless of RoHS status.
PACKAGE
TYPE
6 SOT23
8 TDFN-EP
PACKAGE
CODE
U6SN+1
T823+1
OUTLINE
NO.
21-0058
21-0174
LAND
PATTERN NO.
90-0175
90-0091
Maxim Integrated 28
DS2484
Single-Channel 1-Wire Master with Adjustable Timing and Sleep Mode
Revision History
REVISION
NUMBER
0
1
REVISION
DATE
5/13
7/15
DESCRIPTION
Initial release
Updated the Presence-Pulse Detect (PPD) and Short Detected (SD) sections
PAGES
CHANGED
—
9
Maxim Integrated cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim Integrated product. No circuit patent licenses are implied. Maxim Integrated reserves the right to change the circuitry and specifications without notice at any time. The parametric values (min and max limits) shown in the Electrical Characteristics table are guaranteed. Other parametric values quoted in this data sheet are provided for guidance.
Maxim Integrated 160 Rio Robles, San Jose, CA 95134 USA 1-408-601-1000
© 2015 Maxim Integrated Products, Inc.
29
Maxim Integrated and the Maxim Integrated logo are trademarks of Maxim Integrated Products, Inc.
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