Data Sheet | Atmel AVR XMEGA 8/16-bit High Performance Low Power Flash Microcontrollers Datasheet

8/16-bit Atmel AVR XMEGA Microcontrollers

ATxmega32E5 / ATxmega16E5 / ATxmega8E5

DATASHEET

Features

 High-performance, low-power Atmel ® AVR ® XMEGA ® 8/16-bit Microcontroller

 Nonvolatile program and data memories

 8K –32KB of in-system self-programmable flash

 2K – 4KB boot section

 512Bytes – 1KB EEPROM

 1K – 4KB internal SRAM

 Peripheral features

 Four-channel enhanced DMA controller with 8/16-bit address match

 Eight-channel event system

 Asynchronous and synchronous signal routing

 Quadrature encoder with rotary filter

 Three 16-bit timer/counters

 One timer/counter with four output compare or input capture channels

 Two timer/counter with two output compare or input capture channels

 High resolution extension enabling down to 4ns PWM resolution

 Waveform extension for control of motor, LED, lighting, H-bridge, high drives, and more

 Fault extension for safe and deterministic handling and/or shut-down of external driver

 CRC-16 (CRC-CCITT) and CRC-32 (IEEE 802.3) generator

 XMEGA Custom Logic (XCL) module with timer, counter and logic functions

 Two 8-bit timer/counters with capture/compare and 16-bit cascade mode

 Connected to one USART to support custom data frame length

 Connected to I/O pins and event system to do programmable logic functions

 MUX, AND, NAND, OR, NOR, XOR, XNOR, NOT, D-Flip-Flop, D Latch, RS Latch

 Two USARTs with full-duplex and single wire half-duplex configuration

 Master SPI mode

 Support custom protocols with configurable data frame length up to 256-bit

 System wake-up from deep sleep modes when used with internal 8MHz oscillator

 One two-wire interface with dual address match (I 2 C and SMBus compatible)

 Bridge configuration for simultaneous master and slave operation

 Up to 1MHz bus speed support

 One serial peripheral interface (SPI)

 16-bit real time counter with separate oscillator and digital correction

 One sixteen-channel, 12-bit, 300ksps Analog to Digital Converter with:

 Offset and gain correction

 Averaging

 Over-sampling and decimation

 One two-channel, 12-bit, 1Msps Digital to Analog Converter

 Two Analog Comparators with window compare function and current sources

 External interrupts on all general purpose I/O pins

 Programmable watchdog timer with separate on-chip ultra low power oscillator

 QTouch ® library support

 Capacitive touch buttons, sliders and wheels

 Special microcontroller features

 Power-on reset and programmable brown-out detection

 Internal and external clock options with PLL

 Programmable multilevel interrupt controller

 Five sleep modes

 Programming and debug interface

 PDI (Program and Debug Interface)

 I/O and Packages

 26 programmable I/O pins

 7x7mm 32-lead TQFP

 5x5mm 32-lead VQFN

 4x4mm 32-lead UQFN

 Operating Voltage

 1.6 – 3.6V

 Operating frequency

 0 – 12MHz from 1.6V

 0 – 32MHz from 2.7V

Atmel 8153J–AVR-ATxmega8E5-ATxmega16E5-ATxmega32E5_Datasheet–11/2014

Ordering Code

ATxmega8E5-AU

ATxmega8E5-AUR (4)

ATxmega8E5-MU

ATxmega8E5-MUR (4)

ATxmega8E5-M4U

ATxmega8E5-M4UR

(4)

ATxmega16E5-AU

ATxmega16E5-AUR

(4)

ATxmega16E5-MU

ATxmega16E5-MUR

(4)

ATxmega16E5-M4U

ATxmega16E5-M4UR (4)

ATxmega32E5-AU

ATxmega32E5AUR

(4)

ATxmega32E5-MU

ATxmega32E5-MUR

(4)

ATxmega32E5-M4U

ATxmega32E5-M4UR (4)

ATxmega8E5-AN

ATxmega8E5-ANR (4)

ATxmega8E5-MN

ATxmega8E5-MNR (4)

ATxmega8E5-M4N

ATxmega8E5-M4NR

(4)

ATxmega16E5-AN

ATxmega16E5-ANR

(4)

ATxmega16E5-MN

ATxmega16E5-MNR

(4)

ATxmega16E5-M4N

ATxmega16E5-M4NR (4)

1.

Ordering Information

32Z

(5x5mm VQFN)

32MA

(4x4mm UQFN)

32A

(7x7mm TQFP)

32Z

(5x5mm VQFN)

32MA

(4x4mm UQFN)

32A

(7x7mm TQFP)

32Z

(5x5mm VQFN)

32MA

(4x4mm UQFN)

Package

(1)(2)(3)

32A

(7x7mm TQFP)

32Z

(5x5mm VQFN)

32MA

(4x4mm UQFN)

32A

(7x7mm TQFP)

32Z

(5x5mm VQFN)

32MA

(4x4mm UQFN)

32A

(7x7mm TQFP)

Flash

[Bytes]

8K + 2K

16K + 4K

32K + 4K

8K + 2K

16K + 4K

EEPROM

[Bytes]

SRAM

[Bytes]

Speed

[MHz]

Power supply

[V]

Temp.

[°C]

512

512

1K

512

512

1K

2K

4K

1K

2K

32

32

32

32

32

1.6 – 3.6

1.6 – 3.6

1.6 – 3.6

1.6 – 3.6

1.6 – 3.6

-40 – 85

-40 – 85

-40 – 85

-40 – 105

-40 – 105

XMEGA E5 [DATASHEET]

Atmel-8153J–AVR-ATxmega8E5-ATxmega16E5-ATxmega32E5_Datasheet–11/2014

2

Ordering Code

ATxmega32E5-AN

ATxmega32E5ANR

(4)

Package

(1)(2)(3)

32A

(7x7mm TQFP)

Flash

[Bytes]

EEPROM

[Bytes]

SRAM

[Bytes]

Speed

[MHz]

Power supply

[V]

Temp.

[°C]

ATxmega32E5-MN

ATxmega32E5-MNR

(4)

32Z

(5x5mm VQFN)

32K + 4K 1K 4K 32 1.6 – 3.6

-40 – 105

ATxmega32E5-M4N

ATxmega32E5-M4NR (4)

Notes:

32MA

(4x4mm UQFN)

1.

This device can also be supplied in wafer form. Please contact your local Atmel sales office for detailed ordering information.

2.

Pb-free packaging, complies to the European Directive for Restriction of Hazardous Substances (RoHS directive). Also Halide free and fully Green.

3.

For packaging information, see “Packaging Information” on page 68 .

4.

Tape and Reel.

32A

32Z

32MA

Package Type

32-lead, 7x7mm body size, 1.0mm body thickness, 0.8mm lead pitch, thin profile plastic quad flat package (TQFP)

32-lead, 0.5mm pitch, 5x5mm Very Thin quad Flat No Lead Package (VQFN) Sawn

32-lead, 0.4mm pitch, 4x4x0.60mm Ultra Thin Quad No Lead (UQFN) Package

2.

Typical Applications

Board controller

User interface

Communication bridges

Appliances

Sensor control

Industrial control

Battery charger

Motor control

Ballast control, Inverters

Utility metering



3

3.

Pinout and Block Diagram

Power

Ground

Digital function

Analog function / Oscillators

Programming, debug, test

External clock / Crystal pins

General Purpose I/O

Port D

GND 1

PA4 2

PA3 3

PA2 4

AREF

ADC

DAC

AC0:1

PA1 5

PA0 6

PDI 7

PDI / RESET 8

Power

Supervision

Real Time

Counter

EVENT ROUTING NETWORK

DATA BUS

TEMPREF

Watchdog

Oscillator

VREF

Event System

Controller

Interrupt

Controller

Sleep

Controller

OCD

Watchdog

Timer

CRC CPU

Reset

Controller

OSC/CLK

Control

Prog/Debug

Interface

EDMA

Controller

BUS

Controller

EEPROM SRAM FLASH

DATA BUS

Port C

24 PD4

23 PD5

22 PD6

21 PD7

20 PR0

19 PR1

18 GND

17 VCC

Notes: 1. For full details on pinout and alternate pin functions refer to

“Pinout and Pin Functions” on page 57 .



4

4.

Overview

The Atmel AVR XMEGA is a family of low power, high performance, and peripheral rich 8/16-bit microcontrollers based on the AVR enhanced RISC architecture. By executing instructions in a single clock cycle, the AVR XMEGA devices achieve CPU throughput approaching one million instructions per second (MIPS) per megahertz, allowing the system designer to optimize power consumption versus processing speed.

The AVR CPU combines a rich instruction set with 32 general purpose working registers. All 32 registers are directly connected to the arithmetic logic unit (ALU), allowing two independent registers to be accessed in a single instruction, executed in one clock cycle. The resulting architecture is more code efficient while achieving throughputs many times faster than conventional single-accumulator or CISC based microcontrollers.

The AVR XMEGA E5 devices provide the following features: in-system programmable flash with read-while-write capabilities; internal EEPROM and SRAM; four-channel enhanced DMA (EDMA) controller; eight-channel event system with asynchronous event support; programmable multilevel interrupt controller; 26 general purpose I/O lines; CRC-16

(CRC-CCITT) and CRC-32 (IEEE 802.3) generators; one XMEGA Custom Logic module with timer, counter and logic functions (XCL); 16-bit real-time counter (RTC) with digital correction; three flexible, 16-bit timer/counters with compare and PWM channels; two USARTs; one two-wire serial interface (TWI) allowing simultaneous master and slave; one serial peripheral interface (SPI); one sixteen-channel, 12-bit ADC with programmable gain, offset and gain correction, averaging, over-sampling and decimation; one 2-channel 12-bit DAC; two analog comparators (ACs) with window mode and current sources; programmable watchdog timer with separate internal oscillator; accurate internal oscillators with

PLL and prescaler; and programmable brown-out detection.

The program and debug interface (PDI), a fast, two-pin interface for programming and debugging, is available.

The AVR XMEGA E5 devices have five software selectable power saving modes. The idle mode stops the CPU while allowing the SRAM, EDMA controller, event system, interrupt controller, and all peripherals to continue functioning. The power-down mode saves the SRAM and register contents, but stops the oscillators, disabling all other functions until the next TWI, or pin-change interrupt, or reset. In power-save mode, the asynchronous real-time counter continues to run, allowing the application to maintain a timer base while the rest of the device is sleeping. In standby mode, the external crystal oscillator keeps running while the rest of the device is sleeping. This allows very fast startup from the external crystal, combined with low power consumption. In extended standby mode, both the main oscillator and the asynchronous timer continue to run. In each power save, standby or extended standby mode, the low power mode of the internal 8MHz oscillator allows very fast startup time combined with very low power consumption.

To further reduce power consumption, the peripheral clock to each individual peripheral can optionally be stopped in active mode and idle sleep mode and low power mode of the internal 8MHz oscillator can be enabled.

Atmel offers a free QTouch library for embedding capacitive touch buttons, sliders and wheels functionality into AVR microcontrollers. The devices are manufactured using Atmel high-density, nonvolatile memory technology. The program flash memory can be reprogrammed in-system through the PDI. A boot loader running in the device can use any interface to download the application program to the flash memory. The boot loader software in the boot flash section can continue to run. By combining an 8/16-bit RISC CPU with in-system, self-programmable flash, the AVR XMEGA is a powerful microcontroller family that provides a highly flexible and cost effective solution for many embedded applications.

All Atmel AVR XMEGA devices are supported with a full suite of program and system development tools, including C compilers, macro assemblers, program debugger/simulators, programmers, and evaluation kits.



5

5.

Resources

A comprehensive set of development tools, application notes and datasheets are available for download on http://www.atmel.com/avr .

5.1

Recommended Reading





XMEGA E Manual

XMEGA Application Notes

This device data sheet only contains part specific information with a short description of each peripheral and module. The

XMEGA E Manual describes the modules and peripherals in depth. The XMEGA application notes contain example code and show applied use of the modules and peripherals.

All documentations are available from www.atmel.com/avr .

6.

Capacitive Touch Sensing

The Atmel QTouch ® library provides a simple to use solution to realize touch sensitive interfaces on most Atmel AVR ® microcontrollers. The patented charge-transfer signal acquisition offers robust sensing and includes fully debounced reporting of touch keys and includes Adjacent Key Suppression ™ (AKS ™ ) technology for unambiguous detection of key events. The QTouch library includes support for the QTouch and QMatrix acquisition methods.

Touch sensing can be added to any application by linking the appropriate Atmel QTouch library for the AVR

Microcontroller. This is done by using a simple set of APIs to define the touch channels and sensors, and then calling the touch sensing API’s to retrieve the channel information and determine the touch sensor states.

The Atmel QTouch library is FREE and downloadable from the Atmel website at the following location: http://www.atmel.com/tools/QTOUCHLIBRARY.aspx

. For implementation details and other information, refer to the

Atmel QTouch library user guide - also available for download from the Atmel website.



6

7.

CPU

7.1

Features





8/16-bit, high-performance Atmel AVR RISC CPU

142 instructions

















Hardware multiplier

32x8-bit registers directly connected to the ALU

Stack in RAM

Stack pointer accessible in I/O memory space

Direct addressing of up to 16MB of program memory and 16MB of data memory

True 16/24-bit access to 16/24-bit I/O registers

Efficient support for 8-, 16-, and 32-bit arithmetic

Configuration change protection of system-critical features

7.2

Overview

All AVR XMEGA devices use the 8/16-bit AVR CPU. The main function of the CPU is to execute the code and perform all calculations. The CPU is able to access memories, perform calculations, control peripherals, and execute the program in

the flash memory. Interrupt handling is described in a separate section, refer to “Interrupts and Programmable Multilevel

Interrupt Controller” on page 28 .

7.3

Architectural Overview

In order to maximize performance and parallelism, the AVR CPU uses a Harvard architecture with separate memories and buses for program and data. Instructions in the program memory are executed with single-level pipelining. While one instruction is being executed, the next instruction is pre-fetched from the program memory. This enables instructions to be executed on every clock cycle. For details of all AVR instructions, refer to http://www.atmel.com/avr .



7

Figure 7-1.

Block Diagram of the AVR CPU Architecture

The arithmetic logic unit (ALU) supports arithmetic and logic operations between registers or between a constant and a register. Single-register operations can also be executed in the ALU. After an arithmetic operation, the status register is updated to reflect information about the result of the operation.

The ALU is directly connected to the fast-access register file. The 32 x 8-bit general purpose working registers all have single clock cycle access time allowing single-cycle arithmetic logic unit (ALU) operation between registers or between a register and an immediate. Six of the 32 registers can be used as three 16-bit address pointers for program and data space addressing, enabling efficient address calculations.

The memory spaces are linear. The data memory space and the program memory space are two different memory spaces.

The data memory space is divided into I/O registers, SRAM, and memory mapped EEPROM.

All I/O status and control registers reside in the lowest 4KB addresses of the data memory. This is referred to as the I/O memory space. The lowest 64 addresses can be accessed directly, or as the data space locations from 0x00 to 0x3F.

The rest is the extended I/O memory space, ranging from 0x0040 to 0x0FFF. I/O registers here must be accessed as data space locations using load (LD/LDS/LDD) and store (ST/STS/STD) instructions.

The SRAM holds data. Code execution from SRAM is not supported. It can easily be accessed through the five different addressing modes supported in the AVR architecture. The first SRAM address is 0x2000.

Data addresses 0x1000 to 0x1FFF are reserved for EEPROM.

The program memory is divided in two sections, the application program section and the boot program section. Both sections have dedicated lock bits for write and read/write protection. The SPM instruction that is used for selfprogramming of the application flash memory must reside in the boot program section. The application section contains an application table section with separate lock bits for write and read/write protection. The application table section can be used for save storing of nonvolatile data in the program memory.



8

7.4

ALU - Arithmetic Logic Unit

The arithmetic logic unit (ALU) supports arithmetic and logic operations between registers or between a constant and a register. Single-register operations can also be executed. The ALU operates in direct connection with all 32 general purpose registers. In a single clock cycle, arithmetic operations between general purpose registers or between a register and an immediate are executed and the result is stored in the register file. After an arithmetic or logic operation, the status register is updated to reflect information about the result of the operation.

ALU operations are divided into three main categories – arithmetic, logical, and bit functions. Both 8- and 16-bit arithmetic is supported, and the instruction set allows for efficient implementation of 32-bit arithmetic. The hardware multiplier supports signed and unsigned multiplication and fractional format.

7.4.1

Hardware Multiplier

The multiplier is capable of multiplying two 8-bit numbers into a 16-bit result. The hardware multiplier supports different variations of signed and unsigned integer and fractional numbers:

 Multiplication of unsigned integers











Multiplication of signed integers

Multiplication of a signed integer with an unsigned integer

Multiplication of unsigned fractional numbers

Multiplication of signed fractional numbers

Multiplication of a signed fractional number with an unsigned one

A multiplication takes two CPU clock cycles.

7.5

Program Flow

After reset, the CPU starts to execute instructions from the lowest address in the flash program memory ‘0.’ The program counter (PC) addresses the next instruction to be fetched.

Program flow is provided by conditional and unconditional jump and call instructions capable of addressing the whole address space directly. Most AVR instructions use a 16-bit word format, while a limited number use a 32-bit format.

During interrupts and subroutine calls, the return address PC is stored on the stack. The stack is allocated in the general data SRAM, and consequently the stack size is only limited by the total SRAM size and the usage of the SRAM. After reset, the stack pointer (SP) points to the highest address in the internal SRAM. The SP is read/write accessible in the

I/O memory space, enabling easy implementation of multiple stacks or stack areas. The data SRAM can easily be accessed through the five different addressing modes supported in the AVR CPU.

7.6

Status Register

The status register (SREG) contains information about the result of the most recently executed arithmetic or logic instruction. This information can be used for altering program flow in order to perform conditional operations. Note that the status register is updated after all ALU operations, as specified in the instruction set reference. This will in many cases remove the need for using the dedicated compare instructions, resulting in faster and more compact code.

The status register is not automatically stored when entering an interrupt routine nor restored when returning from an interrupt. This must be handled by software.

The status register is accessible in the I/O memory space.

7.7

Stack and Stack Pointer

The stack is used for storing return addresses after interrupts and subroutine calls. It can also be used for storing temporary data. The stack pointer (SP) register always points to the top of the stack. It is implemented as two 8-bit registers that are accessible in the I/O memory space. Data are pushed and popped from the stack using the PUSH and

POP instructions. The stack grows from a higher memory location to a lower memory location. This implies that pushing data onto the stack decreases the SP, and popping data off the stack increases the SP. The SP is automatically loaded



9

after reset, and the initial value is the highest address of the internal SRAM. If the SP is changed, it must be set to point above address 0x2000, and it must be defined before any subroutine calls are executed or before interrupts are enabled.

During interrupts or subroutine calls, the return address is automatically pushed on the stack. The return address can be two or three bytes, depending on program memory size of the device. For devices with 128KB or less of program memory, the return address is two bytes, and hence the stack pointer is decremented/incremented by two. For devices with more than 128KB of program memory, the return address is three bytes, and hence the SP is decremented/incremented by three. The return address is popped off the stack when returning from interrupts using the

RETI instruction, and from subroutine calls using the RET instruction.

The SP is decremented by one when data are pushed on the stack with the PUSH instruction, and incremented by one when data is popped off the stack using the POP instruction.

To prevent corruption when updating the stack pointer from software, a write to SPL will automatically disable interrupts for up to four instructions or until the next I/O memory write.

7.8

Register File

The register file consists of 32 x 8-bit general purpose working registers with single clock cycle access time. The register file supports the following input/output schemes:

 One 8-bit output operand and one 8-bit result input







Two 8-bit output operands and one 8-bit result input

Two 8-bit output operands and one 16-bit result input

One 16-bit output operand and one 16-bit result input

Six of the 32 registers can be used as three 16-bit address register pointers for data space addressing, enabling efficient address calculations. One of these address pointers can also be used as an address pointer for lookup tables in flash program memory.



10

8.

Memories

8.1

Features









Flash program memory

















One linear address space

In-system programmable

Self-programming and boot loader support

Application section for application code

Application table section for application code or data storage

Boot section for application code or bootloader code

Separate read/write protection lock bits for all sections

Built in fast CRC check of a selectable flash program memory section

Data memory















One linear address space

Single-cycle access from CPU

SRAM

EEPROM





Byte and page accessible

Memory mapped for direct load and store

I/O memory

 Configuration and status registers for all peripherals and modules

 Four bit-accessible general purpose registers for global variables or flags

Bus arbitration

 Deterministic handling of priority between CPU, EDMA controller, and other bus masters

Separate buses for SRAM, EEPROM, and I/O memory

 Simultaneous bus access for CPU and EDMA controller

Production signature row memory for factory programmed data







ID for each microcontroller device type

Serial number for each device

Calibration bytes for factory calibrated peripherals

User signature row







One flash page in size

Can be read and written from software

Content is kept after chip erase

8.2

Overview

The Atmel AVR architecture has two main memory spaces, the program memory and the data memory. Executable code can reside only in the program memory, while data can be stored in the program memory and the data memory. The data memory includes the internal SRAM, and EEPROM for nonvolatile data storage. All memory spaces are linear and require no memory bank switching. Nonvolatile memory (NVM) spaces can be locked for further write and read/write operations. This prevents unrestricted access to the application software.

A separate memory section contains the fuse bytes. These are used for configuring important system functions, and can only be written by an external programmer.

The available memory size configurations are shown in

“Ordering Information” on page 2”

. In addition, each device has a

Flash memory signature row for calibration data, device identification, serial number etc.

8.3

Flash Program Memory

The Atmel AVR XMEGA devices contain on-chip, in-system reprogrammable flash memory for program storage. The flash memory can be accessed for read and write from an external programmer through the PDI or from application software running in the device.



11

All AVR CPU instructions are 16 or 32 bits wide, and each flash location is 16 bits wide. The flash memory is organized in two main sections, the application section and the boot loader section. The sizes of the different sections are fixed, but device-dependent. These two sections have separate lock bits, and can have different levels of protection. The store program memory (SPM) instruction, which is used to write to the flash from the application software, will only operate when executed from the boot loader section.

The application section contains an application table section with separate lock settings. This enables safe storage of nonvolatile data in the program memory.

Figure 8-1.

Flash Program Memory (hexadecimal address)

ATxmega32E5

0

Word Address

ATxmega16E5

0

ATxmega8E5

0 Application Section

(32K/16K/8K)

...

37FF

3800

3FFF

4000

47FF

/

/

/

/

/

17FF

1800

1FFF

2000

27FF

/

/

/

/

/

BFF

C00

FFF

1000

13FF

Application Table Section

(4K/4K/2K)

Boot Section

(4K/4K/2K)

8.3.1

Application Section

The Application section is the section of the flash that is used for storing the executable application code. The protection level for the application section can be selected by the boot lock bits for this section. The application section can not store any boot loader code since the SPM instruction cannot be executed from the application section.

8.3.2

Application Table Section

The application table section is a part of the application section of the flash memory that can be used for storing data.

The size is identical to the boot loader section. The protection level for the application table section can be selected by the boot lock bits for this section. The possibilities for different protection levels on the application section and the application table section enable safe parameter storage in the program memory. If this section is not used for data, application code can reside here.

8.3.3

Boot Loader Section

While the application section is used for storing the application code, the boot loader software must be located in the boot loader section because the SPM instruction can only initiate programming when executing from this section. When programming, the CPU is halted, waiting for the flash operation to complete. The SPM instruction can access the entire flash, including the boot loader section itself. The protection level for the boot loader section can be selected by the boot loader lock bits. If this section is not used for boot loader software, application code can be stored here.

8.3.4

Production Signature Row

The production signature row is a separate memory section for factory programmed data. It contains calibration data for functions such as oscillators and analog modules. Some of the calibration values will be automatically loaded to the corresponding module or peripheral unit during reset. Other values must be loaded from the signature row and written to



12

the corresponding peripheral registers from software. For details on calibration conditions, refer to

“Electrical

Characteristics” on page 71

.

The production signature row also contains an ID that identifies each microcontroller device type and a serial number for each manufactured device. The serial number consists of the production lot number, wafer number, and wafer coordinates for the device. The device ID for the available devices is shown in

Table 8-1 .

The production signature row cannot be written or erased, but it can be read from application software and external programmers.

Table 8-1.

Device ID Bytes for Atmel AVR XMEGA E5 Devices

Device

ATxmega32E5

ATxmega16E5

ATxmega8E5

Byte 2

4C

45

41

Device ID bytes

Byte 1

95

94

93

Byte 0

1E

1E

1E

8.3.5

User Signature Row

The user signature row is a separate memory section that is fully accessible (read and write) from application software and external programmers. It is one flash page in size, and is meant for static user parameter storage, such as calibration data, custom serial number, identification numbers, random number seeds, etc. This section is not erased by chip erase commands that erase the flash, and requires a dedicated erase command. This ensures parameter storage during multiple program/erase operations and on-chip debug sessions.

8.4

Fuses and Lock Bits

The fuses are used to configure important system functions, and can only be written from an external programmer. The application software can read the fuses. The fuses are used to configure reset sources such as brownout detector and watchdog, startup configuration, etc.

The lock bits are used to set protection levels for the different flash sections (i.e., if read and/or write access should be blocked). Lock bits can be written by external programmers and application software, but only to stricter protection levels.

Chip erase is the only way to erase the lock bits. To ensure that flash contents are protected even during chip erase, the lock bits are erased after the rest of the flash memory has been erased.

An un-programmed fuse or lock bit will have the value one, while a programmed fuse or lock bit will have the value zero.

Both fuses and lock bits are reprogrammable like the flash program memory.



13

8.5

Data Memory

The data memory contains the I/O memory, internal SRAM and EEPROM. The data memory is organized as one continuous memory section, see

Table 8-2 on page 15 . To simplify development, I/O Memory, EEPROM and SRAM will

always have the same start addresses for all XMEGA devices.

Figure 8-2.

Data Memory Map (hexadecimal value)

Byte Address

0

FFF

1000

13FF

ATxmega32E5

I/O Registers (4K)

EEPROM (1K)

Byte Address

0

FFF

1000

11FF

RESERVED

2000

2FFF

Internal SRAM (4K)

2000

27FF

ATxmega16E5

I/O Registers (4K)

EEPROM (512B)

RESERVED

Internal SRAM (2K)

Byte Address

0

FFF

1000

11FF

ATxmega8E5

I/O Registers (4K)

EEPROM (512B)

RESERVED

2000

27FF

Internal SRAM (2K)

8.6

EEPROM

Atmel AVR XMEGA E5 devices have EEPROM for nonvolatile data storage. It is memory mapped and accessed in normal data space. The EEPROM supports both byte and page access. EEPROM allows highly efficient EEPROM reading and EEPROM buffer loading. When doing this, EEPROM is accessible using load and store instructions.

EEPROM will always start at hexadecimal address 0x1000.

8.7

I/O Memory

The status and configuration registers for peripherals and modules, including the CPU, are addressable through I/O memory locations. All I/O locations can be accessed by the load (LD/LDS/LDD) and store (ST/STS/STD) instructions, which are used to transfer data between the 32 registers in the register file and the I/O memory. The IN and OUT instructions can address I/O memory locations in the range of 0x00 to 0x3F directly. In the address range 0x00 - 0x1F, single-cycle instructions for manipulation and checking of individual bits are available.

The I/O memory address for all peripherals and modules in XMEGA E5 is shown in the “Peripheral Module Address Map” on page 61

.

8.7.1

General Purpose I/O Registers

The lowest four I/O memory addresses are reserved as general purpose I/O registers. These registers can be used for storing global variables and flags, as they are directly bit-accessible using the SBI, CBI, SBIS, and SBIC instructions.

8.8

Data Memory and Bus Arbitration

Since the data memory is organized as three separate sets of memories, the different bus masters (CPU, EDMA controller read and EDMA controller write, etc.) can access different memory sections at the same time.

8.9

Memory Timing

Read and write access to the I/O memory takes one CPU clock cycle. A write to SRAM takes one cycle, and a read from

SRAM takes two cycles. For burst read (EDMA), new data are available every cycle. EEPROM page load (write) takes one cycle, and three cycles are required for read. For burst read, new data are available every second cycle. Refer to the instruction summary for more details on instructions and instruction timing.



14

8.10

Device ID and Revision

Each device has a three-byte device ID. This ID identifies Atmel as the manufacturer of the device and the device type. A separate register contains the revision number of the device.

8.11

I/O Memory Protection

Some features in the device are regarded as critical for safety in some applications. Due to this, it is possible to lock the

I/O register related to the clock system, the event system, and the waveform extensions. As long as the lock is enabled, all related I/O registers are locked and they cannot be written from the application software. The lock registers themselves are protected by the configuration change protection mechanism.

8.12

Flash and EEPROM Page Size

The flash program memory and EEPROM data memory are organized in pages. The pages are word accessible for the flash and byte accessible for the EEPROM.

Table 8-2

shows the Flash Program Memory organization and Program Counter (PC) size. Flash write and erase operations are performed on one page at a time, while reading the Flash is done one byte at a time. For Flash access the

Z-pointer (Z[m:n]) is used for addressing. The most significant bits in the address (FPAGE) give the page number and the least significant address bits (FWORD) give the word in the page.

Table 8-2.

Number of Words and Pages in the Flash

Devices

ATxmega32E5

ATxmega16E5

ATxmega8E5

PC size bits

15

14

13

Flash size bytes

Page Size words

32K+4K

16K+4K

8K+2K

64

64

64

FWORD

Z[6:0]

Z[6:0]

Z[6:0]

FPAGE

Z[14:7]

Z[13:7]

Z[12:7]

Size

Application

No. of pages

32K

16K

256

128

8K 64

Size

4K

4K

2K

Boot

No. of pages

32

32

16

Table 8-3

shows EEPROM memory organization for the Atmel AVR XMEGA E5 devices. EEPROM write and erase operations can be performed one page or one byte at a time, while reading the EEPROM is done one byte at a time. For

EEPROM access the NVM address register (ADDR[m:n]) is used for addressing. The most significant bits in the address

(E2PAGE) give the page number and the least significant address bits (E2BYTE) give the byte in the page.

Table 8-3.

Number of Words and Pages in the EEPROM

Devices

ATxmega32E5

ATxmega16E5

ATxmega8E5

EEPROM

Size

1K

512Bytes

512Bytes bytes

Page Size

32

32

32

E2BYTE

ADDR[4:0]

ADDR[4:0]

ADDR[4:0]

E2PAGE

ADDR[10:5]

ADDR[10:5]

ADDR[10:5]

32

16

16

No. of Pages



15

9.

EDMA – Enhanced DMA Controller

9.1

Features









The EDMA Controller allows data transfers with minimal CPU intervention







 from data memory to data memory from data memory to peripheral from peripheral to data memory from peripheral to peripheral

Four peripheral EDMA channels with separate:







 transfer triggers interrupt vectors addressing modes data matching

Two peripheral channels can be combined to one standard channel with separate:







 transfer triggers interrupt vectors addressing modes data search

Programmable channel priority











From 1byte to 128KB of data in a single transaction





Up to 64K block transfer with repeat

1 or 2 bytes burst transfers

Multiple addressing modes





Static

Increment

Optional reload of source and destination address at the end of each







Burst

Block

Transaction

Optional Interrupt on end of transaction

Optional connection to CRC Generator module for CRC on EDMA data

9.2

Overview

The four-channel enhanced direct memory access (EDMA) controller can transfer data between memories and peripherals, and thus offload these tasks from the CPU. It enables high data transfer rates with minimum CPU intervention, and frees up CPU time. The four EDMA channels enable up to four independent and parallel transfers.

The EDMA controller can move data between SRAM and peripherals, between SRAM locations and directly between peripheral registers. With access to all peripherals, the EDMA controller can handle automatic transfer of data to/from communication modules. The EDMA controller can also read from EEPROM memory.

Data transfers are done in continuous bursts of 1 or 2 bytes. They build block transfers of configurable size from 1 byte to

64KB. Repeat option can be used to repeat once each block transfer for single transactions up to 128KB. Source and destination addressing can be static or incremental. Automatic reload of source and/or destination addresses can be done after each burst or block transfer, or when a transaction is complete. Application software, peripherals, and events can trigger EDMA transfers.

The four EDMA channels have individual configuration and control settings. This includes source, destination, transfer triggers, and transaction sizes. They have individual interrupt settings. Interrupt requests can be generated when a transaction is complete or when the EDMA controller detects an error on an EDMA channel.

To enable flexibility in transfers, channels can be interlinked so that the second takes over the transfer when the first is finished.



16

The EDMA controller supports extended features such as double buffering, data match for peripherals and data search for SRAM or EEPROM.

The EDMA controller supports two types of channel. Each channel type can be selected individually.



17

10.

Event System

10.1

Features









System for direct peripheral-to-peripheral communication and signaling

Peripherals can directly send, receive, and react to peripheral events









CPU and EDMA controller independent operation

100% predictable signal timing

Short and guaranteed response time

Synchronous and asynchronous event routing

Eight event channels for up to eight different and parallel signal routing and configurations

Events can be sent and/or used by most peripherals, clock system, and software





Additional functions include







Quadrature decoder with rotary filtering

Digital filtering of I/O pin state with configurable filter

Simultaneous synchronous and asynchronous events provided to peripheral

Works in all sleep modes

10.2

Overview

The event system enables direct peripheral-to-peripheral communication and signaling. It allows a change in one peripheral’s state to automatically trigger actions in other peripherals. It is designed to provide a predictable system for short and predictable response times between peripherals. It allows for autonomous peripheral control and interaction without the use of interrupts, CPU, or EDMA controller resources, and is thus a powerful tool for reducing the complexity, size and execution time of application code. It allows for synchronized timing of actions in several peripheral modules.

The event system enables also asynchronous event routing for instant actions in peripherals.

A change in a peripheral’s state is referred to as an event, and usually corresponds to the peripheral’s interrupt conditions. Events can be directly passed to other peripherals using a dedicated routing network called the event routing network. How events are routed and used by the peripherals is configured in software.

Figure 10-1 shows a basic diagram of all connected peripherals. The event system can directly connect together analog

and digital converters, analog comparators, I/O port pins, the real-time counter, timer/counters, IR communication module (IRCOM), and XMEGA Custom Logic (programmable logic) block (XCL). It can also be used to trigger EDMA transactions (EDMA controller). Events can also be generated from software and peripheral clock.



18

Figure 10-1. Event System Overview and Connected Peripherals

CPU /

Software

EDMA

Controller

Event Routing Network

ADC

AC

DAC

Event

System

Controller clk

PER

Prescaler

Real Time

Counter

Timer /

Counters

XMEGA

Custom Logic

IRCOM Port Pins

The event routing network consists of eight software-configurable multiplexers that control how events are routed and used. These are called event channels, and allow up to eight parallel event configurations and routing. The maximum routing latency of an external event is two peripheral clock cycles due to re-synchronization, but several peripherals can directly use the asynchronous event without any clock delay. The event system works in all power sleep modes, but only asynchronous events can be routed in sleep modes where the system clock is not available.



19

11.

System Clock and Clock options

11.1

Features





Fast start-up time

Safe run-time clock switching















Internal Oscillators:









32MHz run-time calibrated and tuneable oscillator

8MHz calibrated oscillator with 2MHz output option and fast start-up

32.768kHz calibrated oscillator

32kHz Ultra Low Power (ULP) oscillator with 1kHz output

External clock options







0.4 - 16MHz Crystal Oscillator

32kHz crystal oscillator with digital correction

External clock input in selectable pin location

PLL with 20 - 128MHz output frequency





Internal and external clock options and 1 to 31x multiplication

Lock detector

Clock Prescalers with 1x to 2048x division

Fast peripheral clocks running at two and four times the CPU clock frequency

Automatic Run-Time Calibration of the 32MHz internal oscillator

External oscillator and PLL lock failure detection with optional non maskable interrupt

11.2

Overview

Atmel AVR XMEGA E5 devices have a flexible clock system supporting a large number of clock sources. It incorporates both accurate internal oscillators and external crystal oscillator and resonator support. A high-frequency phase locked loop (PLL) and clock prescalers can be used to generate a wide range of clock frequencies. A calibration feature (DFLL) is available, and can be used for automatic run-time calibration of the 32MHz internal oscillator to remove frequency drift over voltage and temperature. An oscillator failure monitor can be enabled to issue a nonmaskable interrupt and switch to the internal oscillator if the external oscillator or PLL fails.

When a reset occurs, all clock sources except the 32kHz ultra low power oscillator are disabled. After reset, the device will always start up running from the 2MHz output of the 8MHz internal oscillator. During normal operation, the system clock source and prescalers can be changed from software at any time.

Figure 11-1 on page 21 presents the principal clock system in the XMEGA E5 family of devices. Not all of the clocks need

to be active at a given time. The clocks for the CPU and peripherals can be stopped using sleep modes and power reduction registers, as described in

“Power Management and Sleep Modes” on page 23 .



20

Figure 11-1. The Clock System, Clock Sources, and Clock Distribution

Real Time

Counter

Peripherals RAM clk

PER4 clk

PER2 clk

PER clk

RTC

AVR CPU

Non-Volatile

Memory clk

CPU

Brown-out

Detector

Watchdog

Timer

RTCSRC

System Clock Prescalers clk

SYS

System Clock Multiplexer

(SCLKSEL)

PLL

PLLSRC

XOSCSEL

32 kHz

Int. ULP

32.768 kHz

Int. OSC

32.768 kHz

TOSC

0.4 – 16 MHz

XTAL

32 MHz

Int. Osc

8 MHz

Int. Osc

11.3

Clock Sources

The clock sources are divided in two main groups: internal oscillators and external clock sources. Most of the clock sources can be directly enabled and disabled from software, while others are automatically enabled or disabled, depending on peripheral settings. After reset, the device starts up running from the 2MHz output of the 8MHz internal oscillator. The other clock sources, DFLL and PLL, are turned off by default.

The internal oscillators do not require any external components to run. For details on characteristics and accuracy of the internal oscillators, refer to the device datasheet.

11.3.1 32kHz Ultra Low Power Internal Oscillator

This oscillator provides an approximate 32kHz clock. The 32kHz ultra low power (ULP) internal oscillator is a very low power clock source, and it is not designed for high accuracy. The oscillator employs a built-in prescaler that provides a

1kHz output. The oscillator is automatically enabled/disabled when it is used as clock source for any part of the device.

This oscillator can be selected as the clock source for the RTC.



21

11.3.2 32.768kHz Calibrated Internal Oscillator

This oscillator provides an approximate 32.768kHz clock. It is calibrated during production to provide a default frequency close to its nominal frequency. The calibration register can also be written from software for run-time calibration of the oscillator frequency. The oscillator employs a built-in prescaler, which provides both a 32.768kHz output and a 1.024kHz output.

11.3.3 32.768kHz Crystal Oscillator

A 32.768kHz crystal oscillator can be connected between the TOSC1 and TOSC2 pins and enables a dedicated low frequency oscillator input circuit. A low power mode with reduced voltage swing on TOSC2 is available. This oscillator can be used as a clock source for the system clock and RTC, and as the DFLL reference clock.

11.3.4 0.4 - 16MHz Crystal Oscillator

This oscillator can operate in four different modes optimized for different frequency ranges, all within 0.4 - 16MHz.

11.3.5 8MHz Calibrated Internal Oscillator

The 8MHz calibrated internal oscillator is the default system clock source after reset. It is calibrated during production to provide a default frequency close to its nominal frequency. The calibration register can also be written from software for run-time calibration of the oscillator frequency. The oscillator employs a built-in prescaler, with 2MHz output. The default output frequency at start-up and after reset is 2MHz. A low power mode option can be used to enable fast system wakeup from power-save mode. In all other modes, the low power mode can be enabled to significantly reduce the power consumption of the internal oscillator.

11.3.6 32MHz Run-time Calibrated Internal Oscillator

The 32MHz run-time calibrated internal oscillator is a high-frequency oscillator. It is calibrated during production to provide a default frequency close to its nominal frequency. A digital frequency looked loop (DFLL) can be enabled for automatic run-time calibration of the oscillator to compensate for temperature and voltage drift and optimize the oscillator accuracy. This oscillator can also be adjusted and calibrated to any frequency between 30 and 55MHz.

11.3.7 External Clock Sources

The XTAL1 and XTAL2 pins can be used to drive an external oscillator, either a quartz crystal or a ceramic resonator.

XTAL1 or pin 4 of port C (PC4) can be used as input for an external clock signal. The TOSC1 and TOSC2 pins are dedicated to driving a 32.768kHz crystal oscillator.

11.3.8 PLL with 1x-31x Multiplication Factor

The built-in phase locked loop (PLL) can be used to generate a high-frequency system clock. The PLL has a userselectable multiplication factor of from 1 to 31. In combination with the prescalers, this gives a wide range of output frequencies from all clock sources.



22

12.

Power Management and Sleep Modes

12.1

Features







Power management for adjusting power consumption and functions

Five sleep modes











Idle

Power down

Power save

Standby

Extended standby

Power reduction register to disable clock and turn off unused peripherals in active and idle modes

12.2

Overview

Various sleep modes and clock gating are provided in order to tailor power consumption to application requirements.

This enables the Atmel AVR XMEGA microcontroller to stop unused modules to save power.

All sleep modes are available and can be entered from active mode. In active mode, the CPU is executing application code. When the device enters sleep mode, program execution is stopped and interrupts or a reset is used to wake the device again. The application code decides which sleep mode to enter and when. Interrupts from enabled peripherals and all enabled reset sources can restore the microcontroller from sleep to active mode.

In addition, power reduction registers provide a method to stop the clock to individual peripherals from software. When this is done, the current state of the peripheral is frozen, and there is no power consumption from that peripheral. This reduces the power consumption in active mode and idle sleep modes and enables much more fine-tuned power management than sleep modes alone.

12.3

Sleep Modes

Sleep modes are used to shut down modules and clock domains in the microcontroller in order to save power. XMEGA microcontrollers have five different sleep modes tuned to match the typical functional stages during application execution. A dedicated sleep instruction (SLEEP) is available to enter sleep mode. Interrupts are used to wake the device from sleep, and the available interrupt wake-up sources are dependent on the configured sleep mode. When an enabled interrupt occurs, the device will wake up and execute the interrupt service routine before continuing normal program execution from the first instruction after the SLEEP instruction. If other, higher priority interrupts are pending when the wake-up occurs, their interrupt service routines will be executed according to their priority before the interrupt service routine for the wake-up interrupt is executed. After wake-up, the CPU is halted for four cycles before execution starts.

The content of the register file, SRAM and registers are kept during sleep. If a reset occurs during sleep, the device will reset, start up, and execute from the reset vector.

12.3.1 Idle Mode

In idle mode the CPU and nonvolatile memory are stopped (note that any ongoing programming will be completed), but all peripherals, including the interrupt controller, event system and EDMA controller are kept running. Any enabled interrupt will wake the device.

12.3.2 Power-down Mode

In power-down mode, all clocks, including the real-time counter clock source, are stopped. This allows operation only of asynchronous modules that do not require a running clock. The only interrupts that can wake up the MCU are the twowire interface address match interrupt and asynchronous port interrupts.



23

12.3.3 Power-save Mode

Power-save mode is identical to power down, with one exception. If the real-time counter (RTC) is enabled, it will keep running during sleep, and the device can also wake up from either an RTC overflow or compare match interrupt. Low power mode option of 8MHz internal oscillator enables instant oscillator wake-up time. This reduces the MCU wake-up time or enables the MCU wake-up from UART bus.

12.3.4 Standby Mode

Standby mode is identical to power down, with the exception that the enabled system clock sources are kept running while the CPU, peripheral, and RTC clocks are stopped. This reduces the wake-up time. The low power option of 8MHz internal oscillator can be enabled to further reduce the power consumption.

12.3.5 Extended Standby Mode

Extended standby mode is identical to power-save mode, with the exception that the enabled system clock sources are kept running while the CPU and peripheral clocks are stopped. This reduces the wake-up time. The low power option of

8MHz internal oscillator can be enabled to further reduce the power consumption.



24

13.

System Control and Reset

13.1

Features









Reset the microcontroller and set it to initial state when a reset source goes active

Multiple reset sources that cover different situations













Power-on reset

External reset

Watchdog reset

Brownout reset

PDI reset

Software reset

Asynchronous operation

 No running system clock in the device is required for reset

Reset status register for reading the reset source from the application code

13.2

Overview

The reset system issues a microcontroller reset and sets the device to its initial state. This is for situations where operation should not start or continue, such as when the microcontroller operates below its power supply rating. If a reset source goes active, the device enters and is kept in reset until all reset sources have released their reset. The I/O pins are immediately tri-stated. The program counter is set to the reset vector location, and all I/O registers are set to their initial values. The SRAM content is kept. However, if the device accesses the SRAM when a reset occurs, the content of the accessed location can not be guaranteed.

After reset is released from all reset sources, the default oscillator is started and calibrated before the device starts running from the reset vector address. By default, this is the lowest program memory address, 0, but it is possible to move the reset vector to the lowest address in the boot section.

The reset functionality is asynchronous, and so no running system clock is required to reset the device. The software reset feature makes it possible to issue a controlled system reset from the user software.

The reset status register has individual status flags for each reset source. It is cleared at power-on reset, and shows which sources have issued a reset since the last power-on.

13.3

Reset Sequence

A reset request from any reset source will immediately reset the device and keep it in reset as long as the request is active. When all reset requests are released, the device will go through three stages before the device starts running again:

 Reset counter delay





Oscillator startup

Oscillator calibration

If another reset requests occurs during this process, the reset sequence will start over again.

13.4

Reset Sources

13.4.1 Power-on Reset

A power-on reset (POR) is generated by an on-chip detection circuit. The POR is activated when the V

CC rises and reaches the POR threshold voltage (V

POT

), and this will start the reset sequence.

The POR is also activated to power down the device properly when the V

CC falls and drops below the V

POT level. The

V

POT level is higher for falling V

CC than for rising V

CC

. Consult the datasheet for POR characteristics data.



25

13.4.2 Brownout Detection

The on-chip brownout detection (BOD) circuit monitors the V

CC level during operation by comparing it to a fixed, programmable level that is selected by the BODLEVEL fuses. If disabled, BOD is forced on at the lowest level during chip erase and when the PDI is enabled.

13.4.3 External Reset

The external reset circuit is connected to the external RESET pin. The external reset will trigger when the RESET pin is driven below the RESET pin threshold voltage, V

RST

, for longer than the minimum pulse period, t

EXT

. The reset will be held as long as the pin is kept low. The RESET pin includes an internal pull-up resistor.

13.4.4 Watchdog Reset

The watchdog timer (WDT) is a system function for monitoring correct program operation. If the WDT is not reset from the software within a programmable timeout period, a watchdog reset will be given. The watchdog reset is active for one to two clock cycles of the 2MHz internal oscillator. For more details, see

“WDT – Watchdog Timer” on page 27

.

13.4.5 Software Reset

The software reset makes it possible to issue a system reset from software by writing to the software reset bit in the reset control register. The reset will be issued within two CPU clock cycles after writing the bit. It is not possible to execute any instruction from when a software reset is requested until it is issued.

13.4.6 Program and Debug Interface Reset

The program and debug interface reset contains a separate reset source that is used to reset the device during external programming and debugging. This reset source is accessible only from external debuggers and programmers.



26

14.

WDT – Watchdog Timer

14.1

Features





Issues a device reset if the timer is not reset before its timeout period

Asynchronous operation from dedicated oscillator









1kHz output of the 32kHz ultra low power oscillator

11 selectable timeout periods, from 8ms to 8s

Two operation modes:





Normal mode

Window mode

Configuration lock to prevent unwanted changes

14.2

Overview

The watchdog timer (WDT) is a system function for monitoring correct program operation. It makes it possible to recover from error situations such as runaway or deadlocked code. The WDT is a timer, configured to a predefined timeout period, and is constantly running when enabled. If the WDT is not reset within the timeout period, it will issue a microcontroller reset. The WDT is reset by executing the WDR (watchdog timer reset) instruction from the application code.

The window mode makes it possible to define a time slot or window inside the total timeout period during which WDT must be reset. If the WDT is reset outside this window, either too early or too late, a system reset will be issued.

Compared to the normal mode, this can also catch situations where a code error causes constant WDR execution.

The WDT will run in active mode and all sleep modes, if enabled. It is asynchronous, runs from a CPU-independent clock source, and will continue to operate to issue a system reset even if the main clocks fail.

The configuration change protection mechanism ensures that the WDT settings cannot be changed by accident. For increased safety, a fuse for locking the WDT settings is also available.



27

15.

Interrupts and Programmable Multilevel Interrupt Controller

15.1

Features





Short and predictable interrupt response time

Separate interrupt configuration and vector address for each interrupt





Programmable multilevel interrupt controller









Interrupt prioritizing according to level and vector address

Three selectable interrupt levels for all interrupts: low, medium, and high

Selectable, round-robin priority scheme within low-level interrupts

Non-maskable interrupts for critical functions

Interrupt vectors optionally placed in the application section or the boot loader section

15.2

Overview

Interrupts signal a change of state in peripherals, and this can be used to alter program execution. Peripherals can have one or more interrupts, and all are individually enabled and configured. When an interrupt is enabled and configured, it will generate an interrupt request when the interrupt condition is present. The programmable multilevel interrupt controller (PMIC) controls the handling and prioritizing of interrupt requests. When an interrupt request is acknowledged by the PMIC, the program counter is set to point to the interrupt vector, and the interrupt handler can be executed.

All peripherals can select between three different priority levels for their interrupts: low, medium, and high. Interrupts are prioritized according to their level and their interrupt vector address. Medium-level interrupts will interrupt low-level interrupt handlers. High-level interrupts will interrupt both medium- and low-level interrupt handlers. Within each level, the interrupt priority is decided from the interrupt vector address, where the lowest interrupt vector address has the highest interrupt priority. Low-level interrupts have an optional round-robin scheduling scheme to ensure that all interrupts are serviced within a certain amount of time.

Non-maskable interrupts (NMI) are also supported, and can be used for system critical functions.

15.3

Interrupt Vectors

The interrupt vector is the sum of the peripheral’s base interrupt address and the offset address for specific interrupts in each peripheral. The base addresses for the Atmel AVR XMEGA E5 devices are shown in

Table 15-1 .

Offset addresses for each interrupt available in the peripheral are described for each peripheral in the XMEGA AU manual. For peripherals or modules that have only one interrupt, the interrupt vector is shown in

Table 15-1 . The program address is the word

address.

Table 15-1. Peripheral Module Address Map

Program address

(base address)

0x0000

0x0002

0x0004

0x0006

0x000E

0x0012

0x0014

0x0018

Source

RESET

OSCF_INT_vect

PORTR_INT_vect

EDMA_INT_base

RTC_INT_base

PORTC_INT_vect

TWIC_INT_base

TCC4_INT_base

Interrupt description

Crystal oscillator failure and PLL lock failure interrupt vector (NMI)

Port R Interrupt vector

EDMA Controller Interrupt base

Real time counter interrupt base

Port C interrupt vector

Two-wire interface on Port C interrupt base

Timer/counter 4 on port C interrupt base



28

Program address

(base address)

0x0024

0x002C

0x002E

0x0034

0x0038

0x003C

0x003E

0x0044

0x0046

0x0048

0x0050

Source

TCC5_INT_base

SPIC_INT_vect

USARTC0_INT_base

NVM_INT_base

XCL_INT_base

PORTA_INT_vect

ACA_INT_base

ADCA_INT_base

PORTD_INT_vect

TCD5_INT_base

USARTD0_INT_base

Interrupt description

Timer/counter 5 on port C interrupt base

SPI on port C interrupt vector

USART 0 on port C interrupt base

Non-Volatile Memory interrupt base

XCL (programmable logic) module interrupt base

Port A interrupt vector

Analog comparator on Port A interrupt base

Analog to digital converter on Port A interrupt base

Port D interrupt vector

Timer/counter 5 on port D interrupt base

USART 0 on port D interrupt base



29

16.

I/O Ports

16.1

Features









26 general purpose input and output pins with individual configuration

Output driver with configurable driver and pull settings:











Totem-pole

Wired-AND

Wired-OR

Bus-keeper

Inverted I/O

Input with asynchronous sensing with interrupts and events









Sense both edges

Sense rising edges

Sense falling edges

Sense low level

Optional pull-up and pull-down resistor on input and Wired-OR/AND configurations

















Optional slew rate control per I/O port

Asynchronous pin change sensing that can wake the device from all sleep modes

One port interrupt with pin masking per I/O port

Efficient and safe access to port pins







Hardware read-modify-write through dedicated toggle/clear/set registers

Configuration of multiple pins in a single operation

Mapping of port registers into bit-accessible I/O memory space

Peripheral clocks output on port pin

Real-time counter clock output to port pin

Event channels can be output on port pin

Remapping of digital peripheral pin functions





Selectable USART and timer/counters input/output pin locations

Selectable Analog Comparator output pin locations

16.2

Overview

One port consists of up to eight pins ranging from pin 0 to 7. Each port pin can be configured as input or output with configurable driver and pull settings. They also implement asynchronous input sensing with interrupt and events for selectable pin change conditions.

Asynchronous pin-change sensing means that a pin change can wake the device from all sleep modes, including the modes where no clocks are running.

All functions are individual and configurable per pin, but several pins can be configured in a single operation. The pins have hardware read-modify-write (RMW) functionality for safe and correct change of drive value and/or pull resistor configuration. The direction of one port pin can be changed without unintentionally changing the direction of any other pin.

The port pin configuration also controls input and output selection of other device functions. It is possible to have both the peripheral clock and the real-time clock output to a port pin, and available for external use. The same applies to events from the event system that can be used to synchronize and control external functions. Other digital peripherals, such as

USART, timer/counters, and analog comparator output can be remapped to selectable pin locations in order to optimize pin-out versus application needs.

The notations of the ports are PORTA, PORTC, PORTD, and PORTR.



30

16.3

Output Driver

All port pins (Pxn) have programmable output configuration. The port pins also have configurable slew rate limitation to reduce electromagnetic emission.

16.3.1 Push-pull

Figure 16-1. I/O Configuration - Totem-pole

DIRxn

OUTxn Pxn

INxn

16.3.2 Pull-down

Figure 16-2. I/O Configuration - Totem-pole with Pull-down (on input)

DIRxn

OUTxn Pxn

INxn

16.3.3 Pull-up

Figure 16-3. I/O Configuration - Totem-pole with Pull-up (on input)

DIRxn

OUTxn

INxn

Pxn



31

16.3.4 Bus-keeper

The bus-keeper’s weak output produces the same logical level as the last output level. It acts as a pull-up if the last level was ‘1’, and pull-down if the last level was ‘0’.

Figure 16-4. I/O Configuration - Totem-pole with Bus-keeper

DIRxn

OUTxn

INxn

16.3.5 Others

Figure 16-5. Output Configuration - Wired-OR with Optional Pull-down

OUTxn

Pxn

Pxn

INxn

Figure 16-6. I/O Configuration - Wired-AND with Optional Pull-up

INxn

OUTxn

Pxn



32

16.4

Input Sensing

Input sensing is synchronous or asynchronous depending on the enabled clock for the ports, and the configuration is

shown in Figure 16-7 .

Figure 16-7. Input Sensing System Overview

Asynchronous sensing

EDGE

DETECT

Interrupt

Control

IRQ

Synchronous sensing

Pxn

Synchronizer

INn

D Q D Q

R R

EDGE

DETECT

Synchronous

Events

INVERTED I/O

Asynchronous

Events

When a pin is configured with inverted I/O, the pin value is inverted before the input sensing.

16.5

Alternate Port Functions

Most port pins have alternate pin functions in addition to being a general purpose I/O pin. When an alternate function is enabled, it might override the normal port pin function or pin value. This happens when other peripherals that require pins are enabled or configured to use pins. If and how a peripheral will override and use pins is described in the section for that peripheral.

“Pinout and Pin Functions” on page 57 shows which modules on peripherals that enable alternate

functions on a pin, and which alternate functions that are available on a pin.



33

17.

Timer Counter Type 4 and 5

17.1

Features





Three 16-bit timer/counter





One timer/counter of type 4

Two timer/counter of type 5

32-bit timer/counter support by cascading two timer/counters

























Up to four compare or capture (CC) channels





Four CC channels for timer/counters of type 4

Two CC channels for timer/counters of type 5

Double buffered timer period setting

Double buffered CC channels

Waveform generation modes:







Frequency generation

Single-slope pulse width modulation

Dual-slope pulse width modulation

Input capture:









Input capture with noise cancelling

Frequency capture

Pulse width capture

32-bit input capture

Timer overflow and error interrupts/events

One compare match or input capture interrupt/event per CC channel

Can be used with event system for:







Quadrature decoding

Count and direction control

Input capture

Can be used with EDMA and to trigger EDMA transactions

High-resolution extension

 Increases frequency and waveform resolution by 4x (2-bit) or 8x (3-bit)

Waveform extension

 Low- and high-side output with programmable dead-time insertion (DTI)

Fault extention

 Event controlled fault protection for safe disabling of drivers

17.2

Overview

Atmel AVR XMEGA devices have a set of flexible, 16-bit timer/counters (TC). Their capabilities include accurate program execution timing, frequency and waveform generation, and input capture with time and frequency measurement of digital signals. Two timer/counters can be cascaded to create a 32-bit timer/counter with optional 32-bit input capture.

A timer/counter consists of a base counter and a set of compare or capture (CC) channels. The base counter can be used to count clock cycles or events. It has direction control and period setting that can be used for timing. The CC channels can be used together with the base counter to do compare match control, frequency generation, and pulse width modulation (PWM) generation, as well as various input capture operations. A timer/counter can be configured for either capture, compare, or capture and compare function.

A timer/counter can be clocked and timed from the peripheral clock with optional prescaling, or from the event system.

The event system can also be used for direction control, input capture trigger, or to synchronize operations.



34

There are two differences between timer/counter type 4 and type 5. Timer/counter 4 has four CC channels, and timer/counter 5 has two CC channels. Both timer/counter 4 and 5 can be set in 8-bit mode, allowing the application to double the number of compare and capture channels that then get 8-bit resolution.

Some timer/counters have extensions that enable more specialized waveform generation. The waveform extension

(WeX) is intended for motor control, ballast, LED, H-bridge, power converters, and other types of power control applications. It enables more customized waveform output distribution, and low- and high-side channel output with optional dead-time insertion. It can also generate a synchronized bit pattern across the port pins. The high-resolution (hires) extension can increase the waveform resolution by four or eight times by using an internal clock source four times faster than the peripheral clock. The fault extension (FAULT) enables fault protection for safe and deterministic handling, disabling and/or shut down of external drivers.

A block diagram of the 16-bit timer/counter with extensions and closely related peripheral modules (in grey) is shown in

Figure 17-1 .

Figure 17-1. 16-bit Timer/counter and Closely Related Peripherals

Timer/Counter

Base Counter

Timer Period

Counter

Control Logic

Prescaler

Event

System clk

PER clk

PER4

Compare/Capture Channel D

Compare/Capture Channel C

Compare/Capture Channel B

Compare/Capture Channel A

Comparator

Buffer

Capture

Control

Waveform

Generation

WeX

PORTC has one timer/counter 4 and one timer/counter 5. PORTD has one timer/counter 5. Notation of these are TCC4

(timer/counter C4), TCC5, and TCD5, respectively.



35

18.

WeX – Waveform Extension

18.1

Features











Module for more customized and advanced waveform generation

 Optimized for various type of motor, ballast, and power stage control

Output matrix for timer/counter waveform output distribution





Configurable distribution of compare channel output across port pins

Redistribution of dead-time insertion resource between TC4 and TC5

Four dead-time insertion (DTI) units, each with







Complementary high and low side with non overlapping outputs

Separate dead-time setting for high and low side

8-bit resolution

Four swap (SWAP) units





Separate port pair or low high side drivers swap

Double buffered swap feature

Pattern generation creating synchronized bit pattern across the port pins

 Double buffered pattern generation

18.2

Overview

The waveform extension (WEX) provides extra functions to the timer/counter in waveform generation (WG) modes. It is primarily intended for motor control, ballast, LED, H-bridge, power converters, and other types of power control applications. The WEX consist of five independent and successive units, as shown in

Figure 18-1 .

Figure 18-1. Waveform Extension and Closely Related Peripherals

WEX

T/C4

T/C5

Fault

Unit 4

Fault

Unit 5

DTI1

DTI1

DTI1

DTI1

SWAP1

SWAP1

SWAP1

SWAP1

Px0

Px1

Px2

Px3

Px4

Px5

Px6

Px7

The output matrix (OTMX) can distribute and route out the waveform outputs from timer/counter 4 and 5 across the port pins in different configurations, each optimized for different application types. The dead time insertion (DTI) unit splits the four lower OTMX outputs into a two non-overlapping signals, the non-inverted low side (LS) and inverted high side (HS) of the waveform output with optional dead-time insertion between LS and HS switching.

The swap (SWAP) unit can swap the LS and HS pin position. This can be used for fast decay motor control. The pattern generation unit generates synchronized output waveform with constant logic level. This can be used for easy stepper motor and full bridge control.



36

The output override disable unit can disable the waveform output on selectable port pins to optimize the pins usage. This is to free the pins for other functional use, when the application does not need the waveform output spread across all the port pins as they can be selected by the OTMX configurations.

The waveform extension is available for TCC4 and TCC5. The notation of this is WEXC.



37

19.

Hi-Res – High Resolution Extension

19.1

Features





Increases waveform generator resolution up to 8x (three bits)

Supports frequency, single-slope PWM, and dual-slope PWM generation

 Supports the WeX when this is used for the same timer/counter

19.2

Overview

The high-resolution (hi-res) extension can be used to increase the resolution of the waveform generation output from a timer/counter by four or eight. It can be used for a timer/counter doing frequency, single-slope PWM, or dual-slope PWM generation. It can also be used with the WeX if this is used for the same timer/counter.

The hi-res extension uses the peripheral 4x clock (ClkPER4). The system clock prescalers must be configured so the peripheral 4x clock frequency is four times higher than the peripheral and CPU clock frequency when the hi-res extension is enabled.

There is one hi-res extension that can be enabled for timer/counters pair on PORTC. The notation of this is HIRESC.



38

20.

Fault Extension

20.1

Features





Connected to timer/counter output and waveform extension input

Event controlled fault protection for instant and predictable fault triggering











Fast, synchronous and asynchronous fault triggering

Flexible configuration with multiple fault sources

Recoverable fault modes







Restart or halt the timer/counter on fault condition

Timer/counter input capture on fault condition

Waveform output active time reduction on fault condition

Non-recoverable faults





Waveform output is forced to a pre-configured safe state on fault condition

Optional fuse output value configuration defining the output state during system reset

Flexible fault filter selections







Digital filter to prevent false triggers from I/O pin glitches

Fault blanking to prevent false triggers during commutation

Fault input qualification to filter the fault input during the inactive output compare states

20.2

Overview

The fault extension enables event controlled fault protection by acting directly on the generated waveforms from timer/counter compare outputs. It can be used to trigger two types of faults with the following actions:



Recoverable faults: the timer/counter can be restarted or halted as long as the fault condition is preset. The compare output pulse active time can be reduced as long as the fault condition is preset. This is typically used for current sensing regulation, zero crossing re-triggering, demagnetization re-triggering, and so on.

 Non-recoverable faults: the compare outputs are forced to a safe and pre-configured values that are safe for the application. This is typically used for instant and predictable shut down and to disable the high current or voltage drivers.

Events are used to trigger a fault condition. One or several simultaneous events are supported, both synchronously or asynchronously. By default, the fault extension supports asynchronous event operation, ensuring predictable and instant fault reaction, including system power modes where the system clock is stopped.

By using the input blanking, the fault input qualification or digital filter option in event system, the fault sources can be filtered to avoid false faults detection.

There are two fault extensions, one for each of the timer/counter 4 and timer/counter 5 on PORTC. The notation of these are FAULTC4 and FAULTC5, respectively.



39

21.

RTC – 16-bit Real-Time Counter

21.1

Features









16-bit resolution

Selectable clock source









32.768kHz external crystal

External clock

32.768kHz internal oscillator

32kHz internal ULP oscillator

Programmable 10-bit clock prescaling

One compare register









One period register

Clear counter on period overflow

Optional interrupt/event on overflow and compare match

Correction for external crystal oscillator frequency error down to ±0.5ppm accuracy

21.2

Overview

The 16-bit real-time counter (RTC) is a counter that typically runs continuously, including in low power sleep modes, to keep track of time. It can wake up the device from sleep modes and/or interrupt the device at regular intervals.

The reference clock is typically the 1.024kHz output from a high-accuracy crystal of 32.768kHz, and this is the configuration most optimized for low power consumption. The faster 32.768kHz output can be selected if the RTC needs a resolution higher than 1ms. The RTC can also be clocked from an external clock signal, the 32.768kHz internal oscillator or the 32kHz internal ULP oscillator.

The RTC includes a 10-bit programmable prescaler that can scale down the reference clock before it reaches the counter. A wide range of resolutions and time-out periods can be configured. With a 32.768kHz clock source, the maximum resolution is 30.5μs, and time-out periods can range up to 2000 seconds. With a resolution of 1s, the maximum timeout period is more than 18 hours (65536 seconds). The RTC can give a compare interrupt and/or event when the counter equals the compare register value, and an overflow interrupt and/or event when it equals the period register value.



40

Figure 21-1. Real-time Counter Overview

TOSC1

TOSC2

External Clock

32.768 kHz Crystal

Osc

32.768 kHz Int. Osc

32 kHz int ULP

(DIV32)

CALIB

RTCSRC clk

RTC

PER

=

TOP/

Overflow

Correction

Counter

Hold Count

10-bit prescaler

CNT

=

”match”/

Compare

COMP

The RTC also supports correction when operated using external 32.768 kHz crystal oscillator. An externally calibrated value will be used for correction. The calibration can be done by measuring the default RTC frequency relative to a more accurate clock input to the device as system clock. The RTC can be calibrated to an accuracy of ±0.5ppm. The RTC correction operation will either speed up (by skipping count) or slow down (adding extra cycles) the prescaler to account for the crystal oscillator error.



41

22.

TWI – Two-Wire Interface

22.1

Features









One two-wire interface

 Phillips I 2 C compatible

 System Management Bus (SMBus) compatible

Bus master and slave operation supported











Slave operation

Single bus master operation

Bus master in multi-master bus environment

Multi-master arbitration

Bridge mode with independent and simultaneous master and slave operation

Flexible slave address match functions









7-bit and general call address recognition in hardware

10-bit addressing supported

Address mask register for dual address match or address range masking

Optional software address recognition for unlimited number of addresses

Slave can operate in all sleep modes, including power-down



















Slave address match can wake device from all sleep modes

100kHz, 400kHz, and 1MHz bus frequency support

Slew-rate limited output drivers

Input filter for bus noise and spike suppression

Support arbitration between start/repeated start and data bit (SMBus)

Slave arbitration allows support for address resolve protocol (ARP) (SMBus)

Supports SMBUS Layer 1 timeouts

Configurable timeout values

Independent timeout counters in master and slave (Bridge mode support)

22.2

Overview

The two-wire interface (TWI) is a bidirectional, two-wire communication interface. It is I 2 C and System Management Bus

(SMBus) compatible. The only external hardware needed to implement the bus is one pull-up resistor on each bus line.

A device connected to the bus must act as a master or a slave. One bus can have many slaves and one or several masters that can take control of the bus.

The TWI module supports master and slave functionality. The master and slave functionality are separated from each other, and can be enabled and operate simultaneously and separately. The master module supports multi-master bus operation and arbitration. It contains the baud rate generator. Quick command and smart mode can be enabled to autotrigger operations and reduce software complexity. The master can support 100kHz, 400kHz, and 1MHz bus frequency.

The slave module implements 7-bit address match and general address call recognition in hardware. 10-bit addressing is also supported. A dedicated address mask register can act as a second address match register or as a register for address range masking. The slave continues to operate in all sleep modes, including power-down mode. This enables the slave to wake up the device from all sleep modes on TWI address match. It is possible to disable the address matching to let this be handled in software instead. By using the bridge option, the slave can be mapped to different pin locations. The master and slave can support 100kHz, 400kHz, and 1MHz bus frequency.

The TWI module will detect START and STOP conditions, bus collisions, and bus errors. Arbitration lost, errors, collision, and clock hold on the bus are also detected and indicated in separate status flags available in both master and slave modes.



42

It is possible to disable the TWI drivers in the device, and enable a four-wire digital interface for connecting to an external

TWI bus driver. This can be used for applications where the device operates from a different V

CC the TWI bus.

voltage than used by

It is also possible to enable the bridge mode. In this mode, the slave I/O pins are selected from an alternative port, enabling independent and simultaneous master and slave operation.

PORTC has one TWI. Notation of this peripheral is TWIC. Alternative TWI Slave location in bridge mode is on PORTD.



43

23.

SPI – Serial Peripheral Interface

23.1

Features





One SPI peripheral

Full-duplex, three-wire synchronous data transfer















Master or slave operation lsb first or msb first data transfer

Eight programmable bit rates

Interrupt flag at the end of transmission

Write collision flag to indicate data collision

Wake up from idle sleep mode

Double speed master mode

23.2

Overview

The Serial Peripheral Interface (SPI) is a high-speed, full duplex, synchronous data transfer interface using three or four pins. It allows fast communication between an AVR XMEGA device and peripheral devices or between several microcontrollers.

A device connected to the bus must act as a master or slave. The master initiates and controls all data transactions. The

interconnection between master and slave devices with SPI is shown in Figure 23-1

. The system consists of two shift registers and a clock generator. The SPI master initiates the communication by pulling the slave select (SS) signal low for the desired slave. Master and slave prepare the data to be sent in their respective shift registers, and the master generates the required clock pulses on the SCK line to interchange data. Data are always shifted from master to slave on the master output, slave input (MOSI) line, and from slave to master on the master input, slave output (MISO) line. After each data packet, the master can synchronize the slave by pulling the SS line high.

Figure 23-1. SPI Master-slave Interconnection

MASTER

Transmit Data Register

(DATA) msb lsb

8-bit Shift Register

SLAVE

Transmit Data Register

(DATA)

SPI CLOCK

GENERATOR

Receive Buffer Register

MISO

MOSI

SCK

SS

MISO

MOSI

SCK

SS lsb msb

8-bit Shift Register

Receive Buffer Register

Receive Data Register

(DATA)

Receive Data Register

(DATA)

By default, the SPI module is single buffered and transmit direction and double buffered in the receive direction. A byte written to the transmit data register will be copied to the shift register when a full character has been received. When receiving data, a received character must be read from the transmit data register before the third character has been completely shifted in to avoid losing data. Optionally, buffer modes can be enabled. When used, one buffer is available for transmitter and a double buffer for reception.

PORTC has one SPI. Notation of this is SPIC.



44

24.

USART

24.1

Features





Two identical USART peripherals

Full-duplex or one-wire half-duplex operation





















Asynchronous or synchronous operation





Synchronous clock rates up to 1/2 of the device clock frequency

Asynchronous clock rates up to 1/8 of the device clock frequency

Supports serial frames with:







5, 6, 7, 8, or 9 data bits

Optionally even and odd parity bits

1 or 2 stop bits

Fractional baud rate generator





Can generate desired baud rate from any system clock frequency

No need for external oscillator with certain frequencies

Built-in error detection and correction schemes







Odd or even parity generation and parity check

Data overrun and framing error detection

Noise filtering includes false start bit detection and digital low-pass filter

Separate interrupts for







Transmit complete

Transmit data register empty

Receive complete

Multiprocessor communication mode





Addressing scheme to address a specific devices on a multidevice bus

Enable unaddressed devices to automatically ignore all frames

System wake-up from Start bit

Master SPI mode







Double buffered operation

Configurable data order

Operation up to 1/2 of the peripheral clock frequency

IRCOM module for IrDA compliant pulse modulation/demodulation

One USART is connected to XMEGA Custom Logic (XCL) module:





Extend serial frame length up to 256 bit by using the peripheral counter

Modulate/demodulate data within the frame by using the glue logic outputs

24.2

Overview

The universal synchronous and asynchronous serial receiver and transmitter (USART) is a fast and flexible serial communication module. The USART supports full-duplex with asynchronous and synchronous operation and single wire half-duplex communication with asynchronous operation. The USART can be configured to operate in SPI master mode and used for SPI communication.

Communication is frame based, and the frame format can be customized to support a wide range of standards. The

USART is buffered in both directions, enabling continued data transmission without any delay between frames. Separate interrupts for receive and transmit complete enable fully interrupt driven communication. Frame error and buffer overflow are detected in hardware and indicated with separate status flags. Even or odd parity generation and parity check can also be enabled.

In one-wire configuration, the TxD pin is connected to the RxD pin internally, limiting the IO pins usage. If the receiver is enabled when transmitting, it will receive what the transmitter is sending. This mode can be used for bit error detection.



45

The clock generator includes a fractional baud rate generator that is able to generate a wide range of USART baud rates from any system clock frequencies. This removes the need to use an external crystal oscillator with a specific frequency to achieve a required baud rate. It also supports external clock input in synchronous slave operation.

An IRCOM module can be enabled for one USART to support IrDA 1.4 physical compliant pulse modulation and demodulation for baud rates up to 115.2Kbps.

One USART can be connected to the XMEGA Custom Logic module (XCL). When used with the XCL, the data length within an USART/SPI frame can be controlled by the peripheral counter (PEC) within the XCL. This enables configurable frame length up to 256 bits. In addition, the TxD/RxD data can be encoded/decoded before the signal is fed into the

USART receiver, or after the signal is output from transmitter when the USART is connected to XCL LUT outputs.

When the USART is set in master SPI mode, all USART-specific logic is disabled, leaving the transmit and receive buffers, shift registers, and baud rate generator enabled. The registers are used in both modes, but their functionality differs for some control settings. Pin control and interrupt generation are identical in both modes.

PORTC and PORTD each has one USART. Notation of these peripherals are USARTC0 and USARTD0, respectively.



46

25.

IRCOM – IR Communication Module

25.1

Features





Pulse modulation/demodulation for infrared communication

IrDA compatible for baud rates up to 115.2Kbps







Selectable pulse modulation scheme







3/16 of the baud rate period

Fixed pulse period, 8-bit programmable

Pulse modulation disabled

Built-in filtering

Can be connected to and used by any USART

25.2

Overview

Atmel AVR XMEGA devices contain an infrared communication module (IRCOM) that is IrDA compatible for baud rates up to 115.2Kbps. It can be connected to any USART to enable infrared pulse encoding/decoding for that USART.



47

26.

XCL – XMEGA Custom Logic Module

26.1

Features

















Two independent 8-bit timer/counter with:













Period and compare channel for each timer/counter

Input Capture for each timer

Serial peripheral data length control for each timer

Timeout support for each timer

Timer underflow interrupt/event

Compare match or input capture interrupt/event for each timer

One 16-bit timer/counter by cascading two 8-bit timer/counters with:











Period and compare channel

Input capture

Timeout support

Timer underflow interrupt/event

Compare match or input capture interrupt/event

Programmable lookup table supporting multiple configurations:











Two 2-input units

One 3-input unit

RS configuration

Duplicate input with selectable delay on one input or output

Connection to external I/O pins, event system or one selectable USART

Combinatorial Logic Functions using programmable truth table:

 AND, NAND, OR, NOR, XOR, XNOR, NOT, MUX

Sequential Logic Functions:

 D-Flip-Flop, D Latch, RS Latch

Input sources:







From external pins or the event system

One input source includes selectable delay or synchronizing option

Can be shared with selectable USART pin locations

Outputs:







Available on external pins or event system

Includes selectable delay or synchronizing option

Can override selectable USART pin locations

Operates in active mode and all sleep modes

26.2

Overview

The XMEGA Custom Logic module (XCL) consists of two sub-units, each including 8-bit timer/counter with flexible settings, peripheral counter working with one software selectable USART module, delay elements, glue logic with programmable truth table and a global logic interconnect array.

The timer/counter configuration allows for two 8-bits timer/counters. Each timer/counter supports normal, compare and input capture operation, with common flexible clock selections and event channels for each timer. By cascading the two

8-bit timer/counters, the XCL can be used as a 16-bit timer/counter.

The peripheral counter (PEC) configuration, the XCL is connected to one software selectable USART. This USART controls the counter operation, and the PEC can optionally control the data length within the USART frame.

The glue logic configuration, the XCL implements two programmable lookup tables (LUTs). Each defines the truth table corresponding to the logical condition between two inputs. Any combinatorial function logic is possible. The LUT inputs can be connected to I/O pins or event system channels. If the LUT is connected to the USART0 pin locations, the data lines (TXD/RXD) data encoding/decoding will be possible. Connecting together the LUT units, RS Latch, or any combinatorial logic between two operands or three inputs can be enabled.



48

The LUT works in all sleep modes. Combined with event system and one I/O pin, the LUT can wake-up the system if, and only if, condition on up to three input pins is true.

A block diagram of the programmable logic unit with extensions and closely related peripheral modules (in grey) is shown

in Figure 26-1 .

Figure 26-1. XMEGA Custom Logic Module and Closely Related Peripherals

Interrupts

Event

System

Port

Pins

USART

Periph.Counter

One Shot

PWM

Capture

Normal

BTC0

Normal

Capture

BTC1

PWM

One Shot

Periph.Counter

Timer/Counter

LUT0

Truth

Table

D Q

D Q

G

LUT1

Truth

Table

Glue Logic



49

27.

CRC – Cyclic Redundancy Check Generator

27.1

Features









Cyclic redundancy check (CRC) generation and checking for







Communication data

Program or data in flash memory

Data in SRAM and I/O memory space

Integrated with flash memory, EDMA controller, and CPU







Continuous CRC on data going through an EDMA channel

Automatic CRC of the complete or a selectable range of the flash memory

CPU can load data to the CRC generator through the I/O interface

CRC polynomial software selectable to:





CRC-16 (CRC-CCITT)

CRC-32 (IEEE 802.3)

Zero remainder detection

27.2

Overview

A cyclic redundancy check (CRC) is an error detection technique test algorithm used to find accidental errors in data, and it is commonly used to determine the correctness of a data transmission, and data present in the data and program memories. A CRC takes a data stream or a block of data as input and generates a 16- or 32-bit output that can be appended to the data and used as a checksum. When the same data are later received or read, the device or application repeats the calculation. If the new CRC result does not match the one calculated earlier, the block contains a data error.

The application will then detect this and may take a corrective action, such as requesting the data to be sent again or simply not using the incorrect data.

Typically, an n-bit CRC applied to a data block of arbitrary length will detect any single error burst not longer than n bits

(any single alteration that spans no more than n bits of the data), and will detect the fraction 1-2 -n of all longer error bursts. The CRC module in XMEGA devices supports two commonly used CRC polynomials; CRC-16 (CRC-CCITT) and

CRC-32 (IEEE 802.3).





CRC-16:



Polynomial: x 16 + x 12 + x 5 + 1



Hex Value: 0x1021

CRC-32:



Polynomial: x 32 + x 26 + x 23 + x 22 + x 16 + x 12 + x 11 + x 10 + x 8 + x 7 + x 5 + x 4 + x 2 + x + 1



Hex Value: 0x04C11DB7



50

28.

ADC – 12-bit Analog to Digital Converter

28.1

Features

















12-bit resolution

Up to 300 thousand samples per second





Down to 2.3μs conversion time with 8-bit resolution

Down to 3.35μs conversion time with 12-bit resolution

Differential and single-ended input





Up to 16 single-ended inputs

16x8 differential inputs with optional gain

Built-in differential gain stage

 1/2x, 1x, 2x, 4x, 8x, 16x, 32x, and 64x gain options

Single, continuous and scan conversion options

Four internal inputs









Internal temperature sensor

DAC output

AV

CC voltage divided by 10

1.1V bandgap voltage

Internal and external reference options

Compare function for accurate monitoring of user defined thresholds













Offset and gain correction

Averaging

Over-sampling and decimation

Optional event triggered conversion for accurate timing

Optional interrupt/event on compare result

Optional EDMA transfer of conversion results

28.2

Overview

The ADC converts analog signals to digital values. The ADC has 12-bit resolution and is capable of converting up to 300 thousand samples per second (ksps). The input selection is flexible, and both single-ended and differential measurements can be done. For differential measurements, an optional gain stage is available to increase the dynamic range. In addition, several internal signal inputs are available. The ADC can provide both signed and unsigned results.

The ADC measurements can either be started by application software or an incoming event from another peripheral in the device. The ADC measurements can be started with predictable timing, and without software intervention. It is possible to use EDMA to move ADC results directly to memory or peripherals when conversions are done.

Both internal and external reference voltages can be used. An integrated temperature sensor is available for use with the

ADC. The output from the DAC, AV

CC

/10, and the bandgap voltage can also be measured by the ADC.

The ADC has a compare function for accurate monitoring of user defined thresholds with minimum software intervention required.

When operation in noisy conditions, the average feature can be enabled to increase the ADC resolution. Up to 1024 samples can be averaged, enabling up to 16-bit resolution results. In the same way, using the over-sampling and decimation mode, the ADC resolution is increased up to 16-bits, which results in up to 4-bit extra lsb resolution. The ADC includes various calibration options. In addition to standard production calibration, the user can enable the offset and gain correction to improve the absolute ADC accuracy.



51

Figure 28-1. ADC Overview

V

IN

S&H Σ 2x

V

OUT

ADC0

ADC1

•

•

•

ADC14

ADC15

Internal

Signals

ADC0

•

•

•

ADC7

V

INP

V

INN

ADC

2 bits

DAC

½x 64x

Stage

1

2

clk

ADC

Stage

2

2

Digital Correction Logic

ADC

Gain & Offset

Error

Correction

CMP

RES

<

>

Averaging

Threshold

(Int. Req.)

Internal 1.00V

Internal AVCC/1.6

Internal AVCC/2

AREFA

AREFD

Reference

Voltage

The ADC may be configured for 8- or 12-bit result, reducing the propagation delay from 3.35µs for 12-bit to 2.3µs for 8-bit result. ADC conversion results are provided left- or right adjusted with eases calculation when the result is represented as a signed.

PORTA has one ADC. Notation of this peripheral is ADCA.



52

29.

DAC – Digital to Analog Converter

29.1

Features





One Digital to Analog Converter (DAC)

12-bit resolution



















Two independent, continuous-drive output channels

Up to 1 million samples per second conversion rate per DAC channel

Built-in calibration that removes:





Offset error

Gain error

Multiple conversion trigger sources





On new available data

Events from the event system

Drive capabilities and support for







Resistive loads

Capacitive loads

Combined resistive and capacitive loads

Internal and external reference options

DAC output available as input to analog comparator and ADC

Low-power mode, with reduced drive strength

Optional EDMA transfer of data

29.2

Overview

The digital-to-analog converter (DAC) converts digital values to voltages. The DAC has two channels, each with 12-bit resolution, and is capable of converting up to one million samples per second (Msps) on each channel. The built-in calibration system can remove offset and gain error when loaded with calibration values from software.

Figure 29-1. DAC Overview

EDMA req

(Data Empty)

CH0DATA

12

D

A

Output

Driver

To

AC/ADC

AVCC

Internal 1.00V

AREFA

AREFD

Reference selection

Trigger Select

CTRLB

Trigger Select

Int.

driver

Enable

CTRLA

Enable

Internal Output enable

CH1DATA

12

D

A

Output

Driver

EDMA req

(Data Empty)

A DAC conversion is automatically started when new data to be converted are available. Events from the event system can also be used to trigger a conversion, and this enables synchronized and timed conversions between the DAC and other peripherals, such as a timer/counter. The EDMA controller can be used to transfer data to the DAC.

The DAC is capable of driving both resistive and capacitive loads aswell as loads which combine both. A low-power mode is available, which will reduce the drive strength of the output. Internal and external voltage references can be used. The DAC output is also internally available for use as input to the analog comparator or ADC.

PORTA has one DAC. Notation of this peripheral is DACA.



53

30.

AC – Analog Comparator

30.1

Features





Two Analog Comparators

Selectable propagation delay















Selectable hysteresis







No

Small

Large

Analog Comparator output available on pin

Flexible Input Selection









All pins on the port

Output from the DAC

Bandgap reference voltage

A 64-level programmable voltage scaler of the internal AVCC voltage

Interrupt and event generation on







Rising edge

Falling edge

Toggle

Window function interrupt and event generation on







Signal above window

Signal inside window

Signal below window

Constant current source with configurable output pin selection

Source of asynchronous event

30.2

Overview

The Analog Comparator (AC) compares the voltage level on two inputs and gives a digital output based on this comparison. The Analog Comparator may be configured to give interrupt requests and/or synchronous/asynchronous events upon several different combinations of input change.

One important property of the Analog Comparator when it comes to the dynamic behavior, is the hysteresis. This parameter may be adjusted in order to find the optimal operation for each application.

The input section includes analog port pins, several internal signals and a 64-level programmable voltage scaler. The analog comparator output state can also be directly available on a pin for use by external devices. Using as pair they can also be set in Window mode to monitor a signal compared to a voltage window instead of a voltage level.

A constant current source can be enabled and output on a selectable pin. This can be used to replace, for example, external resistors used to charge capacitors in capacitive touch sensing applications.

The analog comparators are always grouped in pairs on each port. These are called analog comparator 0 (AC0) and analog comparator 1 (AC1). They have identical behavior, but separate control registers. Used as pair, they can be set in window mode to compare a signal to a voltage range instead of a voltage level.

PORTA has one AC pair. Notation is ACA.



54

Figure 30-1. Analog Comparator Overview

Pin Input

Pin Input

DAC

Voltage

Scaler

Bandgap

Pin Input

AC0OUT

Hysteresis

Enable

ACnMUXCTRL ACnCTRL

Interrupt

Mode

WINCTRL

Interrupt

Sensititivity

Control

&

Interrupts

Events

Window

Function

Enable

Hysteresis

AC1OUT

Pin Input

The window function is realized by connecting the external inputs of the two analog comparators in a pair as shown in

Figure 30-2 .

Figure 30-2. Analog Comparator Window Function

Upper limit of window

+

AC0

-

Input signal

Interrupt sensitivity control

Interrupts

Events

Lower limit of window

+

AC1

-



55

31.

Programming and Debugging

31.1

Features







Programming





External programming through PDI interface

 Minimal protocol overhead for fast operation

 Built-in error detection and handling for reliable operation

Boot loader support for programming through any communication interface

Debugging















Nonintrusive, real-time, on-chip debug system

No software or hardware resources required from device except pin connection

Program flow control

Go, Stop, Reset, Step Into, Step Over, Step Out, Run-to-Cursor

Unlimited number of user program breakpoints

Unlimited number of user data breakpoints, break on:





Data location read, write, or both read and write

Data location content equal or not equal to a value





Data location content is greater or smaller than a value

Data location content is within or outside a range

No limitation on device clock frequency

Program and Debug Interface (PDI)







Two-pin interface for external programming and debugging

Uses the Reset pin and a dedicated pin

No I/O pins required during programming or debugging

31.2

Overview

The Program and Debug Interface (PDI) is an Atmel proprietary interface for external programming and on-chip debugging of a device. The PDI supports fast programming of nonvolatile memory (NVM) spaces; flash, EEPOM, fuses, lock bits, and the user signature row.

Debug is supported through an on-chip debug system that offers nonintrusive, real-time debug. It does not require any software or hardware resources except for the device pin connection. Using the Atmel tool chain, it offers complete program flow control and support for an unlimited number of program and complex data breakpoints. Application debug can be done from a C or other high-level language source code level, as well as from an assembler and disassemble level.

Programming and debugging can be done through the PDI physical layer. This is a two-pin interface that uses the Reset pin for the clock input (PDI_CLK) and one other dedicated pin for data input and output (PDI_DATA). Any external programmer or on-chip debugger/emulator can be directly connected to this interface.



56

32.

Pinout and Pin Functions

The device pinout is shown in

“Pinout and Block Diagram” on page 4

. In addition to general purpose I/O functionality, each pin can have several alternate functions. This will depend on which peripheral is enabled and connected to the actual pin. Only one of the pin functions can be used at time.

32.1

Alternate Pin Function Description

The tables below show the notation for all pin functions available and describe its function.

32.1.1 Operation/Power Supply

V

CC

AV

CC

GND

Digital supply voltage

Analog supply voltage

Ground

32.1.2 Port Interrupt Functions

SYNC

ASYNC

Port pin with full synchronous and limited asynchronous interrupt function

Port pin with full synchronous and full asynchronous interrupt function

32.1.3 Analog Functions

ACn

ACnOUT

ADCn

DACn

A

REF

Analog Comparator input pin n

Analog Comparator n Output

Analog to Digital Converter input pin n

Digital to Analog Converter output pin n

Analog Reference input pin

32.1.4 Timer/Counter and WEX Functions

OCnx

OCnxLS

OCnxHS

Output Compare Channel x for timer/counter n

Output Compare Channel x Low Side for Timer/Counter n

Output Compare Channel x High Side for Timer/Counter n

32.1.5 Communication Functions

SCL

SDA

SCLIN

SCLOUT

SDAIN

SDAOUT

Serial Clock for TWI

Serial Data for TWI

Serial Clock In for TWI when external driver interface is enabled

Serial Clock Out for TWI when external driver interface is enabled

Serial Data In for TWI when external driver interface is enabled

Serial Data Out for TWI when external driver interface is enabled



57

XCKn

RXDn

TXDn

SS

MOSI

MISO

SCK

Transfer Clock for USART n

Receiver Data for USART n

Transmitter Data for USART n

Slave Select for SPI

Master Out Slave In for SPI

Master In Slave Out for SPI

Serial Clock for SPI

32.1.6 Oscillators, Clock, and Event

TOSCn

XTALn

CLKOUT

EVOUT

RTCOUT

Timer Oscillator pin n

Input/Output for Oscillator pin n

Peripheral Clock Output

Event Channel Output

RTC Clock Source Output

32.1.7 Debug/System Functions

RESET

PDI_CLK

PDI_DATA

Reset pin

Program and Debug Interface Clock pin

Program and Debug Interface Data pin



58

32.2

Alternate Pin Functions

The tables below show the primary/default function for each pin on a port in the first column, the pin number in the second column, and then all alternate pin functions in the remaining columns. The head row shows what peripheral that enable and use the alternate pin functions.

For better flexibility, some alternate functions also have selectable pin locations for their functions, this is noted under the first table where this apply.

Table 32-1. PORT A – Alternate Functions

PA3

PA4

PA5

PA6

PA7

PORT A

PA0

PA1

PA2

31

30

3

2

29

Pin#

6

5

4

ADCA POS/

GAINPOS

ADC 0

ADC 1

ADC 2

ADC 3

ADC 4

ADC 5

ADC 6

ADC 7

ADCA NEG/

GAINNEG

ADC 0

ADC 1

ADC 2

ADC 3

ADC 4

ADC 5

ADC 6

ADC 7

DACA

DAC0

DAC1

ACA

POS

AC0

AC1

AC2

AC3

AC4

AC5

AC6

ACA

NEG

AC0

AC1

AC3

AC5

AC7

ACA

OUT

AC1OUT

AC0OUT

REFA

AREF

Table 32-2. PORT C – Alternate Functions

PORT C Pin #

PC0 16

PC1

PC2

15

14

PC3

PC4

PC5

PC6

PC7

13

12

11

10

9

TCC4

OC4A

OC4B

OC4C

OC4D

OC4A

OC4B

OC4C

OC4D

WEXC

OC4ALS

OC4AHS

OC4BLS

OC4BHS

OC4CLS

OC4CHS

OC4DLS

OC4DHS

TCC5

OC5A

OC5B

USARTC0

XCK0

RXD0

TXD0

XCK0

RXD0

TXD0

SPIC

SS

SCK

MISO

MOSI

TWI

SDA

SCL

Table 32-3. Debug – Program and Debug Functions

DEBUG

RESET

PDI

Pin #

8

7

PROG

PDI CLOCK

PDI DATA

XCL

(LUT)

IN1/OUT0

IN2

IN0

IN3

IN1/OUT0

IN2

IN0

IN3

EXTCLK

EXTCLK

AC OUT

AC1OUT

AC0OUT



59

Table 32-4. PORT R – Alternate Functions

PORT R

PR0

PR1

Pin #

20

19

XTAL

XTAL2

XTAL1

TOSC

TOSC2

TOSC1

EXTCLK

EXTCLK

CLOCKOUT

CLKOUT

EVENTOUT

EVOUT

RTCOUT

RTCOUT

AC OUT

AC1 OUT

AC0 OUT

Table 32-5. PORT D – Alternate Functions

PORT D

PD4

PD5

PD6

PD7

PD0

PD1

PD2

PD3

Pin #

28

ADCAPOS

GAINPOS

ADC8

TCD5

27

26

25

24

23

22

21

ADC9

ADC10

ADC11

ADC12

ADC13

ADC14

ADC15

OC5A

OC5B

USART

D0

TWID

(Bridge)

SDA

XCK0

RXD0

TXD0

SCL

XCK0

RXD0

TXD0

XCL

(LUT)

IN1/

OUT0

IN2

IN0

IN3

IN1/

OUT0

IN2

IN0

IN3

XCL

(TC)

CLOCK

OUT

EVENT

OUT RTCOUT ACOUT REFD

AREF

OC0

OC1

CLKOUT EVOUT

CLKOUT EVOUT

RTCOUT AC1OUT

AC0OUT



60

33.

Peripheral Module Address Map

The address maps show the base address for each peripheral and module in XMEGA E5. For complete register description and summary for each peripheral module, refer to the XMEGA E Manual .

Table 33-1. Peripheral Module Address Map

0x0080

0x0090

0x00A0

0x00B0

0x00D0

0x0100

0x0040

0x0048

0x0050

0x0060

0x0070

0x0078

Base Address

0x0000

0x0010

0x0014

0x0018

0x001C

0x0030

0x0180

0x01C0

0x0200

0x0300

0x0380

0x0400

0x0460

0x0480

0x0600

0x0640

0x0660

Name

GPIO

VPORT0

VPORT1

VPORT2

VPORT3

CPU

CLK

SLEEP

OSC

DFLLRC32M

PR

RST

WDT

MCU

PMIC

PORTCFG

CRC

EDMA

EVSYS

NVM

ADCA

DACA

ACA

RTC

XCL

TWIC

PORTA

PORTC

PORTD

Description

General Purpose IO Registers

Virtual Port A

Virtual Port C

Virtual Port D

Virtual Port R

CPU

Clock Control

Sleep Controller

Oscillator Control

DFLL for the 32MHz Internal Oscillator

Power Reduction

Reset Controller

Watch-Dog Timer

MCU Control

Programmable Multilevel Interrupt Controller

Port Configuration

CRC Module

Enhanced DMA Controller

Event System

Non Volatile Memory (NVM) Controller

Analog to Digital Converter on port A

Digital to Analog Converter on port A

Analog Comparator pair on port A

Real Time Counter

XMEGA Custom Logic Module

Two-Wire Interface on port C

Port A

Port C

Port D



61

Base Address

0x07E0

0x0800

0x0840

0x0880

0x0890

0x08A0

0x08B0

0x08C0

0x08E0

0x08F8

0x0940

0x09C0

Name

PORTR

TCC4

TCC5

FAULTC4

FAULTC5

WEXC

HIRESC

USARTC0

SPIC

IRCOM

TCD5

USARTD0

Description

Port R

Timer/Counter 4 on port C

Timer/Counter 5 on port C

Fault Extension on TCC4

Fault Extensionon TCC5

Waveform Extension on port C

High Resolution Extension on port C

USART 0 on port C

Serial Peripheral Interface on port C

Infrared Communication Module

Timer/Counter 5 on port D

USART 0 on port D



62

34.

Instruction Set Summary

Mnemonics

EOR

COM

NEG

SBR

CBR

SBIW

AND

ANDI

OR

ORI

ADD

ADC

ADIW

SUB

SUBI

SBC

SBCI

MUL

MULS

MULSU

FMUL

FMULS

INC

DEC

TST

CLR

SER

FMULSU

DES

RJMP

IJMP

EIJMP

JMP

RCALL

Operands

Rd, Rr

Rd

Rd

Rd,K

Rd,K

Rd, K

Rd, Rr

Rd, K

Rd, Rr

Rd, K

Rd, Rr

Rd, Rr

Rd, K

Rd, Rr

Rd, K

Rd, Rr

Rd, K

Rd,Rr

Rd,Rr

Rd,Rr

Rd,Rr

Rd,Rr

Rd

Rd

Rd

Rd

Rd

Rd,Rr

K k k k

Description Operation

Add without Carry

Add with Carry

Add Immediate to Word

Subtract without Carry

Subtract Immediate

Subtract with Carry

Subtract Immediate with Carry

Subtract Immediate from Word

Logical AND

Logical AND with Immediate

Logical OR

Logical OR with Immediate

Exclusive OR

One’s Complement

Two’s Complement

Set Bit(s) in Register

Clear Bit(s) in Register

Increment

Decrement

Test for Zero or Minus

Clear Register

Set Register

Multiply Unsigned

Multiply Signed

Multiply Signed with Unsigned

Fractional Multiply Unsigned

Fractional Multiply Signed

Fractional Multiply Signed with Unsigned

Arithmetic and Logic Instructions

Data Encryption

Relative Jump

Indirect Jump to (Z)

Extended Indirect Jump to (Z)

Jump

Relative Call Subroutine

Rd

Rd

R1:R0 if (H = 0) then R15:R0 else if (H = 1) then R15:R0

Branch instructions

PC

PC(15:0)

PC(21:16)

PC(15:0)

PC(21:16)

PC

PC

Rd

Rd

Rd

Rd

Rd

Rd

Rd

Rd

Rd

Rd

Rd + 1:Rd

Rd

Rd

Rd

Rd

Rd

Rd

Rd

Rd

Rd

R1:R0

R1:R0

R1:R0

R1:R0

R1:R0











































































Rd + 1

Rd - 1

Rd  Rd

Rd  Rd

$FF

Rd x Rr (UU)

Rd x Rr (SS)

Rd x Rr (SU)

Rd x Rr<<1 (UU)

Rd x Rr<<1 (SS)

Rd x Rr<<1 (SU)

Encrypt(R15:R0, K)

Decrypt(R15:R0, K)

Rd + Rr

Rd + Rr + C

Rd + 1:Rd + K

Rd - Rr

Rd - K

Rd - Rr - C

Rd - K - C

Rd + 1:Rd - K

Rd  Rr

Rd  K

Rd v Rr

Rd v K

Rd  Rr

$FF - Rd

$00 - Rd

Rd v K

Rd  ($FFh - K)

PC + k + 1

Z,

0

Z,

EIND k

PC + k + 1

Flags

None

None

None

None

None



#Clocks

2

2

2

3

2 / 3 (1)

63

Z,C,N,V,S,H

Z,C,N,V,S,H

Z,C,N,V,S

Z,C,N,V,S,H

Z,C,N,V,S,H

Z,C,N,V,S,H

Z,C,N,V,S,H

Z,C,N,V,S

Z,N,V,S

Z,N,V,S

Z,N,V,S

Z,N,V,S

Z,N,V,S

Z,C,N,V,S

Z,C,N,V,S,H

Z,N,V,S

Z,N,V,S

Z,C

Z,C

Z,C

Z,C

Z,C

Z,N,V,S

Z,N,V,S

Z,N,V,S

Z,N,V,S

None

Z,C

1

1

1

1

1

1

1

2

1

1

1

1

2

1

1

1

1

2

2

2

2

2

1

1

1

1

1

2

1/2

k

k

k

k

k

k

k s, k

k

k

Rr, b

Rr, b

A, b

A, b s, k

Rd,Rr

Rd,Rr

Rd,Rr

Rd,K

k

k

k

k

k

k

k

k

k

Mnemonics

ICALL

Operands Description

Indirect Call to (Z)

EICALL

BRVS

BRVC

BRIE

BRID

BRLT

BRHS

BRHC

BRTS

BRTC

BRSH

BRLO

BRMI

BRPL

BRGE

BRBC

BREQ

BRNE

BRCS

BRCC

SBRC

SBRS

SBIC

SBIS

BRBS

CALL

RET

RETI

CPSE

CP

CPC

CPI k

Extended Indirect Call to (Z) call Subroutine

Subroutine Return

Interrupt Return

Compare, Skip if Equal

Compare

Compare with Carry

Compare with Immediate

Skip if Bit in Register Cleared

Skip if Bit in Register Set

Skip if Bit in I/O Register Cleared

Skip if Bit in I/O Register Set

Branch if Status Flag Set

Branch if Status Flag Cleared

Branch if Equal

Branch if Not Equal

Branch if Carry Set

Branch if Carry Cleared

Branch if Same or Higher

Branch if Lower

Branch if Minus

Branch if Plus

Branch if Greater or Equal, Signed

Branch if Less Than, Signed

Branch if Half Carry Flag Set

Branch if Half Carry Flag Cleared

Branch if T Flag Set

Branch if T Flag Cleared

Branch if Overflow Flag is Set

Branch if Overflow Flag is Cleared

Branch if Interrupt Enabled

Branch if Interrupt Disabled

MOV

MOVW

LDI

Rd, Rr

Rd, Rr

Rd, K

Copy Register

Copy Register Pair

Load Immediate if (C = 0) then PC if (C = 1) then PC if (N = 1) then PC if (N = 0) then PC if (N  V= 0) then PC if (N  V= 1) then PC if (H = 1) then PC if (H = 0) then PC if (T = 1) then PC if (T = 0) then PC

Operation

PC(15:0)

PC(21:16)





PC(15:0)

PC(21:16)





PC

PC





PC if (Rd = Rr) PC





Rd - Rr

Rd - Rr - C

Rd - K if (Rr(b) = 0) PC if (Rr(b) = 1) PC if (I/O(A,b) = 0) PC

If (I/O(A,b) =1) PC if (SREG(s) = 1) then PC if (SREG(s) = 0) then PC if (Z = 1) then PC if (Z = 0) then PC if (C = 1) then PC if (C = 0) then PC if (V = 1) then PC if (V = 0) then PC if (I = 1) then PC if (I = 0) then PC

















































Data transfer instructions

Z,

0

Z,

EIND k

STACK

STACK

PC + 2 or 3

PC + k + 1

PC + k + 1

PC + k + 1

PC + k + 1

PC + k + 1

PC + k + 1

PC + k + 1

PC + k + 1

PC + k + 1

PC + k + 1

PC + 2 or 3

PC + 2 or 3

PC + 2 or 3

PC + 2 or 3

PC + k + 1

PC + k + 1

PC + k + 1

PC + k + 1

PC + k + 1

PC + k + 1

PC + k + 1

PC + k + 1

PC + k + 1

PC + k + 1

Rd

Rd+1:Rd

Rd







Rr

Rr+1:Rr

K

Flags

None

None

None

None

None

None

None

None

None

None

None

None

None

None

None

None

None

None

None

None

None

None

None

None

None

None

None

None

I

None

Z,C,N,V,S,H

Z,C,N,V,S,H

Z,C,N,V,S,H

#Clocks

2 / 3 (1)

3

(1)

1 / 2

1 / 2

1 / 2

1 / 2

1 / 2

1 / 2

1 / 2

1 / 2

1 / 2

1 / 2

1 / 2

1 / 2

1 / 2

1 / 2

1 / 2

1 / 2

1 / 2

1 / 2

1 / 2

1 / 2 / 3

1 / 2 / 3

2 / 3 / 4

2 / 3 / 4

1 / 2

3 / 4 (1)

4 / 5 (1)

4 / 5

(1)

1 / 2 / 3

1

1

1

None

None

None

1

1

1



64

Rd, -Z

Rd, Z+q k, Rr

X, Rr

X+, Rr

-X, Rr

Y, Rr

Y+, Rr

-Y, Rr

Y+q, Rr

Z, Rr

Z+, Rr

-Z, Rr

Z+q,Rr

ST

ST

ST

LD

LDD

STS

ST

ST

ST

ST

STD

LPM

LPM

ST

STD

ST

LPM

ELPM

ELPM

ELPM

SPM

LD

LDD

LD

LD

LD

LD

LD

Mnemonics

LDS

LD

LD

Operands

Rd, k

Rd, X

Rd, X+

Description

Load Direct from data space

Load Indirect

Load Indirect and Post-Increment

Rd, -X

Rd, Y

Rd, Y+

Rd, -Y

Rd, Y+q

Rd, Z

Rd, Z+

Load Indirect and Pre-Decrement

Load Indirect



Load Indirect with Displacement

Load Indirect


Rd, Z

Rd, Z+

Rd, Z

Rd, Z+


Load Indirect with Displacement

Store Direct to Data Space

Store Indirect

Store Indirect and Post-Increment

Store Indirect and Pre-Decrement

Store Indirect



Store Indirect with Displacement

Store Indirect



Store Indirect with Displacement

Load Program Memory

Load Program Memory

Load Program Memory and Post-Increment

Extended Load Program Memory

Extended Load Program Memory

Extended Load Program Memory and Post-

Increment

Store Program Memory

Rd

X

X  X - 1,

Rd  (X)

Rd  (Y)

Rd

Y

Y

Rd

Operation

Rd 

Rd 



















Rd

Rd









Rd

Z

Z

Rd

Rd







(k)

(Y)

(Y)

Y

Y

(Y)

(X)

(X)

X

X

(X)



















(Y + q)

(Z)

(Z)

Z

Z

(Z + q)

R0



















Rd

Rd

Z

R0

Rd

Rd

Z

(RAMPZ:Z)

















X - 1

(X)

(Y)

(Y)

Y + 1

X - 1,

Rr

Rr

Rr,

Y + 1

(k)

(X)

(X)

X + 1

Z - 1,

(Z)

(Z + q)

Rd

Rr

Rr,

X + 1

Y - 1

(Y)

(Y + q)

(Z)

(Z),

Z+1

(Z),

Z + 1

(RAMPZ:Z)

(RAMPZ:Z)

(RAMPZ:Z),

Z + 1

R1:R0

Y - 1,

Rr

Rr

Rr

Rr

Z + 1

Z - 1

Rr

(Z)

(Z)



65

None

None

None

None

None

None

None

None

None

None

None

None

None

None

None

None

None

None

None

None

None

None

None

None

None

None

None

None

Flags

None

None

None

#Clocks

2

(1)(2)

1

(1)(2)

1

(1)(2)

2

(1)(2)

2

(1)(2)

1

(1)(2)

1

(1)(2)

2

(1)(2)

1

(1)(2)

1

(1)(2)

2

(1)

1

(1)

1

(1)

2

(1)(2)

2

(1)(2)

2

(1)

1

(1)

1

(1)

3

3

3

2

(1)

2

(1)

1

(1)

1

(1)

3

3

2

(1)

2

(1)

3

-

SEC

CLC

SEN

CLN

SEZ

CLZ

SEI

ASR

SWAP

BSET

BCLR

SBI

CBI

BST

BLD

Mnemonics

SPM

IN

OUT

PUSH

POP

XCH

LAS

LAC

LAT

LSL

LSR

ROL

ROR

Rd

Rd s s

A, b

A, b

Rr, b

Rd, b

Operands

Z+

Rd, A

A, Rr

Rr

Rd

Z, Rd

Z, Rd

Z, Rd

Z, Rd

Rd

Rd

Rd

Rd

Description

Store Program Memory and Post-Increment by 2

In From I/O Location

Out To I/O Location

Push Register on Stack

Pop Register from Stack

Exchange RAM location

Load and Set RAM location

Load and Clear RAM location

Load and Toggle RAM location

Bit and bit-test instructions

Operation

(RAMPZ:Z)

Z





Rd

I/O(A)





STACK

Rd











Temp

Rd

(Z)

Temp

Rd

(Z)

Temp

Rd

(Z)

Temp

Rd

(Z)



















R1:R0,

Z + 2

I/O(A)

Rr

Rr

STACK

Rd,

(Z),

Temp

Rd,

(Z),

Temp v (Z)

Rd,

(Z),

($FFh – Rd)



(Z)

Rd,

(Z),

Temp  (Z)

Logical Shift Left

Logical Shift Right













Rd(n),

0,

Rd(7)

Rd(n+1),

0,

Rd(0)

Rotate Left Through Carry

Rotate Right Through Carry

Arithmetic Shift Right

Swap Nibbles

Flag Set

Flag Clear

Set Bit in I/O Register

Clear Bit in I/O Register

Bit Store from Register to T

Bit load from T to Register

Set Carry

Clear Carry

Set Negative Flag

Clear Negative Flag

Set Zero Flag

Clear Zero Flag

Global Interrupt Enable

N

N

C

C

Z

Z

I

Rd(n+1)

Rd(0)

C

Rd(n)

Rd(7)

C

Rd(0)

Rd(n+1)

C

Rd(7)

Rd(n)

C

Rd(n)

Rd(3..0)

SREG(s)

SREG(s)

I/O(A, b)

I/O(A, b)

T

Rd(b)













C,

Rd(n),

Rd(7)

C,

Rd(n+1),

Rd(0)

























 Rd(n+1), n=0..6

 Rd(7..4)

 1

0

1

0

Rr(b)

T

1

0

1

0

1

0

1

Z,C,N,V,H

Z,C,N,V

Z,C,N,V,H

Z,C,N,V

N

N

C

C

Z

I

Z

Z,C,N,V

None

SREG(s)

SREG(s)

None

None

T

None

None

None

None

Flags

None

None

None

None

None

None

2

2

2

#Clocks

-

1

1

1

(1)

2

(1)

2

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1



66

Mnemonics

CLI

SES

CLS

SEV

CLV

SET

CLT

SEH

CLH

Operands Description

Global Interrupt Disable

Set Signed Test Flag

Clear Signed Test Flag

Set Two’s Complement Overflow

Clear Two’s Complement Overflow

Set T in SREG

Clear T in SREG

Set Half Carry Flag in SREG

Clear Half Carry Flag in SREG

Operation

I 

S

S

V

V

T











T

H

H







0

1

0

1

0

0

1

1

0

I

Flags

S

BREAK

NOP

SLEEP

WDR

Notes:

MCU control instructions

Break

No Operation

Sleep

(See specific descr. for BREAK) None

None

None (see specific descr. for Sleep)

Watchdog Reset (see specific descr. for WDR) None

1.

Cycle times for data memory accesses assume internal memory accesses, and are not valid for accesses via the external RAM interface.

2.

One extra cycle must be added when accessing internal SRAM.

V

T

S

V

T

H

H

#Clocks

1

1

1

1

1

1

1

1

1

1

1

1

1



67

35.

Packaging Information

35.1

32A



68

35.2

32Z



69

35.3

32MA



70

36.

Electrical Characteristics

All typical values are measured at T = 25°C unless other temperature condition is given. All minimum and maximum values are valid across operating temperature and voltage unless other conditions are given.

36.1

Absolute Maximum Ratings

Symbol

V

CC

I

VCC

I

GND

V

PIN

I

PIN

T

A

T j

Parameter

Power supply voltage

Current into a V

CC

pin

Current out of a Gnd pin

Pin voltage with respect to Gnd and V

CC

I/O pin sink/source current

Storage temperature

Junction temperature

Min.

-0.3

-0.5

-25

-65

Typ.

Max.

4

200

200

V

CC

+0.5

25

150

150

Units

V mA

V mA

°C

36.2

General Operating Ratings

The device must operate within the ratings listed in

Table 36-1 in order for all other electrical characteristics and typical

characteristics of the device to be valid.

Table 36-1. General Operating Conditions

Symbol

V

CC

AV

CC

T

A

T j

Parameter

Power supply voltage


Temperature range

Junction temperature

Min.

1.6

1.6

-40

-40

Typ.

Max.

3.6

3.6

85

105

Units

V

°C

Table 36-2. Operating Voltage and Frequency

Symbol

Clk

CPU

Parameter

CPU clock frequency

Condition

V

CC

= 1.6V

V

CC

= 1.8V

V

CC

= 2.7V

V

CC

= 3.6V

Min.

0

0

0

0

Typ.

Max.

12

12

32

32

Units

MHz

The maximum CPU clock frequency depends on V

CC

. As shown in

Figure 36-1 the frequency vs. V

CC between 1.8V < V

CC

< 2.7V.

curve is linear



71

Figure 36-1. Maximum Frequency vs. V

CC

MHz

32

12

1.6

1.8

Safe Operating Area

2.7

3.6

V



72

36.3

Current Consumption

Table 36-3. Current Consumption for Active Mode and Sleep Modes

Symbol Parameter Condition

Notes:

I

CC

Active power

consumption

Idle power

consumption

Power-down power consumption

Power-save power consumption

(1)

(1)

Reset power consumption

1.

All Power Reduction Registers set.

32kHz, Ext. Clk

1MHz, Ext. Clk

2MHz, Ext. Clk

32MHz, Ext. Clk

32kHz, Ext. Clk

1MHz, Ext. Clk

2MHz, Ext. Clk

32MHz, Ext. Clk

All disabled, T = 25°C



WDT and sampled BOD enabled,

T = 25°C


T = 85°C


T = 105°C

RTC from ULP clock, WDT and sampled BOD enabled, T = 25 C

RTC from ULP clock, WDT, sampled BOD enabled and 8MHz internal oscillator in low power mode, T = 25 C

RTC on 1kHz low power 32.768kHz

TOSC, T = 25 C

RTC from low power 32.768kHz

TOSC, T = 25 C

Current through RESET pin substracted, T = 25°C

V

CC

= 1.8V

V

CC

= 3.0V

V

CC

= 1.8V

V

CC

= 3.0V

V

CC

= 1.8V

V

CC

= 3.0V

V

CC

= 3.0V

V

CC

= 1.8V

V

CC

= 3.0V

V

CC

= 1.8V

V

CC

= 3.0V

V

CC

= 1.8V

V

CC

= 3.0V

V

CC

= 3.0V

V

CC

= 3.0V

V

CC

= 3.0V

V

CC

= 1.8V

V

CC

= 3.0V

V

CC

= 1.8V

V

CC

= 3.0V

V

CC

= 1.8V

V

CC

= 3.0V

V

CC

= 1.8V

V

CC

= 3.0V

V

CC

= 3.0V



73

Min.

1.2

0.6

0.8

0.9

0.9

1.0

110

2.5

0.4

0.6

0.5

Typ.

200

3.5

0.1

1

2

12

55

105

110

300

0.6

7

7

20

35

155

290

0.5

Max.

Units

400

1.2

10

250

350

5

0.9

3

5

3.5

6

µA mA

µA mA

µA

Table 36-4. Current Consumption for Modules and Peripherals

Symbol

Condition

(1)

Parameter

Internal ULP oscillator

32.768kHz int. oscillator

8MHz int. oscillator

Normal power mode

Low power mode

Min.

Typ.

Max.

Units

100

27 nA

65

45

275

400

32MHz int. oscillator

PLL

DFLL enabled with 32.768kHz int. osc. as reference

20x multiplication factor,

32MHz int. osc. DIV4 as reference

230 µA

Notes:

I

CC

Watchdog timer

BOD

Internal 1.0V reference

Internal temperature sensor

Continuous mode

Sampled mode

ADC

16ksps

V

REF

= Ext. ref.

CURRLIMIT = LOW

CURRLIMIT = MEDIUM

CURRLIMIT = HIGH

CURRLIMIT = LOW

DAC

75ksps, V

REF

= Ext. ref.

300ksps, V

REF

= Ext. ref.

250ksps

V

REF

= Ext. ref.

No load

Normal mode

Low Power mode

AC

EDMA

Timer/counter

USART

XCL

Rx and Tx enabled, 9600 BAUD

16-bit timer/counter

Flash memory and EEPROM programming

0.3

245

0.4

200

100

1.5

1.4

1.3

1.2

1.7

3.1

1.9

1.1

8

6

4

200

200

25 mA

µA mA

1.

All parameters measured as the difference in current consumption between module enabled and disabled. All data at V

CC without prescaling, T = 25°C unless other conditions are given.

= 3.0V, Clk

SYS

= 1MHz external clock



74

36.4

Wake-up Time from Sleep Modes

Table 36-5. Device Wake-up Time from Sleep Modes with Various System Clock Sources t

Symbol wakeup

Notes:

Parameter

Wake-up time from idle, standby, and extended standby mode

Wake-up time from power save mode

8MHz internal oscillator

Wake-up time from power down mode

Condition

External 2MHz clock

32kHz internal oscillator



External 2MHz clock



External 2MHz clock




Normal mode

Low power mode

Min.

Typ.

(1)

0.2

120

0.5

0.2

4.5

320

4.5

0.5

5.0

4.5

320

4.5

5.0

Max.

Units

µs

1.

The wake-up time is the time from the wake-up request is given until the peripheral clock is available on pin, see Figure 36-2 . All peripherals and

modules start execution from the first clock cycle, expect the CPU that is halted for four clock cycles before program execution starts.

Figure 36-2. Wake-up Time Definition

Wakeup time

Wakeup request

Clock output



75

36.5

I/O Pin Characteristics

The I/O pins complies with the JEDEC LVTTL and LVCMOS specification and the high- and low-level input and output voltage limits reflect or exceed this specification.

Table 36-6. I/O Pin Characteristics

Symbol Parameter

I

OH

(1) /

I

OL

(2)

I/O pin source/sink current

V

V

V

V

IH

IL

OH

OL

High level input voltage, except XTAL1 and RESET pin

Low level input voltage, except XTAL1 and RESET pin

High level output voltage

Low level output voltage

Input leakage current

Pull/buss keeper resistor

Condition

V

CC

= 2.4 - 3.6V

V

CC

= 1.6 - 2.4V

V

CC

= 2.4 - 3.6V

V

CC

= 1.6 - 2.4V

V

CC

= 3.3V

V

CC

= 3.0V

V

CC

= 1.8V

V

CC

= 3.3V

V

CC

= 3.0V

V

CC

= 1.8V

T = 25°C

Notes:

I

IN

R

P

1.

The sum of all I

The sum of all I

OH

OH

The sum of all I

OH

for PA[7:5] on PORTA must not exceed 100mA.


The sum of all I

OH

for PORTD and PORTR must not exceed 100mA.

for PORTC and PDI must not exceed 100mA.

2.

The sum of all I

The sum of all I

OL

OL

The sum of all I

OL



The sum of all I

OL

for PORTD and PORTR must not exceed 100mA.

for PORTC PDI must not exceed 100mA.

I

OH

= -4mA

I

OH

= -3mA

I

OH

= -1mA

I

OL

= 8mA

I

OL

= 5mA

I

OL

= 3mA

36.6

ADC Characteristics

Table 36-7. Power Supply, Reference, and Input Range


AV

CC

V

REF

R in

C in

R

AREF

C

AREF


Reference voltage

Input resistance

Input capacitance

Reference input resistance

Reference input capacitance

Switched

Switched

Condition

(leakage only)

Static load

Min.

-15

0.7*V

CC

0.8*V

CC

-0.5

-0.5

2.6

2.1

1.4

Min.

V

CC

- 0.3

1

Typ.

3.1

2.7

1.7

0.20

0.15

0.10

<0.01

27

Typ.

>10

7

Max.

15

V

CC

+0.5

V

CC

+0.5

0.3*V

CC

0.2*V

CC

0.76

0.64

0.46

1.0

Max.

V

CC

+ 0.3

AV

CC

- 0.6

4.5

5

Units mA

V

µA k 

Units

V k  pF

M  pF



76


Vin Input range

Vin

Vin

Conversion range

Conversion range

Table 36-8. Clock and Timing


Clk f

ClkADC f

ADC

ADC

ADC Clock frequency

Sample rate

Sample rate

Sampling Time

Conversion time (latency)

Start-up time

ADC settling time

Condition

Differential mode, Vinp - Vinn

Single ended unsigned mode, Vinp

Min.

0

-0.95*V

REF

-0.05*V

REF

Typ.

Max.

V

REF

0.95*V

REF

0.95*V

REF

Units

V

Condition

Maximum is 1/4 of Peripheral clock frequency

Measuring internal signals

Min.

100

16

16 Current limitation (CURRLIMIT) off

CURRLIMIT = LOW

CURRLIMIT = MEDIUM

CURRLIMIT = HIGH

1/2 Clk

ADC cycle

(RES+2)/2+(GAIN !=0)

RES (Resolution) = 8 or 12

ADC clock cycles

After changing reference or input mode

0.25

6

Typ.

125

12

7

Max.

1800

Units kHz

300

300

250

150

50

5

10

24

7 ksps

µs

Clk

ADC cycles

Table 36-9. Accuracy Characteristics


RES

INL (1)

Resolution

Integral non-linearity

Condition

(2)

Differential

12-bit resolution

Differential mode

Single ended unsigned mode

Single ended signed

Single ended unsigned

16ksps, V

REF

= 3V

16ksps, V

REF

= 1V

300ksps, V

REF

= 3V

300ksps, V

REF

= 1V

16ksps, V

REF

= 3.0V

16ksps, V

REF

= 1.0V

Min.

8

7

8

Typ.

12

1

2

11

12

1

2

1

2

Max.

12

11

12

Units

Bits

1.5

3 lsb



77

Symbol

DNL

Notes:

(1)

Parameter

Differential non-linearity

Differential mode


Condition

(2)

16ksps, V

REF

= 3V

16ksps, V

REF

= 1V

300ksps, V

REF

= 3V

300ksps, V

REF

= 1V

16ksps, V

REF

= 3.0V

16ksps, V

REF

= 1.0V

Min.

Typ.

1

2

Offset Error

Gain Error

Differential mode

Differential mode

Temperature drift

Operating voltage drift

External reference

AV

CC

/1.6

AV

CC

/2.0

Bandgap

Temperature drift

-6

±10

0.02

Gain Error


Operating voltage drift

External reference

AV

CC

/1.6

AV

CC

/2.0

Bandgap

Temperature drift

2

-8

-8

-8

±10

0.03

Operating voltage drift 2

1.

Maximum numbers are based on characterisation and not tested in production, and valid for 10% to 90% input voltage range.

2.

Unless otherwise noted all linearity, offset and gain error numbers are valid under the condition that external V

REF

is used.

2

8

0.01

1

2

1

0.25

-5

-5

Max.

1.5

3

Units lsb mV mV/K mV/V mV mV/K mV/V mV mV/K mV/V

Table 36-10. Gain Stage Characteristics

Symbol

R in

C sample

Parameter

Input resistance

Input capacitance

Signal range

Propagation delay

Clock rate

Condition

Switched

Switched

Gain stage output

ADC conversion rate

Same as ADC

Min.

0

1/2

100

Typ.

4.0

4.4

1

Max.

AV

CC

- 0.6

3

1800

Units k  pF

V

Clk

ADC cycles kHz



78


Gain error

Offset error, input referred

0.5x gain

1x gain

8x gain

64x gain

0.5x gain

1x gain

8x gain

64x gain

Condition

36.7

DAC Characteristics

Table 36-11. Power Supply, Reference, and Output Range


AV

CC

AV

REF

R channel


External reference voltage

DC output impedance

Linear output voltage range

R

AREF

C

AREF

Reference input resistance

Reference input capacitance Static load

Minimum Resistance load

Condition

Maximum capacitance load

Output sink/source

1000  serial resistance

Operating within accuracy specification

Safe operation

Min.

Typ.

-1

-1

5

5

5

-1

-1.5

10

Max.

Units

% mV

Min.

V

CC

- 0.3

1.0

0.15

1

Typ.

>10

7

Max.

V

CC

+ 0.3

V

CC

- 0.6

50

V

REF

-0.15

Units

100

1

AV

CC

/1000

10

M  pF k 

V



V pF nF mA

Table 36-12. Clock and Timing

Symbol Parameter f

DAC

Conversion rate

C load

=100pF, maximum step size

Condition

Normal mode

Low power mode

Min.

0

0

Typ.

Max.

1000

500

Units ksps



79

Table 36-13. Accuracy Characteristics


RES Input Resolution

Condition Min.

Typ.

INL (1)

DNL

Note:

(1)

Integral non-linearity

Differential non-linearity

V

V

V

V

V

REF

REF

REF

REF

REF

= Ext 1.0V

=AV

CC

=INT1V

=Ext 1.0V

=AV

CC

V

REF

=INT1V

After calibration

V

V

V

V

V

V

V

V

CC

CC

V

CC

V

CC

V

CC

V

CC

CC

CC

CC

CC

CC

CC

= 1.6V

= 3.6V

= 1.6V

= 3.6V

= 1.6V

= 3.6V

= 1.6V

= 3.6V

= 1.6V

= 3.6V

= 1.6V

= 3.6V

Gain error

Gain calibration step size

Gain calibration drift

Offset error

Offset calibration step size

V

REF

= Ext 1.0V

After calibration

1.

Maximum numbers are based on characterisation and not tested in production, and valid for 5% to 95% output voltage range.

±5.0

±1.5

±0.6

±1.0

±0.6

±4.5

±2.0

±1.5

±2.0

±1.5

±5.0

±4.5

<4

4

<0.2

<1

1

Max.

12

±3

±2.5

±4

±4

Units

Bits

3

1.5

3.5

1.5

lsb mV/K lsb

36.8

Analog Comparator Characteristics

Table 36-14. Analog Comparator Characteristics

Symbol

V off

I lk

V

V

V hys1 hys2 hys3

Parameter

Input offset voltage

Input leakage current

Input voltage range

AC startup time

Hysteresis, none

Hysteresis, small

Hysteresis, large t delay

Propagation delay

Condition

V

CC

= 1.6V - 3.6V

V

CC

= 1.6V - 3.6V

V

CC

= 1.6V - 3.6V

V

CC

= 3.0V, T= 85°C

V

CC

= 1.6V - 3.6V

Min.

-0.1

28

22

21

50

0

12

Typ.

10

<10

Max.

50

AV

CC

30

40



Units mV nA

V

µs mV ns

80


64-Level Voltage Scaler Integral nonlinearity (INL)

Current source accuracy after calibration

Current source calibration range

Current source calibration range

Condition

Single mode

Double mode

Min.

Typ.

0.3

5

4

8

Max.

0.5

6

12

Units lsb

%

µA

36.9

Bandgap and Internal 1.0V Reference Characteristics

Table 36-15. Bandgap and Internal 1.0V Reference Characteristics


Startup time

Condition

As reference for ADC

As input voltage to ADC and

AC

BANDGAP Bandgap voltage

INT1V

Internal 1.00V reference for ADC and

DAC

Variation over voltage and temperature

T= 25°C, after calibration

Calibrated at T= 25°C

Min.

Typ.

1 Clk

PER

+ 2.5μs

Max.

1.5

0.99

1.1

1.0

±3

1.01

Units

µs

V

%

36.9.1

Brownout Detection Characteristics


V

BOT

BOD level 0 falling V

CC


CC


CC


CC


CC


CC


CC


CC

T

BOD

V

HYST

Detection time

Hysteresis

Continuous mode

Sampled mode

BOD level 0 - 7. Min value measured at BOD level 0

Min.

1.50

2.4

2.6

2.8

3.0

0.4

1.0

Typ.

1.65

1.8

2.0

2.2

1.0

Max.

1.75

Units

V

µs ms

%



81

36.10 External Reset Characteristics

Table 36-16. External Reset Characteristics

Symbol t

EXT

Parameter

Minimum reset pulse width

Reset threshold voltage (V

IH

)

V

RST

Reset threshold voltage (V

IL

)

Condition

V

CC

= 2.7 - 3.6V

V

CC

= 1.6 - 2.7V

V

CC

= 2.7 - 3.6V

V

CC

= 1.6 - 2.7V

R

RST

Reset pin Pull-up Resistor

Min.

90

0.6*V

CC

0.6*V

CC

Typ.

1000

Max.

0.5*V

CC

0.4*V

CC

25

Units ns k

V



36.11 Power-on Reset Characteristics

Table 36-17. Power-on Reset Characteristics

Symbol

V

POT-

(1)

Parameter

POR threshold voltage falling V

CC

Condition

V

CC

falls faster than 1V/ms

V

CC

falls at 1V/ms or slower

Note:

V

POT+

POR threshold voltage raising V

CC

1.

V

POT-

values are only valid when BOD is disabled. When BOD is enabled V

POT-

= V

POT+

.

36.12 Flash and EEPROM Characteristics

Table 36-18. Endurance and Data Retention

Parameter Condition

Flash

EEPROM

Write/Erase cycles

Data retention

Write/Erase cycles

Data retention

25 C

85°C

105°C

25°C

85°C

105°C

25°C

85°C

105°C

25°C

85°C

105°C

Min.

0.4

0.8

Typ.

1.0

1.3

1.3

Max.

1.59

Units

V

100K

100K

30K

100

25

10

Min.

10K

10K

2K

100

25

10

Typ.

Max.

Units

Cycle

Year

Cycle

Year



82

Table 36-19. Programming Time

Parameter

Chip Erase

Flash

EEPROM

Condition

32KB Flash, EEPROM (2)



Page erase

Page write

Atomic page erase and write

Page erase

Page write

Atomic page erase and write

Notes: 1.

Programming is timed from the 2MHz output of 8MHz internal oscillator.

2.

EEPROM is not erased if the EESAVE fuse is programmed.

Min.

Typ.

(1)

50

45

42

4

4

8

4

4

8

Max.

Units ms



83

36.13 Clock and Oscillator Characteristics

36.13.1 Calibrated 32.768kHz Internal Oscillator Characteristics

Table 36-20. 32.768kHz Internal Oscillator Characteristics

Condition Symbol Parameter

Frequency

Factory calibration accuracy

User calibration accuracy

T = 25°C, V

CC

= 3.0V

36.13.2 Calibrated 8MHz Internal Oscillator Characteristics

Table 36-21. 8MHz Internal Oscillator Characteristics


Frequency range

Factory calibrated frequency



T = 25°C, V

CC

= 3.0V

Min.

-0.5

-0.5

Typ.

32.768

Max.

0.5

0.5

Units kHz

%

Min.

4.4

Typ.

8

-0.5

-0.5

Max.

9.4

Units

MHz

0.5

0.5

%

36.13.3 Calibrated and Tunable 32MHz Internal Oscillator Characteristics

Table 36-22. 32MHz Internal Oscillator Characteristics


Frequency range

Condition

DFLL can tune to this frequency over voltage and temperature

Factory calibrated frequency



DFLL calibration step size

T = 25°C, V

CC

= 3.0V

Min.

30

Typ.

32

-1.5

-0.2

0.23

Max.

55

Units

MHz

1.5

0.2

%

36.13.4 32 kHz Internal ULP Oscillator Characteristics

Table 36-23. 32 kHz Internal ULP Oscillator Characteristics


Output frequency

Accuracy

Min.

Typ.

32

-30

Max.

30

Units kHz

%



84

36.13.5 Internal Phase Locked Loop (PLL) Characteristics

Table 36-24. Internal PLL Characteristics

Symbol Parameter f

IN

Input frequency f

OUT

Output frequency

(1)

Condition

Output frequency must be within f

OUT

V

CC

= 1.6 - 1.8V

V

CC

= 2.7 - 3.6V

Start-up time

Re-lock time

Min.

0.4

20

20

Typ.

25

25

Max.

64

48

128

Units

MHz

µs

Note: 1.

The maximum output frequency vs. supply voltage is linear between 1.8V and 2.7V, and can never be higher than four times the maximum CPU frequency.

36.13.6 External Clock Characteristics

Figure 36-3. External Clock Drive Waveform t

CH t

CH t

CR t

CF

V

IH1

V

IL1 t

CL t

CK

Table 36-25. External Clock used as System Clock without Prescaling


1/t t t t t t

CK

CK

CH

CL

CR

CF

Clock Frequency

Clock Period

Clock High Time

Clock Low Time

(1)

Rise Time (for maximum frequency)

Fall Time (for maximum frequency)

Condition

V

CC

= 1.6 - 1.8V

V

CC

= 2.7 - 3.6V

V

CC

= 1.6 - 1.8V

V

CC

= 2.7 - 3.6V

V

CC

= 1.6 - 1.8V

V

CC

= 2.7 - 3.6V

V

CC

= 1.6 - 1.8V

V

CC

= 2.7 - 3.6V

V

CC

= 1.6 - 1.8V

V

CC

= 2.7 - 3.6V

V

CC

= 1.6 - 1.8V

V

CC

= 2.7 - 3.6V

t

CK

Change in period from one clock cycle to the next

Note:

Min.

0

0

83.3

31.5

30.0

12.5

30.0

12.5

Typ.

Max.

12

32

10

3

10

3

10

Units

MHz ns

%

1.

The maximum frequency vs. supply voltage is linear between 1.6V and 2.7V, and the same applies for all other parameters with supply voltage conditions.



85

Table 36-26. External Clock with Prescaler

(1)

for System Clock

Symbol

1/t t t t t t

CK

CK

CH

CL

CR

CF

Parameter

Clock Frequency

Clock Period

Clock High Time

Clock Low Time

(2)

Rise Time (for maximum frequency)

Fall Time (for maximum frequency)

V

CC

V

CC

V

CC

Condition

V

CC

= 1.6 - 1.8V

V

CC

= 2.7 - 3.6V

V

CC

= 1.6 - 1.8V

V

CC

= 2.7 - 3.6V

V

CC

= 1.6 - 1.8V

V

CC

= 2.7 - 3.6V

V

CC

= 1.6 - 1.8V

V

CC

= 2.7 - 3.6V

V

CC

= 1.6 - 1.8V

= 2.7 - 3.6V

= 1.6 - 1.8V

= 2.7 - 3.6V

Min.

0

0

11

7

4.5

2.4

4.5

2.4

Typ.

Max.

90

142

1.5

1.0

1.5

1.0

10

Units

MHz ns

t

CK

Notes:

Change in period from one clock cycle to the next %

1.

System Clock Prescalers must be set so that maximum CPU clock frequency for device is not exceeded.

2.

The maximum frequency vs. supply voltage is linear between 1.6V and 2.7V, and the same applies for all other parameters with supply voltage conditions.

36.13.7 External 16MHz Crystal Oscillator and XOSC Characteristics

Table 36-27. External 16MHz Crystal Oscillator and XOSC Characteristics


Cycle to cycle jitter

XOSCPWR=0

FRQRANGE=0

FRQRANGE=1, 2, or 3

XOSCPWR=1

Long term jitter

XOSCPWR=0

FRQRANGE=0

FRQRANGE=1, 2, or 3

XOSCPWR=1

Min.

Typ.

<10

<1

<1

<6

<0.5

<0.5

Max.

Units ns



86


Frequency error

Duty cycle

Condition

XOSCPWR=0

XOSCPWR=1

XOSCPWR=0

XOSCPWR=1

XOSCPWR=0,

FRQRANGE=0

XOSCPWR=0,

FRQRANGE=1,

CL=20pF

XOSCPWR=0,

FRQRANGE=2,

CL=20pF

R

Q

Negative impedance (1)

XOSCPWR=0,

FRQRANGE=3,

CL=20pF

ESR

XOSCPWR=1,

FRQRANGE=0,

CL=20pF

XOSCPWR=1,

FRQRANGE=1,

CL=20pF

XOSCPWR=1,

FRQRANGE=2,

CL=20pF

XOSCPWR=1,

FRQRANGE=3,

CL=20pF

SF=Safety factor

FRQRANGE=0

FRQRANGE=1

FRQRANGE=2 or 3

FRQRANGE=0

FRQRANGE=1

FRQRANGE=2 or 3

0.4MHz resonator,

CL=100pF

1MHz crystal, CL=20pF

2MHz crystal, CL=20pF

2MHz crystal

8MHz crystal

9MHz crystal

8MHz crystal

9MHz crystal

12MHz crystal

9MHz crystal

12MHz crystal

16MHz crystal

9MHz crystal

12MHz crystal

16MHz crystal

9MHz crystal

12MHz crystal

16MHz crystal

12MHz crystal

16MHz crystal

12MHz crystal

16MHz crystal

Min.

Typ.

<0.1

<0.05

<0.005

<0.005

40

42

45

48

Max.

Units

% min(RQ)

/SF k







87


C

XTAL1

Parasitic capacitance

XTAL1 pin

C

C

XTAL2

LOAD

Parasitic capacitance

XTAL2 pin

Parasitic capacitance load

Note:

Condition Min.

1.

Numbers for negative impedance are not tested in production but guaranteed from design and characterization.

Typ.

5.4

7.1

3.07

Max.

Units pF

36.13.8 External 32.768kHz Crystal Oscillator and TOSC Characteristics

Table 36-28. External 32.768kHz Crystal Oscillator and TOSC Characteristics


ESR/R1

Recommended crystal equivalent series resistance (ESR)

C

TOSC1

C

TOSC2

Parasitic capacitance TOSC1 pin

Parasitic capacitance TOSC2 pin

Recommended safety factor

Condition

Crystal load capacitance 6.5pF

Crystal load capacitance 9.0pF

capacitance load matched to crystal specification

Note: 1.

See Figure 36-4 for definition.

Figure 36-4. TOSC Input Capacitance

Min.

Typ.

3.0

5.3

7.4

Max.

60

35

Units k  pF

T O S C 1

C

L1

C

L2

Device internal

External

T O S C 2

32.768kHz crystal

The parasitic capacitance between the TOSC pins is C

L1

+ C

L2

in series as seen from the crystal when oscillating without external capacitors.



88

36.14 SPI Characteristics

Figure 36-5. SPI Timing Requirements in Master Mode

SS t

MOS

SCK

(CPOL = 0)

SCK

(CPOL = 1)

MISO

(Data Input) t

MIS

MSB t

MIH t

MOH

MOSI

(Data Output)

M S B

Figure 36-6. SPI Timing Requirements in Slave Mode

SS t

SSS

SCK

(CPOL = 0)

SCK

(CPOL = 1) t

SIS

MSB t

SIH

MOSI

(Data Input)

MISO

(Data Output) t

SOSSS

M S B t

SOS t

SCKR t

SCKF t

SCKW t

SCK

LSB t

SCKW t

MOH

L S B t

SCKR t

SCKF t

SSH t

SSCKW t

SSCK

LSB t

SSCKW t

SOSSH

L S B



89

Table 36-29. SPI Timing Characteristics and Requirements

Symbol Parameter t

SSCKW t

SSCKR t

SSCKF t

SIS t

SIH t

SSS t

SCK t

SCKW t

SCKR t

SCKF t

MIS t

MIH t

MOS t

MOH t

SSCK t

SSH t

SOS t

SOH t

SOSS t

SOSH

SCK period

SCK high/low width

SCK rise time

SCK fall time

MISO setup to SCK

MISO hold after SCK

MOSI setup SCK

MOSI hold after SCK

Slave SCK Period

SCK high/low width

SCK rise time

SCK fall time

MOSI setup to SCK

MOSI hold after SCK

SS setup to SCK

SS hold after SCK

MISO setup SCK

MISO hold after SCK

MISO setup after SS low

MISO hold after SS high

Slave

Slave

Slave

Slave

Slave

Slave

Slave

Slave

Master

Master

Slave

Slave

Slave

Slave

Master

Master

Master

Condition

Master

Master

Master

Min.

4×t Clk

PER

2×t Clk

PER

3.0

t Clk

PER

21

20

Typ.

0.5×SCK

2.7

2.7

10

10

0.5×SCK

1.0

8.0

13

11

8.0

Max.

Units

1600

1600 ns



90

36.15 Two-Wire Interface Characteristics

Table 36-6 on page 76

describes the requirements for devices connected to the two-wire interface (TWI) Bus. The Atmel

AVR XMEGA TWI meets or exceeds these requirements under the noted conditions. Timing symbols refer to Figure 36-

7 .

Figure 36-7. Two-wire Interface Bus Timing t of t

HIGH t

LOW t r

SCL t

SU;STA t

HD;DAT t

HD;STA t

SU;DAT t

SU;STO

SDA t

BUF

Table 36-30. Two-wire Interface Characteristics

Symbol t

V

IH

V

IL

V hys

V

OL t

I t

OL t

R r of

SP

I

I

C

I f

SCL

P

HD;STA

Parameter

Input high voltage

Input low voltage

Hysteresis of Schmitt trigger inputs

Output low voltage

Low level output current

Rise time for both SDA and SCL

Output fall time from V

IHmin

to V

ILmax

Spikes suppressed by Input filter

Input current for each I/O Pin

Capacitance for each I/O Pin

SCL clock frequency

Value of pull-up resistor

Hold time (repeated) START condition

Condition Min.

3mA, sink current f

SCL

≤ 400kHz f

SCL

≤ 1MHz f

SCL

≤ 400kHz f

SCL

≤ 1MHz

V

OL

= 0.4V

0.7V

CC

-0.5

0.05V

CC

(1)

0

3

20

20+0.1C

b

(1)(2)

10pF< C b

<400pF

(2)

0.1 V

CC

<V

I

<0.9 V

CC f

SCL

≤ 400kHz 20+0.1C

b

(1)(2)

f

SCL

≤ 1MHz

0

-10 f

PER

(3) > max(10f

SCL

,250kHz) f

SCL

≤ 100kHz f

SCL

≤ 400kHz f

SCL

≤ 1MHz f

SCL

≤ 100kHz f

SCL

≤ 400kHz f

SCL

≤ 1MHz

(V

CC

0

-0.4V)/I

4

0.6

0.26

OL

Typ.

Max.

V

CC

+0.5

0.3V

CC

0.4

300

120

250

120

50

10

10

1

100ns/C b

300ns/C b

550ns/C b

Units

V mA ns

µA pF

MHz

Ω

µs



91

Symbol t t t t t t

LOW

HIGH

SU;STA

HD;DAT

SU;DAT

SU;STO t

BUF

Parameter

Low period of SCL Clock

High period of SCL Clock

Set-up time for a repeated START condition

Data hold time

Data setup time

Setup time for STOP condition

Bus free time between a STOP and

START condition

Condition f

SCL

≤ 100kHz f

SCL

≤ 400kHz f

SCL

≤ 1MHz f

SCL

≤ 100kHz f

SCL

≤ 400kHz f

SCL

≤ 1MHz f

SCL

≤ 100kHz f

SCL

≤ 400kHz f

SCL

≤ 1MHz f

SCL

≤ 100kHz f

SCL

≤ 400kHz f

SCL

≤ 1MHz f

SCL

≤ 100kHz f

SCL

≤ 400kHz f

SCL

≤ 1MHz f

SCL

≤ 100kHz f

SCL

≤ 400kHz f

SCL

≤ 1MHz f

SCL

≤ 100kHz f

SCL

≤ 400kHz f

SCL

≤ 1MHz

Notes: 1.

Required only for f

SCL

> 100kHz.

2.

C b

= Capacitance of one bus line in pF.

3.

f

PER

= Peripheral clock frequency.

50

4

0.6

0

250

100

0.26

4.7

1.3

0.5

Min.

4.7

1.3

0.5

4

0.6

0.26

4.7

0.6

0.26

0

0

Typ.

Max.

Units

3.45

0.9

0.45

µs ns

µs



92

37.

Typical Characteristics

37.1

Current Consumption

37.1.1

Active Mode Supply Current

Figure 37-1. Active Mode Supply Current vs. Frequency f

SYS

= 0 – 1MHz external clock, T = 25°C

0.35

0.30

0.25

0.20

0.15

0.10

0.05

0.00

0.0

0.2

0.4

0.6

Frequency [MHz]

0.8

1.0

V_CC_ 1.6

1.8

2.2

2.7

3

3.6

Figure 37-2. Active Mode Supply Current vs. Frequency f

SYS

= 0 – 32MHz external clock, T = 25°C

9

8

7

6

5

4

3

2

1

0

0 4 8 12 16

Frequency [MHz]

20 24 28 32

V_CC_

2.7

3

3.6

1.6

1.8

2.2



93

Figure 37-3. Active Mode Supply Current vs. V

CC f

SYS

= 32.768kHz internal oscillator

38.0

37.0

36.0

35.0

34.0

33.0

32.0

31.0

30.0

29.0

28.0

27.0

1.6

1.8

2.0

2.2

2.4

2.6

Vcc [V]

2.8

3.0

3.2

3.4

3.6

Temperature -40

25

85

105


CC f

SYS

= 1MHz external clock

0.35

0.30

0.25

0.20

0.15

0.10

1.6

1.8

2.0

2.2

2.4

2.6

Vcc [V]

2.8

3.0

3.2

3.4

3.6

Temperature -40

25

85

105



94


CC f

SYS

= 8MHz internal oscillator prescaled to 2MHz

0.8

0.7

0.6

0.5

0.4

0.3

0.2

1.6

1.8

2.0

2.2

2.4

2.6

Vcc [V]

2.8

3.0

3.2

3.4

3.6

Temperature -40

25

85

105


CC f

SYS

= 8MHz internal oscillator

2.5

2.0

1.5

1.0

0.5

1.6

1.8

2.0

2.2

2.4

2.6

Vcc [V]

2.8

3.0

3.2

3.4

3.6

Temperature -40

25

85

105



95

Figure 37-7. Active mode Supply Current vs. V

CC f

SYS


3.0

2.5

2.0

1.5

1.0

1.6

1.8

2.0

2.2

2.4

2.6

Vcc [V]

2.8

3.0

3.2

3.4

3.6

Temperature -40

25

85

105


CC f

SYS


8.0

7.5

7.0

6.5

6.0

5.5

5.0

4.5

2.6

2.7

2.8

2.9

3.0

3.1

Vcc [V]

3.2

3.3

3.4

3.5

3.6

Temperature -40

25

85

105



96

37.1.2 Idle Mode Supply Current

Figure 37-9. Idle Mode Supply Current vs. Frequency f

SYS

= 0 - 1MHz external clock, T = 25



C

150

125

100

75

50

25

0

0.0

0.2

0.4

0.6

Frequency [MHz]

0.8

1.0

V_CC_ 1.600

1.800

2.200

2.700

3.000

3.600

Figure 37-10.Idle Mode Supply Current vs. Frequency f

SYS

= 1 - 32MHz external clock, T = 25



C

4.0

3.5

3.0

2.5

2.0

1.5

1.0

0.5

0.0

0 4 8 12 16

Frequency [MHz]

20 24 28 32

V_CC_

2.7

3

3.6

1.6

1.8

2.2



97

Figure 37-11.Idle Mode Supply Current vs. V

CC f

SYS

= 32.768kHz internal oscillator

32

31

30

27

26

29

28

25

1.6

1.8

2.0

2.2

2.4

2.6

Vcc [V]

2.8

3.0

3.2

3.4

3.6

Temperature -40

25

85

105


CC f

SYS

= 1MHz external clock

55.5

54.0

52.5

51.0

49.5

48.0

46.5

45.0

1.6

1.8

1.700

2.2

2.4

2.6

Vcc [V]

2.8

1.800

3.2

3.4

3.6

Temperature -40

25

85

105



98


CC f

SYS


1.0

0.9

0.8

0.7

0.6

0.5

0.4

0.3

0.2

1.6

1.8

2.0

2.2

2.4

2.6

Vcc [V]

2.8

3.0

3.2

3.4

3.6

Temperature -40

25

85

105


CC f

SYS


1.1

1.0

0.9

0.8

0.7

0.6

0.5

0.4

0.3

1.6

1.8

2.0

2.2

2.4

2.6

Vcc [V]

2.8

3.0

3.2

3.4

3.6

Temperature -40

25

85

105



99


CC f

SYS


1.8

1.6

1.4

1.2

1.0

0.8

0.6

1.6

1.8

2.0

2.2

2.4

2.6

Vcc [V]

2.8

3.0

3.2

3.4

3.6

Temperature -40

25

85

105


CC f

SYS


4.5

4.0

3.5

3.0

2.5

2.6

2.7

2.8

2.9

3.0

3.1

Vcc [V]

3.2

3.3

3.4

3.5

3.6

Temperature -40

25

85

105



100

37.1.3

Power-down Mode Supply Current

Figure 37-17.Power-down Mode Supply Current vs. Temperature

All functions disabled

3.00

2.70

2.40

2.10

1.80

1.50

1.20

0.90

0.60

0.30

0.00

-30 -15 0 15 30 45

Temperature [°C]

60 75 90 105

V_CC_ 1.6

1.8

2.2

2.7

3

3.6

Figure 37-18.Power-down Mode supply Current vs. V

CC

All functions disabled

3.00

2.70

2.40

2.10

1.80

1.50

1.20

0.90

0.60

0.30

0.00

1.6

1.8

2.0

2.2

2.4

2.6

Vcc [V]

2.8

3.0

3.2

3.4

3.6

Temperature -40

25

85

105



101

Figure 37-19.Power-down Mode Supply Current vs. Temperature

Sampled BOD with Watchdog Timer running on ULP oscillator

0.760

0.755

0.750

0.745

0.740

0.735

0.730

0.725

1.6

1.8

2.0

2.2

2.4

2.6

Vcc [V]

2.8

3.0

3.2

3.4

3.6

37.1.4

Power-save Mode Supply Current

Figure 37-20.Power-save Mode Supply Current vs. V

CC

Real Time Counter enabled and running from 1.024kHz output of 32.768kHz TOSC

1.100

1.050

1.000

0.950

0.900

0.850

0.800

1.6

1.8

2.0

2.2

2.4

2.6

Vcc [V]

2.8

3.0

3.2

3.4

3.6



102

37.1.5

Standby Mode Supply Current

Figure 37-21.Standby Supply Current vs. V

CC

Standby, f

SYS

= 1MHz

10

9

8

7

6

5

4

3

2

1

1.6

1.8

2.0

2.2

2.4

2.6

Vcc [V]

2.8

3.0

3.2

3.4

3.6

Temperature -40

25

85

105

Figure 37-22.Standby Supply Current vs. V

CC

25°C, running from different crystal oscillators

500

450

400

350

300

250

200

150

1.6

1.8

2.0

2.2

2.4

2.6

2.8

3.0

Vcc [V]

3.2

3.4

3.6

Crystals 16.0MHz

12.0MHz

8.0MHz

2.0MHz

0.455MHz



103

37.2

I/O Pin Characteristics

37.2.1 Pull-up

Figure 37-23.I/O pin pull-up Resistor Current vs. Input Voltage

V

CC

= 1.8V

10

0

-10

-20

-30

-40

-50

-60

-70

0.0

0.2

0.4

0.6

0.8

1.0

VPIN [V]

1.2

1.4

1.6

1.8

Temperature

Figure 37-24.I/O Pin Pull-up Resistor Current vs. Input Voltage

V

CC

= 3.0V

20

0

-20

-40

-60

-80

-100

-120

0.0

0.3

0.6

0.9

1.2

1.5

VPIN [V]

1.8

2.1

2.4

2.7

3.0

Temperature -40

25

85

105

-40

25

85

105



104

Figure 37-25.I/O Pin Pull-up Resistor Current vs. Input Voltage

V

CC

= 3.3V

0

-50

-100

-150

0.0

0.3

0.6

0.9

1.2

1.5

1.8

VPIN [V]

2.1

2.4

2.7

3.0

3.3

Temperature -40

25

85

105

37.2.2 Output Voltage vs. Sink/Source Current

Figure 37-26.I/O Pin Output Voltage vs. Source Current

V

CC

= 1.8V

1.80

1.75

1.70

1.65

1.60

1.55

-2.0

-1.8

-1.6

-1.4

-1.2

-1.0

IPIN [mA]

-0.8

-0.6

-0.4

-0.2

0.0

Temperature 25

85

105

-40



105


V

CC

= 3.0V

3.0

2.9

2.8

2.7

2.6

2.5

2.4

2.3

-10 -9 -8 -7 -6 -5

IPIN [mA]

-4 -3 -2 -1 0

Temperature 25

85

105

-40


V

CC

= 3.3V

3.3

3.2

3.1

3.0

2.9

2.8

2.7

2.6

-10 -9 -8 -7 -6 -5

IPIN [mA]

-4 -3 -2 -1 0

Temperature 25

85

105

-40



106

4.0

3.5

3.0

2.5

2.0

1.5

1.0

0.5

-18 -15 -12 -9

IPIN [mA]

-6 -3 0

V_CC_

3

3.3

3.6

1.6

1.8

2.7

Figure 37-30.I/O Pin Output Voltage vs. Sink Current

V

CC

= 1.8V

0.30

0.25

0.20

0.15

0.10

0.05

0.00

0.0

0.5

1.0

1.5

2.0

2.5

IPIN [mA]

3.0

3.5

4.0

4.5

5.0

Temperature 25

85

105

-40



107


V

CC

= 3.0V

0.7

0.6

0.5

0.4

0.3

0.2

0.1

0.0

0 2 4 6 8 10

IPIN [mA]

12 14 16 18 20

Temperature 25

85

105

-40


V

CC

= 3.3V

0.7

0.6

0.5

0.4

0.3

0.2

0.1

0.0

0 2 4 6 8 10

IPIN [mA]

12 14 16 18 20

Temperature 25

85

105

-40



108


1.60

1.40

1.20

1.00

0.80

0.60

0.40

0.20

0.00

0 2 4 6 8 10

IPIN [mA]

12 14 16 18 20

V_CC_

3

3.3

3.6

1.6

1.8

2.7

37.2.3

Thresholds and Hysteresis

Figure 37-34.I/O Pin Input Threshold Voltage vs. V

CC

T = 25°C

1.65

1.50

1.35

1.20

1.05

0.90

0.75

1.6

1.8

2.0

2.2

2.4

2.6

Vcc [V]

2.8

3.0

3.2

3.4

3.6

Test Info VIH

VIL



109


CC

V

IH

I/O pin read as “1”

1.80

1.60

1.40

1.20

1.00

0.80

0.60

1.6

1.8

2.0

2.2

2.4

2.6

Vcc [V]

2.8

3.0

3.2

3.4

3.6

Temperature -40

25

85

105


CC

V

IL

I/O pin read as “0”

1.80

1.60

1.40

1.20

1.00

0.80

0.60

1.6

1.8

2.0

2.2

2.4

2.6

Vcc [V]

2.8

3.0

3.2

3.4

3.6

Temperature -40

25

85

105



110

Figure 37-37.I/O Pin Input Hysteresis vs. V

CC

0.09

0.08

0.07

0.06

0.05

0.04

0.03

0.02

1.6

1.8

2.0

2.2

2.4

2.6

Vcc [V]

2.8

3.0

3.2

3.4

3.6

Temperature -40

25

85

105

37.3

ADC Characteristics

Figure 37-38.ADC INL vs. V

REF

T = 25



C, V

CC

= 3.6V, external reference

1.75

1.50

1.25

1.00

0.75

0.50

0.25

1.0

1.2

1.4

1.6

1.8

2.0

Vref [V]

2.2

2.4

2.6

2.8

3.0

Mode Single-ended unsigned mode

Single-ended signed mode

Differential mode



111

Figure 37-39.ADC INL Error vs. V

CC

T = 25



C, V

REF

= 1.0V

1.80

1.60

1.40

1.20

1.00

0.80

0.60

1.6

1.8

2.0

2.2

2.4

2.6

Vcc [V]

2.8

3.0

3.2

3.4

3.6



Differential mode

Figure 37-40.ADC DNL Error vs. V

SE Unsigned mode, T=25

REF



C, V

CC

= 3.6V, external reference

0.75

0.70

0.65

0.60

0.55

0.50

0.45

1.0

1.2

1.4

1.6

1.8

2.0

Vref [V]

2.2

2.4

2.6

2.8

3.0



112

Figure 37-41. ADC Gain Error vs. V

CC

T = 25



C, V

REF

= 1.0V, ADC sample rate = 300ksps

0.0

-1.0

-2.0

-3.0

-4.0

-5.0

1.6

1.8

2.0

2.2

2.4

2.6

Vcc [V]

2.8

3.0

3.2

3.4

3.6

Mode Single-ended signed mode

Differential mode

Single-ended unsigned mode

Figure 37-42. ADC Gain Error vs. V

REF

T = 25



C, V

CC


-6.0

-8.0

-10.0

0.0

-2.0

-4.0

-12.0

-14.0

1.0

1.2

1.4

1.6

1.8

2.0

Vref [V]

2.2

2.4

2.6

2.8

3.0


Differential mode




113

Figure 37-43. ADC Gain Error vs. Temperature

V

CC

= 3.6V, V

REF


0.0

-1.0

-2.0

-3.0

-4.0

-5.0

-6.0

-7.0

-40 -20 0 20 40

Temperature [°C]

60 80 100


Differential mode


Figure 37-44. ADC Offset Error vs. V

CC

T = 25



C, V

REF


25.0

20.0

15.0

10.0

5.0

0.0

1.6

1.8

2.0

2.2

2.4

2.6

Vcc [V]

2.8

3.0

3.2

3.4

3.6



Differential mode



114

Figure 37-45. ADC Offset Error vs. V

REF

T = 25



C, V

CC


30.0

25.0

20.0

15.0

10.0

5.0

1.0

1.2

1.4

1.6

1.8

2.0

Vref [V]

2.2

2.4

2.6

2.8

3.0



Differential mode

Figure 37-46.ADC Gain Error vs. Temperature

V

CC

= 3.6V, V

REF

= external 1.0V, sample rate = 300ksps

0.0

-1.0

-2.0

-3.0

-4.0

-5.0

-6.0

-7.0

-40 -20 0 20 40

Temperature [°C]

60 80 100


Differential mode




115

37.4

DAC Characteristics

Figure 37-47.DAC INL Error vs. External V

REF

T = 25



C, V

CC

= 3.6V

1.9

1.8

1.7

1.6

1.5

1.4

2.2

2.1

2

1.3

1.0

1.2

1.4

1.6

1.8

2.0

Vref [V]

2.2

2.4

2.6

2.8

3.0

Figure 37-48.DNL Error vs. V

REF

T = 25



C, V

CC

= 3.6V

0.75

0.70

0.65

0.60

0.55

0.50

0.45

0.40

0.35

1.0

1.2

1.4

1.6

1.8

2.0

Vref [V]

2.2

2.4

2.6

2.8

3.0



Differential mode



116

Figure 37-49.DNL Error vs. V

CC

T = 25



C, V

REF

= 1.0V

0.80

0.70

0.60

0.50

0.40

0.30

1.6

1.8

2.0

2.2

2.4

2.6

Vcc [V]

2.8

3.0

3.2

3.4

3.6



Differential mode

37.5

AC Characteristics

Figure 37-50.Analog Comparator Hysteresis vs. V

CC

Small hysteresis

16

14

12

10

8

6

4

1.6

1.8

2.0

2.2

2.4

2.6

2.8

3.0

Vcc [V]

3.2

3.4

3.6

Temperature (°C) 85

25

-40



117

Figure 37-51.Analog Comparator Hysteresis vs. V

CC

Large hysteresis

34

32

30

28

26

24

22

20

18

16

14

1.6

1.8

2.0

2.2

2.4

2.6

2.8

3.0

Vcc [V]

3.2

3.4

3.6

Temperature (°C) 85

25

-40

Figure 37-52.Analog Comparator Propagation Delay vs. V

CC

26

24

22

20

18

16

14

12

10

1.6

1.8

2 2.2

2.4

2.6

2.8

3 3.2

3.4

3.6

Temperature (°C)

Vcc [V]

85

25

-40



118

Figure 37-53.Analog Comparator Propagation Delay vs. Temperature

26

24

22

20

18

16

14

12

10

-40 -30 -20 -10 0 10 20 30 40 50 60 70 80 90

Vcc (V)

Temperature [°C]

1.6

2

2.7

3

3.3

3.6

Figure 37-54.Analog Comparator Current Consumption vs. V

CC

240

230

220

210

200

190

180

170

160

150

1.6

1.8

2.0

2.2

2.4

2.6

Vcc [V]

2.8

3.0

3.2

3.4

3.6

Temperature -40

25

85

105



119

Figure 37-55.Analog Comparator Voltage Scaler vs. SCALEFAC

T = 25



C, V

CC

= 3.0V

0.050

0.025

0

-0.025

-0.050

-0.075

-0.100

-0.125

-0.150

0 10 20 30

SCALEFAC

40 50 60

25°C

70

Figure 37-56.Analog Comparator Offset Voltage vs. Common Mode Voltage

35

Temperature (°C)

30

25

20

15

10

5

0

0 0.4

0.8

1.2

1.6

2 2.4

2.8

3.2

3.6

Vcm [V]

-40

25

85



120

Figure 37-57.Analog Comparator Source vs. Calibration Value

V

CC

= 3.0V

7.0

6.5

6.0

5.5

5.0

4.5

4.0

3.5

0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15

Temperature (°C)

CALIB [3..0]

Figure 37-58.Analog Comparator Source vs. Calibration Value

T = 25



C

8.0

7.0

6.0

5.0

4.0

3.0

2.0

0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15

Vcc [V]

CALIB [3..0]

3.6

3

2.2

1.8

-40

25

85



121

37.6

Internal 1.0V Reference Characteristics

Figure 37-59.ADC/DAC Internal 1.0V Reference vs. Temperature

1.015

1.010

1.005

1.000

0.995

0.990

0.985

0.980

-40 -30 -20 -10 0 10 20 30 40 50 60 70 80 90 100 110

Temperature [°C]

Vcc

2.7

3

3.3

3.6

1.6

1.8

2.2

37.7

BOD Characteristics

Figure 37-60.BOD Thresholds vs. Temperature

BOD level = 1.6V

1.70

1.69

1.68

1.67

1.66

1.65

1.64

1.63

1.62

1.61

-30 -15 0 15 30 45

Temperature [°C]

60 75 90 105

Test Info fall

rise



122

Figure 37-61.BOD Thresholds vs. Temperature

BOD level = 3.0V

3.10

3.05

3.00

2.95

-30 -15 0 15 30 45

Temperature [°C]

60 75 90 105

Test Info fall

rise

37.8

External Reset Characteristics

Figure 37-62.Minimum Reset Pin Pulse Width vs. V

CC

140

130

120

110

100

90

80

1.6

1.8

2.0

2.2

2.4

2.6

Vcc [V]

2.8

3.0

3.2

3.4

3.6

T [°C] -40

25

85

105



123

Figure 37-63.Reset Pin Pull-up Resistor Current vs. Reset Pin Voltage

V

CC

= 1.8V

10

0

-10

-20

-30

-40

-50

-60

-70

-80

0.0

0.2

0.4

0.6

0.8

1.0

VRESET [V]

1.2

1.4

1.6

1.8

Temperature -40

25

85

105


V

CC

= 3.0V

25

0

-25

-50

-75

-100

-125

0.0

0.3

0.6

0.9

1.2

1.5

VRESET [V]

1.8

2.1

2.4

2.7

3.0

Temperature -40

25

85

105



124


V

CC

= 3.3V

0

-75

-100

-25

-50

-125

-150

0.0

0.3

0.6

0.9

1.2

1.5

1.8

VRESET [V]

2.1

2.4

2.7

3.0

3.3

Temperature -40

25

85

105

Figure 37-66.Reset Pin Input Threshold Voltage vs. V

CC

V

IH

- Reset pin read as “1”

,

1.8

1.7

1.6

1.5

1.4

1.3

2.1

2.0

1.9

1.2

1.1

1.0

1.6

1.8

2.0

2.2

2.4

2.6

Vcc [V]

2.8

3.0

3.2

3.4

3.6

T [°C] -40

25

85

105



125

Figure 37-67.Reset Pin Input Threshold Voltage vs. V

CC

V

IL

- Reset pin read as “0”

1.7

1.6

1.5

1.4

1.3

1.2

1.1

1.0

0.9

0.8

0.7

0.6

0.5

1.6

1.8

2.0

2.2

2.4

2.6

Vcc [V]

2.8

3.0

3.2

3.4

3.6

T [°C] -40

25

85

105

37.9

Power-on Reset Characteristics

Figure 37-68.Power-on Reset Current Consumption vs. V

CC

BOD level = 3.0V, enabled in continuous mode

700

600

500

400

300

200

100

0

0.0

0.4

0.8

1.2

V_CC_ [V]

1.6

2.0

2.4

2.8

T [°C] -40

25

85

105



126

Figure 37-69.Power-on Reset Current Consumption vs. V

CC

BOD level = 3.0V, enabled in sampled mode

650

585

520

455

390

325

260

195

130

65

0

0.0

0.4

0.8

1.2

V_CC_ [V]

1.6

2.0

2.4

2.8

T [°C] -40

25

85

105



127

37.10 Oscillator Characteristics

37.10.1 Ultra Low-Power Internal Oscillator

Figure 37-70. Ultra Low-Power Internal Oscillator Frequency vs. Temperature

V_CC_

37

36

35

34

33

32

31

30

29

28

-45 -30 -15 0 15 30 45

Temperature [°C]

60 75 90 105

2.7

3

3.6

1.6

1.8

2.2

37.10.2 32.768KHz Internal Oscillator

Figure 37-71. 32.768kHz Internal Oscillator Frequency vs. Temperature

33.00

32.90

32.80

32.70

32.60

-45 -30 -15 0 15 30 45

Temperature [°C]

60 75 90 105

V_CC_

2.7

3

3.6

1.6

1.8

2.2



128

Figure 37-72. 32.768kHz Internal Oscillator Frequency vs. Calibration Value

V

CC

= 3.0V

50.00

Temperature

45.00

40.00

35.00

30.00

25.00

20.00

0 24 48 72 96 120 144

CAL

168 192 216 240 264

-40

25

85

105

Figure 37-73. 32.768kHz Internal Oscillator Calibration Step Size

V

CC

= 3.0V, T = 25°C to 105°C

1.00

0.00

-1.00

-2.00

-3.00

-4.00

-5.00

0 32 64 96 128

CAL

160 192 224 256

Temperature -40

25

85

105



129

37.10.3 8MHz Internal Oscillator

Figure 37-74. 8MHz Internal Oscillator Frequency vs. Temperature

Normal mode

8.160

8.140

8.120

8.100

8.080

8.060

8.040

8.020

8.000

7.980

7.960

-45 -30 -15 0 15 30 45

Temperature [°C]

60 75 90 105

V_CC_[V] 1.6

1.8

2.2

2.7

3

3.6


Low power mode

8.160

8.140

8.120

8.100

8.080

8.060

8.040

8.020

8.000

7.980

-45 -30 -15 0 15 30 45

Temperature [°C]

60 75 90 105

V_CC_

2.7

3

3.6

1.6

1.8

2.2



130

Figure 37-76. 8MHz Internal Oscillator CAL Calibration Step Size

V

CC

= 3.0V

1.50

1.25

1.00

0.75

0.50

0.25

0.00

0 32 64 96 128

CAL

160 192 224 256

Temperature -40

25

85

105

Figure 37-77. 8MHz Internal Oscillator Frequency vs. Calibration

V

CC

= 3.0V, normal mode

16.000

14.000

12.000

10.000

8.000

6.000

4.000

2.000

0 32 64 96 128

CAL

160 192 224 256

Temperature -40

25

85

105



131

37.10.4 32MHz Internal Oscillator


DFLL disabled

34.00

33.50

33.00

32.50

32.00

31.50

31.00

30.50

30.00

-40 -30 -20 -10 0 10 20 30 40 50 60 70 80 90 100 110

Temperature [°C]

V_CC_[V] 1.6

1.8

2.2

2.7

3

3.6


DFLL enabled, from the 32.768kHz internal oscillator

32.10

32.08

32.06

32.04

32.02

32.00

31.98

31.96

31.94

31.92

31.90

31.88

-45 -30 -15 0 15 30 45

Temperature [°C]

60 75 90 105

V_CC_ [V] 1.6

1.8

2.2

2.7

3

3.6



132

Figure 37-80. 32MHz Internal Oscillator CALA Calibration Step Size

V

CC

= 3.0V

0.25

0.24

0.23

0.18

0.17

0.16

0.15

0.22

0.21

0.20

0.19

0 16 32 48 64

CALA

80 96 112 128

Temperature -40

25

85

105

Figure 37-81. 32MHz Internal Oscillator Frequency vs. CALA Calibration Value

V

CC

= 3.0V

54

Temperature

48

46

44

42

52

50

40

38

0 16 32 48 64

CALA

80 96 112 128

-40

25

85

105



133

Figure 37-82. 32MHz internal Oscillator Frequency vs. CALB Calibration Value

V

CC

= 3.0V

70.00

Temperature

60.00

50.00

40.00

30.00

20.00

0 8 16 24 32

CALB

40 48 56 64

-40

25

85

105

37.11 Two-wire Interface Characteristics

Figure 37-83. SDA Fall Time vs. Temperature

80

70

60

50

40

30

20

10

-40 -20 0 20 40 60

Temperature [°C]

80 100 120

Mode STD

FAST

FAST +



134

Figure 37-84. SDA Fall Time vs. V

CC

70

60

50

40

30

20

10

1.6

1.8

2 2.2

2.4

2.6

Vcc [V]

2.8

3 3.2

3.4

3.6

Mode STD

FAST

FAST +

37.12 PDI Characteristics

Figure 37-85. Maximum PDI Frequency vs. V

CC

18

15

12

24

21

9

6

1.6

1.8

2.0

2.2

2.4

2.6

Vcc [V]

2.8

3.0

3.2

3.4

3.6

T [°C] -40

25

85

105



135

38.

Errata – ATxmega32E5 / ATxmega16E5 / ATxmega8E5

38.1

Rev. B

















DAC: AREF on PD0 is not available for the DAC

ADC: Offset correction fails in unsigned mode

EEPROM write and Flash write operations fails under 2.0V

TWI Master or slave remembering data

TWI SM bus level one Master or slave remembering data

Temperature Sensor not calibrated

Automatic port override on PORT C

Sext timer is not implemented in slave mode

Issue: DAC: AREF on PD0 is not available for the DAC

The AREF external reference input on pin PD0 is not available for the DAC.

Workaround:

No workaround. Only AREF on pin PA0 can be used as external reference input for the DAC.

Issue: ADC: Offset correction fails in unsigned mode

In single ended, unsigned mode, a problem appears in low saturation (zero) when the offset correction is activated. The offset is removed from result and when a negative result appears, the result is not correct.

Workaround:

No workaround, but avoid using this correction method to cancel V effect.

Issue: EEPROM write and Flash write operations fails under 2.0V

EEPROM write and Flash write operations are limited from 2.0V to 3.6V. Other functionalities operates from 1.6V to 3.6V.

Workaround:

None.

Issue: TWI master or slave remembering data

If a write is made to Data register, prior to Address register, the TWI design sends the data as soon as the write to

Address register is made. But the send data will be always 0x00.

Workaround:

None.



136

Issue: TWI SM bus level one Master or slave remembering data



Workaround:

Since single interrupt line is shared by both timeout interrupt and other TWI interrupt sources, there is a possibility in software that data register will be written after timeout is detected but before timeout interrupt routine is executed. To avoid this, in software, before writing data register, always ensure that timeout status flag is not set.

Issue: Temperature sensor not calibrated

Temperature sensor factory calibration is not implemented on devices before date code 1324.

Workaround:

None.

Issue: Automatic port override on PORT C

When Waveform generation is enabled on PORT C Timers, Automatic port override of peripherals other than Tc may not work even though the pin is not used as waveform output pin.

Workaround:

No workaround.

Issue: Sext timer is not implemented in slave mode

In slave mode, only Ttout timer is implemented.

Sext timer is needed in slave mode to release the SCL line and to allow the master to send a STOP condition. If only master implements Sext timer, slave continues to stretch the SCL line (up to the Ttout timeout in the worse case).

Sext = Slave cumulative timeout.

Workaround:

No workaround.



137

38.2

Rev. A





























DAC: AREF on PD0 is not available for the DAC

EDMA: Channel transfer never stops when double buffering is enabled on sub-sequent channels

ADC: Offset correction fails in unsigned mode

ADC: Averaging is failing when channel scan is enabled

ADC: Averaging in single conversion requires multiple conversion triggers

ADC accumulator sign extends the result in unsigned mode averaging

ADC: Free running average mode issue

ADC: Event triggered conversion in averaging mode

AC: Flag can not be cleared if the module is not enabled

USART: Receiver not functional when variable data length and start frame detector are enabled

T/C: Counter does not start when CLKSEL is written

EEPROM write and Flash write operations fails under 2.0V

TWI master or slave remembering data

Temperature Sensor not calibrated

Issue: DAC: AREF on PD0 is not available for the DAC

The AREF external reference input on pin PD0 is not available for the DAC.

Workaround:

No workaround. Only AREF on pin PA0 can be used as external reference input for the DAC.

Issue: EDMA: Channel transfer never stops when double buffering is enabled on sub-sequent channels

When the double buffering is enabled on two channels, the channels which are not set in double buffering mode are never disabled at the end of the transfer. A new transfer can start if the channel is not disabled by software.

Workaround:



CHMODE = 00



Enable double buffering on all channels or do not use channels which are not set the double buffering mode.

CHMODE = 01 or 10

Do not use the channel which is not supporting the double buffering mode.

Issue: ADC: Offset correction fails in unsigned mode

In single ended, unsigned mode, a problem appears in low saturation (zero) when the offset correction is activated. The offset is removed from result and when a negative result appears, the result is not correct.

Workaround:

No workaround, but avoid using this correction method to cancel V effect.



138

Issue: ADC: Averaging is failing when channel scan is enabled

For a correct operation, the averaging must complete on the on-going channel before incrementing the input offset. In the current implementation, the input offset is incremented after the ADC sampling is done.

Workaround:

None.

Issue: ADC: Averaging in single conversion requires multiple conversion triggers

For a normal operation, an unique start of conversion trigger starts a complete average operation. Then, for Nsamples average operation, we should have:







One start of conversion

N conversions + average

Optional interrupt when the Nth conversion/last average is completed

On silicon we need:



N start of conversion

The two additional steps are well done.

Workaround:



Set averaging configuration





N starts of conversion by polling the reset of START bit

Wait for interrupt flag (end of averaging)

Issue: ADC accumulator sign extends the result in unsigned mode averaging

In unsigned mode averaging, when the msb is going high(1), measurements are considered as negative when right shift is used. This sets the unused most significant bits once the shift is done.

Workaround:

Mask to zero the unused most significant bits once shift is done.

Issue: ADC: Free running average mode issue

In free running mode the ADC stops the ongoing averaging as soon as free running bit is disabled. This creates the need to flush the ADC before starting the next conversion since one or two conversions might have taken place in the internal accumulator.

Workaround:

Disable and re-enable the ADC before the start of next conversion in free running average mode.

Issue: ADC: Event triggered conversion in averaging mode

If the ADC is configured as event triggered in averaging mode, then a single event does not complete the entire averaging as it should be.

Workaround:

In the current revision, N events are needed for completing averaging on N samples.



139

Issue: AC: Flag can not be cleared if the module is not enabled

It is not possible to clear the AC interrupt flags without enabling either of the analog comparators.

Workaround:

Clear the interrupt flags before disabling the module.

Issue: USART: Receiver not functional when variable data length and start frame detector are enabled

When using USART in variable frame length with XCL PEC01 configuration and start frame detection activated, the USART receiver is not functional.

Workaround:

Use XCL BTC0PCE2 configuration instead of PEC01.

Issue: T/C: Counter does not start when CLKSEL is written

When STOP bit is cleared (CTRLGCLR.STOP) before the timer/counter is enabled (CTRLA.CLKSEL != OFF), the

T/C doesn't start operation.

Workaround:

Do not write CTRLGCLR.STOP bit before writing CTRLA.CLKSEL bits.

Issue: EEPROM write and Flash write operations fails under 2.0V

EEPROM write and Flash write operations are limited from 2.0V to 3.6V. Other functionalities operates from 1.6V to 3.6V.

Workaround:

None.

Issue: TWI master or slave remembering data



Workaround:

None.

Issue: Temperature sensor not calibrated

Temperature sensor factory calibration is not implemented.

Workaround:

None.



140

39.

Revision History

Please note that referring page numbers in this section are referred to this document. The referring revision in this document section are referring to the document revision.

39.1

8153J – 11/2014

1.

2.

Changed error for ESR parameter in Table 36-27 on page 86 .

Changed the use of capital letters in heading, figure titles, and table headings.

39.2

8153I – 08/2014

1.

2.

3.

4.

Removed preliminary from the front page.

Updated with ESR info in Table 36-27 on page 86

.

Added errata on Automatic port override on PORT C in Section 38. “Errata – ATxmega32E5 / ATxmega16E5 /

ATxmega8E5” on page 136 .

Added errata on Sext timer not implemented in slave mode in

Section 38. “Errata – ATxmega32E5 /

ATxmega16E5 / ATxmega8E5” on page 136 .

39.3

8153H – 07/2014

4.

5.

1.

2.

3.

“Ordering Information” on page 2 : Added ordering codes for XMEGA E5 devices @105

C.

Electrical characteristics updates:

“Current Consumption” : Added power-down numbers for 105°C and updated values in Table 36-3 on page 73

.

“ Flash and EEPROM Characteristics”

: Added Flash and EEPROM write/erase cycles and data retention for

105°C in Table 36-18 on page 82

.

Changed Vcc to AVcc in

Section 28. “ADC – 12-bit Analog to Digital Converter” on page 51

and in Section 30.1

“Features” on page 54

.

32.768 KHz changed to 32 kHz in the heading in

Section 36.13.4 on page 84 and in Table 36-23 on page 84 .

Changed back page according to datasheet template 2014-0502.

39.4

8153G – 10/2013

1.

Updated wake-up time from power-save mode for 32MHz internal oscillator from 0.2µs to 5.0µs in

Table 36-5 on page 75

.

39.5

8153F – 08/2013

1.

TWI characteristics: Units of Data setup time (t

SU;DAT

) changed from µs to ns in Table 36-30 on page 91

.

39.6

8153E – 06/2013

1.

Errata “Rev. B” : Updated date code from 1318 to 1324 in

“Temperature sensor not calibrated” on page 137 .



141

39.7

8153D – 06/2013

1.

Analog Comparator Characteristics: Updated minimum and maximum values of Input Voltage Range, Table 36-14 on page 80 .

39.8

8153C – 05/2013

1.

2.

Electrical Characteristics,

Table on page 73

: Updated typical value from 7mA to 6mA for Active Current

Consumption, 32MHz, V

CC

=3.0V.

Errata

“Rev. A”

and “Rev. B”

: Added DAC errata: AREF on PORT C0.

39.9

8153B – 04/2013

1.

“Rev. B” on page 136

: Removed the “EDMA: Channel transfer never stops when double buffering is enabled on sub-sequent channels” errata.

39.10 8153A – 04/2013

1.

Initial revision.



142

Table of Contents

Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

1.

Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2

2.

Typical Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3

3.

Pinout and Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4

4.

Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

5.

Resources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

5.1

Recommended Reading . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

6.

Capacitive Touch Sensing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

7.

CPU . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

7.1

Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

7.2

Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

7.3

Architectural Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

7.4

ALU - Arithmetic Logic Unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

7.5

Program Flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

7.6

Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

7.7

Stack and Stack Pointer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

7.8

Register File . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

8.

Memories . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

8.1

Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

8.2

Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

8.3

Flash Program Memory. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

8.4

Fuses and Lock Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

8.5

Data Memory. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

8.6

EEPROM. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

8.7

I/O Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

8.8

Data Memory and Bus Arbitration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

8.9

Memory Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

8.10

Device ID and Revision . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

8.11

I/O Memory Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

8.12

Flash and EEPROM Page Size. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

9.

EDMA – Enhanced DMA Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

9.1

Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

9.2

Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

10. Event System . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

10.1

Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

10.2

Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

11. System Clock and Clock options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

11.1

Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

11.2

Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

11.3

Clock Sources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21


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12. Power Management and Sleep Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

12.1

Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

12.2

Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

12.3

Sleep Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

13. System Control and Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

13.1

Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

13.2

Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

13.3

Reset Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

13.4

Reset Sources. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

14. WDT – Watchdog Timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

14.1

Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

14.2

Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

15. Interrupts and Programmable Multilevel Interrupt Controller . . . . . . . . . . . . . . . . 28

15.1

Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

15.2

Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

15.3

Interrupt Vectors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

16. I/O Ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

16.1

Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

16.2

Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

16.3

Output Driver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

16.4

Input Sensing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

16.5

Alternate Port Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

17. Timer Counter Type 4 and 5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

17.1

Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

17.2

Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

18. WeX – Waveform Extension . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36

18.1

Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36

18.2

Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36

19. Hi-Res – High Resolution Extension . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38

19.1

Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38

19.2

Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38

20. Fault Extension . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39

20.1

Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39

20.2

Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39

21. RTC – 16-bit Real-Time Counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40

21.1

Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40

21.2

Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40

22. TWI – Two-Wire Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42

22.1

Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42

22.2

Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42

23. SPI – Serial Peripheral Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44

23.1

Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44


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23.2

Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44

24. USART . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45

24.1

Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45

24.2

Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45

25. IRCOM – IR Communication Module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47

25.1

Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47

25.2

Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47

26. XCL – XMEGA Custom Logic Module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48

26.1

Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48

26.2

Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48

27. CRC – Cyclic Redundancy Check Generator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50

27.1

Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50

27.2

Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50

28. ADC – 12-bit Analog to Digital Converter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51

28.1

Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51

28.2

Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51

29. DAC – Digital to Analog Converter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53

29.1

Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53

29.2

Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53

30. AC – Analog Comparator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54

30.1

Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54

30.2

Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54

31. Programming and Debugging . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56

31.1

Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56

31.2

Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56

32. Pinout and Pin Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57

32.1

Alternate Pin Function Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57

32.2

Alternate Pin Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59

33. Peripheral Module Address Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61

34. Instruction Set Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63

35. Packaging Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68

35.1

32A . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68

35.2

32Z . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69

35.3

32MA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70

36. Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71

36.1

Absolute Maximum Ratings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71

36.2

General Operating Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71

36.3

Current Consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73

36.4

Wake-up Time from Sleep Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75

36.5

I/O Pin Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76

36.6

ADC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76


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36.7

DAC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79

36.8

Analog Comparator Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80

36.9

Bandgap and Internal 1.0V Reference Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81

36.10 External Reset Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82

36.11 Power-on Reset Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82

36.12 Flash and EEPROM Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82

36.13 Clock and Oscillator Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84

36.14 SPI Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89

36.15 Two-Wire Interface Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91

37. Typical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93

37.1

Current Consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93

37.2

I/O Pin Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104

37.3

ADC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111

37.4

DAC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116

37.5

AC Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117

37.6

Internal 1.0V Reference Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122

37.7

BOD Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122

37.8

External Reset Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123

37.9

Power-on Reset Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126

37.10 Oscillator Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128

37.11 Two-wire Interface Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134

37.12 PDI Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135

38. Errata – ATxmega32E5 / ATxmega16E5 / ATxmega8E5 . . . . . . . . . . . . . . . . . . . . 136

38.1

Rev. B . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136

38.2

Rev. A . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138

39. Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 141

39.1

8153J – 11/2014 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 141

39.2

8153I – 08/2014 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 141

39.3

8153H – 07/2014. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 141

39.4

8153G – 10/2013. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 141

39.5

8153F – 08/2013 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 141

39.6

8153E – 06/2013 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 141

39.7

8153D – 06/2013. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142

39.8

8153C – 05/2013. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142

39.9

8153B – 04/2013 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142

39.10 8153A – 04/2013 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142

Table of Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . i


Atmel-8153J–AVR-ATxmega8E5-ATxmega16E5-ATxmega32E5_Datasheet–11/2014 iv

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