POWER MANAGEMENT SYSTEM DEVICE
POWER MANAGEMENT SYSTEM DEVICE
RC5T7315
Product Brief
Rev. 1.0
November 15, 2012
RICOH COMPANY, LTD.
Electronic Devices Company
This specification is subject to change without notice.
©2012
Rev. 1.0
Page1
POWER MANAGEMENT SYSTEM DEVICE
Table of Contents
1.
Outline ........................................................................................................................................................................3
2.
Feature .......................................................................................................................................................................3
3.
Block Diagram...........................................................................................................................................................4
4.
Electrical Characteristics .........................................................................................................................................5
5.
4.1
Absolute Maximum Ratings ............................................................................................................................5
4.2
Recommendation of Operating Conditions ..................................................................................................5
Pin Configuration ......................................................................................................................................................6
5.1
Pin Configuration..............................................................................................................................................6
6.
Pin Description ..........................................................................................................................................................7
7.
Power Control..........................................................................................................................................................11
8.
7.1
Power Mode Control Transition Diagram....................................................................................................11
7.2
Block Diagram.................................................................................................................................................12
Regulator .................................................................................................................................................................13
8.1
9.
Regulators & DCDC Table............................................................................................................................13
GPIO.........................................................................................................................................................................14
9.1
Block Diagram.................................................................................................................................................14
10. INTC .........................................................................................................................................................................15
10.1
Block Diagram.................................................................................................................................................15
11. ADC ..........................................................................................................................................................................16
11.1
Block Diagram.................................................................................................................................................16
12. Li-ion Battery Charger............................................................................................................................................17
12.1
Li-ion Battery Charger Block Diagram.........................................................................................................18
©2012
Rev. 1.0
Page2
POWER MANAGEMENT SYSTEM DEVICE
1. Outline
RC5T7315 is the Power management LSI that integrates Regulators, Battery Charger, and RTC in one chip.
2. Feature
■ Power Supplies
ƒ 13 Linear Regulators
ƒ Five Voltage Detectors (DET1, DETIO, DET2, UVLO, and SHDET)
ƒ Reference Voltage Source
ƒ 3ch Step-down DCDC Converters
■
Serial Interface
The interface circuit with CPU consists of 16-bit serial register (8-bit command and 8-bit address), the
address decoder, and the transmitting register (8 bits).
■
GPIO
THIS BLOCK IS COMPOSED OF 14 I/O PINS WITH PULL-UP/DOWN CONTROL FUNCTION.
THE INPUT SIGNALS TO GPIO PINS ARE OUTPUT TO INTC BLOCK, AND THEY BECOME ONE OF THE
■
INTERRUPT GENERATION FACTORS.
INTC Interrupt Controller (INTC)
INTC block detects the state change of external input signals (GPIO 14 bits) and the internal interrupt
signals, and then it generates interrupt signals.
■
10bit ADC
10bit ADC has 8-channel input ports with a multiplexer.
■
Battery Charger
-There are two external power supply input pins; VCHG1 and VCH2.
-When both VCHG1 and VCHG2 pins have a proper input of voltage range;
the priority is given to VCHG1 pin input. Proper voltage range: 4.0V < VVCHG 1(VCHG2) < 6.3V
-The efficient power supply to the system and battery is performed by the current limit protection and the
charge current control.
-Various timers for the charge control are integrated.
-Chip temperature detection circuit is integrated, and it prevents the chip overheating due to the charge.
-Thermistor temperature monitoring circuit is integrated, and it stops charging at the detection of error
temperature while charging. Also, the temperature can be monitored by the integrated ADC.
-LED connection pin is equipped; the external LED can be turned on。
-Maximum allowable current from VBAT pin to VSYS pin: 1.6A.
-VCHG1 and VCHG2 pin: 7V withstand (absolute maximum ratings)
■
Reset Control
The Reset Control circuit generates the RESETB signal by the 7 factors.
■
Real Time Clock
- The time and calendar data are transferred to CPU through serial transfer.
- Integrates the periodic interrupt circuit with alarm function
(RTC interrupt request can be output to INTOUT pin through INTC block).
- All the registers of integrated RTC have their own backup in BKBAT (REGRTC: always ON).
■
Package
CSP0606-120 (0.5mm pitch, PKG thickness = 1mm@MAX)
■
Process
CMOS 0.18μm
©2012
Rev. 1.0
Page3
POWER MANAGEMENT SYSTEM DEVICE
3. Block Diagram
ExternalPower2
RC5T7315
VSYS Input
Battery
VCHG11
VCHG12
VCHG13
Note(*1): PSM = Power Save Mode
For TEST
Notes(*2): DCDC2V or VSYS
Notes(*3): External Power2 or VSYS
VCHG21
VCHG22
VCHG23
VSYS1
VSYS2
VSYS3
VSYS4
DET1
DCDCL1
(0.75V 1.375
V/1400mA)
ON/OFF
Charger
Charger Logic
(1.8V)
DETIO
Interrupt Control
Circuit(1.8V)
ECOREG
DCDCIO
(1.8V/1200mA)
DCDC/ECOREG
MODE
CHGGND
DETVBUS
DCDC2V
(2.0V/1.8V/
350mA)
VSYS
Digital Delay
L0DET
REGPLL
(1.025V-1.2V/20mA)
VPLLIN
VPLL
REGANA
(2.8V/150mA)
VANAIN
VANA
ON/OFF
REG1
(1.8V/100mA)
VREG1
ON/OFF
REG2
(1.8V/100mA)
ON/OFF
REG3
(1.8V/150mA)
ON/OFF
ADC
ON/OFF
PSM(*1)
/Normal
REGUSB
(3.3V/115mA)
VUSB
INTOSC
(32kHz)
ON/OFF
VANAIN
UVLO
REGINTD18
(1.8V/10mA)
PSM(*1)
/Normal
ON/OFF
ON/OFF
PSM(*1)
/Normal
Power for Internal Logic
VGP12IN
VGP1
REGGP2
(2.85V/150mA)
PSM(*1)
/Normal
ON/OFF
ON/OFF
REGGP3
(2.85V/200mA)
VGP2
VGP3IN
VGP3
REGGP4
(2.85V/100mA)
VGP4IN
VGP4
REGLOG
(1.8V/50mA)
VLOGIN
VLOG
GND1
GND2
Internal Logic(1.8V)
VREF
DGND1,2
IOVDD2
IOVDD
(*2)
VREG12IN
VREG2
VREG3IN
VREG3
REGGP1
(2.85V/150mA)
PSM(*1)
/Normal
ON/OFF
Analog Delay
VINTD
DD3VFBK
DD3LX1
DD3GNDB1
DETVBAT
VCCVBUS
VCCVBAT
ADIN[8:4]
ADVDD
(*3) ADGND
VREGUSBIN
DD2GNDB2
DD3INB1
IREF
ON/OFF
DETADP
DD2INB1
DD2INB2
DD2VFBK
DD2LX1
DD2LX2
DD2GNDB1
ON/OFF
CHG Register
(1.8V)
VCCVADP
VSYS
DD1INB1
DD1INB2
DD1VFBK
DD1LX1
DD1LX2
DD1GNDB1
DD1GNDB2
DDGNDA
SUPREG
VBAT1
VBAT2
VBAT3
VBAT4
VCHGREGA
VCHGREGD
IMONI2
THERMBAT
BOOTMASK
VCHG2ENB
VCHG2LIM
PREICHG0
PREICHG1
SUSPEND
VBATTH0
VBATTH1
VTHM
LEDCTL
TEST
ISENSE
OSENSE
FSOURCE
DDINA
Digital Delay
REGCONT
ExternalPower1
E-fuse
COM
(*3)
VRTCIN
DI
DO
CE
CLK
INTOUT
RTC
VINTD
32KOUT
BKBAT
OSCIN
OSCOUT
REGOSC
(2V/1.4V variable)
GPIO
IOVDD
(1.8V)
RESETB
EXTRST
RDET
RESET
ADCONT
IOVDD2
(2.85V/1.8V)
Oscillator
INTC
GPIO[3:0],[11:8]
GPIO[7:4],[13:12]
DET2
REGRTC
(2.85V)
CPUIF
(μ-wire)
Internal(VINTD)
Logic(1.8V)
BKBAT
Logic(2.85V)
Charger Logic
(1.8V)
ADVDD
(2.85V)
VSYS
(4V)
REGOSC
(2.0V/1.4V)
Fig 3-1 Block Diagram
©2012
Rev. 1.0
Page4
POWER MANAGEMENT SYSTEM DEVICE
4. Electrical Characteristics
4.1 Absolute Maximum Ratings
Exposure to the condition exceeded absolute maximum ratings may cause the permanent damages and
affect the reliability and safety of both device and systems using the device. The functional operations
cannot be guaranteed beyond specified values in the recommended conditions.
Parameter
Symbol
Condition
Rating
Units
Battery voltage pin
-0.3~7.0
V
-0.3~4.5
V
Power voltage 1
VBAT1~3
Power voltage 2
ADVDD
2.85V/3.1V power supply pin
Power voltage 3
IOVDD
1.8V power supply pin
-0.3~2.5
V
Power voltage 4
IOVDD2
1.8V/2.85V/3.1V power supply pin
-0.3~4.5
V
Power voltage 5
VBUS
5V power supply pin
-0.3~7.0
V
Power voltage 6
VCHG
CHG power supply pin
-0.3~7.0
V
-0.3~VDD+0.3
V
2273
mW
-55 ~ +125
°C
Input voltage range
Vin
Package power
dissipation
PD
Storage temperature
Tstg
All input pins
(VDD = VBAT, IOVDD, IOVDD2)
JEDEC substrate mounting state,
wind velocity 0m/s, Ta=25°C
Linear derating coefficient=0.0182 W/°C
Power dissipation at Ta=85°C is given by:
PD=(150-85)×(Linear derating coefficient)
Table 4-1 Absolute Maximum Ratings
4.2 Recommendation of Operating Conditions
Parameter
MIN
TYP
MAX
UNITS
VBAT1
VSYS connection power supply pin
3.1
3.6
5.5
V
VBAT2
VSYS connection power supply pin
3.1
3.6
5.5
V
VBAT3
DCDC2V/VSYS connection power supply pin
1.96
3.6
5.5
V
Power voltage 2
ADVDD
2.85V/3.1V power supply pin
2.75
2.85
3.25
V
Power voltage 3
IOVDD
1.8V power supply pin
1.7
1.8
1.9
V
Power voltage 4
IOVDD2
1.8V/2.85V/3.1V power supply pin
1.7
2.85
3.25
V
Power voltage 5
VBUS
5V power supply
4.5
5.0
5.5
V
Power voltage 6
VCHG
Charge power supply pin
4.5
5.0
5.5
V
Temperature range that guarantees the
described electrical characteristics
-30
+85
℃
Power voltage 1
Operating peripheral
temperature
Symbol
Ta
Condition
Table 4-2 Recommendation of Operating Conditions
©2012
Rev. 1.0
Page5
POWER MANAGEMENT SYSTEM DEVICE
5. Pin Configuration
5.1 Pin Configuration
CSP0606 – 120 pin 0.5 mm pitch (TOP VIEW)
11
10
9
8
7
6
5
4
3
2
1
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●
A
B
C
D
E
F
G
H
J
K
L
Pin Configuration (TOP VIEW)
11 NC(OSENSE)
DD1INB1
DD1LX1
DD1GNDB1 DD2GNDB1
DD2LX1
DD2INB1
32KOUT
DO
DD3VFBK
NC(ISENSE)
10
GPIO4
DD1INB2
DD1LX2
DD1GNDB2 DD2GNDB2
DD2LX2
DD2INB2
RDET
CLK
DD3GNDB1
DD3LX1
9
GPIO5
DD1INA
DD1GNDA
DD1VFBK
DD2VFBK
NC(FSOURCE)
SUSPEND
RESETB
CE
EXTRST
DD3INB
8
GPIO11
IOVDD2
GPIO7
GPIO6
IOVDD
INTOUT
L0DET
DI
VINTD
VANA
VANAIN
7
VBATTH0
GPIO13
GPIO12
GPIO10
DGND2
DGND
GPIO9
GPIO1
COM
VGP2
VGP3
6
BOOTMASK
VBATTH1
LEDCTL
PREICHG1
PREICHG0
GPIO8
GPIO0
VGP3IN
VGP12IN
VGP1
5
VCHG11
IMONI2
VCHGREGA VCHG2ENB
VCHG2LIM
GPIO3
GPIO2
GND1
VGP4IN
VGP4
OSCOUT
4
VCHG13
VCHG12
VCCVADP
CHGGND
ADGND
ADIN8
ADIN5
VREG3IN
GND2
BKBAT
OSCIN
3
VSYS4
VSYS3
VCCVBUS
VCHGREGD
ADVDD
ADIN6
ADIN4
VREG12IN
VLOGIN
VRTCIN
VLOG
2
VBAT3
VBAT4
VSYS2
VCHG21
VCHG22
VTHM
ADIN7
VUSB
1
NC
VBAT1
VBAT2
VSYS1
VCHG23
THERMBAT
A
B
C
D
E
F
VCCVBAT VREGUSBIN
G
H
VREG1
VPLLIN
VPLL
VREG2
VREG3
NC(TEST)
J
K
L
Note*: Four pins at the corners of the device are “NC”.
Fig5-1 Pin Configuration
©2012
Rev. 1.0
Page6
1
E9
Name
Block
DD2VFBK DCDC
Function
©2012
Feedback input/ECOREG
output
for Buck DCDCIO monitor
Power pin for Buck DCDCIO
buffer1
Power pin for Buck DCDCIO
buffer2
I/O
D/A
Type
I
Analog
-
Power
(VSYS:3.1~5.5V)
Power
(VSYS: 3.1~5.5V)
PullUp/Down
I/F Voltage
Power
GND
Buff.
State
Initial
State
-
1.8V
DDINA
DDGNDA
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
DD2INB1,2 DD2GNDB1,2
-
-
DD2INB1,2 DD2GNDB1,2
-
-
Up/Down
kΩ
-
-
-
2
G11
DD2INB1
DCDC
3
G10
DD2INB2
DCDC
Buck DCDCIO LX1output pin
O
Analog
-
-
-
1.8V
Buck DCDCIO LX2 output pin
O
Analog
-
-
-
1.8V
-
Table 6-1 Pin Description (1)
Rev. 1.0
4
F11
DD2LX1
DCDC
5
F10
DD2LX2
DCDC
6
E11
DD2GNDB1 DCDC Buck DCDCIO Buffer1 GND pin -
GND
-
-
-
-
-
-
-
-
7
E10
DD2GNDB2 DCDC Buck DCDCIO Buffer2 GND pin -
GND
-
-
-
-
-
-
-
-
8
D11
DD1GNDB1 DCDC Buck DCDCL1 Buffer1GND pin
-
GND
-
-
-
-
-
-
-
-
9
D10
DD1GNDB2 DCDC Buck DCDCL1 Buffer2 GND pin -
GND
-
-
-
-
-
-
-
-
10
C11
DD1LX1
DCDC Buck DCDCL1 LX1 output pin
O
Analog
-
-
-
0.75V~1.375V DD1INB1,2 DD1GNDB1,2
-
-
11
C10
DD1LX2
DCDC Buck DCDCL1 LX2 output pin
O
Analog
-
-
-
0.75V~1.375V DD1INB1,2 DD1GNDB1,2
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
12
B11
DD1INB1
DCDC Buck DCDCL1 Buffer1 power pi -
13
B10
DD1INB2
DCDC Buck DCDCL1 Buffer2 power pi -
14
C9
DDGNDA
DDINA
DCDC
DCDC
15
B9
16
D9
DD1VFBK DCDC
17
K10
DD3GNDB1 DCDC
18
L10
DD3LX1
DD3INB1
Common analog GND pin
for Buck DCDC
Common analog power pin
for Buck DCDC
Feedback input pin
for Buck DCDCL1 monitor
Buck DCDC2V Buffer1 GND
pin
DCDC Buck DCDC2V LX1 output pin
Power
(VSYS:3.1~5.5V)
Power
(VSYS:3.1~5.5V)
-
GND
-
-
-
-
Power
(VSYS:3.1~5.5V)
-
-
-
-
-
-
-
-
I
Analog
-
-
-
0.75V~1.375V
DDINA
DDGNDA
-
-
-
GND
-
-
-
-
-
-
-
-
O
Analog
-
-
-
2.0V/1.8V
DD3INB1
DD3GNDB1
-
-
Power
(VSYS:3.1~5.5V)
-
-
-
-
-
-
-
-
I
Analog
-
-
-
2.0V/1.8V
DDINA
DDGNDA
-
-
DCDC Buck DCDC2V Buffer1 power p -
19
L9
20
K11
21
L4
OSCIN
RTC
Clock input of 32kHz Oscillation I
Analog
-
-
-
1.4V/2.0V
OSCREG GND1
-
-
22
L5
OSCOUT
RTC
Clock output of 32kHz Oscillatio O
Analog
-
-
-
1.4V/2.0V
OSCREG GND1
-
-
DD3VFBK DCDC
Feedback input pin
for Buck DCDC2V monitor
Page7
23
K2
VPLLIN
REG
REGPLL power pin
-
Power
(VSYS:3.1~5.5V)
-
-
-
-
-
-
-
-
24
L2
VPLL
REG
REGPLL output pin
O
Analog
-
-
-
1.025~1.2V
VPLLIN
GND2
-
-
25
L8
VANAIN
REG
Power pin for REGANA/VREFL
-
Power
(VSYS:3.1~5.5V)
-
-
-
-
-
-
-
-
26
K8
VANA
REG
REGANA output pin
O
Analog
-
-
-
2.85V/3.1V
VANAIN
GND1
-
-
27
J2
VREG1
REG
REG1output pin
O
Analog
-
-
-
1.8V
VREG12IN GND2
-
-
-
-
-
-
-
-
-
-
-
-
28
H3
VREG12IN
REG
Power pin for REG1/REG2
-
Power
(VSYS:3.1~5.5V)or
(DCDC2V:2.0V)
29
J1
VREG2
REG
REG2 output pin
O
Analog
-
-
-
1.8V
-
Power
(VSYS:3.1~5.5V)
-
-
-
-
30
J3
VLOGIN
REG
Power pin for REGLOG
-
-
VREG12IN GND2
-
-
Note
POWER MANAGEMENT SYSTEM DEVICE
Ball
No.
6. Pin Description
No.
Ball
No.
Name
Block
Function
I/O
D/A
Type
31
L3
VLOG
REG
REGLOG output pin
O
Analog
PullUp/Down
Up/Down
kΩ
-
-
-
I/F Voltage
Power
GND
Buff.
State
Initial
State
1.8V
VLOGIN
GND2
-
-
-
-
-
©2012
Table 6-2 Pin Description (2)
Rev. 1.0
32
K6
VGP12IN
REG
Power pin
for REGGP1/REGGP2
-
Power
(VSYS:3.1~5.5V)
-
-
-
-
-
33
L6
VGP1
REG
REGGP1output pin
O
Analog
-
-
-
2.85V/3.1V VGP12IN GND1
-
-
34
K7
VGP2
REG
REGGP2 output pin
O
Analog
-
-
-
2.85V/3.1V VGP12IN GND1
-
-
35
J6
VGP3IN
REG
REGGP3 power pin
-
Power
(VSYS:3.1~5.5V)
-
-
-
-
-
-
-
-
36
L7
VGP3
REG
REGGP3 output pin
O
Analog
-
-
-
2.85V/3.1V
VGP3IN
GND1
-
-
37
J5
VGP4IN
REG
REGGP4 power pin
-
Power
(VSYS:3.1~5.5V)
-
-
-
-
-
-
-
-
38
K5
VGP4
REG
REGGP4 output pin
O
Analog
-
-
-
2.85V/3.1V
VGP4IN
GND1
-
-
Power pin for REG3
-
Power
(VSYS:3.1~5.5V)or
(DCDC2V:2.0V)
-
-
-
-
-
-
-
-
REG3 output pin
O
Analog
-
-
-
1.8V
VREG3IN GND2
-
-
O
Analog
-
-
-
2.0V
VANAIN
GND1
-
-
-
GND
-
-
-
-
-
-
-
-
-
GND
-
-
-
-
-
-
-
-
-
Power
(VSYS:3.1~5.5V)
-
-
-
-
-
-
-
-
Analog/
Power(2.85V)
39
H4
VREG3IN
REG
40
K1
VREG3
REG
Reference Voltage(VREF)
output pin
GND pin for VREF/
REGANA/REGGP[14]/REGINTD
GND pin for REGRTC/
REGLOG/REGPLL/REG[1-3]
41
J7
COM
REG
42
H5
GND1
REG
43
J4
GND2
REG
44
K3
VRTCIN
RTC
Power pin for REGRTC
RTC
REGRTC output pin/
RTC power pin
O
45
K4
BKBAT
-
-
-
2.85V
VRTCIN
GND2
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
Page8
46
A5
VCHG11 Charger
Charge Input1-1pin
-
47
B4
VCHG12 Charger
Charge Input1-2 pin
-
48
A4
VCHG13 Charger
Charge Input1-3 pin
-
49
D2
VCHG21 Charger
Charge Input2-1 pin
-
50
E2
VCHG22 Charger
Charge Input2-2 pin
-
51
E1
VCHG23 Charger
Charge Input2-2 pin
-
Power
(VCHG:4.5V~5.5V)
Power
(VCHG:4.5V~5.5V)
Power
(VCHG:4.5V~5.5V)
Power
(VBUS:4.5V~5.5V)
Power
(VBUS:4.5V~5.5V)
Power
(VBUS:4.5V~5.5V)
52
D1
VSYS1
Charger
System Power1 pin
-
Analog
-
-
-
-
-
CHGGND
-
-
53
C2
VSYS2
Charger
System Power2 pin
-
Analog
-
-
-
-
-
CHGGND
-
-
54
B3
VSYS3
Charger
System Power3 pin
-
Analog
-
-
-
-
-
CHGGND
-
-
55
A3
VSYS4
Charger
System Power4 pin
-
Analog
-
-
-
-
-
CHGGND
-
-
56
B1
VBAT1
Charger
Battery1 pin
-
Analog
-
-
-
-
-
CHGGND
-
-
57
C1
VBAT2
Charger
Battery2 pin
-
Analog
-
-
-
-
-
CHGGND
-
-
58
A2
VBAT3
Charger
Battery3 pin
-
Analog
-
-
-
-
-
CHGGND
-
-
VBAT4
Charger
Analog
-
-
-
-
-
CHGGND
-
-
Analog/Power(2.5V -
-
-
-
-
CHGGND
-
-
59
B2
60
C5
VCHGREGACharger
Battery4 pin
-
REG output pin/
Chage analog power pin
O
Note
Connect to GND when
not using Charger.
Connect to GND when
not using Charger.
Connect to GND when
not using Charger.
Connect to GND when
not using Charger.
Connect to GND when
not using Charger.
Connect to GND when
not using Charger.
Connect to GND when
not using Charger.
Connect to GND when
not using Charger.
Connect to GND when
not using Charger.
Connect to GND when
not using Charger.
Connect to GND when
not using Charger.
Connect to GND when
not using Charger.
Connect to GND when
not using Charger.
Connect to GND when
not using Charger.
Connect to GND when
not using Charger.
POWER MANAGEMENT SYSTEM DEVICE
No.
Ball
No.
61
D3
62
B5
Name
Block
VCHGREGDCharger
IMONI2
Charger
Function
©2012
REG output pin/
Carge digital power pin
Output pin
for Charge Current monitor
63
F1
Battery temperature detection
THERMBATCharger
(Thermistor connection) pin
64
D4
CHGGND Charger
GND pin for Charger
I/O
O
D/A
Type
PullUp/Down
I/F Voltage
Power
GND
Buff.
State
Initial
State
-
-
-
CHGGND
-
-
Up/Down
kΩ
Analog/Power(1.8V -
-
O
Analog
-
-
-
-
-
CHGGND
-
-
I
Analog
-
-
-
-
-
CHGGND
-
-
-
GND
-
-
-
-
-
CHGGND
-
-
65
A6
BOOTMASKCharger System boot-up mask control p I
Digital
CMOS
Schmitt
Pull UP
1.1MΩ±50%
1.8V
VCHGREGDDGND1,2
-
-
66
D5
VCHG2ENBCharger Charger ON/OFF setting pin
I
Digital
Pull UP
1.1MΩ±50%
1.8V
VCHGREGDDGND1,2
-
-
67
E5
VCHG2LIM Charger VBUS current limit setting pin
I
Digital
Pull UP
1.1MΩ±50%
1.8V
VCHGREGDDGND1,2
-
-
68
E6
PREICHG0 Charger Trickle charge current setting pi I
Digital
CMOS
Schmitt
CMOS
Schmitt
CMOS
Schmitt
Pull UP
1.1MΩ±50%
1.8V
VCHGREGDDGND1,2
-
-
Table 6-3 Pin Description (3)
Rev. 1.0
69
D6
PREICHG1 Charger Trickle charge current setting pi I
Digital
CMOS
Schmitt
Pull UP
1.1MΩ±50%
1.8V
VCHGREGDDGND1,2
-
-
70
G9
SUSPEND Charger
I
Digital
CMOS
Schmitt
Pull DOWN
1.1MΩ±50%
1.8V
IOVDD DGND1,2
-
-
I
Digital
CMOS
Schmitt
Pull UP
1.1MΩ±50%
1.8V
VCHGREGDDGND1,2
-
-
I
Digital
CMOS
Schmitt
Pull UP
1.1MΩ±50%
1.8V
VCHGREGDDGND1,2
-
-
Voltage apply pin for battery
temperature detection
I/O
Analog
-
-
-
-
VCHGREGACHGGND
-
-
71
A7
VBATTH0 Charger
72
B6
VBATTH1 Charger
73
F2
74
C6
75
C4
76
E4
ADGND
77
E3
78
F4
79
VTHM
Charger
LEDCTL
Charger
Charge suspend setting pin
VSYS output ON/OFF
threshold setting pin
VSYS output ON/OFF
threshold setting pin
LED driver pin
O
Digital
O/D
-
-
-
VCHGREGDDGND1,2
-
-
VCCVADP detection
I
Power
(VCHG:4.5V~5.5V)
-
-
-
-
VCHG1 CHGGND
-
-
ADC
GND pin for AD converter
-
GND
-
-
-
-
-
-
-
-
ADVDD
ADC
Power pin for AD converter
-
Power
(VGP1:2.85V)
-
-
-
-
-
-
-
-
ADIN8
ADC
AD converter input8 pin
I
Analog
-
-
-
0~2.85V
ADVDD
ADGND
-
-
G2
ADIN7
ADC
AD cConverter input7 pin
I
Analog
-
-
-
0~2.85V
ADVDD
ADGND
-
-
80
F3
ADIN6
ADC
AD converter input6 pin
I
Analog
-
-
-
0~2.85V
ADVDD
ADGND
-
-
81
G4
ADIN5
ADC
AD converter input5 pin
I
Analog
-
-
-
0~2.85V
ADVDD
ADGND
-
-
82
G3
ADIN4
ADC
AD converter input4 pin
I
Analog
-
-
-
0~2.85V
ADVDD
ADGND
-
-
I
-
-
-
0~4.5V
ADVDD
ADGND
-
-
I
Power
(VBAT:3.1V~4.5V)
Power
(VBUS:4.5V~5.5V)
-
-
-
0~7V
ADVDD
ADGND
-
-
VCCVADP Charger
ADC conversion BAT input /
VCCVBAT detection
ADC conversion VBUS input
pin/VCCVBUS detection
Page9
83
G1
VCCVBAT
ADC
84
C3
VCCVBUS
ADC
85
H11
32KOUT
RTC
RTC clock output pin
O
Digital
CMOS
-
-
1.8V
IOVDD DGND1,2 2mA
L
86
H9
RESETB
RESET
Reset signal output pin
O
Digital
-
-
-
1.8V
IOVDD DGND1,2 2mA
L
87
H10
RDET
RESET
I
Digital
CMOS
Schmitt
-
-
1.8V
IOVDD DGND1,2
88
G8
L0DET
REGCONT
O
Digital
CMOS
-
-
1.8V
IOVDD DGND1,2 2mA
L
89
J11
DO
CPUIF
O
Digital
CMOS
-
-
1.8V
IOVDD DGND1,2 8mA
Hi-Z
Digital
CMOS
Schmitt
-
-
1.8V
IOVDD
90
H8
DI
CPUIF
Autonomous reset signal
detection pin
Output pin
for Buck DCDCL1 boot-up
Serial data output pin
Serial data input pin
I
DGND1,2
-
-
-
-
Note
Connect to GND when
not using Charger.
Connect to GND when
not using Charger.
Connect to GND when
not using Charger. But,
connect with thermistor
Connect to GND when
not using Charger.
No connection when
not using Charger.
No connection when
not using Charger.
No connection when
not using Charger.
No connection when
not using Charger.
No connection when
not using Charger.
No connection when
not using Charger.
No connection when
not using Charger.
No connection when
not using Charger.
No Connection when
not using Charger. But,
connect with thermistor
No connection when
not using Charger.
No connection when
not using Charger.
No connection when
not using Charger.
No connection when
not using Charger.
No connection when
not using Charger.
No connection when
not using Charger.
No connection when
not using Charger.
"H" output resistance
(12kΩ±50%)
POWER MANAGEMENT SYSTEM DEVICE
No.
Ball
No.
Name
Block
91
J9
CE
©2012
Rev. 1.0
Table 6-4 Pin Description (4)
Power
GND
Buff.
State
Initial
State
-
1.8V
IOVDD
DGND1,2
-
-
-
1.8V
IOVDD
DGND1,2
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
50kΩ±50%
1.8V/2.85V
IOVDD2 DGND1,2 2mA
"PullDpwn" IN
50kΩ±50%
1.8V/2.85V
IOVDD2 DGND1,2 2mA
"PullDpwn" IN
50kΩ±50%
1.8V/2.85V
IOVDD2 DGND1,2 2mA
"PullDpwn" IN
50kΩ±50%
1.8V/2.85V
IOVDD2 DGND1,2 2mA
"PullDpwn" IN
50kΩ±50%
1.8V
I/O
D/A
Type
CPUIF
Chip selector pin
I
Digital
I
-
92
J10
CLK
CPUIF
CLK for Serial data
transmission/reception
93
E7
DGND2
LOGIC
GND pin for IO/Internal logic
PullUp/Down
I/F Voltage
Function
Up/Down
kΩ
CMOS
Schmitt
-
Digital
CMOS
Schmitt
-
GND
-
94
E8
IOVDD
LOGIC
Power pin for Internal IO
95
B8
IOVDD2
LOGIC
Power pin for Internal IO
96
B7
GPIO13
GPIO
GPIO13 input/output pin
Power(DCDCIO:
1.8V)
Power
- (DCDCIO:1.8V)
or
Digital
I/O
97
C7
GPIO12
GPIO
GPIO12 input/output pin
I/O
Digital
98
A8
GPIO11
GPIO
GPIO11 input/output pin
I/O
Digital
Pull Up/Down
CMOS
Schmitt (Register setting)
Pull Up/Down
CMOS
Schmitt (Register setting)
Pull Up/Down
CMOS
Schmitt (Register setting)
Pull Up/Down
CMOS
Schmitt (Register setting)
99
D7
GPIO10
GPIO
GPIO10 input/output pin
I/O
Digital
100
G7
GPIO9
GPIO
GPIO9 input/output pin
I/O
Digital
101
G6
GPIO8
GPIO
GPIO8 input/output pin
I/O
Digital
102
C8
GPIO7
GPIO
GPIO7 input/output pin
I/O
Digital
103
D8
GPIO6
GPIO
GPIO6 input/output pin
I/O
Digital
104
A9
GPIO5
GPIO
GPIO5 input/output pin
I/O
Digital
105
A10
GPIO4
GPIO
GPIO4 input/output pin
I/O
Digital
106
F5
GPIO3
GPIO
GPIO3 input/output pin
I/O
Digital
107
G5
GPIO2
GPIO
GPIO2 input/output pin
I/O
Digital
108
H7
GPIO1
GPIO
GPIO1 input/output pin
I/O
Digital
109
H6
GPIO0
GPIO
GPIO0 input/output pin
I/O
Digital
INTC
Interfupt output pin
O
Digital
CMOS
RESET External reset signal detection p I
Digital
CMOS
Schmitt
Pull Up/Down
CMOS
Schmitt (Register setting)
Pull Up/Down
CMOS
Schmitt (Register setting)
IOVDD
DGND1,2
2mA
"PullDpwn" IN
IOVDD
DGND1,2
2mA
"PullDpwn" IN
50kΩ±50%
1.8V
50kΩ±50%
1.8V/2.85V
IOVDD2 DGND1,2 2mA "OPEN" IN
50kΩ±50%
1.8V/2.85V
IOVDD2 DGND1,2 2mA "OPEN" IN
50kΩ±50%
1.8V/2.85V
IOVDD2 DGND1,2 2mA "OPEN" IN
50kΩ±50%
1.8V/2.85V
IOVDD2 DGND1,2 2mA "OPEN" IN
50kΩ±50%
1.8V
IOVDD
DGND1,2
2mA "OPEN" IN
50kΩ±50%
1.8V
IOVDD
DGND1,2
2mA "OPEN" IN
50kΩ±50%
1.8V
IOVDD
DGND1,2
2mA "OPEN" IN
50kΩ±50%
1.8V
IOVDD
DGND1,2
2mA "OPEN" IN
-
-
1.8V
IOVDD
DGND1,2
2mA
L
Pull UP
100kΩ±50%
1.8V
VINTD
DGND1,2
-
-
-
-
Pull Up/Down
CMOS
Schmitt (Register setting)
Pull Up/Down
CMOS
Schmitt (Register setting)
Pull Up/Down
CMOS
Schmitt (Register setting)
Pull Up/Down
CMOS
Schmitt (Register setting)
Pull Up/Down
CMOS
Schmitt (Register setting)
Pull Up/Down
CMOS
Schmitt (Register setting)
Pull Up/Down
CMOS
Schmitt (Register setting)
Pull Up/Down
CMOS
Schmitt (Register setting)
110
F8
INTOUT
111
K9
EXTRST
112
F7
DGND
LOGIC
GND pin for IO/Internal logic
-
GND
-
-
-
-
113
H2
VUSB
REG
REGUSB output pin
O
Analog
-
-
-
3.3V
REGUSB power pin
-
Power
(VSYS:3.1~5.5V)or
(VBUS:4.5~5.5V)
-
-
-
VSYS:3.1~5.5V
VBUS:4.5~5.5V
-
REGINTD output pin/
Internal logic power
O
Analog/Power(1.8V)
-
-
-
1.8V
VANAIN
PullDown
1MΩ±50%
3.1~5.5V
114
H1
115
J8
116
L1
VREGUSBI REG
VINTD
REG
TEST
Test
TEST1 pin(Test mode control)
I
Digital
CMOS
Schmitt
-
-
-
-
-
-
-
GND1
-
-
-
-
VREGUSBINGND2
VANAIN DGND1,2
Page10
117
L11
ISENSE
Test
TEST2 pin(Test monitor)
I/O
Analog
-
-
-
3.1~5.5V
DDINA
DGND1,2
-
Hi-Z
118
A11
OSENSE
Test
TEST3 pin(Test monitor)
I/O
Analog
-
-
-
3.1~5.5V
DDINA
DGND1,2
-
Hi-Z
119
F9
FSOURCE
Test
TEST4 pin(E-Fuse write)
I/O
Analog
-
-
-
3.1~5.5V
-
DGND1,2
-
-
120
A1
NC
-
-
-
-
-
-
-
-
-
-
-
-
Note
No connection
or Connect to GND.
No connection
or Connect to GND.
No connection
or Connect to GND.
No connection
or Connect to GND.
No connection
or Connect to GND.
POWER MANAGEMENT SYSTEM DEVICE
No.
POWER MANAGEMENT SYSTEM DEVICE
7. Power Control
7.1 Power Mode Control Transition Diagram
This is a reference example of the power mode control used in RC5T7315.
The relationship of each mode transition is shown in the figure below.
Fig 7-1 Power Mode Transition Diagram
©2012
Rev. 1.0
Page11
POWER MANAGEMENT SYSTEM DEVICE
7.2
Block Diagram
Fig 7-2 Power Block Diagram
©2012
Rev. 1.0
Page12
*1)
Output Voltage
Ripple Rejection Rate
( PSM *2) or
Output Noise
Short-Circuit
Current
Current
Limit
Rising Time
LowPSRR )
ON/OFF
Control
PSMz( *2)
Initial
State
Capacitor
Comment
LowPSRR )
©2012
MAX
TYP
MAX
TYP
TYP
MAX
MAX
MAX
Table 8-1 Regulator & DCDC Table
Rev. 1.0
1
REGPLL
3.1V ~ 5.5V
1.15V
1.025 ~ 1.2V Step
25mV 3bit
20mA
20uA
50mV
60d B@1kHz
100μVrms
100mA
150mA
250μs
Register control
-
ON
1.0μF
SinkTr built-in
(SinkTr=OFF at
DeepSleep)
2
REGLOG
3.1V ~ 5.5V
1.8V
(1.7V ~ 2.0V)
*possible to
trimming
50mA
3uA
100mV
50d B@120Hz
100μVrms
120mA
220mA
200μs
Register control
-
OFF
1.0μF
SinkTr built-in
3
REGANA
3.1V ~ 5.5V
2.85V
2.85V/3.1V
150mA
(5mA)
75uA
(1uA)
50mV
(100mV)
60 d B@20kHz
(40dB@120Hz)
55μVrms
150mA
350mA
200μs
Register control
Built-in
OFF
1.0μF
SinkTr built-in
4
REG1
1.96V ~ 5.5V
1.8V
-
100mA
10uA
100mV
300μVrms
190mA
270mA
200μs
Register control
-
OFF
1.0μF
SinkTr built-in
5
REG2
1.96V ~ 5.5V
1.8V
-
100mA
100uA
100mV
60μVrms
190mA
270mA
200μs
Register control
-
OFF
1.0μF
SinkTr built-in
6
REG3
1.96V ~ 5.5V
1.8V
-
150mA
10uA
150mV
300μVrms
190mA
300mA
200μs
Register control
-
OFF
1.0μF
SinkTr built-in
7
REGGP1
3.1V ~ 5.5V
2.85V
2.85V/3.1V
150mA
(5mA)
75uA
(1uA)
40mV
75d B@1kHz
55μVrms
100mA
350mA
200μs
Always ON
(at
DET1release)
Built-in
ON
1.0μF
SinkTr built-in
8
REGGP2
3.1V ~ 5.5V
2.85V
2.85V/3.1V
150mA
(5mA)
75uA
(1uA)
40mV
75d B@1kHz
55μVrms
150mA
350mA
200μs
Register control
Built-in
OFF
1.0μF
SinkTr built-in
9
REGGP3
3.1V ~ 5.5V
2.85V
2.85V/3.1V
200mA
(5mA)
75uA
(1uA)
60mV
75d B@1kHz
55μVrms
170mA
350mA
200μs
Register control
Built-in
OFF
1.0μF
SinkTr built-in
10
REGGP4
3.1V ~ 5.5V
2.85V
2.85V/3.1V
100mA
(5mA)
50uA
(1uA)
60mV
70d B@1kHz
75μVrms
100mA
270mA
200μs
Register control
Built-in
OFF
1.0μF
SinkTr built-in
11
REGRTC
2.3V ~ 5.5V
2.85V
(2.2V at Vin=2.3V)
-
10mA
6uA
100mV
50db@1kHz
130μVrms
120mA
120mA
200μs
Always ON
( at UVLO
release )
-
ON
1.0μF
12
REGUSB
4.35V ~
5.5V(VBUS)
3.3V ~ 5.5V(VSYS)
3.3V
-
115mA (VBUS)
2mA (VSYS)
25uA
100mV (VBUS)
150mV (VSYS)
Vin=3.6V : 40 d B@1kHz
110μVrms
150mA
230mA
200μs
Register control
-
OFF
1.0μF
13
REGINTD
UVLO ~ 5.5V
1.825V
-
10mA
1uA
-
-
-
30mA
30mA
-
Always ON
( at UVLO
release )
-
ON
1.0μF
Vin=2.0V : 40@1kHz
Vin=3.6V : 60@1kHz
Vin=2.0V : 40 d B@20kHz
Vin=3.6V : 70 d B@20kHz
Vin=2.0V : 30@1kHz
Vin=3.6V : 40@1kHz
Vin=5.0V : 65 d B@1kHz
SinkTr built-in
Notes(*1) : The condition of I/O potential difference ≧ 0.2V is necessary to be fulfilled.
Notes(*2) : PSM = Power Save Mode
No.
14
REG Name
DCDCL1
Input Voltage
3.1V ~ 5.5V
Output Voltage
Variable Voltage(V)
1.15V
1.0~ 1.375V
25mV/step(Normal)
0.75~ 0.9375V
12.5mV/step
( DeepSleep)
Maximum
Output Current
Consumption
Current
( PFM )
Transient
Response
Efficiency
(PFM)
Output Ripple
(PFM)
Current Limit
MAX
TYP
MAX
TYP
TYP
TYP
MAX
TYP
1400mA
200μA
(50μA)
100mV
85%@100mA
( 82%@12mA /
82%@40mA )
10mV
(25mV)
2000mA
(2500mA by setting
500μs
ON/OFF
Control
Initial
State
Capacitor
/L value
2.2MHz
Register
control
ON
10μF
(ceramic),
2.2μH
Rising Time Oscillation Freq
Register)
Page13
15
DCDCIO
3.1V ~ 5.5V
1.8V
-
1200mA
200μA
(50μA)
100mV
88%@100mA
( 82%@2mA /
82%@10mA )
10mV
(25mV)
1700mA
500μs
2.2MHz
Always ON(at
DET1release)
ON
10μF
(ceramic),
2.2μH
16
DCDC2V
3.1V ~ 5.5V
2.0V
2.0V/1.8V
350mA
200μA
(50μA)
100mV
85%@100mA
( 82%@5.5mA /
82%@50mA )
10mV
(25mV)
800mA
200μs
2.2MHz
Register
control
OFF
10μF
(ceramic),
2.2μH
Comment
POWER MANAGEMENT SYSTEM DEVICE
Input Voltage(
Transient
Response
10μA ~ Iomax/2
∆t=1μ s
( PSM *2) or
8. Regulator
REG Name
Consumption
Current
( PSM *2) or
LowPSRR )
8.1 Regulators & DCDC Table
No.
Maximum
Variable
Output Current
Voltage(PSM *2) or
( PSM *2) or
LowPSRR)
LowPSRR )
POWER MANAGEMENT SYSTEM DEVICE
9. GPIO
This block is composed of 14 I/O pins with pull-up/down control function.
The input signals to GPIO pins are output to INTC block, and they become one of the interrupt generation
factors.
9.1 Block Diagram
<GPPUPD1>
[D7:D0]
GPIO
<GPPUPD2>
[D7:D0]
<IOSEL1>
[D7:D0]
<IOOUT1>
[D7:D0]
<IOIN1>
[D7:D0]
All 14 pins
Default = Input mode
1
R
0
0
[GPI0INT]
GPIO0
R
0
0
1
1
GPIO1
[GPI1INT]
3
2
5
4
2
GPIO2
1
6
6
5
4
7
GPIO9
GPIO13
[GPI6INT]
6
7
6
GPIO7
GPIO8
[GPI2INT]
2
14 pins
GPIO6
2
0
1
0
0
[GPI7INT]
1
[GPI8INT]
[GPI9INT]
1
3
2
5
[GPI13INT]
5
<IOSEL2>
[D7:D0]
<GPPUPD3>
[D7:D0]
To INTC block
7
1
0
3
2
5
7
<IOOUT2>
[D7:D0]
<IOIN2>
[D7:D0]
<GPPUPD4>
[DD0]
Fig 9-1 Block Diagram
Note*: Registers initialized by [RESET regC] (hardware reset): <IOSEL1~2> and <GPPUPD1~4>.
Registers initialized by [RESET regB] (internal reset): <IOIN1~2> and <IOOUT1~2>.
©2012
Rev. 1.0
Page14
POWER MANAGEMENT SYSTEM DEVICE
10. INTC
INTC block detects the state change of external input signals (GPIO 14 bits) and the internal interrupt signals,
and then it generates interrupt signals. INTC block has the following functions; chattering rejection (30ms),
forward interrupt mask, backward interrupt mask, and interrupt detecting type selection (level/rising
edge/falling edge detection). The interrupt signal INTOUT, which is output from this block, continues to output
“H” until the interrupt factor registers (<FACTOR1~3>) are cleared. To Wakeup (Warm Boost) from Deep
Sleep/Suspend, INT_SIGNAL is used.
10.1 Block Diagram
PWRICGPIO
<FACTOR1[D7:D0]>
<FACTOR2[D7:D0]>
<FACTOR3[D7:D0]>
GPIO
Interrupt Mask
Chattering Rejection
Circuit
Total 22 signals
Default = Mask
[GPI0INT]
Interrupt Mask
Interrupt Factor
Default = ”H” level
H level 00
[GPCR0]
default = 0
Default = Mask
0
0
Chattering
Rejection
0
[FIO00]
Rising 01
1
Falling
30ms
0
10
0
0
0、1
1
[GPI1INT]
14 pins
1
[GPI2INT]
2、3
(*6)
[GPCR ]
[GPCR ]
2
[FIO01]
2
1
4、5
2
1
[FIO02]
2
5
[GPI13INT]
[GPCR
5
[ADINT]
Default=Mask
[INTRA]
[INTRB]
[RTCINT]
0
Default=Mask
Default = 0 Through
Default=Mask
Default = 0 Through
1
[CHGINT]
1
2
From Charger [SDETBAT]
[SDETADP] After
chattering rejection (30ms)
2
Default=Mask
Default = 00
“H” level detection
Default = 00
“H” level detection
Default = 00
“H” level detection
Default = 0 Through
5
5
Default=Mask
Default = 0 Through
6
[SDETUSB] After
chattering rejection(30ms)
Default = 00
“H” level detection
Default = 00
“H” level detection
Default = 00
“H” level detection
Default = 0 Through
0
8 pins
2、3
]
6
Default=Mask
Default = 0 Through
7
7
[FIO13]
6
[INT_SIGNAL]
0
0、1
1
0
2
1
2、3
4、5
2
5
2、3
6
5
7
6
4、5
6、7
7
Other Peripheral
[DET1DELAY]
<FMASK1[D7:D0]>
<FMASK2[D7:D0]>
<FMASK3[D7:D0]>
[32kHz]
<STATE1[D7:D0]>
<STATE2[D7:D0]>
<STATE3[D7:D0]>
<CLRFACT1[D7:D0]>
<CLRFACT2[D7:D0]>
<CLRFACT3[D7:D0]>
<DETMOD1L[D7:D0]>
<DETMOD1H[D7:D0]>
<DETMOD2L[D7:D0]>
<DETMOD2H[D7:D0]>
<DETMOD3L[D7:D0]>
<DETMOD3H[D7:D0]>
[WAKEWAIT_sig]
<BMASK1[D7:D0]>
<BMASK2[D7:D0]>
<BMASK3[D7:D0]>
INTC
Fig 10-1 Block Diagram
©2012
Rev. 1.0
Page15
POWER MANAGEMENT SYSTEM DEVICE
11. ADC
1) Start ADC by the serial I/F register write.
2) The following two types of ADC can be selected:
-Single ADC: Converts one input.
-Auto ADC: Converts four inputs consecutively.
3) Automatically stops after completing the Single/Auto ADC.
4) VCCVBATSW/VCCVBUSSW automatic control function.
5) ADCLK frequency: 32kHz (OSC block).
6) ADC interval time (1s, 10s) is set, ADC is performed automatically, and interrupt signal is generated when ADC
result is out of threshold value range.
11.1 Block Diagram
-
Fig 11-1 Block Diagram
©2012
Rev. 1.0
Page16
POWER MANAGEMENT SYSTEM DEVICE
12. Li-ion Battery Charger
RC5T7315 integrates Li-ion Battery charger, and the outline is as follows.
-There are two external power supply input pins; VCHG1 and VCH2.
-When both VCHG1 and VCHG2 pins have a proper input of voltage range;
the priority is given to VCHG1 pin input. Proper voltage range: 4.0V < VVCHG 1(VCHG2) < 6.3V
-The efficient power supply to the system and battery is performed by the current limit protection and the charge current
control.
-Various timers for the charge control are integrated.
-Chip temperature detection circuit is integrated, and it prevents the chip overheating due to the charge.
-Thermistor temperature monitoring circuit is integrated, and it stops charging at the detection of error temperature while
charging. Also, the temperature can be monitored by the integrated ADC (See “6-5.ADC” for details).
-The following charge modes are provided.
・VCHG1 charge: Charge while supplying power to the system. Start charging after automatically detecting
the
connection of external power supply (VCHG1).
・VCHG2 charge: Has following three modes.
a)
Charge while supplying power to the system.
b)
Battery voltage condition at power-on is changed depending on a level of BOOTMASK external pin.
When BOOTMASK = “H”, charging is started during the power supply to the system, and continues until the
system’s power supply allowable voltage value set by VBATTH0 and VBATTH1. After that, the system turns
on.
When BOOTMASK = “L”, the system can turn on if DET1 is released ([DET1] = “H”) at the connection with an
external power.
c)
In suspend state, the power is supplied from battery, and the charge operation turns OFF.
-There are pins that control the following: Trickle charge current, VCHG2 charge permission, VCHG2 current limit, power
supply permission voltage to the system, VSYS output ON/OFF, and suspend.
-The followings are monitored, and interrupt signals are generated.
VCHG1 connection detection, VCHG2 connection detection, VCHG1 overvoltage, VCHG2 overvoltage
Battery connection detection, Battery overvoltage,
Timer completion (Trickle charge, Rapid charge)
During charge, complete charge
Thermistor high temperature detection, thermistor low temperature detection
-Soft start circuit operates at the VCHG2 charge.
-LED connection pin is equipped; the external LED can be turned on。
-Maximum allowable current from VBAT pin to VSYS pin: 1.6A.
-VCHG1 and VCHG2 pin: 7V withstand (absolute maximum ratings)
©2012
Rev. 1.0
Page17
POWER MANAGEMENT SYSTEM DEVICE
12.1 Li-ion Battery Charger Block Diagram
External
power
supply 1
VCHG11
VSYS1
FET1
System
VCHG1
VCHG12
VCHG1
Overvoltage
detection DET
[VCHG1OV]
VCHG13
VCHG1
VSYS2
(*1,*2)
Reversecurrent
detectio1
VSYS3
VCHG1 VCHG2
FET1 Controller
External
power
supply 2
VCHG21
VSYS4
FET3
VCHG2
VCHG22
VCHG2
Overvoltage
detection DET
[VCHG2OV]
VCHG23
VCHG2
Charger
Controler
FET2
Reversecurrent
detectio3
FET3 Controller
(Soft start)
VBAT1
VCHGREGD
VBAT2
VBAT3
VCHGREGD
VBAT4
VCHGREGD
VCHGREGD
VSYS
VCHG1 or VCHG2
8MHz
Clock
VCHGREGA
VCCVBAT
Battery
Overvoltage
detection DET
[VBOV]
VCCVADP
(*1)
Li-ion
Battery
DDINA
Battery
Connection
detection DET
[SDETBAT]
VCHG1
connection
detection DET
[SDETADP]
VCCVBUS
VCHGREGD
VCHG2
Connection
detection DET
[SDETUSB]
Complete
detection DET
IMONI2
1kΩ
VCHGREGA
LEDCTL
VCHGREGD
BOOTMASK
1.1MΩ
VCHGREGD
ADVDD
CHG
logic
LEDCTL
logic
VTHM
Thermistor
Monitor
VCHGREGD
VCHGREGA
THERMBAT
Thermistor
VCHGREGD
VCHG2ENB
1.1MΩ
VCHG2LIM
1.1MΩ
PREICHG0
1.1MΩ
Chip
temperature
detection
circuit
VCHGREGD
VCHGREGD
Pin
information
VCHGREGD
VCHGREGD
System power
supply permission
DET
VCHGREGD
VCHGREGD
VCHGREGD
1.0uF
VCHGREGA
0.1uF
VCHGREGD
PREICHG1
1.1MΩ
VCHGREGD
Pin control
circuit
Register
information
VINTD
SUSPEND
CHG
register
1.1MΩ
CHGGND
1.1MΩ
Interrupt control
circuit
VINTD
VCHGREGD
VBATTH0
VINTD
IOVDD
[CHGINT]
VCHGREGD
INTOUT
INTC
VCHGREGD
VBATTH1
1.1MΩ
VCHGREGD
to ADC Block
Note(*1): See “Appendix” for decoupring capacitors of VCHG11/12/13 and VCHG21/22/23, and capacitors of
VSYS1/2/3/4 and VBAT1/2/3/4/VCCVBAT.
Note(*2): The total of capacity connected with VSYS pin must become 50uF or less at the nominal capacity value.
Fig 12-1 Li-ion Battery Charger Block Diagram
©2012
Rev. 1.0
Page18
POWER MANAGEMENT SYSTEM DEVICE
NOTICE
1.
The products and the product specifications described in this Data Sheet are subject to change or
discontinuation of production without notice for reasons such as improvement. Therefore, before
deciding to use the products, please refer to Ricoh sales representatives for the latest information
thereon.
2.
This Data Sheet may not be copied or otherwise reproduced in whole or in part without prior written
consent of Ricoh.
3.
Please be sure to take any necessary formalities under relevant laws or regulations before exporting or
otherwise taking out of your country the products or the technical information described herein.
4.
The technical information described in this Data Sheet shows typical characteristics of and example
application circuits for the products. The release of such information is not to be construed as a warranty
of or a grant of license under Ricoh’s or any third party’s intellectual property rights or any other rights.
5.
The products listed in this Data Sheet are intended and designed for use as general electronic
components in standard applications (office equipment, computer equipment, measuring instruments,
consumer electronic products, amusement equipment etc.). Those customers intending to use a product
in an application requiring extreme quality and reliability, for example, in a highly specific application
where the failure or miss-operation of the product could result in human injury or death (aircraft, space
vehicle, nuclear reactor control system, traffic control system, automotive and transportation equipment,
combustion equipment, safety devices, life support system etc.) should first contact us.
6.
We are making our continuous effort to improve the quality and reliability of our products, but
semiconductor products are likely to fail with certain probability. In order prevent any injury to persons or
damages to property resulting from such failure, customers should be careful enough to incorporate
safety measures in their design, such as redundancy feature, fire-containment feature, and fail-safe
feature. We do not assume any liability or responsibility for any loss or damage arising from misuse or
inappropriate use of the products.
7.
Anti-radiation design is not implemented in the products described in this Data Sheet.
8.
Please contact Ricoh sales representatives should you have any questions or comments concerning the
products or the technical information.
Nov. 2012
© RICOH 2012
All materials on this document are protected by Japanese copyright laws, and other applicable laws and treaty provisions of countries
throughout the world. Except for personal or non-commercial internal use, copying, modifying, reproducing in whole or part, transmitting,
distributing, licensing, selling and publishing any of the materials is prohibited without obtaining prior written permission from RICOH.
©2012
Rev. 1.0
Page19