256K x 36/256K x 32/512K x 18 Pipelined SRAM

CY7C1360V25
CY7C1362V25
CY7C1364V25
PRELIMINARY
256K x 36/256K x 32/512K x 18 Pipelined SRAM
Features
• Supports 200-MHz bus
• Fully registered inputs and outputs for pipelined
operation
• Single 2.5V power supply
• Fast clock-to-output times
— 3.1 ns (for 200-MHz device)
— 3.5 ns (for 166-MHz device)
— 4.0 ns (for 133-MHz device
— 5.0 ns (for 100-MHz device
• User-selectable burst counter supporting Intel®
Pentium® interleaved or linear burst sequences
• Separate processor and controller address strobes
• Synchronous self-timed writes
• Asynchronous output enable
• Available as a 100-pin TQFP or 119 BGA
• “ZZ” Sleep Mode option and Stop Clock option
Functional Description
The CY7C1360V25, CY7C1364V25 and CY7C1362V25 are
2.5V, 256K x 36, 256K x 32 and 512K x 18 synchronous-pipelined cache SRAM, respectively. They are designed to support
zero wait state secondary cache with minimal glue logic.
All synchronous inputs pass through input registers controlled
by the rising edge of the clock. All data outputs pass through
output registers controlled by the rising edge of the clock. Maximum access delay from the clock rise is 3.1 ns (200-MHz
device).
The CY7C1360V25/CY7C1364V25/CY7C1362V25 supports
either the interleaved burst sequence used by the Intel Pentium processor or a linear burst sequence used by processors
such as the PowerPC™. The burst sequence is selected
through the MODE pin. Accesses can be initiated by asserting either the Processor Address Strobe (ADSP) or the Controller Address Strobe (ADSC) at clock rise. Address advancement through the burst sequence is controlled by the ADV
input. A 2-bit on-chip wraparound burst counter captures the
first address in a burst sequence and automatically increments
the address for the rest of the burst access.
Byte write operations are qualified with the Byte Write Select
(BWa,b,c,d for 1360V25/1364V25 and BWa,b for 1362V25) inputs. A Global Write Enable (GW) overrides all byte write inputs and writes data to all four bytes. All writes are conducted
with on-chip synchronous self-timed write circuitry.
Three synchronous Chip Selects (CE1, CE2, CE3) and an
asynchronous Output Enable (OE) provide for easy bank selection and output three-state control. In order to provide proper data during depth expansion, OE is masked during the first
clock of a read cycle when emerging from a deselected state.
Logic Block Diagram
CE
D
Data-In REG.
Q
ADV
Ax
GW
CE1
CE2
CE3
BWE
BWx
MODE
ADSP
ADSC
CONTROL
and WRITE
LOGIC
256Kx36/
512Kx18
CLK
OOUTPUT
REGISTERS
and LOGIC
CLK
DQx
DPx
MEMORY
ARRAY
ZZ
OE
1360V25
A[17:0]
1362V25
1364V25
A[18:0]
A[18:0]
DQX
DQa,b,c,d
DQa,b
DQa,b
DPX
DPa,b,c,d
DPa,b
NC
BWX
BWa,b,c,d
BWa,b
BWa,b
AX
Intel and Pentium are registered trademarks of Intel Corporation.
PowerPC is a trademark of IBM Corporation.
Cypress Semiconductor Corporation
•
3901 North First Street
•
San Jose
•
CA 95134
•
408-943-2600
December 3, 1999
CY7C1360V25
CY7C1362V25
CY7C1364V25
PRELIMINARY
Pin Configurations
NC,DQPb
DQb
DQb
VDDQ
VSSQ
DQb
DQb
DQb
DQb
VSSQ
VDDQ
DQb
DQb
VSS
NC
VDD
ZZ
DQa
DQa
VDDQ
VSSQ
DQa
DQa
DQa
DQa
VSSQ
VDDQ
DQa
DQa
NC,DQPa
NC
NC
NC
CY7C1362
(512K x 18)
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
MODE
A
A
A
A
A1
A0
DNU
DNU
V SS
V DD
DNU
A
A
A
A
A
A
A
A
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
VDDQ
VSSQ
NC
NC
DQb
DQb
VSSQ
VDDQ
DQb
DQb
VDD
VDD
NC
VSS
DQb
DQb
VDDQ
VSSQ
DQb
DQb
DPb
NC
VSSQ
VDDQ
NC
NC
NC
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
2
DNU
A
A
A
A
A
A
A
A
CY7C1360/1364
(256K X 36/256K x 32)
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
MODE
A
A
A
A
A1
A0
DNU
DNU
V SS
V DD
NC,DQPc
DQc
DQc
VDDQ
VSSQ
DQc
DQc
DQc
DQc
VSSQ
VDDQ
DQc
DQc
VDD
VDD
NC
VSS
DQd
DQd
VDDQ
VSSQ
DQd
DQd
DQd
DQd
VSSQ
VDDQ
DQd
DQd
NC,DQPd
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
A
A
CE 1
CE 2
NC
NC
BWb
BWa
CE 3
VDD
VSS
CLK
GW
BWE
OE
ADSC
ADSP
ADV
A
A
A
A
CE 1
CE 2
BWd
BWc
BWb
BWa
CE 3
V DD
V SS
CLK
GW
BWE
OE
ADSC
ADSP
ADV
A
A
100-Pin TQFP
A
NC
NC
VDDQ
VSSQ
NC
DPa
DQa
DQa
VSSQ
VDDQ
DQa
DQa
VSS
NC
VDD
ZZ
DQa
DQa
VDDQ
VSSQ
DQa
DQa
NC
NC
VSSQ
VDDQ
NC
NC
NC
CY7C1360V25
CY7C1362V25
CY7C1364V25
PRELIMINARY
Pin Configurations (continued)
119-Ball BGA
1
CY7C1360/1364 (256K x 36/256K x 32)
2
3
4
5
6
7
A
VDDQ
A
A
ADSP
A
A
VDDQ
B
C
NC
NC
CE2
A
A
A
ADSC
VDD
A
A
A
A
NC
NC
D
E
DQc
NC,DQPc
VSS
NC
VSS
NC,DQPb
DQb
DQc
DQc
VSS
CE1
VSS
DQb
DQb
F
VDDQ
DQc
VSS
OE
VSS
DQb
VDDQ
G
H
J
K
DQc
DQc
VDDQ
DQd
DQc
DQc
VDD
DQd
BWc
VSS
NC
VSS
ADV
GW
VDD
CLK
BWb
VSS
NC
VSS
DQb
DQb
VDD
DQa
DQb
DQb
VDDQ
DQa
L
DQd
DQd
BWd
NC
BWa
DQa
DQa
M
VDDQ
DQd
VSS
BWE
VSS
DQa
VDDQ
N
DQd
DQd
VSS
A1
VSS
DQa
DQa
P
DQd
NC,DQPd
VSS
A0
VSS
NC,DQPa
DQa
R
NC
A
MODE
VDD
VDD
A
NC
T
U
NC
VDDQ
NC
TMS
A
TDI
A
TCK
A
TDO
NC
DNU
ZZ
VDDQ
CY7C1362 (512K x 18)
1
2
3
4
5
6
7
A
VDDQ
A
A
ADSP
A
A
VDDQ
B
NC
CE2
A
ADSC
A
A
NC
C
NC
A
A
VDD
A
A
NC
D
DQb
NC
VSS
NC
VSS
DQPa
NC
E
NC
DQb
VSS
CE1
VSS
NC
DQ a
F
VDDQ
NC
VSS
OE
VSS
DQa
VDDQ
G
H
J
NC
DQb
VDDQ
DQb
NC
VDD
BWb
VSS
NC
ADV
GW
VDD
VSS
VSS
NC
NC
DQd
VDD
DQ a
NC
VDDQ
K
NC
DQb
VSS
CLK
VSS
NC
DQ a
L
DQb
NC
VSS
NC
BWa
DQa
NC
M
VDDQ
DQb
VSS
BWE
VSS
NC
VDDQ
N
DQb
NC
VSS
A1
VSS
DQa
NC
P
NC
DQPb
VSS
A0
VSS
NC
DQ a
R
T
U
NC
NC
VDDQ
A
A
TMS
MODE
A
TDI
Vdd
NC
TCK
VDD
A
TDO
A
A
DNU
NC
ZZ
VDDQ
3
CY7C1360V25
CY7C1362V25
CY7C1364V25
PRELIMINARY
Selection Guide
7C1360V25-200 7C1360V25-166 7C1360V25-133 7C1360V25-100
7C1364V25-200 7C1364V25-166 7C1364V25-133 7C1364V25-100
7C1362V25-200 7C1362V25-166 7C1362V25-133 7C1362V25-100
Maximum Access Time (ns)
Maximum Operating Current (mA)
Commercial
Maximum CMOS Standby Current (mA)
3.1
3.5
4.0
5.0
450
400
350
325
10
10
10
10
Pin Definitions (100-Pin TQFP)
x18 Pin Locations x36 Pin Locations
37, 36, 32–25,
37, 36, 32–35,
43–50, 80–82, 99, 43–50, 81, 82, 99,
100
100
Name
A0
A1
A
I/O
InputSynchronous
93, 94
93, 94, 95, 96,
InputSynchronous
88
88
BWa
BWb
BWc
BWd
GW
87
87
BWE
InputSynchronous
89
89
CLK
Input-Clock
98
98
CE1
InputSynchronous
97
97
CE2
InputSynchronous
92
92
CE3
InputSynchronous
86
86
OE
InputAsynchronous
83
83
ADV
InputSynchronous
84
84
ADSP
InputSynchronous
InputSynchronous
4
Description
Address Inputs used to select one of the address
locations. Sampled at the rising edge of the CLK if
ADSP or ADSC is active LOW, and CE1, CE2, and
CE3 are sampled active. A[1:0] feed the 2-bit
counter.
Byte Write Select Inputs, active LOW. Qualified with
BWE to conduct byte writes to the SRAM. Sampled
on the rising edge of CLK.
Global Write Enable Input, active LOW. When asserted LOW on the rising edge of CLK, a global
write is conducted (ALL bytes are written, regardless of the values on BWa,b,c,d and BWE).
Byte Write Enable Input, active LOW. Sampled on
the rising edge of CLK. This signal must be asserted LOW to conduct a byte write.
Clock Input. Used to capture all synchronous inputs
to the device. Also used to increment the burst
counter when ADV is asserted LOW, during a burst
operation.
Chip Enable 1 Input, active LOW. Sampled on the
rising edge of CLK. Used in conjunction with CE2
and CE3 to select/deselect the device. ADSP is ignored if CE1 is HIGH.
Chip Enable 2 Input, active HIGH. Sampled on the
rising edge of CLK. Used in conjunction with CE1
and CE3 to select/deselect the device.
Chip Enable 3 Input, active LOW. Sampled on the
rising edge of CLK. Used in conjunction with CE1
and CE2 to select/deselect the device.
Output Enable, asynchronous input, active LOW.
Controls the direction of the I/O pins. When LOW,
the I/O pins behave as outputs. When deasserted
HIGH, I/O pins are three-stated, and act as input
data pins. OE is masked during the first clock of a
read cycle when emerging from a deselected state.
Advance Input signal, sampled on the rising edge
of CLK. When asserted, it automatically increments
the address in a burst cycle.
Address Strobe from Processor, sampled on the
rising edge of CLK. When asserted LOW, A is captured in the address registers. A[1:0] are also loaded
into the burst counter. When ADSP and ADSC are
both asserted, only ADSP is recognized. ASDP is
ignored when CE1 is deasserted HIGH.
PRELIMINARY
CY7C1360V25
CY7C1362V25
CY7C1364V25
Pin Definitions (100-Pin TQFP) (continued)
x18 Pin Locations x36 Pin Locations
85
85
Name
ADSC
31
31
MODE
64
64
ZZ
InputAsynchronous
(a) 58, 59, 62, 63,
68, 69, 72, 73
(b) 8, 9, 12, 13, 18,
19, 22, 23
(a) 52, 53, 56–59,
62, 63
(b) 68, 69, 72–75,
78, 79
(c) 2, 3, 6–9, 12, 13
(d) 18, 19, 22–25,
28, 29
DQa
DQb
DQc
DQd
I/OSynchronous
74, 24
51, 80, 1, 30
NC,DQPa
NC,DQPb
NC,DQPc
NC,DQPd
I/OSynchronous
15, 41, 65, 91
15, 41, 65, 91
VDD
Power Supply
17, 40, 67, 90
17, 40, 67, 90
VSS
Ground
4, 11, 20, 27, 54,
61, 70, 77
5, 10, 21, 26, 55,
60, 71, 76
1, 2, 3, 6, 7, 14, 16,
25, 28, 29, 30, 51,
52, 53, 56, 57, 66,
75, 78, 79, 95, 96
42
4, 11, 20, 27, 54, 61,
70, 77
5, 10, 21, 26, 55, 60,
71, 76
16, 66
VDDQ
42
DNU
38, 39
38, 39
DNU
VSSQ
I/O
InputSynchronous
InputStatic
I/O Power
Supply
I/O Ground
NC
-
Description
Address Strobe from Controller, sampled on the rising edge of CLK. When asserted LOW, A[x:0] is captured in the address registers. A[1:0] are also loaded
into the burst counter. When ADSP and ADSC are
both asserted, only ADSP is recognized.
Selects Burst Order. When tied to GND selects linear burst sequence. When tied to VDDQ or left floating selects interleaved burst sequence. This is a
strap pin and should remain static during device
operation.
ZZ “sleep” Input. This active HIGH input places the
device in a non-time critical “sleep” condition with
data integrity preserved.
Bidirectional Data I/O lines. As inputs, they feed
into an on-chip data register that is triggered by the
rising edge of CLK. As outputs, they deliver the data
contained in the memory location specified by A
during the previous clock rise of the read cycle. The
direction of the pins is controlled by OE. When OE
is asserted LOW, the pins behave as outputs.
When HIGH, DQa and DPa are placed in a
three-state condition.
Bidirectional Data I/O lines. As inputs, they feed
into an on-chip data register that is triggered by the
rising edge of CLK. As outputs, they deliver the data
contained in the memory location specified by A
during the previous clock rise of the read cycle. The
direction of the pins is controlled by OE. When OE
is asserted LOW, the pins behave as outputs.
When HIGH, DQx and DPx are placed in a
three-state condition.
These are not connect pins on the CY7C1364.
Power supply inputs to the core of the device.
Should be connected to 2.5V power supply.
Ground for the core of the device. Should be connected to ground of the system.
Power supply for the I/O circuitry. Should be connected to a 2.5V power supply.
Ground for the I/O circuitry. Should be connected
to ground of the system.
No Connects.
Do Not Use Pin. This pin is used for the expansion
to the 16M density.
Do Not Use Pins. These pins should be left floating
or tied to VSS.
5
PRELIMINARY
CY7C1360V25
CY7C1362V25
CY7C1364V25
Pin Definitions (119-Ball BGA)
x18 Pin Locations
x36 Pin Locations
4P, 4N, 2A, 3A, 5A,
6A, 3B, 5B, 2C, 3C,
5C, 6C, 2R, 6R, 2T,
3T, 5T, 6B, 6T
4P, 4N,
2A, 2C, 2R, 3A, 3B,
3C, 3T, 4T, 5A, 5B,
5C, 5T, 6A, 6B, 6C,
6R
5L, 3G
Name
I/O
Description
A0
A1
A
InputSynchronous
Address Inputs used to select one of the address
locations. Sampled at the rising edge of the CLK if
ADSP or ADSC is active LOW, and CE1, CE 2, and
CE3 are sampled active. A [1:0] feed the 2-bit
counter.
5L, 5G, 3G, 3L
BWa
BWb
BWc
BWd
InputSynchronous
Byte Write Select Inputs, active LOW. Qualified with
BWE to conduct byte writes to the SRAM. Sampled
on the rising edge of CLK.
4M
4M
GW
InputSynchronous
Global Write Enable Input, active LOW. When asserted LOW on the rising edge of CLK, a global
write is conducted (ALL bytes are written, regardless of the values on BWa,b,c,d and BWE).
4H
4H
BWE
InputSynchronous
Byte Write Enable Input, active LOW. Sampled on
the rising edge of CLK. This signal must be asserted LOW to conduct a byte write.
4K
4K
CLK
Input-Clock
Clock Input. Used to capture all synchronous inputs
to the device. Also used to increment the burst
counter when ADV is asserted LOW, during a burst
operation.
4E
4E
CE1
InputSynchronous
Chip Enable 1 Input, active LOW. Sampled on the
rising edge of CLK. Used in conjunction with CE 2
and CE3 to select/deselect the device. ADSP is ignored if CE1 is HIGH.
97
97
CE2
InputSynchronous
Chip Enable 2 Input, active HIGH. Sampled on the
rising edge of CLK. Used in conjunction with CE1
and CE3 to select/deselect the device. This pin is
also used for expansion to a 16M density SRAM.
92
92
CE3
InputSynchronous
Chip Enable 3 Input, active LOW. Sampled on the
rising edge of CLK. Used in conjunction with CE1
and CE2 to select/deselect the device.
4F
4F
OE
InputAsynchronous
Output Enable, asynchronous input, active LOW.
Controls the direction of the I/O pins. When LOW,
the I/O pins behave as outputs. When deasserted
HIGH, I/O pins are three-stated, and act as input
data pins. OE is masked during the first clock of a
read cycle when emerging from a deselected state.
4G
4G
ADV
InputSynchronous
Advance Input signal, sampled on the rising edge
of CLK. When asserted, it automatically increments
the address in a burst cycle.
4A
4A
ADSP
InputSynchronous
Address Strobe from Processor, sampled on the
rising edge of CLK. When asserted LOW, A is captured in the address registers. A[1:0] are also loaded
into the burst counter. When ADSP and ADSC are
both asserted, only ADSP is recognized. ASDP is
ignored when CE1 is deasserted HIGH.
4B
4B
ADSC
InputSynchronous
Address Strobe from Controller, sampled on the rising edge of CLK. When asserted LOW, A[x:0] is captured in the address registers. A[1:0] are also loaded
into the burst counter. When ADSP and ADSC are
both asserted, only ADSP is recognized.
6
CY7C1360V25
CY7C1362V25
CY7C1364V25
PRELIMINARY
Pin Definitions (119-Ball BGA) (continued)
x18 Pin Locations
x36 Pin Locations
Name
I/O
Description
InputStatic
Selects Burst Order. When tied to GND selects linear burst sequence. When tied to VDDQ or left floating selects interleaved burst sequence. This is a
strap pin and should remain static during device
operation.
3R
3R
MODE
7T
7T
ZZ
InputAsynchronous
ZZ “sleep” Input. This active HIGH input places the
device in a non-time critical “sleep” condition with
data integrity preserved.
(a) 6F, 6H, 6L, 6N,
7E, 7G, 7K, 7P
(b) 1D, 1H, 1L, 1N,
2E, 2G, 2K, 2M
(a) 6K, 6L, 6M, 6N,
7K, 7L, 7N, 7P
(b) 6E, 6F, 6G, 6H,
7D, 7E, 7G, 7H
(c) 1D, 1E, 1G, 1H,
2E, 2F, 2G, 2H
(d) 1K, 1L, 1N, 1P,
2K, 2L, 2M, 2N
DQa
DQb
DQc
DQd
I/OSynchronous
Bidirectional Data I/O lines. As inputs, they feed into
an on-chip data register that is triggered by the rising edge of CLK. As outputs, they deliver the data
contained in the memory location specified by A
during the previous clock rise of the read cycle. The
direction of the pins is controlled by OE. When OE
is asserted LOW, the pins behave as outputs. When
HIGH, DQ x and DQPx are placed in a three-state
condition.
U5
U5
TDO
JTAG Serial
Output
Synchronous
Serial data-out to the JTAG circuit. Delivers data on
the negative edge of TCK.
U3
U3
TDI
JTAG Serial
Input
Synchronous
Serial data-In to the JTAG circuit. Sampled on the
rising edge of TCK.
U2
U2
TMS
Test Mode
Select
Synchronous
This pin controls the Test Access Port state machine. Sampled on the rising edge of TCK.
U4
U4
TCK
JTAG-Clock
Clock input to the JTAG circuitry.
6D, 2P
6P, 6D, 2D, 2P
NC,DQPa
NC,DQPb
NC,DQPc
NC,DQPd
I/OSynchronous
Bidirectional Data I/O lines. As inputs, they feed into
an on-chip data register that is triggered by the rising edge of CLK. As outputs, they deliver the data
contained in the memory location specified by A
during the previous clock rise of the read cycle. The
direction of the pins is controlled by OE. When OE
is asserted LOW, the pins behave as outputs. When
HIGH, DQx and DPx are placed in a three-state condition.
These are not connect pins on the CY7C1364
2J, 4C, 4J, 4R, 5R,
6J
2J, 4C, 4J, 4R, 5R, 6J VDD
Power Supply
Power supply inputs to the core of the device.
Should be connected to 2.5V power supply.
3D, 3E, 3F, 3H, 3K,
3M, 3N, 3P, 5D, 5E,
5F, 5H, 5K, 5M, 5N,
5P
3D, 3E, 3F, 3H, 3K,
3M, 3N, 3P, 5D, 5E,
5F, 5H, 5K, 5M, 5N,
5P
VSS
Ground
Ground for the device. Should be connected to
ground of the system.
1A, 1F, 1J, 1M, 1U,
7A, 7F, 7J, 7M, 7U
1A, 1F, 1J, 1M, 1U,
7A, 7F, 7J, 7M, 7U
VDDQ
1B, 1C, 1E, 1G, 1K, 1B, 1C, 1R, 1T, 2T,
1P, 1R, 1T, 2D, 2F, 3J, 4D, 4L, 5J, 6T, 7B,
2H, 2L, 2N, 3J, 4D, 7C, 7R
4L, 4T, 5J, 6E, 6G,
6K, 6M, 6P, 7B, 7C,
7D, 7H, 7L, 7N, 7R
NC
6U
DNU
6U
I/O Power
Supply
-
Power supply for the I/O circuitry. Should be connected to a 2.5V power supply.
No Connects.
Do Not Use Pins. These pins should be left floating.
7
PRELIMINARY
CY7C1360V25
CY7C1362V25
CY7C1364V25
is loaded into the address register and the address advancement logic while being delivered to the RAM core. The write
signals (GW, BWE, and BWx) and ADV inputs are ignored during this first cycle.
Introduction
Functional Overview
All synchronous inputs pass through input registers controlled
by the rising edge of the clock. All data outputs pass through
output registers controlled by the rising edge of the clock. Maximum access delay from the clock rise (tCO) is 3.1 ns (200-MHz
device).
ADSP triggered write accesses require two clock cycles to
complete. If GW is asserted LOW on the second clock rise, the
data presented to the DQ x inputs is written into the corresponding address location in the RAM core. If GW is HIGH,
then the write operation is controlled by BWE and BWx signals. The CY7C1360V25/1364V25/1362V25 provides byte
write capability that is described in the Write Cycle Description
table. Asserting the Byte Write Enable input (BWE) with the
selected Byte Write ( BWa,b,c,d for CY7C1360V25/1364V25 &
BWa,b for CY7C1362V25) input will selectively write to only the
desired bytes. Bytes not selected during a byte write operation
will remain unaltered. A synchronous self-timed write mechanism has been provided to simplify the write operations.
The CY7C1360V25/CY7C1364V25/CY7C1362V25 supports
secondary cache in systems utilizing either a linear or interleaved burst sequence. The interleaved burst order supports
Pentium and i486 processors. The linear burst sequence is
suited for processors that utilize a linear burst sequence. The
burst order is user selectable, and is determined by sampling
the MODE input. Accesses can be initiated with either the Processor Address Strobe (ADSP) or the Controller Address
Strobe (ADSC). Address advancement through the burst sequence is controlled by the ADV input. A two-bit on-chip wraparound burst counter captures the first address in a burst sequence and automatically increments the address for the rest
of the burst access.
Because the CY7C1360V25/CY7C1364V25/CY7C1362V25
is a common I/O device, the Output Enable (OE) must be
deasserted HIGH before presenting data to the DQ inputs. Doing so will three-state the output drivers. As a safety precaution, DQ are automatically three-stated whenever a write cycle
is detected, regardless of the state of OE.
Byte write operations are qualified with the Byte Write Enable
(BWE) and Byte Write Select (BWa,b,c,d for CY7C1360V25/
CY7C1364V25 and BWa,b for CY7C1362V25) inputs. A Global
Write Enable (GW) overrides all byte write inputs and writes
data to all four bytes. All writes are simplified with on-chip synchronous self-timed write circuitry.
Single Write Accesses Initiated by ADSC
ADSC write accesses are initiated when the following conditions are satisfied: (1) ADSC is asserted LOW, (2) ADSP is
deasserted HIGH, (3) CE1, CE2, CE3 are all asserted active,
and (4) the appropriate combination of the write inputs (GW,
BWE, and BWx) are asserted active to conduct a write to the
desired byte(s). ADSC triggered write accesses require a single clock cycle to complete. The address presented to A[17:0]
is loaded into the address register and the address advancement logic while being delivered to the RAM core. The ADV
input is ignored during this cycle. If a global write is conducted,
the data presented to the DQ[x:0] is written into the corresponding address location in the RAM core. If a byte write is conducted, only the selected bytes are written. Bytes not selected during a byte write operation will remain unaltered. A synchronous
self-timed write mechanism has been provided to simplify the
write operations.
Three synchronous Chip Selects (CE1, CE2, CE3) and an
asynchronous Output Enable (OE) provide for easy bank selection and output three-state control. ADSP is ignored if CE1
is HIGH.
Single Read Accesses
This access is initiated when the following conditions are satisfied at clock rise: (1) ADSP or ADSC is asserted LOW, (2)
CE1, CE2, CE3 are all asserted active, and (3) the write signals
(GW, BWE) are all deasserted HIGH. ADSP is ignored if CE1
is HIGH. The address presented to the address inputs is
stored into the address advancement logic and the Address
Register while being presented to the memory core. The corresponding data is allowed to propagate to the input of the
Output Registers. At the rising edge of the next clock the data
is allowed to propagate through the output register and onto
the data bus within 3.1 ns (200-MHz device) if OE is active
LOW. The only exception occurs when the SRAM is emerging
from a deselected state to a selected state; its outputs are
always three-stated during the first cycle of the access. After
the first cycle of the access, the outputs are controlled by the
OE signal. Consecutive single read cycles are supported.
Once the SRAM is deselected at clock rise by the chip select
and either ADSP or ADSC signals, its output will three-state
immediately.
Because the CY7C1360V25/CY7C1364V25/CY7C1362V25
is a common I/O device, the Output Enable (OE) must be
deasserted HIGH before presenting data to the DQ[x:0] inputs.
Doing so will three-state the output drivers. As a safety precaution, DQ[x:0] are automatically three-stated whenever a write
cycle is detected, regardless of the state of OE.
Burst Sequences
The CY7C1360V25/CY7C1364V25/CY7C1362V25 provides
a two-bit wraparound counter, fed by A[1:0], that implements
either an interleaved or linear burst sequence. The interleaved
burst sequence is designed specifically to support Intel Pentium applications. The linear burst sequence is designed to
support processors that follow a linear burst sequence. The
burst sequence is user selectable through the MODE input.
Single Write Accesses Initiated by ADSP
This access is initiated when both of the following conditions
are satisfied at clock rise: (1) ADSP is asserted LOW, and (2)
CE1, CE2, CE3 are all asserted active. The address presented
8
CY7C1360V25
CY7C1362V25
CY7C1364V25
PRELIMINARY
Asserting ADV LOW at clock rise will automatically increment
the burst counter to the next address in the burst sequence.
Both read and write burst operations are supported.
Linear Burst Sequence
First
Address
Interleaved Burst Sequence
First
Address
Second
Address
Third
Address
Fourth
Address
Second
Address
Third
Address
Fourth
Address
A[1:0]
A[1:0]
A[1:0]
A[1:0]
00
01
10
11
01
10
11
00
10
11
00
01
11
00
01
10
A[1:0]]
A[1:0]
A[1:0]
A[1:0]
00
01
10
11
01
00
11
10
10
11
00
01
Sleep Mode
11
10
01
00
The ZZ input pin is an asynchronous input. Asserting ZZ places the SRAM in a power conservation “sleep” mode. Two clock
cycles are required to enter into or exit from this “sleep” mode.
While in this mode, data integrity is guaranteed. Accesses
pending when entering the “sleep” mode are not considered
valid nor is the completion of the operation guaranteed. The
device must be deselected prior to entering the “sleep” mode.
CE 1, CE2, CE3, ADSP, and ADSC must remain inactive for the
duration of tZZREC after the ZZ input returns LOW.
ZZ Mode Electrical Characteristics
Parameter
Description
Test Conditions
IDDZZ
Snooze mode
standby current
tZZS
tZZREC
Min
Max
Unit
ZZ > VDD − 0.2V
15
mA
Device operation to
ZZ
ZZ > VDD − 0.2V
2tCYC
ns
ZZ recovery time
ZZ < 0.2V
2tCYC
9
ns
CY7C1360V25
CY7C1362V25
CY7C1364V25
PRELIMINARY
Cycle Description[1, 2, 3]
Next Cycle
Add. Used
ZZ
CE3
CE2
CE1
ADSP
ADSC
ADV
OE
DQ
Write
Unselected
None
L
X
X
1
X
0
X
X
Hi-Z
X
Unselected
None
L
1
X
0
0
X
X
X
Hi-Z
X
Unselected
None
L
X
0
0
0
X
X
X
Hi-Z
X
Unselected
None
L
1
X
0
1
0
X
X
Hi-Z
X
Unselected
None
L
X
0
0
1
0
X
X
Hi-Z
X
Begin Read
External
L
0
1
0
0
X
X
X
Hi-Z
X
Begin Read
External
L
0
1
0
1
0
X
X
Hi-Z
Read
Continue Read
Next
L
X
X
X
1
1
0
1
Hi-Z
Read
Continue Read
Next
L
X
X
X
1
1
0
0
DQ
Read
Continue Read
Next
L
X
X
1
X
1
0
1
Hi-Z
Read
Continue Read
Next
L
X
X
1
X
1
0
0
DQ
Read
Suspend Read
Current
L
X
X
X
1
1
1
1
Hi-Z
Read
Suspend Read
Current
L
X
X
X
1
1
1
0
DQ
Read
Suspend Read
Current
L
X
X
1
X
1
1
1
Hi-Z
Read
Suspend Read
Current
L
X
X
1
X
1
1
0
DQ
Read
Begin Write
Current
L
X
X
X
1
1
1
X
Hi-Z
Write
Begin Write
Current
L
X
X
1
X
1
1
X
Hi-Z
Write
Begin Write
External
L
0
1
0
1
0
X
X
Hi-Z
Write
Continue Write
Next
L
X
X
X
1
1
0
X
Hi-Z
Write
Continue Write
Next
L
X
X
1
X
1
0
X
Hi-Z
Write
Suspend Write
Current
L
X
X
X
1
1
1
X
Hi-Z
Write
Suspend Write
Current
L
X
X
1
X
1
1
X
Hi-Z
Write
ZZ “sleep”
None
H
X
X
X
X
X
X
X
Hi-Z
X
Note:
1. X = ”don't care,” 1 = HIGH, 0 = LOW.
2. Write is defined by BWE, BWx, and GW. See Write Cycle Description table.
3. The DQ pins are controlled by the current cycle and the OE signal. OE is asynchronous and is not sampled with the clock.
10
CY7C1360V25
CY7C1362V25
CY7C1364V25
PRELIMINARY
Write Cycle Description[1, 2, 3]
Function (1360/1364)
GW
BWE
BWd
BWc
BWb
BWa
Read
1
1
X
X
X
X
Read
1
0
1
1
1
1
Write Byte 0-DQa
1
0
1
1
1
0
Write Byte 1-DQb
1
0
1
1
0
1
Write Bytes 1, 0
1
0
1
1
0
0
Write Byte 2 - DQc
1
0
1
0
1
1
Write Bytes 2, 0
1
0
1
0
1
0
Write Bytes 2, 1
1
0
1
0
0
1
Write Bytes 2, 1, 0
1
0
1
0
0
0
Write Byte 3 - DQd
1
0
0
1
1
1
Write Bytes 3, 0
1
0
0
1
1
0
Write Bytes 3, 1
1
0
0
1
0
1
Write Bytes 3, 1, 0
1
0
0
1
0
0
Write Bytes 3, 2
1
0
0
0
1
1
Write Bytes 3, 2, 0
1
0
0
0
1
0
Write Bytes 3, 2, 1
1
0
0
0
0
1
Write All Bytes
1
0
0
0
0
0
Write All Bytes
0
X
X
X
X
X
Function (1362)
GW
BWE
BWb
BWa
Read
1
1
X
X
Read
1
0
1
1
Write Byte 0 - DQ[7:0] and DP0
1
0
1
0
Write Byte 1 - DQ[15:8] and DP1
1
0
0
1
Write All Bytes
1
0
0
0
Write All Bytes
0
X
X
X
11
PRELIMINARY
CY7C1360V25
CY7C1362V25
CY7C1364V25
ry. Only one register can be selected at a time through the
instruction registers. Data is serially loaded into the TDI pin on
the rising edge of TCK. Data is output on the TDO pin on the
falling edge of TCK.
IEEE 1149.1 Serial Boundary Scan (JTAG)
The CY7C1360/62 incorporates a serial boundary scan Test
Access Port (TAP) in the FBGA package only. The TQFP package does not offer this functionality. This port operates in accordance with IEEE Standard 1149.1-1900, but does not have
the set of functions required for full 1149.1 compliance. These
functions from the IEEE specification are excluded because
their inclusion places an added delay in the critical speed path
of the SRAM. Note that the TAP controller functions in a manner that does not conflict with the operation of other devices
using 1149.1 fully compliant TAPs. The TAP operates using
JEDEC standard 2.5V I/O logic levels.
Instruction Register
Three-bit instructions can be serially loaded into the instruction
register. This register is loaded when it is placed between the
TDI and TDO pins as shown in the TAP Controller Block
Diagram. Upon power-up, the instruction register is loaded
with the IDCODE instruction. It is also loaded with the IDCODE
instruction if the controller is placed in a reset state as described in the previous section.
When the TAP controller is in the CaptureIR state, the two least
significant bits are loaded with a binary "01" pattern to allow
for fault isolation of the board level serial test path.
Disabling the JTAG Feature
It is possible to operate the SRAM without using the JTAG
feature. To disable the TAP controller, TCK must be tied LOW
(VSS) to prevent clocking of the device. TDI and TMS are internally pulled up and may be unconnected. They may alternately be connected to VDD through a pull-up resistor. TDO
should be left unconnected. Upon power-up, the device will
come up in a reset state which will not interfere with the operation of the device.
Bypass Register
To save time when serially shifting data through registers, it is
sometimes advantageous to skip certain states. The bypass
register is a single-bit register that can be placed between TDI
and TDO pins. This allows data to be shifted through the
SRAM with minimal delay. The bypass register is set LOW
(VSS) when the BYPASS instruction is executed.
Test Access Port (TAP) - Test Clock
The test clock is used only with the TAP controller. All inputs
are captured on the rising edge of TCK. All outputs are driven
from the falling edge of TCK.
Boundary Scan Register
The boundary scan register is connected to all the input and
output pins on the SRAM. Several no connect (NC) pins are
also included in the scan register to reserve pins for higher
density devices. The x36 configuration has a xx-bit-long register, and the x18 configuration has a yy-bit-long register.
Test Mode Select
The TMS input is used to give commands to the TAP controller
and is sampled on the rising edge of TCK. It is allowable to
leave this pin unconnected if the TAP is not used. The pin is
pulled up internally, resulting in a logic HIGH level.
The boundary scan register is loaded with the contents of the
RAM Input and Output ring when the TAP controller is in the
Capture-DR state and is then placed between the TDI and
TDO pins when the controller is moved to the Shift-DR state.
The EXTEST, SAMPLE/PRELOAD and SAMPLE Z instructions can be used to capture the contents of the Input and
Output ring.
Test Data-In (TDI)
The TDI pin is used to serially input information into the registers and can be connected to the input of any of the registers.
The register between TDI and TDO is chosen by the instruction that is loaded into the TAP instruction register. For information on loading the instruction register, see the TAP Controller State Diagram. TDI is internally pulled up and can be
unconnected if the TAP is unused in an application. TDI is
connected to the Most Significant Bit (MSB) on any register.
The Boundary Scan Order tables show the order in which the
bits are connected. Each bit corresponds to one of the bumps
on the SRAM package. The MSB of the register is connected
to TDI, and the LSB is connected to TDO.
Identification (ID) Register
Test Data Out (TDO)
The TDO output pin is used to serially clock data-out from the
registers. The output is active depending upon the current
state of the TAP state machine (see TAP Controller State
Diagram). The output changes on the falling edge of TCK.
TDO is connected to the Least Significant Bit (LSB) of any
register.
The ID register is loaded with a vendor-specific, 32-bit code
during the Capture-DR state when the IDCODE command is
loaded in the instruction register. The IDCODE is hardwired
into the SRAM and can be shifted out when the TAP controller
is in the Shift-DR state. The ID register has a vendor code and
other information described in the Identification Register Definitions table.
Performing a TAP Reset
TAP Instruction Set
A Reset is performed by forcing TMS HIGH (VDD) for five rising
edges of TCK. This RESET does not affect the operation of the
SRAM and may be performed while the SRAM is operating. At
power-up, the TAP is reset internally to ensure that TDO
comes up in a high-Z state.
Eight different instructions are possible with the three-bit instruction register. All combinations are listed in the Instruction
Code table. Three of these instructions are listed as RESERVED and should not be used. The other five instructions
are described in detail below.
TAP Registers
The TAP controller used in this SRAM is not fully compliant to
the 1149.1 convention because some of the mandatory 1149.1
instructions are not fully implemented. The TAP controller cannot be used to load address, data or control signals into the
Registers are connected between the TDI and TDO pins and
allow data to be scanned into and out of the SRAM test circuit-
12
PRELIMINARY
CY7C1360V25
CY7C1362V25
CY7C1364V25
When the SAMPLE / PRELOAD instructions are loaded into
the instruction register and the TAP controller is in the Capture-DR state, a snapshot of data on the inputs and output pins
is captured in the boundary scan register.
SRAM and cannot preload the Input or Output buffers. The
SRAM does not implement the 1149.1 commands EXTEST or
INTEST or the PRELOAD portion of SAMPLE / PRELOAD;
rather it performs a capture of the Inputs and Output ring when
these instructions are executed.
The user must be aware that the TAP controller clock can only
operate at a frequency up to 10 MHz, while the SRAM clock
operates more than an order of magnitude faster. Because
there is a large difference in the clock frequencies, it is possible
that during the Capture-DR state, an input or output will undergo a transition. The TAP may then try to capture a signal while
in transition (metastable state). This will not harm the device,
but there is no guarantee as to the value that will be captured.
Repeatable results may not be possible.
Instructions are loaded into the TAP controller during the
Shift-IR state when the instruction register is placed between
TDI and TDO. During this state, instructions are shifted
through the instruction register through the TDI and TDO pins.
To execute the instruction once it is shifted in, the TAP controller needs to be moved into the Update-IR state.
EXTEST
EXTEST is a mandatory 1149.1 instruction which is to be executed whenever the instruction register is loaded with all 0s.
EXTEST is not implemented in the TAP controller, and therefore this device is not compliant to the 1149.1 standard.
To guarantee that the boundary scan register will capture the
correct value of a signal, the SRAM signal must be stabilized
long enough to meet the TAP controller's capture set-up plus
hold times (tCS and tCH). The SRAM clock input might not be
captured correctly if there is no way in a design to stop (or
slow) the clock during a SAMPLE / PRELOAD instruction. If
this is an issue, it is still possible to capture all other signals
and simply ignore the value of the CK and CK# captured in the
boundary scan register.
The TAP controller does recognize an all-0 instruction. When
an EXTEST instruction is loaded into the instruction register,
the SRAM responds as if a SAMPLE / PRELOAD instruction
has been loaded. There is one difference between the two
instructions. Unlike the SAMPLE / PRELOAD instruction, EXTEST places the SRAM outputs in a High-Z state.
Once the data is captured, it is possible to shift out the data by
putting the TAP into the Shift-DR state. This places the boundary scan register between the TDI and TDO pins.
IDCODE
The IDCODE instruction causes a vendor-specific, 32-bit code
to be loaded into the instruction register. It also places the
instruction register between the TDI and TDO pins and allows
the IDCODE to be shifted out of the device when the TAP controller enters the Shift-DR state. The IDCODE instruction is
loaded into the instruction register upon power-up or whenever
the TAP controller is given a test logic reset state.
Note that since the PRELOAD part of the command is not
implemented, putting the TAP into the Update to the
Update-DR state while performing a SAMPLE / PRELOAD instruction will have the same effect as the Pause-DR command.
Bypass
When the BYPASS instruction is loaded in the instruction register and the TAP is placed in a Shift-DR state, the bypass
register is placed between the TDI and TDO pins. The advantage of the BYPASS instruction is that it shortens the boundary
scan path when multiple devices are connected together on a
board.
SAMPLE Z
The SAMPLE Z instruction causes the boundary scan register
to be connected between the TDI and TDO pins when the TAP
controller is in a Shift-DR state. It also places all SRAM outputs
into a High-Z state.
Reserved
SAMPLE / PRELOAD
These instructions are not implemented but are reserved for
future use. Do not use these instructions.
SAMPLE / PRELOAD is a 1149.1 mandatory instruction. The
PRELOAD portion of this instruction is not implemented, so
the TAP controller is not fully 1149.1 compliant.
13
CY7C1360V25
CY7C1362V25
CY7C1364V25
PRELIMINARY
TAP Controller State Diagram
1
TEST-LOGIC
RESET
0
TEST-LOGIC/
IDLE
1
1
1
SELECT
DR-SCAN
SELECT
IR-SCAN
0
0
1
1
CAPTURE-DR
CAPTURE-DR
0
0
SHIFT-DR
SHIFT-IR
0
1
0
1
1
EXIT1-DR
1
EXIT1-IR
0
0
PAUSE-DR
0
0
PAUSE-IR
1
1
0
0
EXIT2-IR
EXIT2-DR
1
1
UPDATE-DR
1
0
Note: The 0/1 next to each state represents the value at TMS at the rising edge of TCK.
14
UPDATE-IR
1
0
CY7C1360V25
CY7C1362V25
CY7C1364V25
PRELIMINARY
TAP Controller Block Diagram
0
Bypass Register
Selection
Circuitry
2
TDI
1
0
1
0
1
0
Selection
Circuitry
TDO
Instruction Register
31 30
29
.
.
2
Identification Register
x
.
.
.
.
2
Boundary Scan Register
TCK
TAP Controller
TMS
TAP Electrical Characteristics Over the Operating Range[4, 5]
Parameter
Description
Test Conditions
Min.
Max.
Unit
VOH1
Output HIGH Voltage
IOH = –2.0 mA
1.7
V
VOH2
Output HIGH Voltage
IOH = –100 mA
2.1
V
VOL1
Output LOW Voltage
IOL = 2.0 mA
0.7
V
VOL2
Output LOW Voltage
IOL = 100 mA
0.2
V
VIH
Input HIGH Voltage
1.7
VDD+0.3
V
VIL
Input LOW Voltage
–0.3
0.7
V
IX
Input Load Current
–5
5
mA
4.
5.
GND < VI < VDDQ
All Voltage referenced to Ground.
Overshoot: VIH(AC)<VDD+1.5V for t<tTCYC/2, Undershoot: VIL(AC)<0.5V for t<tTCYC/2, Power-up: VIH<2.6V and VDD<2.4V and VDDQ <1.4V for t<200 ms.
15
CY7C1360V25
CY7C1362V25
CY7C1364V25
PRELIMINARY
TAP AC Switching Characteristics Over the Operating Range[6, 7]
Parameters
Description
Min.
Max.
Unit
10
MHz
tTCYC
TCK Clock Cycle Time
tTF
TCK Clock Frequency
100
ns
tTH
TCK Clock HIGH
40
ns
tTL
TCK Clock LOW
40
ns
tTMSS
TMS Set-up to TCK Clock Rise
10
ns
tTDIS
TDI Set-up to TCK Clock Rise
10
ns
tCS
Capture Set-up to TCK Rise
10
ns
tTMSH
TMS Hold after TCK Clock Rise
10
ns
tTDIH
TDI Hold after Clock Rise
10
ns
tCH
Capture Hold after Clock Rise
10
ns
Set-up Times
Hold Times
Output Times
tTDOV
TCK Clock LOW to TDO Valid
tTDOX
TCK Clock LOW to TDO Invalid
20
0
Notes:
6. t CS and t CH refer to the set-up and hold time requirements of latching data from the boundary scan register.
7. Test conditions are specified using the load in TAP AC test conditions. tR/tF= 1 ns.
16
ns
ns
CY7C1360V25
CY7C1362V25
CY7C1364V25
PRELIMINARY
TAP Timing and Test Conditions
1.25V
50Ω
ALL INPUT PULSES
TDO
2.5V
Z0 =50Ω
1.25V
CL =20 pF
0V
GND
(a)
tTH
tTL
Test Clock
TCK
tTCYC
tTMSS
tTMSH
Test Mode Select
TMS
tTDIS
tTDIH
Test Data-In
TDI
Test Data-Out
TDO
tTDOX
17
tTDOV
CY7C1360V25
CY7C1362V25
CY7C1364V25
PRELIMINARY
Identification Register Definitions
Instruction Field
Value
Description
Revision Number
(31:28)
TBD
Reserved for version number.
Device Depth
(27:23)
TBD
Defines depth of SRAM.
Device Width
(22:18)
TBD
Defines with of the SRAM.
Cypress Device ID
(17:12)
TBD
Reserved for future use.
Cypress JEDEC ID
(11:1)
TBD
Allows unique identification of SRAM vendor.
ID Register Presence
(0)
TBD
Indicate the presence of an ID register.
Scan Register Sizes
Register Name
Bit Size
Instruction
3
Bypass
1
ID
32
Boundary Scan
TBD
Identification Codes
Instruction
Code
Description
EXTEST
000
Captures the Input/Output ring contents. Places the boundary scan register
between the TDI and TDO. Forces all SRAM outputs to High-Z state. This
instruction is not 1149.1 compliant.
IDCODE
001
Loads the ID register with the vendor ID code and places the register between TDI and TDO. This operation does not affect SRAM operation.
SAMPLE Z
010
Captures the Input/Output contents. Places the boundary scan register between TDI and TDO. Forces all SRAM output drivers to a High-Z state.
RESERVED
011
Do Not Use: This instruction is reserved for future use.
SAMPLE/PRELOAD
100
Captures the Input/Output ring contents. Places the boundary scan register
between TDI and TDO. Does not affect the SRAM operation. This instruction
does not implement 1149.1 preload function and is therefore not 1149.1
compliant.
RESERVED
101
Do Not Use: This instruction is reserved for future use.
RESERVED
110
Do Not Use: This instruction is reserved for future use.
BYPASS
111
Places the bypass register between TDI and TDO. This operation does not
affect SRAM operation.
18
CY7C1360V25
CY7C1362V25
CY7C1364V25
PRELIMINARY
Boundary Scan Order
Boundary Scan Order
Bit #
Signal
Name
Bump
ID
Bit #
Signal
Name
Bump
ID
Bit #
Signal
Name
Bump
ID
Bit #
Signal
Name
Bump
ID
1
TBD
TBD
36
TBD
TBD
33
TBD
TBD
68
TBD
TBD
2
TBD
TBD
37
TBD
TBD
34
TBD
TBD
69
TBD
TBD
3
TBD
TBD
38
TBD
TBD
35
TBD
TBD
70
TBD
TBD
4
TBD
TBD
39
TBD
TBD
71
TBD
TBD
TBD
TBD
5
TBD
TBD
40
TBD
TBD
72
TBD
TBD
TBD
TBD
6
TBD
TBD
41
TBD
TBD
73
TBD
TBD
TBD
TBD
7
TBD
TBD
42
TBD
TBD
74
TBD
TBD
TBD
TBD
8
TBD
TBD
43
TBD
TBD
75
TBD
TBD
TBD
TBD
9
TBD
TBD
44
TBD
TBD
76
TBD
TBD
TBD
TBD
10
TBD
TBD
45
TBD
TBD
77
TBD
TBD
TBD
TBD
11
TBD
TBD
46
TBD
TBD
78
TBD
TBD
TBD
TBD
12
TBD
TBD
47
TBD
TBD
79
TBD
TBD
TBD
TBD
13
TBD
TBD
48
TBD
TBD
80
TBD
TBD
TBD
TBD
14
TBD
TBD
49
TBD
TBD
81
TBD
TBD
TBD
TBD
15
TBD
TBD
50
TBD
TBD
82
TBD
TBD
TBD
TBD
16
TBD
TBD
51
TBD
TBD
83
TBD
TBD
TBD
TBD
17
TBD
TBD
52
TBD
TBD
84
TBD
TBD
TBD
TBD
18
TBD
TBD
53
TBD
TBD
85
TBD
TBD
TBD
TBD
19
TBD
TBD
54
TBD
TBD
86
TBD
TBD
TBD
TBD
20
TBD
TBD
55
TBD
TBD
87
TBD
TBD
TBD
TBD
21
TBD
TBD
56
TBD
TBD
88
TBD
TBD
TBD
TBD
22
TBD
TBD
57
TBD
TBD
89
TBD
TBD
TBD
TBD
23
TBD
TBD
58
TBD
TBD
90
TBD
TBD
TBD
TBD
24
TBD
TBD
59
TBD
TBD
91
TBD
TBD
TBD
TBD
25
TBD
TBD
60
TBD
TBD
92
TBD
TBD
TBD
TBD
26
TBD
TBD
61
TBD
TBD
93
TBD
TBD
TBD
TBD
27
TBD
TBD
62
TBD
TBD
94
TBD
TBD
TBD
TBD
28
TBD
TBD
63
TBD
TBD
95
TBD
TBD
TBD
TBD
29
TBD
TBD
64
TBD
TBD
96
TBD
TBD
TBD
TBD
30
TBD
TBD
65
TBD
TBD
97
TBD
TBD
TBD
TBD
31
TBD
TBD
66
TBD
TBD
98
TBD
TBD
TBD
TBD
32
TBD
TBD
67
TBD
TBD
99
TBD
TBD
TBD
TBD
19
CY7C1360V25
CY7C1362V25
CY7C1364V25
PRELIMINARY
Current into Outputs (LOW)......................................... 20 mA
Static Discharge Voltage .......................................... >2001V
(per MIL-STD-883, Method 3015)
Latch-Up Current .................................................... >200 mA
Maximum Ratings
(Above which the useful life may be impaired. For user guidelines, not tested.)
Storage Temperature ..................................... −65°C to +150°C
Ambient Temperature with
Power Applied .................................................. −55°C to +125°C
Supply Voltage on VDD Relative to GND .........−0.3V to +3.6V
DC Voltage Applied to Outputs
in High Z State[8] .....................................−0.5V to VDDQ + 0.5V
DC Input Voltage[8] ..................................−0.5V to VDDQ + 0.5V
Operating Range
Range
Ambient
Temperature[9]
VDD/VDDQ
Com’l
0°C to +70°C
2.5V ± 5%
Electrical Characteristics Over the Operating Range
Parameter
Description
Test Conditions
Min.
Max.
Unit
VDD
Power Supply Voltage
2.375
2.625
V
VDDQ
I/O Supply Voltage
2.375
2.625
V
VOH
Output HIGH Voltage
VDD = Min., IOH = −1.0 mA
VOL
Output LOW Voltage
VDD = Min., IOL = 1.0 mA
VIH
Input HIGH Voltage
VIL
Input LOW Voltage[8]
IX
Input Load Current
except ZZ and MODE
IZZ
Input Current of MODE
2.0
GND ≤ VI ≤ V DDQ
0.2
V
1.7
VDD + 0.3V
V
−0.3
0.7
V
−5
5
µA
−30
30
µA
Input Current of ZZ
Input = VSS
−5
IOZ
Output Leakage
Current
GND ≤ VI ≤ V DDQ, Output Disabled
−2
IDD
VDD Operating Supply
Current
VDD = Max., IOUT = 0 mA,
f = fMAX = 1/tCYC
ISB1
Automatic CS
Power-Down
Current—TTL Inputs
Max. VDD, Device Deselected,
VIN ≥ V IH or VIN ≤ VIL
f = fMAX = 1/tCYC
ISB2
Automatic CS
Max. VDD, Device Deselected, VIN
Power-Down
≤ 0.3V or VIN > VDDQ – 0.3V, f = 0
Current—CMOS Inputs
ISB3
Automatic CS
Max. VDD, Device Deselected, or
Power-Down
VIN ≤ 0.3V or VIN > VDDQ – 0.3V
Current—CMOS Inputs f = fMAX = 1/tCYC
ISB4
Automatic CS
Power-Down
Current—TTL Inputs
Max. VDD, Device Deselected,
VIN ≥ V IH or VIN ≤ VIL, f = 0
Note:
8. Minimum voltage equals –2.0V for pulse durations of less than 20 ns.
9. TA is the temperature.
20
V
µA
2
µA
5.0-ns cycle, 200 MHz
450
mA
6.0-ns cycle, 166 MHz
400
mA
7.5-ns cycle, 133 MHz
350
mA
10-ns cycle, 100 MHz
325
mA
5.0-ns cycle, 200 MHz
90
mA
6.0-ns cycle, 166 MHz
80
mA
7.5-ns cycle, 133 MHz
70
mA
10-ns cycle, 100 MHz
65
mA
10
mA
5.0-ns cycle, 200 MHz
45
mA
6.0-ns cycle, 166 MHz
40
mA
7.5-ns cycle, 133 MHz
35
mA
10-ns cycle, 100 MHz
30
mA
25
mA
CY7C1360V25
CY7C1362V25
CY7C1364V25
PRELIMINARY
Capacitance[10]
Parameter
Description
Test Conditions
CIN
Input Capacitance
CCLK
Clock Input Capacitance
CI/O
Input/Output Capacitance
TA = 25°C, f = 1 MHz,
VDD = 2.5V,
VDDQ = 2.5V
Max.
Unit
4
pF
4
pF
4
pF
AC Test Loads and Waveforms[11]
R=1667Ω
2.5V
OUTPUT
ALL INPUT PULSES
OUTPUT
Z0 =50Ω
RL =50Ω
2.5V
10%
5 pF
R=1538Ω
VL = 1.25V
(a)
INCLUDING
JIG AND
SCOPE
(b)
Note:
10. Tested initially and after any design or process changes that may affect these parameters.
11. Input waveform should have a slew rate of 1 V/ns.
21
[10]
90%
10%
90%
GND
≤ 2.5ns
≤ 2.5ns
(c)
CY7C1360V25
CY7C1362V25
CY7C1364V25
PRELIMINARY
Switching Characteristics Over the Operating Range[12, 13, 14]
-200
Parameter
Min.
Description
-166
Max.
Min.
-133
Max.
Min.
-100
Max.
Min.
Max.
Unit
tCYC
Clock Cycle Time
5.0
6.0
7.5
10
ns
tCH
Clock HIGH
1.6
1.7
1.9
3.2
ns
tCL
Clock LOW
1.6
1.7
1.9
3.2
ns
tAS
Address Set-Up Before CLK Rise
1.5
1.5
2.0
2.0
ns
tAH
Address Hold After CLK Rise
0.5
0.5
0.5
0.5
ns
tCO
Data Output Valid After CLK Rise
tDOH
Data Output Hold After CLK Rise
1.0
1.5
1.5
1.5
ns
tADS
ADSP, ADSC Set-Up Before CLK
Rise
1.5
1.5
2.0
2.0
ns
tADH
ADSP, ADSC Hold After CLK Rise
0.5
0.5
0.5
0.5
ns
tWES
BWE, GW, BWx Set-Up Before CLK
Rise
1.5
1.5
2.0
2.0
ns
tWEH
BWE, GW, BWx Hold After CLK Rise
0.5
0.5
0.5
0.5
ns
tADVS
ADV Set-Up Before CLK Rise
1.5
1.5
2.0
2.0
ns
tADVH
ADV Hold After CLK Rise
1.5
1.5
0.5
0.5
ns
tDS
Data Input Set-Up Before CLK Rise
1.5
1.5
2.0
2.0
ns
tDH
Data Input Hold After CLK Rise
0.5
0.5
0.5
0.5
ns
tCES
ChipEnable Set-Up
1.5
1.5
2.0
2.0
ns
tCEH
Chip Enable Hold After CLK Rise
0.5
0.5
0.5
0.5
ns
tCHZ
[13]
1.5
tCLZ
Clock to High-Z
[13]
Clock to Low-Z
3.1
0
[13, 14]
tEOHZ
OE HIGH to Output High-Z
tEOLZ
OE LOW to Output Low-Z[13, 14]
tEOV
3.1
[13]
OE LOW to Output Valid
3.5
1.5
3.5
0
3.2
0
1.5
4.2
0
3.5
0
3.1
4.2
1.5
5.0
0
4.2
0
3.5
5.0
ns
ns
4.5
0
4.2
ns
ns
ns
5.0
ns
Notes:
12. Unless otherwise noted, test conditions assume signal transition time of 2.5 ns or less, timing reference levels of 1.25V, input pulse levels of 0 to 2.5V, and
output loading of the specified I OL/IOH and load capacitance. Shown in (a), (b) and (c) of AC Test Loads.
13. t CHZ, t CLZ, tOEV, t EOLZ, and tEOHZ are specified with a load capacitance of 5 pF as in part (b) of AC Test Loads. Transition is measured ± 200 mV from
steady-state voltage.
14. At any given voltage and temperature, tEOHZ is less than t EOLZ and tCHZ is less than tCLZ.
22
CY7C1360V25
CY7C1362V25
CY7C1364V25
PRELIMINARY
1
Switching Waveforms
Write Cycle Timing[15, 16]
Single Write
Burst Write
Pipelined Write
tCH
Unselected
tCYC
CLK
tADH
tADS
tCL
ADSP ignored with CE1 inactive
ADSP
tADH
tADS
ADSC initiated write
ADSC
tADVH
tADVS
ADV
tAS
ADD
ADV Must Be Inactive for ADSP Write
WD1
WD3
WD2
tAH
GW
tWS
tWH
WE
tCES
tWH
tWS
tCEH
CE1 masks ADSP
CE1
tCES
tCEH
Unselected with CE2
CE2
CE3
tCES
tCEH
OE
tDH
tDS
Data- High-Z
In
1a
1a
2a
2b
2c
= UNDEFINED
2d
= DON’T CARE
Notes:
15. WE is the combination of BWE, BWx, and GW to define a write cycle (see Write Cycle Description table).
16. WDx stands for Write Data to Address X.
23
3a
High-Z
CY7C1360V25
CY7C1362V25
CY7C1364V25
PRELIMINARY
Switching Waveforms (continued)
Read Cycle Timing[15, 17]
Single Read
tCYC
Burst Read
Unselected
tCH
Pipelined Read
CLK
tADH
tADS
tCL
ADSP ignored with CE1 inactive
ADSP
tADS
ADSC initiated read
ADSC
tADVS
tADH
Suspend Burst
ADV
tADVH
tAS
ADD
RD1
RD3
RD2
tAH
GW
tWS
tWS
tWH
WE
tCES
tCEH
tWH
CE1 masks ADSP
CE1
Unselected with CE2
CE2
tCES
tCEH
CE3
tCES
OE
tCEH
tEOV
tOEHZ
tDOH
Data Out
tCO
1a
1a
2a
2b
2c 2c
2d
3a
tCLZ
tCHZ
= DON’T CARE
= UNDEFINED
Note:
17. RDx stands for Read Data from Address X.
24
CY7C1360V25
CY7C1362V25
CY7C1364V25
PRELIMINARY
Switching Waveforms (continued)
Read/Write Cycle Timing[15, 16, 17]
Single Read
tCYC
Single Write
Unselected
Burst Read
tCH
Pipelined Read
CLK
tADH
tADS
tCL
ADSP ignored with CE1 inactive
ADSP
tADS
ADSC
tADVS
tADH
ADV
tAS
ADD
tADVH
RD1
WD2
RD3
tAH
GW
tWS
tWS
tWH
WE
tCES
tCEH
tWH
CE1 masks ADSP
CE1
CE2
tCES
tCEH
CE3
tCES
tCEH
tEOV
OE
tEOHZ
Data In/Out
tEOLZ
tCO
1a
1a
Out
tDS
tDH
2a
In
2a
Out
= DON’T CARE
= UNDEFINED
25
3a
Out
tDOH
3b
Out
3c
Out
3d
Out
tCHZ
CY7C1360V25
CY7C1362V25
CY7C1364V25
PRELIMINARY
Switching Waveforms (continued)
Pipeline Timing[18, 19]
tCH
tCYC
tCL
CLK
tAS
ADD
RD1
tADS
RD2
RD3
WD1
RD4
WD2
WD3
WD4
tADH
ADSC initiated Reads
ADSC
ADSP initiated Reads
ADSP
ADV
tCEH
tCES
CE1
CE
tWES
tWEH
WE
ADSP ignored
with CE1 HIGH
OE
tCLZ
Data In/Out
1a
Out
2a
Out
3a
Out
1a
In
4a
Out
2a
In
3a
In
tCDV
tDOH
Back to Back Reads
tCHZ
= UNDEFINED
= DON’T CARE
Notes:
18. Device originally deselected.
19. CE is the combination of CE2 and CE3. All chip selects need to be active in order to select the device.
26
4a
D(C)
In
CY7C1360V25
CY7C1362V25
CY7C1364V25
PRELIMINARY
Switching Waveforms (continued)
OE Switching Waveforms
OE
tEOV
tEOHZ
I/Os
Three-State
tEOLZ
27
PRELIMINARY
CY7C1360V25
CY7C1362V25
CY7C1364V25
Switching Waveforms (continued)
ZZ Mode Timing [20, 21]
CLK
ADSP
HIGH
ADSC
CE1
CE2
LOW
HIGH
CE3
ZZ
IDD
tZZS
IDD(active)
IDDZZ
tZZREC
I/O’s
Three-state
NotefjdfdhfdjfdfjdjdjdjNo
Note:
20. Device must be deselected when entering ZZ mode. See Cycle Description Table for all possible signal conditions to deselect the device.
21. I/Os are in three-state when exiting ZZ sleep mode.
28
CY7C1360V25
CY7C1362V25
CY7C1364V25
PRELIMINARY
Ordering Information
Speed
(MHz)
Ordering Code
200
CY7C1360V25-200AC
166
CY7C1360V25-166AC
133
CY7C1360V25-133AC
100
CY7C1360V25-100AC
200
CY7C1362V25-200AC
166
CY7C1362V25-166AC
133
CY7C1362V25-133AC
100
CY7C1362V25-100AC
200
CY7C1364V25-200AC
166
CY7C1364V25-166AC
133
CY7C1364V25-133AC
100
CY7C1364V25-100AC
200
CY7C1360V25-200BGC
166
CY7C1360V25-166BGC
133
CY7C1360V25-133BGC
100
CY7C1360V25-100BGC
200
CY7C1362V25-200BGC
166
CY7C1362V25-166BGC
133
CY7C1362V25-133BGC
100
CY7C1362V25-100BGC
200
CY7C1364V25-200BGC
166
CY7C1364V25-166BGC
133
CY7C1364V25-133BGC
100
CY7C1364V25-100BGC
Package
Name
Package Type
Operating
Range
A101
100-Lead Thin Quad Flat Pack
Commercial
A101
100-Lead Thin Quad Flat Pack
Commercial
A101
100-Lead Thin Quad Flat Pack
Commercial
BG119
119-Ball (14 x 22 x 2.4 mm) BGA
Commercial
BG119
119-Ball (14 x 22 x 2.4 mm) BGA
Commercial
BG119
119-Ball (14 x 22 x 2.4 mm) BGA
Commercial
Document #:38–00760–A
29
PRELIMINARY
CY7C1360V25
CY7C1362V25
CY7C1364V25
Package Diagrams
100-Pin Thin Plastic Quad Flatpack (14 x 20 x 1.4 mm) A101
51-85050-A
30
CY7C1360V25
CY7C1362V25
CY7C1364V25
PRELIMINARY
Package Diagrams (continued)
119-Lead FBGA (14 x 22 x 2.4 mm) BG119
51-85115
Revision History
Document Title: CY7C1360V25/CY7C1362V25/CY7C1364V25
Document Number: 38-00760
REV.
ECN NO.
ISSUE DATE
ORIG. OF
CHANGE
**
2560
4/29/99
SKX
1. New Datasheet
*A
2683
9/10/99
SKX
1. Updated the BGA pinout
2. Added revision history
DESCRIPTION OF CHANGE
© Cypress Semiconductor Corporation, 1999. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use
of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize
its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress
Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges.