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AS4C128M8D2
Confidential
128M x 8 bit DDRII Synchronous DRAM (SDRAM)
Advanced (Rev. 1.0, Jun. /2013)
Features
JEDEC Standard Compliant
JEDEC standard 1.8V I/O (SSTL_18-compatible)
Power supplies: V
DD
& V
DDQ
= +1.8V 0.1V
Operating temperature range
- Commercial (0 ~ 85°C)
- Industrial (-40 ~ 95°C)
Fully synchronous operation
Fast clock rate: 400 MHz
Differential Clock, CK & CK#
Bidirectional single/differential data strobe
8 internal banks for concurrent operation
4-bit prefetch architecture
Internal pipeline architecture
Precharge & active power down
Programmable Mode & Extended Mode registers
Posted CAS# additive latency (AL): 0, 1, 2, 3, 4, 5, 6
WRITE latency = READ latency - 1 t
CK
Burst lengths: 4 or 8
Burst type: Sequential / Interleave
DLL enable/disable
On-die termination (ODT)
RoHS compliant
Auto Refresh and Self Refresh
8192 refresh cycles / 64ms
- Average refresh period
7.8µs @ 0℃ ≦TC≦ +85℃
3.9µs @ +85℃ <TC≦ +95℃
60-ball 8 x 10 x 1.2mm (max) FBGA package
-
Pb and Halogen Free
Table 1. Ordering Information
Overview
The DDR2 SDRAM is a high-speed CMOS Double-Data-
Rate-Two (DDR2), synchronous dynamic random - access memory (SDRAM) containing 1024 Mbits in a 8-bit wide data I/Os. It is internally configured as a 8-bank DRAM, 8 banks x 16Mb addresses x 8 I/Os.
The device is designed to comply with DDR2 DRAM key features such as posted CAS# with additive latency, Write latency = Read latency -1 and On Die Termination(ODT)
.
All of the control and address inputs are synchronized with a pair of externally supplied differential clocks. Inputs are latched at the cross point of differential clocks (CK rising and CK# falling)
All I/Os are synchronized with a pair of bidirectional strobes
(DQS and DQS#) in a source synchronous fashion. The address bus is used to convey row, column, and bank address information in RAS #, CAS# multiplexing style.
Accesses begin with the registration of a Bank Activate command, and then it is followed by a Read or Write command. Read and write accesses to the DDR2 SDRAM are
4 or 8-bit burst oriented; accesses start at a selected location and continue for a programmed number of locations in a programmed sequence.
Operating the eight memory banks in an interleaved fashion allows random access operation to occur at a higher rate than is possible with standard DRAMs. An auto precharge function may be enabled to provide a self-timed row precharge that is initiated at the end of the burst sequence.
A sequential and gapless data rate is possible depending on burst length, CAS latency, and speed grade of the device.
Part Number
AS4C128M8D2-25BCN
Clock Frequency
400MHz
Data Rate
800Mbps/pin V
DD
Power Supply
1.8V, V
DDQ
1.8V
AS4C128M8D2-25BIN 400MHz 800Mbps/pin VDD 1.8V, VDDQ 1.8V
B: indicates 60-ball 8 x 10 x 1.2mm (max) FBGA package
C: indicates commercial temperature
I: indicates industrial temperature
N: indicates Pb and Halogen Free ROHS
Table 2. Speed Grade Information
Package
FBGA
FBGA
Speed Grade
DDR2-800
Clock Frequency
400 MHz
CAS Latency
5
Alliance Memory Inc. 551 Taylor Way, San Carlos, CA 94070
TEL: (650) 610-6800 FAX: (650) 620-9211
t
RCD
(ns)
12.5
Alliance Memory Inc. reserves the right to change products or specification without notice.
1 Rev. 1.0
t
RP
(ns)
12.5
June 2013
H
J
F
G
K
C
D
A
B
E
L
AS4C128M8D2
Figure 1. Ball Assignment (FBGA Top View)
1 2 3
…
7 8 9
VDD
DQ6
VDDQ
DQ4
VDDL
BA2
VSS
VDD
RDQS#
VSSQ
DQ1
VSSQ
VREF
CKE
BA0
A10
A3
A7
A12
VSS
DM/
RDQS
VDDQ
DQ3
VSS
WE#
BA1
A1
A5
A9
NC
VSSQ
DQS
VDDQ
DQ2
VSSDL
RAS#
CAS#
A2
A6
A11
NC
DQS#
VSSQ
DQ0
VSSQ
CK
CK#
CS#
A0
A4
A8
A13
VDDQ
DQ7
VDDQ
DQ5
VDD
ODT
VDD
VSS
Alliance Memory Inc. 551 Taylor Way, San Carlos, CA 94070
TEL: (650) 610-6800 FAX: (650) 620-9211
Alliance Memory Inc. reserves the right to change products or specification without notice.
2 Rev. 1.0 June 2013
Figure 2. Block Diagram
CK
CK#
CKE
AS4C128M8D2
DLL
CLOCK
BUFFER
16M x 8
CELL ARRAY
(BANK #0)
Column Decoder
CS#
RAS#
CAS#
WE#
COMMAND
DECODER
CONTROL
SIGNAL
GENERATOR
16M x 8
CELL ARRAY
(BANK #1)
Column Decoder
16M x 8
CELL ARRAY
(BANK #2)
Column Decoder
A10/AP
COLUMN
COUNTER
MODE
REGISTER
16M x 8
CELL ARRAY
(BANK #3)
Column Decoder
A0~A9
A11~A13
BA0~BA2
ADDRESS
BUFFER
16M x 8
CELL ARRAY
(BANK #4)
Column Decoder
REFRESH
COUNTER
16M x 8
CELL ARRAY
(BANK #5)
Column Decoder
DQS
DQS#
RDQS
RDQS#
DATA
STROBE
BUFFER
DQ0
DQ7
DQ
Buffer
ODT DM
Alliance Memory Inc. 551 Taylor Way, San Carlos, CA 94070
TEL: (650) 610-6800 FAX: (650) 620-9211
Alliance Memory Inc. reserves the right to change products or specification without notice.
3 Rev. 1.0
16M x 8
CELL ARRAY
(BANK #6)
Column Decoder
16M x 8
CELL ARRAY
(BANK #7)
Column Decoder
June 2013
AS4C128M8D2
Figure 3. State Diagram
OCD calibration
Initialization
Sequence
CKEL
Self
Refreshing
PR
SRF
CKE
H
Setting
MR,
EMR(1)
EMR(2)
EMR(3)
(E)MRS
Idle
All banks precharged
ACT
CKE
L
CKE
H
REF
CK
EL
Refreshing
Precharge
Power
Down
Activating
Automatic Sequence
Cammand Sequence
CKEL
Active
Power
Down
CKE
L
CKEL
WR
Writing
WRA
Writing
With
Autoprecharge
CKEH
CKEL
Bank
Active
RD
RD
WR
W
RA
RD
Reading
WR
RD
A
RDA
WR
A
PR, PRA
PR, PRA
PR, PRA
RDA
Reading
With
Autoprecharge
Precharging
CKEL = CKE LOW, enter Power Down
CKEH = CKE HIGH, exit Power Down,exit Self Refresh
ACT = Activate
WR(A) = Write (with Autoprecharge)
RD(A) = Read (with Autoprecharge)
PR(A) = Precharge (All)
(E)MRS = (Extended) Mode Register Set
SRF = Enter Self Refresh
REF = Refresh
Note: Use caution with this diagram. It is indented to provide a floorplan of the possible state transitions and the commands to control them, not all details. In particular situations involving more than one bank, enabling/disabling on-die termination, Power Down entry/exit, timing restrictions during state transitions, among other things, are not captured in full detail.
Alliance Memory Inc. 551 Taylor Way, San Carlos, CA 94070
TEL: (650) 610-6800 FAX: (650) 620-9211
Alliance Memory Inc. reserves the right to change products or specification without notice.
4 Rev. 1.0 June 2013
AS4C128M8D2
Ball Descriptions
Symbol
CK, CK#
CKE
BA0-BA2
Table 3. Ball Descriptions
Type Description
Input Differential Clock: CK, CK# are driven by the system clock. All SDRAM input signals are sampled on the crossing of positive edge of CK and negative edge of CK#. Output (Read) data is referenced to the crossings of CK and CK# (both directions of crossing).
Input Clock Enable: CKE activates (HIGH) and deactivates (LOW) the CK signal. If CKE goes LOW synchronously with clock, the internal clock is suspended from the next clock cycle and the state of output and burst address is frozen as long as the CKE remains LOW. When all banks are in the idle state, deactivating the clock controls the entry to the Power Down and Self
Refresh modes.
Input Bank Address: BA0-BA2 define to which bank the BankActivate, Read, Write, or
BankPrecharge command is being applied.
A0-A13
CS#
Input Address Inputs: A0-A13 are sampled during the BankActivate command (row address A0-A13) and Read/Write command (column address A0-A9 with A10 defining Auto Precharge). A13
Row address use on x8 components only.
Input Chip Select: CS# enables (sampled LOW) and disables (sampled HIGH) the command decoder.
All commands are masked when CS# is sampled HIGH. CS# provides for external bank selection on systems with multiple banks. It is considered part of the command code.
RAS#
CAS#
WE#
DQS,
DQS#
RDQS
RDQS#
Input Row Address Strobe: The RAS# signal defines the operation commands in conjunction with the CAS# and WE# signals and is latched at the crossing of positive edges of CK and negative edge of CK#. When RAS# and CS# are asserted "LOW" and CAS# is asserted "HIGH," either the
BankActivate command or the Precharge command is selected by the WE# signal. When the
WE# is asserted "HIGH," the BankActivate command is selected and the bank designated by
BA is turned on to the active state. When the WE# is asserted "LOW," the Precharge command is selected and the bank designated by BA is switched to the idle state after the precharge operation.
Input Column Address Strobe: The CAS# signal defines the operation commands in conjunction with the RAS# and WE# signals and is latched at the crossing of positive edges of CK and negative edge of CK#. When RAS# is held "HIGH" and CS# is asserted "LOW," the column access is started by asserting CAS# "LOW." Then, the Read or Write command is selected by asserting WE# “HIGH " or “LOW".
Input Write Enable: The WE# signal defines the operation commands in conjunction with the RAS# and CAS# signals and is latched at the crossing of positive edges of CK and negative edge of
CK#. The WE# input is used to select the BankActivate or Precharge command and Read or
Write command.
Input /
Output
Bidirectional Data Strobe:
output with read data, input with write data. Edge aligned with read data, centered with write data. For the RDQS option using DM pin can be enabled via the EMR(1) to simplify read timing.The data strobes DQS and RDQS may be used in single ended mode or paired with the optional complementary signals DQS# and RDQS# to provide differential pair signaling to the system during both reads and writes. An EMRS(1) control bit enables or disables the complementary data strobe signals.
Alliance Memory Inc. 551 Taylor Way, San Carlos, CA 94070
TEL: (650) 610-6800 FAX: (650) 620-9211
Alliance Memory Inc. reserves the right to change products or specification without notice.
5 Rev. 1.0 June 2013
AS4C128M8D2
DM
DQ0 – DQ7
Input Data Input Mask: Input data is masked when DM is sampled HIGH during a write cycle. x8 device, the function of DM or RDQS/RQDS# is enabled by EMRS command.
Input /
Output
Data I/O: Bi-directional data bus.
ODT Input On Die Termination: ODT enables internal termination resistance. It is applied to each DQ,
DQS/DQS#, RDQS/RDQS# and DM signal. The ODT pin is ignored if the EMR (1) is programmed to disable ODT.
Supply Power Supply: +1.8V 0.1V V
DD
V
SS
V
DDL
V
V
SSDL
DDQ
Supply Ground
Supply DLL Power Supply: +1.8V 0.1V
Supply DLL Ground
Supply DQ Power: +1.8V 0.1V.
V
SSQ
V
REF
NC
Supply DQ Ground
Supply Reference Voltage for Inputs: +0.5*V
DDQ
- No Connect: These pins should be left unconnected.
Alliance Memory Inc. 551 Taylor Way, San Carlos, CA 94070
TEL: (650) 610-6800 FAX: (650) 620-9211
Alliance Memory Inc. reserves the right to change products or specification without notice.
6 Rev. 1.0 June 2013
AS4C128M8D2
Operation Mode
Table 4 shows the truth table for the operation commands.
Table 4. Truth Table (Note (1), (2))
Command
BankActivate
Single Bank Precharge
All Banks Precharge
Write
Write with AutoPrecharge
Read
Read and Autoprecharge
(Extended) Mode Register Set
No-Operation
Burst Stop
Device Deselect
Refresh
SelfRefresh Entry
SelfRefresh Exit
Power Down Mode Entry
Power Down Mode Exit
Data Input Mask Disable
State CKE n-1
CKE n
DM BA
0-2
A
10
A
0-9, 11-13
CS# RAS# CAS# WE#
Idle
(3)
H H X V Row address L L H H
Any H H X V L X L L H L
Any H
Active
(3)
H
Active (3) H
Active
Active
(3)
(3)
H
H
H
H
H
H
H
H
X
X
X
X
X
X
X
X
X
V
V
V
V
V
X
H
L
H
L
H
X
Column address
(A0 – A9)
Column address
(A0 – A9)
OP code
L
L
L
L
L
L
L
L
H
H
H
H
L
H
H
L
L
L
L
L
H
L
L
L
H
H
L
H
Idle H
Any H
Active
(4)
H
Any H
Idle
Idle
H
H
X
X
H
L
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
L
H
L
L
H
X
L
L
H
X
L
L
H
H
L
X
Idle
Idle
Any
Active
L
H
L
H
H
L
H
X
X
X
X
L
X
X
X
X
X
X
X
X
X
X
X
X
L
X
L
H
X
H
L
H
X
H
X
H
X
H
X
X
X
H
X
H
X
H
X
X
H
X
H
X
X
X
H
X
Data Input Mask Enable(5) Active H X H X X
NOTE 1:
V=Valid data, X=Don't Care, L=Low level, H=High level
NOTE 2:
CKEn signal is input level when commands are provided.
NOTE 3:
CKEn
-1
signal is input level one clock cycle before the commands are provided.
NOTE 4:
These are states of bank designated by BA signal.
NOTE 5:
Device state is 4, and 8 burst operation.
NOTE 6:
LDM and UDM can be enabled respectively.
X
Alliance Memory Inc. 551 Taylor Way, San Carlos, CA 94070
TEL: (650) 610-6800 FAX: (650) 620-9211
Alliance Memory Inc. reserves the right to change products or specification without notice.
7 Rev. 1.0 June 2013
AS4C128M8D2
Functional Description
Read and write accesses to the DDR2 SDRAM are burst oriented; accesses start at a selected location and continue for a burst length of four or eight in a programmed sequence. Accesses begin with the registration of an Active command, which is then followed by a Read or Write command. The address bits registered coincident with the active command are used to select the bank and row to be accessed (BA0-BA2 select the bank; A0-A13 select the row). The address bits registered coincident with the Read or Write command are used to select the starting column location for the burst access and to determine if the auto precharge command is to be issued.
Prior to normal operation, the DDR2 SDRAM must be initialized. The following sections provide detailed information covering device initialization, register definition, command descriptions, and device operation.
Power-up and Initialization
DDR2 SDRAMs must be powered up and initialized in a predefined manner. Operational procedures other than those specified may result in undefined operation.
The following sequence is required for POWER UP and Initialization.
1. Apply power and attempt to maintain CKE below 0.2*V
DDQ
and ODT
*1
at a low state (all other inputs may be undefined.)
The V
DD voltage ramp time must be no greater than 200ms from when V
DD
ramps from 300mV to V
DD min; and during the
V
DD voltage ramp, |V
DD
-V
DDQ
| ≦ 0.3V
- V
DD
, V
DDL
and V
DDQ
are driven from a single power converter output, AND
- V
TT
is limited to 0.95 V max, AND
- V
REF tracks V
DDQ
/2. or
- Apply V
DD
before or at the same time as V
DDL
.
- Apply V
DDL
before or at the same time as V
DDQ
.
- Apply V
DDQ
before or at the same time as V
TT
& V
REF
.
At least one of these two sets of conditions must be met.
2. Start clock and maintain stable condition.
3. For the minimum of 200 s after stable power and clock (CK, CK#), then apply NOP or deselect and take CKE HIGH.
4. Wait minimum of 400ns then issue precharge all command. NOP or deselect applied during 400ns period.
5. Issue EMRS(2) command. (To issue EMRS (2) command, provide “LOW” to BA0 and BA2, “HIGH” to BA1.)
6. Issue EMRS (3) command. (To issue EMRS (3) command, provide “LOW” to BA2, “HIGH” to BA0 and BA1.)
7. Issue EMRS to enable DLL. (To issue "DLL Enable" command, provide "LOW" to A0, "HIGH" to BA0 and "LOW" to BA1 and
BA2.)
8. Issue a Mode Register Set command for “DLL reset”.
(To issue DLL reset command, provide "HIGH" to A8 and "LOW" to BA0-BA2)
9. Issue precharge all command.
10. Issue 2 or more auto-refresh commands.
11. Issue a mode register set command with LOW to A8 to initialize device operation. (i.e. to program operating parameters without resetting the DLL.)
12. At least 200 clocks after step 8, execute OCD Calibration (Off Chip Driver impedance adjustment).If OCD calibration is not used, EMRS OCD Default command (A9=A8=A7=HIGH) followed by EMRS OCD calibration Mo de
Exit command
(A9=A8=A7=LOW) must be issued with other operating parameters of EMRS.
13. The DDR2 SDRAM is now ready for normal operation.
NOTE 1: To guarantee ODT off, V
REF
must be valid and a LOW level must be applied to the ODT pin.
Alliance Memory Inc. 551 Taylor Way, San Carlos, CA 94070
TEL: (650) 610-6800 FAX: (650) 620-9211
Alliance Memory Inc. reserves the right to change products or specification without notice.
8 Rev. 1.0 June 2013
AS4C128M8D2
Mode Register Set(MRS)
The mode register stores the data for controlling the various operating modes of DDR2 SDRAM. It controls CAS latency, burst length, burst sequence, test mode, DLL reset, WR, and various vendor specific options to make DDR2 SDRAM useful for various applications.The default value of the mode register is not defined, therefore the mode register must be programmed during initialization for proper operation. The mode register is written by asserting LOW on CS#, RAS#, CAS#,
WE#, BA0 and BA1, while controlling the state of address pins A0 - A13. The DDR2 SDRAM should be in all bank precharge state with CKE already HIGH prior to writing into the mode register.The mode register set command cycle time (t
MRD
) is required to complete the write operation to the mode register. The mode register contents can be changed using the same command and clock cycle requirements during normal operation as long as all bank are in the precharge state.The mode register is divided into various fields depending on functionality.
- Burst Length Field (A2, A1, A0) : This field specifies the data length of column access and selects the Burst Length.
- Addressing Mode Select Field (A3) : The Addressing Mode can be Interleave Mode or Sequential Mode. Both Sequential
Mode and Interleave Mode support burst length of 4 and 8.
- CAS Latency Field (A6, A5, A4) : This field specifies the number of clock cycles from the assertion of the Read command to
the first read data. The minimum whole value of CAS Latency depends on the frequency of CK. The minimum whole value satisfying the following formula must be programmed into this field.
(tCAC(min) ≦ CAS Latency X t
CK
)
- Test Mode Field (A7); DLL Reset Mode Field (A8) : These two bits must be programmed to "00" in normal operation.
- Write recovery Field (A11, A10, A9) : The WR register is used by the DDR2 SDRAM during WRITE with auto precharge operation. The WR register is used by the DDR2 SDRAM during WRITE with auto precharge operation.
- Active Power down Field (A12) : PD mode enables the user to determine the active power-down mode, which determines performance versus power savings. oes not apply to precharge PD mode.
- (BA0-BA1): Bank addresses to define MRS selection.
Table 5. Mode Register Bitmap
BA2 BA1 BA0 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 Address Field
0
*2
0 0 0
*2
PD
A8 DLL Reset
0 No
WR DLL TM CAS Latency
A7 Mode
0 Normal
A3
0
BT Burst Length Mode Register
Burst Type
Sequential
A2 A1 A0 BL
0 1 0 4
1 Yes 1 Test 1 Interleave 0 1 1 8
A12 Active power down exit time
0
1
Fast exit (use t
XARD
)
Slow exit (use t
XARDS
)
Write recovery for autoprecharge
A11 A10 A9
0 0 0
*1
WR(cycles) A6 A5 A4
Reserved 0 0 0
BA1 BA0 MRS Mode
0
0
0
1
1
0
2
3
0
0
0
1
1
0
CAS Latency
Reserved
Reserved
Reserved
0
0
0
1
MR
EMR(1)
0
1
1
0
1
0
4
5
0
1
1
0
1
0
3
4
1
1
0
1
EMR(2)
EMR(3)
1
1
0
1
1
0
6 1
Reserved
1
0
1
1
0
5
6
1 1 1
Reserved
1 1 1 Reserved
NOTE 1: For DDR2-800, WR min is determined by t
CK
(avg) max and WR max is determined by t
CK
(avg) min. WR [cycles] = RU
{t
WR
[ns]/t
CK
(avg)[ns]}, where RU stands for round up. The mode register must be programmed to this value.This is also used with t
RP
to determine t
DAL
.
NOTE 2: BA2 and A13 are reserved for future use and must be set to 0 when programming the MR.
Alliance Memory Inc. 551 Taylor Way, San Carlos, CA 94070
TEL: (650) 610-6800 FAX: (650) 620-9211
Alliance Memory Inc. reserves the right to change products or specification without notice.
9 Rev. 1.0 June 2013
AS4C128M8D2
Extended Mode Register Set (EMRS)
- EMR(1)
The extended mode register(1) stores the data for enabling or disabling the DLL, output driver strength, ODT value selection and additive latency. The default value of the extended mode register is not defined, therefore the extended mode register must be written after power-up for proper operation. The extended mode register is written by asserting
LOW on CS#, RAS#, CAS#, WE#, BA1 and HIGH on BA0, while controlling the states of address pins A0 ~ A13. The DDR2
SDRAM should be in all bank precharge with CKE already HIGH prior to writing into the extended mode register. The mode register set command cycle time (t
MRD
) must be satisfied to complete the write operation to the extended mode register.
Mode register contents can be changed using the same command and clock cycle requirements during normal operation as long as all banks are in the precharge state. A0 is used for DLL enable or disable. A1 is used for enabling a half strength data-output driver. A3~A5 determine the additive latency, A2 and A6 are used for ODT value selection, A7~A9 are used for
OCD control, A10 is used for DQS# disable and A11 is used for RDQS enable.
- DLL Enable/Disable
The DLL must be enabled for normal operation. DLL enable is required during power up initialization, and upon returning to normal operation after having the DLL disabled. The DLL is automatically disabled when entering self refresh operation and is automatically re-enabled upon exit of self refresh operation. Any time the DLL is enabled (and subsequently reset),
200 clock cycles must occur before a Read command can be issued to allow time for the internal clock to be synchronized with the external clock. Failing to wait for synchronization to occur may result in a violation of the t
AC
or t
DQSCK
parameters.
Table 6. Extended Mode Register EMR (1) Bitmap
BA2 BA1 BA0 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 Address Field
0
*3
0 1 0
*3
Qoff
RDQS DQS#
OCD program Rtt
Additive Latency
Rtt
D.I.C
DLL
Extended Mode Register
BA1 BA0
0 0
0
1
1
1
0
1
MRS mode
MR
EMR(1)
EMR(2)
EMR(3)
A6 A2 Rtt
(NOMINAL)
0 0 ODT Disable
0
1
1
1
0
1
75Ω
150Ω
50Ω
A0
0
1
DLL Enable
Enable
Disable
A9 A8 A7 OCD Calibration Program
0
0
0
1
1
0
0
1
0
1
0 OCD Calibration mode exit; maintain setting
1
Reserved
0
Reserved
0
Reserved
1
OCD Calibration default
*1
A1
0
1
A12
0
Qoff
*2
Output buffer enabled
0
0
0
0 A10
0
1
DQS#
Enable
Disable
1 Output buffer disabled
A11
0
RDQS Enable
*4
Disable
1
1
1
0
1
1 Enable 1
NOTE 1: After setting to default, OCD calibration mode needs to be exited by setting A9-A7 to 000.
1
1
0
0
0
1
Output Driver
Impedance Control
Full strength
Reduced strength
A5 A4 A3 Additive Latency
0
1
0
1
0
1
0
1
0
1
2
3
4
5
6
Reserved
Alliance Memory Inc. 551 Taylor Way, San Carlos, CA 94070
TEL: (650) 610-6800 FAX: (650) 620-9211
Alliance Memory Inc. reserves the right to change products or specification without notice.
10 Rev. 1.0 June 2013
AS4C128M8D2
NOTE 2: Output disabled – DQs, DQSs, DQSs#, RDQS, RDQS#. This feature is intended to be used during I
DD
characterization of read current.
NOTE 3: A13 and BA2 are reserved for future use and must be set to 0 when programming the MR.
NOTE 4: If RDQS is enabled, the DM function is disabled. RDQS is active for reads and do not care for writes.
Table 7. Extended Mode Register EMR (1) Bitmap
A11
(RDQS Enable)
0(Disable)
0(Disable)
1(Enable)
1(Enable)
A10
(DQS# Enable)
0(Enable)
1(Disable)
0(Enable)
1(Disable)
RDQS
/DM
DM
DM
RDQS
RDQS
RDQS#
Hi-z
Hi-z
RDQS#
Hi-z
DQS
DQS
DQS
DQS
DQS
DQS#
DQS#
Hi-z
DQS#
Hi-z
- EMR(2)
The extended mode register (2) controls refresh related features. The default value of the extended mode register (2) is not defined, therefore the extended mode register (2) must be written after power-up for proper operation. The extended mode register(2) is written by asserting LOW on CS#, RAS#, CAS#, WE#, HIGH on BA1 and LOW on BA0, while controlling the states of address pins A0 ~ A13. The DDR2 SDRAM should be in all bank precharge with CKE already HIGH prior to writing into the extended mode register (2). The mode register set command cycle time (t
MRD
) must be satisfied to complete the write operation to the extended mode register (2). Mode register contents can be changed using the same command and clock cycle requirements during normal operation as long as all banks are in the precharge state.
Table 8. Extended Mode Register EMR(2) Bitmap
BA2 BA1 BA0 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 Address Field
0
*3
1 0 0
*1
SRF
0
*1
Extended Mode Register(2)
A7
0
1
High Temperature Self-Refresh Rate Enable
Disable
Enable
*2
NOTE 1: The rest bits in EMRS(2) are reserved for future use and all bits in EMRS(2) except A7, BA0 and BA1 must be programmed to 0 when setting the extended mode register(2) during initialization.
NOTE 2: Due to the migration nature, user needs to ensure the DRAM part supports higher than 85℃ Tcase temperature self-refresh entry. If the high temperature self-refresh mode is supported then controller can set the EMRS2[A7] bit to enable the selfrefresh rate in case of higher than 85℃ temperature self-refresh operation.
NOTE 3: BA2 is reserved for future use and must be set to 0 when programming the MR.
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- EMR(3)
No function is defined in extended mode register(3).The default value of the extended mode register(3) is not defined, therefore the extended mode register(3) must be programmed during initialization for proper operation.
Table 9. Extended Mode Register EMR (3) Bitmap
BA2 BA1 BA0 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 Address Field
0
*1
1 1 0
*1
Extended Mode Register(3)
NOTE 1: All bits in EMR (3) except BA0 and BA1 are reserved for future use and must be set to 0 when programming the
EMR (3).
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ODT (On Die Termination)
On Die Termination (ODT) is a feature that allows a DRAM to turn on/off termination resistance for each DQ, DQS/DQS#,
RDQS/RDQS#, DM signal via the ODT control pin. The ODT feature is designed to improve signal integrity of the memory channel by allowing the DRAM controller to independently turn on/off termination resistance for any or all DRAM devices.
The ODT function is supported for ACTIVE and STANDBY modes. It is turned off and not supported in SELF REFRESH mode.
Figure 4. Functional representation of ODT
V
DDQ
V
DDQ
V
DDQ
SW1
SW2 SW3
Rval1 Rval2
DRAM
Input
Buffer
Rval1 Rval2
Rval3
Input pin
Rval3
SW1
SW2 SW3
V
SSQ
V
SSQ
V
SSQ
Switch (sw1, sw2, sw3) is enabled by ODT pin.
Selection among sw1, sw2, and sw3 is determined by “Rtt (nominal)” in EMR.
Termination included on all DQs, DM, DQS, DQS#, RDQS and RDQS# pins
Table 10. ODT DC Electrical Characteristics
Parameter/Condition Symbol Min. Nom.
Rtt effective impedance value for EMRS(A6,A2)=0,1;75Ω
Rtt effective impedance value for EMRS(A6,A2)=1,0;150Ω
Rtt effective impedance value for EMRS(A6,A2)=1,1;50Ω
Rtt mismatch tolerance between any pull-up/pull-down pair
NOTE 1: Measurement Definition for Rtt(eff):
Rtt1(eff)
Rtt2(eff)
Rtt3(eff)
Rtt(mis)
60
120
40
-6
75
150
50
-
90
180
60
6
Apply V
IH
(ac) and V
IL
(ac) to test pin seperately, then measure current I(V
IH
(ac)) and I(V
IL
(ac)) respectively.
Rtt(eff)=
IH
( )
V ac
Ω
Ω
Ω
%
IL
NOTE 2: Measurement Defintion for Rtt (mis): Measure voltage (VM) at test pin (midpoint) with no load.
Rtt(mis)=
2xVM
V
DDQ
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Max. Unit Note
1
1
1
2
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Bank activate command
The Bank Activate command is issued by holding CAS# and WE# HIGH with CS# and RAS# LOW at the rising edge of the clock.
The bank addresses BA0-BA2 are used to select the desired bank. The row addresses A0 through A13 are used to determine which row to activate in the selected bank. The Bank Activate command must be applied before any Read or Write operation can be executed. Immediately after the bank active command, the DDR2 SDRAM can accept a read or write command (with or without Auto-Precharge) on the following clock cycle. If a R/W command is issued to a bank that has not satisfied the t
RCD min specification, then additive latency must be programmed into the device to delay the R/W command which is internally issued to the device. The additive latency value must be chosen to assure t
RCD min is satisfied. Additive latencies of 0,
1, 2, 3, and 4 are supported. Once a bank has been activated it must be precharged before another Bank Activate command can be applied to the same bank. The bank active and precharge times are defined as t
RAS
and t
RP
, respectively. The minimum time interval between successive Bank Activate commands to the same bank is determined (t
RC
). The minimum time interval between Bank Active commands is t
RRD
In order to ensure that 8 bank devices do not exceed the instantaneous current supplying capability of 4 bank devices, certain restrictions on operation of the 8 bank devices must be observed. There are two rules. One for restricting the number of sequential ACT commands that can be issued and another for allowing more time for RAS precharge for a Precharge All command. The rules are as follows:
- 8 bank device Sequential Bank Activation Restriction : No more than 4 banks may be activated in a rolling t
FAW
window.
Converting to clocks is done by dividing t
FAW
[ns] by t
CK
[ns] or t
CK
[ns], depending on the speed bin, and rounding up to next integer value. As an example of the rolling window, if RU{ (t
FAW
/ t
CK
) } or RU{ (t
FAW
/ t
CK
)} is 10 clocks, and an activate command is issued in clock N, no more than three further activate commands may be issued at or between clock N+1 and
N+9.
- 8 bank device Precharge All Allowance : t
RP
for a Precharge All command for an 8 Bank device will equal to t
RP
+ 1 x t
CK or t
RP
+ 1 x t
CK
, depending on the speed bin, where t
RP
= RU{ t
RP
/ t
CK
} and t
RP
is the value for a single bank precharge.
Read and Write access modes
After a bank has been activated, a Read or Write cycle can be executed. This is accomplished by setting RAS# HIGH, CS# and
CAS# LOW at the clock’s rising edge. WE# must also be defined at this time to determine whether the access cycle is a Read operation (WE# HIGH) or a Write operation (WE# LOW). The DDR2 SDRAM provides a fast column access operation. A single
Read or Write Command will initiate a serial Read or Write operation on successive clock cycles. The boundary of the burst cycle is strictly restricted to specific segments of the page length. Any system or application incorporating random access memory products should be properly designed, tested, and qualified to ensure proper use or access of such memory products. Disproportionate, excessive, and/or repeated access to a particular address or addresses may result in reduction of product life.
Posted CAS#
Posted CAS# operation is supported to make command and data bus efficient for sustainable bandwidths in DDR2 SDRAM. In this operation, the DDR2 SDRAM allows a CAS# Read or Write command to be issued immediately after the RAS bank activate command (or any time during the RAS# -CAS#-delay time, t
RCD
, period). The command is held for the time of the Additive
Latency (AL) before it is issued inside the device. The Read Latency (RL) is controlled by the sum of AL and the CAS latency
(CL). Therefore if a user chooses to issue a R/W command before the t
RCD min, then AL (greater than 0) must be written into the EMR(1). The Write Latency (WL) is always defined as RL - 1 (Read Latency -1) where Read Latency is defined as the sum of additive latency plus CAS latency (RL=AL+CL). Read or Write operations using AL allow seamless bursts (refer to seamless operation timing diagram examples in Read burst and Write burst section)
Burst Mode Operation
Burst mode operation is used to provide a constant flow of data to memory locations (Write cycle), or from memory locations
(Read cycle). The parameters that define how the burst mode will operate are burst sequence and burst length. The DDR2
SDRAM supports 4 bit and 8 bit burst modes only. For 8 bit burst mode, full interleave address ordering is supported, however, sequential address ordering is nibble based for ease of implementation. The burst length is programmable and defined by the addresses A0 ~ A2 of the MRS. The burst type, either sequential or interleaved, is programmable and defined by the address bit 3 (A3) of the MRS. Seamless burst Read or Write operations are supported. Interruption of a burst Read or
Write operation is prohibited, when burst length = 4 is programmed. For burst interruption of a Read or Write burst when
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burst length = 8 is used, see the “Burst Interruption“ section of this datasheet. A Burst Stop command is not supported on
DDR2 SDRAM devices.
Table 11. Burst Definition, Addressing Sequence of Sequential and Interleave Mode
Burst Length
4
8
0
1
1
1
1
X
0
0
0
A2
Start Address
A1 A0
X
X
X
0
0
1
0
1
0
1
0
0
1
1
0
0
1
1
1
0
1
0
1
1
0
1
0
Burst read command
Sequential
0, 1, 2, 3
1, 2, 3, 0
2, 3, 0, 1
3, 0, 1, 2
0, 1, 2, 3, 4, 5, 6, 7
1, 2, 3, 0, 5, 6, 7, 4
2, 3, 0, 1, 6, 7, 4, 5
3, 0, 1, 2, 7, 4, 5, 6
4, 5, 6, 7, 0, 1, 2, 3
5, 6, 7, 4, 1, 2, 3, 0
6, 7, 4, 5, 2, 3, 0, 1
7, 4, 5, 6, 3, 0, 1, 2
Interleave
0, 1, 2, 3
1, 0, 3, 2
2, 3, 0, 1
3, 2, 1, 0
0, 1, 2, 3, 4, 5, 6, 7
1, 0, 3, 2, 5, 4, 7, 6
2, 3, 0, 1, 6, 7, 4, 5
3, 2, 1, 0, 7, 6, 5, 4
4, 5, 6, 7, 0, 1, 2, 3
5, 4, 7, 6, 1, 0, 3, 2
6, 7, 4, 5, 2, 3, 0, 1
7, 6, 5, 4, 3, 2, 1, 0
The Burst Read command is initiated by having CS# and CAS# LOW while holding RAS# and WE# HIGH at the rising edge of the clock. The address inputs determine the starting column address for the burst. The delay from the start of the command to when the data from the first cell appears on the outputs is equal to the value of the Read Latency (RL). The data strobe output (DQS) is driven LOW 1 clock cycle before valid data (DQ) is driven onto the data bus. The first bit of the burst is synchronized with the rising edge of the data strobe (DQS). Each subsequent data-out appears on the DQ pin in phase with the DQS signal in a source synchronous manner. The RL is equal to an additive latency (AL) plus CAS Latency
(CL). The CL is defined by the Mode Register Set (MRS), similar to the existing SDR and DDR SDRAMs. The AL is defined by the Extended Mode Register Set (1) (EMRS (1)).
DDR2 SDRAM pin timings are specified for either single ended mode or differential mode depending on the setting of the
EMRS “Enable DQS” mode bit; timing advantages of differential mode are realized in system design. The method by which the DDR2 SDRAM pin timings are measured is mode dependent. In single ended mode, timing relationships are measured relative to the rising or falling edges of DQS crossing at V
REF
. In differential mode, these timing relationships are measured relative to the crosspoint of DQS and its complement, DQS#. This distinction in timing methods is guaranteed by design and characterization. Note that when differential data strobe mode is disabled via the EMRS, the complementary pin,
DQS#, must be tied externally to V
SS
through a 20 Ω to 10 KΩ resistor to insure proper operation.
Burst write operation
The Burst Write command is initiated by having CS#, CAS# and WE# LOW while holding RAS# HIGH at the rising edge of the clock. The address inputs determine the starting column address. Write latency (WL) is defined by a Read latency (RL) minus one and is equal to (AL + CL -1);and is the number of clocks of delay that are required from the time the Write command is registered to the clock edge associated to the first DQS strobe. A data strobe signal (DQS) should be driven
LOW (preamble) one clock prior to the WL. The first data bit of the burst cycle must be applied to the DQ pins at the first rising edge of the DQS following the preamble. The t
DQSS
specification must be satisfied for each positive DQS transition to its associated clock edge during write cycles.
The subsequent burst bit data are issued on successive edges of the DQS until the burst length is completed, which is 4 or 8 bit burst. When the burst has finished, any additional data supplied to the DQ pins will be ignored. The DQ Signal is ignored after the burst write operation is complete. The time from the completion of the burst Write to bank precharge is the write recovery time (WR). DDR2 SDRAM pin timings are specified for either single ended mode or differential mode depending on the setting of the EMRS “Enable DQS” mode bit; timing advantages of differential mode are realized in system design.
The method by which the DDR2 SDRAM pin timings are measured is mode dependent.
In single ended mode, timing relationships are measured relative to the rising or falling edges of DQS crossing at the specified AC/DC levels. In differential mode, these timing relationships are measured relative to the crosspoint of DQS and
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its complement, DQS#. This distinction in timing methods is guaranteed by design and characterization. Note that when differential data strobe mode is disabled via the EMRS, the complementary pin, DQS#, must be tied externally to V
SS through a 20Ω to 10KΩ resistor to insure proper operation.
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Write data mask
One Write data mask (DM) pin for each 8 data bits (DQ) will be supported on DDR2 SDRAMs, Consistent with the implementation on DDR SDRAMs. It has identical timings on Write operations as the data bits, and though used in a unidirectional manner, is internally loaded identically to data bits to insure matched system timing. DM is not used during read cycles.
Precharge operation
The Precharge command is used to precharge or close a bank that has been activated. The Precharge Command is triggered when CS#, RAS# and WE# are LOW and CAS# is HIGH at the rising edge of the clock. The Precharge Command can be used to precharge each bank independently or all banks simultaneously. Three address bits A10, BA2, BA1, and BA0 are used to define which bank to precharge when the command is issued.
Table 12. Bank Selection for Precharge by address bits
A10
LOW
LOW
LOW
LOW
LOW
LOW
LOW
BA2
LOW
LOW
LOW
LOW
HIGH
HIGH
HIGH
BA1
LOW
LOW
HIGH
HIGH
LOW
LOW
HIGH
BA0
LOW
HIGH
LOW
HIGH
LOW
HIGH
LOW
Precharged Bank(s)
Bank 0 only
Bank 1 only
Bank 2 only
Bank 3 only
Bank 4 only
Bank 5 only
Bank 6 only
LOW HIGH HIGH HIGH Bank 7 only
HIGH DON’T CARE DON’T CARE DON’T CARE
Burst read operation followed by precharge
ALL Banks
Minimum Read to precharge command spacing to the same bank = AL + BL/2 + max (RTP, 2) - 2 clocks. For the earliest possible precharge, the precharge command may be issued on the rising edge which “Additive latency (AL) + BL/2 clocks” after a Read command. A new bank active (command) may be issued to the same bank after the RAS# precharge time (t
RP
).
A precharge command cannot be issued until t
RAS
is satisfied.
The minimum Read to Precharge spacing has also to satisfy a minimum analog time from the rising clock edge that initiates the last 4-bit prefetch of a Read to Precharge command. This time is called t
RTP
(Read to Precharge). For BL = 4 this is the time from the actual read (AL after the Read command) to Precharge command. For BL = 8 this is the time from AL + 2 clocks after the Read to the Precharge command.
Burst Write operation followed by precharge
Minimum Write to Precharge command spacing to the same bank = WL + BL/2 + t
WR
. For write cycles, a delay must be satisfied from the completion of the last burst write cycle until the Precharge command can be issued. This delay is known as a write recovery time (t
WR
) referenced from the completion of the burst write to the Precharge command. No Precharge command should be issued prior to the t
WR
delay, as DDR2 SDRAM does not support any burst interrupt by a Precharge command. t
WR
is an analog timing parameter and is not the programmed value for t
WR
in the MRS.
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Auto precharge operation
Before a new row in an active bank can be opened, the active bank must be precharged using either the Precharge
Command or the auto-precharge function. When a Read or a Write Command is given to the DDR2 SDRAM, the CAS# timing accepts one extra address, column address A10, to allow the active bank to automatically begin precharge at the earliest possible moment during the burst read or write cycle. If A10 is LOW when the READ or WRITE Command is issued, then normal Read or Write burst operation is executed and the bank remains active at the completion of the burst sequence. If A10 is HIGH when the Read or Write Command is issued, then the auto-precharge function is engaged. During auto-precharge, a Read Command will execute as normal with the exception that the active bank will begin to precharge on the rising edge which is CAS latency (CL) clock cycles before the end of the read burst. Auto-precharge also be implemented during Write commands. The precharge operation engaged by the Auto precharge command will not begin until the last data of the burst write sequence is properly stored in the memory array. This feature allows the precharge operation to be partially or completely hidden during burst Read cycles (dependent upon CAS latency) thus improving system performance for random data access. The RAS# lockout circuit internally delays the Precharge operation until the array restore operation has been completed (t
RAS
satisfied) so that the auto precharge command may be issued with any
Read or Write command.
Burst read with auto precharge
If A10 is HIGH when a Read Command is issued, the Read with Auto-Precharge function is engaged. The DDR2 SDRAM starts an Auto-Precharge operation on the rising edge which is (AL + BL/2) cycles later from the Read with AP command if t
RAS
(min) and t
RTP
are satisfied. If t
RAS
(min) is not satisfied at the edge, the start point of Auto-Precharge operation will be delayed until t
RAS
(min) is satisfied. If t
RTP
(min) is not satisfied at the edge, the start point of Auto-precharge operation will be delayed until t
RTP
(min) is satisfied.
In case the internal precharge is pushed out by t
RTP
, t
RP
starts at the point where the internal precharge happens (not at the next rising clock edge after this event). So for BL = 4 the minimum time from Read with Auto-Precharge to the next
Activate command becomes AL + t
RTP
+ t
RP
. For BL = 8 the time from Read with Auto-Precharge to the next Activate command is AL + 2 + t
RTP
+ t
RP
. Note that both parameters t
RTP
and t
RP
have to be rounded up to the next integer value. In any event internal precharge does not start earlier than two clocks after the last 4-bit prefetch.
A new bank active (command) may be issued to the same bank if the following two conditions are satisfied simultaneously:
(1) The RAS# precharge time (t
RP
) has been satisfied from the clock at which the Auto-Precharge begins.
(2) The RAS# cycle time (t
RC
) from the previous bank activation has been satisfied.
Burst write with auto precharge
If A10 is HIGH when a Write Command is issued, the Write with Auto-Precharge function is engaged. The DDR2 SDRAM automatically begins precharge operation after the completion of the burst write plus Write recovery time (t
WR
). The bank undergoing auto-precharge from the completion of the write burst may be reactivated if the following two conditions are satisfied.
(1) The data-in to bank activate delay time (WR + t
RP
) has been satisfied.
(2) The RAS# cycle time (t
RC
) from the previous bank activation has been satisfied.
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Table 13. Precharge & Auto Precharge Clariification
From Command
Read
Read w/AP
Write
Write w/AP
Precharge
To Command
Precharge (to same Bank as Read)
Precharge All
Precharge (to same Bank as Read w/AP)
Precharge All
Precharge (to same Bank as Write)
Precharge All
Precharge (to same Bank as Write w/AP)
Precharge All
Precharge (to same Bank as Precharge)
Precharge All
Minimum Delay between “From Command” to “To Command”
Unit Note
AL+BL/2+max(RTP,2)-2
AL+BL/2+max(RTP,2)-2 t
CK
1,2
AL+BL/2+max(RTP,2)-2
AL+BL/2+max(RTP,2)-2
WL+BL/2+t
WR
WL+BL/2+t
WR
WL+BL/2+t
WR
WL+BL/2+t
WR
1
1 t t t t
CK
CK
CK
CK
1,2
2
2
2
Precharge All
Precharge
Precharge All
1
1 t
CK
2
NOTE 1: RTP [cycles] =RU {t
RTP
[ns]/t
CK
(avg) [ns]}, where RU stands for round up.
NOTE 2: For a given bank, the precharge period should be counted from the latest precharge command, either one bank precharge or precharge all, issued to that bank.The prechrage period is satisfied after t
RP
or t
RP all(=t
RP
for 8 bank device +
1X t
CK
) depending on the latest precharge command issued to that bank.
Refresh command
When CS#, RAS# and CAS# are held LOW and WE# HIGH at the rising edge of the clock, the chip enters the Refresh mode
(REF). All banks of the DDR2 SDRAM must be precharged and idle for a minimum of the Precharge time (t
RP
) before the
Refresh command (REF) can be applied. An address counter, internal to the device, supplies the bank address during the refresh cycle. No control of the external address bus is required once this cycle has started.
When the refresh cycle has completed, all banks of the DDR2 SDRAM will be in the precharged (idle) state. A delay between the Refresh command (REF) and the next Activate command or subsequent Refresh command must be greater than or equal to the Refresh cycle time (t
RFC
).To allow for improved efficiency in scheduling and switching between tasks, some flexibility in the absolute refresh interval is provided. A maximum of eight Refresh commands can be posted to any given DDR2 SDRAM, meaning that the maximum absolute interval between any Refresh command and the next Refresh command is 9 * t
REFI
.
Self refresh operation
The Self Refresh command can be used to retain data in the DDR2 SDRAM, even if the rest of the system is powered down.
When in the Self Refresh mode, the DDR2 SDRAM retains data without external clocking. The DDR2 SDRAM device has a built-in timer to accommodate Self Refresh operation. The Self Refresh Command is defined by having CS#, RAS#, CAS# and
CKE# held LOW with WE# HIGH at the rising edge of the clock. ODT must be turned off before issuing Self Refresh command, by either driving ODT pin LOW or using EMRS command. Once the Command is registered, CKE must be held
LOW to keep the device in Self Refresh mode. The DLL is automatically disabled upon entering Self Refresh and is automatically enabled upon exiting Self Refresh. When the DDR2 SDRAM has entered Self Refresh mode all of the external signals except CKE, are “don’t care”. For proper Self Refresh operation all power supply pins (V
DD
, V
DDQ
, V
DDL
and V
REF
) must be at valid levels. The DRAM initiates a minimum of one refresh command internally within t
CKE
period once it enters Self
Refresh mode. The clock is internally disabled during Self Refresh Operation to save power. The minimum time that the
DDR2 SDRAM must remain in Self Refresh mode is t
CKE
. The user may change the external clock frequency or halt the external clock one clock after Self Refresh entry is registered, however, the clock must be restarted and stable before the device can exit Self Refresh operation.
The procedure for exiting Self Refresh requires a sequence of commands. First, the clock must be stable prior to CKE going back HIGH. Once Self Refresh Exit is registered, a delay of at least t
XSNR
must be satisfied before a valid command can be issued to the device to allow for any internal refresh in progress. CKE must remain HIGH for the entire Self Refresh exit period t
XSRD
for proper operation except for Self Refresh re-entry. Upon exit from Self Refresh, the DDR2 SDRAM can be put back into Self Refresh mode after waiting at least t
XSNR
period and issuing one refresh command(refresh period of t
RFC
).
NOP or Deselect commands must be registered on each positive clock edge during the Self Refresh exit interval t
XSNR
. ODT
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should be turned off during t
XSRD
. The use of Self Refresh mode introduces the possibility that an internally timed refresh event can be missed when CKE is raised for exit from Self Refresh mode. Upon exit from Self Refresh, the DDR2 SDRAM requires a minimum of one extra auto refresh command before it is put back into Self Refresh mode.
Power-Down
Power-down is synchronously entered when CKE is registered LOW along with NOP or Deselect command. No read or write operation may be in progress when CKE goes LOW. These operations are any of the following: read burst or write burst and recovery. CKE is allowed to go LOW while any of other operations such as row activation, precharge or autoprecharge, mode register or extended mode register command time, or autorefresh is in progress.
The DLL should be in a locked state when power-down is entered. Otherwise DLL should be reset after exiting power-down mode for proper read operation.
If power-down occurs when all banks are precharged, this mode is referred to as Precharge Power-down; if power-down occurs when there is a row active in any bank, this mode is referred to as Active Power-down. For Active Power-down two different power saving modes can be selected within the MRS register, address bit A12. When A12 is set to “LOW” this mode is referred as “standard active power-down mode” and a fast power-down exit timing defined by the t
XARD
timing parameter can be used. When A12 is set to “HIGH” this mode is referred as a power saving “LOW power active powerdown mode”. This mode takes longer to exit from the power-down mode and the t
XARDS
timing parameter has to be satisfied. Entering power-down deactivates the input and output buffers, excluding CK, CK#, ODT and CKE. Also the DLL is disabled upon entering precharge power-down or slow exit active power-down, but the DLL is kept enabled during fast exit active power-down. In power-down mode, CKE LOW and a stable clock signal must be maintained at the inputs of the
DDR2 SDRAM, and all other input signals are “Don’t Care”. Power-down duration is limited by 9 times t
REFI
of the device.
The power-down state is synchronously exited when CKE is registered HIGH (along with a NOP or Deselect command). A valid, executable command can be applied with power-down exit latency, t
XP
, t
XARD
or t
XARDS
, after CKE goes HIGH. Powerdown exit latencies are defined in the AC spec table of this data sheet.
Asynchronous CKE LOW Event
DRAM requires CKE to be maintained “HIGH” for all valid operations as defined in this datasheet. If CKE asynchronously drops “LOW” during any valid peration DRAM is not guaranteed to preserve the contents of array. If this event occurs, memory controller must satisfy DRAM timing specification tDelay efore turning off the clocks. Stable clocks must exist at the input of DRAM before CKE is raised “HIGH” again. DRAM must be fully re-initialized. DRAM is ready for normal operation after the initialization sequence.
Input clock frequency change during precharge power down
DDR2 SDRAM input clock frequency can be changed under following condition: DDR2 SDRAM is in precharged power down mode. ODT must be turned off and CKE must be at logic LOW level. A minimum of 2 clocks must be waited after CKE goes
LOW before clock frequency may change. SDRAM input clock frequency is allowed to change only within minimum and maximum operating frequency specified for the particular speed grade. During input clock frequency change, ODT and CKE must be held at stable LOW levels. Once input clock frequency is changed, stable new clocks must be provided to DRAM before precharge power down may be exited and DLL must be RESET via EMRS after precharge power down exit.
Depending on new clock frequency an additional MRS command may need to be issued to appropriately set the WR, CL etc.
During DLL re-lock period, ODT must remain off. After the DLL lock time, the DRAM is ready to operate with new clock frequency.
No operation command
The No Operation Command should be used in cases when the DDR2 SDRAM is in an idle or a wait state. The purpose of the No Operation Command (NOP) is to prevent the DDR2 SDRAM from registering any unwanted commands between operations. A No Operation Command is registered when CS# is LOW with RAS#, CAS#, and WE# held HIGH at the rising edge of the clock. A No Operation Command will not terminate a previous operation that is still executing, such as a burst read or write cycle.
Deselect command
The Deselect Command performs the same function as a No Operation Command. Deselect Command occurs when CS# is brought HIGH at the rising edge of the clock, the RAS#, CAS#, and WE# signals become don’t cares.
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Table 14. Absolute Maximum DC Ratings
Symbol Parameter Rating Unit Note
V
DD
Voltage on V
DD pin relative to Vss
V
DDQ
Voltage on V
DDQ pin relative to Vss
V
DDL
Voltage on V
DDL pin relative to Vss
V
IN
, V
OUT
Voltage on any pin relative to Vss
-1.0 ~ 2.3
-0.5 ~ 2.3
-0.5 ~ 2.3
- 0.5 ~ 2.3
V
V
V
V
1,3
1,3
1,3
1,4
T
STG
Storage temperature - 55~100 °C 1,2
NOTE1: Stress greater than those listed under “Absolute Maximum Ratings” may cause permanent damage to the devices.
This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.
NOTE2: Storage temperature is the case temperature on the center/top side of the DRAM.
NOTE3: When V
DD
and V
DDQ
and V
DDL
are less than 500mV, Vref may be equal to or less than 300mV.
NOTE4: Voltage on any input or I/O may not exceed voltage on V
DDQ
.
T
able 15. Operating Temperature Condition
Symbol Parameter Rating Unit Note
Commercial 0~85 °C 1, 2
T
OPER
Operating temperature
Industrial -40~95 °C 1, 2
NOTE1: Operating temperature is the case surface temperature on center/top of the DRAM.
NOTE2: When T
OPER
exceeds 85℃, it is required to set 3.9us tREFI in auto refresh mode or to set ‘1’ for EMRS(2) bit A7 in self refresh mode.
Table 16. Recommended DC Operating Conditions (SSTL_1.8)
Symbol Parameter
V
DD
Power supply voltage
V
DDL
Power supply voltage for DLL
V
DDQ
Power supply voltage for I/O Buffer
V
REF
Input reference voltage
Min.
1.7
1.7
1.7
0.49 x V
DDQ
Typ.
1.8
1.8
1.8
0.5 x V
DDQ
Max.
1.9
1.9
1.9
0.51 x V
DDQ
Unit Note
V
V
1
5
V 1,5 mV 2,3
V
TT
Termination voltage V
REF
- 0.04 V
REF
V
REF
+ 0.04 V 4
NOTE1: There is no specific device VDD supply voltage requirement for SSTL_18 compliance. However under all conditions
V
DDQ
must be less than or equal to V
DD.
NOTE2: The value of V
REF
may be selected by the user to provide optimum noise margin in the system. Typically the value of
V
REF
is expected to be about 0.5 x V
DDQ
of the transmitting device and V
REF
is expected to track variations in V
DDQ
.
NOTE3: Peak to peak ac noise on V
REF
may not exceed ±2 % V
REF
(dc).
NOTE4: V
TT
of transmitting device must track V
REF
of receiving device.
NOTE5: V
DDQ
tracks with V
DD
, V
DDL
tracks with V
DD
. AC parameters are measured with V
DD
, V
DDQ
and V
DDL
tied together
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AS4C128M8D2
Table 17. Input logic level (
V
DD
= 1.8V 0.1V, T
OPER
= -40~95 C)
Symbol Parameter
V
IH
(DC) DC Input logic High Voltage
V
IL
(DC) DC Input Low Voltage
V
IH
(AC) AC Input High Voltage
V
IL
(AC) AC Input Low Voltage
V
ID
(AC) AC Differential Voltage
Min.
V
REF
+ 0.125
-0.3
V
REF
+ 0.2
Vss
Q
–V
PEAK
0.5
-25
Max.
V
DDQ
+ 0.3
V
REF
- 0.125
V
DDQ
+V
PEAK
V
REF
– 0.2
V
DDQ
+ 0.6
Unit
V
V
V
V
V
V
IX
(AC) AC Differential crosspoint Voltage 0.5 x V
DDQ
-0.175 0.5 x V
DDQ
+0.175 V
NOTE1: Refer to Overshoot/undershoot specification for V peak
value: maximum peak amplitude allowed for overshoot and undershoot.
Table 18. AC Input test conditions
(V
DD
= 1.8V 0.1V, T
OPER
= -40~95 C)
Symbol Parameter
V
REF
Input reference voltage
V
SWING(max)
Input signal maximum peak to peak swing
-25
0.5 x V
DDQ
1.0
Unit Note
V 1
V 1
Slew Rate Input signal minimum slew rate 1.0 V/ns 2, 3
NOTE1: Input waveform timing is referenced to the input signal crossing through the V
IH
/
IL
(ac) level applied to the device under test.
NOTE2: The input signal minimum slew rate is to be maintained over the range from V
REF
to V
IH
(ac) min for rising edges and the range from V
REF
to V
IL
(ac) max for falling edges .
NOTE3: AC timings are referenced with input waveforms switching from V
IL
(ac) to V
IH
(ac) on the positive transitions and V
IH
(ac) to V
IL
(ac) on the negative transitions.
Table 19. Differential AC output parameters
(V
DD
= 1.8V 0.1V, T
OPER
= -40~95 C)
-25
Symbol Parameter Unit Note
Min. Max.
V ox(ac)
AC Differential Cross Point Voltage 0.5xV
DDQ
-0.125 0.5xV
DDQ
+0.125 V
NOTE1: The typical value of V
OX
(ac) is expected to be about 0.5 x V
DDQ of the transmitting device and V
OX
(ac) is expected to track variations in V
DDQ
. V
OX
(ac) indicates the voltage at which differential output signals must cross.
1
Table 20. AC overshoot/undershoot specification for address and control pins
(A0-A12, BA0-BA2, CS#, RAS#, CAS#, WE#, CKE, ODT)
Parameter
Maximum peak amplitude allowed for overshoot area
Maximum peak amplitude allowed for undershoot area
Maximum overshoot area above V
DD
Maximum undershoot area below V
SS
-25
0.5
0.5
0.66
0.66
Unit
V
V
V-ns
V-ns
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Table 21. AC overshoot/undershoot specification for clock, data, strobe, and mask pins
(DQ, DQS, DQS#, DM, CK, CK#)
Parameter
Maximum peak amplitude allowed for overshoot area
Maximum peak amplitude allowed for undershoot area
Maximum overshoot area above V
DD
Maximum undershoot area below V
SS
Table 22. Output AC test conditions (
V
DD
= 1.8V 0.1V, T
OPER
= -40~95 C)
-25
0.5
0.5
0.23
0.23
Unit
V
V
V-ns
V-ns
Symbol Parameter
V
OTR
Output timing measurement reference level
NOTE1: The V
DDQ
of the device under test is referenced.
Table 23. Output DC current drive
(V
DD
= 1.8V 0.1V, T
OPER
= -40~95 C)
-25
0.5xV
DDQ
Unit Note
V 1
Symbol Parameter -25 Unit Note
I
OH
(dc) Output minimum source DC current -13.4 mA 1, 3, 4
I
OL
(dc) Output minimum sink DC current 13.4 mA 2, 3, 4
NOTE1: V
DDQ
= 1.7 V; V
OUT
= 1420 mV. (V
OUT
- V
DDQ
) /I
OH
must be less than 21 Ω for values of V
OUT
between V
DDQ and V
DDQ
- 280 mV.
NOTE2: V
DDQ
= 1.7 V; V
OUT
= 280 mV. V
OUT
/I
OL
must be less than 21 Ω for values of V
OUT
between 0 V and 280 mV.
NOTE3: The dc value of V
REF
applied to the receiving device is set to V
TT
NOTE4: The values of I
OH
(dc) and I
OL
(dc) are based on the conditions given in Notes 1 and 2. They are used to test device drive current capability to ensure V
IH
min plus a noise margin and VIL max minus a noise margin are delivered to an
SSTL_18 receiver. The actual current values are derived by shifting the desired driver operating point (see JEDEC standard: Section 3.3 of JESD8-15A) along a 21 Ω load line to define a convenient driver current for measurement.
Table 24. Capacitance
(V
DD
= 1.8V, f = 1MHz, T
OPER
= 25 C)
Symbol
C
IN
C
CK
C
I/O
Parameter
Input Capacitance : Command and Address
Input Capacitance (CK, CK#)
DM, DQ, DQS Input/Output Capacitance
Min.
1.0
1.0
2.5
DDR2-800
Max.
1.75
2.0
3.5
Delta
0.25
0.25
0.5
Unit
pF pF pF
NOTE: These parameters are periodically sampled and are not 100% tested.
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Table 25. IDD specification parameters and test conditions
(V
DD
= 1.8V 0.1V, T
OPER
= -40~95 C)
Parameter & Test Condition Symbol
-25
Max.
Unit
Operating one bank active-precharge current:
t
CK
=t
CK
(min), t
RC
= t
RC
(min), t
RAS
= t
RAS
(min); CKE is HIGH, CS# is HIGH between valid commands; Address bus inputs are SWITCHING; Data bus inputs are
SWITCHING
Operating one bank active-read-precharge current:
I
OUT
= 0mA; BL = 4, CL = CL (min), AL = 0; t
CK
= t
CK
(min),t
RC
= t
RC
(min), t
RAS
= t
RAS
(min), t
RCD
= t
RCD
(min);CKE is HIGH, CS# is HIGH between valid commands;Address bus inputs are switching; Data pattern is same as I
DD4W
Precharge power-down current:
All banks idle;t
CK
=t
CK
(min); CKE is LOW; Other control and address bus inputs are STABLE; Data bus inputs are FLOATING
Precharge quiet standby current:
All banks idle; t
CK
=t
CK
(min); CKE is HIGH, CS# is HIGH; Other control and address bus inputs are STABLE; Data bus inputs are FLOATING
Precharge standby current:
All banks idle; t
CK
= t
CK
(min); CKE is HIGH, CS# is HIGH; Other control and address bus inputs are SWITCHING; Data bus inputs are SWITCHING
Active power-down current:
All banks open; t
CK
=t
CK
(min); CKE is LOW; Other control and address bus inputs are STABLE; Data bus inputs are FLOATING
MRS(A12)=0
MRS(A12)=1
Active standby current:
All banks open; t
CK
= t
CK
(min), t
RAS
= t
RAS
(max), t
RP
= t
RP
(min); CKE is HIGH, CS# is
HIGH between valid commands; Other control and address bus inputs are
SWITCHING; Data bus inputs are SWITCHING
Operating burst write current:
All banks open,continuous burst writes; BL = 4, CL = CL (min), AL = 0; t
CK
= t
CK
(min), t
RAS
= t
RAS
(max), t
RP
= t
RP
(min); CKE is HIGH, CS# is HIGH between valid commands; Address bus inputs are switching; Data bus inputs are switching
Operating burst read current:
All banks open, continuous burst reads, I
OUT
= 0mA; BL = 4, CL = CL (min), AL = 0; t
CK
= t
CK
(min), t
RAS
= t
RAS
(max), t
RP
= t
RP
(min); CKE is HIGH, CS# is HIGH between valid commands; Address bus inputs are SWITCHING; Data bus inputs are
SWITCHING
Burst refresh current:
t
CK
= t
CK
(min); refresh command at every t
RFC
(min) interval; CKE is HIGH, CS# is
HIGH between valid commands; Other control and address bus inputs are
SWITCHING; Data bus inputs are SWITCHING
Self refresh current:
CK and CK# at 0V; CKE ≤ 0.2V;Other control and address bus inputs are
FLOATING; Data bus inputs are FLOATING
Operating bank interleave read current:
All bank interleaving reads, I
OUT
= 0mA; BL = 4, CL = CL (min), AL =t
RCD t
CK
(min); t
CK
= t
CK
(min), t
RC
= t
RC
(min), t
RRD
= t
RRD
(min), t
RCD
= t
(min) - 1 x
RCD
(min); CKE is
HIGH, CS# is HIGH between valid commands; Address bus inputs are STABLE during DESELECTs.Data pattern is same as IDD4R
I
DD0
I
DD1
I
DD2P
I
DD2Q
I
DD2N
I
DD3P
I
DD3N
I
DD4W
I
DD4R
I
DD5
I
DD6
I
DD7
70
85
10
35
40
30
10
50
120
120
175
9
250 mA mA mA mA mA mA mA mA mA mA mA mA mA
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Table 26. Electrical Characteristics and Recommended A.C. Operating Conditions
(V
DD
= 1.8V 0.1V, T
OPER
= -40~95 C)
-25
Symbol Parameter
CL=4 t
CK(avg)
Average clock period
CL=5
CL=6 t
CH(avg)
Average clock HIGH pulse width t
CL(avg)
Average Clock LOW pulse width
WL Write command to DQS associated clock edge t
DQSS t
DSS t
DSH t
DQSH t
DQSL t
WPRE t
WPST
DQS latching rising transitions to associated clock edges
DQS falling edge to CK setup time
DQS falling edge hold time from CK
DQS input HIGH pulse width
DQS input LOW pulse width
Write preamble
Write postamble
-0.25
0.2
0.2
0.35
0.35
0.35
0.4
Min.
-
2.5
2.5
0.48
0.48
RL-1
Max.
8
8
8
0.52
0.52
0.25
-
-
-
-
-
0.6 t
IS(base)
Address and Control input setup time 0.175 - t
IH(base)
Address and Control input hold time t
IPW
Control & Address input pulse width for each input t
DS(base)
DQ & DM input setup time t
DH(base)
DQ & DM input hold time t
CCD t
WR t
DAL t
WTR t
RTP t
CKE t
QH t
RPRE t
RPST t
RRD t
FAW t
DIPW t
AC t
DQSCK
DQS output access time from CK, CK# t
HZ
Data-out high-impedance time from CK, CK# t
LZ(DQS)
DQS(DQS#) low-impedance time from CK, CK# t
LZ(DQ) t
DQSQ
DQ and DM input pulse width for each input
DQ output access time from CK, CK#
DQ low-impedance time from CK, CK#
DQS-DQ skew for DQS and associated DQ signals t
HP t
QHS
CK half pulse width
DQ hold skew factor
DQ/DQS output hold time from DQS
Read preamble
Read postamble
Active to active command period
Four Activate Window
CAS# to CAS# command delay
Write recovery time
Auto Power write recovery + precharge time
Internal Write to Read Command Delay
Internal read to precharge command delay
CKE minimum pulse width
0.25
0.6
0.05
0.125
0.35
-0.4
-0.35
- t
AC
(min)
2t
AC
(min)
- min (t
CH
,t
CL
)
- t
HP
-t
QHS
0.9
0.4
7.5
35
2
15
WR + t
RP
7.5
7.5
3
-
-
-
-
-
0.3
-
1.1
0.6
-
-
0.4
0.35 t
AC
(max) t
AC
(max) t
AC
(max)
0.2
-
-
-
-
-
-
-
Unit
Specific
Notes
ns
15, 33, 34 ns ns t
CK t
CK t
CK t
CK t
CK t
CK t
CK t
CK t
CK t
CK
34, 35
34, 35
28
28
10 ns ns
5, 7, 9, 22,
27
5, 7, 9, 23,
27 t
CK ns ns
6-8, 20, 26,
29
6-8, 21, 26,
29 t
CK ns ns ns ns ns
38
38
18, 38
18, 38
18, 38 ns
13 ns
11, 12, 35 ns ns t
CK t
CK ns
12, 36
37
19, 39
19, 40
4, 30 ns t
CK ns
4, 30
30 ns
14, 31 ns
3, 24, 30 ns t
CK
3, 30
25
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t
XSNR t
XSRD t
XP t
XARD
Exit self refresh to non-read command delay
Exit self refresh to a read command
Exit precharge power down to any command t
XARDS
Exit active power down to read command
Exit active power down to read command(slow exit, lower power)
ODT turn-on delay t
AOND t
AON
ODT turn-on t
AONPD
ODT turn-on (Power-Down mode) t
AOFD t
AOF
ODT turn-off delay
ODT turn-off t
AOFPD
ODT turn-off (Power-Down mode) t
ANPD t
AXPD t
MRD t
MOD t t t
Delay
RFC
REFI
ODT to power down entry latency
ODT power down exit latency
Mode register set command cycle time
MRS command to ODT update delay
Minimum time clocks remains ON after CKE asynchronously drops LOW
Refresh to active/Refresh command time
-40℃ ≦TC≦ +85℃
Average periodic refesh interval
+85℃ <TC≦ +95℃ t
RCD t
RP t
RC t
RAS
RAS# to CAS# Delay time
Row precharge Delay time
Row cycle Delay time
Row active Delay time t
RFC
+10
200
2
2
8-AL
2 t
AC
(min) t
AC
(min)
+2
2.5 t
AC
(min) t
AC
(min)
+2
2
0
3
8 t
IS
+ t
CK
+t
IH
127.5
-
-
12.5
12.5
57.5
45
-
30
1
2 t
CK t
AC
(max)
+0.7
2 t
CK
+t
AC
(max)
+1 ns
16 ns
6, 16, 38
2.5 t
CK t
AC
(max)
+0.6
2.5 t
CK
+t
AC
(max)
+1 ns
17, 42 ns
17, 41, 42
-
-
-
12 t
CK t
CK t
CK ns
30
-
-
7.8
3.9
-
-
-
70K
-
-
-
- ns ns ns ns s s ns ns t
CK t
CK t
CK t
CK ns
1, 2
15
43
43
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General notes, which may apply for all AC parameters:
NOTE 1: DDR2 SDRAM AC timing reference load
The below figure represents the timing reference load used in defining the relevant timing parameters of the part. It is not intended to be either a precise representation of the typical system environment or a depiction of the actual load presented by a production tester.
Figure 5. AC timing reference load
VDDQ
DUT
DQ
DQS
DQS#
RDQS
RDQS#
Ouput
V
TT
=V
DDQ
/2
25Ω
Timing reference point
The output timing reference voltage level for single ended signals is the crosspoint with VTT. The output timing reference voltage level for differential signals is the crosspoint of the true (e.g. DQS) and the complement (e.g. DQS#) signal.
NOTE 2: Slew Rate Measurement Levels a) Output slew rate for falling and rising edges is measured between V
TT
- 250 mV and V
TT
+ 250 mV for single ended signals.
For differential signals (e.g. DQS – DQS#) output slew rate is measured between DQS – DQS# = - 500 mV and DQS – DQS#
= + 500 mV. Output slew rate is guaranteed by design, but is not necessarily tested on each device. b) Input slew rate for single ended signals is measured from V
REF
(dc) to V
IH
(ac), min for rising edges and from V
REF
(dc) to
V
IL
(ac),max for falling edges.For differential signals (e.g. CK – CK#) slew rate for rising edges is measured from CK – CK# = -
250 mV to CK -CK# = + 500 mV (+ 250 mV to - 500 mV for falling edges). c) V
ID
is the magnitude of the difference between the input voltage on CK and the input voltage on CK#, or betweenDQS and
DQS# for differential strobe.
NOTE 3: DDR2 SDRAM output slew rate test load
Output slew rate is characterized under the test conditions as bellow
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AS4C128M8D2
VDDQ
Figure 6. Slew rate test load
DUT
DQ
DQS
DQS#
RDQS
RDQS#
Ouput
25Ω
Test point
V
TT
=V
DDQ
/2
NOTE 4: Differential data strobe
DDR2 SDRAM pin timings are specified for either single ended mode or differential mode depending on the setting of the EMRS “Enable DQS” mode bit; timing advantages of differential mode are realized in system design. The method by which the DDR2 SDRAM pin timings are measured is mode dependent. In single ended mode, timing relationships are measured relative to the rising or falling edges of DQS crossing at V
REF
. In differential mode, these timing relationships are measured relative to the crosspoint of DQS and its complement, DQS#. This distinction in timing methods is guaranteed by design and characterization. Note that when differential data strobe mode is disabled via the EMRS, the complementary pin, DQS#, must be tied externally to V
SS
through a 20 Ω to 10 kΩ resistor to insure proper operation
NOTE 5: AC timings are for linear signal transitions.
NOTE 6: All voltages are referenced to V
SS
.
NOTE 7: These parameters guarantee device behavior, but they are not necessarily tested on each device.They may be guaranteed by device design or tester correlation
NOTE 8: Tests for AC timing, I
DD
, and electrical (AC and DC) characteristics, may be conducted at nominal reference/supply voltage levels, but the related specifications and device operation are guaranteed for the full voltage range specified.
Specific notes for dedicated AC parameters
NOTE 1: User can choose which active power down exit timing to use via MRS (bit 12). t
XARD
is expected to be used for fast active power down exit timing. t
XARDS
is expected to be used for slow active power down exit timing where a lower power value is defined by each vendor data sheet.
NOTE 2: AL=Additive Latency.
NOTE 3: This is a minimum requirement. Minimum read to precharge timing is AL+BL/2 provided that the t
RTP
and t
RAS
(min) have been satisfied.
NOTE 4: A minimum of two clocks (2* t
CK
) is required irrespective of operating frequency.
NOTE 5: Timings are specified with command/address input slew rate of 1.0 V/ns.
NOTE 6: Timings are specified with DQs, DM, and DQS’s (DQS/RDQS in single ended mode) input slew rate of 1.0V/ns.
NOTE 7: Timings are specified with CK/CK# differential slew rate of 2.0 V/ns. Timings are guaranteed for DQS signals with a differential slew rate of 2.0 V/ns in differential strobe mode and a slew rate of 1 V/ns in single ended mode.
NOTE 8: Data setup and hold time derating.
For all input signals the total t
DS
(setup time) and t
DH
(hold time) required is calculated by adding the data sheet. t
DS(base) and t
DH(base)
value to the Δt
DS
and Δt
DH
derating value respectively.
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Example: t
DS
(total setup time) =t
DS (base)
+ Δt
DS
.For slew rates in between the values listed in Tables 28, the derating values may obtained by linear interpolation.These values are typically not subject to production test. They are verified by design and characterization.
Table 27. DDR2-800 tDS/tDH derating with differential data strobe
DQ
Slew
Rate
V/ns
2.0
1.5
1.0
0.9
0.8
0.7
0.6
0.5
0.4
-
-
-
-
0
-
-
2.8 V/ns
△
tDS
△
tDH
100 63
67 42
△tDS, △tDH derating values for DD2-800 (All units in ‘ps’; the note applies to the entire table)
2.4 V/ns
△
tDS
100
△
tDH
63
2.0 V/ns
△
tDS
100
△
tDH
63
DQS,DQS# Differential Slew Rate
1.8 V/ns
△
tDS
△
tDH
1.6 V/ns
△
tDS
△
tDH
1.4 V/ns
△
tDS
△
tDH
- - - - - -
1.2 V/ns
△
tDS
-
△
tDH
-
67 42 67 42 79 54 - - - - - -
1.0 V/ns
△
tDS
△
tDH
- -
- -
-
-
-
-
0
-
-
-
-
-
-
0
-5
-
-
-
-
-
0
-14
-
-
-
-
-
0
-5
-13
-
-
-
-
0
-14
-31
12
7
-1
-10
-
-
-
12
-2
-19
-42
-
-
-
24
19
11
2
-10
-
-
24
10
-7
-30
-59
-
-
-
31
23
14
2
-24
-
-
22
5
-18
-47
-89
-
-
-
35
26
14
-12
-52
-
-
17
-6
-35
-77
-140
38
26
0
-40
-
-
-
6
-23
-65
-128
-
-
-
0.8 V/ns
△
tDS
△
tDH
- -
- -
-
38
12
-28
-
-
-
-
-11
-53
-116
-
-
-
NOTE 9: t
IS
and t
IH
(input setup and hold) derating
For all input signals the total t
IS
(setup time) and t
IH
(hold time) required is calculated by adding the data sheet t
IS(base)
and t
IH(base)
value to the Δt
IS
and Δ tIH
derating value respectively. Example: t
IS
(total setup time) = t
IS
(base) + Δt
IS
For slew rates in between the values listed in Tables 29, the derating values may obtained by linear interpolation.These values are typically not subject to production test. They are verified by design and characterization
Table 28. Derating values for DDR2-800
Command/
Address Slew rate
(V/ns)
0.9
0.8
0.7
0.6
0.5
0.4
0.3
0.25
4.0
3.5
3.0
2.5
2.0
1.5
1.0
0.2
0.15
0.1
△tIS and △tIH Derating Values for DDR2-800
CK,CK# Differential Slew Rate
△tIS
2.0 V/ns
△tIH △tIS
1.5 V/ns
△tIH △tIS
1.0 V/ns
△tIH
-5
-13
-22
-34
-60
-100
-168
-200
+150
+143
+133
+120
+100
+67
0
-325
-517
-1000
+94
+89
+83
+75
+45
+21
0
-14
-31
-54
-83
-125
-188
-292
-375
-500
-708
-1125
+180
+173
+163
+150
+130
+97
+30
+25
+17
+8
-4
-30
-70
-138
-170
-295
-487
-970
+124
+119
+113
+105
+75
+51
+30
+16
-1
-24
-53
-95
-158
-262
-345
-470
-678
-1095
+210
+203
+193
+180
+160
+127
+60
+55
+47
+38
+26
0
-40
-108
-140
-265
-457
-940
+46
+29
+6
-23
-65
-128
-232
-315
+154
+149
+143
+135
+105
+81
+60
-440
-648
-1065
Units ps ps ps ps ps ps ps ps ps ps ps ps ps ps ps ps ps ps
Notes
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
NOTE 10: The maximum limit for this parameter is not a device limit. The device will operate with a greater value for this parameter, but system performance (bus turnaround) will degrade accordingly.
NOTE 11: MIN (t
CL
, t
CH
) refers to the smaller of the actual clock LOW time and the actual clock HIGH time as provided to the device (i.e. this value can be greater than the minimum specification limits for t
CL and t
CH
).
NOTE 12: t
QH
= t
HP
– t
QHS
, where:
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t
HP
= minimum half clock period for any given cycle and is defined by clock HIGH or clock LOW (t
CH
, t
CL
). t
QHS
accounts for:
1) The pulse duration distortion of on-chip clock circuits; and
2) The worst case push-out of DQS on one transition followed by the worst case pull-in of DQ on the next transition, both of which are, separately, due to data pin skew and output pattern effects, and p-channel to n-channel variation of the output drivers.
NOTE 13: t
DQSQ
: Consists of data pin skew and output pattern effects, and p-channel to n-channel variation of the output drivers as well as output slew rate mismatch between DQS / DQS# and associated DQ in any given cycle.
NOTE 14: t
DAL
= WR + RU{ t
RP
[ns] / t
CK
[ns] }, where RU stands for round up.WR refers to the t
WR
parameter stored in the MRS.
For t
RP
, if the result of the division is not already an integer, round up to the next highest integer. t
CK
refers to the application clock period.
NOTE 15: The clock frequency is allowed to change during self–refresh mode or precharge power-down mode. In case of clock frequency change during precharge power-down.
NOTE 16: ODT turn on time min is when the device leaves high impedance and ODT resistance begins to turn on. ODT turn on time max is when the ODT resistance is fully on. Both are measured from t
AOND
, which is interpreted differently per speed bin. For DDR2-800, t
AOND
is 2 clock cycles after the clock edge that registered a first ODT HIGH counting the actual input clock edges.
NOTE 17: ODT turn off time min is when the device starts to turn off ODT resistance. ODT turn off time max is when the bus is in high impedance. Both are measured from t
AOFD
, which is interpreted differently per speed bin. For DDR2-800, if t
CK
(avg) = 2.5 ns is assumed, t
AOFD
is 1.25 ns (= 0.5 x 2.5ns) after the second trailing clock edge counting from the clock edge that registered a first ODT LOW and by counting the actual input clock edges.
NOTE 18: t
HZ
and t
LZ
transitions occur in the same access time as valid data transitions. These parameters are referenced to a specific voltage level which specifies when the device output is no longer driving (t
HZ
), or begins driving (t
LZ
).
NOTE 19: t
RPST
end point and t
RPRE
begin point are not referenced to a specific voltage level but specify when the device output is no longer driving (t
RPST
), or begins driving (t
RPRE
). The actual voltage measurement points are not critical as long as the calculation is consistent.
NOTE 20: Input waveform timing t
DS
with differential data strobe enabled MR[bit10]=0, is referenced from the input signal crossing at the V
IH
(ac) level to the differential data strobe crosspoint for a rising signal, and from the input signal crossing at the V
IL
(ac) level to the differential data strobe crosspoint for a falling signal applied to the device under test.
DQS, DQS# signals must be monotonic between V
IL
(dc)max and V
IH
(dc)min.
NOTE 21: Input waveform timing t
DH
with differential data strobe enabled MR[bit10]=0, is referenced from the differential data strobe crosspoint to the input signal crossing at the V
IH
(dc) level for a falling signal and from the differential data strobe crosspoint to the input signal crossing at the V
IL
(dc) level for a rising signal applied to the device under test. DQS,
DQS# signals must be monotonic between V
IL
(dc)max and V
IH
(dc)min.
NOTE 22: Input waveform timing is referenced from the input signal crossing at the V
IH
(ac) level for a rising signal and V
IL
(ac) for a falling signal applied to the device under test.
NOTE 23: Input waveform timing is referenced from the input signal crossing at the V
IL
(dc) level for a rising signal and V
IH
(dc) for a falling signal applied to the device under test.
NOTE 24: t
WTR
is at lease two clocks (2 x t
CK
) independent of operation frequency.
NOTE 25: t
CKE min of 3 clocks means CKE must be registered on three consecutive positive clock edges. CKE must remain at the valid input level the entire time it takes to achieve the 3 clocks of registration. Thus, after any CKE transition, CKE may not transition from its valid level during the time period of t
IS
+ 2 x t
CK
+ t
IH
.
NOTE 26: If t
DS
or t
DH
is violated, data corruption may occur and the data must be re-written with valid data before a valid
READ can be executed.
NOTE 27: These parameters are measured from a command/address signal (CKE, CS#, RAS#, CAS#, WE#, ODT, BA0, A0, A1, etc.) transition edge to its respective clock signal (CK/CK#) crossing. The spec values are not affected by the amount of
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clock jitter applied (i.e. t
JIT
(per), t
JIT
(cc), etc.), as the setup and hold are relative to the clock signal crossing that latches the command/address. That is, these parameters should be met whether clock jitter is present or not.
NOTE 28: These parameters are measured from a data strobe signal (DQS) crossing to its respective clock signal (CK/CK#) crossing. The spec values are not affected by the amount of clock jitter applied (i.e. t
JIT
(per), t
JIT
(cc), etc.), as these are relative to the clock signal crossing. That is, these parameters should be met whether clock jitter is present or not.
NOTE 29: These parameters are measured from a data signal (DM, DQ0, DQ1, etc.) transition edge to its respective data strobe signal (DQS/ DQS#) crossing.
NOTE 30: For these parameters, the DDR2 SDRAM device is characterized and verified to support tnPARAM = RU{tPARAM / t
CK
(avg)}, which is in clock cycles, assuming all input clock jitter specifications are satisfied.
NOTE 31: t
DAL
[t
CK
] = WR [t
CK
] + tRP [t
CK
] = WR + RU {t
RP
[ps] / t
CK
(avg) [ps] }, where WR is the value programmed in the mode register set.
NOTE 32: New units, ‘t
CK
(avg)’ is introduced in DDR2-800. Unit ‘t
CK
(avg)’ represents the actual t
CK
(avg) of the input clock under operation.
NOTE 33: Input clock jitter spec parameter. These parameters and the ones in the table below are referred to as 'input clock jitter spec parameters' and these parameters apply to DDR2-800. The jitter specified is a random jitter meeting a
Gaussian distribution.
Table 29. Input clock jitter spec parameter
-25
Parameter Symbol Unit Note
Clock period jitter
Clock period jitter during DLL locking period
Cycle to cycle clock period jitter
Cycle to cycle clock period jitter during DLL locking period
Cumulative error across 2 cycles t
JIT ( per) t
JIT
(per,lck) t
JIT
(cc) t
JIT
(cc,lck) t
ERR
(2per)
Min.
-100
-80
-200
-160
-150
Max.
100
80
200
160
150 ps ps ps ps ps
33
33
33
33
33
Cumulative error across 3 cycles t
ERR
(3per) -175 175 ps 33
Cumulative error across 4 cycles
Cumulative error across 5 cycles
Cumulative error across n cycles, n=6...10, inclusive t
ERR
(4per) t
ERR
(5per) t
ERR
(6-10per)
-200
-200
-300
200
200
300 ps ps ps
33
33
33
Cumulative error across n cycles, n=11...50, inclusive t
ERR
(11-50per) -450 450 ps 33
Duty cycle jitter t
JIT
(duty) -100 100 ps 33
NOTE 34: These parameters are specified per their average values, however it is understood that the following relationship between the average timing and the absolute instantaneous timing holds at all times. (Min andmax of SPEC values are to be used for calculations in the table below.)
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Table 30. Absolute clock period average values
Parameter
Absolute clock period
Symbol
t
CK
(abs)
Min.
t
CK
(avg),min + t
JIT
(per),min
Absolute clock HIGH pulse width
Absolute clock LOW pulse width t
CH
(abs) t
CL
(abs) t
CH
(avg),min * t
CK
(avg),min + t
JIT
(duty),min t
CL
(avg),min * t
CK
(avg),min + t
JIT
(duty),min
Max.
t
CK
(avg),max + t
JIT
(per),max t
CH
(avg),max * t
CK
(avg),max + t
JIT
(duty),max t
CL
(avg), max * t
CK
(avg),max + t
JIT
(duty), max
Unit
ps ps ps
NOTE 35: t
HP
is the minimum of the absolute half period of the actual input clock. t
HP
is an input parameter but not an input specification parameter. It is used in conjunction with t
QHS
to derive the DRAM output timing t
QH
. The value to be used for tQH calculation is determined by the following equation;
t
HP
= Min ( t
CH
(abs), t
CL
(abs) ),
where,
t
CH
(abs) is the minimum of the actual instantaneous clock HIGH time;
t
CL
(abs) is the minimum of the actual instantaneous clock LOW time;
NOTE 36: t
QHS
accounts for:
1) The pulse duration distortion of on-chip clock circuits, which represents how well the actual t
HP
at the input is transferred to the output; and
2) The worst case push-out of DQS on one transition followed by the worst case pull-in of DQ on the next transition, both of which are independent of each other, due to data pin skew, output pattern effects, and p-channel to n-channel variation of the output drivers
NOTE 37: t
QH
= t
HP
– t
QHS
, where: t
HP
is the minimum of the absolute half period of the actual input clock; and t
QHS
is the specification value under the max column. {The less half-pulse width distortion present, the larger the t
QH
value is; and the larger the valid data eye will be.}
NOTE 38: When the device is operated with input clock jitter, this parameter needs to be derated by the actual t
ERR
(6-10per) of the input clock. (output deratings are relative to the SDRAM input clock.)
NOTE 39: When the device is operated with input clock jitter, this parameter needs to be derated by the actual tJIT(per) of the input clock. (output deratings are relative to the SDRAM input clock.)
NOTE 40: When the device is operated with input clock jitter, this parameter needs to be derated by the actual t
JIT
(duty) of the input clock. (output deratings are relative to the SDRAM input clock.)
NOTE 41: When the device is operated with input clock jitter, this parameter needs to be derated by { - t
JIT
(duty),max - t
ERR
(6-
10per),max } and { - t
JIT
(duty),min - t
ERR
(6-10per),min } of the actual input clock. (output deratings are relative to the
SDRAM input clock.)
NOTE 42: For t
AOFD
of DDR2-800, the 1/2 clock of t
CK
in the 2.5 x t
CK
assumes a t
CH
(avg), average input clock HIGH pulse width of
0.5 relative to t
CK
(avg). t
AOF
,min and t
AOF
,max should each be derated by the same amount as the actual amount of t
CH
(avg) offset present at the DRAM input with respect to 0.5.
NOTE 43: If refresh timing is violated, data corruption may occur and the data must be re-writtern with valid data before a valid READ can be executed.
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Timing Waveforms
Figure 7. Initialization sequence after power-up
t
CH t
CL
CK
CK# t
IS
CKE t
IS
ODT
Command
NOP
PRE
ALL
EMR
S
MRS
PRE
ALL
REF REF MRS
EMR
S
EMR
S
ANY
CMD t
RFC 400ns t
RP
DLL
ENABLE t
MRD
DLL
RESET t
MRD t
RP t
RFC min 200 Cycle
NOTE 1: To guarantee ODT off, V
REF
must be valid and a LOW level must be applied to the ODT pin.
Figure 8. ODT update delay timing-tMOD
CMD EMRS NOP NOP NOP t
MRD
Follow OCD Flowchart
OCD
Default
OCD
CAL.MOD
E EXIT t
OIT
NOP NOP
CK#
CK
ODT t
IS t
MOD, max
Rtt t
AOFD
Old setting t
MOD, min
Updating New setting
NOTE 1: To prevent any impedance glitch on the channel, the following conditions must be met:
- t
AOFD
must be met before issuing the EMRS command.
- ODT must remain LOW for the entire duration of t
MOD
window, until t
MOD
, max is met.
then the ODT is ready for normal operation with the new setting, and the ODT signal may be raised again to turned
on the ODT.
NOTE 2: EMRS command directed to EMR(1), which updates the information in EMR(1)[A6,A2], i.e. Rtt (Nominal).
NOTE 3: "setting" in this diagram is the Register and I/O setting, not what is measured from outside.
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Figure 9. ODT update delay timing-t
MOD
, as measured from outside
CK#
CK
CMD
EMRS NOP
NOP NOP NOP NOP
ODT
Rtt t
IS t
AOND t
AOFD
Old setting t
MOD, max
New setting
NOTE 1: EMRS command directed to EMR(1), which updates the information in EMR(1)[A6,A2], i.e. Rtt (Nominal).
NOTE 2: "setting" in this diagram is measured from outside.
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Figure 10. ODT timing for active standby mode
T0 T1 T2
CK#
CK
T3 T4 T5
T6 t
IS
CKE t
IS t
IS
V
IH(ac)
V
IL(ac)
ODT t
AOND t
AOFD
Internal
Term Res.
RTT t
AON,min t
AOF,min t
AON,max t
AOF,max
Figure 11. ODT timing for power-down mode
T0 T1 T2
CK#
CK
CKE
V
IH(AC) t
IS
V
IL(AC)
ODT t
IS
T3 T4 T5 T6
Internal
Term Res.
t
AOFPD,max t
AOFPD,min
RTT t
AONPD,min t
AONPD,max
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Figure 12. ODT timing mode switch at entering power-down mode
T-5 T-4 T-3 T-2 T-1 T0
CK#
CK t
ANPD
CKE t
IS
T1 T2 T3 T4
Entering Slow Exit Active Power Down Mode or Precharge Power Down Mode.
ODT
V
IL(ac) t
IS t
AOFD
Internal
Term Res.
RTT
ODT
V
IL(ac) t
IS t
AOFPD max
Internal
Term Res.
RTT
V
IH(ac) t
IS
ODT
Internal
Term Res.
t
AOND
V
IH(ac) t
IS
ODT
Internal
Term Res.
t
AONPD max
RTT
RTT
Active & Standby mode timings to be applied.
Power Down mode timings to be applied.
Active & Standby mode timings to be applied.
Power Down mode timings to be applied.
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Figure 13.ODT timing mode switch at exit power-down mode
T0 T1 T4 T5 T6 T7
CK#
CK t
IS t
AXPD
V
IH(ac)
CKE
T8 T9 T10 T11
Exiting from Slow Active Power Down Mode or Precharge power Down Mode.
ODT
V
IL(ac) t
IS
Active & Standby mode timings to be applied.
t
AOFD
Internal
Term Res.
RTT
Power Down mode timings to be applied.
ODT
V
IL(ac) t
IS t
AOFPD max
Internal
Term Res.
RTT
V
IH(ac) t
IS
Active & Standby mode timings to be applied.
ODT t
AOND
Internal
Term Res.
V
IH(ac) t
IS
Power Down mode timings to be applied.
ODT t
AONPD max
Internal
Term Res.
RTT
Figure 14. Bank activate command cycle (t
RCD
=3, AL=2, t
RP
=3, t
RRD
=2, t
CCD
=2)
T0 T1 T2 T3 Tn Tn+1
CK#
CK
Internal RAS# - CAS# delay (>=t
RCD min
)
ADDRESS
Bank A
Row Addr.
Bank A
Col. Addr.
Bank B
Row Addr.
Bank B
Col. Addr
Bank A
Addr.
CAS# - CAS# delay time (t
CCD
)
Additive latency delay (AL) t
RCD
= 1
RAS# - RAS# delay time (>=t
RRD
)
Read Begins
COMMAND
Bank A
Activate
Bank A
Post CAS#
Read
Bank B
Activate
Bank Active (>=t
RAS
)
Bank B
Post CAS#
Read
Tn+2
Bank B
Addr.
Bank A
Precharge
Bank precharge time (>=t
RP
)
Bank B
Precharge
RAS# Cycle time (>=t
RC
)
RTT
Tn+3
Bank A
Row Addr.
Bank A
Activate
Alliance Memory Inc. 551 Taylor Way, San Carlos, CA 94070
TEL: (650) 610-6800 FAX: (650) 620-9211
Alliance Memory Inc. reserves the right to change products or specification without notice.
37 Rev. 1.0 June 2013
AS4C128M8D2
Figure 15. Posted CAS# operation: AL=2
Read followed by a write to the same bank
-1 0 1 2 3 4 5 6
CK#
CK
7 8 9 10 11 12
Write
A-Bank
CMD
DQS
DQS#
Active
A-Bank
Read
A-Bank
AL=2
>=t
RCD
CL=3
WL=RL-1=4
RL=AL+CL=5
DQ
Dout 0 Dout 1 Dout 2 Dout 3 Din 0 Din 1 Din 2 Din 3
[ AL=2 and CL=3, RL= (AL+CL)=5, WL= (RL-1)=4, BL=4]
Figure 16. Posted CAS# operation: AL=0
Read followed by a write to the same bank
-1 0 1 2 3 4 5
CK#
6 7
CK
CMD
Active
A-Bank
AL=0
Read
A-Bank
CL=3
Write
A-Bank
8
WL=RL-1=2
DQS
DQS#
>=t
RCD
RL=AL+CL=3
DQ
Dout 0 Dout 1 Dout 2 Dout 3
9 10
Din 0 Din 1 Din 2 Din 3
11 12
[ AL=0 and CL=3, RL= (AL+CL)=3, WL= (RL-1)=2, BL=4]
Alliance Memory Inc. 551 Taylor Way, San Carlos, CA 94070
TEL: (650) 610-6800 FAX: (650) 620-9211
Alliance Memory Inc. reserves the right to change products or specification without notice.
38 Rev. 1.0 June 2013
AS4C128M8D2
Figure 17. Data output (read) timing
CK# t
CH t
CL
CK
CK
DQS
DQS#
DQS#
DQS t
RPRE
DQ
Q t
DQSQ max
Figure 18. Data input (write) timing
DQS#
DQS
DQS#
DQS t
DQSH t
WPRE t
QH t
DQSL
Q Q t
DQSQ max t
RPST
Q t
QH t
WPSL
DQ t
DS
V
IH(ac)
V
D
IL(ac)
D
V
IH(dc)
D
IL(dc) t
DH
D
DM
DMin t
DS
V
IH(ac)
DMin
V
IL(ac)
DMin t
DH
V
IH(dc)
DMin
V
IL(dc)
Alliance Memory Inc. 551 Taylor Way, San Carlos, CA 94070
TEL: (650) 610-6800 FAX: (650) 620-9211
Alliance Memory Inc. reserves the right to change products or specification without notice.
39 Rev. 1.0 June 2013
AS4C128M8D2
Figure 19. Burst read operation: RL=5 (AL=2, CL=3, BL=4)
T0 T1 T2 T3 T4
CK#
CK
T5 T6 T7 T8
CMD Posted CAS#
READ A
NOP NOP NOP NOP NOP
=< t
DQSCK
NOP NOP NOP
DQS
DQS#
AL=2 CL=3
RL=5
DQs
Figure 20. Burst read operation: RL=3 (AL=0, CL=3, BL=8)
T0 T1 T2 T3 T4
CK#
CK
T5
Dout A0 Dout A1 Dout A2 Dout A3
T6 T7 T8
CMD
READ A NOP NOP NOP
=< t
DQSCK
NOP NOP NOP NOP NOP
DQS
DQS#
CL=3
RL=3
DQs
Dout A0 Dout A1 Dout A2 Dout A3 Dout A4 Dout A5 Dout A6 Dout A7
Figure 21. Burst read followed by burst write: RL=5, WL= (RL-1) =4, BL=4
T0 T1 Tn-1 Tn Tn+1 Tn+2 Tn+3
CK#
CK
CMD
Post CAS#
READ A
NOP NOP
Post CAS#
WRITE A
NOP t
RTW
(Read to Write turn around time)
NOP NOP
DQS
DQS#
RL=5
WL = RL-1 = 4
DQs
Dout A
0
Dout A
1
Dout A
2
Dout A
3
Tn+4
NOP
Tn+5
NOP
Din A
0
Din A
1
Din A
2
Din A
3
NOTE : The minimum time from the burst read command to the burst write command is defined by a read-to-write-
turn-around-time, which is 4 clocks in case of BL = 4 operation, 6 clocks in case of BL = 8 operation.
Alliance Memory Inc. 551 Taylor Way, San Carlos, CA 94070
TEL: (650) 610-6800 FAX: (650) 620-9211
Alliance Memory Inc. reserves the right to change products or specification without notice.
40 Rev. 1.0 June 2013
AS4C128M8D2
Figure 22. Seamless burst read operation: RL=5, AL=2, CL=3, BL=4
T0 T1 T2 T3 T4 T5
CK#
CK
T6 T7 T8
CMD
Post CAS#
READ A
NOP
Post CAS#
READ B
NOP NOP NOP NOP NOP NOP
DQS
DQS#
AL=2
RL=5
CL=3
DQs
Dout A0 Dout A1 Dout A2 Dout A3 Dout B0 Dout B1 Dout B2
NOTE : The seamless burst read operation is supported by enabling a read command at every other clock for BL =
4 operation, and every 4 clock for BL =8 operation. This operation is allowed regardless of same or different banks as long as the banks are activated.
Figure 23. Read burst interrupt timing: (CL=3, AL=0, RL=3, BL=8)
CK#
CK
CMD
Read A NOP Read B NOP NOP NOP NOP NOP NOP NOP
DQS
DQS#
DQs
A0 A1 A2 A3 B0 B1 B2 B3 B4 B5 B6 B7
NOTE 1: Read burst interrupt function is only allowed on burst of 8. Burst interrupt of 4 is prohibited.
NOTE 2: Read burst of 8 can only be interrupted by another Read command. Read burst interruption by Write command or Precharge command is prohibited.
NOTE 3: Read burst interrupt must occur exactly two clocks after previous Read command. Any other Read burst interrupt timings are prohibited.
NOTE 4: Read burst interruption is allowed to any bank inside DRAM.
NOTE 5: Read burst with Auto Precharge enabled is not allowed to interrupt.
NOTE 6: Read burst interruption is allowed by another Read with Auto Precharge command.
NOTE 7: All command timings are referenced to burst length set in the mode register. They are not referenced to actual burst. For example, Minimum Read to Precharge timing is AL+BL/2 where BL is the burst length set in the mode register and not the actual burst (which is shorter because of interrupt).
Alliance Memory Inc. 551 Taylor Way, San Carlos, CA 94070
TEL: (650) 610-6800 FAX: (650) 620-9211
Alliance Memory Inc. reserves the right to change products or specification without notice.
41 Rev. 1.0 June 2013
AS4C128M8D2
Figure 24. Burst write operation: RL=5 (AL=2, CL=3), WL=4, BL=4
T0 T1 T2 T3 T4 T5
CK#
CK
CMD Posted CAS#
WRITE A
Case 1: with t
DQSS (max)
DQS
DQS#
NOP NOP
WL = RL-1 =4
NOP NOP t
DQSS
NOP t
DSS t
DQSS
T6 T7
NOP NOP t
DSS
Completion of the
Burst Write
>=t
WR
Tn
Precharge
DQs
Case 2: with t
DQSS (min)
DQS
DQS#
WL = RL-1 =4
DQs
DNA
0
DNA
1
DNA
2
DNA
3 t
DQSS t
DSH t
DQSS t
DSH
DNA
0
DNA
1
DNA
2
DNA
3
>=t
WR
Figure 25. Burst write operation: RL=3 (AL=0, CL=3), WL=2, BL=4
T0 T1 T2 T3 T4 T5
CK#
CK
Tm Tm+1
Tn
CMD
WRITE A
DQS
DQS#
NOP NOP
<=t
DQSS
NOP NOP NOP
Completion of the
Burst Write
Precharge
NOP
Bank A
Activate
WL = RL-1 =2
>=t
WR
>=t
RP
DQs
DNA
0
DNA
1
DNA
2
DNA
3
Alliance Memory Inc. 551 Taylor Way, San Carlos, CA 94070
TEL: (650) 610-6800 FAX: (650) 620-9211
Alliance Memory Inc. reserves the right to change products or specification without notice.
42 Rev. 1.0 June 2013
AS4C128M8D2
Figure 26. Burst write followed by burst read:
RL=5 (AL=2, CL=3, WL=4, t
WTR
=2, BL=4)
T0 T1 T2 T3 T4
CK#
CK
Write to Read = CL-1+BL/2+t
WTR
CKE
NOP NOP NOP NOP
Post CAS#
READ A
DQS#
DQS
DQS#
WL = RL-1 = 4
DQS
T5
AL=2
NOP
T6
NOP
T7
CL=3
NOP
T8
NOP
T9
RL=5
>=t
WTR
DQ
DNA
0
DNA
1
DNA
2
DNA
3
DOUT A
0
NOTE : The minimum number of clock from the burst write command to the burst read command is [CL-1 + BL/2 + t
WTR
].
This t
WTR
is not a write recovery time (t
WR sense amplifiers in the array. t
WTR
) but the time required to transfer the 4 bit write data from the input buffer into
is defined in the timing parameter table of this standard.
Figure 27. Seamless burst write operation RL=5, WL=4, BL=4
T0 T1 T2 T3 T4
CK#
T5 T6 T7 T8
CK
CMD
DQS
DQS#
DQ
Post CAS#
Write A
NOP
WL = RL-1 = 4
Post CAS#
Write B
NOP
DQS#
DQS
NOP NOP NOP NOP NOP
DNA
0
DNA
1
DNA
2
DNA
3
DNB
0
DNB
1
DNB
2
DNB
3
NOTE : The seamless burst write operation is supported by enabling a write command every other clock for
BL= 4 operation, every four clocks for BL = 8 operation. This operation is allowed regardless of same or different banks as long as the banks are activated.
Alliance Memory Inc. 551 Taylor Way, San Carlos, CA 94070
TEL: (650) 610-6800 FAX: (650) 620-9211
Alliance Memory Inc. reserves the right to change products or specification without notice.
43 Rev. 1.0 June 2013
AS4C128M8D2
Figure 28. Write burst interrupt timing: (CL=3, AL=0, RL=3, WL=2, BL=8)
CK#
CK
CMD
NOP Write A NOP Write B NOP NOP NOP NOP NOP NOP
DQS
DQS#
DQs
A0 A1 A2 A3 B0 B1 B2 B3 B4 B5 B6 B7
NOTE 1: Write burst interrupt function is only allowed on burst of 8. Burst interrupt of 4 is prohibited.
NOTE 2: Write burst of 8 can only be interrupted by another Write command. Write burst interruption by Read command or
Precharge command is prohibited.
NOTE 3: Write burst interrupt must occur exactly two clocks after previous Write command. Any other Write burst interrupt timings are prohibited.
NOTE 4: Write burst interruption is allowed to any bank inside DRAM.
NOTE 5: Write burst with Auto Precharge enabled is not allowed to interrupt.
NOTE 6: Write burst interruption is allowed by another Write with Auto Precharge command.
NOTE 7: All command timings are referenced to burst length set in the mode register. They are not referenced to actual burst. For example, minimum Write to Precharge timing is WL + BL/2 + tWR where tWR starts with the rising clock after the uninterrupted burst end and not from the end of actual burst end.
Alliance Memory Inc. 551 Taylor Way, San Carlos, CA 94070
TEL: (650) 610-6800 FAX: (650) 620-9211
Alliance Memory Inc. reserves the right to change products or specification without notice.
44 Rev. 1.0 June 2013
AS4C128M8D2
Figure 29. Write data mask
Data Mask Timing
DQS
DQS#
DQ
V
IH(ac)
V
IH(dc)
V
IL(ac)
V
IL(dc) t
DS t
DH
V
IH(ac)
V
IH(dc)
V
IL(ac)
V
IL(dc) t
DS t
DH
DM
Data Mask Function, WL=3, AL=0, BL=4 shown
Case 1: min t
DQSS
CK#
CK
COMMAND
Write
WL
DQS
DQS#
DQ
DM
Case 2: max t
DQSS
DQS
DQS#
DQ
DM t
DQSS t
DQSS t
WR
Alliance Memory Inc. 551 Taylor Way, San Carlos, CA 94070
TEL: (650) 610-6800 FAX: (650) 620-9211
Alliance Memory Inc. reserves the right to change products or specification without notice.
45 Rev. 1.0 June 2013
AS4C128M8D2
Figure 30. Burst read operation followed by precharge:
(RL=4, AL=1, CL=3, BL=4, t
RTP
≦2 clocks)
T0 T1 T2 T3 T4
CK#
CK
T5 T6 T7 T8
CMD
Post CAS#
Read A
NOP
AL+BL'/2 clks
NOP
Precharge
NOP NOP
DQS
DQS#
AL=1
RL=4
CL=3
DQ
>=t
RAS
>=t
RTP
DOUTA
0
DOUTA
1
DOUTA
2
DOUTA
3
CL=3
Figure 31. Burst read operation followed by precharge:
(RL=4, AL=1, CL=3, BL=8, t
RTP
≦2 clocks)
T0 T1 T2 T3 T4
CK#
CK
T5 T6
NOP
>=t
RP
T7
Bank A
Active
T8
NOP
CMD
DQS
DQS#
DQ's
Post CAS#
READ A
NOP
AL + BL/2 clks
AL = 1
NOP
RL= 4
CL = 3
NOP NOP
Precharge A
NOP NOP
>=t
RTP
DOUT
A
0
DOUT
A
1
DOUT
A
2
DOUT
A
3
DOUT
A
4
DOUT
A
5
DOUT
A
6
DOUT
A
7
First 4-bit prefetch Second 4-bit prefetch
Alliance Memory Inc. 551 Taylor Way, San Carlos, CA 94070
TEL: (650) 610-6800 FAX: (650) 620-9211
Alliance Memory Inc. reserves the right to change products or specification without notice.
46 Rev. 1.0
NOP
June 2013
AS4C128M8D2
Figure 32. Burst read operation followed by precharge:
(RL=5, AL=2, CL=3, BL=4, t
RTP
≦2 clocks)
T0 T1 T2 T3 T4
CK#
CK
T5 T6 T7 T8
CMD
Post CAS#
READ A
NOP NOP NOP
Precharge A
NOP NOP
Bank A
Activate
AL + BL/2 clks
DQS
DQS#
AL = 2 CL = 3
RL= 5
DQ's
>=t
RAS
>=t
RTP
Figure 33. Burst read operation followed by precharge:
(RL=6, AL=2, CL=4, BL=4, t
RTP
≦2 clocks)
T0 T1 T2 T3 T4
CK#
CK
CL = 3
T5
>=t
RP
DOUT
A
0
DOUT
A
1
DOUT
A
2
DOUT
A
3
T6 T7 T8
NOP
CMD
DQS
DQS#
Post CAS#
READ A
NOP
AL + BL/2 clks
AL = 2
RL= 6
NOP
DQ's
>=t
RAS
>=t
RTP
NOP
CL = 4
Precharge A
CL = 4
NOP
>=t
RP
NOP
DOUT
A
0
DOUT
A
1
DOUT
A
2
DOUT
A
3
Alliance Memory Inc. 551 Taylor Way, San Carlos, CA 94070
TEL: (650) 610-6800 FAX: (650) 620-9211
Alliance Memory Inc. reserves the right to change products or specification without notice.
47 Rev. 1.0
Bank A
Activate
NOP
June 2013
AS4C128M8D2
Figure 34. Burst read operation followed by precharge:
(RL=4, AL=0, CL=4, BL=8, t
RTP
>2 clocks)
T0 T1 T2 T3 T4
CK#
CK
T5 T6 T7 T8
CMD
DQS
DQS#
AL = 0
DQ's
Post CAS#
READ A
NOP NOP
AL + 2 + max( t
RTP
, 2 t
CK
)*
NOP
CL = 4
RL= 4
>=t
RAS
>=t
RTP
NOP
Precharge A
NOP NOP
Bank A
Activate
>=t
RP
DOUT
A
0
DOUT
A
1
DOUT
A
2
DOUT
A
3
DOUT
A
4
DOUT
A
5
DOUT
A
6
DOUT
A
7
First 4-bit prefetch Second 4-bit prefetch
*: rounded to next integer.
Figure 35. Burst write operation followed by precharge: WL= (RL-1) =3
T0 T1 T2 T3 T4 T5
CK#
CK
T6 T7 T8
CMD
Post CAS#
Write A
DQS
DQS#
WL= 3
NOP
DQ's
NOP NOP NOP NOP NOP
Completion of the Burst Write
>=t
WR
NOP
Precharge A
DNA
0
DNA
1
DNA
2
DNA
3
Alliance Memory Inc. 551 Taylor Way, San Carlos, CA 94070
TEL: (650) 610-6800 FAX: (650) 620-9211
Alliance Memory Inc. reserves the right to change products or specification without notice.
48 Rev. 1.0 June 2013
AS4C128M8D2
Figure 36. Burst write followed by precharge: WL= (RL-1) =4
T0 T1 T2 T3 T4
CK#
CK
T5 T6 T7 T9
CMD
DQS
DQS#
Post CAS#
Write A
WL= 4
NOP NOP NOP NOP NOP NOP NOP
Completion of the Burst Write
>=t
WR
Precharge A
DQ's
DNA
0
DNA
1
DNA
2
DNA
3
Figure 37. Burst read operation with auto precharge:
(RL=4,AL=1, CL=3, BL=8, t
RTP
≦2 clocks)
T0 T1 T2 T3 T4
CK#
CK
T5 T6 T7 T8
CMD
DQS
DQS#
Post CAS#
READ A
Autoprecharge
DQ's
NOP NOP
AL + BL/2 clks
NOP NOP NOP NOP
>= t
RP
NOP
AL = 1
RL= 4
CL = 3
First 4-bit prefetch
>=t
RTP t
RTP
DOUT
A
0
DOUT
A
1
DOUT
A
2
DOUT
A
3
DOUT
A
4
DOUT
A
5
DOUT
A
6
DOUT
A
7
Second 4-bit prefetch Precharge begins here
Bank A
Activate
Alliance Memory Inc. 551 Taylor Way, San Carlos, CA 94070
TEL: (650) 610-6800 FAX: (650) 620-9211
Alliance Memory Inc. reserves the right to change products or specification without notice.
49 Rev. 1.0 June 2013
AS4C128M8D2
Figure 38. Burst read operation with auto precharge:
(RL=4, AL=1, CL=3, BL=4, t
RTP
>2 clocks)
T0 T1 T2 T3 T4
CK#
CK
T5 T6 T7 T8
CMD
Post CAS#
READ A
DQS
DQS#
Autoprecharge
AL= 1
NOP NOP NOP
>= AL+t
RTP
+t
RP
CL= 3
RL= 4
NOP NOP NOP
Bank A
Activate
NOP
DQ's t
RTP
DoutA
0
DoutA
1
DoutA
2
DoutA
3 t
RP
First 4-bit prefetch Precharge begins here
Figure 39. Burst read operation with auto precharge followed by activation to the same bank (t
RC
Limit): RL=5(AL=2, CL=3, internal t
RCD
=3, BL=4, t
RTP
≦2 clocks)
T0 T1 T2 T3 T4 T5 T6 T7 T8
CK#
CK
A10= 1
CMD
Post CAS#
READ A
NOP NOP NOP NOP NOP
>=t
RAS
(min)
Auto Precharge Begins
NOP NOP
Bank A
Activate
DQS
DQS#
AL= 2
RL= 5
CL= 3
>=t
RP
DQ's
DoutA
0
DoutA
1
DoutA
2
DoutA
3
CL=3
>= t
RC
Alliance Memory Inc. 551 Taylor Way, San Carlos, CA 94070
TEL: (650) 610-6800 FAX: (650) 620-9211
Alliance Memory Inc. reserves the right to change products or specification without notice.
50 Rev. 1.0 June 2013
AS4C128M8D2
Figure 40. Burst read operation with auto precharge followed by an activation to the same bank (t
RP
Limit): (RL=5 (AL=2, CL=3, internal t
RCD
=3, BL=4, t
RTP
≦2 clocks)
T0 T1 T2 T3 T4 T5 T6 T7 T8
CK#
CK
A10= 1
CMD
Post CAS#
READ A
NOP NOP
>=t
RAS
(min)
NOP NOP NOP
Auto Precharge Begins
NOP
Bank A
Activate
NOP
DQS
DQS#
AL= 2
RL= 5
CL= 3
>= t
RP
DQ's
DoutA
0
DoutA
1
DoutA
2
DoutA
3
CL=3
>= t
RC
Figure 41. Burst write with auto-precharge (t
RC
Limit): WL=2, WR=2, BL=4, t
RP
=3
T0 T1 T2 T3 T4 T5 T6
CK#
CK
A10 = 1
T7 Tm
CMD
Post CAS#
WRA Bank A
NOP NOP NOP
Bank A
Active
DQS
DQS#
WL= RL-1=2
NOP NOP
Completion of the Burst Write
NOP NOP
Auto Precharge Begins
>=WR >=t
RP
DQ's
DNA
0
DNA
1
DNA
2
DNA
3
>=t
RC
Alliance Memory Inc. 551 Taylor Way, San Carlos, CA 94070
TEL: (650) 610-6800 FAX: (650) 620-9211
Alliance Memory Inc. reserves the right to change products or specification without notice.
51 Rev. 1.0 June 2013
AS4C128M8D2
Figure 42. Burst write with auto-precharge (WR+t
RP
): WL=4, WR=2, BL=4, t
RP
=3
T0 T3 T4 T5 T6 T7 T8
CK#
CK
T9 T12
CMD
DQS
DQS#
DQ's
A10=1
Post CAS#
WRA Bank A
NOP NOP NOP NOP NOP NOP
Completion of the Burst Write
Auto Precharge Begins
NOP
>=WR >=t
RP
WL= RL-1=4
DNA
0
DNA
1
DNA
2
DNA
3
>=t
RC
Figure 43. Refresh command
T0 T1
CK#
CK
T2
HIGH
CKE
>=t
RP
T3
>=t
RFC
Tm Tn
>=t
RFC
Bank A
Active
Tn+1
CMD
Precharge
NOP NOP REF REF NOP ANY
Alliance Memory Inc. 551 Taylor Way, San Carlos, CA 94070
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52 Rev. 1.0 June 2013
AS4C128M8D2
Figure 44. Self refresh operation
T0 t
CH t
CK t
CL
T1 T2 T3
CK#
CK t
RP*
CKE
T4 T5 T6 Tm
>=t
XSRD
Tn
V
IH(ac)
>=t
XSNR t
AOFD
V
IL(ac) t
IS t
IS
ODT
CMD
V
IL(ac) t
IS t
IS t
IH t
IH
V
IH(ac)
V
IL(ac)
Self
Refresh
V
IH(dc)
V
IL(dc) t
IS
NOP NOP NOP t
IH
Valid
NOTE 1 Device must be in the "All banks idle" state prior to entering Self Refresh mode.
NOTE 2 ODT must be turned off t turned on again when t
XSRD
AOFD
before entering Self Refresh mode, and can be
timing is satisfied.
NOTE 3 t
XSRD
is applied for Read or a Read with autoprecharge command.
t
XSNR
is applied for any command except a Read or a Read with autoprecharge command.
Figure 45. Basic power down entry and exit timing diagram
CK
CK#
CKE t
IH t
IS t
IH t
IS t
IH t
IS t
IH
Command
VALID NOP t
CKE min
Enter Power-Down mode
NOP NOP VALID t
XP, t
XARD t
XARDS
Exit Power-Down mode t
CKE(min)
VALID or NOP
Don't Care
Figure 46. CKE intensive environment
CK#
CK t
CKE t
CKE
CKE t
CKE
NOTE: DRAM guarantees all AC and DC timing & voltage specifications and proper DLL operation with intensive CKE operation
Alliance Memory Inc. 551 Taylor Way, San Carlos, CA 94070
TEL: (650) 610-6800 FAX: (650) 620-9211
Alliance Memory Inc. reserves the right to change products or specification without notice.
53 Rev. 1.0 t
CKE
June 2013
DQ
DQS
DQS#
AS4C128M8D2
Figure 47. CKE intensive environment
CK#
CK
CKE t
CKE t
XP t
CKE t
XP t
CKE t
CKE
CMD
REF REF t
REFI
NOTE: The pattern shown above can repeat over a long period of time. With this pattern, DRAM guarantees all AC and DC timing & voltage specifications and DLL operation with temperature and voltage drift
Figure 48. Read to power-down entry
T0 T1 T2 Tx Tx+1
CK#
CK
Tx+2 Tx+3 Tx+4 Tx+5 Tx+6 Tx+7 Tx+8 Tx+9
CMD
CKE
RD
BL=4
Read operation starts with a read command and
CKE should be kept HIGH until the end of burst operation
AL+CL t
IS
DQ
DQS
DQS#
Q Q Q Q
T1 T2 Tx Tx+1 Tx+2 Tx+3 Tx+4 Tx+5 Tx+6 Tx+7 Tx+8 Tx+9
CK#
CK
T0
CMD
CKE
RD
BL=8
CKE should be kept HIGH until the end of burst operation
AL+CL t
IS
Q Q Q Q Q Q Q Q
Alliance Memory Inc. 551 Taylor Way, San Carlos, CA 94070
TEL: (650) 610-6800 FAX: (650) 620-9211
Alliance Memory Inc. reserves the right to change products or specification without notice.
54 Rev. 1.0 June 2013
AS4C128M8D2
Figure 49. Read with autoprecharge to power-down entry
T0 T1 T2 Tx Tx+1 Tx+2 Tx+3
CK#
CK
Tx+4 Tx+5 Tx+6 Tx+7 Tx+8 Tx+9
CMD
CKE
RDA
BL=4
PRE
AL+BL/2 with t
RTP
& t
RAS
= 7.5ns
min satisfied
AL+CL
Q Q Q Q
CKE should be kept HIGH until the end of burst operation t
IS
DQ
DQS
DQS#
T0 T1 T2 Tx Tx+1 Tx+2 Tx+3 Tx+4 Tx+5 Tx+6 Tx+7 Tx+8 Tx+9
CK#
CK
CMD
CKE
RD
BL=8
Start internal precharge
PRE
AL+BL/2 with t
& t
RAS
RTP
= 7.5ns
min satisfied
AL+CL
Q Q Q Q Q Q Q Q
CKE should be kept HIGH until the end of burst operation t
IS
DQ
DQS
DQS#
Figure 50. Write to power-down entry
T0 T1 Tm Tm+1 Tm+2
CK#
CK
Tm+3 Tx Tx+1 Tx+2 Ty Ty+1 Ty+2 Ty+3
CMD
CKE
WR
BL=4
WL t
IS
DQ
DQS
DQS#
Q Q Q Q t
WTR
CK#
CK
T0 T1 Tm Tm+1 Tm+2 Tm+3 Tm+4 Tm+5 Tx Tx+1
CMD
CKE
WR
BL=8
WL
DQ Q Q Q Q Q Q Q Q t
WTR
DQS
DQS#
Alliance Memory Inc. 551 Taylor Way, San Carlos, CA 94070
TEL: (650) 610-6800 FAX: (650) 620-9211
Alliance Memory Inc. reserves the right to change products or specification without notice.
55 Rev. 1.0 t
IS
Tx+2 Tx+3 Tx+4
June 2013
AS4C128M8D2
Figure 51. Write with autoprecharge to power-down entry
T0 T1 Tm Tm+1 Tm+2 Tm+3 Tx
CK#
CK
Tx+1 Tx+2 Tx+3 Tx+4 Tx+5 Tx+6
CMD
CKE
WRA
BL=4
PRE
WL t
IS
DQ
DQS
DQS#
Q Q Q Q
WR*1
CK#
CK
CMD
CKE
T0
DQ
DQS
DQS#
T1
WRA
BL=8
Tm Tm+1 Tm+2 Tm+3 Tm+4 Tm+5 Tx Tx+1 Tx+2 Tx+3 Tx+4
PRE
Start internal Precharge
WL
Q Q Q Q Q Q Q Q t
IS
WR*1
*1: WR is programmed through MRS
Alliance Memory Inc. 551 Taylor Way, San Carlos, CA 94070
TEL: (650) 610-6800 FAX: (650) 620-9211
Alliance Memory Inc. reserves the right to change products or specification without notice.
56 Rev. 1.0 June 2013
AS4C128M8D2
Figure 52. Refresh command to power-down entry
T0 T1 T2 T3 T4 T5
CK#
CK
T6 T7 T8 T9 T10 T11
CMD REF
CKE can go to LOW one clock after an Auto-refresh command
CKE t
IS
Figure 53. Active command to power-down entry
T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11
CMD ACT
CKE can go to LOW one clock after an Active command
CKE t
IS
Figure 54. Precharge/precharge-all command to power-down entry
T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10
CMD PR or PRA
CKE can go to LOW one clock after a Precharge or Precharge all command
CKE t
IS
Figure 55. MRS/EMRS command to power-down entry
T0 T1 T2 T3 T4 T5 T6 T7
CMD
MRS or
EMRS t
MRD
CKE t
IS
T8
Alliance Memory Inc. 551 Taylor Way, San Carlos, CA 94070
TEL: (650) 610-6800 FAX: (650) 620-9211
Alliance Memory Inc. reserves the right to change products or specification without notice.
57 Rev. 1.0
T9 T10
T11
T11
June 2013
AS4C128M8D2
Figure 56. Asynchronous CKE LOW event
Stable clocks t
CK
CK#
CK
CKE t
Delay t
IS
CKE asynchronously drops LOW
Clocks can be turned off after this point
Figure 57. Clock frequency change in precharge power down mode
T0 T1 T2 T4 Tx Tx+1 Ty Ty+1 Ty+2
CK#
CK
CMD NOP NOP NOP
Frequency Change Occurs here
CKE t
IS
ODT t
IS t
RP t
AOFD t
XP
Ty+3
NOP
Minimum 2 clocks required before changing frequency
Stable new clock before power down exit
Ty+4
DLL
RESET
NOP
Tz
Valid
200 Clocks t
IH
ODT is off during DLL RESET
Alliance Memory Inc. 551 Taylor Way, San Carlos, CA 94070
TEL: (650) 610-6800 FAX: (650) 620-9211
Alliance Memory Inc. reserves the right to change products or specification without notice.
58 Rev. 1.0 June 2013
AS4C128M8D2
Figure 58. 60-Ball FBGA Package Outline Drawing Information
PIN A1 INDEX
Top View Bottom View
Side View
DETAIL : "A"
Symbol
A
A1
D
E
D1
E1
F e b
D2
Dimension in inch Dimension in mm
Min Nom Max Min Nom Max
-- -- 0.047 -- -- 1.20
0.010 -- 0.016 0.25 -- 0.40
0.311
0.340
--
0.315
0.394
0.252
0.319
0.0.398
--
7.90
9.90
--
8.00
10.00
6.40
8.10
10.10
--
--
--
--
0.016
--
0.315
0.126
0.031
0.018
--
--
--
--
0.020
0.081
--
--
--
0.40
--
8.00
3.20
0.80
0.45
--
--
--
--
0.50
2.05
Alliance Memory Inc. 551 Taylor Way, San Carlos, CA 94070
TEL: (650) 610-6800 FAX: (650) 620-9211
Alliance Memory Inc. reserves the right to change products or specification without notice.
59 Rev. 1.0 June 2013
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