Silicon Laboratories SI5351A/B/C Datasheet

Si5351A/B/C-B
I 2 C - P R O G R A M M A B L E A NY -F R E Q U E N C Y C M O S C LO CK
G EN ER ATO R + V C X O
Features
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www.silabs.com/custom-timing
Generates up to 8 non-integer-related
frequencies from 2.5 kHz to 200 MHz


I2C user definable configuration
Exact frequency synthesis at each output

(0 ppm error)
Highly linear VCXO

Optional clock input (CLKIN)
Low output period jitter: < 70 ps pp, typ 
Configurable spread spectrum selectable 

at each output
Operates from a low-cost, fixed frequency 

crystal: 25 or 27 MHz

Supports static phase offset
Programmable rise/fall time control
Glitchless frequency changes
Separate voltage supply pins provide
level translation:
Core VDD: 2.5 or 3.3 V
Output VDDO: 1.8, 2.5, or 3.3 V
Excellent PSRR eliminates external
power supply filtering
Very low power consumption
Adjustable output delay
Available in 2 packages types:
10-MSOP: 3 outputs
20-QFN (4x4 mm): 8 outputs
PCIE Gen 1 compatible
Supports HCSL compatible swing
10-MSOP
20-QFN
Ordering Information:
See page 29
Applications
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HDTV, DVD/Blu-ray, set-top box
Audio/video equipment, gaming
 Printers, scanners, projectors
 Handheld Instrumentation
Residential gateways
Networking/communication
 Servers, storage
 XO replacement
Description
The Si5351 is an I2C configurable clock generator that is ideally suited for replacing
crystals, crystal oscillators, VCXOs, phase-locked loops (PLLs), and fanout buffers in
cost-sensitive applications. Based on a PLL/VCXO + high resolution MultiSynth fractional
divider architecture, the Si5351 can generate any frequency up to 200 MHz on each of its
outputs with 0 ppm error. Three versions of the Si5351 are available to meet a wide
variety of applications. The Si5351A generates up to 8 free-running clocks using an
internal oscillator for replacing crystals and crystal oscillators. The Si5351B adds an
internal VCXO and provides the flexibility to replace both free-running clocks and
synchronous clocks. It eliminates the need for higher cost, custom pullable crystals while
providing reliable operation over a wide tuning range. The Si5351C offers the same
flexibility but synchronizes to an external reference clock (CLKIN).
Functional Block Diagram
Si5351C (20-QFN)
Si5351B (20-QFN)
XA
OSC
PLL
MultiSynth
1
XB
VCXO
VC
SDA
SCL
OEB
SSEN
Rev. 1.0 4/15
I2C
Control
Logic
MultiSynth
0
VDDOA
R0
R1
CLK0
CLK1
XA
OSC
XB
VDDOB
MultiSynth
2
R2
MultiSynth
3
R3
MultiSynth
4
R4
MultiSynth
5
R5
CLK2
CLK4
CLK5
VDDOD
MultiSynth
6
R6
MultiSynth
7
R7
PLL
B
CLKIN
CLK3
VDDOC
CLK6
CLK7
Copyright © 2015 by Silicon Laboratories
SDA
SCL
I2C
INTR
OEB
PLL
A
Control
Logic
VDDOA
MultiSynth
0
R0
MultiSynth
1
R1
CLK0
CLK1
VDDOB
MultiSynth
2
R2
MultiSynth
3
R3
MultiSynth
4
R4
MultiSynth
5
R5
MultiSynth
6
R6
MultiSynth
7
R7
CLK2
CLK3
VDDOC
CLK4
CLK5
VDDOD
CLK6
CLK7
Si5351A/B/C-B
Si5351A/B/C-B
Table 1. The Complete Si5350/51 Clock Generator Family
Part Number
I2C or Pin
Frequency Reference
Programmed?
Outputs
Datasheet
Si5351A-B-GT
I2C
XTAL only
Blank
3
Si5351-B
Si5351A-B-GM
I2C
XTAL only
Blank
8
Si5351-B
Si5351B-B-GM
I2C
XTAL and/or Voltage
Blank
8
Si5351-B
Si5351C-B-GM
I2C
XTAL and/or CLKIN
Blank
8
Si5351-B
Si5351A-Bxxxxx-GT
I2C
XTAL only
Factory Pre-Programmed
3
Si5351-B
Si5351A-Bxxxxx-GM
I2C
XTAL only
Factory Pre-Programmed
8
Si5351-B
Si5351B-Bxxxxx-GM
I2C
XTAL and/or Voltage
Factory Pre-Programmed
8
Si5351-B
Si5351C-Bxxxxx-GM
I2C
XTAL and/or CLKIN
Factory Pre-Programmed
8
Si5351-B
Si5350A-Bxxxxx-GT
Pin
XTAL only
Factory Pre-Programmed
3
Si5350A-B
Si5350A-Bxxxxx-GM
Pin
XTAL only
Factory Pre-Programmed
8
Si5350A-B
Si5350B-Bxxxxx-GT
Pin
XTAL and/or Voltage
Factory Pre-Programmed
3
Si5350B-B
Si5350B-Bxxxxx-GM
Pin
XTAL and/or Voltage
Factory Pre-Programmed
8
Si5350B-B
Si5350C-Bxxxxx-GT
Pin
XTAL and/or CLKIN
Factory Pre-Programmed
3
Si5350C-B
Si5350C-Bxxxxx-GM
Pin
XTAL and/or CLKIN
Factory Pre-Programmed
8
Si5350C-B
Notes:
1. XTAL = 25/27 MHz, Voltage = 0 to VDD, CLKIN = 10 to 100 MHz. "xxxxx" = unique custom code.
2. Create custom, factory pre-programmed parts at www.silabs.com/ClockBuilder.
2
Rev. 1.0
Si5351A/B/C-B
TABLE O F C ONTENTS
Section
Page
1. Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5
2. Detailed Block Diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
3. Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
3.1. Input Stage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
3.2. Synthesis Stages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
3.3. Output Stage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15
3.4. Spread Spectrum . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
3.5. Control Pins (OEB, SSEN) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
4. I2C Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
5. Configuring the Si5351 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
5.1. Writing a Custom Configuration to RAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
5.2. Si5351 Application Examples . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
5.3. Replacing Crystals and Crystal Oscillators . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
5.4. Replacing Crystals, Crystal Oscillators, and VCXOs . . . . . . . . . . . . . . . . . . . . . . . .20
5.5. Replacing Crystals, Crystal Oscillators, and PLLs . . . . . . . . . . . . . . . . . . . . . . . . . . 21
5.6. Applying a Reference Clock at XTAL Input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
5.7. HCSL Compatible Outputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
6. Design Considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23
6.1. Power Supply Decoupling/Filtering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
6.2. Power Supply Sequencing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
6.3. External Crystal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23
6.4. External Crystal Load Capacitors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
6.5. Unused Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23
6.6. Trace Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
7. Register Map Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
8. Register Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24
9. Si5351 Pin Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
9.1. Si5351A 20-pin QFN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25
9.2. Si5351B 20-Pin QFN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26
9.3. Si5351C 20-Pin QFN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
9.4. Si5351A 10-Pin MSOP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
10. Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
11. Package Outlines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
11.1. 20-pin QFN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30
12. Land Pattern: 20-Pin QFN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
12.1. 10-Pin MSOP Package Outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
13. Land Pattern: 10-Pin MSOP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
14. Top Marking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .38
14.1. 20-Pin QFN Top Marking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
14.2. Top Marking Explanation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
14.3. 10-Pin MSOP Top Marking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
Rev. 1.0
3
Si5351A/B/C-B
14.4. Top Marking Explanation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
Document Change List . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .40
Contact Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .41
4
Rev. 1.0
Si5351A/B/C-B
1. Electrical Specifications
Table 2. Recommended Operating Conditions
Parameter
Symbol
Ambient Temperature
TA
Core Supply Voltage
VDD
Output Buffer Voltage
Test Condition
VDDOx
Min
Typ
Max
Unit
–40
25
85
°C
3.0
3.3
3.60
V
2.25
2.5
2.75
V
1.71
1.8
1.89
V
2.25
2.5
2.75
V
3.0
3.3
3.60
V
Notes:All minimum and maximum specifications are guaranteed and apply across the recommended operating conditions.
Typical values apply at nominal supply voltages and an operating temperature of 25 °C unless otherwise noted.
VDD and VDDOx can be operated at independent voltages.
Power supply sequencing for VDD and VDDOx requires that all VDDOx be powered up either before or at the same
time as VDD.
Table 3. DC Characteristics
(VDD = 2.5 V ±10%, or 3.3 V ±10%, TA = –40 to 85 °C)
Parameter
Core Supply Current
Output Buffer Supply Current
(Per Output)*
Input Current
Output Impedance
Symbol
Test Condition
Min
Typ
Max
Unit
Enabled 3 outputs
—
22
35
mA
Enabled 8 outputs
—
27
45
mA
IDDOx
CL = 5 pF
—
2.2
5.6
mA
ICLKIN
CLKIN, SDA, SCL
Vin < 3.6 V
—
—
10
µA
IVC
VC
—
—
30
µA
ZO
3.3 V VDDO, default high
drive
—
50
—

IDD
*Note: Output clocks less than or equal to 100 MHz.
Rev. 1.0
5
Si5351A/B/C-B
Table 4. AC Characteristics
(VDD = 2.5 V ±10%, or 3.3 V ±10%, TA = –40 to 85 °C)
Parameter
Symbol
Test Condition
Min
Typ
Max
Unit
Power-up Time
TRDY
From VDD = VDDmin to valid
output clock, CL = 5 pF,
fCLKn > 1 MHz
—
2
10
ms
Power-up Time, PLL Bypass
Mode
TBYP
From VDD = VDDmin to valid
output clock, CL = 5 pF,
fCLKn > 1 MHz
—
0.5
1
ms
Output Enable Time
TOE
From OEB pulled low to valid
clock output, CL = 5 pF,
fCLKn > 1 MHz
—
—
10
µs
Output Frequency Transition
Time
TFREQ
fCLKn > 1 MHz
—
—
10
µs
Output Phase Offset
PSTEP
—
333
—
ps/step
Down spread. Selectable in 0.1%
steps.
–0.1
—
–2.5
%
Center spread. Selectable in
0.1% steps.
±0.1
—
±1.5
%
30
31.5
33
kHz
0
VDD/2
VDD
V
Spread Spectrum Frequency
Deviation
SSDEV
Spread Spectrum Modulation
Rate
SSMOD
VCXO Specifications (Si5351B only)
VCXO Control Voltage Range
Vc
VCXO Gain (configurable)
Kv
Vc = 10–90% of VDD, VDD = 3.3 V
18
—
150
ppm/V
VCXO Control Voltage Linearity
KVL
Vc = 10–90% of VDD
–5
—
+5
%
VCXO Pull Range
(configurable)
PR
VDD = 3.3 V*
±30
0
±240
ppm
—
10
—
kHz
VCXO Modulation Bandwidth
*Note: Contact Silicon Labs for 2.5 V VCXO operation.
Table 5. Input Clock Characteristics
(VDD = 2.5 V ±10%, or 3.3 V ±10%, TA = –40 to 85 °C)
Parameter
Min
Typ
Max
Unit
fXTAL
25
—
27
MHz
CLKIN Input Low Voltage
VIL
–0.1
—
0.3 x VDD
V
CLKIN Input High Voltage
VIH
0.7 x VDD
—
3.60
V
CLKIN Frequency Range
fCLKIN
10
—
100
MHz
Crystal Frequency
6
Symbol
Test Condition
Rev. 1.0
Si5351A/B/C-B
Table 6. Output Clock Characteristics
(VDD = 2.5 V ±10%, or 3.3 V ±10%, TA = –40 to 85 °C)
Parameter
Symbol
Test Condition
Min
Typ
Max
Unit
Frequency Range1
FCLK
0.0025
—
200
MHz
Load Capacitance
CL
—
—
15
pF
FCLK < 160 MHz, Measured
at VDD/2
45
50
55
%
FCLK > 160 MHz, Measured
at VDD/2
40
50
60
%
—
1
1.5
ns
—
1
1.5
ns
VDD – 0.6
—
—
V
—
—
0.6
V
20-QFN, 4 outputs running,
1 per VDDO
—
40
95
ps, pkpk
10-MSOP or 20-QFN,
all outputs running
—
70
155
ps, pkpk
20-QFN, 4 outputs running,
1 per VDDO
—
50
90
ps, pk
10-MSOP or 20-QFN,
all outputs running
—
70
150
ps, pk
20-QFN, 4 outputs running,
1 per VDDO
—
50
95
ps, pkpk
10-MSOP or 20-QFN,
all outputs running
—
70
155
ps, pkpk
20-QFN, 4 outputs running,
1 per VDDO
—
50
90
ps, pk
10-MSOP or 20-QFN,
all outputs running
—
70
150
ps, pk
Duty Cycle
DC
tr
Rise/Fall Time
tf
Output High Voltage
VOH
Output Low Voltage
VOL
Period Jitter2,3
Cycle-to-Cycle Jitter
JPER
2,3
Period Jitter VCXO2,3
Cycle-to-Cycle Jitter
VCXO2,3
JCC
JPER_VCXO
JCC_VCXO
20%–80%, CL = 5 pF,
Default high drive strength
CL = 5 pF
Notes:
1. Only two unique frequencies above 112.5 MHz can be simultaneously output.
2. Measured over 10K cycles. Jitter is only specified at the default high drive strength (50  output impedance).
3. Jitter is highly dependent on device frequency configuration. Specifications represent a “worst case, real world”
frequency plan; actual performance may be substantially better. Three-output 10 MSOP package measured with clock
outputs of 74.25, 24.576, and 48 MHz. Eight-output 20 QFN package measured with clock outputs of 33.333, 74.25,
27, 24.576, 22.5792, 28.322, 125, and 48 MHz.
Rev. 1.0
7
Si5351A/B/C-B
Table 7. Crystal Requirements1,2
Parameter
Symbol
Min
Typ
Max
Unit
Crystal Frequency
fXTAL
25
—
27
MHz
Load Capacitance
CL
6
—
12
pF
rESR
—
—
150

dL
100
—
—
µW
Equivalent Series Resistance
Crystal Max Drive Level
Notes:
1. Crystals which require load capacitances of 6, 8, or 10 pF should use the device’s internal load capacitance for
optimum performance. See register 183 bits 7:6. A crystal with a 12 pF load capacitance requirement should use a
combination of the internal 10 pF load capacitance in addition to external 2 pF load capacitance (e.g., by using 4 pF
capacitors on XA and XB).
2. Refer to “AN551: Crystal Selection Guide” for more details.
Table 8. I2C Specifications (SCL,SDA)1
Parameter
Symbol
LOW Level
Input Voltage
VILI2C
HIGH Level
Input Voltage
VIHI2C
Hysteresis of
Schmitt Trigger
Inputs
VHYS
LOW Level
Output Voltage
(open drain or
open collector)
at 3 mA Sink
Current
VOLI2C2
Test Condition
Standard Mode
100 kbps
Fast Mode
400 kbps
Min
Max
Min
Max
–0.5
0.3 x VDDI2
–0.5
0.3 x VDDI2C2
V
3.6
0.7 x VDDI2C2
3.6
V
—
—
0.1
—
V
0
0.4
0
0.4
V
–10
10
–10
10
µA
C
0.7 x VDDI2
C
VDDI2C2 = 2.5/3.3 V
Unit
Input Current
III2C
Capacitance for
Each I/O Pin
CII2C
VIN = –0.1 to VDDI2C
—
4
—
4
pF
I2C Bus
Timeout
TTO
Timeout Enabled
25
35
25
35
ms
Notes:
1. Refer to NXP’s UM10204 I2C-bus specification and user manual, revision 03, for further details, go to:
www.nxp.com/acrobat_download/usermanuals/UM10204_3.pdf.
2. Only I2C pullup voltages (VDDI2C) of 2.25 to 3.63 V are supported.
8
Rev. 1.0
Si5351A/B/C-B
Table 9. Thermal Characteristics
Parameter
Symbol
Test Condition
Thermal Resistance
Junction to Ambient
JA
Still Air
Thermal Resistance
Junction to Case
JC
Still Air
Package
Value
Unit
10-MSOP
131
°C/W
20-QFN
119
°C/W
20-QFN
16
°C/W
Value
Unit
–0.5 to 3.8
V
Table 10. Absolute Maximum Ratings1
Parameter
DC Supply Voltage
Symbol
Test Condition
VDD_max
VIN_CLKIN
CLKIN, SCL, SDA
–0.5 to 3.8
V
VIN_VC
VC
–0.5 to (VDD+0.3)
V
VIN_XA/B
Pins XA, XB
–0.5 to 1.3 V
V
TJ
–55 to 150
°C
Soldering Temperature (Pb-free
profile)2
TPEAK
260
°C
Soldering Temperature Time at
TPEAK (Pb-free profile)2
TP
20–40
Sec
Input Voltage
Junction Temperature
Notes:
1. Permanent device damage may occur if the absolute maximum ratings are exceeded. Functional operation should be
restricted to the conditions as specified in the operational sections of this data sheet. Exposure to absolute maximum
rating conditions for extended periods may affect device reliability.
2. The device is compliant with JEDEC J-STD-020.
Rev. 1.0
9
Si5351A/B/C-B
2. Detailed Block Diagrams
VDD
Si5351A 3-Output
VDDO
PLL
A
MultiSynth
0
R0
CLK0
PLL
B
MultiSynth
1
R1
CLK1
MultiSynth
2
R2
CLK2
XA
OSC
XB
SDA
SCL
I2C
Interface
10-MSOP
GND
VDD
Si5351A 8-Output
VDDOA
MultiSynth
0
R0
MultiSynth
1
R1
MultiSynth
2
R2
MultiSynth
3
R3
MultiSynth
4
R4
SCL
MultiSynth
5
R5
OEB
MultiSynth
6
R6
MultiSynth
7
R7
PLL
A
XA
OSC
PLL
B
XB
A0
SDA
SSEN
I2C
Interface
Control
Logic
CLK0
CLK1
VDDOB
CLK2
CLK3
VDDOC
CLK4
CLK5
VDDOD
CLK6
CLK7
20-QFN
GND
Figure 1. Block Diagrams of 3-Output and 8-Output Si5351A Devices
10
Rev. 1.0
Si5351A/B/C-B
VDD
XA
OSC
PLL
XB
VCXO
VC
SDA
I2C
SCL
Interface
OEB
Control
Logic
SSEN
Si5351B
VDDOA
MultiSynth
0
R0
MultiSynth
1
R1
MultiSynth
2
R2
MultiSynth
3
R3
MultiSynth
4
R4
MultiSynth
5
R5
MultiSynth
6
R6
MultiSynth
7
R7
VDDOB
SCL
INTR
OEB
Control
Logic
CLK5
CLK6
CLK7
VDDOA
R0
MultiSynth
1
R1
MultiSynth
2
R2
MultiSynth
3
R3
MultiSynth
4
R4
MultiSynth
5
R5
MultiSynth
6
R6
MultiSynth
7
R7
PLL
B
I2C
Interface
CLK4
VDDOD
MultiSynth
0
PLL
A
SDA
CLK3
Si5351C
XA
CLKIN
CLK2
VDDOC
VDD
XB
CLK1
20-QFN
GND
OSC
CLK0
CLK0
CLK1
VDDOB
CLK2
CLK3
VDDOC
CLK4
CLK5
VDDOD
CLK6
CLK7
20-QFN
GND
Figure 2. Block Diagrams of Si5351B and Si5351C 8-Output Devices
Rev. 1.0
11
Si5351A/B/C-B
3. Functional Description
The Si5351 is a versatile I2C programmable clock generator that is ideally suited for replacing crystals, crystal
oscillators, VCXOs, PLLs, and buffers. A block diagram showing the general architecture of the Si5351 is shown in
Figure 3. The device consists of an input stage, two synthesis stages, and an output stage.
The input stage accepts an external crystal (XTAL), a control voltage input (VC), or a clock input (CLKIN)
depending on the version of the device (A/B/C). The first stage of synthesis multiplies the input frequencies to an
high-frequency intermediate clock, while the second stage of synthesis uses high resolution MultiSynth fractional
dividers to generate the desired output frequencies. Additional integer division is provided at the output stage for
generating output frequencies as low as 2.5 kHz. Crosspoint switches at each of the synthesis stages allows total
flexibility in routing any of the inputs to any of the outputs.
Because of this high resolution and flexible synthesis architecture, the Si5351 is capable of generating
synchronous or free-running non-integer related clock frequencies at each of its outputs, enabling one device to
synthesize clocks for multiple clock domains in a design.
Input
Stage
CLKIN
Synthesis
Stage 1
Div
PLL A
(SSC)
XA
OSC
XTAL
XB
VC
VCXO
PLL B
(VCXO)
Synthesis
Stage 2
Output
Stage
VDDOA
Multi
Synth
0
R0
Multi
Synth
1
R1
Multi
Synth
2
R2
Multi
Synth
3
R3
Multi
Synth
4
R4
Multi
Synth
5
R5
Multi
Synth
6
R6
Multi
Synth
7
R7
Rev. 1.0
CLK1
VDDOB
CLK2
CLK3
VDDOC
CLK4
CLK5
VDDOD
Figure 3. Si5351 Block Diagram
12
CLK0
CLK6
CLK7
Si5351A/B/C-B
3.1. Input Stage
3.1.1. Crystal Inputs (XA, XB)
The Si5351 uses a fixed-frequency standard AT-cut crystal as a reference to the internal oscillator. The output of
the oscillator can be used to provide a free-running reference to one or both of the PLLs for generating
asynchronous clocks. The output frequency of the oscillator will operate at the crystal frequency, either 25 MHz or
27 MHz. The crystal is also used as a reference to the VCXO to help maintain its frequency accuracy.
Internal load capacitors are provided to eliminate the need for external components when connecting a crystal to
the Si5351. The total internal XTAL load capacitance (CL) can be selected to be 0, 6, 8, or 10 pF. Crystals with
alternate load capacitance requirements are supported using additional external load capacitance  2 pF (e.g., by
using  4 pF capacitors on XA and XB) as shown in Figure 4. Refer to application note AN551 for crystal
recommendations.
XA
XB
Optional internal
load capacitance
0, 6, 8,10 pF
Optional additional
external load
capacitance
(< 2 pF)
Figure 4. External XTAL with Optional Load Capacitors
3.1.2. External Clock Input (CLKIN)
The external clock input is used as a clock reference for the PLLs when generating synchronous clock outputs.
CLKIN can accept any frequency from 10 to 100 MHz. A divider at the input stage limits the PLL input frequency to
30 MHz.
3.1.3. Voltage Control Input (VC)
The VCXO architecture of the Si5351B eliminates the need for an external pullable crystal. Only a standard, lowcost, fixed-frequency (25 or 27 MHz) AT-cut crystal is required.
The tuning range of the VCXO is configurable allowing for a wide variety of applications. Key advantages of the
VCXO design in the Si5351 include high linearity, a wide operating range (linear from 10 to 90% of VDD), and
reliable startup and operation. Refer to Table 4 on page 6 for VCXO specification details.
A unique feature of the Si5351B is its ability to generate multiple output frequencies controlled by the same control
voltage applied to the VC pin. This replaces multiple PLLs or VCXOs that would normally be locked to the same
reference. An example is illustrated in Figure 5 on page 14.
Rev. 1.0
13
Si5351A/B/C-B
3.2. Synthesis Stages
The Si5351 uses two stages of synthesis to generate its final output clocks. The first stage uses PLLs to multiply
the lower frequency input references to a high-frequency intermediate clock. The second stage uses highresolution MultiSynth fractional dividers to generate the required output frequencies. Only two unique frequencies
above 112.5 MHz can be simultaneously output. For example, 125 MHz (CLK0), 130 MHz (CLK1), and 150 MHz
(CLKx) is not allowed. Note that multiple copies of frequencies above 112.5 MHz can be provided, for example,
125 MHz could be provided on four outputs (CLKS0-3) simultaneously with 130 MHz on four different outputs
(CLKS4-7).
A crosspoint switch at the input of the first stage allows each of the PLLs to lock to the CLKIN or the XTAL input.
This allows each of the PLLs to lock to a different source for generating independent free-running and synchronous
clocks. Alternatively, both PLLs could lock to the same source. The crosspoint switch at the input of the second
stage allows any of the MultiSynth dividers to connect to PLLA or PLLB. This flexible synthesis architecture allows
any of the outputs to generate synchronous or non-synchronous clocks, with spread spectrum or without spread
spectrum, and with the flexibility of generating non-integer related clock frequencies at each output.
All VCXO outputs are generated by PLLB only. The Multisynth high-resolution dividers synthesizes the VCXO
output’s center frequency up to 112.5 MHz. The center frequency is then controlled (or pulled) by the VC input. An
interesting feature of the Si5351 is that the VCXO output can be routed to more than one MultiSynth divider. This
creates a VCXO with multiple output frequencies controlled from one VC input as shown in Figure 5.
Frequencies down to 2.5 kHz can be generated by applying the R divider at the output of the Multisynth (see
Figure 5 below).
XA
Control VC
Voltage
XB
Fixed Frequency
Crystal (non-pullable)
OSC
Multi
Synth
0
R0
CLK0
VCXO
Multi
Synth
1
R1
CLK1
Multi
Synth
2
R2
CLK2
The clock frequency
generated from CLK0 is
controlled by the VC input
Additional MultiSynths
can be “linked” to the
VCXO to generate
additional clock
frequencies
Figure 5. Using the Si5351 as a Multi-Output VCXO
14
Rev. 1.0
Si5351A/B/C-B
3.3. Output Stage
An additional level of division (R) is available at the output stage for generating clocks as low as 2.5 kHz. All output
drivers generate CMOS level outputs with separate output voltage supply pins (VDDOx) allowing a different voltage
signal level (1.8, 2.5, or 3.3 V) at each of the four 2-output banks.
3.4. Spread Spectrum
Spread spectrum can be enabled on any of the clock outputs that use PLLA as its reference. Spread spectrum is
useful for reducing electromagnetic interference (EMI). Enabling spread spectrum on an output clock modulates its
frequency, which effectively reduces the overall amplitude of its radiated energy. Note that spread spectrum is not
available on clocks synchronized to PLLB or to the VCXO.
The Si5351 supports several levels of spread spectrum allowing the designer to chose an ideal compromise
between system performance and EMI compliance.
Reduced
Amplitude
and EMI
Reduced
Amplitude
and EMI
Center
Frequency
Amplitude
fc
fc
fc
No Spread
Spectrum
Center Spread
Down Spread
Figure 6. Available Spread Spectrum Profiles
3.5. Control Pins (OEB, SSEN)
The Si5351 offers control pins for enabling/disabling clock outputs and spread spectrum.
3.5.1. Output Enable (OEB)
The output enable pin allows enabling or disabling outputs clocks. Output clocks are enabled when the OEB pin is
held low, and disabled when pulled high. When disabled, the output state is configurable as output high, output low,
or high-impedance.
The output enable control circuitry ensures glitchless operation by starting the output clock cycle on the first leading
edge after OEB is pulled low. When OEB is pulled high, the clock is allowed to complete its full clock cycle before
going into a disabled state.
3.5.2. Spread Spectrum Enable (SSEN)—Si5351A and Si5351B only
This control pin allows disabling the spread spectrum feature for all outputs that were configured with spread
spectrum enabled. Hold SSEN low to disable spread spectrum. The SSEN pin provides a convenient method of
evaluating the effect of using spread spectrum clocks during EMI compliance testing.
Rev. 1.0
15
Si5351A/B/C-B
4. I2C Interface
Many of the functions and features of the Si5351 are controlled by reading and writing to the RAM space using the
I2C interface. The following is a list of the common features that are controllable through the I2C interface. For a
complete listing of available I2C registers and programming steps, please see “AN619: Manually Generating an
Si5351 Register Map.”
Read Status Indicators
Crystal
Reference Loss of signal, LOS_XTAL, reg0[3]
Loss of signal, LOS_CLKIN, reg0[4]
PLLA and/or PLLB Loss of lock, LOL_A or LOL_B, reg0[6:5]
CLKIN
Configuration
of multiplication and divider values for the PLLs, MultiSynth dividers
of the Spread Spectrum profile (down or center spread, modulation percentage)
Control of the cross point switch selection for each of the PLLs and MultiSynth dividers
Set output clock options
Configuration
Enable/disable
for each clock output
for each clock output
Invert/non-invert
divider values (2n, n=1.. 7)
Output state when disabled (stop hi, stop low, Hi-Z)
Output phase offset
Output
The I2C interface operates in slave mode with 7-bit addressing and can operate in Standard-Mode (100 kbps) or
Fast-Mode (400 kbps) and supports burst data transfer with auto address increments.
The I2C bus consists of a bidirectional serial data line (SDA) and a serial clock input (SCL) as shown in Figure 7.
Both the SDA and SCL pins must be connected to the VDD supply via an external pull-up as recommended by the
I2C specification.
VDD
>1k
>1k
Si5351
SCL
I2C Bus
SDA
4.7 k
INTR
I2C Address Select:
A0
Pull-up to VDD (A0 = 1)
Pull-down to GND (A0 = 0)
Figure 7. I2C and Control Signals
The 7-bit device (slave) address of the Si5351 consist of a 6-bit fixed address plus a user selectable LSB bit as
shown in Figure 8. The LSB bit is selectable as 0 or 1 using the optional A0 pin which is useful for applications that
require more than one Si5351 on a single I2C bus.
Slave Address
6
5
4
3
2
1
0
1
1
0
0
0
0 0/1
A0
Figure 8. Si5351 I2C Slave Address
16
Rev. 1.0
Si5351A/B/C-B
Data is transferred MSB first in 8-bit words as specified by the I2C specification. A write command consists of a 7bit device (slave) address + a write bit, an 8-bit register address, and 8 bits of data as shown in Figure 9. A write
burst operation is also shown where every additional data word is written using to an auto-incremented address.
Write Operation – Single Byte
S Slv Addr [6:0] 0 A Reg Addr [7:0] A Data [7:0]
A P
Write Operation - Burst (Auto Address Increment)
S Slv Addr [6:0] 0 A Reg Addr [7:0] A Data [7:0] A Data [7:0] A P
Reg Addr +1
From slave to master
From master to slave
1 – Read
0 – Write
A – Acknowledge (SDA LOW)
N – Not Acknowledge (SDA HIGH)
S – START condition
P – STOP condition
Figure 9. I2C Write Operation
A read operation is performed in two stages. A data write is used to set the register address, then a data read is
performed to retrieve the data from the set address. A read burst operation is also supported. This is shown in
Figure 10.
Read Operation – Single Byte
S Slv Addr [6:0] 0 A Reg Addr [7:0] A P
S Slv Addr [6:0] 1 A Data [7:0] N P
Read Operation - Burst (Auto Address Increment)
S Slv Addr [6:0] 0 A Reg Addr [7:0] A P
S Slv Addr [6:0] 1 A Data [7:0] A Data [7:0] N P
Reg Addr +1
From slave to master
From master to slave
1 – Read
0 – Write
A – Acknowledge (SDA LOW)
N – Not Acknowledge (SDA HIGH)
S – START condition
P – STOP condition
Figure 10. I2C Read Operation
AC and DC electrical specifications for the SCL and SDA pins are shown in Table 8. The timing specifications and
timing diagram for the I2C bus is compatible with the I2C-Bus Standard. SDA timeout is supported for compatibility
with SMBus interfaces.
Rev. 1.0
17
Si5351A/B/C-B
5. Configuring the Si5351
The Si5351 is a highly flexible clock generator which is entirely configurable through its I2C interface. The device’s
default configuration is stored in non-volatile memory (NVM) as shown in Figure 11. The NVM is a one time
programmable memory (OTP) which can store a custom user configuration at power-up. This is a useful feature for
applications that need a clock present at power-up (e.g., for providing a clock to a processor).
Power-Up
NVM
(OTP)
RAM
Default
Config
I2C
Figure 11. Si5351 Memory Configuration
During a power cycle the contents of the NVM are copied into random access memory (RAM), which sets the
device configuration that will be used during normal operation. Any changes to the device configuration after
power-up are made by reading and writing to registers in the RAM space through the I2C interface.
5.1. Writing a Custom Configuration to RAM
To simplify device configuration, Silicon Labs has released the ClockBuilder Desktop. The software serves two
purposes: to configure the Si5351 with optimal configuration based on the desired frequencies and to control the
EVB when connected to a host PC.
The optimal configuration can be saved from the software in text files that can be used in any system, which
configures the device over I2C. ClockBuilder Desktop can be downloaded from www.silabs.com/ClockBuilder and
runs on Windows XP, Windows Vista, and Windows 7.
Once the configuration file has been saved, the device can be programmed via I2C by following the steps shown in
Figure 12.
18
Rev. 1.0
Si5351A/B/C-B
Disable Outputs
Set CLKx_DIS high; Reg. 3 = 0xFF
Powerdown all output drivers
Reg. 16, 17, 18, 19, 20, 21, 22, 23 =
0x80
Set interrupt masks
(see register 2 description)
Register
Map
Use ClockBuilder
Desktop v3.1 or later
Write new configuration to device using
the contents of the register map
generated by ClockBuilder Desktop. This
step also powers up the output drivers.
149-170
and 183)
(Registers 15-92 ,and
149-170)
Apply PLLA and PLLB soft reset
Reg. 177 = 0xAC
Enable desired outputs
(see Register 3)
Figure 12. I2C Programming Procedure
Rev. 1.0
19
Si5351A/B/C-B
5.2. Si5351 Application Examples
The Si5351 is a versatile clock generator which serves a wide variety of applications. The following examples show
how it can be used to replace crystals, crystal oscillators, VCXOs, and PLLs.
5.3. Replacing Crystals and Crystal Oscillators
Using an inexpensive external crystal, the Si5351A can generate up to 8 different free-running clock frequencies
for replacing crystals and crystal oscillators. A 3-output version packaged in a small 10-MSOP is also available for
applications that require fewer clocks. An example is shown in Figure 13.
XA
OSC
27 MHz
Multi
Synth
0
PLL
Multi
Synth
1
XB
Multi
Synth
2
Multi
Synth
3
125 MHz
Ethernet
PHY
CLK1
48 MHz
USB
Controller
CLK2
28.322 MHz
CLK3
74.25 MHz
HDMI
Port
CLK4
74.25/1.001 MHz
CLK5
24.576 MHz
Multi
Synth
6
CLK6
22.5792 MHz
Multi
Synth
7
CLK7
33.3333 MHz
Multi
Synth
4
Multi
Synth
5
Si5351A
CLK0
Video/Audio
Processor
CPU
Note: Si5351A replaces crystals, XOs, and PLLs.
Figure 13. Using the Si5351A to Replace Multiple Crystals, Crystal Oscillators, and PLLs
5.4. Replacing Crystals, Crystal Oscillators, and VCXOs
The Si5351B combines free-running clock generation and a VCXO in a single package for cost sensitive video
applications. An example is shown in Figure 14.
Free-running
Clocks
XA
OSC
27 MHz
PLL
Multi
Synth
0
Multi
Synth
1
XB
Multi
Synth
2
VC
VCXO
Multi
Synth
3
Multi
Synth
4
Si5351B
Multi
Synth
5
CLK0
125 MHz
CLK1
48 MHz
CLK2
28.322 MHz
Ethernet
PHY
USB
Controller
HDMI
Port
CLK3
74.25 MHz
CLK4
74.25/1.001 MHz
CLK5
24.576 MHz
Video/Audio
Processor
VCXO Clock
Outputs
Note: FBW = 10 kHz
Figure 14. Using the Si5351B to Replace Crystals, Crystal Oscillators, VCXOs, and PLLs
20
Rev. 1.0
Si5351A/B/C-B
5.5. Replacing Crystals, Crystal Oscillators, and PLLs
The Si5351C generates synchronous clocks for applications that require a fully integrated PLL instead of a VCXO.
Because of its dual PLL architecture, the Si5351C is capable of generating both synchronous and free-running
clocks. An example is shown in Figure 15.
Free-running
Clocks
XA
OSC
25 MHz
PLL
Multi
Synth
0
Multi
Synth
1
XB
Multi
Synth
2
CLKIN
PLL
54 MHz
Multi
Synth
3
Multi
Synth
4
Si5351C
Multi
Synth
5
CLK0
125 MHz
CLK1
48 MHz
CLK2
28.322 MHz
Ethernet
PHY
USB
Controller
HDMI
Port
CLK3
74.25 MHz
CLK4
74.25/1.001 MHz
CLK5
24.576 MHz
Video/Audio
Processor
Synchronous
Clocks
Figure 15. Using the Si5351C to Replace Crystals, Crystal Oscillators, and PLLs
5.6. Applying a Reference Clock at XTAL Input
The Si5351 can be driven with a clock signal through the XA input pin. This is especially useful when in need of
generating clock outputs in two synchronization domains. With the Si5351C, one reference clock can be provided
at the CLKIN pin and at XA.
VIN = 1 VPP
25/27 MHz
XA
0.1 µF
XB
PLLA
Multi
Synth
0
Multi
Synth
1
OSC
PLLB
Note: Float the XB input while driving
the XA input with a clock
Multi
Synth
N
Figure 16. Si5351 Driven by a Clock Signal
Rev. 1.0
21
Si5351A/B/C-B
5.7. HCSL Compatible Outputs
The Si5351 can be configured to support HCSL compatible swing when the VDDO of the output pair of interest is
set to 2.5 V (i.e., VDDOA must be 2.5 V when using CLK0/1; VDDOB must be 2.5 V for CLK2/3 and so on).
The circuit in the figure below must be applied to each of the two clocks used, and one of the clocks in the pair
must also be inverted to generate a differential pair. See register setting CLKx_INV.
ZO = 50 
PLLA
Multi
Synth
0
0
R1
511 
240 
OSC
PLLB
Multi
Synth
1
ZO = 50 
0
R1
511 
240 
Multi
Synth
N
R2
Note: The complementary -180 degree
out of phase output clock is generated
using the INV function
Figure 17. Si5351 Output is HCSL Compatible
22
R2
Rev. 1.0
HCSL
CLKIN
Si5351A/B/C-B
6. Design Considerations
The Si5351 is a self-contained clock generator that requires very few external components. The following general
guidelines are recommended to ensure optimum performance. Refer to “AN554: Si5350/51 PCB Layout Guide” for
additional layout recommendations.
6.1. Power Supply Decoupling/Filtering
The Si5351 has built-in power supply filtering circuitry and extensive internal Low Drop Out (LDO) voltage
regulators to help minimize the number of external bypass components. All that is recommended is one 0.1 to
1.0 µF decoupling capacitor per power supply pin. This capacitor should be mounted as close to the VDD and
VDDOx pins as possible without using vias.
6.2. Power Supply Sequencing
The VDD and VDDOx (i.e., VDDO0, VDDO1, VDDO2, VDDO3) power supply pins have been separated to allow
flexibility in output signal levels. Power supply sequencing for VDD and VDDOx requires that all VDDOx be
powered up either before or at the same time as VDD. Unused VDDOx pins should be tied to VDD.
6.3. External Crystal
The external crystal should be mounted as close to the pins as possible using short PCB traces. The XA and XB
traces should be kept away from other high-speed signal traces. See “AN551: Crystal Selection Guide” for more
details.
6.4. External Crystal Load Capacitors
The Si5351 provides the option of using internal and external crystal load capacitors. If internal load capacitance is
insufficient, capacitors of value < 2 pF may be used to increased equivalent load capacitance. If external load
capacitors are used, they should be placed as close to the XA/XB pads as possible. See “AN551: Crystal Selection
Guide” for more details.
6.5. Unused Pins
Unused voltage control pin should be tied to GND.
Unused CLKIN pin should be tied to GND.
Unused XA/XB pins should be left floating. Refer to "5.6. Applying a Reference Clock at XTAL Input" on page 21
when using XA as a clock input pin.
Unused output pins (CLK0–CLK7) should be left floating.
Unused VDDOx pins should be tied to VDD.
6.6. Trace Characteristics
The Si5351A/B/C features various output current drive strengths. It is recommended to configure the trace
characteristics as shown in Figure 18 when the default high drive strength is used.
ZO = 50 ohms
R = 0 ohms
CLK
(Optional resistor for
EMI management)
Figure 18. Recommended Trace Characteristics with Default Drive Strength Setting
Rev. 1.0
23
Si5351A/B/C-B
7. Register Map Summary
For many applications, the Si5351's register values are easily configured using ClockBuilder Desktop software.
However, for customers interested in using the Si5351 in operating modes beyond the capabilities available with
ClockBuilder™, refer to “AN619: Manually Generating an Si5351 Register Map” for a detailed description of the
Si5351 registers and their usage.
8. Register Descriptions
Refer to “AN619: Manually Generating an Si5351 Register Map” for a detailed description of Si5351 registers.
24
Rev. 1.0
Si5351A/B/C-B
9. Si5351 Pin Descriptions
XA
1
XB
2
A0
3
SCL
4
16 CLK6
17 CLK5
18 VDDOC
19 CLK4
20 VDD
9.1. Si5351A 20-pin QFN
15 CLK7
14 VDDOD
GND
PAD
13 CLK0
12 CLK1
9
CLK2
VDDOB 10
7
8
OEB
SSEN
CLK3
11 VDDOA
6
SDA 5
Figure 19. Si5351A 20-QFN Top View
Table 11. Si5351A Pin Descriptions
Pin Name
Pin
Number
Pin Type1
XA
1
I
Input pin for external crystal.
XB
2
I
Input pin for external crystal.
CLK0
13
O
Output clock 0.
CLK1
12
O
Output clock 1.
CLK2
9
O
Output clock 2.
CLK3
8
O
Output clock 3.
CLK4
19
O
Output clock 4.
CLK5
17
O
Output clock 5.
CLK6
16
O
Output clock 6.
CLK7
15
O
Output clock 7.
A0
3
I
I2C address bit.
SCL
4
I
I2C bus serial clock input. Pull-up to VDD core with 1 k
SDA
5
I/O
I2C bus serial data input. Pull-up to VDD core with 1 k
SSEN
6
I
Spread spectrum enable. High = enabled, Low = disabled.
OEB
7
I
Output driver enable. Low = enabled, High = disabled.
Function
VDD
20
P
Core voltage supply pin. See 6.2.
VDDOA
11
P
Output voltage supply pin for CLK0 and CLK1. See 6.2.
VDDOB
10
P
Output voltage supply pin for CLK2 and CLK3. See 6.2.
VDDOC
18
P
Output voltage supply pin for CLK4 and CLK5. See 6.2.
VDDOD
14
P
Output voltage supply pin for CLK6 and CLK7. See 6.2.
GND
Center Pad
P
Ground. Use multiple vias to ensure a solid path to GND.
1. I = Input, O = Output, P = Power.
2. Input pins are not internally pulled up.
Rev. 1.0
25
Si5351A/B/C-B
16 CLK6
17 CLK5
18 VDDOC
19 CLK4
20 VDD
9.2. Si5351B 20-Pin QFN
XA
1
15
XB
2
14
VC
3
SCL
4
12
SDA
5
11
GND
PAD
7
8
9
OEB
CLK3
CLK2
VDDOD
CLK0
CLK1
VDDOA
VDDOB 10
6
SSEN
13
CLK7
Figure 20. Si5351B 20-QFN Top View*
Table 12. Si5351B Pin Descriptions
Pin Name
Pin
Number
Pin Type1
XA
1
I
Input pin for external crystal
XB
2
I
Input pin for external crystal
CLK0
13
O
Output clock 0
CLK1
12
O
Output clock 1
CLK2
9
O
Output clock 2
CLK3
8
O
Output clock 3
CLK4
19
O
Output clock 4
CLK5
17
O
Output clock 5
CLK6
16
O
Output clock 6
CLK7
15
O
Output clock 7
VC
3
I
VCXO control voltage input
SCL
4
I
I2C bus serial clock input. Pull-up to VDD core with 1 k
SDA
5
I/O
I2C bus serial data input. Pull-up to VDD core with 1 k
SSEN
6
I
Spread spectrum enable. High = enabled, Low = disabled.
OEB
7
I
Output driver enable. Low = enabled, High = disabled.
Function
VDD
20
P
Core voltage supply pin
VDDOA
11
P
Output voltage supply pin for CLK0 and CLK1. See 6.2
VDDOB
10
P
Output voltage supply pin for CLK2 and CLK3. See 6.2
VDDOC
18
P
Output voltage supply pin for CLK4 and CLK5. See 6.2
VDDOD
14
P
Output voltage supply pin for CLK6 and CLK7. See 6.2
GND
Center Pad
P
Ground
1. I = Input, O = Output, P = Power
2. Input pins are not internally pulled up.
26
Rev. 1.0
Si5351A/B/C-B
XA
1
XB
2
16 CLK6
17 CLK5
18 VDDOC
19 CLK4
20 VDD
9.3. Si5351C 20-Pin QFN
GND
PAD
15
CLK7
14
VDDOD
13
CLK0
VDDOA
VDDOB 10
11
9
5
CLK2
SDA
8
CLK1
CLK3
12
7
4
OEB
SCL
6
3
CLKIN
INTR
Table 13. Si5351C Pin Descriptions
Pin Name
Pin
Number
Pin Type1
Function
20-QFN
XA
1
I
Input pin for external crystal.
XB
2
I
Input pin for external crystal.
CLK0
13
O
Output clock 0.
CLK1
12
O
Output clock 1.
CLK2
9
O
Output clock 2.
CLK3
8
O
Output clock 3.
CLK4
19
O
Output clock 4.
CLK5
17
O
Output clock 5.
CLK6
16
O
Output clock 6.
CLK7
15
O
Output clock 7.
INTR
3
O
Interrupt pin. Open drain active low output, requires a pull-up
resistor greater than 1 k
SCL
4
I
I2C bus serial clock input. Pull-up to VDD core with 1 k
SDA
5
I/O
I2C bus serial data input. Pull-up to VDD core with 1 k
CLKIN
6
I
PLL clock input.
OEB
7
I
Output driver enable. Low = enabled, High = disabled.
VDD
20
P
Core voltage supply pin
VDDOA
11
P
Output voltage supply pin for CLK0 and CLK1. See 6.2
VDDOB
10
P
Output voltage supply pin for CLK2 and CLK3. See 6.2
VDDOC
18
P
Output voltage supply pin for CLK4 and CLK5. See 6.2
VDDOD
14
P
Output voltage supply pin for CLK6 and CLK7. See 6.2
GND
Center Pad
P
Ground.
Notes:
1. I = Input, O = Output, P = Power.
2. Input pins are not internally pulled up.
Rev. 1.0
27
Si5351A/B/C-B
9.4. Si5351A 10-Pin MSOP
VDD
1
10
CLK0
XA
2
9
CLK1
XB
3
8
GND
SCL
4
7
VDDO
SDA
5
6
CLK2
Figure 21. Si5351A 10-MSOP Top View
Table 14. Si5351A 10-MSOP Pin Descriptions
Pin Name
Pin
Number
Pin Type*
Function
10-MSOP
XA
2
I
Input pin for external crystal.
XB
3
I
Input pin for external crystal.
CLK0
10
O
Output clock 0.
CLK1
9
O
Output clock 1.
CLK2
6
O
Output clock 2.
SCL
4
I
Serial clock input for the I2C bus. This pin must be pulled-up using a pullup resistor of at least 1 k.
SDA
5
I/O
Serial data input for the I2C bus. This pin must be pulled-up using a pull-up
resistor of at least 1 k.
VDD
1
P
Core voltage supply pin.
VDDO
7
P
Output voltage supply pin for CLK0, CLK1, and CLK2. See "6.2. Power
Supply Sequencing" on page 23.
GND
8
P
Ground.
*Note: I = Input, O = Output, P = Power
28
Rev. 1.0
Si5351A/B/C-B
10. Ordering Information
Factory pre-programmed Si5351 devices (e.g., with bootup frequencies) can be requested using the ClockBuilder
web-based utility available at: www.silabs.com/ClockBuilder. A unique part number is assigned to each custom
configuration as indicated in Figure 22. Blank, un-programmed Si5351 devices (with no boot-up frequency) do not
contain a custom code.
Figure 22. Device Part Numbers
An evaluation kit containing ClockBuilder Desktop software and hardware enable easy evaluation of the Si5351A/B/
C. The orderable part numbers for the evaluation kits are provided in Figure 23.
Figure 23. Si5351A/B/C Evaluation Kit
Rev. 1.0
29
Si5351A/B/C-B
11. Package Outlines
Figure 24 shows the package details for the Si5351 in a 20-QFN package. Table 15 lists the values for the
dimensions shown in the illustration.
Seating Plane
11.1. 20-pin QFN
C
D2
B
D
A
D2/2
A1
L
E
E2
E2/2
b
A
e
Figure 24. 20-pin QFN Package Drawing
30
Rev. 1.0
Si5351A/B/C-B
Table 15. Package Dimensions
Dimension
A
Min
0.80
Nom
0.85
Max
0.90
A1
0.00
—
0.05
b
D
D2
e
E
E2
L
0.20
0.30
2.65
0.35
0.25
4.00 BSC
2.70
0.50 BSC
4.00 BSC
2.70
0.40
2.75
0.45
aaa
—
—
0.10
bbb
—
—
0.10
ccc
—
—
0.08
ddd
—
—
0.10
2.65
2.75
Notes:
1. All dimensions shown are in millimeters (mm) unless otherwise noted.
2. Dimensioning and Tolerancing per ANSI Y14.5M-1994.
3. This drawing conforms to JEDEC Outline MO-220, variation VGGD-5.
4. Recommended card reflow profile is per the JEDEC/IPC J-STD-020 specification for
Small Body Components.
Rev. 1.0
31
Si5351A/B/C-B
12. Land Pattern: 20-Pin QFN
Figure 25 shows the recommended land pattern details for the Si5351 in a 20-Pin QFN package. Table 16 lists the
values for the dimensions shown in the illustration.
Figure 25. 20-Pin QFN Land Pattern
32
Rev. 1.0
Si5351A/B/C-B
Table 16. PCB Land Pattern Dimensions
Symbol
Millimeters
C1
4.0
C2
4.0
E
0.50 BSC
X1
0.30
X2
2.70
Y1
0.80
Y2
2.70
Notes:
General
1. All dimensions shown are in millimeters
(mm) unless otherwise noted.
2. This land pattern design is based on IPC7351 guidelines.
Solder Mask Design
3. All metal pads are to be non-solder mask
defined (NSMD). Clearance between the
solder mask and the metal pad is to be
60 µm minimum, all the way around the pad.
Stencil Design
4. A stainless steel, laser-cut and electropolished stencil with trapezoidal walls should
be used to assure good solder paste release.
5. The stencil thickness should be 0.125 mm
(5 mils).
6. The ratio of stencil aperture to land pad size
should be 1:1 for all perimeter pads.
7. A 2x2 array of 1.10 x 1.10 mm openings on
1.30 mm pitch should be used for the center
ground pad.
Card Assembly
8. A No-Clean, Type-3 solder paste is
recommended.
9. The recommended card reflow profile is per
the JEDEC/IPC J-STD-020 specification for
Small Body components.
Rev. 1.0
33
Si5351A/B/C-B
12.1. 10-Pin MSOP Package Outline
Figure 26 illustrates the package details for the Si5351 in a 10-pin MSOP package. Table 17 lists the values for the
dimensions shown in the illustration.
Figure 26. 10-pin MSOP Package Drawing
34
Rev. 1.0
Si5351A/B/C-B
Table 17. 10-MSOP Package Dimensions
Dimension
A
A1
A2
b
c
D
E
E1
e
L
L2
q
aaa
bbb
ccc
ddd
Min
—
0.00
0.75
0.17
0.08
Nom
—
—
0.85
—
—
3.00 BSC
4.90 BSC
3.00 BSC
0.50 BSC
0.60
0.25 BSC
—
—
—
—
—
0.40
0
—
—
—
—
Max
1.10
0.15
0.95
0.33
0.23
0.80
8
0.20
0.25
0.10
0.08
Notes:
1. All dimensions shown are in millimeters (mm) unless otherwise noted.
2. Dimensioning and Tolerancing per ANSI Y14.5M-1994.
3. This drawing conforms to the JEDEC Solid State Outline MO-137, Variation C
4. Recommended card reflow profile is per the JEDEC/IPC J-STD-020 specification for Small Body
Components.
Rev. 1.0
35
Si5351A/B/C-B
13. Land Pattern: 10-Pin MSOP
Figure 27 shows the recommended land pattern details for the Si5351 in a 10-Pin MSOP package. Table 18 lists
the values for the dimensions shown in the illustration.
Figure 27. 10-Pin MSOP Land Pattern
36
Rev. 1.0
Si5351A/B/C-B
Table 18. PCB Land Pattern Dimensions
Symbol
Millimeters
Min
Max
C1
4.40 REF
E
0.50 BSC
G1
3.00
—
X1
—
0.30
Y1
Z1
1.40 REF
—
5.80
Notes:
General
1. All dimensions shown are in millimeters (mm) unless otherwise noted.
2. Dimensioning and Tolerancing per ASME Y14.5M-1994.
3. This Land Pattern Design is based on the IPC-7351 guidelines.
4. All dimensions shown are at Maximum Material Condition (MMC). Least
Material Condition (LMC) is calculated based on a Fabrication
Allowance of 0.05mm.
Solder Mask Design
5. All metal pads are to be non-solder mask defined (NSMD). Clearance
between the solder mask and the metal pad is to be 60 µm minimum, all
the way around the pad.
Stencil Design
6. A stainless steel, laser-cut and electro-polished stencil with trapezoidal
walls should be used to assure good solder paste release.
7. The stencil thickness should be 0.125 mm (5 mils).
8. The ratio of stencil aperture to land pad size should be 1:1.
Card Assembly
9. A No-Clean, Type-3 solder paste is recommended.
10. The recommended card reflow profile is per the JEDEC/IPC J-STD020C specification for Small Body components.
Rev. 1.0
37
Si5351A/B/C-B
14. Top Marking
14.1. 20-Pin QFN Top Marking
Figure 28. 20-Pin QFN Top Marking
14.2. Top Marking Explanation
Mark Method:
Laser
Pin 1 Mark:
Filled Circle = 0.50 mm Diameter
(Bottom-Left Corner)
Font Size:
0.60 mm (24 mils)
Line 1 Mark Format
Device Part Number
Si5351
Line 2 Mark Format:
TTTTTT = Mfg Code*
Manufacturing Code from the Assembly Purchase
Order Form.
Line 3 Mark Format:
YY = Year
WW = Work Week
Assigned by the Assembly House. Corresponds to
the year and work week of the assembly date.
*Note: The code shown in the “TTTTTT” line does not correspond to the orderable part number or frequency plan. It is used
for package assembly quality tracking purposes only.
38
Rev. 1.0
Si5351A/B/C-B
14.3. 10-Pin MSOP Top Marking
Figure 29. 10-Pin MSOP Top Marking
14.4. Top Marking Explanation
Mark Method:
Laser
Pin 1 Mark:
Mold Dimple (Bottom-Left Corner)
Font Size:
0.60 mm (24 mils)
Line 1 Mark Format
Device Part Number
Si5351
Line 2 Mark Format:
TTTT = Mfg Code*
Line 2 from the “Markings” section of the Assembly
Purchase Order form.
Line 3 Mark Format:
YWW = Date Code
Assigned by the Assembly House.
Y = Last Digit of Current Year (Ex: 2013 = 3)
WW = Work Week of Assembly Date.
*Note: The code shown in the “TTTT” line does not correspond to the orderable part number or frequency plan. It is used for
package assembly quality tracking purposes only.
Rev. 1.0
39
Si5351A/B/C-B
DOCUMENT CHANGE LIST
Revision 0.75 to Revision 1.0









40
Extended frequency range from 8 MHz-160 MHz to
2.5 kHz-200 MHz.
Updated block diagrams for clarity.
Added complete Si5350/1 family table, Table 1.
Added top mark information.
Added land pattern drawings.
Added PowerUp Time, PLL Bypass mode, Table 4.
Clarified Down Spread step sizes in Table 4.
Updated max jitter specs (typ unchanged) in Table 6.
Clarified power supply sequencing requirement,
Section 6.2.
Rev. 1.0
Si5351A/B/C-B
CONTACT INFORMATION
Silicon Laboratories Inc.
400 West Cesar Chavez
Austin, TX 78701
Tel: 1+(512) 416-8500
Fax: 1+(512) 416-9669
Toll Free: 1+(877) 444-3032
Please visit the Silicon Labs Technical Support web page:
https://www.silabs.com/support/pages/contacttechnicalsupport.aspx
and register to submit a technical support request.
Patent Notice
Silicon Labs invests in research and development to help our customers differentiate in the market with innovative low-power, small size, analogintensive mixed-signal solutions. Silicon Labs' extensive patent portfolio is a testament to our unique approach and world-class engineering team.
The information in this document is believed to be accurate in all respects at the time of publication but is subject to change without notice.
Silicon Laboratories assumes no responsibility for errors and omissions, and disclaims responsibility for any consequences resulting from
the use of information included herein. Additionally, Silicon Laboratories assumes no responsibility for the functioning of undescribed features or parameters. Silicon Laboratories reserves the right to make changes without further notice. Silicon Laboratories makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does Silicon Laboratories assume any
liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation
consequential or incidental damages. Silicon Laboratories products are not designed, intended, or authorized for use in applications intended to support or sustain life, or for any other application in which the failure of the Silicon Laboratories product could create a situation where
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Rev. 1.0
41