Cypress Semiconductor | CY7C1380C | User manual | 512K x 36/1M x 18 Pipelined SRAM
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PRELIMINARY
CY7C1380C
CY7C1382C
512K x 36/1M x 18 Pipelined SRAM
Features
• Fast clock speed: 250, 225, 200, 167, 133 MHz
• Provide high-performance 3-1-1-1 access rate
• Fast OE access times: 2.6, 2.8, 3.0, 3.4, 4.2 ns
• Optimal for depth expansion
• 3.3V (–5% / +10%) power supply
• Separate V
DDQ
for 3.3V or 2.5V I/O
• Common data inputs and data outputs
• Byte Write Enable and Global Write control
• Chip enable for address pipeline
• Address, data, and control registers
• Internally self-timed Write Cycle
• Burst control pins (interleaved or linear burst sequence)
• Automatic power-down available using ZZ mode or CE deselect
• High-density, high-speed packages
• Available in 119-ball bump BGA, 165-ball FBGA and
100-pin TQFP packages
• JTAG boundary scan for BGA packaging version
Functional Description
The Cypress Synchronous Burst SRAM family employs high-speed, low-power CMOS designs using advanced single-layer polysilicon, triple-layer metal technology. Each memory cell consists of six transistors.
The CY7C1380C and CY7C1382C SRAMs integrate 524,288
× 36 and 1,048,576 × 18 SRAM cells with advanced
Selection Guide
Maximum Access Time
Maximum Operating Current
Maximum CMOS Standby Current
Shaded areas contain advance information.
250 MHz
2.6
350
70
225 MHz
2.8
325
70 synchronous peripheral circuitry and a two-bit counter for internal burst operation. All synchronous inputs are gated by registers controlled by a positive-edge-triggered Clock Input
(CLK). The synchronous inputs include all addresses, all data inputs, address-pipelining Chip Enable (CE), burst control inputs (ADSC, ADSP, and ADV), write enables (BWa, BWb,
BWc, BWd and BWE), and Global Write (GW).
Asynchronous inputs include the Output Enable (OE) and burst mode control (MODE). DQ
CY7C1380C and DQ a,b a,b,c,d and DP a,b and DP a,b,c,d apply to apply to CY7C1382C a, b, c, d each are eight bits wide in the case of DQ and one bit wide in the case of DP.
Addresses and chip enables are registered with either
Address Status Processor (ADSP) or Address Status
Controller (ADSC) input pins. Subsequent burst addresses can be internally generated as controlled by the Burst Advance
Pin (ADV).
Address, data inputs, and write controls are registered on-chip to initiate a self-timed Write cycle. Write cycles can be one to four bytes wide, as controlled by the write control inputs.
Individual byte writes allow individual bytes to be written. BWa controls DQa and DPa. BWb controls DQb and DPb. BWc controls DQc and DPd. BWd controls DQd-DQd and DPd.
BWa, BWb, BWc, and BWd can be active only with BWE being
LOW. GW being LOW causes all bytes to be written. Write pass-through capability allows written data available at the output for the next Read cycle. This device also incorporates pipelined enable circuit for easy depth expansion without penalizing system performance.
All inputs and outputs of the CY7C1380C and the CY7C1382C are JEDEC standard JESD8-5-compatible.
200 MHz
3.0
300
70
167 MHz
3.4
275
70
133 MHz
4.2
245
70
Unit ns mA mA
Cypress Semiconductor Corporation
Document #: 38-05237 Rev. *B
• 3901 North First Street • San Jose
,
CA 95134 • 408-943-2600
Revised December 18, 2002
PRELIMINARY
Logic Block Diagram CY7C1380C – 512K × 36
CLK
ADV
ADSC
ADSP
A
[18:0]
GW
BWE
BW d
BW c
BW b
BW a
CE
1
CE
2
CE
3
19
MODE
(A
[1;0]
) 2
CE
CLR
BURST
COUNTER
Q
0
Q
1
17
CE
D
ADDRESS
REGISTER
Q
D
D
D
D
D
DQ d
, DP d
BYTEWRITE
REGISTERS
DQ c
, DP c
BYTEWRITE
REGISTERS
DQ b
, DP b
BYTEWRITE
REGISTERS
DQ a
, DP a
BYTEWRITE
REGISTERS
Q
Q
Q
Q
ENABLE CE
REGISTER
Q
17
D
ENABLE DELAY
REGISTER
Q
OE
ZZ SLEEP
CONTROL
Logic Block Diagram CY7C1382C – 1M × 18
CLK
ADV
ADSC
ADSP
MODE
(A
[1;0]
) 2
CE
CLR
BURST
COUNTER
Q
0
Q
1
A
[19:0]
GW
20 18
CE
D
ADDRESS
REGISTER
Q
BWE
BW b
BW a
D
D
DQ b
, DP b
BYTEWRITE
REGISTERS
DQ a
, DP a
BYTEWRITE
REGISTERS
Q
Q
18
CE
1
CE
2
CE
3
OE
ZZ
D
CE
ENABLE CE
REGISTER
Q
D
ENABLE DELAY
REGISTER
Q
SLEEP
CONTROL
CY7C1380C
CY7C1382C
19
512K × 36
MEMORY
ARRAY
36
OUTPUT
REGISTERS
CLK
36
INPUT
REGISTERS
CLK
DQ a,b,c,d
DP a,b
18
1M × 18
MEMORY
ARRAY
18
OUTPUT
REGISTERS
CLK
18
INPUT
REGISTERS
CLK
DQ a,b
DP a,b
Document #: 38-05237 Rev. *B Page 2 of 28
PRELIMINARY
DQPc
DQc
DQc
V
DDQ
V
SSQ
DQc
DQc
DQc
DQc
V
SSQ
V
DDQ
DQc
DQc
NC
V
DD
NC
V
SS
DQd
DQd
V
DDQ
V
SSQ
DQd
DQd
DQd
DQd
V
SSQ
V
DDQ
DQd
DQd
DQPd
25
26
27
28
29
30
21
22
23
24
17
18
19
20
12
13
14
15
16
8
9
10
11
6
7
4
5
1
2
3
Pin Configurations
CY7C1380C
(512K × 36)
100-pin TQFP (Top View)
56
55
54
53
52
51
60
59
58
57
64
63
62
61
69
68
67
66
65
73
72
71
70
80
79
78
77
76
75
74
24
25
26
27
28
29
30
17
18
19
20
21
22
23
13
14
15
16
8
9
10
11
12
5
6
3
4
7
1
2
DQPb
DQb
DQb
V
DDQ
V
SSQ
DQb
NC
NC
NC
V
DDQ
V
SSQ
NC
DQb
DQb
NC
DQb
DQb
DQb
V
SSQ
V
DDQ
DQb
V
V
SSQ
DDQ
DQb
DQb
DQb
V
SS
NC
V
DD
ZZ
DQa
NC
V
NC
V
DD
SS
DQb
DQb DQa
V
DDQ
V
SSQ
DQa
V
DDQ
V
SSQ
DQb
DQa
DQa
DQb
DPb
NC DQa
V
SSQ
V
DDQ
DQa
V
V
SSQ
DDQ
NC
DQa
DQPa
NC
NC
CY7C1380C
CY7C1382C
CY7C1382C
(1M × 18)
DQa
DQa
V
SSQ
V
DDQ
DQa
DQa
V
SS
NC
V
DD
ZZ
DQa
DQa
V
DDQ
V
SSQ
DQa
DQa
A
NC
NC
V
DDQ
V
SSQ
NC
DPa
NC
NC
V
SSQ
V
DDQ
NC
NC
NC
57
56
55
54
53
52
51
64
63
62
61
60
59
58
68
67
66
65
73
72
71
70
69
80
79
78
77
76
75
74
Document #: 38-05237 Rev. *B Page 3 of 28
Pin Configurations (continued)
1
V
DDQ
NC
NC
DQc
DQc
V
DDQ
DQc
DQc
V
DDQ
DQd
DQd
V
DDQ
DQd
DQd
NC
NC
V
DDQ
N
P
R
T
U
G
H
J
K
L
M
D
E
F
A
B
C
2
A
A
A
DPc
DQc
DQc
DQc
DQc
V
DD
DQd
DQd
DQd
DQd
DPd
A
72M
TMS
PRELIMINARY
CY7C1380C (512K × 36)
3 4
A
A
A
V
SS
V
SS
V
SS
BWc
V
SS
NC
V
SS
BWd
V
SS
V
SS
V
SS
MODE
A
TDI
ADSP
ADSC
V
DD
NC
CE
1
OE
ADV
GW
V
DD
CLK
NC
BWE
A1
A0
V
DD
A
TCK
5
A
A
V
SS
V
SS
V
SS
NC
A
TDO
A
V
SS
V
SS
V
SS
BWb
V
SS
NC
V
SS
BWa
1
V
DDQ
NC
NC
DQb
NC
V
DDQ
NC
DQb
V
DDQ
NC
DQb
V
DDQ
DQb
NC
NC
72M
V
DDQ
N
P
R
T
U
A
E
F
B
C
D
G
H
J
K
L
M
2
A
A
A
NC
DQb
NC
DQb
NC
V
DD
DQb
NC
DQb
NC
DPb
A
A
TMS
CY7C1382C (1M x 18)
3 4
A
A
A
V
SS
V
SS
V
SS
BWb
V
SS
NC
V
SS
V
SS
V
SS
V
SS
V
SS
MODE
A
TDI
ADSP
ADSC
V
DD
NC
CE
1
OE
ADV
GW
V
DD
CLK
NC
BWE
A1
A0
Vdd
36M
TCK
5
A
A
A
V
SS
V
SS
V
SS
V
SS
V
SS
NC
V
SS
BWa
V
SS
V
SS
V
SS
NC
A
TDO
7
V
DDQ
NC
NC
NC
DQa
V
DDQ
DQa
NC
V
DDQ
DQa
NC
V
DDQ
NC
DQa
NC
ZZ
V
DDQ
6
A
A
A
DPa
NC
DQa
NC
DQa
V
DD
NC
DQa
NC
DQa
NC
A
A
NC
7
V
DDQ
NC
NC
DQb
DQb
V
DDQ
DQb
DQb
V
DDQ
DQa
DQa
V
DDQ
DQa
DQa
NC
ZZ
V
DDQ
6
A
A
A
DPb
DQb
DQb
DQb
DQb
V
DD
DQa
DQa
DQa
DQa
DPa
A
36M
NC
CY7C1380C
CY7C1382C
Document #: 38-05237 Rev. *B Page 4 of 28
PRELIMINARY
Pin Configurations (continued)
A
E
F
G
H
J
K
L
M
B
C
D
N
P
R
1
NC
NC
DPc
DQc
DQc
DQc
DQc
NC
DQd
DQd
DQd
DQd
DPd
NC
MODE
165-ball Bump FBGA
2
A
A
NC
DQc
DQc
DQc
DQc
V
SS
DQd
DQd
DQd
DQd
NC
72M
36M
CY7C1380C (512K × 36) – 11 × 15 FBGA
3
CE
1
CE
2
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
DDQ
NC
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
DDQ
A
A
5
BWb
BWa
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
NC
TDI
TMS
4
BWc
BWd
V
SS
V
DD
V
DD
V
DD
V
DD
V
DD
V
DD
V
DD
V
DD
V
DD
V
SS
A
A
7
BWE
GW
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
TDO
TCK
6
CE
3
CLK
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
A
A1
A0
8
ADSC
OE
V
SS
V
DD
V
DD
V
DD
V
DD
V
DD
V
DD
V
DD
V
DD
V
DD
V
SS
A
A
9
ADV
ADSP
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
DDQ
NC
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
DDQ
A
A
CY7C1380C
CY7C1382C
10
A
A
NC
DQb
DQb
DQb
DQb
NC
DQa
DQa
DQa
DQa
NC
A
A
11
NC
144M
DPb
DQb
DQb
DQb
DQb
ZZ
DQa
DQa
DQa
DQa
DPa
A
A
1
NC
NC
NC
DQb
DQb
DQb
DQb
NC
NC
NC
NC
NC
DPb
NC
MODE
A
E
F
G
H
J
K
L
M
B
C
D
N
P
R
2
A
A
NC
DQb
DQb
DQb
DQb
V
SS
NC
NC
NC
NC
NC
72M
36M
CY7C1382C (1M × 18) – 11 × 15 FBGA
5
NC
BWa
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
NC
TDI
TMS
4
BWb
NC
V
SS
V
DD
V
DD
V
DD
V
DD
V
DD
V
DD
V
DD
V
DD
V
DD
V
SS
A
A
3
CE
1
CE
2
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
DDQ
NC
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
DDQ
A
A
6
CE
3
CLK
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
A
A1
A0
7
BWE
GW
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
TDO
TCK
8
ADSC
OE
V
SS
V
DD
V
DD
V
DD
V
DD
V
DD
V
DD
V
DD
V
DD
V
DD
V
SS
A
A
9
ADV
ADSP
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
DDQ
NC
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
DDQ
A
A
10
A
A
NC
NC
NC
NC
NC
NC
DQa
DQa
DQa
DQa
NC
A
A
11
A
144M
DPa
DQa
DQa
DQa
DQa
ZZ
NC
NC
NC
NC
NC
A
A
Document #: 38-05237 Rev. *B Page 5 of 28
PRELIMINARY
CY7C1380C
CY7C1382C
Pin Definitions
A0
A1
A
Name
BWa
BWb
BWc
BWd
GW
I/O
Input-
Synchronous
Input-
Synchronous
BWE
CLK
CE
1
CE
2
CE
3
OE
ADV
ADSP
ADSC
MODE
ZZ
DQa, DPa
DQb, DPb
DQc, DPc
DQd, DPd
TDO
TDI
TMS
Description
Address Inputs used to select one of the address locations. Sampled at the rising edge of the CLK if ADSP or ADSC is active LOW, and CE
1,
CE
2
, and CE
3 are sampled active. A
[1:0] feed the two-bit counter.
Byte Write Select Inputs, active LOW. Qualified with BWE to conduct byte writes to the
SRAM. Sampled on the rising edge of CLK.
Input-
Synchronous
Input-
Synchronous
Input-
Clock
Input-
Synchronous
Input-
Synchronous
Input-
Synchronous
Input-
Asynchronous
Input-
Synchronous
Input-
Synchronous
Input-
Synchronous
Global Write Enable Input, active LOW. When asserted LOW on the rising edge of CLK, a global write is conducted (ALL bytes are written, regardless of the values on BW a,b,c,d
BWE).
and
Byte Write Enable Input, active LOW. Sampled on the rising edge of CLK. This signal must be asserted LOW to conduct a byte write.
Clock Input. Used to capture all synchronous inputs to the device. Also used to increment the burst counter when ADV is asserted LOW, during a burst operation.
Chip Enable 1 Input, active LOW. Sampled on the rising edge of CLK. Used in conjunction with CE
2
and CE
3
to select/deselect the device. ADSP is ignored if CE
1
is HIGH.
Chip Enable 2 Input, active HIGH. Sampled on the rising edge of CLK. Used in conjunction with CE
1
and CE
3
to select/deselect the device. (TQFP Only)
Chip Enable 3 Input, active LOW. Sampled on the rising edge of CLK. Used in conjunction with CE
1 and CE
2
to select/deselect the device. (TQFP Only)
Output Enable, asynchronous input, active LOW. Controls the direction of the I/O pins.
When LOW, the I/O pins behave as outputs. When deasserted HIGH, I/O pins are three-stated, and act as input data pins. OE is masked during the first clock of a read cycle when emerging from a deselected state.
Advance Input signal, sampled on the rising edge of CLK. When asserted, it automatically increments the address in a burst cycle.
Address Strobe from Processor, sampled on the rising edge of CLK. When asserted
LOW, A is captured in the address registers. A
[1:0]
are also loaded into the burst counter. When
ADSP and ADSC are both asserted, only ADSP is recognized. ASDP is ignored when CE
1 deasserted HIGH.
is
Address Strobe from Controller, sampled on the rising edge of CLK. When asserted
LOW, A
[x:0]
is captured in the address registers. A
[1:0]
are also loaded into the burst counter.
When ADSP and ADSC are both asserted, only ADSP is recognized.
Input Pin
Input-
Asynchronous
I/O-
Synchronous
Selects Burst Order. When tied to GND selects linear burst sequence. When tied to V
DDQ or left floating selects interleaved burst sequence. This is a strap pin and should remain static during device operation.
ZZ “sleep” Input. This active HIGH input places the device in a non-time critical “sleep” condition with data integrity preserved.
Bidirectional Data I/O lines. As inputs, they feed into an on-chip data register that is triggered by the rising edge of CLK. As outputs, they deliver the data contained in the memory location specified by A
X during the previous clock rise of the read cycle. The direction of the pins is controlled by OE. When OE is asserted LOW, the pins behave as outputs. When HIGH, DQx and DPx are placed in a three-state condition. DQ a,b,c and d are 8 bits wide. DP a,b,c and d are 1 bit wide.
JTAG serial output
Synchronous
JTAG serial input
Synchronous
Serial data-out to the JTAG circuit. Delivers data on the negative edge of TCK. (BGA and
FBGA Only)
Serial data-In to the JTAG circuit. Sampled on the rising edge of TCK.(BGA and FBGA Only)
Test Mode Select
Synchronous
This pin controls the Test Access Port state machine. Sampled on the rising edge of TCK.
(BGA and FBGA Only)
Document #: 38-05237 Rev. *B Page 6 of 28
PRELIMINARY
CY7C1380C
CY7C1382C
V
SS
V
DDQ
V
SSQ
36M
72M
144M
NC
Pin Definitions
Name
TCK
V
DD
I/O Description
JTAG serial clock Serial clock to the JTAG circuit. (BGA and FBGA Only)
Power Supply Power supply inputs to the core of the device. Should be connected to 3.3V –5% +10% power supply.
Ground Ground for the core of the device. Should be connected to ground of the system.
I/O Power Supply Power supply for the I/O circuitry. Should be connected to a 2.5 –5% to 3.3V +10% power supply.
I/O Ground
–
Ground for the I/O circuitry. Should be connected to ground of the system.
No connects. Reserved for address expansion. Pins are not internally connected.
– No connects. Pins are not internally connected.
Introduction
Functional Overview
All synchronous inputs pass through input registers controlled by the rising edge of the clock. All data outputs pass through output registers controlled by the rising edge of the clock.
Maximum access delay from the clock rise (t
CO
(250-MHz device).
) is 2.6 ns
The CY7C1380C/CY7C1382C supports secondary cache in systems utilizing either a linear or interleaved burst sequence.
The interleaved burst order supports Pentium
®
and i486
processors. The linear burst sequence is suited for processors that utilize a linear burst sequence. The burst order is user selectable, and is determined by sampling the MODE input.
Accesses can be initiated with either the Processor Address
Strobe (ADSP) or the Controller Address Strobe (ADSC).
Address advancement through the burst sequence is controlled by the ADV input. A two-bit on-chip wraparound burst counter captures the first address in a burst sequence and automatically increments the address for the rest of the burst access.
Byte write operations are qualified with the Byte Write Enable
(BWE) and Byte Write Select (BW a,b,c,d
BW a,b for CY7C1380 and
for CY7C1382) inputs. A Global Write Enable (GW) overrides all byte write inputs and writes data to all four bytes.
All writes are simplified with on-chip synchronous self-timed write circuitry.
Synchronous Chip Selects (CE
1
, CE
2
, CE
3 for TQFP/CE
1
for
BGA) and an asynchronous Output Enable (OE) provide for easy bank selection and output three-state control. ADSP is ignored if CE
1
is HIGH.
Single Read Accesses
This access is initiated when the following conditions are satisfied at clock rise: (1) ADSP or ADSC is asserted LOW, (2) chip selects are all asserted active, and (3) the write signals
(GW, BWE) are all deasserted HIGH. ADSP is ignored if CE
1 is HIGH. The address presented to the address inputs is stored into the address advancement logic and the Address
Register while being presented to the memory core. The corresponding data is allowed to propagate to the input of the
Output Registers. At the rising edge of the next clock the data is allowed to propagate through the output register and onto the data bus within 2.6 ns (250-MHz device) if OE is active
LOW. The only exception occurs when the SRAM is emerging from a deselected state to a selected state, its outputs are always three-stated during the first cycle of the access. After the first cycle of the access, the outputs are controlled by the
OE signal. Consecutive single read cycles are supported.
Once the SRAM is deselected at clock rise by the chip select and either ADSP or ADSC signals, its output will three-state immediately.
Single Write Accesses Initiated by ADSP
This access is initiated when both of the following conditions are satisfied at clock rise: (1) ADSP is asserted LOW, and (2) chip select is asserted active. The address presented is loaded into the address register and the address advancement logic while being delivered to the RAM core. The write signals (GW, BWE, and BWx) and ADV inputs are ignored during this first cycle.
ADSP triggered write accesses require two clock cycles to complete. If GW is asserted LOW on the second clock rise, the data presented to the DQx inputs is written into the corresponding address location in the RAM core. If GW is HIGH, then the write operation is controlled by BWE and BWx signals. The CY7C1380C/CY7C1382C provides byte write capability that is described in the Write Cycle Description table.
Asserting the Byte Write Enable input (BWE) with the selected
Byte Write (BW a,b,c,d for CY7C1380C and BW a,b
for
CY7C1382C) input will selectively write to only the desired bytes. Bytes not selected during a byte write operation will remain unaltered. A synchronous self-timed write mechanism has been provided to simplify the write operations.
Because the CY7C1380C/CY7C1382C is a common I/O device, the Output Enable (OE) must be deasserted HIGH before presenting data to the DQ inputs. Doing so will three-state the output drivers. As a safety precaution, DQ are automatically three-stated whenever a write cycle is detected, regardless of the state of OE.
Single Write Accesses Initiated by ADSC
ADSC write accesses are initiated when the following conditions are satisfied: (1) ADSC is asserted LOW, (2) ADSP is deasserted HIGH, (3) chip select is asserted active, and (4) the appropriate combination of the write inputs (GW, BWE, and BWx) are asserted active to conduct a write to the desired byte(s). ADSC triggered write accesses require a single clock cycle to complete. The address presented to A
[17:0]
is loaded into the address register and the address advancement logic while being delivered to the RAM core. The ADV input is
Document #: 38-05237 Rev. *B Page 7 of 28
PRELIMINARY
CY7C1380C
CY7C1382C ignored during this cycle. If a global write is conducted, the data presented to the DQ
[x:0]
is written into the corresponding address location in the RAM core. If a byte write is conducted, only the selected bytes are written. Bytes not selected during a byte write operation will remain unaltered. A synchronous self-timed write mechanism has been provided to simplify the write operations.
Because the CY7C1380C/CY7C1382C is a common I/O device, the Output Enable (OE) must be deasserted HIGH before presenting data to the DQ
[x:0]
inputs. Doing so will three-state the output drivers. As a safety precaution, DQ
[x:0] are automatically three-stated whenever a write cycle is detected, regardless of the state of OE.
Interleaved Burst Sequence
First
Address
A
[1:0]
00
01
10
11
Second
Address
A
[1:0]
01
00
11
10
Third
Address
A
[1:0]
10
11
00
01
Fourth
Address
A
[1:0]
11
10
01
00
Burst Sequences
The CY7C1380C/CY7C1382C provides a two-bit wraparound counter, fed by A
[1:0]
, that implements either an interleaved or linear burst sequence. The interleaved burst sequence is designed specifically to support Intel Pentium applications.
The linear burst sequence is designed to support processors that follow a linear burst sequence. The burst sequence is user selectable through the MODE input.
Asserting ADV LOW at clock rise will automatically increment the burst counter to the next address in the burst sequence.
Both read and write burst operations are supported.
Linear Burst Sequence
First
Address
A
[1:0]
00
01
10
11
Second
Address
A
[1:0]
01
10
11
00
Sleep Mode
The ZZ input pin is an asynchronous input. Asserting ZZ places the SRAM in a power conservation “sleep” mode. Two clock cycles are required to enter into or exit from this “sleep” mode. While in this mode, data integrity is guaranteed.
Accesses pending when entering the “sleep” mode are not considered valid nor is the completion of the operation guaranteed. The device must be deselected prior to entering the “sleep” mode. CEs, ADSP, and ADSC must remain inactive for the duration of t
ZZREC
after the ZZ input returns
LOW.
ZZ Mode Electrical Characteristics
Parameter Description
I
DDZZ t
ZZS t
ZZREC
Sleep mode standby current
Device operation to ZZ
ZZ recovery time
Cycle Descriptions [1, 2, 3, 4]
Test Conditions
ZZ > V
DD
– 0.2V
ZZ > V
DD
– 0.2V
ZZ < 0.2V
Next Cycle
Unselected
Unselected
Unselected
Unselected
Unselected
Begin Read
Begin Read
Add. Used
None
None
None
None
None
External
External
ZZ
0
0
0
0
0
0
0
CE
X
1
X
1
X
0
0
3
CE
X
X
0
X
0
1
1
2
CE
1
0
0
0
0
0
0
1
ADSP ADSC
X 0
0
0
0
1
1
1
X
X
0
0
X
0
Continue Read Next
Continue Read Next
0
0
X
X
X
X
X
X
1
1
1
1
0
0
Continue Read Next 0 X X 1 X 1 0
Notes:
1.
X = “Don't Care.” 1 = HIGH, 0 = LOW.
2.
Write is defined by BWE, BWx, and GW. See Write Cycle Descriptions table.
3.
The DQ pins are controlled by the current cycle and the OE signal. OE is asynchronous and is not sampled with the clock.
4.
CE
1
, CE
2
, and CE
3
are available only in the TQFP package. The BGA package has a single chip select, CE
1
.
X
X
X
X
ADV
X
X
X
Min.
2t
CYC
X
X
X
X
OE
X
X
X
1
0
1
Third
Address
A
[1:0]
10
11
00
01
Max.
60
2t
CYC
DQ
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
DQ
Hi-Z
Fourth
Address
A
[1:0]
11
00
01
10
Unit mA ns ns
X
X
X
Write
X
X
X
Read
Read
Read
Read
Document #: 38-05237 Rev. *B Page 8 of 28
PRELIMINARY
CY7C1380C
CY7C1382C
Cycle Descriptions (continued)
[1, 2, 3, 4]
Next Cycle Add. Used
Continue Read Next
Suspend Read Current
Suspend Read Current
Suspend Read Current
Suspend Read Current
Begin Write Current
Begin Write
Begin Write
Current
External
Continue Write Next
Continue Write Next
Suspend Write
Suspend Write
ZZ “sleep”
Current
Current
None
Function (1380C)
Read
Read
Write Byte 0 – DQa
Write Byte 1 – DQb
Write Bytes 1, 0
Write Byte 2 – DQc
Write Bytes 2, 0
Write Bytes 2, 1
Write Bytes 2, 1, 0
Write Byte 3 – DQd
Write Bytes 3, 0
Write Bytes 3, 1
Write Bytes 3, 1, 0
Write Bytes 3, 2
Write Bytes 3, 2, 0
Write Bytes 3, 2, 1
Write All Bytes
Write All Bytes
0
0
1
0
0
0
0
0
0
0
0
ZZ
0
0
Write Cycle Descriptions [1, 5, 6]
X
X
0
X
X
X
X
X
X
X
CE
3
X
X
X
1
X
0
X
1
X
X
1
1
1
CE
1
1
X
X
X
X
1
X
X
X
X
X
X
X
CE
2
X
X
X
1
X
X
1
X
X
1
ADSP ADSC
X
1
1
1
X
1
1
X
1
1
1
1
1
1
X
1
1
1
0
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
DQ
DQ
Hi-Z
DQ
Hi-Z
DQ
Hi-Z
X
X
X
X
X
X
X
0
X
0
1
OE
0
1
1
1
X
0
0
1
X
ADV
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
GW
1
1
1
1
1
0
BWE
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
X
BWd
X
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
X
BWc
X
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
X
BWb
X
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
X
Read
Read
Function (1382C)
Write Byte 0 – DQ
[7:0] and DP
0
Write Byte 1 – DQ
Write All Bytes
[15:8] and DP
1
GW
1
1
1
1
1
BWE
1
0
0
0
0
BWb
X
1
1
0
0
BWa
X
1
0
1
0
Write All Bytes 0 X X X
Notes:
5.
The SRAM always initiates a read cycle when ADSP asserted, regardless of the state of GW, BWE, or BW x
.
Writes may occur only on subsequent clocks after the ADSP or with the assertion of ADSC. As a result, OE must be driven HIGH prior to the start of the write cycle to allow the outputs to three-state. OE is a
“don't care” for the remainder of the write cycle.
6.
OE is asynchronous and is not sampled with the clock rise. It is masked internally during write cycles. During a read cycle DQ = High-Z when OE is inactive or when the device is deselected, and DQ = data when OE is active.
1
0
1
0
1
0
1
0
1
0
1
0
BWa
X
1
0
1
0
X
Write
Write
Write
Write
Write
Write
X
Write
Read
Read
Read
Read
Read
Write
Document #: 38-05237 Rev. *B Page 9 of 28
IEEE 1149.1 Serial Boundary Scan (JTAG)
The CY7C1380C/CY7C1382C incorporates a serial boundary scan Test Access Port (TAP) in the FBGA package only. The
TQFP package does not offer this functionality. This port operates in accordance with IEEE Standard 1149.1-1900, but does not have the set of functions required for full 1149.1
compliance. These functions from the IEEE specification are excluded because their inclusion places an added delay in the critical speed path of the SRAM. Note that the TAP controller functions in a manner that does not conflict with the operation of other devices using 1149.1 fully compliant TAPs. The TAP operates using JEDEC standard 3.3V I/O logic levels.
Disabling the JTAG Feature
It is possible to operate the SRAM without using the JTAG feature. To disable the TAP controller, TCK must be tied LOW
(V
SS
) to prevent clocking of the device. TDI and TMS are internally pulled up and may be unconnected. They may alternately be connected to V
DD
through a pull-up resistor. TDO should be left unconnected. Upon power-up, the device will come up in a reset state which will not interfere with the operation of the device.
Test Access Port (TAP)—Test Clock
The test clock is used only with the TAP controller. All inputs are captured on the rising edge of TCK. All outputs are driven from the falling edge of TCK.
Test Mode Select
The TMS input is used to give commands to the TAP controller and is sampled on the rising edge of TCK. It is allowable to leave this pin unconnected if the TAP is not used. The pin is pulled up internally, resulting in a logic HIGH level.
Test Data-In (TDI)
The TDI pin is used to serially input information into the registers and can be connected to the input of any of the registers. The register between TDI and TDO is chosen by the instruction that is loaded into the TAP instruction register. For information on loading the instruction register, see the TAP
Controller State Diagram. TDI is internally pulled up and can be unconnected if the TAP is unused in an application. TDI is connected to the Most Significant Bit (MSB) on any register.
Test Data Out (TDO)
The TDO output pin is used to serially clock data-out from the registers. The output is active depending upon the current state of the TAP state machine (see TAP Controller State
Diagram). The output changes on the falling edge of TCK.
TDO is connected to the Least Significant Bit (LSB) of any register.
Performing a TAP Reset
A Reset is performed by forcing TMS HIGH (V
DD
) for five rising edges of TCK. This RESET does not affect the operation of the SRAM and may be performed while the SRAM is operating. At power-up, the TAP is reset internally to ensure that TDO comes up in a high-Z state.
TAP Registers
Registers are connected between the TDI and TDO pins and allow data to be scanned into and out of the SRAM test
PRELIMINARY
CY7C1380C
CY7C1382C circuitry. Only one register can be selected at a time through the instruction registers. Data is serially loaded into the TDI pin on the rising edge of TCK. Data is output on the TDO pin on the falling edge of TCK.
Instruction Register
Three-bit instructions can be serially loaded into the instruction register. This register is loaded when it is placed between the
TDI and TDO pins as shown in the TAP Controller Block
Diagram. Upon power-up, the instruction register is loaded with the IDCODE instruction. It is also loaded with the IDCODE instruction if the controller is placed in a reset state as described in the previous section.
When the TAP controller is in the CaptureIR state, the two least significant bits are loaded with a binary “01” pattern to allow for fault isolation of the board level serial test path.
Bypass Register
To save time when serially shifting data through registers, it is sometimes advantageous to skip certain states. The bypass register is a single-bit register that can be placed between TDI and TDO pins. This allows data to be shifted through the
SRAM with minimal delay. The bypass register is set LOW
(VSS) when the BYPASS instruction is executed.
Boundary Scan Register
The boundary scan register is connected to all the input and output pins on the SRAM. Several no connect (NC) pins are also included in the scan register to reserve pins for higher density devices. The x36 configuration has a 70-bit-long register, and the x18 configuration has a 51-bit-long register.
The boundary scan register is loaded with the contents of the
RAM Input and Output ring when the TAP controller is in the
Capture-DR state and is then placed between the TDI and
TDO pins when the controller is moved to the Shift-DR state.
The EXTEST, SAMPLE/PRELOAD and SAMPLE Z instructions can be used to capture the contents of the Input and
Output ring.
The Boundary Scan Order tables show the order in which the bits are connected. Each bit corresponds to one of the bumps on the SRAM package. The MSB of the register is connected to TDI, and the LSB is connected to TDO.
Identification (ID) Register
The ID register is loaded with a vendor-specific, 32-bit code during the Capture-DR state when the IDCODE command is loaded in the instruction register. The IDCODE is hardwired into the SRAM and can be shifted out when the TAP controller is in the Shift-DR state. The ID register has a vendor code and other information described in the Identification Register
Definitions table.
TAP Instruction Set
Eight different instructions are possible with the three-bit instruction register. All combinations are listed in the
Instruction Code table. Three of these instructions are listed as RESERVED and should not be used. The other five instructions are described in detail below.
The TAP controller used in this SRAM is not fully compliant to the 1149.1 convention because some of the mandatory 1149.1
instructions are not fully implemented. The TAP controller cannot be used to load address, data or control signals into the
Document #: 38-05237 Rev. *B Page 10 of 28
SRAM and cannot preload the Input or Output buffers. The
SRAM does not implement the 1149.1 commands EXTEST or
INTEST or the PRELOAD portion of SAMPLE/PRELOAD; rather it performs a capture of the Input and Output ring when these instructions are executed.
Instructions are loaded into the TAP controller during the
Shift-IR state when the instruction register is placed between
TDI and TDO. During this state, instructions are shifted through the instruction register through the TDI and TDO pins.
To execute the instruction once it is shifted in, the TAP controller needs to be moved into the Update-IR state.
EXTEST
EXTEST is a mandatory 1149.1 instruction which is to be executed whenever the instruction register is loaded with all
0s. EXTEST is not implemented in the TAP controller, and therefore this device is not compliant to the 1149.1 standard.
The TAP controller does recognize an all-0 instruction. When an EXTEST instruction is loaded into the instruction register, the SRAM responds as if a SAMPLE/PRELOAD instruction has been loaded. There is one difference between the two instructions. Unlike the SAMPLE/PRELOAD instruction,
EXTEST places the SRAM outputs in a High-Z state.
IDCODE
The IDCODE instruction causes a vendor-specific, 32-bit code to be loaded into the instruction register. It also places the instruction register between the TDI and TDO pins and allows the IDCODE to be shifted out of the device when the TAP controller enters the Shift-DR state. The IDCODE instruction is loaded into the instruction register upon power-up or whenever the TAP controller is given a test logic reset state.
SAMPLE Z
The SAMPLE Z instruction causes the boundary scan register to be connected between the TDI and TDO pins when the TAP controller is in a Shift-DR state. It also places all SRAM outputs into a High-Z state.
SAMPLE/PRELOAD
SAMPLE/PRELOAD is a 1149.1 mandatory instruction. The
PRELOAD portion of this instruction is not implemented, so the TAP controller is not fully 1149.1-compliant.
PRELIMINARY
CY7C1380C
CY7C1382C
When the SAMPLE/PRELOAD instructions are loaded into the instruction register and the TAP controller is in the Capture-DR state, a snapshot of data on the input and output pins is captured in the boundary scan register.
The user must be aware that the TAP controller clock can only operate at a frequency up to 10 MHz, while the SRAM clock operates more than an order of magnitude faster. Because there is a large difference in the clock frequencies, it is possible that during the Capture-DR state, an input or output will undergo a transition. The TAP may then try to capture a signal while in transition (metastable state). This will not harm the device, but there is no guarantee as to the value that will be captured. Repeatable results may not be possible.
To guarantee that the boundary scan register will capture the correct value of a signal, the SRAM signal must be stabilized long enough to meet the TAP controller’s capture set-up plus hold times (t
CS
and t
CH
). The SRAM clock input might not be captured correctly if there is no way in a design to stop (or slow) the clock during a SAMPLE/PRELOAD instruction. If this is an issue, it is still possible to capture all other signals and simply ignore the value of the CK and CK captured in the boundary scan register.
Once the data is captured, it is possible to shift out the data by putting the TAP into the Shift-DR state. This places the boundary scan register between the TDI and TDO pins.
Note that since the PRELOAD part of the command is not implemented, putting the TAP into the Update to the
Update-DR state while performing a SAMPLE/PRELOAD instruction will have the same effect as the Pause-DR command.
Bypass
When the BYPASS instruction is loaded in the instruction register and the TAP is placed in a Shift-DR state, the bypass register is placed between the TDI and TDO pins. The advantage of the BYPASS instruction is that it shortens the boundary scan path when multiple devices are connected together on a board.
Reserved
These instructions are not implemented but are reserved for future use. Do not use these instructions.
Document #: 38-05237 Rev. *B Page 11 of 28
PRELIMINARY
TAP Controller State Diagram [7]
1
TEST-LOGIC
RESET
0
TEST-LOGIC/
IDLE
1
1
SELECT
DR-SCAN
0
CAPTURE-DR
0
SHIFT-DR
1
0
1
EXIT1-DR
0
1
0 PAUSE-DR
1
0
EXIT2-DR
1
UPDATE-DR
1
0
Note:
7.
The 0/1 next to each state represents the value at TMS at the rising edge of TCK.
CY7C1380C
CY7C1382C
1
SELECT
IR-SCAN
0
1
CAPTURE-DR
0
SHIFT-IR
1
EXIT1-IR
0
PAUSE-IR
1
0
EXIT2-IR
1
0
1
0
UPDATE-IR
1
0
Document #: 38-05237 Rev. *B Page 12 of 28
PRELIMINARY
TAP Controller Block Diagram
TDI
Selection
Circuitry
Bypass Register
0
2
Instruction Register
1 0
31 30 29 .
.
2
Identification Register
1 0
.
.
.
.
.
2 1
Boundary Scan Register
0
CY7C1380C
CY7C1382C
Selection
Circuitry
TDO
TCK
TMS
TAP Controller
TAP Electrical Characteristics Over the Operating Range (3.135
≤
V
DD
≤
3.63)
[8, 9]
V
OH1
V
OH2
V
OL1
V
OL2
V
IH
V
IL
I
X
Parameter Description
Output HIGH Voltage I
OH
=
−
4.0 mA
Output HIGH Voltage I
OH
=
−
100
µ
A
Output LOW Voltage
Output LOW Voltage
I
OL
= 8.0 mA
I
OL
= 100
µ
A
Input HIGH Voltage
Input LOW Voltage
Input Load Current GND
≤
V
I
≤
V
DDQ
Test Conditions
V
V
V
V
V
V
DDQ
DDQ
DDQ
DDQ
DDQ
DDQ
= 3.3V
= 3.3V
= 3.3V
= 3.3V
= 3.3V
= 3.3V
TAP AC Switching Characteristics Over the Operating Range
[10, 11]
Parameters Description t
TCYC t
TF t
TH
TCK Clock Cycle Time
TCK Clock Frequency
TCK Clock HIGH t
TL
TCK Clock LOW
Notes:
8.
All Voltage referenced to Ground.
9.
10. t
Overshoot: V
CS
and t
CH
IH
(AC) < V
DD
+ 1.5V for t < t
TCYC
/2, undershoot:V
IL
(AC) >
−
0.5V for t < t
11.
Test conditions are specified using the load in TAP AC Test Conditions. t
R
TCYC
/t
F
= 1 V/ ns.
/2.
refer to the set-up and hold time requirements of latching data from the boundary scan register.
Min.
2.4
2.9
2.0
–0.5
–5
Min.
100
40
40
Max.
0.4
0.2
V
DD
+
0.3
0.7
5
V
V
V
µ
A
Unit
V
V
V
Max.
10
Unit ns
MHz ns ns
Document #: 38-05237 Rev. *B Page 13 of 28
PRELIMINARY
TAP AC Switching Characteristics Over the Operating Range (continued)
[10, 11]
Description Parameters
Set-up Times t
TMSS t
TDIS t
CS
Hold Times t
TMSH t
TDIH t
CH
Output Times t
TDOV t
TDOX
TMS Set-up to TCK Clock Rise
TDI Set-up to TCK Clock Rise
Capture Set-up to TCK Rise
TMS Hold after TCK Clock Rise
TDI Hold after Clock Rise
Capture Hold after Clock Rise
TCK Clock LOW to TDO Valid
TCK Clock LOW to TDO Invalid
TAP Timing and Test Conditions
1.5V
50
Ω
Min.
10
10
10
10
10
10
0
3.0V
ALL INPUT PULSES
1.50V
0V
TDO
Z
0
= 50
Ω
C
L
= 20 pF
CY7C1380C
CY7C1382C
Max.
20
Unit ns ns ns ns ns ns ns ns
(a)
GND t
TH t
TL
Test Clock
TCK t
TCYC t
TMSS t
TMSH
Test Mode Select
TMS t
TDIS t
TDIH
Test Data-In
TDI
Test Data-Out
TDO t
TDOV t
TDOX
Document #: 38-05237 Rev. *B Page 14 of 28
PRELIMINARY
CY7C1380C
CY7C1382C
Identification Register Definitions
Instruction Field
Revision Number (31:28)
Cypress Device ID (27:24)
Device Type (23:18)
Device Width and Density (17:12)
Cypress JEDEC ID (11:0)
512K x 36
0100
1010
000000
1M x 18
0100
1010
000000
Description
Reserved for version number.
Reserved for internal use.
Defines memory type and architecture
100101 010101 Defines width and density.
000001101001 000001101001 Allows unique identification of SRAM vendor.
Scan Register Sizes
Register Name
Instruction
Bypass
ID
Boundary Scan
Bit Size (x18)
3
1
32
51
Identification Codes
Instruction
EXTEST
Code
000
IDCODE
SAMPLE Z
RESERVED 011
SAMPLE/PRELOAD 100
RESERVED
RESERVED
BYPASS
001
010
101
110
111
Bit Size (x36)
3
1
32
70
Description
Captures the Input/Output ring contents. Places the boundary scan register between the TDI and TDO. Forces all SRAM outputs to High-Z state. This instruction is not 1149.1-compliant.
Loads the ID register with the vendor ID code and places the register between TDI and TDO.
This operation does not affect SRAM operation.
Captures the Input/Output contents. Places the boundary scan register between TDI and TDO.
Forces all SRAM output drivers to a High-Z state.
Do Not Use: This instruction is reserved for future use.
Captures the Input/Output ring contents. Places the boundary scan register between TDI and
TDO. Does not affect the SRAM operation. This instruction does not implement 1149.1 preload function and is therefore not 1149.1-compliant.
Do Not Use: This instruction is reserved for future use.
Do Not Use: This instruction is reserved for future use.
Places the bypass register between TDI and TDO. This operation does not affect SRAM operation.
Boundary Scan Order (512K × 36) – 119 BGA
9
10
11
12
13
14
7
8
5
6
3
4
1
2
Bit #
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
Signal
Name
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
Bump
ID
TBD
TBD
TBD
TBD
TBD
TBD
47
48
49
43
44
45
46
39
40
41
42
36
Bit #
37
38
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
Signal
Name Bump ID
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
Boundary Scan Order (512K × 36) – 119 BGA
25
26
27
28
21
22
23
24
17
18
19
20
Bit #
15
16
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
Signal
Name
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
Bump
ID
TBD
TBD
TBD
TBD
TBD
TBD
60
61
62
63
56
57
58
59
52
53
54
55
Bit #
50
51
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
Signal
Name Bump ID
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
Document #: 38-05237 Rev. *B Page 15 of 28
Boundary Scan Order (512K × 36) – 119 BGA
31
32
33
34
35
29
30
Bit #
Signal
Name
TBD
TBD
TBD
TBD
TBD
TBD
TBD
Bump
ID
TBD
TBD
TBD
TBD
TBD
TBD
TBD
66
67
68
69
70
64
65
Bit #
Signal
Name Bump ID
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
Boundary Scan Order (1M × 18) – 119 BGA
8
9
10
11
12
13
6
7
4
5
2
3
1
Bit #
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
Signal
Name
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
Bump
ID
TBD
TBD
TBD
TBD
TBD
43
44
45
46
47
48
39
40
41
42
Bit #
36
37
38
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
Signal
Name
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
Bump
ID
TBD
TBD
TBD
TBD
TBD
PRELIMINARY
CY7C1380C
CY7C1382C
Boundary Scan Order (1M × 18) – 119 BGA
23
24
25
26
19
20
21
22
Bit #
14
15
16
17
18
31
32
33
34
35
27
28
29
30
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
Bump
ID
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
Signal
Name
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
58
59
60
61
54
55
56
57
Bit #
49
50
51
52
53
66
67
68
69
70
62
63
64
65
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
Signal
Name
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
Bump
ID
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
Document #: 38-05237 Rev. *B Page 16 of 28
PRELIMINARY
CY7C1380C
CY7C1382C
Maximum Ratings
(Above which the useful life may be impaired. For user guidelines, not tested.)
Storage Temperature .................................–65°C to +150°C
Ambient Temperature with
Power Applied............................................. –55°C to +125°C
Supply Voltage on V
DD
Relative to GND........ –0.3V to +4.6V
DC Voltage Applied to Outputs in High-Z State
[12]
............................... –0.5V to V
DDQ
+ 0.5V
DC Input Voltage
[12]
............................. –0.5V to V
DDQ
+ 0.5V
Current into Outputs (LOW)......................................... 20 mA
Static Discharge Voltage........................................... >2001V
(per MIL-STD-883, Method 3015)
Latch-up Current..................................................... >200 mA
Operating Range
Range
Com’l
Ind’l
Ambient
Temperature
0°C to +70°C
–40°C to +85°C
Electrical Characteristics Over the Operating Range
I
I
I
Parameter
V
DD
V
DDQ
V
OH
V
V
V
X
OL
IH
IL
OZ
DD
Description
Power Supply Voltage
I/O Supply Voltage
Output HIGH Voltage
Output LOW Voltage
Test Conditions
V
DD
= Min., I
OH
= –4.0 mA
V
DD
= Min., I
OH
= –1.0 mA
V
DD
= Min., I
OL
= 8.0 mA
V
DD
= Min., I
OL
= 1.0 mA
3.3V
2.5V
3.3V
Input HIGH Voltage
2.5V
3.3V
2.5V
3.3V Input LOW Voltage
[12]
2.5V
Input Load Current GND < V
I
< V
DDQ
Input Current of MODE
Input Current of ZZ Input = V
SS
Output Leakage Current GND < V
I
< V
DDQ,
Output Disabled
V
DD
Operating Supply V
DD
= Max., I f = f
MAX
OUT
= 0 mA,
= 1/t
CYC
4.0-ns cycle, 250 MHz
4.4-ns cycle, 225 MHz
5.0-ns cycle, 200 MHz
I
I
I
SB1
SB2
SB3
Automatic CE
Power-down
Current—TTL Inputs
Automatic CE
Power-down
Current—CMOS Inputs
Automatic CE
Power-down
Current—CMOS Inputs
6.0-ns cycle, 167 MHz
7.5-ns cycle, 133 MHz
Max. V
DD
, Device Deselected,
V
IN
> V
IH
or V
IN
<V
IL f = f
MAX
= 1/t
CYC
4.0-ns cycle, 250 MHz
4.4-ns cycle, 225 MHz
5.0-ns cycle, 200 MHz
6.0-ns cycle, 167 MHz
7.5-ns cycle, 133 MHz
Max. V
DD
, Device Deselected,
V
IN
< 0.3V or V
0.3V, f = 0
IN
> V
DDQ
–
All speed grades
Max. V or V
IN
DD
, Device Deselected,
≤
0.3V or V
0.3V f = f
MAX
IN
> V
= 1/t
CYC
DDQ
−
4.0-ns cycle, 250 MHz
4.4-ns cycle, 225 MHz
5.0-ns cycle, 200 MHz
6.0-ns cycle, 167 MHz
I
SB4
Automatic CS
Power-down
Current—TTL Inputs
Shaded areas contain advance information.
Note:
12. Minimum voltage equals –2.0V for pulse durations of less than 20 ns.
7.5-ns cycle, 133 MHz
Max. V
V
IN
≥
V
DD
IH
, Device Deselected,
or V
IN
≤
V
IL
, f = 0
All Speeds
V
DD
3.3V
–5%/+10%
Min.
3.135
2.375
2.4
2.0
2.0
1.7
–0.3
–0.3
–5
–30
–30
–5
V
DDQ
2.5V – 5%
3.3V + 10%
105
100
95
85
80
80
Max.
3.63
V
DD
0.4
0.4
V
V
DD
+ 0.3
V
V
DD
+ 0.3
V
0.8
V
V
V
Unit
V
V
V mA mA mA mA
V
µ
A
µ
A
µ
A
µ
A mA mA mA mA mA mA mA
275
245
120
110
100
90
85
70
5
350
325
300
0.7
5
30
30 mA mA mA mA mA mA
Document #: 38-05237 Rev. *B Page 17 of 28
PRELIMINARY
CY7C1380C
CY7C1382C
Capacitance [13]
Parameter
C
IN
C
CLK
C
I/O
Description
Input Capacitance
Clock Input Capacitance
Input/Output Capacitance
AC Test Loads and Waveforms [14]
Test Conditions
T
A
= 25
°
C, f = 1 MHz
100-TQFP
TBD
TBD
TBD
Max.
119-BGA
TBD
TBD
TBD
165-FBGA
TBD
TBD
TBD
Unit pF pF pF
OUTPUT
Z
0
= 50
Ω
3.3/2.5V
R t
= 50
Ω
OUTPUT
R = 317/1667
Ω
V
CC
10%
ALL INPUT PULSES
[14]
90%
90%
10%
30 pF
V t
= 1.5 for 3.3V V
DDQ
1.25V for 2.5V V
DDQ
V t
- Termination Voltage
R t
- Termination Resistance (a)
5 pF GND
R = 351/1538
Ω
< 1ns
INCLUDING
JIG AND
SCOPE
(b)
< 1ns
(c)
Thermal Resistance [13]
Parameter
Θ
JA
Θ
JC
Description Test Conditions
Thermal Resistance (Junction to Ambient) Still Air, soldered on a 3 x 4.5
Thermal Resistance (Junction to Case) inch
2
, two-layer printed circuit board
TQFP 119 BGA 165 FBGA Unit
31
6
45
7
46
3
°
C/W
°
C/W
Switching Characteristics Over the Operating Range
[15, 16, 17]
-250 -225 -200 -167 -133
Parameter Description Min. Max. Min. Max. Min. Max. Min. Max. Min. Max.
Unit t
CYC t
CH t
CL t
AS t
AH t
CO t
DOH t
ADS
Clock Cycle Time
Clock HIGH
Clock LOW
Address Set-up Before CLK Rise
Address Hold After CLK Rise
Data Output Valid After CLK Rise
Data Output Hold After CLK Rise
ADSP, ADSC Set-up Before CLK Rise
4.0
1.7
1.7
1.2
0.3
1.0
1.2
2.6
4.4
2.0
2.0
1.4
0.4
1.0
1.4
2.8
5
2.0
2.0
1.4
0.4
1.3
1.4
3.0
6
2.2
2.2
1.5
0.5
1.3
1.5
3.4
7.5
2.5
2.5
1.5
0.5
1.3
1.5
4.2
ns ns ns ns ns ns ns ns t
ADH t
WES t
WEH t
ADVS t
ADVH t
DS t
DH t
CES
ADSP, ADSC Hold After CLK Rise
BWE, GW, BW
BWE, GW, BW x x
Set-up Before CLK Rise
Hold After CLK Rise
ADV Set-up Before CLK Rise
ADV Hold After CLK Rise
Data Input Set-up Before CLK Rise
Data Input Hold After CLK Rise
Chip enable Set-up
0.3
1.2
0.3
1.2
0.3
1.2
0.3
1.2
0.4
1.4
0.4
1.4
0.4
1.4
0.4
1.4
0.4
1.4
0.4
1.4
0.4
1.4
0.4
1.4
0.5
1.5
0.5
1.5
0.5
1.5
0.5
1.5
0.5
1.5
0.5
1.5
0.5
1.5
0.5
1.5
ns ns ns ns ns ns ns ns t
CEH
Chip enable Hold After CLK Rise 0.3
0.4
0.4
0.5
0.5
ns
Shaded areas contain advance information.
Notes:
13. Tested initially and after any design or process changes that may affect these parameters.
14. Input waveform should have a slew rate of < 1 ns.
15. Unless otherwise noted, test conditions assume signal transition time of 1 ns or less, timing reference levels of 1.5/1.25V, input pulse levels of 0 to 3.0/2.5V for 3.3/2.5V V
DDQ
respectively, and output loading of the specified I
16. t
CHZ
, t
CLZ
, t voltage.
OEV
, t
EOLZ
, and t
EOHZ
OL
/I
OH
and load capacitance. Shown in (a), (b) and (c) of AC Test Loads.
are specified with a load capacitance of 5 pF as in (b) of AC Test Loads. Transition is measured
±
200 mV from steady-state
17. At any given voltage and temperature, t
EOHZ
is less than t
EOLZ
and t
CHZ
is less than t
CLZ
.
Document #: 38-05237 Rev. *B Page 18 of 28
PRELIMINARY
CY7C1380C
CY7C1382C
Switching Characteristics Over the Operating Range
[15, 16, 17]
Parameter t
CHZ t
CLZ t
EOHZ t
EOLZ t
EOV
Description
Clock to High-Z
[16]
Clock to Low-Z
[16]
OE HIGH to Output High-Z
[16, 17]
OE LOW to Output Low-Z
[16, 17]
OE LOW to Output Valid
[16]
Min. Max. Min. Max. Min. Max. Min. Max. Min. Max.
Unit
1.0
-250
2.6
1.0
-225
2.8
-200
1.3
3.0
-167
1.3
3.4
-133
1.3
3.4
ns ns
2.6
2.8
3.0
3.4
0
2.6
0
2.8
0
3.0
0
3.4
0
4.0
ns ns
4.2
ns
Switching Waveforms
Write Cycle Timing
[4, 18, 19, 20]
Single Write Burst Write
Pipelined Write t
CH
Unselected t
CYC
CLK t
ADH t
ADS t
CL
ADSP ignored with CE
1
inactive
ADSP t
ADS t
ADH ADSC initiated write
ADSC t
ADVS t
ADVH
ADV
ADD t
AS
WD1
ADV Must Be Inactive for ADSP Write
WD2 t
AH
GW t
WS t
WH t
WH t
WS
WE t
CES t
CEH
CE
1
masks ADSP
CE
1 t
CES t
CEH
CE
2
WD3
Unselected with CE
2
CE
3 t
CES t
CEH
OE t
DH t
DS
Data In High-Z
2a 2b 2c 2d
= UNDEFINED = DON’T CARE
Notes:
18. WE is the combination of BWE and BWx to define a write cycle (see Write Cycle Descriptions table).
19. WDx stands for Write Data to Address X.
20. Device originally deselected.
3a
High-Z
Document #: 38-05237 Rev. *B Page 19 of 28
PRELIMINARY
CY7C1380C
CY7C1382C
Switching Waveforms (continued)
Read Cycle Timing
[4, 18, 20, 21]
Single Read t
CYC t
CH
CLK t
ADS
ADSP t
ADH t
CL t
ADS
ADSC t
ADVS t
ADH
ADV t
AS t
ADVH
ADD RD1 RD2 t
AH
GW t
WS t
WH
WE t
CES t
CEH
CE
1 t
WS
Burst Read t
WH
Suspend Burst
Pipelined Read
ADSP ignored with CE
1
inactive
ADSC initiated read
RD3
CE
1
masks ADSP
Unselected
Unselected with CE
2
CE
2 t
CES
CE
3 t
CES
OE t
CEH t
CEH t
EOV
Data Out t
CO t
OEHZ
2a t
CLZ
= DON’T CARE t
DOH
2b 2c 2c
= UNDEFINED
2d 3a t
CHZ
Note:
21. RDx stands for Read Data from Address X.
Document #: 38-05237 Rev. *B Page 20 of 28
PRELIMINARY
Switching Waveforms (continued)
Read/Write Cycle Timing
[4, 18, 19, 20, 21]
Single Read t
CYC
Single Write t
CH
CLK t
ADS
ADSP t
ADH t
CL
Single Write
Burst Read
ADSC t
ADVS
ADV
ADD t
AS
RD1 t
AH
GW t
ADVH
WD2 t
WS t
WH
WE t
CES
CE
1 t
CEH t
WS t
WH
WD3 RD4 RD5
CY7C1380C
CY7C1382C
Single cycle deselect
Pipelined Read
CE
1
Unselected
CE
2 t
CES
CE
3 t
CES
OE
Data In/Out t
CEH t
CEH t
EOV t
EOLZ t
CO
Out t
EOHZ
2a
In
3a
In
= DON’T CARE = UNDEFINED t
DS
4a
Out t
DH
4b
Out
4c
Out t
DOH
4d
Out t
CHZ
I/O Disabled within one clock cycle after deselect
Document #: 38-05237 Rev. *B Page 21 of 28
PRELIMINARY
Switching Waveforms (continued)
Pipelined Read/Write Timing
[4, 18, 19, 20, 21]
ADSC read ADSP read
Selected
Unselected ADSC write
CLK
ADSP write
CY7C1380C
CY7C1382C
ADSP
ADSC
ADV
CE
2
CE
3
OE
ADD RD1 RD2 RD3 RD4
GW
WE
CE
1
Data In/Out
WD5 WD6
2a
Out
3a
Out
= DON’T CARE
4a
Out
5a
In
= UNDEFINED
6a
In
WD7
OE Switching Waveforms
OE
I/Os t
EOHZ three-state t
EOV
7a
In
WD8 t
EOLZ
Document #: 38-05237 Rev. *B Page 22 of 28
PRELIMINARY
CY7C1380C
CY7C1382C
Switching Waveforms (continued)
ZZ Mode Timing
[4, 22, 23]
CLK
ADSP
ADSC
CE
1
CE
2
CE
3
HIGH
LOW
HIGH
ZZ
I
DD
I/Os
I
DD t
ZZS
(active)
I
DDZZ t
ZZREC
Three-state
Notes:
22. Device must be deselected when entering ZZ mode. See Cycle Descriptions Table for all possible signal conditions to deselect the device.
23. I/Os are in three-state when exiting ZZ sleep mode.
Document #: 38-05237 Rev. *B Page 23 of 28
PRELIMINARY
Ordering Information
Speed
(MHz)
250
225
Ordering Code
CY7C1382C-250AC
CY7C1380C-250AC
CY7C1382C-250BGC
CY7C1380C-250BGC
CY7C1382C-250BZC
CY7C1380C-250BZC
CY7C1382C-225AC
CY7C1380C-225AC
CY7C1382C-225BGC
CY7C1380C-225BGC
Package
Name
A101
BG119
BB165A
A101
Package Type
100-Lead Thin Quad Flat Pack
119 PBGA
165 FBGA
100-Lead Thin Quad Flat Pack
200
167
CY7C1382C-225BZC
CY7C1380C-225BZC
CY7C1382C-200AC
CY7C1380C-200AC
CY7C1380C-200BGC
CY7C1382C-200BGC
CY7C1382C-200BZC
CY7C1380C-200BZC
CY7C1382C-167AC
CY7C1380C-167AC
CY7C1382C-167BGC
CY7C1380C-167BGC
BG119
BG119
BB165A
A101
BG119
BG119
BB165A
A101
119 PBGA
119 PBGA
165 FBGA
100-Lead Thin Quad Flat Pack
119 PBGA
119 PBGA
165 FBGA
100-Lead Thin Quad Flat Pack
BG119
BG119
BB165A
119 PBGA
119 PBGA
165 FBGA
133
167
CY7C1382C-167BZC
CY7C1380C-167BZC
CY7C1380C-133AC
CY7C1382C-167AI
CY7C1380C-167AI
CY7C1382C-167BGI
CY7C1380C-167BGI
A101
A101
BG119
100-Lead Thin Quad Flat Pack
100-Lead Thin Quad Flat Pack
119 PBGA
CY7C1382C-167BZI
CY7C1380C-167BZI
BB165A
Shaded areas contain advance information and parts that may not be offered.
165 FBGA
CY7C1380C
CY7C1382C
Operating
Range
Commercial
Industrial
Document #: 38-05237 Rev. *B Page 24 of 28
Package Diagrams
PRELIMINARY
100-pin Thin Plastic Quad Flatpack (14 x 20 x 1.4 mm) A101
CY7C1380C
CY7C1382C
Document #: 38-05237 Rev. *B
51-85050-A
Page 25 of 28
PRELIMINARY
Package Diagrams (continued)
119-lead PBGA (14 x 22 x 2.4 mm) BG119
CY7C1380C
CY7C1382C
Document #: 38-05237 Rev. *B
51-85115-*B
Page 26 of 28
PRELIMINARY
Package Diagrams (continued)
165-Ball FBGA (13 x 15 x 1.2 mm) BB165A
CY7C1380C
CY7C1382C
51-85122-*C
Intel and Pentium are registered trademarks, and i486 is a trademark, of Intel Corporation. All product and company names mentioned in this document may be the trademarks of their respective holders.
Document #: 38-05237 Rev. *B Page 27 of 28
© Cypress Semiconductor Corporation, 2002. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress
Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges.
PRELIMINARY
CY7C1380C
CY7C1382C
Document History Page
Document Title: CY7C1380C/CY7C1382C 512K x 36/1M x 18 Pipelined SRAM
Document Number:38-05237
Rev.
**
*A
ECN No.
116277
121540
Issue
Date
08/27/02
11/21/02
Orig. of
Change
SKX
DSG
New Data Sheet
Updated package diagrams 51-85115 (BG119) to rev. *B and 51-85122
(BB165A) to rev. *C.
Description of Change
*B 121797 12/19/02 CJM Added 7C1380C-133 spec.
Updated ordering information.
Document #: 38-05237 Rev. *B Page 28 of 28
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