Belkin XM Commander Specifications

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Belkin XM Commander Specifications | Manualzz

REF: BB_SRM_xM BeagleBoard-xM System

Reference Manual

Revision A2

BeagleBoard-xM Rev A2

System Reference Manual

Revision 0.1

July 7, 2010

Page 1 of 164

REF: BB_SRM_xM BeagleBoard-xM System

Reference Manual

Revision A2

THIS DOCUMENT

This work is licensed under the Creative Commons Attribution-Share Alike 3.0 Unported

License. To view a copy of this license, visit http://creativecommons.org/licenses/bysa/3.0/ or send a letter to Creative Commons, 171 Second Street, Suite 300, San

Francisco, California, 94105, USA.

All derivative works are to be attributed to Gerald Coley of BeagleBoard.org.

For more information, see http://creativecommons.org/license/resultsone?license_code=by-sa

For any questions, concerns, or issues submit them to [email protected]

BEAGLEBOARD DESIGN

These design materials referred to in this document are *NOT SUPPORTED* and DO

NOT constitute a reference design. Only “community” support is allowed via resources at BeagleBoard.org/discuss.

THERE IS NO WARRANTY FOR THE DESIGN MATERIALS, TO THE EXTENT

PERMITTED BY APPLICABLE LAW. EXCEPT WHEN OTHERWISE STATED IN

WRITING THE COPYRIGHT HOLDERS AND/OR OTHER PARTIES PROVIDE

THE DESIGN MATERIALS “AS IS” WITHOUT WARRANTY OF ANY KIND,

EITHER EXPRESSED OR IMPLIED, INCLUDING, BUT NOT LIMITED TO, THE

IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A

PARTICULAR PURPOSE. THE ENTIRE RISK AS TO THE QUALITY AND

PERFORMANCE OF THE DESIGN MATERIALS IS WITH YOU. SHOULD THE

DESIGN MATERIALS PROVE DEFECTIVE, YOU ASSUME THE COST OF ALL

NECESSARY SERVICING, REPAIR OR CORRECTION.

We mean it; these design materials may be totally unsuitable for any purposes.

Page 2 of 164

REF: BB_SRM_xM BeagleBoard-xM System

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BeagleBoard.org provides the enclosed product(s) under the following conditions:

This evaluation board/kit is intended for use for ENGINEERING DEVELOPMENT, DEMONSTRATION, OR

EVALUATION PURPOSES ONLY and is not considered by BeagleBoard.org to be a finished end-product fit for general consumer use. Persons handling the product(s) must have electronics training and observe good engineering practice standards. As such, the goods being provided are not intended to be complete in terms of required design-, marketing-, and/or manufacturing-related protective considerations, including product safety and environmental measures typically found in end products that incorporate such semiconductor components or circuit boards. This evaluation board/kit does not fall within the scope of the

European Union directives regarding electromagnetic compatibility, restricted substances (RoHS), recycling

(WEEE), FCC, CE or UL, and therefore may not meet the technical requirements of these directives or other related directives.

Should this evaluation board/kit not meet the specifications indicated in the User’s Guide, the board/kit may be returned within 30 days from the date of delivery for a full refund. THE FOREGOING WARRANTY IS

THE EXCLUSIVE WARRANTY MADE BY SELLER TO BUYER AND IS IN LIEU OF ALL OTHER

WARRANTIES, EXPRESSED, IMPLIED, OR STATUTORY, INCLUDING ANY WARRANTY OF

MERCHANTABILITY OR FITNESS FOR ANY PARTICULAR PURPOSE.

The user assumes all responsibility and liability for proper and safe handling of the goods. Further, the user indemnifies BeagleBoard.org from all claims arising from the handling or use of the goods. Due to the open construction of the product, it is the user’s responsibility to take any and all appropriate precautions with regard to electrostatic discharge.

EXCEPT TO THE EXTENT OF THE INDEMNITY SET FORTH ABOVE, NEITHER PARTY SHALL BE

LIABLE TO THE OTHER FOR ANY INDIRECT, SPECIAL, INCIDENTAL, OR CONSEQUENTIAL

DAMAGES.

BeagleBoard.org currently deals with a variety of customers for products, and therefore our arrangement with the user is not exclusive. BeagleBoard.org assumes no liability for applications assistance, customer product design, software performance, or infringement of patents or services described

herein.

Please read the User’s Guide and, specifically, the Warnings and Restrictions notice in the User’s Guide prior to handling the product. This notice contains important safety information about temperatures and voltages. For additional information on BeagleBoard.org environmental and/or safety programs, please contact visit BeagleBoard.org

.

No license is granted under any patent right or other intellectual property right of BeagleBoard.org covering or relating to any machine, process, or combination in which such BeagleBoard.org products or services might be or are used.

Mailing Address:

BeagleBoard.org

675 North Glenville #195

Richardson, TX 75081

Page 3 of 164

REF: BB_SRM_xM BeagleBoard-xM System

Reference Manual

Revision A2

WARRANTY: The BeagleBoard is warranted against defects in materials and workmanship for a period of 90 days from purchase. This warranty does not cover any problems occurring as a result of improper use, modifications, exposure to water, excessive voltages, abuse, or accidents. All boards will be returned via standard mail if an issue is found. If no issue is found or express return

is needed, the customer will pay all shipping costs.

Before returning the board, please visit BeagleBoard.org/support

Please refer to sections 12 and 13 of this document for the board checkout procedures and troubleshooting guides.

To return a defective board, please request an RMA at http://beagleboard.org/support/rma .

Page 4 of 164

REF: BB_SRM_xM BeagleBoard-xM System

Reference Manual

Revision A2

Table of Contents

FIGURES .......................................................................................................................................................9

TABLES.......................................................................................................................................................11

1.0

INTRODUCTION.........................................................................................................................13

2.0

CHANGE HISTORY....................................................................................................................15

2.1

C HANGE H ISTORY .......................................................................................................................15

2.2

R EVISION C4 VS .

– X M R EVISION A2...........................................................................................15

2.2.1

Hardware Changes................................................................................................................15

2.2.2

Software Changes..................................................................................................................16

3.0

DEFINITIONS AND REFERENCES.........................................................................................17

3.1

D EFINITIONS ...............................................................................................................................17

4.0

BEAGLEBOARD OVERVIEW..................................................................................................17

4.1

B EAGLE B OARD V ERSIONS ..........................................................................................................17

5.0

BEAGLEBOARD SPECIFICATION.........................................................................................19

5.1

B EAGLE B OARD F EATURES ..........................................................................................................19

5.2

P ROCESSOR .................................................................................................................................20

5.3

M EMORY .....................................................................................................................................20

5.4

P OWER M ANAGEMENT ................................................................................................................20

5.5

HS USB 2.0

OTG P ORT ..............................................................................................................21

5.6

HS USB 2.0

H OST P ORT .............................................................................................................21

5.7

S TEREO A UDIO O UTPUT C ONNECTOR .........................................................................................22

5.8

S TEREO A UDIO I N C ONNECTOR ..................................................................................................22

5.9

S-V IDEO C ONNECTOR .................................................................................................................22

5.10

DVI-D C ONNECTOR ....................................................................................................................22

5.11

LCD H EADER .............................................................................................................................22

5.12

MICRO SD C ONNECTOR ...............................................................................................................23

5.13

R ESET B UTTON ...........................................................................................................................23

5.14

U SER B UTTON .............................................................................................................................23

5.15

I NDICATORS ................................................................................................................................23

5.16

P OWER C ONNECTOR ...................................................................................................................23

5.17

JTAG C ONNECTOR .....................................................................................................................24

5.18

RS232 DB9 C ONNECTOR ............................................................................................................24

5.19

M AIN E XPANSION H EADER .........................................................................................................24

5.20

C AMERA C ONNECTOR .................................................................................................................24

5.21

MMC3 E XPANSION H EADER ......................................................................................................24

5.22

M C BSP E XPANSION H EADER .....................................................................................................25

5.23

B EAGLE B OARD M ECHANICAL S PECIFICATIONS ..........................................................................25

5.24

E LECTRICAL S PECIFICATIONS .....................................................................................................26

6.0

PRODUCT CONTENTS..............................................................................................................28

6.1

B EAGLE B OARD I N THE B OX .......................................................................................................28

6.2

S OFTWARE ON THE B EAGLE B OARD ............................................................................................29

6.3

R EPAIRS ......................................................................................................................................29

7.0

BEAGLEBOARD HOOKUP.......................................................................................................30

7.1

C ONNECTING USB OTG.............................................................................................................30

7.2

C ONNECTING USB H OST ............................................................................................................31

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7.3

C ONNECTING DC P OWER ............................................................................................................32

7.4

C ONNECTING JTAG....................................................................................................................33

7.5

C ONNECTING S ERIAL C ABLE ......................................................................................................34

7.6

C ONNECTING S-V IDEO ................................................................................................................35

7.7

C ONNECTING DVI-D C ABLE .......................................................................................................36

7.8

C ONNECTING S TEREO O UT C ABLE ..............................................................................................37

7.9

C ONNECTING S TEREO I N C ABLE .................................................................................................38

7.10

I NDICATOR L OCATIONS ...............................................................................................................39

7.11

B UTTON L OCATIONS ...................................................................................................................40

7.12

MICRO SD C ONNECTION ..............................................................................................................41

7.13

LCD C ONNECTION ......................................................................................................................42

8.0

BEAGLEBOARD SYSTEM ARCHITECTURE AND DESIGN.............................................43

8.1

S YSTEM B LOCK D IAGRAM ..........................................................................................................43

8.2

O VER V OLTAGE P ROTECTION .....................................................................................................45

8.2.1

Detection ...............................................................................................................................46

8.2.2

Indication ..............................................................................................................................46

8.2.3

Shutdown ...............................................................................................................................46

8.3

P OWER C ONDITIONING ...............................................................................................................47

8.3.1

USB DC Source.....................................................................................................................48

8.3.2

Wall Supply Source ...............................................................................................................48

8.3.3

DC Source Control................................................................................................................48

8.3.4

AUX 3.3V Supply...................................................................................................................49

8.4

M ETER C URRENT M EASUREMENT ..............................................................................................50

8.5

P ROCESSOR C URRENT M EASUREMENT .......................................................................................50

8.6

VBAT P OWER C ONDITIONING ....................................................................................................52

8.7

TPS65950 R ESET AND P OWER M ANAGEMENT ...........................................................................53

8.7.1

Main Core Voltages...............................................................................................................53

8.7.2

Main DC Input.......................................................................................................................53

8.7.3

Processor I2C Control ..........................................................................................................53

8.7.4

VIO_1V8................................................................................................................................53

8.7.5

Main Core Voltages Smart Reflex .........................................................................................56

8.7.6

VOCORE_1V3.......................................................................................................................56

8.7.7

VDD2.....................................................................................................................................56

8.8

P ERIPHERAL V OLTAGES ..............................................................................................................57

8.8.1

VDD_PLL2............................................................................................................................57

8.8.2

VDD_PLL1............................................................................................................................58

8.8.3

VDAC_1V8 ............................................................................................................................58

8.8.4

VDD_SIM ..............................................................................................................................59

8.8.5

VMMC2 .................................................................................................................................59

8.8.6

VDD_VMMC1 .......................................................................................................................59

8.8.7

CAM_2V8 ..............................................................................................................................59

8.8.8

CAM_1V8 ..............................................................................................................................59

8.8.9

USB_1V8 ...............................................................................................................................59

8.8.10

EXP_VDD.........................................................................................................................60

8.9

O THER S IGNALS ..........................................................................................................................60

8.9.1

Boot Configuration................................................................................................................60

8.9.2

RTC Backup Battery..............................................................................................................60

8.9.3

Power Sequencing .................................................................................................................61

8.9.4

Reset Signals .........................................................................................................................62

8.9.5

mSecure Signal......................................................................................................................63

8.10

P ROCESSOR .................................................................................................................................64

8.10.1

Overview...........................................................................................................................64

8.10.2

SDRAM Bus ......................................................................................................................65

8.10.3

GPMC Bus........................................................................................................................65

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8.10.4

DSS Bus ............................................................................................................................66

8.10.5

McBSP2 ............................................................................................................................66

8.10.6

McBSP1 ............................................................................................................................66

8.10.7

McBSP3 ............................................................................................................................67

8.10.8

Pin Muxing .......................................................................................................................67

8.10.9

GPIO Mapping .................................................................................................................69

8.10.10

Interrupt Mapping ............................................................................................................69

8.11

POP M EMORY D EVICE ...............................................................................................................70

8.12

S YSTEM C LOCKS .........................................................................................................................70

8.12.1

32KHz Clock.....................................................................................................................71

8.12.2

26MHz Clock ....................................................................................................................71

8.12.3

McBSP_CLKS...................................................................................................................72

8.13

USB OTG P ORT ..........................................................................................................................72

8.13.1

USB OTG Overview..........................................................................................................72

8.13.2

USB OTG Design..............................................................................................................73

8.13.3

OTG ULPI Interface.........................................................................................................73

8.13.4

OTG Charge Pump...........................................................................................................74

8.13.5

OTG USB Connector ........................................................................................................75

8.13.6

OTG USB Protection ........................................................................................................75

8.14

O NBOARD USB HUB..................................................................................................................75

8.14.1

Power................................................................................................................................76

8.14.2

HS USB PHY ....................................................................................................................77

8.14.3

USB HUB..........................................................................................................................79

8.14.4

USB Port Connectors .......................................................................................................81

8.14.5

Ethernet ............................................................................................................................82

8.15

MICRO SD ....................................................................................................................................83

8.15.1

microSD Power.................................................................................................................83

8.15.2

Processor Interface...........................................................................................................83

8.15.3

Card Detect ......................................................................................................................84

8.15.4

Booting From SD/MMC Cards.........................................................................................84

8.16

A UDIO I NTERFACE ......................................................................................................................85

8.16.1

Processor Audio Interface ................................................................................................85

8.16.2

TPS65950 Audio Interface................................................................................................86

8.16.3

Audio Output Jack ............................................................................................................86

8.16.4

Audio Input Jack...............................................................................................................86

8.17

DVI-D I NTERFACE ......................................................................................................................87

8.17.1

Processor LCD Interface..................................................................................................88

8.17.2

LCD Power.......................................................................................................................89

8.17.3

TFP410 Power..................................................................................................................89

8.17.4

TFP410 Framer................................................................................................................89

8.17.5

TFP410 Control Pins........................................................................................................90

8.17.6

DVI-D Connector .............................................................................................................91

8.18

LCD E XPANSION H EADERS ........................................................................................................93

8.19

S-V IDEO ......................................................................................................................................95

8.20

C AMERA P ORT ............................................................................................................................96

8.20.1

Camera Power..................................................................................................................97

8.20.2

Camera I2C Port ..............................................................................................................97

8.20.3

Processor Camera Port Interface.....................................................................................97

8.20.4

Camera Modules.............................................................................................................100

8.21

RS232 P ORT .............................................................................................................................101

8.21.1

Processor Interface.........................................................................................................101

8.21.2

Level Translator .............................................................................................................101

8.21.3

RS232 Transceiver..........................................................................................................102

8.21.4

Connector .......................................................................................................................102

8.22

I NDICATORS ..............................................................................................................................102

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8.22.1

Power Indicator..............................................................................................................103

8.22.2

PMU Status Indicator.....................................................................................................103

8.22.3

User Indicators ...............................................................................................................104

8.22.4

HUB Power Indicator.....................................................................................................104

8.22.5

Overvoltage Indicators ...................................................................................................104

8.23

JTAG........................................................................................................................................105

8.23.1

Processor Interface.........................................................................................................105

8.23.2

JTAG Connector .............................................................................................................106

8.24

M AIN E XPANSION H EADER .......................................................................................................106

8.24.1

Processor Interface.........................................................................................................106

8.24.2

Expansion Signals...........................................................................................................108

8.24.3

Power..............................................................................................................................109

8.24.4

Reset ...............................................................................................................................109

8.24.5

Power Control ................................................................................................................109

8.25

LCD E XPANSION H EADER ........................................................................................................110

8.26

A UXILIARY E XPANSION H EADER ..............................................................................................111

8.26.1

MCBSP5 Signals.............................................................................................................111

8.26.2

MMC3 Signals ................................................................................................................112

8.26.3

ETK Signals ....................................................................................................................112

8.26.4

HSUSB1 Signals .............................................................................................................113

8.26.5

Alternate Clock ...............................................................................................................113

8.26.6

HDQ 1-Wire ...................................................................................................................113

8.26.7

ADC ................................................................................................................................113

8.26.8

GPIO Signals..................................................................................................................114

8.26.9

DMAREQ........................................................................................................................114

8.27

A UDIO E XPANSION H EADER .....................................................................................................114

9.0

CONNECTOR PINOUTS AND CABLES ...............................................................................115

9.1

P OWER C ONNECTOR .................................................................................................................115

9.2

USB OTG.................................................................................................................................116

9.3

S-V IDEO ....................................................................................................................................117

9.4

DVI-D ......................................................................................................................................118

9.5

LCD..........................................................................................................................................120

9.5.1

Connector Pinout ................................................................................................................120

9.5.2

Camera ................................................................................................................................122

9.5.3

Audio McBSP2 Port ............................................................................................................124

9.5.4

Auxiliary Access Header .....................................................................................................125

9.5.5

LCD and Expansion Measurements ....................................................................................126

9.5.6

Mounting Scenarios.............................................................................................................127

9.6

A UDIO C ONNECTIONS ...............................................................................................................128

9.7

A UDIO O UT ...............................................................................................................................129

9.8

JTAG........................................................................................................................................130

9.9

B ATTERY I NSTALLATION ..........................................................................................................132

9.9.1

Battery .................................................................................................................................132

9.9.2

Battery Installation..............................................................................................................132

10.0

BEAGLEBOARD ACCESSORIES ..........................................................................................134

10.1

DC P OWER S UPPLY ...................................................................................................................135

10.2

DVI C ABLES .............................................................................................................................136

10.3

DVI-D M ONITORS ....................................................................................................................136

10.4

MICRO SD C ARDS ......................................................................................................................137

10.5

USB TO W I F I ............................................................................................................................137

10.6

USB TO B LUETOOTH ................................................................................................................138

11.0

MECHANICAL INFORMATION............................................................................................140

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11.1

B EAGLE B OARD D IMENSIONS ....................................................................................................140

11.2

B EAGLE B OARD E XPANSION C ARD D ESIGN I NFORMATION .......................................................141

11.2.1

Mounting Method ...........................................................................................................141

11.2.2

Expansion EEPROM ......................................................................................................143

12.0

BOARD VERIFICATION TEST POINTS ..............................................................................144

12.1.1

Signal Access Points.......................................................................................................146

12.2

T ROUBLESHOOTING G UIDE .......................................................................................................147

13.0

KNOWN ISSUES........................................................................................................................148

14.0

PCB COMPONENT LOCATIONS ..........................................................................................149

15.0

SCHEMATICS............................................................................................................................151

16.0

BILLS OF MATERIAL .............................................................................................................163

17.0

PCB INFORMATION................................................................................................................164

Figures

Figure 1. BeagleBoards C4 and -xM............................................................................ 18

Figure 2. USB Y-Cable ................................................................................................ 21

Figure 3. The -xM Rev A Box ..................................................................................... 28

Figure 4. -xM Rev A Box Contents ............................................................................. 29

Figure 5. USB OTG Connection .................................................................................. 30

Figure 6. USB Host Connection................................................................................... 31

Figure 7. DC Power Connection .................................................................................. 32

Figure 8. BeagleBoard JTAG Connection ................................................................... 33

Figure 9. BeagleBoard Serial Cable Connection.......................................................... 34

Figure 10. BeagleBoard S-Video Connection............................................................ 35

Figure 11. BeagleBoard DVI-D Connection.............................................................. 36

Figure 12. BeagleBoard Audio Out Cable Connection.............................................. 37

Figure 13. BeagleBoard Audio In Cable Connection................................................. 38

Figure 14. BeagleBoard Indicator Locations ............................................................. 39

Figure 15. BeagleBoard Button Location................................................................... 40

Figure 16. BeagleBoard microSD Card Location ...................................................... 41

Figure 17. BeagleBoard LCD Header Location......................................................... 42

Figure 18. BeagleBoard-xM High Level Block Diagram .......................................... 43

Figure 19. BeagleBoard Major Components.............................................................. 44

Figure 20. Overvoltage Protection ............................................................................. 45

Figure 21. Input Power Section.................................................................................. 47

Figure 22. AUX 3.3 Power Section............................................................................ 50

Figure 23. Processor Current Measurement ............................................................... 51

Figure 24. VBAT Power Conditioning ...................................................................... 52

Figure 25. Main Power Rails...................................................................................... 55

Figure 26. Peripheral Voltages................................................................................... 58

Figure 27. Power Sequencing..................................................................................... 61

Figure 28. Reset Circuitry .......................................................................................... 62

Figure 29. AM37x Block Diagram............................................................................. 64

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Figure 30. McBSP2 Interface..................................................................................... 66

Figure 31. McBSP1 Interface..................................................................................... 67

Figure 32. McBSP3 Interface..................................................................................... 67

Figure 33. POP Memory ............................................................................................ 70

Figure 34. System Clocks........................................................................................... 70

Figure 35. USB OTG Design ..................................................................................... 73

Figure 36. USB HUB Block Diagram........................................................................ 76

Figure 37. HUB Power Circuitry ............................................................................... 77

Figure 38. USB PHY Design ..................................................................................... 78

Figure 39. USB HUB Design ..................................................................................... 80

Figure 40. USB Port Power Design............................................................................ 81

Figure 41. USB Based Ethernet Design ..................................................................... 82

Figure 42. microSD Interface..................................................................................... 83

Figure 43. Audio Circuitry ......................................................................................... 85

Figure 44. DVI-D Interface ........................................................................................ 87

Figure 45. S-Video Interface ...................................................................................... 95

Figure 46. Camera Port Interface ............................................................................... 96

Figure 47. Camera Modules ..................................................................................... 100

Figure 48. RS232 Interface Design .......................................................................... 101

Figure 49. Indicator Design...................................................................................... 103

Figure 50. JTAG Interface........................................................................................ 105

Figure 51. Main Expansion Header Processor Connections .................................... 106

Figure 52. Power Connector..................................................................................... 115

Figure 53. USB OTG Connector.............................................................................. 116

Figure 54. OTG Host Shorting Pads ........................................................................ 116

Figure 55. S-Video Connector.................................................................................. 117

Figure 56. DVI-D Connector.................................................................................... 118

Figure 57. DVI-D Cable........................................................................................... 119

Figure 58. DVI-D Cable........................................................................................... 119

Figure 59. LCD Expansion Connector Pins ............................................................. 121

Figure 60. Camera Connector .................................................................................. 123

Figure 61. Camera Module....................................................................................... 123

Figure 62. McBSP Audio Connector ....................................................................... 124

Figure 63. Auxiliary Access Connector ................................................................... 125

Figure 64. Top Mount LCD Adapter........................................................................ 126

Figure 65. Bottom Mount LCD Adapter .................................................................. 127

Figure 66. Audio In Plug.......................................................................................... 128

Figure 67. Audio In Connector................................................................................. 128

Figure 68. Audio Out Plug ....................................................................................... 129

Figure 69. Audio Out Connector.............................................................................. 129

Figure 70. JTAG Connector Pinout.......................................................................... 130

Figure 71. JTAG 14 to 20 Pin Adapter .................................................................... 131

Figure 72. JTAG Connector Pinout.......................................................................... 131

Figure 73. Optional Battery...................................................................................... 132

Figure 74. Optional Battery Location....................................................................... 133

Figure 75. Resistor R65............................................................................................ 133

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Figure 76. DC Power Supply ................................................................................... 135

Figure 77. HDMI to DVI-D Cable .......................................................................... 136

Figure 78. USB to WiFi ........................................................................................... 137

Figure 79. USB to Bluetooth.................................................................................... 138

Figure 80. BeagleBoard Dimension Drawing .......................................................... 140

Figure 81. BeagleBoard Bottom Stacked Daughter Card ....................................... 141

Figure 82. BeagleBoard-xM Expansion Headers..................................................... 142

Figure 83. BeagleBoard Expansion Board EEPROM Schematic ............................ 143

Figure 84. BeagleBoard Voltage Access Points....................................................... 144

Figure 85. BeagleBoard Signal Access Points ......................................................... 146

Figure 86. BeagleBoard Top Side Components....................................................... 149

Figure 87. BeagleBoard Bottom Side Components ................................................. 150

Tables

Table 1. Change History ............................................................................................. 15

Table 2. BeagleBoard-xM Features ............................................................................ 19

Table 3. BeagleBoard Electrical Specification -xM Rev A ........................................ 26

Table 4. Processor Pin Muxing Settings ..................................................................... 68

Table 5. Processor GPIO Pins..................................................................................... 69

Table 6. Processor Interrupt Pins ................................................................................ 69

Table 7. Processor ULPI Interface.............................................................................. 74

Table 8. TPS65950 ULPI Interface............................................................................. 74

Table 9. USB OTG Charge Pump Pins....................................................................... 75

Table 10. USB Host Port OMAP Signals ..................................................................... 78

Table 11. SD/MMC OMAP Signals ............................................................................. 83

Table 12. Processor Audio Signals ............................................................................... 85

Table 13. Processor Audio Signals ............................................................................... 86

Table 14. Processor LCD Signals ................................................................................. 88

Table 15. TFP410 Interface Signals.............................................................................. 89

Table 16. P11 LCD Signals........................................................................................... 93

Table 17. P13 LCD Signals........................................................................................... 94

Table 18. S-Video Interface Signals ............................................................................. 95

Table 19. Camera Interface Signals .............................................................................. 98

Table 20. Camera Pin Signal Mapping ......................................................................... 99

Table 21. JTAG Signals .............................................................................................. 105

Table 22. Expansion Connector Signals ..................................................................... 107

Table 23. Expansion Connector Signal Groups .......................................................... 108

Table 24. P11 GPIO Signals ....................................................................................... 110

Table 25. P13 GPIO Signals ....................................................................................... 110

Table 26. P13 Auxiliary Expansion Signals ............................................................... 111

Table 27. P13 McBSP5 Expansion Signals ................................................................ 111

Table 28. P13 MMC3 Expansion Signals................................................................... 112

Table 29. P13 Auxiliary ETK Signals ........................................................................ 112

Table 30. P13 High Speed USB Expansion Signals ................................................... 113

Table 31. P13 Auxiliary GPIO Signals....................................................................... 114

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Table 32. DVI-D to HDMI Cable ............................................................................... 118

Table 33. P11 LCD Signals......................................................................................... 120

Table 34. P13 LCD Signals......................................................................................... 121

Table 35. P10 Camera Signals .................................................................................... 122

Table 36. P10 McBSP2 Signals .................................................................................. 124

Table 37. P17 Auxiliary Access Signals..................................................................... 125

Table 38. Connector Dimensions................................................................................ 126

Table 39. JTAG Signals .............................................................................................. 130

Table 40. DC Power Supply Specifications................................................................ 135

Table 41. DC Power Supplies ..................................................................................... 135

Table 42. DVI-D Monitors Tested.............................................................................. 136

Table 43. SD/MMC Cards Tested............................................................................... 137

Table 44. USB to WiFi Adapters ................................................................................ 138

Table 45. USB to Bluetooth Adapters ........................................................................ 139

Table 46. Voltages ...................................................................................................... 145

Table 47. Troubleshooting .......................................................................................... 147

Table 48. Known Issues .............................................................................................. 148

NOTES

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1.0 Introduction

This document is the System Reference Manual for the BeagleBoard-xM, a low cost

ARM Cortex A8 board supported through BeagleBoard.org

. This document provides detailed information on the overall design and usage of the BeagleBoard from the system level perspective. It is not intended to provide detailed documentation of the processor or any other component used on the board. It is expected that the user will refer to the appropriate documents for these devices to access detailed information.

The processor used on the BeagleBoard-xM is compatible with several Cortex A8 processors manufactured by Texas Instruments. Currently, the processor is a DM3730 processor, which has yet to be announced by Texas Instruments. The only documentation that is available is the AM3715. The key difference between the AM3715 and the

DM3730, is that the DSP is not included on the AM3715.

For the remainder of this document, it will only be referred to as the processor.

The key sections in this document are:

Section 2.0– Change History

Provides tracking for the changes made to the System Reference Manual.

Section 3.0– Definitions and References

This section provides definitions for commonly used terms and acronyms.

Section 4.0– Overview

This is a high level overview of the BeagleBoard.

Section 5.0– Specification

Provided here are the features and electrical specifications of the BeagleBoard.

Section 6.0-Product Contents

Describes what the BeagleBoard package looks like and what is included in the box.

Section 7.0– Hookup

Covered here is how to connect the various cables to the BeagleBoard.

Section 8.0– System Architecture and Design

This section provides information on the overall architecture and design of the

BeagleBoard. This is a very detailed section that goes into the design of each circuit on the board.

Section 9.0– Connector Pinouts and Cables

The section describes each connector and cable used in the system. This will allow the user to create cables, purchase cables, or to perform debugging as needed.

Section 10.0– BeagleBoard Accessories

Covered in this section are a few of the accessories that may be used with

BeagleBoard. This is not an exhaustive list, but does provide an idea of the types

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Revision A2 of cables and accessories that can be supported and how to find them. It also provides a definition of what they need to be. It does not guarantee that these devices will work on all OS implementations.

Section 11.0 – Mechanical

Information is provided here on the dimensions of the BeagleBoard.

Section 12.0 – Troubleshooting

Here is where you can find tips on troubleshooting the setup of the BeagleBoard.

Section 13.0- Known Issues

This section describes the known issues with the current revision of the

BeagleBoard and any workarounds that may be possible.

Section 14.0- BeagleBoard Components

This section provides information on the top and bottom side silkscreen of the

BeagleBoard showing the location of the components.

Section 15.0- BeagleBoard Schematics

These are the schematics for the BeagleBoard and information on where to get the

PDF and OrCAD files..

Section 16.0- Bill Of Material

This section describes where to get the latest Bill of Material for the BeagleBoard.

Section 17.0- BeagleBoard PCB Information

This section describes where to get the PCB file information for the BeagleBoard.

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2.0 Change History

2.1 Change History

Table 1 tracks the changes made for each revision of this document.

Rev

Table 1. Change History

Changes

Revision A2

Date By

A1 Updated to new power OVP scheme

A2 Updated with camera and Memory information

6/21/2020 GC

7/23/2010 GC

2.2 Revision C4 vs. –xM Revision A2

There are several key differences between the BeagleBoard Revision C4 versus the -xM

Rev A2 version.

2.2.1 Hardware Changes

AREA -xM C4 Comments

ARM Frequency

DSP Frequency

SGX Frequency

1GHZ

800Mhz

200Mhz

720MHz

520MHz

110MHz

DDR Speed 166MHz 166MHz

SD Connector

USB Host Ports

Host Port Speed

Serial Connector

Camera Header

Ships with 4G SD

Overvoltage Protection

Power LED turnoff

Serial Port Power Turnoff

MMC3 Expansion Header

McBSP2 Expansion

Header uSD

4

FS/LS/HS

DB9

MMC/SD

1

HS

Header Direct connect to USB to Serial

Cable

Yes

Yes

Yes

Yes

No

No

No

No

Leopard Imaging Camera module

Contains bootable desktop

Yes

Yes

No

No

Yes No

There will be two different assembly versions of the –xM. These two versions will be shipping at the same time. The long-term plan is to only ship one eventually.

Micron

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Revision A2

Here is a brief explanation for the reason behind this.

We are having yield issues with the current batch of Micron parts. We are hoping that the next batch of production versions will work. However, the dates are continuing to ship so we do not know when we will receive those parts. So, we are starting production with the

Numonyx parts and will continue to build using those parts until such time as the Micron parts are proved to be working, have acceptable yields, and we have steady supply. There are no issues with the -00 assemblies that use the Micron parts. We just cannot afford to scrap all those boards due to poor yields.

All features and capabilities are the same between the two assemblies with the exception that in theory the Micron parts should run at 200MHz.

2.2.2 Software Changes

Following are the changes to the SW. o

Use of a universal Beagle XLoader and UBoot. These will work on any Beagle made. They include support for the 512MB DDR and the removal of the NAND from the –xM board. o

A demo version of the Angstrom desktop distribution.

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3.0 Definitions and References

3.1 Definitions

SD- Secure Digital

microSD- Smal version of the standard SD card

MDDR- Mobile Dual Data Rate

SDRAM- Synchronous Dualrate Random Access Memory

.

Revision A2

4.0 BeagleBoard Overview

The BeagleBoard is designed specifically to address the Open Source Community. It has been equipped with a minimum set of features to allow the user to experience the power of the processor and is not intended as a full development platform as many of the features and interfaces supplied by the processor are not accessible from the

BeagleBoard. By utilizing standard interfaces, the BeagleBoard is highly extensible to add many features and interfaces. It is not intended for use in end products. All of the design information is freely available and can be used as the basis for a product.

BeagleBoards will not be sold for use in any product as this hampers the ability to get the boards to as many community members as possible and to grow the community.

4.1 BeagleBoard Versions

There are two different versions of the beagle in production, the Rev C4 and the –xM.

Figure 1 is a picture of each of these versions. This manual covers the –xm Version only.

Please refer to the Rev C4

The Figure 1 provides an example of a few of the various usage scenarios for the

BeagleBoard.

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Figure 1. BeagleBoards C4 and -xM

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5.0 BeagleBoard Specification

This section covers the specifications of the BeagleBoard and provides a high level description of the major components and interfaces that make up the BeagleBoard.

5.1 BeagleBoard Features

Table 2 provides a list of the BeagleBoard’s features.

Processor

POP Memory

PMIC TPS65950

Debug Support

PCB

Indicators

HS USB 2.0 OTG Port

USB Host Ports

Ethernet

Audio Connectors

SD/MMC Connector

User Interface

Video

Camera

Power Connector

Overvoltage Protection

Main Expansion

Connector

2 LCD Connectors

Auxiliary Audio

Auxiliary Expansion

Table 2. BeagleBoard-xM Features

Feature

Texas Instruments Cortex A8 1GHz processor

Micron 4Gb MDDR SDRAM (512MB) 200MHz

Power Regulators

Audio CODEC

Reset

USB OTG PHY

14-pin JTAG GPIO Pins

3.1” x 3.0” (78.74 x 76.2mm)

Power, Power Error

PMU

6 layers

2-User Controllable

USB Power

Mini AB USB connector

TPS65950 I/F

SMSC LAN9514 Ethernet HUB

4 FS/LS/HS

Up to 500ma per Port if adequate power is supplied

10/100

3.5mm

L+R out

From USB HUB

3.5mm

L+R Stereo In

MicroSD

1-User defined button Reset Button

DVI-D S-Video

Connector Supports Leopard Imaging Module

USB Power

Shutdown @ Over voltage

DC Power

Power (5V & 1.8V) UART

McBSP McSPI

I2C GPIO

MMC2 PWM

Access to all of the LCD control signals plus I2C

4 pin connector

3.3V, 5V, 1.8V

McBSP2

MMC3 MMC3,GPIO,ADC,HDQ

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Revision A2

The following sections provide more detail on each feature and sections of the

BeagleBoard.

5.2 Processor

The BeagleBoard-xM processor is the DM3730CBP 1GHz version and comes in a .4mm pitch POP package. POP (Package on Package) is a technique where the memory is mounted on top of the processor. For this reason, when looking at the BeagleBoard, you will not find an actual part labeled DM3730CBP, but instead see the part number for the memory.

5.3 Memory

There are two possible memory devices used on the –xM. The -00 assembly uses the

Micron POP memory and the -01 uses the Numonyx POP memory. The key function of the POP memory is to provide: o

4Gb MDDR SDRAM x32 (512MB @ 166MHz)

No other memory devices are on the BeagleBoard. It is possible however, that additional non volatile memory storage can be added to BeagleBoard by: o

Accessing the memory on the uSD card o

Use the USB OTG port and a powered USB hub to drive a USB Thumb drive or hard drive. o

Install a thumbdrive into one of the USB ports o

Add a USB to Hard Disk adapter to one of the USB ports

Support for these devices is dependent upon driver support in the OS.

5.4 Power Management

The TPS65950 is used on the BeagleBoard to provide power with the exception of a 3.3V regulator which is used to provide power to the DVI-D encoder and RS232 driver and an additional 3.3V regulator to power the USB Hub. In addition to the power the TPS65950 also provides: o

Stereo Audio Out o

Stereo Audio in o

Power on reset o

USB OTG PHY o

Status LED

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5.5 HS USB 2.0 OTG Port

The USB OTG port can be used as the primary power source and communication link for the BeagleBoard and derives power from the PC over the USB cable. The client port is limited in most cases to 500mA by the PC. A single PC USB port is not sufficient to power the BeagleBoard if the USB Host is enabled. It is configured by the default in the software supplied. The increase in power is due to the addition of the USB HUB on

BeagleBoard.

It is possible to take the current supplied by the USB ports to 1A by using a Y cable.

Figure 2 shows and example of the Y-Cable for the USB.

Figure 2. USB Y-Cable

The BeagleBoard requires a Y-Cable minAB to USB A cable or as mentioned a single cable can be used if the USB Hub is powered down.

There is an option to provide external power to the BeagleBoard using a 5V DC supply and is discussed later in this section.

5.6 HS USB 2.0 Host Port

On the board are four USB Type A connectors with full LS/FS/HS support. Each port can provide power on/off control and up to 500mA of current at 5V as long as the input DC is at least 3A.

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5.7 Stereo Audio Output Connector

A 3.5mm standard stereo output audio jack is provided to access the stereo output of the onboard audio CODEC. The Audio CODEC is provided by the TPS65950.

5.8 Stereo Audio In Connector

A 3.5mm standard stereo audio input jack is provided to access the stereo output of the onboard audio CODEC.

5.9 S-Video Connector

A 4 pin DIN connector is provided to access the S-Video output of the BeagleBoard. This is a separate output from the processor and can contain different video output data from what is found on the DVI-D output if the software is configured to do it.

It will support NTSC or PAL format output to a standard TV. The default is NTSC, but can be changed via the Software.

5.10 DVI-D Connector

The BeagleBoard can drive a LCD panel equipped with a DVI-D digital input. This is the standard LCD panel interface of the processor and will support 24b color output.

DDC2B (Display Data Channel) or EDID (Enhanced Display ID) support over I2C is provided in order to allow for the identification of the LCD monitor type and the required settings.

The BeagleBoard is equipped with a DVI-D interface that uses an HDMI connector that was selected for its small size. It does not support the full HDMI interface and is used to provide the DVI-D interface portion only.

The user must use a HDMI to DVI-D cable or adapter to connect to a LCD monitor. This cable or adapter is not provided with the

BeagleBoard. A standard HDMI cable can be used when connecting to a monitor with an

HDMI connector.

DO NOT PLUG IN THE DVI-D CONNECTOR TO A DISPLAY WITH THE

BEAGLEBAORD POWERED ON. PLUG IN THE CABLE TO THE DISPLAY

AND THEN POWER ON THE BEAGLEBOARD.

5.11 LCD Header

A pair of 1.27mm pitch 2x10 headers are provided to gain access to the LCD signals.

This allows for the creation of LCD boards that will allow adapters to be made to provide the level translation to support different LCD panels.

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5.12 microSD Connector

A single microSD connector is provided as a means for the main non-volatile memory storage on the board. This replaces the 6 in 2 SD/MMC connector found on the C4.

5.13 Reset Button

When pressed and released, causes a power on reset of the BeagleBoard.

5.14 User Button

A button is provided on the BeagleBoard to be used as an application button that can be used by SW as needed. As there is no NAND boot option on the board, this button is no longer needed to force an SD card boot. It is can be used by the UBoot SW to switch between user scripts to allow different boot configurations to be selected as long as that feature is included in the UBoot used..

5.15 Indicators

There are five green LEDs on the BeagleBoard that can be controlled by the user. o

One on the TPS65950 that is programmed via the I2C interface o

Two on the processor controlled via GPIO pins o

One Power LED that indicates that power is applied and can be turned off via SW. o

One to indicate that power is applied to the onboard USB HUB and can be controlled via the SW.

There is also on RED on the BeagleBoard that provides an indication that the connected to the board exceeds the voltage range of the board. If this LED ever turns on, please remove the power connector and look for the correct power supply.

5.16 Power Connector

Power will be supplied via the USB OTG connector and if a need arises for additional power, such as when a board is added to the expansion connectors, a larger wall supply

5V can be plugged into the optional power jack. When the wall supply is plugged in, it will remove the power path from the USB connector and will be the power source for the whole board. The power supply is not provided with the BeagleBoard.

When using the USB OTG port in the host mode, the DC supply must be connected as the USB port will be used to provide limited power to the hub at a maximum of 100mA,

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Revision A2 so a hub must be powered. The 100mA is not impacted by having a higher amperage supply plugged into the DC power jack. The 100mA is a function of the OTG port itself.

Make sure the DC supply is regulated and a clean supply. If the power is over the voltage specification, a RED LED will turn on. This will prevent the power form actually making it to the circuitry on the board and will stay on as long as the power exceeds the voltage specification.

5.17 JTAG Connector

A 14 pin JTAG header is provided on the BeagleBoard to facilitate the SW development and debugging of the board by using various JTAG emulators. The interface is at 1.8V on all signals. Only 1.8V Levels are supported. DO NOT expose the JTAG header to

3.3V.

5.18 RS232 DB9 Connector

Support for RS232 via UART3 is provided by DB9 connector on the BeagleBoard for access to an onboard RS232 transceiver. A USB to Serial cable can be plugged directly into the Beagle. No null modem cable is required. A standard male to female straight

DB9 cable may also be used.

5.19 Main Expansion Header

A single 28 pin header is provided on the board to allow for the connection of various expansion cards that could be developed by the users or other sources. Due to multiplexing, different signals can be provided on each pin. This header is populated on each board.

5.20 Camera Connector

A single connector has been added to the BeagleBoard–xM board for the purpose of supporting a camera module. The camera module does not come with the board but can be obtained from Leopard Imaging. The supported resolutions include VGA, 2MP, 3MP, and 5MP camera modules. For proper operation of the cameras, the correct SW drivers are required. This connector is populated on the board and is ready for the camer module to ne installed.

5.21 MMC3 Expansion Header

New to the BeagleBoard-xM is a 20 pin connector provided to allow access to additional signals including GPIO and the MMC3 port. This connector is populated on the board.

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5.22 McBSP Expansion Header

A 4 pin connector is provided to allow access to the McBSP2 signals for audio applications. In order to use these signals, the audio interface on the TPS65950 must be disabled by the SW. This connector is populated on the board..

5.23 BeagleBoard Mechanical Specifications

Size: 3.35” x 3.45”

Max height: TBM

Layers: 6

PCB thickness: .062”

RoHS Compliant: Yes

Weight: TBW

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5.24 Electrical Specifications

Table 3 is the electrical specification of the external interfaces to the BeagleBoard-xM

Rev A.

Table 3. BeagleBoard Electrical Specification -xM Rev A

Specification

Power

Input Voltage USB

Current USB

Input Voltage DC

Current DC

Max Voltage without damage

Expansion Voltage (5V)

Curent (Dépends on source current avalable)

Expansion Voltage (1.8V)

Min Typ Max

4.8

4.8

1.75

5

350

5

750

5

1

1.8

5.2

5.2

12

5.2

1.85

Unit

V

V

A

V

V mA

V mA

USB Host (Same as the DC supplied by the power plug or USB 5V)

Current (Depends on what the DC source can supply over what the board requires)

USB OTG

High Speed Mode

Full Speed Mode

Low Speed Mode

USB Host

4.8 5 5.2

Varies

480

12.5

1.5

V

Mb/S

Mb/S

Mb/S

High Speed Mode

Full Speed Mode

Low Speed Mode

480

12.5

1.5

Mb/S

Mb/S

Mb/S

RS232

Transmit

High Level Output Voltage

Low Level output voltage

5

-5

5.4

-5.5

V

V

Output impedance

Maximum data rate 250

+/-35 +/-60 mA

Kbit/S

Receive

High level Input Voltage -2.7 -3.2 V

Lo Level Input Voltage

Input resistance 3 5

.4

7 Kohms

JTAG

Realview ICE Tool 30 MHz

Lauterbach(tm)

Voltage Mode 1.8V

Voltage Mode 3.0V microSD

1.71

2.7

1.8

3.0

30

1.89

MHz

V

V

Pixel Clock Frequency

High level output voltage

DVI-D

25

3.3

65 MHz

V

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Swing output voltage

Maximum resolution

S-Video

Full scale output voltage (75ohm load)

Offset voltage

Output Impedance

Peak-to-peak single-ended input voltage (0 dBFs)

Audio In

Total harmonic distortion (sine wave @ 1.02 kHz @ -1 dBFs)

Total harmonic distortion (sine wave @ 1.02 kHz) 2

0 Hz to 20 kHz, A-weighted audio, Gain = 0 dB

Audio Out

Load Impedance @100 pF

Maximum Output Power (At 0.53 Vrms differential output voltage and load impedance = 16 Ohms)

Peak-to-Peak output voltage

Total Harmonic Distortion @ 0 dBFs

Idle channel noise (20Hz to 20KHz)

400

.7

67.5

.88

50

75

-80

Revision A2

600

1024 x 768

1

82.5

1.5

-75 mVp-p

V mV

Ohms

Vpp dB

14 16 ohms

17.56 mW

-80

-90

1.5

-75

-85

Vpp dB dB

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6.0 Product Contents

Under this section is a description of what comes in the box when the BeagleBoard is purchased.

6.1 BeagleBoard In the Box

The final packaged -xM Rev A product will contain the following: o

1 Box o

1 BeagleBoard in an ESD Bag o

1 uSD card o

1 uSD Card to MMC Adapter

NO CABLES ARE PROVIDED WITH THE BEAGLEBOARD.

Figure 3. The -xM Rev A2 Box

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Figure 4. -xM Rev A2 Box Contents

6.2 Software on the BeagleBoard

There is no NAND on the board so no SW is preinstalled on the board as it is on the Rev

C4. The –xM does come with a 4GB SD card that the board boots from. It contains all of the code required for the board to boot to an Angstrom desktop. It can also be used to boot to UBoot by hitting a key during the booting process before it reads the UImage.

6.3 Repairs

If you feel the board is in need of repair, follow the RMA Request process found at http://beagleboard.org/support/rma

Do not send the board in for repair until a RMA authorization has been provided.

Do not return the board t the distributor.

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7.0 BeagleBoard Hookup

This section provides an overview of all of the connectors on the BeagleBoard.

7.1 Connecting USB OTG

The USB OTG port connects to the PC host and uses a miniAB cable through which power can be provided to the BeagleBoard. Figure 5 shows where the cable is connected to the BeagleBoard.

If the OTG Port is to be used as a Host, the ID pin must be grounded. This means that you must have a 5 pin cable connected to the OTG port on the BeagleBoard and you must use a USB powered HUB. There is also an option to ground the ID on the board and is discussed later. You can power the board form this port, but there may not be enough power supplied by the PC to power all features, such as the USB Host ports and the

Ethernet Port. If you use the double ended USB cable, you should be able to power the board with minimal issues as long as you do not load down the USB Host ports with heavy current devices.

Figure 5. USB OTG Connection

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7.2 Connecting USB Host

The Beagle is equipped with 4 USB Host connectors. Figure 6 shows the location of the

USB Host connectors.

Figure 6. USB Host Connection

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7.3 Connecting DC Power

A DC supply can be used to power the BeagleBoard by plugging it into the power jack.

The power supply is not provided with the BeagleBoard, but can be obtained from various sources. You need to make sure the supply is a regulated 5V supply. Figure 7 shows where to insert the power supply into the power jack.

Figure 7. DC Power Connection

The power supply must have a 2.1mm I.D x 5.5mm O.D. x 9.5mm and can be either straight or right angle. Connecting anything other than 5V will activate the over voltage circuitry, turning on a red LED. The board will not function until the correct power supply is used. If you are using the USB OTG port in the OTG or host mode, you must have an external DC supply powering the BeagleBoard.

It is highly recommended that on the -XM Rev A version of the board that an external power supply or double USB cable be used if the USB Host is to be used. Most USB supplies will not be able to supply the required current over a single USB port.

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7.4 Connecting JTAG

A JTAG emulator can be used for advanced debugging by connecting it to the JTAG header on the BeagleBoard. Only the 14pin version of the JTAG is supported and if a

20pin version is needed, you will to contact your emulator supplier for the appropriate adapter. Figure 8 shows the connection of the JTAG cable to the BeagleBoard.

Figure 8. BeagleBoard JTAG Connection

DO NOT expose the JTAG header to 3.3V. It supports 1.8V only.

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7.5 Connecting Serial Cable

In order to access the serial port of the BeagleBoard a serial cable is required. New to the

–xM version is the removal of the 10 pin header and the addition of a female DB9 connector. The configuration of the DB9 is such that a USB to serial adapter can be plugged direct into the Beagle connector. No null modem cable is required. Figure 9 shows where the serial cable is to be installed.

Figure 9. BeagleBoard Serial Cable Connection

If you are using a standard serial port on the PC, a straight through male to female cable is required. The cable used on the Rev C4 will not work on the –xM board.

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7.6 Connecting S-Video

An S-Video cable can be connected to the BeagleBoard and from there it can be connected to a TV or monitor that supports an S-Video input. This cable is not supplied with the BeagleBoard. Figure 10 shows the connector for the S-Video cable.

Figure 10. BeagleBoard S-Video Connection

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7.7 Connecting DVI-D Cable

In order to connect the DVI-D output to a monitor, a HDMI to DVI-D cable is required.

This cable is not supplied with BeagleBoard but can be obtained through numerous sources. Figure 11 shows the proper connection point for the cable.

Figure 11. BeagleBoard DVI-D Connection

DO NOT PLUG IN THE DVI-D CONNECTOR TO A DISPLAY WITH THE BEAGLEBAORD

POWERED ON. PLUG IN THE CABLE TO THE DISPLAY AND THEN POWER ON THE

BEAGLEBOARD.

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7.8 Connecting Stereo Out Cable

An external Audio output device, such as external stereo powered speakers, can be connected to the BeagleBoard via a 3.5mm jack. The audio cables are not provided with

BeagleBoard, but can be obtained from just about anywhere. Figure 12 shows where the cable connected to the stereo out jack.

Figure 12. BeagleBoard Audio Out Cable Connection

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7.9 Connecting Stereo In Cable

External Audio input devices, such as a powered microphone or the audio output of a PC or MP3 player, can be connected to the Beagle via a 3.5mm jack. The audio cables are not provided with BeagleBoard, but can be obtained from several sources. Figure 13 shows where the cable is connected to the stereo input jack.

Figure 13. BeagleBoard Audio In Cable Connection

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7.10 Indicator Locations

There are five green and one RED indicator on the BeagleBoard. Figure 14 shows the location of each indicator. Each indicator will be described in more detail later in this document.

Figure 14. BeagleBoard Indicator Locations

POWER indicates that power is applied to the board.

USR0/1 can be used by the SW as needed

PMU is controlled from the power management chip and can be connected to a PWM.

VOLT will turn on when the DC voltage exceeds specification

HUB turns on when power is applied to the USB HUB.

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7.11 Button Locations

There are two buttons on the BeagleBoard; the RESET button when pressed will force a board reset and the USER button which can be used by the SW for user interaction.

Figure 15 shows the location of the buttons.

Figure 15. BeagleBoard Button Location

The User button does no affect the boot source of the board as is the case on the rev C4 version.

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7.12 microSD Connection

The microSD is the primary boot source for the board. It uses a push-push connector for the insertion and removal of the microSD card. The connector is mounted on the bottom side of the board. Figure 16 shows the location of the microSD connector.

Figure 16. BeagleBoard microSD Card Location

The microSD card should be inserted with the writing on the card facing up. The white silkscreen area on top of the board works as a guide to align the card for insertion.

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7.13 LCD Connection

There are two headers provided to allow access to the LCD signals on the BeagleBoard.

These headers are 2x10 headers with a spacing of .05 (1.27mm) pitch. How these connectors are used is determined by the design of the adapter board that is connected to them. Figure 17 shows the location of the LCD headers on the Beagle.

Figure 17. BeagleBoard LCD Header Location

Adapter boards are becoming available for such things as LCD panels and VGA adapters.

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8.0 BeagleBoard System Architecture and Design

This section provides a high level description of the design of the BeagleBoard-xM and its overall architecture.

8.1 System Block Diagram

Figure 18 is the high level block diagram of the BeagleBoard-xM.

Figure 18. BeagleBoard-xM High Level Block Diagram

Figure 19 shows the location of the key components on the board.

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Figure 19. BeagleBoard Major Components

This remainder of this section describes in detail the architecture and design of the

BeagleBoard.

You will notice certain things in this section. o

The schematic has been created for each section showing only the pertinent components and their connections. o

The pin names differ from the actual schematic. For ease of reading, the names have been truncated to only show the specific functions of that pin as used in the design.

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8.2 Over Voltage Protection

A new feature found on the –xM board is the overvoltage protection circuit. The primary function of this circuit it to prevent voltage levels in excess of the specification from reaching other circuitry on the board and causing damage to the board. Figure 21 is the diagram of the circuitry design.

DC_IN

DC_IN

DC_IN

D13

LTST-C150CKT

VOLT_ERR

R131

22.6K,.1%,0603

R133

DNI,0603

DC5V_LVL

C188

R132

0.1uF,10V R134

8.06K,.1%,0603

DNI,0603

4

DC5V_SNS 5

2

U19

VDD

SENSE RSET

GND NC

TPS3803G15

3

1

R130

10K

2

VOLTERR_LED

510

R121

Q2A

RN1907

5

Q2B

RN1907

DC_IN

P2

2

3

1

CONN_PWR1_2.5MM

5V DC_POWER

R143

32.4K,1%

R1_U32

C214

10uF,CER,1206,25V

4

U32

FDC6331L

VIN

5

ON/OFF

6

R1/C1

VOUT2

VOUT1

R2

3

2

1 R2_U32

R152

DC_5V

C221

330

10uF,CER,1206,25V

R138

10K

VOLTERR

R150

C212

10uF,CER,1206,25V

4

U31

FDC6331L

VIN

5

ON/OFF

6

R1/C1

VOUT2

VOUT1

R2

3

2

1

DC_5V_USB

R2_U31 R144 330

Figure 20. Overvoltage Protection

The circuit is comprised of the following key functions: o

Overvoltage detection o

Overvoltage indication o

Overvoltage shutdown

Each of these functions is discussed in the following sections.

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8.2.1 Detection

The detection is handled by a TPS3803G15 voltage detector which has a fixed-sense threshold voltage of 1.4V set by an internal voltage divider, There is a another version of this devices, the TPS3803−01 has an adjustable SENSE input that can be configured by two external resistors. The design does allow for this, but the resistors are not populated and the TPS3803G15 device is used in the design. RESET is asserted in the case where the VDD drops below the 1.4V level.

In this design we use the device in reverse. If the voltage exceeds 1.4 volts, the RESET is released which results in an error condition. The voltage divider made of R168 and R169 is set to where if the voltage coming in is over 5.3V a level in excess of the 1.4V is presented to the TPS3803G15. If detected, a release of the RESET signal, which is open drain, will result in the signal going high via the pullup R158.

8.2.2 Indication

When the error condition occurs, a red LED, D16, will turn on. This is driven by ½ of

Q3. This indicates to the user that the voltage is too high and that another power supply should be used. The LED will remain on until the overvoltage condition has been removed.

8.2.3 Shutdown

The error condition also results in ½ of Q3 being activated which takes the VOLTERR signal low. This will prevent the two FDC6330L load switches from turning on.

One load switch, U35, removes the power form the main board regulator that provides power to the board, preventing anything from receiving power. Until the overvoltage condition has been resolved, the board will not power up.

The other load switch, U34, removes the power from the DC_5V_USB rail which provides the power to the USB devices. This helps prevent damage to any USB device that may be plugged in at the time of power up. Until the overvoltage condition has been resolved, the board will not power up.

If there is no overvoltage condition or if the previous one has been removed, the pullup,

R160, will turn on the two load switches connecting the power. Each of these switches can handle in excess of 2A in normal operation.

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8.3 Power Conditioning

There are two possible sources of the 5V required by the BeagleBoard. It can come from the USB OTG port connected to a PC or a 5V DC supply. The USB supply is sufficient to power the BeagleBoard in some cases if the SW does not activate the USB HUB. If the

USB HUB is needed, then a minimum of two PC USB ports are required t supply the power. However, depending on the load needed by the expansion port on BeagleBoard and the usage of the USB Host ports, additional power most likely will be required even in this scenario. This is where the DC supply comes in to play.

It should also be noted that if an OTG configuration is used, for example tying two

BeagleBoards together via a UBS OTG cable, both of the BeagleBoards must be powered by the DC supply. If the OTG port is used as a Host port, then the DC supply must also be used.

Figure 21 is the design of the power input section.

USB_CLIENT /

OTG PORT

P1

1

2

3

4

5

VB

D-

D+

ID

G1 mini USB-AB

5V

P2

2

3

1

CONN_PWR1_2.5MM

DC_POWER

4

6

LDO_EN

3

2

5

U2

LDO_IN

SW_IN

SW_IN

SW_EN

TPS2141PWP

LDO_PLDN

LDO_OUT

ADJ

LDO_PG

9

8

10

11

SW_OUT

SW_OUT

SW_PLDN

SW_PG

13

12

14

1

R153 32.4K,1% R1_U32

4

C214

10uF,CER,1206,25V

U32

FDC6331L

VIN VOUT2

3

5

ON/OFF VOUT1

2

6

R1/C1 R2

1 R152 330

DC_5V

10uF,CER,1206,25V

C6

Figure 21. Input Power Section

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8.3.1 USB DC Source

The USB specification requires that the current consumed prior to enumeration be limited to 100mA @ 5V (500mW). The 5V DC from the USB is routed through the TPS2141 switch to insure that this requirement is met as uncharged capacitors on the BeagleBoard can exhibit a large current drain during start up that could exceed this requirement. The

TPS2141 is a USB 2.0 Specification-compatible IC containing a dual-current limiting power switch and an adjustable low dropout regulator (LDO). Both the switch and LDO limit inrush current by controlling the turn on slew rate. The dual-current-limiting feature of the switch allows USB peripherals to utilize high-value capacitance at the output of the switch, while keeping the inrush current low.

During turn on, the switch limits the current delivered to the capacitive load to less than

100 mA. When the output voltage from the switch reaches about 93% of the input voltage, the switch current limit increases to 800mA (minimum), at which point higher current loads can be turned on. The higher current limit provides short circuit protection while allowing the peripheral to draw maximum current from the USB bus.

When in the USB powered mode and no DC supply is connected, the TPS2141 is enabled, allowing the power to be supplied to the board from the OTG port through the integrated switch inside the TPS2141.

8.3.2 Wall Supply Source

A wall supply can be used to provide power to the board. A regulated 5V DC supply of at least 1A is required and a rating of 3A is preferred, assuming that the USB ports and expansion headers are likely to be used. It needs to have a 2.1mm plug with a center hot configuration. If you are using the USB HUB or Ethernet interface, additional current is required. In the event that a higher DC load is required due to the addition of a

Daughtercard or if all the USB host ports need to supply the full 500mA per port, a higher current supply can be used. The maximum current should not exceed 3A.

8.3.3 DC Source Control

Unlike when powering from the USB OTG port, in the case of the DC voltage, the current limiting is not required. As long as the DC supply is not connected, the switch for the USB is enabled. When the DC supply is plugged in, the switch is disabled because the ground is removed from pin 5 of the TPS2141. This insures that the 5V from the USB is not connected by disabling the internal FET. In the case where there is no USB plugged in, there is no 5V available to be routed so the removal of the pullup in pin 5 has no affect.

When in the DC mode of operation, the USB OTG can be used in the Host or Client modes. The TPS65950 will be responsible for handling the supply of the VBUS_5V0 rail

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Revision A2 in the OTG or Host modes. As this is limited to 100mA, a powered hub must be used to support peripherals on the OTG port.

It is possible to provide 5V via the expansion connectors as would be the case from a daughter card to prevent you from having to have two DC supplies. You should be careful in doing this. If you plan to use the USB OTG port, you will need to place an unconnected connector into the DC power jack to insure that the DC from the OTG port is not shorted to the 5V supplied via the expansion connector. There is a signal called

nUSB_POWER which if Hi (5V) indicates that there is 5V supplied by the USB OTG port, it is plugged in, and the DC dummy jack is installed. This condition could be used on the daughtercard to know that it is OK to supply power onto the expansion bus to power the board. If this signal is low, then that indicates that there is no DC power connected and there is no USB OTG port connected. For this reason, is recommended however, that a large pullup be provided on the daughtercard to make the signal HI (5V) to detect the true state of the DC jack. It is always possible that at any point a USBOTG cable could be installed. This means that in order to power the board from the expansion headers, the DC dummy jack must be installed and there is a method to verify that condition.

8.3.4 AUX 3.3V Supply

The TPS2141 has an integrated 3.3V LDO which is being used to supply the 3.3V as required on the BeagleBoard for the DVI-D interface and the UART. The input to the

LDO is supplied by the main DC_5V. This insures that the power to the LDO can be supplied by either the USB or the DC wall supply and that the current measurement includes the 3.3V supply. The 3.3V supply can be turned off by activating GPIO1 on the

TPS65950 to a 1. By default the voltage is on. You will also see that the 3.3V supply powers the power LED, D5. If during a low power mode, the user chooses to turn of the power LED, this GPIO pin can be used to turn off the power LED. It should also be noted, that the 3.3V rail controls the serial port power, so this will be powered down as well. Figure 22 is the AUX 3.3V Supply design.

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VIO_1V8

C204

0.1uF,10V

1

U18A

SN74LVC2G06DCKR

6

BeagleBoard-xM System

Reference Manual

Revision A2

R8

10K

VBAT

AUX_3V3

4

6

LDO_EN

3

2

5

U2

LDO_IN

SW_IN

SW_IN

SW_EN

TPS2141PWP

LDO_PLDN

LDO_OUT

ADJ

LDO_PG

10

11

9

8

SW_OUT

SW_OUT

SW_PLDN

SW_PG

13

12

14

1

R9

620K,1%,0603

3V3_ADJ

R10

C207 D5

LTST-C190GKT

4.7uF,6.3V,0603

POWER

R12

200K,1%,0603

330

U7A TPS65950

GPIO.1/CD2/JTAG.TMS

N12

R54

10K

Figure 22. AUX 3.3 Power Section

8.4 Meter Current Measurement

Jumper J2 is a header that allows for the voltage drop across the resistor to be measured using a meter, providing a way to measure the current consumption of the BeagleBoard from the main voltage rails, either USB or DC. The resistor, R13, is a .1 ohm resistor across which the voltage is measured. The reading you get is .1mV per mA of current.

You will need to make sure you have a sensitive meter to make your measurements.

Please keep in mind, that this current reading does not include any current consumed by the USB HUB, USB ports, or the Expansion headers.

8.5 Processor Current Measurement

The resistor across J2 can also be used to measure the current of the board by reading the voltage drop across R13 from software. There are two pairs of resistors provided on the

TPS65950 that measure the voltage on either side of R13. This is done via the I2C control bus to the TPS65950 from the processor. These values along with resistance of

R13 are used to calculate the current consumption of the board. Figure 24 is the schematic of the measurement circuitry. The maximum value that can be input to the

ADC inputs is based on the setting of the VINTANA2.OUT voltage rail which defaults

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DC_5V

2

1

3

U3

IN OUT

SHDN GND

GND ADJ

TL1963A

4

6

5

4.2V

VBAT_MAIN

VBAT_FB R14

56.2K,1%

R15

22.6K,1%

1

J2

+

2

HDR2_.1x.1

R13 .1,0805

VBAT

C5

C7

0.1uF,10V

10uF,CER,0805,6.3V

R48

12K,1%

C83 0.1uF,10V

R49

12K,1%

C84 0.1uF,10V

R53 10K,1% U7A TPS65950

RTSO/CLK64K/BERCLK/ADCIN5

CTSI/BERDATA/ADCIN3

N11

P11

ADCIN5

R52

ADCIN3

10K,1%

Figure 23. Processor Current Measurement

This results in a value that is 46% of the actual value. So, for a maximum value of 5.25V, the voltage read would be 2.415V which keeps it below the 2.5V point. The voltage drop across R13 will be small as the value of the resistor is 0.1 ohms. For every 100 mA of current a voltage of .01V will be detected. In order to determine the actual power, the input voltage and the voltage drop must be measured.

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8.6 VBAT Power Conditioning

This circuitry regulates the DC input to a nominal 4.2VDC level. This is required in order to meet the maximum DC voltage level as specified by the TPS65950 Power

Management device which is 4.7V. Using 4.2V gives us some margin and meets the nominal 4.2V rating of the TPS65950.

Figure 25 is the power conditioning section of the BeagleBoard.

DC_5V

2

1

3

U3

IN OUT

SHDN GND

GND ADJ

TL1963A

4

6

5

VBAT_MAIN

4.2V

VBAT_FB R14

56.2K,1%

R15

22.6K,1%

VBAT

J2

1 + 2

HDR2_.1x.1

R13 .1,0805 C5

10uF,CER,0805,6.3V

C7

0.1uF,10V

Figure 24. VBAT Power Conditioning

The TPS65950 provides the main power rails to the board and has a maximum limit of

4.7V on its VBAT input and a nominal of 4.2V. U3, the TL1963A, is used to convert the

DC_5V, which can come from a DC wall supply or the USB, to 4.2V to meet this requirement. The TL1963A is a linear low-dropout (LDO) voltage regulator and is thermal shutdown and current limit protected. It has the ability to deliver 1A of current, although this is far and above the requirements of the board. By adjusting the values of

R14 and R15, the actual voltage can be adjusted if needed.

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8.7 TPS65950 Reset and Power Management

The TPS65950 supplies several key functions on the BeagleBoard. This section covers a portion of those functions centered on the power and reset functions. Included in this section are: o

Main Core Voltages o

Peripheral Voltages o

Power Sequencing o

Reset o

Current measurement via SW

The other functions are covered in other sections in this document and are grouped by their overall board functions. The explanation of the various regulators found on the

TPS65950 is based upon how they are used in the board design and are not intended to reflect the overall capability of the TPS65950 device. Please refer to the TPS65950 documents for a full explanation of the device operation.

8.7.1 Main Core Voltages

The TPS65950 supplies the three main voltage rails for the processor and the board: o

VOCORE_1V3 (1.2V, adjustable) o

VDD2 (1.3V) o

VIO_1V8 (1.8V)

The VOCORE_1V3 defaults to 1.2V at power up, but can be adjusted by software to the

1.3V level. Figure 26 is the interfacing of the TPS65950 to the system as it provides the three main rails.

8.7.2 Main DC Input

The main supply to the TPS65950 for the main rails is the VBAT rail which is a nominal

4.2V. Each rail has a filter cap of 10uF connected to each of the three inputs. A .1uF cap is also provided for high frequency noise filtering.

8.7.3 Processor I2C Control

The various components in the TPS65950 are controlled from the processor via the I2C interface. I2C_0 is used to control the TPS65950 device.

8.7.4 VIO_1V8

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The VIO_1V8 rail is generated by the TPS65950 VIO regulator. The VIO output is a stepdown converter with a choice of two output voltage settings: 1.8 V or 1.85 V. The voltage is set by configuring the VSEL bit (VIO_VSEL[0]). When the VSEL bit is set to

0, the output voltage is 1.8 V, and when it is set to 1, the output voltage is 1.85 V.

When the TPS65950 resets, the default value of this LDO is 1.80 V; the processor must write 1 to the VSEL field to change the output to 1.85 V. The default for the BeagleBoard is 1.8V. This regulator output is used to supply power to the system memories and I/O ports. It is one of the first power supplies to be switched on in the power-up sequence.

VIO does not support the SmartReflex voltage control schemes. VIO can be put into sleep or off mode by configuring the SLEEP_STATE and OFF_STATE fields of the

VIO_REMAP register.

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VBAT U7B TPS65950

R1

10K

Power control

8

4

4

4

REGEN

I2C4_SCL

I2C4_SDA

VBAT nSLEEP

C106

2.2uF,6.3V

A10

REGEN

VBAT

F8

D6

B14

C4

P7

G9

VMODE1(VDD1)

VMODE2(VDD2)/I2C.SR.SCL

N.C.

N.C./I2C.SR.SDA

nSLEEP1 nSLEEP2

IO_1P8

CP.CAPP

R7

T7

CP.IN

CP.CAPP

CP.CAPM

T6

R6

CP.CAPM

CP.GND

USB CP

VBAT

VDD1

L4

C110

C112

0.1uF,10V

1 2

1uH,2A,LM3015

T2_VDD1.L

C111

10uF,CER,0805,6.3V

10uF,CER,0805,6.3V

VBAT

D14

E14

E15

E13

C14

D15

D16

VDD1.IN

VDD1.IN

VDD1.IN

VDD1.OUT

VDD1.L

VDD1.L

VDD1.L

B15

C15

C16

VDD1.GND

VDD1.GND

VDD1.GND

VDD1

VDD2

VDD2

L5

0.1uF,10V 1

C117 C118

10uF,CER,0805,6.3V

2

1uH,LM3010

T2_VDD2.L

C119

10uF,CER,0805,6.3V

R13

P14

N13

T13

R14

T14

R15

VDD2.IN

VDD2.IN

VDD2.FB

VDD2.L

VDD2.L

VDD2.GND

VDD2.GND

VBAT

VIO_1V8

L6

1 2 T2_VIO.L

C136

C138

10uF,CER,0805,6.3V

0.1uF,10V

1uH,2A,LM3015

C132

10uF,CER,0805,6.3V

P3

R4

N3

R3

T4

R2

T3

VIO.IN

VIO.IN

VIO.OUT

VIO.L

VIO.L

VIO.GND

VIO.GND

VIO

Revision A2

MEM_1V8

0.1uF,10V

C139 C140 C189

Figure 25. Main Power Rails

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8.7.5 Main Core Voltages Smart Reflex

VDD1 and VDD2 regulators on the TPS65950 provide SmartReflex-compliant voltage management. The SmartReflex controller in the processor interfaces with the TPS65950 counterpart through the use of a dedicated I2C bus. The processor computes the required voltage and informs the TPS65950 using the SmartReflex I2C interface.

SmartReflex control of the VDD1 and VDD2 regulators can be enabled by setting the

SMARTREFLEX_ENABLE bit (DCDC_GLOBAL_CFG[3]) to 1. To perform VDD1 voltage control through the SmartReflex interface, the TPS65950 provides the

VDD1_SR_CONTROL register. The MODE field of the VDD1_SR_CONTROL register can be set to 0 to put VDD1 in an ACTIVE state; setting the field to 1 moves VDD1 to a

SLEEP state. VDD1 output voltage can be programmed by setting the VSEL field of the

VDD1_SR_ CONTROL register. The VDD1 output voltage is given by VSEL*12.5 mV

+ 600 mV.

8.7.6 VOCORE_1V3

The VOCORE_1V3 rail is supplied by the VDD1 regulator of the TPS65950. The

VDD1 regulator is a 1.1A stepdown power converter with configurable output voltage between 0.6 V and 1.45 V in steps of 12.5 mV. This regulator is used to power the

AM3730 core.

The AM3730 can request the TPS65950 to scale the VDD1 output voltage to reduce power consumption. The default output voltage at power-up depends on the boot mode settings, which in the case of the BeagleBoard is 1.2V. The output voltage of the VDD1 regulator can be scaled by software or hardware by setting the ENABLE_VMODE bit

(VDD1_VMODE_CFG[0]). In each of these modes, the output voltage ramp can be single-step or multiple-step, depending on the value of the STEP_REG field of the

VDD1_STEP[4:0] register. The VOCORE_1V3 rail should be set to 1.3V after boot up.

Apart from these modes, the VDD1 output voltage can also be controlled by the AM3730 through the SmartReflex I2C interface between the AM3730 and the TPS65950. The default voltage scaling method selected at reset is a software-controlled mode. Regardless of the mode used, VDD1 can be configured to the same output voltage in sleep mode as in active mode by programming the DCDC_SLP bit of the VDD1_VMODE_CFG[2] register to 0. When the DCDC_SLP bit is 1, the sleep mode output voltage of VDD1 equals the floor voltage that corresponds to the VFLOOR field (VDD1_VFLOOR[6:0]).

8.7.7 VDD2

The VDD2 voltage rail is generated by the TPS65950 using the VDD2 regulator. The

VDD2 regulator is a stepdown converter with a configurable output voltage of between

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0.6 V and 1.45 V and is used to power the processor core. VDD2 differs from VDD1 in its current load capabilities with an output current rating of 600 mA in active mode.

The VDD2 provides different voltage regulation schemes. When VDD2 is controlled by the VMODE2 signal or with the SmartReflex interface, the range of output voltage is 0.6

V to 1.45 V. The use of the VMODE2 signal and the VDD2_VMODE_CFG,

VDD2_STEP, VDD2_FLOOR, and VDD2_ROOF registers is similar to the use of the corresponding signals and registers for VDD1. VDD2 shares the same SmartReflex I2C bus to provide voltage regulation. The VDD2_SR_CONTROL register is provided for controlling the VDD2 output voltage in SmartReflex mode.

When the VDD2 is used in software-control mode, the VSEL (VDD2_

DEDICATED[4:0]) field can be programmed to provide output voltages of between 0.6

V and 1.45 V. The output voltage for a given value of the VSEL field is given by

VSEL*12.5 mV + 600 mV. If the VSEL field is programmed so that the output voltage computes to more than 1.45 V, the TPS65950 sets the VDD2 output voltage to 1.5 V.

8.8 Peripheral Voltages

There are 10 additional voltages used by the system that are generated by the TPS65950.

These are: o

VDD_PLL2 o

VDD_PLL1 o

VDAC_1V8 o

VDD_SIM o

VMMC2 o

VDD_VMMC1 o

CAM_2V8 o

CAM_1V8 o

USB_1V8 o

EXP_VDD

Figure 27 shows the peripheral voltages supplied by the TPS65950.

8.8.1 VDD_PLL2

This programmable LDO is used to power the processor PLL circuitry. The VPLL2 LDO can be configured through the I2C interface to provide output voltage levels of 1.0 V, 1.2

V, 1.3 V, or 1.8 V, based on the value of the VSEL field (VPLLI_DEDICATED[3:0]).

On the board this rail is used to power DVI output for pins DSS_DATA(0:5),

DSS_DATA(10:15) and DSS_DATA(22:23). The VPLL2 must be set to 1.8V for proper operation of the DVI-D interface.

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8.8.2 VDD_PLL1

The VPLL1 programmable LDO regulator is low-noise, linear regulator used for the processor PLL supply. The VDD_PLL1 rail is initialized to 1.8V.

U7B TPS65950

N5

VAC

BCI

ICTLAC1

ICTLAC2

ICTLUSB1

ICTLUSB2

VPRECH

N7

P2

P6

P1

N2 T2_VPRECH

PCHGAC

PCHGUSB

VCCS

VBATS

VBAT

N4

N6

P5

P4

R5

VBAT C104

0.1uF,10V

N1

BCIAUTO

R65

M14 BKBAT 0,0603

Backup battery

BKBAT

VIO_1V8

IO Level C107 0.1uF,10V

VIO_1P8

BT1

IO_1P8

IO.1P8

C8

VBAT.RIGHT

VBAT.RIGHT

VBAT.LEFT

VBAT.LEFT

D11

D12

D9

D10

C108

1uF,10V

C109

1uF,10V

VBAT

BAT_LI_RTC

VMMC2.IN

VMMC1.IN

VAUX4.IN

VBAT.USB

VDAC.IN

VAUX12S

VPLLA3R

VINT

A3

C1

B2

R9

K1

L1

H15

K15

C113

1uF,10V

C114

1uF,10V

C115

1uF,10V

C116

1uF,10V

VPLL2

VPLL1

VDAC.OUT

VSIM

VMMC2.OUT

VMMC1.OUT

VAUX4.OUT

VAUX3.OUT

VAUX2.OUT

VAUX1.OUT

J15

H14

L2

K2

A4

C2

B3

G16

M3

M2

VDD_PLL2

VDD_PLL1

VDAC_1V8

VDD_SIM

VMMC2

VDD_MMC1

CAM_2V8

CAM_1V8

USB_1V8

EXP_VDD (1.85V-3V)

C120

1uF,10V

C121

1uF,10V

C122

2.2uF,6.3V

C123

1uF,10V

C124

1uF,10V

C125

1uF,10V

C126

1uF,10V

C127

1uF,10V

C213

1uF,10V

C128

10uF,CER,0805,6.3V

Figure 26. Peripheral Voltages

8.8.3 VDAC_1V8

The VDAC programmable LDO regulator is a high-PSRR, low-noise, linear regulator that powers the AM3730 dual-video DAC. It is controllable with registers via I2C and can be powered down if needed. The VDAC LDO can be configured to provide 1.2V, 1.3

V, or 1.8 V in on power mode, based on the value of the VSEL field

(VDAC_DEDICATED[3:0]). The VDAC_1V8 rail should be set to 1.8V for the

BeagleBoard.

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8.8.4 VDD_SIM

This voltage regulator is a programmable, low dropout, linear voltage regulator supplying the bottom 4 bits of the 8 bit SD/MMC card slot. The VSEL field

(VSIM_DEDICATED[3:0]) can be programmed to provide output voltage of 1.0 V, 1.2

V, 1.3 V, 1.8 V, 2.8 V, or 3.0 V and can deliver up to 50mA. The default output voltage of this LDO as directed by the TPS65950 boot pins is 1.8V.

8.8.5 VMMC2

The VMMC2 rail uses the VMMC2.OUT rail from the TP65950. VMMC2 is adjustable from 1.85 to 3.15V and can deliver up to 100mA of current. VMMC2 is provided as an auxiliary voltage rail on P17, the Auxiliary Access Header. The proper setting of this rail is determined by the application and the HW supplied that connects to P17.

8.8.6 VDD_VMMC1

The VMMC1 LDO regulator is a programmable linear voltage converter that powers the

MMC1 slot and includes a discharge resistor and overcurrent protection (short-circuit).

This LDO regulator can also be turned off automatically when the MMC card extraction is detected. The VMMC1 LDO is powered from the main VBAT rail. The VMMC1 rail defaults to 3.0V as directed by the TPS65950 boot pins and will deliver up to 220mA. It can be set to 3.0V in the event 3V cards are being used.

8.8.7 CAM_2V8

This rail powers the optional camera module and uses the VAUX4.OUT rail from the

TPS65950. VAUX4 is adjustable from .7 to 2.8V and can deliver up to 200mA of power.

This railed should be set to 1.8V for proper operation of the camera module. See the camera module section for more information.

8.8.8 CAM_1V8

This rail powers the optional camera module and uses the VAUX3.OUT rail form the

TPS65950. VAUX4 is adjustable form 1.5 to 2.8V and can deliver up to 100mA of power. This railed should be set to 1.8V for proper operation of the camera module. See the camera module section for more information.

8.8.9 USB_1V8

The VAUX2 LDO regulator is a programmable linear voltage converter that powers the

1.8V I/O rail of the USB PHY and includes a discharge resistor and overcurrent

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Revision A2 protection (short-circuit). The VAUX2 LDO is powered from the main VBAT rail. The

VMMC1 rail defaults to 3.0V as directed by the TPS65950 boot pins and will deliver up to 220mA. The voltage rail is labeled VDD_EHCI on the schematic.

8.8.10 EXP_VDD

The EXP_VDD rail uses the VAUX1.OUT rail from the TP65950. EXP_VDD is adjustable from 2.5 to 3.0V and can deliver up to 200mA of current. EXP_VDD is provided as an auxiliary voltage rail on P13, the LCD Expansion Header. The proper setting of this rail is determined by the application and the HW supplied that connects to

P13.

8.9 Other Signals

This section describes other signals in the design that have not been categorized.

8.9.1 Boot Configuration

The boot configuration pins on the TPS65950 determine the power sequence of the device. For the AM3730 support, the boot pin configuration is fixed at: o

BOOT0 tied to VBAT o

BOOT1 tied to Ground.

8.9.2 RTC Backup Battery

An optional battery to backup for the Real Time Clock that is in the TPS65950 is provided for in the design. The board does not come equipped with the battery. The battery can be purchased from DigiKey or other component suppliers. When the battery is not installed, R66 must be installed. You must make sure that prior to installing the battery that R66 is removed.

Refer to section 9.11 for information on the battery selection and installation.

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8.9.3 Power Sequencing

Based on the boot configuration pins, the TPS65950 knows the type of OMAP processor that it needs to support, in this case the processor. The voltages are ramped in a sequence that is compatible with the processor. Figure 27 is the sequence in which the power rails, clocks, and reset signal come up.

Figure 27. Power Sequencing

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8.9.4 Reset Signals

The BeagleBoard uses three distinct reset circuits: o

Warm Reset o

Cold Reset o

User Reset

Figure 28 shows the connections for the Reset interfaces.

U7A

AM3730

T

R61 P

4.7K

VIO_1V8 AH25

AF24

Revision A2

U4B

SYS_nRESPWRON

SYS_nRESWARM/GPIO_30

S

6

IO_1P8

5

VBAT

9

5 nRESPWRON nRESWARM

PWRON

A13

B13

A11 nRESPWRON nRESWARM

PWRON

4.7K

R59

VBAT

VIO_1V8

R53

DNI

C12

VIO_1V8

PROCESSOR nRESET

18

20

22

24

26

28

10

12

14

16

6

8

2

4

P9

0

1

0.1uF

5

U5A

6

R42

10K

SN74LVC2G07DCKR

4

3

S2

B3F-1000

2

1

17

19

21

23

25

27

9

11

13

15

5

7

1

3

2

Figure 28. Reset Circuitry

8.9.4.1 Warm Reset

The warm reset is generated by the processor on power up. The nRESWARM signal is a bidirectional reset. When an internal reset occurs, nRESWARM goes low and resets all the peripherals and the TPS65950. The TPS65950 can be configured to perform a warm reset of the device to bring it into a known defined state by detecting a request for a warm reset on the NRESWARM pin. The minimum duration of the pulse on the nRESWARM pin should be two 32-kHz clock cycles. The nRESWARM output is open-drain; consequently, an external pullup resistor is required. There is no way for the user to generate a warm reset on the BeagleBoard.

8.9.4.2 Cold Reset

On power up as shown in Figure 27, the TPS65950 generates nRESPWRON, power on reset. The signal from the TPS65950 is an output only and is not an open drain signal.

By running the signal through a buffer, SN74LVC2G07, the signal becomes open drain, which requires a pullup on the signal. This will allow the nRESPWRON signal to be

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Revision A2 pulled low, by pressing the reset switch S2, to force a reset to the AM3730 processor and to any device on the expansion card that require a reset.

It also allows for the reset signal to be pulled low or held low for an extended time by circuitry on the expansion card if needed.

8.9.4.3 User Reset

The USER RESET button can be used to request a Warm Reset from the processor. After initialization, this pin becomes an input to the processor. By pushing the Reset button, an interrupt is generated into the processor. The software that is run as a result of this can then do whatever housekeeping is required and then send the processor into a reset mode.

8.9.4.4 PWRON

You will notice another signal on the TPS65950 called PWRON. This signal is referenced in the TPS65950 documentation. In the BeagleBoard design it is not used but it is pulled high to insure the desired operation is maintained.

8.9.5 mSecure Signal

This signal provides for protection of the RTC registers in the TPS65950 be disabling that function via a control signal from the processor.

For more information on the operation on the signal, please refer to the processor

Technical Reference Manual.

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8.10 Processor

The heart of BeagleBoard is the DM3730 processor. Figure 29 is a high level block diagram of the processor.

Figure 29. AM37x Block Diagram

8.10.1 Overview

The DM3730 high-performance, multimedia application device and is integrated on TI's advanced 45-nm process technology. The processor architecture is configured with different sets of features in different tier devices. Some features are not available in the lower-tier devices. For more information, refer to the Technical Reference Manual

(TRM).The architecture is designed to provide best-in-class video, image, and graphics processing sufficient to various applications.

The processor supports high-level operating systems (OSs), such as: o

Windows CE o

Linux

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Revision A2 o

QNX o

Symbian o

Others

This processor device includes state-of-the-art power-management techniques required for high-performance low power products. The DM3730 supports the following functions and interfaces on the BeagleBoard: o

Microprocessor unit (MPU) subsystem based on the ARM Cortex-A8™ microprocessor o

POP Memory interface o

4Gb MDDR (512Mbytes) o

24 Bit RGB Display interface (DSS) o

SD/MMC interface o

USB OTG interface o

NTSC/PAL/S-Video output o

Power management o

Serial interface o

I o

I

2

2

C interface

S Audio interface (McBSP2) o

Expansion McBSP1 o

JTAG debugging interface

8.10.2 SDRAM Bus

The SDRAM bus is not accessible on the BeagleBoard. Its connectivity is limited to the

POP memory access on the top of the processor and therefore is only accessible by the

SDRAM memory. The base address for the DDR SDRAM in the POP device is 0x8000

0000.

If you look at the –xM schematic, you will notice on page 3 there are a lot of signals labeled NA0…65. These pins are located on the bottom of the processor. In the Rev C4 processor, these pins provided access to the SDRAM bus. However, in the case of the processor on the –xM, these there are no signals on these pins.

8.10.3 GPMC Bus

The GPMC bus is not accessible on the BeagleBoard. Its connectivity is limited to the

POP memory access on the top of the processor and therefore is only accessible by the

NAND memory.

The memory on the GPMC bus is NAND and therefore will support the classical NAND interface. The address of the memory space is programmable.

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8.10.4 DSS Bus

The display subsystem provides the logic to display a video frame from the memory frame buffer in SDRAM onto a liquid-crystal display (LCD) display via the DVI-D interface or to a standalone LCD panel via the LCD interface connectors. The logic levels of the LCD expansion connectors are 1.8V so it will require buffering of the signals to drive most LCD panels. The DSS is configured to a maximum of 24 bits, but can be used in lower bit modes if needed.

8.10.5 McBSP2

The multi-channel buffered serial port (McBSP) McBSP2 provides a full-duplex direct serial interface between the processor and the audio CODEC in the TPS65950 using the

I2S format. Only four signals are supported on the McBSP2 port. Figure 30 is a depiction of McBSP2.

Processor

Figure 30. McBSP2 Interface

8.10.6 McBSP1

McBSP1 provides a full-duplex direct serial interface between the processor and the expansion interface. There are 6 signals supported on McBSP1, unlike the 4 signals on the other ports. Figure 31 is a diagram of McBSP1.

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Processor

Figure 31. McBSP1 Interface

8.10.7 McBSP3

McBSP3 provides a full-duplex direct serial interface between the processor and the expansion interface. Figure 32 is a diagram of McBSP3.

Processor

Figure 32. McBSP3 Interface

8.10.8 Pin Muxing

On the processor, the majority of pins have multiple configurations that the pin can be set to. In essence, the pin can become different signals depending on how they are set in the software. In order for the BeagleBoard to operate, the pins used must be set to the correct signal. In some cases, the default signal is the correct signal. Each pin can have a maximum of 8 options on the pin. This is called the pin mode and is indicated by a three

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Revision A2 bit value (0:3). In the case of the signals going to the expansion connector, the settings required for those pins depends on how they are to be used. For an explanation of the options, please refer to the Expansion Header section. Each pin can be set to a different mode independent of the other pins on the connector.

Table 4 is a list of all of the signals used on the processor for the BeagleBoard and the required mode setting for each pin. Where the default setting is needed, it will be indicated. The USER notation under mode indicates that this is an expansion signal and can be set at the discretion of the user. A FIXED indicates that there is only one function for that signal and that it cannot be changed,

Table 4. Processor Pin Muxing Settings

Signal Mode

DSS Default

MMC1 Default

MMC2 User

UART3 Default

GPMC Default

UART1 Default

I2C1 Default

I2C2 Default

I2C3 Default

I2C4 Default

JTAG FIXED

TV_OUT Default

SYS_nRESPWRON Default

SYS_nRESWARM Default

SYS_nIRQ Default

SYS_OFF Default

SYS_CLKOUT Default

SYS_CLKOUT2 Default

SYS_CLKREQ Default

SYS_XTALIN FIXED

GPIO_149 4

GPIO_150 4

McBSP1 Default

McBSP2 User

McBSP3 Default

GPIO_171 4

GPIO_172 4

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8.10.9 GPIO Mapping

There are a number of GPIO pins from the processor that are used on the BeagleBoard design. Table 5 shows which of these GPIO pins are used in the design and whether they are inputs or outputs. While GPIO pins can be used as interrupts, the table only covers the

GPIO pin mode. If it is an interrupt, then it is covered in the interrupt section.

Table 5. Processor GPIO Pins

OMAP

PIN

INT/GPIO I/O Signal

AA9 GPIO_149 O LED_GPIO149 Controls User LED0

W8 GPIO_150 O LED_GPIO149 Controls User LED1

AG9 GPIO_23 I MMC1_WP

J25 GPIO_170 O DVI_PUP

AE21 GPIO_7 I SYSBOOT_5

USAGE

SD/MMC card slot Write protect

Controls the DVI-D interface. A Hi = DVI-D enabled.

Used to put the device in the boot mode or as a user button input

Other signals, such as those that connect to the expansion connector, may also be set as a

GPIO pin. For information on those, refer to the Expansion Connector section.

8.10.10 Interrupt Mapping

There are a small number of pins on the processor that act as interrupts. Some of these interrupts are connected to the TPS65950 and their status is reflected through the main

TPS65950 interrupt. Table 6 lists the interrupts.

TPS65950

Pin

P12

Table 6. Processor Interrupt Pins

Processor

PIN

INT/GPIO USAGE

AF26 SYS_nIRQ Interrupt from the TPS65950

AH8 GPIO_29 SD Write protect lead. Can be polled or set to an interrupt.

GPIO0 MMC1 card detect input. Goes to the processor over the

SYS_nIRQ pin.

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8.11 POP Memory Device

The processor uses what is called POP (Package-on-Package) memory. The memory is a

MCP (Multi Chip Package) that contains a dual Mobile DDR SDRAM stack. Figure 33 shows the POP Memory concept.

Figure 33. POP Memory

The Memory device mounts on top of the processor. The configuration used on the board is a 200MHz 4Gb MDDR SDRAM device from Micron.

8.12 System Clocks

There are three main clocks needed for the operation of the board, 32KHz, 26MHz and

McBSP_CLKS. Figure 34 shows the components that make up the System Clocks.

There are additional clocks needed elsewhere in the system, such as USB HUB, but those are discussed in separate sections.

VIO_1V8

OSC_EN R55 4.7K

Y 1

1

NC +VCC

2

COM/CASE OUT

OSC_26MHZ_EAE

4

3

C85

26MHZ

0.1uF,10V

U7A TPS65950

R56 33

R47

HFCLK_26MHz

33 HFCLKOUT

R51

C102 22PF T2_XOUT

33

A14

R12

OSC_EN

CLK256FS

C6

D7

G10

D13

P15

P16

Y3

32KHz Cry stal

N10

HFCLKIN

HFCLKOUT

CLKEN

CLKEN2

CLKREQ

CLK256FS

32KXOUT

32KXIN

32KCLKOUT

C103 22PF T2_XIN

AF25

AE17

AE25

T21

U4B

SYS_CLKREQ/GPIO_1

SYS_XTALIN

SYS_32K

McBSP_CLKS

Figure 34. System Clocks

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8.12.1 32KHz Clock

The 32KHz clock is needed for the TPS65950 and the processoe and is provided by the

TPS65950 via the external 32KHz crystal, Y2. The TPS65950 has a separate output from the crystal to drive the processor that buffers the resulting 32-kHz signal and provides it as 32KCLKOUT, which is provided to the processor on ball AE25. The default mode of the 32KCLKOUT signal is active, but it can be disabled if desired under SW control.

The 32.768-kHz clock drives the RTC embedded in the TPS65950. The RTC is not enabled by default; the host processor must set the correct date and time to enable the

RTC.

8.12.2 26MHz Clock

This section describes the 26MHz clock section of the BeagleBoard.

8.12.2.1 26MHz Source

The BeagleBoard is designed to support two suppliers of the 26MHz oscillator. The

26MHz clock is provided by an onboard oscillator, Y1. The TPS65950 receives the external HFCLKIN signal on ball A14 and uses it to synchronize or generate the clocks required to operate the TPS65950 subsystems. The TPS65950 must have this clock in order to function to the point where it can power up the BeagleBoard. This is the reason the 26MHz clock is routed through the TPS65950.

8.12.2.2 TPS65950 Setup

When the TPS65950 enters an active state, the Processor must immediately indicate the

HFCLKIN frequency (26 MHz) by setting the HFCLK_FREQ bit field (bits [1:0]) in the

CFG_BOOT register of the TPS65950. HFCLK_FREQ has a default of being not programmed, and in that condition, the USB subsection does not work. The three DCDC switching supplies (VIO, VDD1, and VDD2) operate from their free-running 3-MHz

(RC) oscillators, and the PWR registers are accessed at a default 1.5-M byte.

HFCLK_FREQ must be set by the processor during the initial power-up sequence. On the

BeagleBoard, this is done by the internal boot ROM on startup.

8.12.2.3 Processor 26MHz

The 26MHz clock for the processor is provided by the TPS65950 on ball R12 through

R38, a 33 ohm resistor is providing to minimize any reflections on the clock line. The clock signal enters via ball AE17 on the PROCESSOR.

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8.12.3 McBSP_CLKS

An additional clock is also provided by the TPS65950 called McBSP_CLKS. This clock is provided to the PROCESSOR in order to insure synchronization of the I2S interface between the processor and the TPS65950.

8.13 USB OTG Port

The BeagleBoard has a USB OTG (On-the-Go) port. It can be used as an OTG port,

Client port, or Host port. The main use is as a client port, as that is the mode that will supply the power needed to power the BeagleBoard. With the addition of the USB Host ports, the need to use three OTG port as a Host, is not really needed.

NOTE: In order to use the OTG in the Host mode, the

BeagleBoard must be powered from the DC supply.

8.13.1 USB OTG Overview

USB OTG is a supplement to the USB 2.0 specification. The standard USB uses a master/slave architecture, a USB host acting as a master and a USB peripheral acting as a slave. Only the USB host can schedule the configuration and data transfers over the link.

The USB peripherals cannot initiate data transfers, they only respond to instructions given by a host.

USB OTG works differently in that gadgets don't need to be pure peripherals because they can sometimes act as hosts. An example might be connecting a USB keyboard or printer to BeagleBoard or a USB printer that knows how to grab documents from certain peripherals and print them. The USB OTG compatible devices are able to initiate the session, control the connection and exchange Host/Peripheral roles between each other.

The USB OTG supplement does not prevent the use of a hub, but it describes role swapping only in the case of a one-to-one connection where two OTG devices are directly connected. If a standard hub is used, the supplement notes that using it will lead to losing USB OTG role-swap capabilities making one device as the Default-Host and the other as the Default-Peripheral until the hub is disconnected.

The combination of the processor and the TPS65950 allows the BeagleBoard to work as an OTG device if desired. The primary mode of operation however, is intended to be a client mode in order to pull power from the USB host which is typically a PC. As the Rev

B does not have a Host USB port, this port will be used as a Host port in many applications.

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8.13.2 USB OTG Design

Figure 34 is the design of the USB OTG port on the BeagleBoard.

4

4

4

4

USB0HS_CLK

USB0HS_STP

USB0HS_DIR

USB0HS_NXT

4

4

4

4

4

4

4

4

USB0HS_DAT0

USB0HS_DAT1

USB0HS_DAT2

USB0HS_DAT3

USB0HS_DAT4

USB0HS_DAT5

USB0HS_DAT6

USB0HS_DAT7

VBUS_5V0

L15

L14

L13

M13

U7A TPS65950

UCLK

STP

DIR

NXT

K14

K13

J14

J13

G14

G13

F14

F13

DATA0

DATA1

DATA2

DATA3

DATA4

DATA5

DATA6

DATA7

DN

DP

ID

T11

T10

R11

PGB0010603MR

R57 0,0603

R8

6 4.7uF,6.3V,0603

VBUS

J1

JMP

Revision A2

D1 D2

VBUS_5V0

PGB0010603MR

USB_CLIENT /

OTG PORT

P1

C3 D3 D4

0.1uF,10V

PGB0010603MR PGB0010603MR

1

2

3

4

5

VB

D-

D+

ID

G1 mini USB-AB

Figure 35. USB OTG Design

8.13.3 OTG ULPI Interface

ULPI is an interface standard for high-speed USB 2.0 systems. It defines an interface between USB link controller (processor) and the TPS65950 that drives the actual bus.

ULPI stands for UTMI+ low pin interface and is designed specifically to reduce the pin count of discrete high-speed USB PHYs. Pin count reductions minimize the cost and footprint of the PHY chip on the PCB and reduce the number of pins dedicated to USB for the link controller.

.

Unlike full- and low-speed USB systems, which utilize serial interfaces, high-speed requires a parallel interface between the controller and PHY in order to run the bus at

480Mbps. This leads to a corresponding increase in complexity and pin count. The ULPI used on the BeagleBoard keeps this down to only 12 signals because it combines just three control signals, plus clock, with an 8-bit bi-directional data bus. This bus is also used for the USB packet transmission and for accessing register data in the ULPI PHY.

8.13.3.1 Processor Interface

The controller for the ULPI interface is the Processor. It provides all of the required signals to drive the interface. Table 7 describes the signals from the processor that are used for the USB OTG interface.

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Table 7. Processor ULPI Interface

Signal Description Type Ball hsusb0_clk hsusb0_stp

Dedicated for external transceiver 60-MHz clock input from PHY

Dedicated for external transceiver Stop signal hsusb0_dir Dedicated for external transceiver Data direction control from PHY hsusb0_nxt Dedicated for external transceiver Next signal from PHY hsusb0_data0 Transceiver Bidirectional data bus hsusb0_data1 Transceiver Bidirectional data bus hsusb0_data2 Transceiver Bidirectional data bus hsusb0_data3 Transceiver Bidirectional data bus hsusb0_data4 Transceiver Bidirectional data bus hsusb0_data5 Transceiver Bidirectional data bus hsusb0_data6 Transceiver Bidirectional data bus hsusb0_data7 Transceiver Bidirectional data bus

I/O

I/O

I/O

I/O

I

O

I

I

I/O

I/O

I/O

I/O

8.13.3.2 TPS65950 Interface

The TPS65950 USB interfaces to the Processor over the ULPI interface. Table 8 is a list of the signals used on the TPS65950 for the ULPI interface.

T28

T25

R28

T26

T27

U28

U27

U26

U25

V28

V27

V26

Table 8. TPS65950 ULPI Interface

Signal Description Type Ball

UCLK

STP

DIR

NXT

DATA0

DATA1

DATA2

DATA3

DATA4

DATA5

DATA6

DATA7

High speed USB clock

High speed USB stop

High speed USB dir

High speed USB direction

High speed USB Data bit 0

High speed USB Data bit 0

High speed USB Data bit 0

High speed USB Data bit 0

High speed USB Data bit 0

High speed USB Data bit 0

High speed USB Data bit 0

High speed USB Data bit 0

I/O

I

O

O

I/O

I/O

I/O

I/O

I/O

I/O

I/O

I/O

8.13.4 OTG Charge Pump

When the TPS65950 acts as an A-device, the USB charge pump is used to provide 4.8

V/100 mA to the VBUS pin. When the TPS65950 acts as a B-device, the USB charge pump is in high impedance. If used in the OTG mode as an A-device, the BeagleBoard will need to be powered from the DC supply. If acting as a B-device, there will not be a voltage source on the USB OTG port to drive the BeagleBoard. Table 9 describes the charge pump pins.

L15

L14

L13

M1

K14

K13

J14

J13

G14

G13

F14

F13

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Table 9. USB OTG Charge Pump Pins

Signal

CP.IN

CP.CAPP

CP.CAPM

CP.GND

Description

The charge pump input voltage. Connected to VBAT.

The charge pump flying capacitor plus.

The charge pump flying capacitor minus.

The charge pump ground.

Type Ball

Power R7

O L14

O

GND

T6

R6

The charge pump is powered by the VBAT voltage rail. The charge pump generates a

4.8-V (nominal) power supply voltage to the VBUS pin. The input voltage range is 2.7 V to 4.5 V so the 4.2V VBAT is within this range. The charge pump operating frequency is

1 MHz. The charge pump integrates a short-circuit current limitation at 450 mA.

8.13.5 OTG USB Connector

The OTG USB interface is accessed through the miniAB USB connector. If you want to use the OTG port as a USB Host, pin 4 of the connector must be grounded. The -xM Rev

A version of Beagle provides jumper pad, J6 that allows for a small piece of solder to be placed on the pads to perform this function. It should be noted that with the USB Host port on the -xM Rev A Beagle, the need to convert the OTG port to a host mode is greatly diminished.

8.13.6 OTG USB Protection

Each lead on the USB port has ESD protection. In order for the interface to meet the USB

2.0 Specification Eye Diagram, these protection devices must be low capacitance.

8.14 Onboard USB HUB

A new feature of the –xM board is the inclusion of an onboard USB 4 port hub with an integrated 10/100 Ethernet. This section describes the design of the HUB and the interface to the processor. This allows for the support of LS and FS USB devices without the need for an external USB HUB. Figure 36 is a high level block diagram of the system design of the integrated HUB.

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Figure 36. USB HUB Block Diagram

The following section covers each of the key function in the overall design. o

Power o

HS USB PHY o

HUB o

USB Port Power o

Ethernet

8.14.1 Power

The power for the HUB is provided by two sources. Figure 37 is the design of the HUB power circuitry. The HUB_3V3 rail, the main supply rail for the HUB, is provided by

U16, a TL1963A LDO. Power for the LDO is provided by the DC_5V_USB rail from the overvoltage protection circuit. The LDO is set to provide 3.3V and is set by R111 and

R113. This rail can be turned on or off from the processor by using the I2C bus to communicate to the TPS65950. By default, the LDO is turned off.

The TPS65950 provides the USB_1V8 rail which is used by the USB PHY. The processor can turn on or off this rail by communicating with the TPS65950 via the I2C bus.

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AM37xx_ES1.0

I2C1_SDA

I2C1_SCL

U4B

J21

K21

D4

D5

U7A TPS65950

VAUX2.OUT

I2C.CNTL.SDA

I2C.CNTL.SCL

LEDA/VIBRA.P

M3

F15

USB_1V8

VBAT

DC_5V_USB

2

1

3

U16

IN OUT

SHDN GND

GND ADJ

TL1963A

4

6

5

R120

200K,1%,0603

4.7uF,6.3V,0603 C211

U16_FB R111

R113

56.2K,1%

32.4K,1%

HUB_3V3

C177

4.7uF,6.3V,0603

D14

LTST-C190GKT

USB ACTIVE

R136

330

Figure 37. HUB Power Circuitry

A green LED, D14, indicates that power is applied to the HUB circuitry.

8.14.2 HS USB PHY

The configuration of the HS USB PHY is basically the same as on the Rev C4 design. A

PHY is required between the processor ULPI interface and the USB HUB. Figure 39 shows the processor and PHY interface.

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OMAP3730_ES1.0

U4B

HSUSB2_TLL_STP

HSUSB2_TLL_DIR

HSUSB2_TLL_NXT

HSUSB2_D0

HSUSB2_D1

HSUSB2_D2

HSUSB2_D3

HSUSB2_D4

HSUSB2_D5

HSUSB2_D6

HSUSB2_D7

AF7

AG7

AH7

AG8

AH8

AB2

V3

Y 2

Y 3

Y 4

AA3

GPIO_56

HSUSB2_CLK

R8

AE7

USB_1V8

R98

0,0603

HUB_3V3

10

13

7

9

16

15

27

26

25

5

6

3

4

29

31

2

1

U14

STP

DIR

NXT

CLKOUT

DATA0

DATA1

DATA2

DATA3

DATA4

DATA5

DATA6

DATA7

SPK_R

SPK_L

RESETB

REFCLK

VBUS

DM

DP

ID

RBIAS

REFSEL0

REFSEL1

REFSEL2

VDD3.3

VDDIO

VDD1.8_1

VDD1.8_0

CPEN

VBAT

NC

GND

24

8

11

14

22

19

18

23

20

32

30

28

17

21

12

33

USB33_VBUS

USB33_ID

USB33_RBIAS

R99

R100

R102

10K,DNI

0

8.06K_1%_0603

USBDM0

USBDP0

USB_1V8F

C206

USB33_VDD3.3

C164

L12

USB_1V8

1 2

C205

30MHZ_50mA

C167

C165

0.1uF,10V

0.1uF,10V

0.1uF,10V

4.7uF,6.3V,0603

10uF,CER,0805,6.3V

R103

10K HUB_3V3

C168

0.1uF,10V

C169

4.7uF,6.3V,0603

Figure 38. USB PHY Design

The interface to the processor is the HSUSB2 interface. The signals used on this interface are contained in Table 10.

Table 10. USB Host Port OMAP Signals

Signal

Hsusb2_clk

Hsusb2_stp

Hsusb2_dir

Description

External transceiver 60-MHz clock output to PHY

External transceiver Stop signal

Transceiver data direction control from PHY

Hsusb2_nxt Next signal from PHY

Hsusb2_data0 Bidirectional data bus signal for 12-pin ULPI operation

Hsusb2_data1 Bidirectional data bus signal for 12-pin ULPI operation

Hsusb2_data2 Bidirectional data bus signal for 12-pin ULPI operation

Hsusb2_data3 Bidirectional data bus signal for 12-pin ULPI operation

Hsusb2_data4 Bidirectional data bus signal for 12-pin ULPI operation

Hsusb2_data5 Bidirectional data bus signal for 12-pin ULPI operation

Hsusb2_data6 Bidirectional data bus signal for 12-pin ULPI operation

Hsusb2_data7 Bidirectional data bus signal for 12-pin ULPI operation

Gpio_147 Enable/reset line to the USB PHY.

Input/Output

O

O

I

I

I/O

I/O

I/O

I/O

I/O

I/O

I/O

I/O

O

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The husb2_clk signal is an output only and is used to support a HS USB PHY that supports an input clock mode. The SMSC PHY device supports this mode and is used on the Beagle.

The PHY used in the design is a USB3320 series device from SMSC. The USB3320 is a highly integrated Hi-Speed USB2.0 Transceiver (PHY) that meets all of the electrical requirements to be used as a Hi-Speed USB Host. In this design, only the host mode of operation is being supported as it is used to connect to the HUB on the board.

In order to interface to the processor, the device must be used in the 60MHz clock mode.

This is done by tying the CLKOUT signal on the USB PHY to VIO_1V8. On -XM Rev

A, a zero ohm series resistor was added. This is not required, but was added as a “just in case” option if the CLKOUT signal was a source of noise in the PHY. It was proven not to be the case. The clock for the PHY is derived from the 60MHz signal generated by the processor. All of the signals and their functions align with the descriptions found in the processor interface section.

The USB3322 device requires two voltages, the USB_1V8 rail to power the I/O rails and the HUB_3V3 to power the rest of the device. The 3.3V rail for the device is generated internally and requires a filter and bypass cap to be connected externally. The USB_1V8 rail is derived from the VAUX2 rail supplied by the TPS65950 PMIC.

The RBIAS block in the PHY consists of an internal bandgap reference circuit used for generating the driver current and the biasing of the analog circuits. This block requires an external 8.06KΩ, 1% tolerance, reference resistor connected from RBIAS to ground. The nominal voltage at RBIAS is 0.8V and therefore the resistor will dissipate approximately

80µW of power.

As we are not using this device to support the OTG protocol but instead as a host device, we ground the ID pin to force it into a Host mode at all times. The USB3322 transceiver fully integrates all of the USB termination resistors on both DP and DM. This includes

1.5kΩ pull-up resistors, 15kΩ pull-down resistors and the 45Ω high speed termination resistors. These resistors require no tuning or trimming.

8.14.3 USB HUB

The key component in the HUB design is a SMSC LAN9514 USB HUB plus Ethernet device. Figure 40 is the HUB design.

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HUB_3V3

C184

4.7uF,6.3V,0603

C180 C181 C183

0.1uF,10V

C182

0.1uF,10V

0.1uF,10V

C185

0.1uF,10V

0.1uF,10V

1

L11

2.0 Amp/0.05 DCR

2

C190 C186

4.7uF,6.3V,0603 0.1uF,10V

VDD18CORE

38

VDD18ETHPLL

VDD18USBPLL

48

62

19

27

33

39

46

C187

1uF,10V

VDD33IO

VDD33IO

VDD33IO

VDD33IO

VDD33IO

U15

Pow er

VDD33A

VDD33A

VDD33A

VDD33A

VDD33A

VDD33A

VDD33A

VDD18CORE

VDD18CORE

VDD18ETHPLL

VDD18USBPLL

Upstream

VSS(FLAG)

5

10

49

51

54

57

64

65

HUB_3V3

R101

C196

C197 R109

0.1uF,10V 12K,1%

100K

USRBIAS

VBUS_DET

63

USBRBIAS

USBDP0

USBDM0

59

58

1uF,10V Dow nstream

USBDP0

USBDM0

HUB_3V3

HUB_3V3A

1

L10

2.0 Amp/0.05 DCR

2

USBDM2

USBDP2

PRTCTL2

USBDM3

USBDP3

PRTCTL3

1

2

14

3

4

16

USBDM2

USBDP2

USBDM_2

USBDP_2

3 HUB_RESET

3

U18B

SN74LVC2G06DCKR

4

USBDM4

USBDP4

PRTCTL4

USBDM5

USBDP5

PRTCTL5

6

7

17

8

9

18

HUB_3V3

R105

100K

R112

HUB_3V3 nHUB_RESET

1M

R118

10K

XO xtal2-216x60-hcm49

1

25.000MHz

2

Y 4

C178

33pF

C179

33pF

HUB_3V3

R129

R128

R108

R107

R63

12.4K,1%,0603

AUTOMDIX_EN

HUB_3V3

26

EEDI

EEPROM

EEDO

EECS

EECLK

25

24

23

Ethernet

EXRES

41

AUTOMDIX_EN

RXP

RXN

TXP

TXN

52

53

55

56

13

34

40

47

12

TEST1

TEST2

TEST3

TEST4 n_RESET

GPIO + Misc.

nFDX_LED/GPIO0 nLNKA_LED/GPIO1 nSPD_LED/GPIO2

GPIO3

GPIO4

GPIO5

GPIO6

GPIO7

20

21

22

35

36

37

42

43

RXP

RXN

TXP

TXN

XI 61

XI

60

XO

10K

10K

10K

10K

HUB_nTRST

HUB_TMS

HUB_TDI

HUB_TCK

28

29

30

31

32 nTRST

TMS

TDI

TDO

TCK

Clocks

CLK24_EN

44

CLK24_OUT

45

JTAG

CLK24_EN qf n64-11x27-smsc

LAN9514

R106

10K

Figure 39. USB HUB Design

The LAN9514/LAN9514i is a high performance Hi-Speed USB 2.0 hub with a 10/100

Ethernet controller. The LAN9514/LAN9514i contains an integrated USB 2.0 hub, four integrated downstream USB 2.0 PHYs, an integrated upstream USB 2.0 PHY, a 10/100

Ethernet PHY, a 10/100 Ethernet Controller.

The main power supply for the LAN9514 is the HUB_3V3 supplied by the dedicated power regulator. Filtering is required on all input pins. A 1.8V core voltage is derived form an internal LDO and requires external filtering.

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The LAN9514 requires an external 25MHZ crystal to generate the required internal clocks. The optional 24MHz clock output is not used on the board and is disabled.

The AUTOMIDX feature is enabled which allows for auto polarity detection. This enables the port to automatically switch the TX and RX leads if needed.

8.14.4 USB Port Connectors

There a two dual port type A USB connectors used on the –xM board each one provides connections for four signals, DP, DM, VBUS, and Ground. You will notice that there are no external ESD devices on the connector. The ESD protection is integrated into the USB

HUB.

Figure 41 is the design of the power control for each USB host port. Each port can be turned on or off from the LAN9514 over the USB interface. U13, a TPS2045, is a four port FET with over current detection. The overcurrent detect output is tied to the enable pin from the LAN9514. In an over current condition the signal is immediately turned off without waiting for the processor to turn off the power. The LAN9514 detects the overcurrent condition and keeps the over current condition turned off..

DC_5V_USB

2

6

7

8

3

4

U13

IN1

IN2

EN1

EN2

EN3

EN4

OUT1

OUT2

OUT3

OUT4

OC1

OC2

OC3

OC4

15

14

11

10

16

13

12

9

VBUS1

VBUS2

VBUS3

VBUS4

C160

+

100UF

C161

+

100UF

C162

+

100UF

C163

+

100UF

TPS2054BD

LAN9514 U15

USBDM2

USBDP2

PRTCTL2

USBDM3

USBDP3

PRTCTL3

1

2

14

3

4

16

USBDM4

USBDP4

PRTCTL4

USBDM5

USBDP5

PRTCTL5

6

7

17

8

9

18

VBUS1

USBDM_1

USBDP_1

VBUS2

USBDM_2

USBDP_2

VBUS3

USBDM_3

USBDP_3

VBUS4

USBDM_4

USBDP_4

A1

A2

A3

A4

B1

B2

B3

B4

P14

USB-A Conn.

VBUSA

DA-

DA+

GNDA

SHIELD

SHIELD

SHIELD

VBUSB

DB-

DB+

GNDB

SHIELD

MH1

MH2

MH3

MH4

A1

A2

A3

A4

B1

B2

B3

B4

P16

USB-A Conn.

VBUSA

DA-

DA+

GNDA

SHIELD

SHIELD

SHIELD

VBUSB

DB-

DB+

GNDB

SHIELD

MH1

MH2

MH3

MH4

Figure 40. USB Port Power Design

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Each USB Host port has its own dedicated FET and power control. A 100uf capacitor is connected to each USB power port for added surge current capabilities. A .1uf capacitor

8.14.5 Ethernet

Figure 41 is the circuitry that applies to the Ethernet interface on the board. The

LAN9514 device while performing the function of the HUB also contains the Ethernet controller.

HUB_3V3

LAN9514 U15

RXP

RXN

TXP

TXN

52

53

55

56

RXP

RXN

TXP

TXN nFDX_LED/GPIO0 nLNKA_LED/GPIO1 nSPD_LED/GPIO2

20

21

22 nLNKA nSPD R104

R50

330

330

HUB_3V3 nSPDR nLNKAR

HUB_3V3A

TCT_RCT

C198

0.022uF,10V

15

16

17

18

11

12

9

10

2

7

3

1

8

6

P15

TCT

TD+

TD-

RD+

RD-

RCT

GND1

GND2

Y ELC

Y ELA

GRNC

GRNA

SHD1

SHD2

GRN+

GRN-

Y EL-

Y EL+

ETHER

4

5

13

14

R119

0,1210

Figure 41. USB Based Ethernet Design

The 10/100 Ethernet controller provides an integrated Ethernet MAC and PHY which are fully IEEE 802.3 10BASE-T and 802.3u 100BASE-TX compliant. A connector, P15, with integrated magnetics is used to provide the physical interface off the board. The

Ethernet features auto polarity correction and Auto-MIDX.

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8.15 microSD

The board provides a single microSD interface. Its primary use is for providing the boot source for SW. Unlike the Rev C4, it cannot be used for the typical SDIO or MMC functions. Figure 42 is the microSD interface design on the BeagleBoard.

VDD_MMC1

C144 C145

0.1uF,10V

10uF,CER,0805,6.3V

VIO_1V8

U7A TPS65950

VMMC1.OUT

CD1

C2

P12

U4A

MMC1_DAT2

MMC1_DAT3

MMC1_CMD

N25

P28

M27

MMC1_CLK

N28

MMC1_DAT0

MMC1_DAT1

PROCESSOR

N27

N26

R16 33

7

8

5

6

3

4

1

2

P7

DAT2

CD/DAT3

CMD

VDD

CLOCK

VSS

DAT0

DAT1 microSD

SCHA2B0300

GND

CD

GND3

GND4

TBD1

TBD2

TBD3

9

10

11

12

13

14

15

R135

10K

Figure 42. microSD Interface

8.15.1 microSD Power

The microSD connector is supplied power from the TPS65950 using the VMMC1 rail.

The default setting on this rail is 3.0V as set by the Boot ROM and under SW control, can be set to 1.80V for use with 1.8V cards. The maximum current this rail can provide is

220mA as determined by the TPS65950 regulator. Maximum current can be limited by the overall current available from the USB interface of the PC.

8.15.2 Processor Interface

There are no external buffers required for the microSD operation. The processor provides all of the required interfaces for the microSD interface. Table 11 provides a description of the signals on the MMC card.

Signal Name

MMC1_CLK

Table 11. SD/MMC OMAP Signals

Description

SD/MMC Clock output.

I/O Pin

O N28

I/O M27

P26,R27,R25

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8.15.3 Card Detect

When a card is inserted into the connector, the Card Detect pin is grounded. This is detected on pin P12 of the TPS65950. An interrupt, if enabled, is sent to the processor via the interrupt pin. The SW can be written such that the system comes out of sleep or a reduced frequency mode when the card is detected.

8.15.4 Booting From SD/MMC Cards

The ROM code supports booting from the microSD cards with some limitations: o

Support for SD cards compliant with the Multimedia Card System Specification v4.2 from the MMCA Technical Committee and the Secure Digital I/O Card

Specification v2.0 from the SD Association. Including high-capacity (size >2GB) cards: HC-SD and HC MMC. o

3-V power supply, 3-V I/O voltage on port 1 o

Initial 1-bit MMC mode, 4-bit SD mode. o

Clock frequency:

– Identification mode: 400 kHz

– Data transfer mode: 20 MHz o

Only one card connected to the bus o

FAT12/16/32 support, with or without master boot sector (MBR).

The high-speed microSD host controllers handle the physical layer while the ROM code handles the simplified logical protocol layer (read-only protocol). A limited range of commands is implemented in the ROM code. The MMC/SD specification defines two operating voltages for standard or high-speed cards. The ROM code only supports standard operating voltage range (3-V). The ROM code reads out a booting file from the card file system and boots from it.

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8.16 Audio Interface

The BeagleBoard supports stereo in and out through the TPS65950 which provides the audio CODEC.

Figure 43 is the Audio circuitry design on the BeagleBoard.

U7A TPS65950

HSOL

HSOR

B4

B5

HSMIC.P

HSMIC.M

E3

F3

MIC.MAIN.P

MIC.MAIN.M

E2

F2

MIC.SUB.P/DIG.MIC.0

MIC.SUB.M/DIG.MIC1

G2

H2

AUXL

AUXR

F1

G1

HSOL

C87

HSOR

C88

INTER_HSOL

47uF,CER

R58

INTER_HSOR

47uF,CER

R60

33

33

CONN_HSOL

CONN_HSOR

HSMIC.P

HSMIC.M

C89

47pF C90

47pF

D8 D9

MIC.MAIN.P

MIC.MAIN.M

DIG.MIC.0

DIG.MIC.1

C97

100PF

C92

100pF

C93

100pF

C96

100PF

AUXL

AUXR

C94

100PF

C95

100PF

C98 0.1uF,10V CONN_AUXL

C99 0.1uF,10V

C100

47pF

CONN_AUXR

D10 D11

C101

47pF

1

3

2

P5

AUDIO_OUT

1

3

AUDIO_IN

P6

2

Figure 43. Audio Circuitry

8.16.1 Processor Audio Interface

There are five McBSP modules called McBSP1 through McBSP5 on the AM3730.

McBSP2 provides a full-duplex, direct serial interface between CODEC inside the

TPS65950. It supports the I2S format to the TPS65950. In Table 12 are the signals used on the processor to interface to the CODEC.

Signal Name mcbsp2_dr mcbsp2_dx mcbsp2_clkx mcbsp2_fsx

Mcbsp_clks

Table 12. Processor Audio Signals

Description

Received serial data

Transmitted serial data

Combined serial clock

Combined frame synchronization

External clock input. Used to synchronize with the TPS65950

I/O Pin

I

I/O

I/O

I/O

R21

M21

N21

P21

I T21

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8.16.2 TPS65950 Audio Interface

The TPS65950 acts as a master or a slave for the I2S interface. If the TPS65950 is the master, it must provide the frame synchronization (I2S_SYNC) and bit clock (I2S_CLK) to the processor. If it is the slave, the TPS65950 receives frame synchronization and bit clock. The TPS65950 supports the I2S left-justified and right-justified data formats, but doesn’t support the TDM slave mode .

In Table 13 are all the signals used to interface to the processor.

Table 13. Processor Audio Signals

Signal Name

I2S.CLK

I2S.SYNC

I2S.DIN

I2S. DOUT

CLK256FS

Description

Clock signal (audio port)

Synchronization signal (audio port)

Data receive (audio port)

Data transmit (audio port)

Synchronization frame sync to the AM3730

I/O

I/O

IO

I

O

O

Pin

L3

K6

K4

K3

D13

A new feature on the –xM is the ability to access the audio signals for use on an external add on board. If this feature is to be used, you must disable via SW this interface on the

TPS65950.

8.16.3 Audio Output Jack

A single 3.5mm jack is provided on BeagleBoard to support external stereo audio output devices such as headphones and powered speakers. This interface is not amplified and may require the use of amplified speakers in certain instances.

8.16.4 Audio Input Jack

A single 3.5mm jack is supplied to support external audio inputs including stereo or mono. If a microphone is o be used, it may require additional amplification of the signal for proper use.

Page 86 of 164

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Reference Manual

Revision A2

8.17 DVI-D Interface

The LCD interface on the processor is accessible from the DVI-D interface connector on the board. Figure 44 is the DVI-D interface design.

AUX_3V3

L7

L8

1

1

2

2

FERRITE, MMZ1608R301A

DVI_PVDD

TVDD

FERRITE, MMZ1608R301A

C152 0.1uF,10V

C153 0.1uF,10V

C154 0.1uF,10V

L9 1 2 FERRITE, MMZ1608R301A

DVI_DVDD C155 0.1uF,10V

VIO_1V8 C156 0.1uF,10V

C157 0.1uF,10V

DC_5V

PTC_RXEF010

RT1

Processor U4A

DSS_D0

DSS_D1

DSS_D2

DSS_D3

DSS_D4

DSS_D5

DSS_D6

DSS_D7

DSS_D8

DSS_D9

DSS_D10

DSS_D11

DSS_D12

DSS_D13

DSS_D14

DSS_D15

DSS_D16

DSS_D17

DSS_D18

DSS_D19

DSS_D20

DSS_D21

DSS_D22

DSS_D23

DSS_D18

DSS_D19

DSS_D20

DSS_D21

DSS_D22

DSS_D23

DSS_PCLK

DSS_ACBIAS

DSS_HSYNC

DSS_VSYNC

F27

G26

AD28

AD27

AB28

AB27

AA28

AA27

AG22

AH22

AG23

AH23

AG24

AH24

E26

F28

G25

H27

H26

H25

E28

J26

AC27

AC28

AH26

AG26

AF18

AF19

AE21

AF21

D28

E27

D26

D27

RP1F

RP1E

RP1D

RP1C

RP1B

RP1A

4

3

2

1

6

5

RP2C

RP2D

RP2E

RP2F

RP2G

RP2H

RP3A

RP3B

RP3C

RP3D

RP3E

RP3F

RP3G

RP3H

RP4A

RP4B

RP4C

RP4D 4

RP7H

RP7G

RP7F

RP7E

RP7D

RP7C

2

3

8

1

6

7

4

5

2

3

8

1

6

7

3

4

5

5

4

3

8

7

6

RP5A

RP5B

RP5C

RP5D

RP5E

RP5F

3

4

1

2

5

6

11

12

13

14

15

16

10

10

10

10

10

10

9

16

15

14

13

9

10

10

10

10

10

11

12

13

14

10

10

10

10

10

10

10

10

10

10

10

10

10

10

10

10

10

10

10

10

13

12

11

10

9

16

15

14

14

13

12

11

10

16

15

14

13

12

11

10

10

10

10

10

10

RP4H 8

RP4G

RP4F 6

RP4E

7

5

AUX_3V3

Adjusted for .9V

R85

R84

8.45K_1%_0603

8.06K_1%_0603

9 10

11

10

12

10

10

10

R90

R91

DVI_CLK+

DVI_DEN

DVI_PUP

DVI_DATA0

DVI_DATA1

DVI_DATA2

DVI_DATA3

DVI_DATA4

DVI_DATA5

DVI_DATA6

DVI_DATA7

DVI_DATA8

DVI_DATA9

DVI_DATA10

DVI_DATA11

DVI_DATA12

DVI_DATA13

DVI_DATA14

DVI_DATA15

DVI_DATA16

DVI_DATA17

DVI_DATA18

DVI_DATA19

DVI_DATA20

DVI_DATA21

DVI_DATA22

DVI_DATA23

DVI_VSYNC

DVI_HSYNC

57

56

2

5

4

3

47

46

45

44

53

52

51

50

59

58

55

54

63

62

61

60

39

38

37

36

43

42

41

40

10

13

R93

R94

R95

R96

R97

10K

10K

1K

10K

RES_0_0402,DNI

RES_0_0402,DNI

RES_0_0402,DNI

ISEL

BSEL

DVI_DSEL

DK3

DK2

DK1

15

14

6

7

8

TFP410

U11

PD16

PD17

PD18

PD19

PD20

PD21

PD22

PD23

IDCK+

IDCK-

DE

VSYNC

HSYNC

VREF

PD8

PD9

PD10

PD11

PD12

PD13

PD14

PD15

PD0

PD1

PD2

PD3

PD4

PD5

PD6

PD7

PD

ISEL/RESET

BSEL/SCL

DSEL/SDA

DK3

DK2

DK1

TXD2-

TXD2+

TXD1-

TXD1+

30

31

27

28

HTPLG

TXD0-

TXD0+

9

24

25

TXC+

TXC-

22

21

TFADJ

DKEN

RSVD2

NC

19

35

34

49

MSEN

11

HTPLG R86

TXD2-

TXD2+

TXD1-

TXD1+

AUX_3V3

10K

TXD0-

TXD0+

TVDD

TFADJ

DKEN

410_NC

TXC+

TXC-

AUX_3V3

R87

510

R88

1K

R89

VIO_1V8

4.7K

R92

4.7K

MSEN t

100Ma

DVI_+5v

3

1

2

15

16

6

4

5

P12

DAT2-

DAT2+

DAT2_S

MTG1

SCL

SDA

DAT1-

DAT1+

DAT1_S

MTG2

MTG3

11

10

12

CLK_S

CLK+

CLK-

CEC

NC

CONN_HDMI

MTG1

MTG2

MTG3

18

17

19

9

7

8

+5V MTG4

DDC/CEC GND

HPLG

DAT0-

DAT0+

DAT0_S

MTG4

13

14

U5B

SN74LVC2G07DBVR

4

3 DVI_UP

Insures that the

DVI-D is powered down at powerup.

R43

10K

3

4

4

VIO_1V8

I2C3_SCL

I2C3_SDA

C159 0.1uF,10V

I2C3_SCL

I2C3_SDA 4

6

3

5

VCCA

A1

A2

OE

U12

VCCB

B1

B2

GND

TXS0102DCU

DDC I2C Interface

1

2

7

8

Internal 10K Pullups.

C158 0.1uF,10V

DDC_I2C3_SCL

DDC_I2C3_SDA

Figure 44. DVI-D Interface

One of the main changes in the DSS area on the –xM is the change of the DSS pin usage.

The processor requires that different pins be used if 720p resolutions are required. These pins are different than those that are currently used on the Rev C4. The basic change requires that the DSS_D0-D5 need to be moved to the pins that normally carry the

DSS_D18-D23 leads. In this case, the signals for DSS_D18-D23 need to be moved to other pins. Reflected in Figure 44 are four resistor packs inside either Red or Blue boxes.

These are the loading options to enable the new mode used by the –xM or the legacy mode used by the Rev C4. The resistor packs in the RED boxes are installed and the

BLUE boxes are not installed on the –xM to support the 720p resolution.

For legacy operation, you would need to install the BLUE boxes and leave out the RED boxes. The SW will take care of this automatically, but you may want to do this if your design were to need to work in the legacy mode.

Page 87 of 164

REF: BB_SRM_xM BeagleBoard-xM System

Reference Manual

Revision A2

8.17.1 Processor LCD Interface

The main driver for the DVI-D interface originates at the processor via the DSS pins. The

AM3730 provides 24 bits of data to the DVI-D framer chip, TFP410. There are three other signals used to control the DVI-D that originate at the processor. These are

I2C3_SCL, I2C3_SDA, and GPIO_170. All of the signals used are described in Table

14.

Table 14. Processor LCD Signals

Signal dss_pclk dss_hsync dss_vsync dss_acbias dss_data0 dss_data1 dss_data2 dss_data3 dss_data4 dss_data5 dss_data6 dss_data7 dss_data8 dss_data9 dss_data10 dss_data11 dss_data12 dss_data13 dss_data14 dss_data15 dss_data16 dss_data17 dss_data18 dss_data19 dss_data20 dss_data21 dss_data22 dss_data23

GPIO_170

I2C3_SCL

I2C3_SDA

Description

LCD Pixel Clock

LCD Horizontal Synchronization

LCD Vertical Synchronization

Pixel data enable (TFT) output

LCD Pixel Data bit 0

LCD Pixel Data bit 1

LCD Pixel Data bit 2

LCD Pixel Data bit 3

LCD Pixel Data bit 4

LCD Pixel Data bit 5

LCD Pixel Data bit 6

LCD Pixel Data bit 7

LCD Pixel Data bit 8

LCD Pixel Data bit 9

LCD Pixel Data bit 10

LCD Pixel Data bit 11

LCD Pixel Data bit 12

LCD Pixel Data bit 13

LCD Pixel Data bit 14

LCD Pixel Data bit 15

LCD Pixel Data bit 16

LCD Pixel Data bit 17

LCD Pixel Data bit 18

LCD Pixel Data bit 19

LCD Pixel Data bit 20

LCD Pixel Data bit 21

LCD Pixel Data bit 22

LCD Pixel Data bit 23

Powers down the TFP410 when

Lo. TFP410 is active when Hi.

I2C3 clock line. Used to communicate with the monitor to determine setting information.

I2C3 data line. Used to communicate with the monitor to determine setting information.

GREEN4

GREEN5

GREEN6

GREEN7

RED0

RED1

RED2

RED3

RED4

RED5

RED6

RED7

BLUE0

BLUE1

BLUE2

BLUE3

BLUE4

BLUE5

BLUE6

BLUE7

GREEN0

GREEN1

GREEN2

GREEN3

Type Ball

(Legacy)

Ball

(720p)

O

O

O

O

D28

D26

D27

E27

D28

D26

D27

E27

O AG22 H26

O AH22 H25

O AG23 E28

O AH23 J26

O AG24 AC27

O AH24 AC28

O E26 E26

O F28 F28

O F27 F27

O G26 G26

O AD28 AD28

O AD27 AD27

O AB28 AB28

O AB2 AB2

O AA28 AA28

O AA27 AA27

O G25 G25

O H27 H27

O H26 AH26

O H25 AG26

O E28 AF18

O J26 AF19

O AC27 AE21

O AC28 AF21

O J25

10ohm series resistors are provide in the signal path to minimize reflections in the high frequency signals from the processor to the TFP410. These resistors are in the form of

Page 88 of 164

IDCK+

IDCK-

DE

HSYNC

VSYNC

DK3

DK2

DK1

REF: BB_SRM_xM BeagleBoard-xM System

Reference Manual

Revision A2 resistor packs on the BeagleBoard. The maximum clock frequency of these signals is

65MHz.

It should be noted that on the Rev A2 version, the ability to shut off the DVI-D display is not supported. This will be fixed on the next letter revision of the board.

8.17.2 LCD Power

In order for the DSS outputs to operate correctly out of the processor, two voltage rails must be active, VIO_1V8 and VDD_PLL2. Both of these rails are controlled by the

TPS65950 and must be set to 1.8V. By default, VDD_PLL2 is not turned and must be activated by SW. Otherwise some of the bits will not have power supplied to them.

8.17.3 TFP410 Power

Power to the TFP410 is supplied from the 3.3V regulator in U1, the TPS2141. In order to insure a noise free signal, there are three inductors, L4, L5, and L6 that are used to filter the 3.3V rail into the TFP410.

8.17.4 TFP410 Framer

The TFP410 provides a universal interface to allow a glue-less connection to provide the

DVI-D digital interface to drive external LCD panels. The adjustable 1.1-V to 1.8-V digital interface provides a low-EMI, high-speed bus that connects seamlessly with the

1.8V and 24-bit interface output by the processor. The DVI interface on the BeagleBoard supports flat panel display resolutions up to XGA at 65 MHz in 24-bit true color pixel format.

Table 15 is a description of all of the interface and control pins on the TFP410 and how they are used on BeagleBoard.

Signal Name

DATA[23:12]

DATA[11:0]

Table 15. TFP410 Interface Signals

Description

The upper 12 bits of the 24-bit pixel bus.

The bottom 12 bits of the 24-bit pixel bus.

Single ended clock input.

Tied to ground to support the single ended mode.

Data enable. During active video (DE = high), the transmitter encodes pixel data, DATA[23:0]. During the blanking interval

(DE = low), the transmitter encodes HSYNC and VSYNC.

Horizontal sync input

Vertical sync input

These three inputs are the de-skew inputs DK[3:1], used to adjust the setup and hold times of the pixel data inputs

DATA[23:0], relative to the clock input IDCK±.

A low level indicates a powered on receiver is detected at the

Type Ball

I

I

I

I

I

36–47

50–55.56-

53

57

56

2

I

I

4

5

I 6

I 7

I 8

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REF: BB_SRM_xM BeagleBoard-xM System

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Revision A2

MSEN

ISEL

BSEL

DSEL

EDGE

DKEN

V REF

PD

TGADJ differential outputs. A high level indicates a powered on receiver is not detected.

This pin disables the I2C mode on chip. Configuration is specified by the configuration pins (BSEL, DSEL, EDGE,

VREF) and state pins (PD, DKEN).

Selects the 24bit and single-edge clock mode.

Lo to select the single ended clock mode.

A high level selects the primary latch to occur on the rising edge of the input clock IDCK

A HI level enables the de-skew controlled by DK[1:3]

Sets the level of the input signals from the AM3730.

A HI selects normal operation and a LO selects the powerdown mode.

This pin controls the amplitude of the DVI output voltage swing, determined by the value of the pullup resistor RTFADJ connected to 3.3V.

8.17.5 TFP410 Control Pins

O 11

I

I

13

I

I

13

14

I 9

I

I

35

3

I 10

19

There are twelve control pins that set up the TFP410 to operate with the processor. Most of these pins are set by HW and do not require any intervention by the processor to set them.

8.17.5.1 ISEL

The ISEL pin is pulled LO via R99 to place the TFP410 in the control pin mode with the

I2C feature disabled. This allows the other modes for the TFP410 to be set by the other control pins.

8.17.5.2 BSEL

The BSEL pin is pulled HI to select the 24 bit mode for the Pixel Data interface from the processor.

8.17.5.3 DSEL

The DSEL pin is pulled low to select the single ended clock mode from the AM3730.

8.17.5.4 EDGE

The EDGE signal is pulled HI through R82 to select the rising edge on the IDCK+ lead which is the pixel clock from the AM3730.

8.17.5.5 DKEN

The DKEN signal is pulled HI to enable the de-skew pins. The de-skew pins, DK1-DK3, are pulled low by the internal pulldown resistors in the TFP410. This is the default mode of operation. If desired, the resistors can be installed to pull the signals high. However, it

Page 90 of 164

REF: BB_SRM_xM BeagleBoard-xM System

Reference Manual

Revision A2 is not expected that any of the resistors will need to be installed. The DK1-DK3 pins adjust the timing of the clock as it relates to the data signals.

8.17.5.6 MSEN

The MSEN signal, when low, indicates that there is a powered monitor plugged into the

DVI-D connector. This signal is not connected to the AM3730 and is provided as a test point only.

8.17.5.7 VREF

The VREF signal sets the voltage level of the DATA, VSYNC, HSYNC, DE, and

IDCK+ leads from the processor. As the AM3730 is 1.8V, the level is set to .9V by R64 and R65.

8.17.5.8 PD

The PD signal originates from the processor on the GPIO_170 pin. Because the PD signal on the TFP410 is 3.3V referenced, this signal must be converted to 3.3V. This is done by U4, SN74LVC2G07, a non-inverting open drain buffer. If the GPIO_170 pin is

HI, then the open drain signal is inactive, causing the signal to be pulled HI by R98.

When GPIO_170 is taken low, the output of U4 will also go LO, placing the TFP410 in the power down mode. Even though U4 is running at 1.8V to match the processor, the output will support being pulled up to 3.3V. On power up, the TFP410 is disabled by

R109, a 10K resistor. When the processor powers on, pin J25 comes in the safe mode, meaning it is not being driven. R109 insures that the signal is pulled LO, putting the

TFP410 in the power down mode.

8.17.5.9 TFADJ

The TFADJ signal controls the amplitude of the DVI output voltage swing, determined by the value of R95.

8.17.5.10 RSVD2

This unused pin is terminated to ground as directed by the TFP410 data manual.

8.17.5.11 NC

This unused pin is pulled HI as directed by the TFP410 data manual.

8.17.6 DVI-D Connector

In order to minimize board size, a HDMI connector was selected for the DVI-D connection. The BeagleBoard does not support HDMI but only the DVI-D component of

Page 91 of 164

REF: BB_SRM_xM BeagleBoard-xM System

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Revision A2

HDMI. The Cable is not supplied with the BeagleBoard but is available from numerous cable suppliers and is required to connect a display to the BeagleBoard.

8.17.6.1 Shield Wire

Each signal has a shield wire that is used in the cable to provide signal protection for each differential pair. This signal is tied directly to ground.

8.17.6.2 DAT0+/DAT0-

The differential signal pair DAT0+/DAT0- transmits the 8-bit blue pixel data during active video and HSYNC and VSYNC during the blanking interval.

8.17.6.3 DAT1+/DAT1-

The differential signal pair DAT1+/DAT1- transmits the 8-bit green pixel data during active video.

8.17.6.4 DAT2+/DAT2-

The differential signal pair DAT2+/DAT2- transmits the 8-bit red pixel data during active.

8.17.6.5 TXC+/TXC-

The differential signal pair TXC+/TXC- transmits the differential clock from the

TFP410.

8.17.6.6 DDC Channel

The Display Data Channel or DDC (sometimes referred to as EDID Enhanced Display

ID) is a digital connection between a computer display and the processor that allows the display specifications to be read by the processor. The standard was created by the Video

Electronics Standards Association (VESA). The current version of DDC, called DDC2B, is based on the I²C bus. The monitor contains a read-only memory (ROM) chip programmed by the manufacturer with information about the graphics modes that the monitor can display. This interface in the LCD panel is powered by the +5V pin on the connector through RT1, a resetable fuse. As the processor is 1.8V I/O, the I2C bus is level translated by U11, a TXS0102. It provides for a split rail to allow the signals to interface on both sides of the circuit. Inside of TXS0102 is a pullup on each signal, removing the need for an external resistor.

8.17.6.7 HDMI Support

Page 92 of 164

REF: BB_SRM_xM BeagleBoard-xM System

Reference Manual

Revision A2

The digital portion of the DVI-D interface is compatible with HDMI and is electrically the same. A standard HDMI cable may be used to connect to the HDMI input of monitors or televisions. Whether or not the Beagle will support those monitors is dependent on the timings that are used on the BeagleBoard and those that are accepted by the monitor. This may require a change in the software running on the Beagle. The audio and encryption features of HDMI are not supported by the BeagleBoard.

8.17.6.8 DVI to VGA

The analog portion of DVI, which provides RGB analog signals, is not supported by the

BeagleBoard. Buying a DVI to VGA adapter connector will not work on a VGA display.

You will need an active DVI-D to VGA adapter. Another option for these signals is to buy a board that connects to the J4 and J5 expansion connectors and generates the RGB signals for the VGA display.

8.18 LCD Expansion Headers

Access is provided on the -XM Rev A to allow access to the LCD signals. Table 16 shows the signals that are on the P11 connector. You will notice that the signals are not in a logical order or grouping. This is due to the routing on the PCB where we allowed the routing to take precedence to get it to route with no addition of layers to the design.

Table 16. P11 LCD Signals

Pin# Signal I/O Description

5

6

7

8

1

2

3

4

DC_5V

DC_5V

DVI_DATA1

DVI_DATA0

DVI_DATA3

DVI_DATA2

DVI_DATA5

DVI_DATA4

PWR DC rail from the Main DC supply

PWR DC rail from the Main DC supply

O LCD Pixel Data bit

O LCD Pixel Data bit

O LCD Pixel Data bit

O LCD Pixel Data bit

O LCD Pixel Data bit

O LCD Pixel Data bit

9 DVI_DATA12 O LCD Pixel Data bit

10 DVI_DATA10 O LCD Pixel Data bit

11 DVI_DATA23 O LCD Pixel Data bit

12 DVI_DATA14 O LCD Pixel Data bit

13 DVI_DATA19 O LCD Pixel Data bit

14 DVI_DATA22 O LCD Pixel Data bit

15 I2C3_SDA I/O I2C3 Data Line

16 DVI_DATA11 O LCD Pixel Data bit

17 DVI_VSYNC

18 DVI_PUP

O

O

LCD Vertical Sync Signal

Control signal for the DVI controller. When Hi,

DVI is enabled. Can be used to activate

Page 93 of 164

REF: BB_SRM_xM BeagleBoard-xM System

Reference Manual

Revision A2 circuitry on adapter board if desired.

19 GND

20 GND

The current available on the DC_5V rail is limited to the available current that remains from the DC supply that is connected to the DC power jack on the board. Keep in mind that some of that power is needed by the USB Host power rail and if more power is needed for the expansion board, the main DC power supply current capability may need to be increased. All signals are 1.8V except the DVI_PUP which is a 3.3V signal.

Table 17 shows the signals that are on connector P13.

Pin#

Table 17. P13 LCD Signals

Signal

5

6

7

8

1

2

3

4

3.3V

VIO_1V8

DVI_DATA20

DVI_DATA21

DVI_DATA17

DVI_DATA18

DVI_DATA15

DVI_DATA16

9 DVI_DATA7

10 DVI_DATA13

11 DVI_DATA8

12 NC

13 DVI_DATA9

14 I2C3_SCL

15 DVI_DATA6

16 DVI_CLK+

17 DVI_DEN

I/O Description

PWR 3.3V reference rail

PWR 1.8V buffer reference rail.

O LCD Pixel Data bit

O LCD Pixel Data bit

O LCD Pixel Data bit

O LCD Pixel Data bit

O LCD Pixel Data bit

O LCD Pixel Data bit

O LCD Pixel Data bit

O LCD Pixel Data bit

O LCD Pixel Data bit

LCD Pixel Data bit

I/O I2C3 Clock Line

O LCD Pixel Data bit

19 GND

20 GND

The 1.8V rail is for level translation only and should not be used to power circuitry on the board. The 3.3V rail also has limited capacity on the power as well. If the TFP410 is disabled on the Beagle, then 80mA is freed up for use on an adapter card connected to the

LCD signals connectors. It is not required that the TFP410 be disabled when running an adapter card, but the power should be taken into consideration when making this decision.

It is suggested that the 5V rail be used to generate the required voltages for an adapter card.

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REF: BB_SRM_xM BeagleBoard-xM System

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Revision A2

8.19 S-Video

A single S-Video port is provided on the BeagleBoard. Figure 45 is the design of the S-

Video interface.

L2

C10

47pF

1

L3

2

3.3uH

C11

47pF

1 2

3.3uH

P4

P1

P2

P3

P4

5

6

7

1

2

3

4

MH1

MH2

MH3

CONN_SVideo

R32

R33

R34

1.65K,1%

1.65K,1%

0,DNI

C9

0.1uF,10V

W28

Y28

Y27

W27

W26

Processor

TV_OUT2

TV_OUT1

TV_VFB1

TV_VFB2

TV_VREF

U4B

Figure 45. S-Video Interface

Table 18 is the list of the signals on the S-Video interface and their definitions.

Table 18. S-Video Interface Signals

Signal I/O tv_out1

Description

O TV analog output composite tv_out2 O TV analog output S-VIDEO tv_vref tv_vfb1

I Reference output voltage from internal bandgap

O Amplifier feedback node tv_vfb2 O Amplifier feedback node

Power to the internal DAC is supplied by the TPS65950 via the VDAC_1V8 rail. Figure

37 reflects the filtering that is used on these rails, including the input VBAT rail.

A 47pf CAP and 3.3uh inductor are across the feedback resistors to improve the quality of the S-Video signal.

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8.20 Camera Port

A new addition to the –xM is the camera port. This camera port is the native camera interface of the processor. The connector configuration is designed to be compatible with the camera modules from Leopard Imaging. USB cameras may also be used if desired, but this interface has many HW assisted features and can support camera modules from

VGA to 5MP resolutions. Figure 46 is the Camera interface design.

OMAP3730_ES1.0

U4B

I2C2_SDA

I2C2_SCL

CAM_XCLKA

CAM_WEN

CAM_FLD

CAM_D11

CAM_D10

CAM_D9

CAM_D8

CAM_D7

CAM_D6

CAM_D5

CAM_D4

CAM_D3

CAM_D2

CAM_D1

CAM_D0

CAM_PCLK

CAM_HS

CAM_VS

I2C1_SDA

I2C1_SCL

AE15

AF15

C27

A24

A23

J21

K21

C25

B23

C23

C26

B25

L27

K27

L28

K28

A25

D24

C24

B24

AH17

AG17

VIO_1V8

CAM_CLKA

CAM_D11

CAM_D10

CAM_D9

CAM_D8

CAM_D7

CAM_D6

CAM_D5

CAM_D4

CAM_D3

CAM_D2

CAM_D1

CAM_D0

CAM_FLD

P10

9

11

5

7

13

15

1

3

27

29

31

33

17

19

21

23

25

2

4

6

8

10

12

14

16

28

30

32

34

18

20

22

24

26

CAM_ANA

CAM_DIGITAL

D4

D5

F618-MG -D051-XX-CF358

U7B TPS65950

I2C.CNTL.SDA

I2C.CNTL.SCL

VAUX4.OUT

VAUX3.OUT

B3

G16

LEDA

F15

CAM_WEN

I2C2_SDA

I2C2_SCL

CMOS_OE

CAM_IO

R83 0,0603

R154

R151

C128

1uF,10V

C213

1uF,10V

VIO_1V8

DNI,0

0

R155

10K

DC_5V

DC_5V_USB

2

1

3

U16

IN OUT

SHDN GND

GND ADJ

TL1963A

4

6

5 U16_FB R111

56.2K,1%

R113

32.4K,1%

HUB_3V3

C177

4.7uF,6.3V,0603

Figure 46. Camera Port Interface

The design of the camera interface is described in more detail in the remainder of this section.

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8.20.1 Camera Power

There are three main power sources required by the camera module. Each of these are described in the following sections.

8.20.1.1 CAM_ANA Power

The DC input can be either 5V or 3.3V. It is selected by installing either R151 or R154.

The default is set at 3.3V and is controlled by turning on and off the USB HUB power rail at U16. The power is controlled by setting the LEDA signal on the TPS65950.

Access to this register is via the I2C2 interface on the processor.

The 5V is on whenever a power source is applied o the board.

8.20.1.2 CAM_DIGITAL Power

The digital power is a 1.8V rail that is supplied by the TPS65950. The power is controlled via the I2C1 interface from the processor by setting the VAUX4 regulator to

1.8V. This is used for the internal logic in the camera module.

8.20.1.3 CAM_IO Power

The I/O power is a 1.8V rail that is supplied by the TPS65950. The power is controlled via the I2C1 interface from the processor by setting the VAUX3 regulator to 1.8V. This will set the level of all of the interface signals to the processor.

8.20.2 Camera I2C Port

The processor uses the I2C2 port to communicate to the camera module to set the registers in the device. There are no pullups on the board for the I2C to prevent conflict with add on boards that do have the pullups. If an add-on board is not used, the SW will need to enable the internal pullups on the I2C2 signals in order for the interface to work.

8.20.3 Processor Camera Port Interface

Table 19 shows the signals that are the interface between the processor and the camera modules. The I/O status of each pin is defined from the perspective of the processor.

The cam_wen signal is labeled as CMOS_OE on the schematic. All of the current camera modules do not use this signal and this signal has no affect on the operation of the camera modules. It is provided for future use.

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Signal

Table 19. Camera Interface Signals

Function Description cam_vs VS Camera Vertical Synchronization cam_xclka Clock Camera Clock Output cam_d0 Camera Data Camera image data bit 0

Data Camera image data bit 1

Data Camera image data bit 2

Data Camera image data bit 3

Data Camera image data bit 4

Data Camera image data bit 5

Data Camera image data bit 6

Data Camera image data bit 7

Data Camera image data bit 8

Data Camera image data bit 9

Data Camera image data bit 10

Data Camera image data bit 11

Revision A2

I/O Processor

I/O

I

I

I

I

I

I

I

I

I

I/O

O

I

I

I

A24 cam_pclk Pixel Clock Camera pixel clock I C27 cam_wen Camera Write Enable I B23

The cam_fld signal is used as a RESET signal to the camera board. When used as a reset, the pin should be set up as a GPIO pin.

Table 20 shows the mapping of the pins on the camera sensors to the pins on the processor. In order to work with the different modules, you must take into account the order of the bits. The table covers the currently available camera modules that are compatible with the Beagle –xM. You will notice some of the lettering in red. These are signals that are not used by the camera module. In order for the data to be correct, these signals need to be tied low by enabling the internal pulldown resistors.

C25

AG17

AH17

B24

C24

D24

A25

K28

L28

K27

L27

B25

C26

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Table 20. Camera Pin Signal Mapping

28

29

30

31

24

25

26

27

32

33

17

18

19

20

21

22

23

12

13

14

15

16

8

9

10

11

4

5

2

3

6

7

Resolution VGA 1.3MP 2MP 3MP 5MP

Camera Module Part Number LI-LBCMVGA LI-LBCM1M1 LI-LBCM2M1 LI-BCM3M1 LI-LBCM5M1

Data Width---> 10 10 10 8 12

PIN

1

NAME

D11

I/O/V

MCLK

D10

GND

D9

SDATA

D8

SCLK

D7

RESET

D6

OE

D5

GND

D4

CAM_IO

D3

CAM_IO

D2

GND

D1

I D1

I D0

D1

D0

D1

D0

D3

D2

I PULL-DOWN PULL-DOWN PULL-DOWN PULL-DOWN D1

GND

D0 I PULL-DOWN PULL-DOWN PULL-DOWN PULL-DOWN D0

CAM_ANA PWR

CAM_ANA PWR

CAM_ANA PWR

PCLK

GND

HS

CAM_DIG

VS

CAM_DIG

GND

34 GND

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8.20.4 Camera Modules

The camera module can be purchased from Leopard Imaging or one of their distributors.

It uses the same modules as the LeopardBoard DM355 version. The figure below shows the different modules that can be used. The part numbers can be found in Table 20.

Figure 47. Camera Modules

At this time, only the VGA camera board has been confirmed to work on the –xM board.

Other boards will be added as the SW drivers are completed. The 3MP module is next on the list. It is expected that all of the listed modules will work and no complications are expected as they are all compatible at the hardware level.

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8.21 RS232 Port

A single RS232 port is provided on the BeagleBoard and provides access to the TX and

RX lines of UART3 on the processor. Figure 48 shows the design of the RS232 port.

AUX_3V3

C146 0.1uF,10V

C147 0.1uF,10V

VIO_1V8

3

3

UART3_TX

UART3_RX

R81 10K

232OE

4

6

3

5

U10

VCCA

A1

A2

OE

VCCB

B1

B2

GND

TXS0102DCU

1

2

7

8 UART3_TX_3V

UART3_RX_3V

U9

C148

0.1uF,10V 232_C14

232_C2+ 5

C150

232_C1+ 2

0.1uF,10V 232_C26

11

9

C1+

C1-

C2+

C2-

DIN

ROUT

1

12

EN

FORCEON

SN65C3221EPW

AUX_3V3

C143

0.1uF,10V

V-

7

V+

3

232_V-

232_V+

DOUT

RIN

13

8

INVALID

FORCEOFF

10

16

RS232_TX1

RS232_RX1

C151

0.1uF,10V

R78

R79

R80

R82

C149

0.1uF,10V

0

0,DNI

0,DNI

0

232_PIN2

232_PIN3

P8

7

8

5

6

9

3

4

1

2

7

8

5

6

9

3

4

1

2

SHL1

SHL2

10

11

DSUB_FEMALE_SHORT

Figure 48. RS232 Interface Design

8.21.1 Processor Interface

Two lines, UART3_Tx and UART3_Rx, are provided by the processor. The UART3 function contains a programmable baud generator and a set of fixed dividers that divide the 48-MHz clock input down to the expected baud rate and also supports auto bauding.

8.21.2 Level Translator

All of the I/O levels from the processor are 1.8V while the transceiver used runs at 3.3V.

This requires that the voltage levels be translated. This is accomplished by the TXS0102 which is a two-bit noninverting translator that uses two separate configurable powersupply rails. The A port tracks VCCA, 1.8V and the B port tracks VCCB, 3.3V. This allows for low-voltage bidirectional translation between the two voltage nodes. When the output-enable (OE) input is low, all outputs are placed in the high-impedance state. In this design, the OE is tied high via a 10K ohm resistor to insure that it is always on.

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8.21.3 RS232 Transceiver

The RS232 transceiver used is the SN65C322 which consists of one line driver, one line receiver, and a dual charge-pump circuit with ±15-kV IEC ESD protection pin to pin

(serial-port connection pins, including GND). These devices provide the electrical interface between an asynchronous communication controller and the serial-port connector. The charge pump and four small external capacitors allow operation from a single 3-V to 5.5-V supply. The SN65C3221 operates at data signaling rates up to 1

Mbit/s and a driver output slew rate of 24 V/ms to 150 V/ms. While the processor can easily drive a 1Mbit/S rate, your results may vary based on cabling, distance, and the loads and drive capability on the other end of the RS232 port.

The transceiver is powered from the 3.3V rail and is active at power up. This allows the port to be used for UART based peripheral booting over the port.

8.21.4 Connector

Access to the RS232 port is through a 9 pin DB9 connector, P9. This is new on the –xM version and replaces the 10 pin header. A standard male to female straight DB9 cable can be used or a USB to DB9 adapter can be plugged direct into the board.

8.22 Indicators

There are five green indicators on the BeagleBoard: o

Power o

PMU_STAT o

USER0 o

USER1 o

HUB Power

All of the green LEDs are programmable under software control. Figure 49 shows the connection of all of these indicators.

There is also a single RED LED on the board. Turning on this LED is not something that a person should try to do as it indicates that the user is not paying attention and has plugged in a potentially damaging power supply into the power jack.

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VBAT

LTST-C190GKT

GRN

D12

U4B Processor

GPIO_149

GPIO_150

AA9

W8

2

DC_5V_USB

R64

2

1

3

U16

IN

SHDN

OUT

4

GND

GND ADJ

TL1963A

6

5

330 G15

F15

U7A TPS65950

LEDB/VIBRA.M

LEDA/VIBRA.P

F16

N12

LEDGND

GPIO.1

U16_FB R111

R113

56.2K,1%

32.4K,1% D14

HUB_3V3

R136

330

C177

4.7uF,6.3V,0603

USB ACTIVE

LTST-C190GKT

D13

LTST-C150CKT

VBAT

R8

R39

Q1A

RN1907

LTST-C190GKT

GRN

330 D6

USER0

R40

VBAT

GRN

330

USER1

VBAT

D7

LTST-C190GKT

5

Q1B

RN1907

1

U18A

VIO_1V8

10K

6

SN74LVC2G06DCKR

DC_IN

4

U2

LDO_IN

6

LDO_EN

3

2

SW_IN

SW_IN

5

SW_EN

TPS2141PWP

DC_IN

4

5

U19

VDD

SENSE RSET

3

R130

10K

2

R121

510

Q2A

RN1907

VOLT_ERR

LDO_PLDN

LDO_OUT

ADJ

LDO_PG

10

11

9

8

AUX_3V3

R12

D5

LTST-C190GKT

POWER

SW_OUT

SW_OUT

SW_PLDN

SW_PG

13

12

14

1

330

2

GND NC

TPS3803G15

1

Figure 49. Indicator Design

8.22.1 Power Indicator

This indicator, D5, connects from the 3.3V rail supply and ground. It indicates that the entire power path is supplying the power to the board. Indicator D5 does not indicate which power source is being used to supply the main power to the board but only that it is active. Software does have the ability to turn off this regulator and thereby turning off the

LED. By default this is always disabled on power up.

8.22.2 PMU Status Indicator

This output is driven from the TPS65950 using the LED.B output. The TPS65950 provides LED driver circuitry to power two LED circuits that can provide user indicators.

The first circuit can provide up to 160 mA and the second, 50 mA. Each LED circuit is independently controllable for basic power (on/off) control and illumination level (using

PWM). The second driver, LED.B, is used to drive an LED that is connected to the

VBAT rail through a resistor.

The PWM inside the TPS65950 can be used to alter the brightness of the LED if desired or it can be turned on or off by the processor using the I2C bus. The PWM is programmable, register-controlled, duty cycle based on a nominal 4-Hz cycle which is

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Revision A2 derived from an internal 32-kHz clock. It is possible to set the LED to flash automatically without software control if desired.

8.22.3 User Indicators

There are two user LEDs, D6 and D7, that can be driven directly from a GPIO pin on the processor. These can be used for any purpose by the software. The output level of the processor is 1.8V and the current sink capability is not enough to drive an LED with any level of brightness. A transistor pair, RN1907 is used to drive the LEDs from the VBAT rail. A logic level of 1 will turn the LED on.

8.22.4 HUB Power Indicator

The HUB power LED, D14, is turned on whenever the USB HUB power is active. This output is driven from the TPS65950 using the LED.A output. The processor can control the LED by communicating via the I2C to the TPS65950.

8.22.5 Overvoltage Indicators

The Over Voltage LED, D13, turns on whenever the DC voltage exceeds 5.3V. The detection circuit, TPS3803, turns on the LED.

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8.23 JTAG

A JTAG header is provided to allow for advanced debugging on the BeagleBoard by using a JTAG based debugger. Figure 50 shows the interconnection to the processor.

VIO_1V8

VIO_1V8

8

10

12

14

2

4

P3

2

4

8

10

12

14

HDR 2x7

1

11

13

7

9

3

5

5

7

1

3

9

11

13

C8

0.1uF,10V

JTAG_TMS

JTAG_TDI

JTAG_TDO

JTAG_RTCK

JTAG_TCK

JTAG_EMU0

R31

10K

JTAG_nTRST

AA19

AA17

AA18

AA20

AA13

AA12

AA11

AA10

Processor

JTAG_TDO

JTAG_nTRST

JTAG_TMS

JTAG_TDI

JTAG_TCK

JTAG_RTCK

JTAG_EMU0

JTAG_EMU1

U4B

Figure 50. JTAG Interface

8.23.1 Processor Interface

The JTAG interface connects directly to the OMAP processor. All signals are a 1.8V level. Table 21 describes the signals on the JTAG connector.

Table 21. JTAG Signals

Signal Description

JTAG_TMS

JTAG_TDI

Test mode select

Test data input

JTAG_TDO Test Data Output

JTAG_RTCK ARM Clock Emulation

JTAG_EMU0 Test emulation 0

JTAG_EMU1 Test emulation 1

I/O

I/O

I

O

O

I

I

I/O

I/O

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8.23.2 JTAG Connector

The JTAG interface uses a 14 pin connector. All JTAG emulator modules should be able to support this interface. Contact your emulator supplier for further information or if an adapter is needed.

8.24 Main Expansion Header

The expansion header is provided to allow a limited number of functions to be added to the BeagleBoard via the addition of a daughtercard.

Figure 51 is the design of the expansion connector and the interfaces to the processor.

DC_5V J3 VIO_1V8

Processor U3B

McBSP3_DX

McBSP3_CLKX

McBSP3_FSX

McBSP3_DR

McBSP1_DX

McBSP1_CLKX

McBSP1_FSX

McBSP1_DR

McBSP1_CLKR

McBSP1_FSR

I2C2_SCL

I2C2_SDA

AB26

AA25

AE5

AE6

V21

W21

K26

U21

Y21

AA21

AF15

AE15

UART2_CTS

MCBSP3_CLKX

MCBSP3_FSX

MCBSP3_DR

MCBSP1_DX

MCBSP1_CLKX

MCBSP1_FSX

MCBSP1_DR

MCBSP1_CLKR

MCBSP1_FSR

I2C2_SCL nRESET

10

12

14

16

18

2

4

6

8

20

22

24

26

28

9

11

13

15

17

1

3

5

7

19

21

23

25

27

MMC2_DAT7

MMC2_DAT6

MMC2_DAT5

MMC2_DAT4

MMC2_DAT3

MMC2_DAT2

MMC2_DAT1

MMC2_DAT0

MMC2_CMD

MMC2_CLKO

I2C2_SDA nUSB_DC_EN

AE3

AF3

AH3

AE4

AF4

AG4

AH4

AH5

AG5

AE2

U3A

Processor

MMC2_DAT7

MMC2_DAT6

MMC2_DAT5

MMC2_DAT4

MMC2_DAT3

MMC2_DAT2

MMC2_DAT1

MMC2_DAT0

MMC2_CMD

MMC2_CLK

To the Reset circuitry To the power circuitry

HEADER 14X2

Figure 51. Main Expansion Header Processor Connections

CAUTION: The voltage levels on the expansion header are 1.8V. Exposure of these signals to a higher voltage will result in damage to the board and a voiding of the warranty.

8.24.1 Processor Interface

The main purpose of the expansion connector is to route additional signals from the processor. Table 22 shows all of the signals that are on the expansion header. As the processor has a multiplexing feature, multiple signals can be connected to certain pins to add additional options as it pertains to the signal available. Each pin can be set individually for a different mux mode. This allows any of the listed mux modes to be set on a pin by pin basis by writing to the pin mux register in software. Following is the legend for Table 22.

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X

= there is no signal connected when this mode is selected

Z

= this is the safe mode meaning neither input to output. This is the default mode on power up.

*

= this indicates that there is a signal connected when this mode is selected, but it has no useful purpose without other pins being available. Access to these other pins is not provided on the expansion connector.

The first column is the pin number of the expansion connector.

The second column is the pin number of the processor.

The columns labeled 0-7 represent each of the pin mux modes for that pin. By setting this value in the control register, this signal will be routed to the corresponding pin of the expansion connector. These setting are on a pin by pin basis. Any pin can be set with the mux register setting, and the applicable signal will be routed to the pin on the expansion connector.

Table 22. Expansion Connector Signals

EXP Processor

1

2

3

0

AE3 MMC2_DAT7

1

*

2

*

3 4 5 6 7

VIO_1V8

DC_5V

4

5

6

7

8

9

10

AF3 MMC2_DAT6

AA25

AH3 MMC2_DAT5

AB25

*

*

AE5 McBSP3_FSX UART2_RX

AE4 MMC2_DAT4 *

AF4 MMC2_DAT3 McSPI3_CS0

*

*

X

X

X 11

12

13

14

15

16

AG4 MMC2_DAT2 McSPI3_CS1

W21 McBSP1_CLK

X

AH4 MMC2_DAT1 X

X

X

AH5 MMC2_DAT0 McSPI3_SOMI X 17

18

19

20

AG5 MMC2_CMD McSPI3_SIMO

Y21 McBSP1_CLK

R

AE2 MMC2_CLKO McSPI3_CLK

X

21

22

23

24

AA21 McBSP1_FSR

AE15 I2C2_SDA

AF15 I2C2_SCL

X

X

X

X

*

X

X X X Z

25

26

27

28

25 REGEN

26 Nreset

27 GND

28 GND

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8.24.2 Expansion Signals

This section provides more detail on each of the signals available on the expansion connector. They are grouped by functions in Table 23 along with a description of each signal and the MUX setting to activate the pin. If you use these signals in their respective groups and that is the only function you use, all of the signals are available. Whether or not the signals you need are all available, depends on the muxing function on a per-pin basis. Only one signal per pin is available at any one time.

Table 23. Expansion Connector Signal Groups

GPIO_130

GPIO_131

GPIO_132

GPIO_133

GPIO_134

GPIO_135

GPIO_136

GPIO_137

GPIO_138

GPIO_139

GPIO_143

GPIO_144

GPIO_145

GPIO_146

GPIO_156

GPIO_158

GPIO_159

GPIO_161

GPIO_162

Signal Description

SD/MMC Port 2

I/O EXP OMAP Mux

MMC2_DAT7

MMC2_DAT6

MMC2_DAT5

MMC2_DAT4

MMC2_DAT3

MMC2_DAT2

MMC2_DAT1

MMC2_DAT0

SD/MMC data pin 7.

SD/MMC data pin 6.

SD/MMC data pin 5.

SD/MMC data pin 4.

SD/MMC data pin 3.

SD/MMC data pin 2.

SD/MMC data pin 1.

SD/MMC data pin 0.

I/O

I/O

I/O

I/O

I/O 11

I/O 13

I/O 15

I/O 17

3

5

7

9

AE3

AF3

AH3

AE4

AF4

AG4

AH4

AH5

MMC2_CMD

MMC_CLKO

SD/MMC command signal.

SD/MMC clock signal.

McBSP Port 1

Multi channel buffered serial port receive

I/O

O

19

21

AG5

AE2

1

1

McBSP1_DR I 18

McBSP1_CLKS -------------------------------------------------------------------------- N/A N/A

McBSP1_FSR Multi channel buffered serial port transmit frame sync RCV I/O 22

McBSP1_DX Multi channel buffered serial port transmit

McBSP1_CLKX Multi channel buffered serial port transmit clock

McBSP1_FSX Multi channel buffered serial port transmit frame sync XMT I/O 16

McBSP1_CLKR Multi channel buffered serial port receive clock I/O 20

I2C Port 2

I/O 12

I/O 14

I2C2_SDA

I2C2_SCL

I2C data line.

I2C clock line

IOD 23

IOD 24

McBSP Port 3

McBSP3_DR

McBSP3_DX

Multi channel buffered serial port receive

Multi channel buffered serial port transmit

McBSP3_CLKX Multi channel buffered serial port receive clock

McBSP3_FSX Multi channel buffered serial port frame sync transmit

I 10,18

I/O 4,12

I/O 6,14

I/O 8,16

1

1

1

1

1

1

1

1

General Purpose I/O Pins

GP Input/Output pin. Can be used as an interrupt pin.

GP Input/Output pin. Can be used as an interrupt pin.

GP Input/Output pin. Can be used as an interrupt pin.

GP Input/Output pin. Can be used as an interrupt pin.

GP Input/Output pin. Can be used as an interrupt pin.

GP Input/Output pin. Can be used as an interrupt pin.

GP Input/Output pin. Can be used as an interrupt pin.

GP Input/Output pin. Can be used as an interrupt pin.

GP Input/Output pin. Can be used as an interrupt pin.

GP Input/Output pin. Can be used as an interrupt pin.

GP Input/Output pin. Can be used as an interrupt pin.

GP Input/Output pin. Can be used as an interrupt pin.

GP Input/Output pin. Can be used as an interrupt pin.

GP Input/Output pin. Can be used as an interrupt pin.

GP Input/Output pin. Can be used as an interrupt pin.

GP Input/Output pin. Can be used as an interrupt pin.

GP Input/Output pin. Can be used as an interrupt pin.

GP Input/Output pin. Can be used as an interrupt pin.

GP Input/Output pin. Can be used as an interrupt pin.

I/O 21

I/O 19

I/O 17

I/O 15

I/O 13

I/O 11

I/O

I/O

I/O

I/O

I/O

I/O

9

7

5

3

8

4

I/O 10

I/O 6

I/O 20

I/O 12

I/O 18

I/O 16

I/O 14

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GPIO_168

GPIO_183

GP Input/Output pin. Can be used as an interrupt pin.

GP Input/Output pin. Can be used as an interrupt pin.

McSPI Port 3

McSPI3_CS0

McSPI3_CS1

Multi channel SPI chip select 0

Multi channel SPI chip select 1

McSPI3_SIMO Multi channel SPI slave in master out

McSPI3_SOMI Multi channel SPI slave out master in

McSPI3_CLK Multi channel SPI clock

McSPI Port 4

McSPI4_SIMO Multi channel SPI slave in master out

McSPI4_SOMI Multi channel SPI slave out master in

McSPI4_CS0 Multi channel SPI chip select 0

McSPI4_CLK Multi channel SPI clock

UART Port 2

UART2_CTS

UART2_RTS

UART clear to send.

UART request to send

I/O 24

I/O 23

O

O

11

13

I/O 19

I/O 17

I/O 21

I/O 12

I/)

O

18

16

I/O 20

GPT PWM

GPT9_PWMEVT PWM or event for GP timer 9

I/O

O

4

10

I 8

O 6

O 4

GPT11_PWMEVT PWM or event for GP timer 11 O 10

GPT10_PWMEVT PWM or event for GP timer 10 O 8

8.24.3 Power

The expansion connector provides two power rails. The first is the VIO_1.8V rail which is supplied by the TPS65950. This rail is limited in the current it can supply from the

TPS65950 and what remains from the current consumed by the BeagleBoard and is intended to be used to provide a rail for voltage level conversion only. It is not intended to power a lot of circuitry on the expansion board. All signals from the BeagleBoard are at 1.8V.

The other rail is the DC_5V. The same restriction exits on this rail as mentioned in the

USB section. The amount of available power to an expansion board depends on the available power from the DC supply or the USB supply from the PC.

8.24.4 Reset

The nRESET signal is the main board reset signal. When the board powers up, this signal will act as an input to reset circuitry on the expansion board. After power up, a system reset can be generated by the expansion board by taking this signal low. This signal is a 1.8V level signal.

8.24.5 Power Control

There is an additional open-drain signal on the connector called REGEN. The purpose of this signal is to provide a means to control power circuitry on the expansion card to turn on and off the voltages. This insures that the power on the expansion board is turned on at the appropriate time. Depending on what circuitry is provided on the expansion board, an

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Revision A2 additional delay may be needed to be added before the circuitry is activated. Refer to the processor and TPS65950 documentation for more information.

8.25 LCD Expansion Header

If you choose not to use the LCD headers for access to the LCD signals or for the DVI-D interface, they can also be used for other functions on the board based on the pin mux setting of each pin. Table 24 shows the options for P11 and Table 25 shows the options for P135. The MUX: column indicates which MUX mode must be set for each pin to make the respective signals accessible on the pins of the processor.

Table 24. P11 GPIO Signals

Pin# Signal MUX:0 MUX:2 MUX:4

3 DVI_DATA1 DATA1 UART1_RTS GPIO71

4 DVI_DATA0 DATA0 UART1_CTS GPIO70

5 DVI_DATA3 DATA3

6 DVI_DATA2 DATA2

-

-

GPIO73

GPIO72

7 DVI_DATA5 DATA5 UART3_TX GPIO75

8 DVI_DATA4 DATA4 UART3_RX GPIO74

9 DVI_DATA12 DATA12

10 DVI_DATA10 DATA10 -

GPIO82

GPIO79

11 DVI_DATA23 DATA23

12 DVI_DATA14 DATA14

-

-

GPIO93

GPIO84

13 DVI_DATA19 DATA19 McSPI3_SIMO GPIO89

14 DVI_DATA22 DATA22 McSPI3_CS1 GPIO92

15 I2C3_SDA I2C3_SDA

16 DVI_DATA11 DATA11

17 DVI_VSYNC VSYNC

18 DVI_PUP DVI_PUP

-

-

-

-

-

GPIO81

GPIO68

-

Table 25. P13 GPIO Signals

Pin# Signal MUX:0 MUX:2 MUX:4

3 DVI_DATA20 DATA20 McSPI3_SOMI GPIO90

- GPIO87

-

-

GPIO85

GPIO86

9 DVI_DATA7 DATA7 UART1_RX GPIO77

10 DVI_DATA13 DATA13 - GPIO83

11 DVI_DATA8 DATA8

12 NC -

13 DVI_DATA9 DATA9

14 I2C3_SCL I2C3_SCL

-

-

-

GPIO78

-

GPIO79

-

15 DVI_DATA6 DATA6 UART1_TX GPIO_76

16 DVI_CLK+ PCLK - GPIO66

17 DVI_DEN DEN

18 DVI_HSYNC HSYNC

-

-

GPIO69

GPIO67

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8.26 Auxiliary Expansion Header

New to the –xM version is the addition of expansion header called the Auxiliary

Expansion Header. As is the case with many of the signals on the various connectors, these pins have multiple functions mapped per pin. Table 26 below is the pin out of the

MMC Connector. In order to access other signals on these pins, the pin muxing register will need to be set as needed on a per pin basis.

Table 26. P13 Auxiliary Expansion Signals

PIN

1

2

3

4

5

6

SIGNAL PROC 0 1 2 3 4 5

VIO_1V8

VMMC2

MMC3_DAT2 AF13 ETK_D6 MCBSP5_DX MMC3_DAT2

MMC3_DAT7 AH14 ETK_D7 MCSPI3_CS1 MMC3_DAT7 MM1_TXEN_N

7

8

9

MMC3_DAT3 AE13 ETK_D3 MCSPI3_CLK MMC3_DAT3 HSUSB_D7 GPIO_17

GPIO_16 AH12 ETK_D2 MCSPI3_CS0 HSUSB1_D2 GPIO_16 MM1_TXDAT

GPIO_15

MMC3_DAT1

MMC3_DAT5

AG12 ETK_D1 MCBSPI3_SOMI

AH9 ETK_D5 MCBSP5_FSX

AG9 ETK_D9 SERCURE_IND

HSUSB1_D1 GPIO_15 MM1_TXSE0

10 MMC3_DAT4 AF11 ETK_D0 MCSPI3_SIMO HSUSB1_D0 GPIO_14 MM1_RXRCV

11 MMC3_DAT0 AE11 ETK_D4 MCBSP5_DR MMC3_DAT0

12 MMC3_CMD AE10 ETK_CTL

13 MMC3_DAT6 AF9 ETK_D8 DRM_SECURE

14 MMC3_CLK AF10- ETK_CLK MCBSP5_CLKX MMC3_CLK HSUSB1_STP GPIO_12 MM1_RXDP

J25 HDQ SYS_ALTCLK GPIO_170 15

16

17

HDQ

DMAREQ3

AUX_DC

18

19

PWR_CNTRL

AUX_ADC

PWR_CNTRL

GND

20 GND

The following sections provide a brief description of the functions of the pins available.

For a more complete description, please refer to the datasheet or Technical Reference

Manuals. Not all of these signals can be used at the same time. Only one signal can be used per pin at one time based on the setting of the pin mux registers in the processor.

Make sure that you set the correct mux mode when using these signals for their various configurations.

8.26.1 MCBSP5 Signals

Access to McBSP5 is provided as an option on the connector. Table 27 below shows the pins that the McBSP5 interface appears on. In order to se these signals, the mux mode for each pin must be set to 1.

PIN

3

8

11

14

Table 27. P13 McBSP5 Expansion Signals

SIGNAL I/O DESCRIPTION

Data

MCBSP5_FSX O

MCBSP5_DR I Received

MCBSP5_CLKX O

PROC PINS

AF13

AH9

AE11

AF10-

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8.26.2 MMC3 Signals

These signals can be used to provide an additional SD/MMC interface on an expansion board. All of these signals are 1.8V, so if you plan to use the signals as an SD/MMC interface, then a level shifter will be required. In order to access these signals, they must be in Mux mode 2. Table 28 is a description of these signals.

Table 28. P13 MMC3 Expansion Signals

PIN

3

4

5

8

9

10

11

12

13

14

SIGNAL

MMC3_DAT2

MMC3_DAT7

MMC3_DAT3

MMC3_DAT1

MMC3_DAT5

MMC3_DAT4

MMC3_DAT0

MMC3_CMD

MMC3_DAT6

MMC3_CLK

I/O

I/O

I/O

I/O

I/O

I/O

I/O

I/O

O

I/O

O

PROC

AF13

AH14

AE13

AH9

AG9

AF11

AE11

AE10

AF9

AF10-

DESCRIPTION

Bidirectional data pin.

Bidirectional data pin.

Bidirectional data pin.

Bidirectional data pin.

Bidirectional data pin.

Bidirectional data pin.

Bidirectional data pin.

Command indicator signal

Bidirectional data pin.

Clock

This interface could also be used to communicate to an FPGA or a WLAN device that uses the SDIO style interface.

8.26.3 ETK Signals

The ETK signals can be used to provide additional debugging information. For more information on the use of these signals, please refer to the processor Technical reference

Manual. Table 29 has the signals for the ETK interface that are provided.

6

7

8

9

PIN

3

4

5

10

11

12

13

14

Table 29. P13 Auxiliary ETK Signals

SIGNAL I/O

ETK_D6 O

ETK_D7

ETK_D3

O

O

ETK_D2

ETK_D1

ETK_D5

ETK_D9

O

O

O

O

ETK_D0

ETK_D4

O

O

ETK_CTL O

ETK_D8 O

ETK_CLK O

PROC

AF13

AH14

AE13

AH12

AG12

AH9

AG9

AF11

AE11

AE10

AF9

DESCRIPTION

Trace data pin.

Trace data pin.

Trace data pin.

Trace data pin.

Trace data pin.

Trace data pin.

Trace data pin.

Trace data pin.

Trace data pin.

Trace control signal.

Trace data pin.

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8.26.4 HSUSB1 Signals

These signals are the other High Speed USB port found on the processor. It is the same interface that is used to communicate to the UBS PHY on the board, but a different port.

Table 30 gives the signals that are used for this interface. In order for these pins to be used, the pin mux must be set to Mode 3.

Table 30. P13 High Speed USB Expansion Signals

6

7

8

9

PIN

3

4

5

10

11

12

13

14

SIGNAL

HSUSB1_D6

HSUSB1_D3

HSUSB_D7

HSUSB1_D2

HSUSB1_D1

HSUSB1_D5

HSUSB1_NXT

HSUSB1_D0

HSUSB1_D4

HSUSB1_CLK

HSUSB1_DIR

HSUSB1_STP

I/0 PROC

I/O AF13

I/O AH14

I/O AE13

I/O AH12

I/O AG12

I/O

I

AH9

AG9

I/O AF11

I/O AE11

O

I

O

AE10

AF9

AF10-

DESCRIPTION

Bidirectional Data

Bidirectional Data

Bidirectional Data

Bidirectional Data

Bidirectional Data

Bidirectional Data

Next signal

Bidirectional Data

Bidirectional Data

60MHZ Clock output

Data direction signal

Stop signal

8.26.5 Alternate Clock

The SYS_ALTCLK signal can be used to provide an alternate system clock into the processor. This can be used for things such as the GPTIMERS, USB, or as a clock for the

NTSC/PAL S-Video output.

8.26.6 HDQ 1-Wire

The HDQ/1-Wire module implements the hardware protocol of the master functions of the Benchmarq HDQ and the Dallas Semiconductor 1-Wire® protocols. These protocols use a single wire for communication between the master (HDQ/1-Wire controller) and the slaves (HDQ/1-Wire external compliant devices).

8.26.7 ADC

There is one A to D converter pin provided on the Auxiliary Expansion Header. This pin is labeled AUX_ADC and connects to the ADCIN6 pin of the TPS65950 and can be controlled and read by the processor using the I2C1 interface. There are voltage level restrictions to this pin, so refer to the TPS65950 documentation before using this pin.

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8.26.8 GPIO Signals

Most of the signals can also be configured as either inputs or outputs from the processor.

Table 31 shows the GPIO pin options that can be used on each pin of the connector.

Table 31. P13 Auxiliary GPIO Signals

PIN SIGNAL I/O

3 GPIO_20 I/O

4 GPIO_21 I/O

5 GPIO_17 I/O

6 GPIO_16 I/O

7 GPIO_15 I/O

8 GPIO_19 I/O

9 GPIO_23 I/O

10 GPIO_14 I/O

11 GPIO_18 I/O

12

13

16

GPIO_13

GPIO_22

I/O

I/O

14 GPIO_12 I/O

15 GPIO_170 I/O

GPIO_57 I/O

PROC

AF13

AH14

AE13

AH12

AG12

AH9

AG9

AF11

AE11

AE10

AF9

AF10-

J25

P8

DESCRIPTION

General Purpose Input/Output

General Purpose Input/Output

General Purpose Input/Output

General Purpose Input/Output

General Purpose Input/Output

General Purpose Input/Output

General Purpose Input/Output

General Purpose Input/Output

General Purpose Input/Output

General Purpose Input/Output

General Purpose Input/Output

General Purpose Input/Output

General Purpose Input/Output

General Purpose Input/Output

8.26.9 DMAREQ

Pin 16 of the expansion connector can also be configured for a DMAREQ pin. Refer to the processor Technical Reference Manual for more information on how to use this signal.

8.27 Audio Expansion Header

Also new to the –xM is the addition of the Audio Header that provides access to the

McBSP2 bus that connects to the TPS65950. This is the primary audio bus for the processor. For further information on these signals, refer to Section 8.16.2

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9.0 Connector Pinouts and Cables

This section provides a definition of the pinouts and cables to be used with all of the connectors and headers on the BeagleBoard.

THERE ARE NO CABLES SUPPLIED WITH THE BEAGLEBOARD.

9.1 Power Connector

Figure 52 is a picture of the BeagleBoard power connector with the pins identified. The supply must have a 2.1mm center hot connector with a 5.5mm outside diameter.

Figure 52. Power Connector

The supply must be at least 1A with a maximum of 3A. If the expansion connector is used, more power will be required depending on the load of the devices connected to the expansion connector.

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9.2 USB OTG

Figure 53 is a picture of the BeagleBoard USB OTG connector with the pins identified.

Figure 53. USB OTG Connector

The shorting pads, J1, to convert the OTG port to a Host mode are found in Figure 54.

Figure 54. OTG Host Shorting Pads

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9.3 S-Video

Figure 55 is the S-Video connector on the BeagleBoard.

Revision A2

Figure 55. S-Video Connector

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9.4 DVI-D

Figure 56 is the pinout of the DVI-D connector on BeagleBoard.

Revision A2

Figure 56. DVI-D Connector

Table 32 is the pin numbering of the two ends of the cable as it relates to the signals used in the

DVI-D interface itself.

Table 32. DVI-D to HDMI Cable

SIGNAL

DATA 2-

DVI-D PIN#

1

HDMI PIN#

3

DATA 2+ 2 1

SHIELD 3 2

4

5

DDS CLOCK

DDS DATA

6

7

15

16

8

DATA 1- 9 6

DATA 1+ 10 4

SHIELD 11 5

12

13

5V 14 18

GROUND (5V) 15 17

16

DATA 0- 17 9

SIGNAL

DATA 0+

DVI-D PIN#

18

DVI-D PIN#

7

SHIELD 19 5

20

21

22

CLOCK+ 23 10

CLOCK- 24 12

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DO NOT PLUG IN THE DVI-D CONNECTOR TO A DISPLAY WITH THE

BEAGLEBAORD POWERED ON. PLUG IN THE CABLE TO THE DISPLAY

AND THEN POWER ON THE BEAGLEBOARD.

Figure 57 is one of the cables that can be used to connect to an LCD monitor.

Figure 57. DVI-D Cable

A standard HDMI cable may be used as well as long as it is used with an adapter if you are connecting to a monitor via the DVI-D port. Figure 58 shows this configuration.

Figure 58. DVI-D Cable

In some cases, the HDMI to HDMI connector could be used to connect direct to a monitor equipped with a HDMI port. It some cases, the BeagleBoard may not work if the display timing is not accepted by the display. It should also be noted that no audio will be provided over this interface.

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9.5 LCD

This section covers the pair of headers that provide access to the raw 1.8V DSS signals from the processor. This provides the ability to create adapters for such things as different

LCD panels, LVDS interfaces, etc.

9.5.1 Connector Pinout

The Table 33 and 34 define the pinout of the LCD connectors. All signal levels are 1.8V with the exception of DVI_PUP signal which is 3.3V.

Table 33. P11 LCD Signals

Pin# Signal I/O Description

5

6

7

8

1

2

3

4

DC_5V

DC_5V

DVI_DATA1

DVI_DATA0

DVI_DATA3

DVI_DATA2

DVI_DATA5

DVI_DATA4

9 DVI_DATA12 O LCD Pixel Data bit

10 DVI_DATA10 O LCD Pixel Data bit

11 DVI_DATA23 O LCD Pixel Data bit

12 DVI_DATA14 O LCD Pixel Data bit

13 DVI_DATA19 O LCD Pixel Data bit

14 DVI_DATA22 O LCD Pixel Data bit

15 I2C3_SDA I/O I2C3 Data Line

16 DVI_DATA11 O LCD Pixel Data bit

17 DVI_VSYNC O LCD Vertical Sync Signal

Control signal for the DVI

18 DVI_PUP O controller. When Hi, DVI is enabled. Can be used to activate circuitry on adapter board if desired.

19 GND

20 GND

PWR DC rail from the Main DC supply

PWR DC rail from the Main DC supply

O LCD Pixel Data bit

O LCD Pixel Data bit

O LCD Pixel Data bit

O LCD Pixel Data bit

O LCD Pixel Data bit

O LCD Pixel Data bit

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Pin#

Table 34. P13 LCD Signals

Signal

5

6

7

8

1

2

3

4

3.3V

VIO_1V8

DVI_DATA20

DVI_DATA21

DVI_DATA17

DVI_DATA18

DVI_DATA15

DVI_DATA16

9 DVI_DATA7

10 DVI_DATA13

11 DVI_DATA8

12 NC

13 DVI_DATA9

14 I2C3_SCL

15 DVI_DATA6

16 DVI_CLK+

17 DVI_DEN

I/O Description

PWR 3.3V reference rail

PWR 1.8V buffer reference rail.

O LCD Pixel Data bit

O LCD Pixel Data bit

O LCD Pixel Data bit

O LCD Pixel Data bit

O LCD Pixel Data bit

O LCD Pixel Data bit

O LCD Pixel Data bit

O LCD Pixel Data bit

O LCD Pixel Data bit

LCD Pixel Data bit

I/O I2C3 Clock Line

O LCD Pixel Data bit

19 GND

20 GND

Figure 59 shows where pins 1 and 2 are located on each connector, front and back sides shown. The top side pins make for convenient test points if needed.

Figure 59. LCD Expansion Connector Pins

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9.5.2 Camera

Table 35 is the pinout of the camera connector on the board. Figure 60 shows the pin number and location of the camera connector.

Pin#

1

Table 35. P10 Camera Signals

Signal

CAM_D11

I/O

I

Description

Camera Data 11

3 CAM_D10

4 GND

5

6

CAM_D9

I2C_SCL

7

8

CAM_D8

I2C_SCL

9 CAM_D7

10 CAM_FLD

I

I

I

I/O

I

Camera Data 10

Camera Data 9

Camera control data

Camera Data 8

Camera control clock

Camera Data 7

11 CAM_D6

12 CAM_WEN

13 CAM_D5

14 GND

15

16

17

18

CAM_D4

CAM_2V8

CAM_D3

CAM_2V8

I

I

I

Camera Data 6

Camera Output enable

Camera Data 5

I Camera Data 4

PWR Camera 2.8V core voltage

I Camera Data 3

PWR Camera 2.8V core voltage

I Camera Data 2 19 CAM_D2

20 GND

21 CAM_D1

22 GND

I Camera Data 1

23 CAM_D0

24 DC_5V

25 DC_5V

26 DC_5V

I Camera Data 0

27 CAM_PCLK I Camera Clock

28 GND

29 CAM_HS

30 CAM_1V8

31 CAM_VS

32 CAM_1V8

33 GND

34 GND

PWR 1.8V IO rail

PWR 1.8V IO rail

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Figure 60. Camera Connector

Figure 61 is the front of the camera module. The camera should face to the edge of the board (Left) when installed. The camera module is not supplied with the BeagleBoard.

Figure 61. Camera Module

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9.5.3 Audio McBSP2 Port

New to the –xM version is the addition of a four pin connector that provides access to the

McBSP2 audio serial interface. While other McBSP ports can be used for audio, McBSP is the most desirable due its large buffers. Table 36 is the pin out of the connector.

Pin#

Table 36. P10 McBSP2 Signals

Signal I/O Description

3 McBSP2_DR I Receive

4 McBSP2_CLKX O Clock

Figure 62 is the pin number location of P10.

Figure 62. McBSP Audio Connector

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9.5.4 Auxiliary Access Header

Table 37 gives the signal names of the pins on the Auxiliary Access Connector.

Table 37. P17 Auxiliary Access Signals

Pin# Signal I/O Description

5

6

7

8

1

2

3

4

VIO_1V8

VMMC2

PWR 1.8V IO Rail

PWR 1.85V to 3.15V Rail. Configurable via SW.

MMC3_DAT2 I/O MMC interface data pin.

MMC_DAT7 I/O MMC interface data pin.

MMC3_DAT3 I/O MMC interface data pin.

GPIO_16 I/O General purpose I/O pin

GPIO_15

MMC3_DAT

I/O

I/O

General purpose I/O pin

MMC interface data pin.

9 MMC_DAT5 I/O MMC interface data pin.

10 MMC3_DAT4 I/O MMC interface data pin.

11 MMC_DAT0

12 MMC3_CMD

I/O

O

MMC interface data pin.

MMC CMD signal pin

13 MMC_DAT6

14 MMC3_CLK

15 HDQ

16 DMAREQ3

I/O

O

I/O

I/O

MMC interface data pin.

MMC clock pin

I-wire interface pin

DMA request input pin

17 AUX_ADC

18 PWR_CNTRL

19 GND

20 GND

I

I

ADC on TPS65950

Control pin for on/off button to the TPS65950

PWR

PWR

Figure 63 shows the location of P17.

Figure 63. Auxiliary Access Connector

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9.5.5 LCD and Expansion Measurements

Figure 64 provides some of the dimensions that can assist in the location of the LCD headers. It is strongly recommended that the CAD data be used in order to determine their location exact. Table 38 provides the values for each lettered dimension.

Figure 64. Top Mount LCD Adapter

Table 38. Connector Dimensions

Dimension Inches Millimeters

A 1.085 27.56

B 0.118 2.99

C 0.296 7.52

D 0.190 4.83

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9.5.6 Mounting Scenarios

This section provides a few possible mounting scenarios for the LCD connectors. It should be noted that the voltage level of these signals are 1.8V. It will require that they be buffered in order to drive other voltage levels.

Figure 65 shows the board being mounted under the BeagleBoard.

Buffer Logic BeagleBoard

LCD Connector

Adapter

Figure 65. Bottom Mount LCD Adapter

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9.6 Audio Connections

Figure 66 is the audio input jack required to connect to the BeagleBoard.

Figure 66. Audio In Plug

Figure 67 is the actual connector used on the BeagleBoard.

Figure 67. Audio In Connector

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9.7 Audio Out

Figure 68 is the audio out jack required to connect to the BeagleBoard.

Revision A2

Figure 68. Audio Out Plug

Figure 69 is the actual connector used on the BeagleBoard.

Figure 69. Audio Out Connector

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9.8 JTAG

Figure 70 is the JTAG connector pin out showing the pin numbering.

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Figure 70. JTAG Connector Pinout

Table 39 gives a definition of each of the signals on the JTAG header.

Table 39. JTAG Signals

Pin

1

3

7

9

Signal Description

JTAG_TMS

JTAG_TDI

Test mode select

Test data input

JTAG_TDO Test Data Output

JTAG_RTCK ARM Clock Emulation

13

14

JTAG_EMU0 Test emulation 0

JTAG_EMU1 Test emulation 1

5 VIO Voltage

4,8,10,12,14 GND Ground

I/O

I/O

I

O

O

I

I

I/O

I/O

PWR

PWR

All of the signals are 1.8V only. The JTAG emulator must support 1.8V signals for use on the BeagleBoard.

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If a 20 pin connector is provided on the JTAG emulator, then a 20 pin to 14 pin adapter must be used. You may also use emulators that are either equipped with a 14 pin connector or are universal in nature.

Figure 71 shows an example of a 14 pin to 20 pin adapter.

Figure 71. JTAG 14 to 20 Pin Adapter

Figure 72 shows how the JTAG cable is to be routed when connected to the

BeagleBoard.

C4

Figure 72. JTAG Connector Pinout

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9.9 Battery Installation

9.9.1 Battery

The board was designed to use the MS412FE-FL26E battery from Seiko Instruments.

This is a Lithium Rechargeable Battery with a 1mAH capacity. Figure 73 is a picture of the battery. It is also possible that the user may choose to install a higher capacity

Lithium battery.

Figure 73. Optional Battery

9.9.2 Battery Installation

THE FOLLOWING STRUCTIONS ASSUME THE USER HAS PREVIOUS

EXPERIENCE WITH BATTERIES. BATTERY INSTALLATION IS THE SOLE

RESPONSABILTY OF THE USER. INSTALLATION OF THE BATTERY BY THE

USER IS AT THEIR OWN RISK. FAILURE TO FOLLOW THE INSTRUCTIONS

CAN RESULT IN DAMAGE TO THE BOARD. THIS DAMAGE IS NOT COVERED

UNDER THE WARRANTY.

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Figure 74. Optional Battery Location

Figure 75. Resistor R65

Following are the steps required to install the battery.

1) Remove all cables from the board.

2) Remove R65 from the board as shown on Figure 73.

3) Using Figure 66, locate the positive (+) lead of the battery.

4) Insert the (+) lead into the hole that is marked (+) on Figure 74.

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10.0 BeagleBoard Accessories

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Throughout this manual various items are mentioned as not being provided with the standard BeagleBoard package or as options to extend the features of the BeagleBoard.

The concept behind BeagleBoard is that different features and functions can be added to

BeagleBoard by bringing your own peripherals. This has several key advantages: o

User can choose which peripherals to add. o

User can choose the brand of peripherals based on driver availability and ability to acquire the particular peripheral o

User can add these peripherals at a lower cost than if they were integrated into the

BeagleBoard.

This section covers these accessories and add-ons and provides information on where they may be obtained. Obviously things can change very quickly as it relates to devices that may be available. Please check BeagleBoard.org for an up to date listing of these peripherals.

Inclusion of any products in this section does not guarantee that they will operate with all SW releases. It is up to the user to find the appropriate drivers for each of these products. Information provided here is intended to expose the capabilities of what can be done with the BeagleBoard and how it can be expanded.

Inclusion of any product in this section is not an endorsement of the product by Beagleboard.org, but is provided as a convenience only to the users of the

BeagleBoard-xM board.

All pricing information provided is subject to change an din most cases is likely to be lower depending on the products purchased and from where they are purchased.

Covered in this section are the following accessories: o

DC Power Supplies o

Serial Ribbon cable o

USB Hubs o

USB Thumb Drives o

DVI-D Cables o

DVI-D Monitors o

SD/MMC Cards o

USB to Ethernet

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USB to WiFi o

USB Bluetooth o

Expansion Cards

NO CABLES OR POWER SUPPLIES ARE PROVIDED WITH THE BEAGLEBOARD .

10.1 DC Power Supply

Tabletop or wall plug supplies can be used to power BeagleBoard. Table 40 provides the specifications for the BeagleBoard DC supply. Supplies that provide additional current than what is specified can be used if additional current is needed for add on accessories.

The amount specified is equal to that supplied by a USB port.

Table 40. DC Power Supply Specifications

Specification Requirement Unit

Connector 2.1mm x 5.5mm Center hot

It is recommended that a supply higher than 1.5A be used if higher current peripherals are expected to be used or if expansion boards are added. The onboard USB hub and Ethernet do consume additional power and if you plan to load the USB Host ports, more power will be required..

Table 41 lists some power supplies that will work with the BeagleBoard.

Part #

Table 41. DC Power Supplies

Manufacturer Supplier Price

DPS050200UPS-P5P-SZ CUI Digi-Key

Figure 76 is a picture of the type of power supply that will be used on the BeagleBoard.

Figure 76. DC Power Supply

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10.2 DVI Cables

In order to connect the DVI-D interface to a LCD monitor, a HDMI to DVI-D cable is required. Figure 77 is a picture of a HDMI to DVI-D cable.

Figure 77. HDMI to DVI-D Cable

10.3 DVI-D Monitors

There are many monitors that can be used with the BeagleBoard. With the integrated EDID feature, timing data is collected from the monitor to enable the SW to adjust its timings. Table 42 shows a short list of the monitors that have been tested to date on the BeagleBoard at the

1024x768 resolution. Please check on BeagleBoard.org

for an up to date listing of the DVI-D monitors as well as information on the availability of drivers.

Table 42. DVI-D Monitors Tested

Manufacturer Part Number Status

LG FLATRON W2243T Tested

DO NOT PLUG IN THE DVI-D CONNECTOR TO A DISPLAY WITH THE

BEAGLEBAORD POWERED ON. PLUG IN THE CABLE TO THE DISPLAY

AND THEN POWER ON THE BEAGLEBOARD.

The digital portion of the DVI-D interface is compatible with HDMI and is electrically the same. A standard HDMI cable may be used to connect to the HDMI input of monitors. Whether or not the Beagle will support those monitors is dependent on the timings that are used on the Beagle and those that are accepted by the monitor. This may require a change in the software running on the Beagle. The audio and encryption features of HDMI are not supported by the Beagle.

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The analog portion of DVI which provides RGB analog type signals is not supported by the Beagle. Buying a DVI to VGA adapter connector will not work on a VGA display.

You will need an active DVI-D to VGA adapter.

10.4 microSD Cards

Table 43 is a list of SD/MMC cards that have been tested on BeagleBoard. Please check

BeagleBoard.org

for an up to date listing of the SD/MMC cards that have been tested as well as information on the availability of drivers if required.

Table 43. SD/MMC Cards Tested

Manufacturer Type Part Number Status

Patriot 4GB Tested

10.5 USB to WiFi

There are several USB to WiFi adapters on the market and Figure 78 shows a few of these devices. These devices can easily add WiFi connectivity to BeagleBoard by using the USB OTG port in the host mode. This will require a special cable to convert the miniAB connector to a Type A or a hub can also be used. These are provided as examples only. Check BeagleBoard.org

for information on devices that have drivers available for them.

Figure 78. USB to WiFi

Table 44 provides a list of USB to WiFi adapters that could be used with the

BeagleBoard. Inclusion of these items in the table does not guarantee that they will work, but is provided as examples only. Please check BeagleBoard.org

for an up to date listing of the USB to WiFi devices as well as information on the availability of drivers.

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Table 44. USB to WiFi Adapters

Product Manufacturer

4410-00-00AF Zoom

Revision A2

Status

TEW-429Uf Trendnet Not

It should be noted that the availability of Linux drivers for various WiFi devices is limited. Before purchasing a particular device, please verify the availability of drivers for that device.

10.6 USB to Bluetooth

There are several USB to Bluetooth adapters on the market and Figure 79 shows a few of these devices. These devices can easily add Bluetooth connectivity to BeagleBoard by using the USB OTG port in the host mode. This will require a special cable to convert the miniAB connector to a Type A or a hub can also be used. These are provided as examples only. Check BeagleBoard.org for information on devices that have drivers available for them and their test status.

Figure 79. USB to Bluetooth

Table 45 provides a list of USB to Bluetooth adapters that could be used with the

BeagleBoard. Inclusion of these items in the table does not guarantee that they will work, but is provided as examples only. Please check BeagleBoard.org for an up to date listing of the USB to Bluetooth devices as well as information on the availability of drivers.

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Table 45. USB to Bluetooth Adapters

Product

TBW-105UB

Manufacturer

Revision A2

Status

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11.0 Mechanical Information

11.1 BeagleBoard Dimensions

This section provides information on the mechanical aspect of the BeagleBoard. Figure

80 is the dimensions of the BeagleBoard. Despite the change in the overall dimensions of the board, the mounting holes and the replacement of the main expansion and LCD headers are the same as is found on the rev C4 board.

Figure 80. BeagleBoard Dimension Drawing

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11.2 BeagleBoard Expansion Card Design Information

This section provides information on what is required from a mechanical and electrical aspect to create expansion cards for the BeagleBoard that are designed to connect to the

Expansion header on the BeagleBoard. Users are free to create their own cards for private or commercial use, but in order to be supported by the Software they must conform to these standards if such support is desired.

11.2.1 Mounting Method

The standard method to provide a daughtercard for the BeagleBoard is for it to be mounted UNDER the Beagle Board as described in Figure 81.

Figure 81. BeagleBoard Bottom Stacked Daughter Card

All BeagleBoard-xM produced will have the connectors pre mounted onto the bottom of the BeagleBoard as described above. The –xM has additional connectors on the back of the board. Figure 82 shows their location.

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Figure 82. BeagleBoard-xM Expansion Headers

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11.2.2 Expansion EEPROM

All expansion cards designed for use with the BeagleBoard are required to have a

EEPROM located on the board. This is to allow for the identification of the card by the

Software in order to set the pin muxing on the expansion connector to be compatible with the expansion card.

The schematic for the EEPROM is in Figure 83 below.

VIO_1V8

A0

A1

A2

U8

3

4

1

2

A0

A1

A2

VSS

VCC

WP

SCL

SDA

AT24C01

8

7

6

5

VIO_1V8

BB_WP

BB_I2C_SCL

BB_I2C_SDA

C28

TP

0.1uf ,CER,0402

TP7

Figure 83. BeagleBoard Expansion Board EEPROM Schematic

The EEPROM must be write protected. It is suggested that a testpoint be used to allow for the WP to be disabled during test to allow the required data to be written to the

EEPROM. The EEPROM is to be connected to I2C2 as found on the main expansion connector.

The EEPROM that is designated is the AT24C01 or ATC24C01B. The AT24C01 is designated as “Not Recommended for New Design” but can still be used. The

AT24C01B is the replacement part and is available in several different packages, all of which can be used. o

TSSOP 8 o

PDIP 8 o

UDFN 8 o

SOIC 8 o

SOT23 5 o

dBGA2 8

The contents of the EEPROM are not specified in this document.

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12.0 Board Verification Test Points

There are several test points that may be useful if it becomes necessary to troubleshoot the BeagleBoard-xM board. Figure 84 shows the top side test points.

Figure 84. BeagleBoard Voltage Access Points

Some of these voltages may not be present depending on the state of the TWL4030 as set by the processor. Others may be at different voltage levels depending on the same factor.

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Table 46 provides the ranges of the voltages and the definition of the conditions as applicable.

Table 46. Voltages

Voltage Min Nom Max Conditions

VIO_1V8 1.78 1.8 1.81

VDD_SIM 1.78 1.8 1.81

VBUS_5V0 4.9

VOCORE_1V3 1.15

5.0

1.2

5.2

1.4

From the host PC. May be lower or higher.

Can be set via SW. Voltage levels may vary.

VBAT 4.1 4.2 4.3

VDAC_1V8 1.78 1.8 1.81

VDD_PLL1 1.78 1.8 1.81

VDD_PLL2 1.78 1.8 1.81

VDD2

3.3V

1.15 1.2 1.25

3.28 3.3 3.32

VMMC1 (3V) 2.9 3.0 3.1 3.0V at power up. Can be set to via SW.

VMMC1(1.8V) 1.78 1.8 1.81

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12.1.1 Signal Access Points

Figure 85 shows the access points for various signals on BeagleBoard.

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Figure 85. BeagleBoard Signal Access Points

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12.2 Troubleshooting Guide

Table 47 provides a list of possible failure modes and conditions and suggestions on how to diagnose them and ultimate determine whether the HW is operational or not.

Symptoms

JTAG does not connect.

UBoot does not start, and no activity on the

RS232 monitor.

USB Host Connection

Issues via OTG.

Table 47. Troubleshooting

Possible Problem

Verify that the Power LED is on.

Action

If off and running over USB, the PC may have shut down the voltage due to excessive current as related to what it is capable of providing. Remove the USB cable and re insert.

If running on a DC supply make sure that voltage is being supplied.

Reset the BeagleBoard. JTAG interface needs to be reset

Incorrect serial cable configuration.

If a 60 is displayed over the serial cable, processor is booting. Issue could be the

SD/MMC card.

Cheap USB Cable. OTG cables are typically not designed for higher current.

The expect 100mA max.

Verify straight thru cable configuration

Make sure the SD/MMC card is installed all they way into the connector.

Make sure the card is formatted correctly and that the MLO file is the first file written to the SD card.

Measure the voltage at the card to determine the voltage drop across the cable. If it the level is below 4.35V, the USB power is not guaranteed to work,

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13.0 Known Issues

This section provides information on any known issues with the BeagleBoard HW and the overall status. Table 48 provides a list of the know issues on the BeagleBoard.

Affected

Revision

A

Issue

USB Hub reset

Table 48. Known Issues

Description Workaround Final

Fix

None B

Reset signal to hub is not operational Hub can be powered off and on to create a reset scenario

No Plan

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14.0 PCB Component Locations

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Figures 86 and Figure 87 contain the bottom and top side component locations of the

BeagleBoard.

Figure 86. BeagleBoard Top Side Components

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Figure 87. BeagleBoard Bottom Side Components

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15.0 Schematics

The following pages contain the PDF schematics for the BeagleBoard. This manual will be periodically updated, but for the latest documentation be sure and check

BeagleBoard.org for the latest schematics.

OrCAD source files are provided for BeagleBoard on BeagleBoard.org at the following link. http://beagleboard.org/hardware/design

These design materials are *NOT SUPPORTED* and DO NOT constitute a reference design. Only “community” support is allowed via resources at BeagleBoard.org/discuss.

THERE IS NO WARRANTY FOR THE DESIGN MATERIALS, TO THE EXTENT

PERMITTED BY APPLICABLE LAW. EXCEPT WHEN OTHERWISE STATED IN

WRITING THE COPYRIGHT HOLDERS AND/OR OTHER PARTIES PROVIDE THE

DESIGN MATERIALS “AS IS” WITHOUT WARRANTY OF ANY KIND, EITHER

EXPRESSED OR IMPLIED, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED

WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR

PURPOSE. THE ENTIRE RISK AS TO THE QUALITY AND PERFORMANCE OF THE

DESIGN MATERIALS IS WITH YOU. SHOULD THE DESIGN MATERIALS PROVE

DEFECTIVE, YOU ASSUME THE COST OF ALL NECESSARY SERVICING, REPAIR

OR CORRECTION.

We mean it, these design materials may be totally unsuitable for any purposes.

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16.0 Bills of Material

The Bill of Material for the Beagle Board is provided at BeagleBoard.org at the following location: http://beagleboard.org/hardware/design

These design materials are *NOT SUPPORTED* and DO NOT constitute a reference design. Only “community” support is allowed via resources at BeagleBoard.org/discuss.

THERE IS NO WARRANTY FOR THE DESIGN MATERIALS, TO THE EXTENT

PERMITTED BY APPLICABLE LAW. EXCEPT WHEN OTHERWISE STATED IN

WRITING THE COPYRIGHT HOLDERS AND/OR OTHER PARTIES PROVIDE THE

DESIGN MATERIALS “AS IS” WITHOUT WARRANTY OF ANY KIND, EITHER

EXPRESSED OR IMPLIED, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED

WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR

PURPOSE. THE ENTIRE RISK AS TO THE QUALITY AND PERFORMANCE OF THE

DESIGN MATERIALS IS WITH YOU. SHOULD THE DESIGN MATERIALS PROVE

DEFECTIVE, YOU ASSUME THE COST OF ALL NECESSARY SERVICING, REPAIR

OR CORRECTION.

We mean it; these design materials may be totally unsuitable for any purposes.

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17.0 PCB Information

The following pages contain the PDF PCB layers for the BeagleBoard. Gerber files and

Allegro source files are available on BeagleBoard.org at the following address. http://beagleboard.org/hardware/design

These design materials are *NOT SUPPORTED* and DO NOT constitute a reference design. Only “community” support is allowed via resources at BeagleBoard.org/discuss.

THERE IS NO WARRANTY FOR THE DESIGN MATERIALS, TO THE EXTENT

PERMITTED BY APPLICABLE LAW. EXCEPT WHEN OTHERWISE STATED IN

WRITING THE COPYRIGHT HOLDERS AND/OR OTHER PARTIES PROVIDE THE

DESIGN MATERIALS “AS IS” WITHOUT WARRANTY OF ANY KIND, EITHER

EXPRESSED OR IMPLIED, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED

WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR

PURPOSE. THE ENTIRE RISK AS TO THE QUALITY AND PERFORMANCE OF THE

DESIGN MATERIALS IS WITH YOU. SHOULD THE DESIGN MATERIALS PROVE

DEFECTIVE, YOU ASSUME THE COST OF ALL NECESSARY SERVICING, REPAIR

OR CORRECTION.

We mean it; these design materials may be totally unsuitable for any purposes.

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