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Rev.1.0, May. 2011
MMBTFxxGUBCA-xMExx
Samsung SD & MicroSD Card product family
SDA 3.0 specification compliant-Up to High Speed mode datasheet
SAMSUNG ELECTRONICS RESERVES THE RIGHT TO CHANGE PRODUCTS, INFORMATION AND
SPECIFICATIONS WITHOUT NOTICE.
Products and specifications discussed herein are for reference purposes only. All information discussed herein is provided on an "AS IS" basis, without warranties of any kind.
This document and all information discussed herein remain the sole and exclusive property of Samsung
Electronics. No license of any patent, copyright, mask work, trademark or any other intellectual property right is granted by one party to the other party under this document, by implication, estoppel or otherwise.
Samsung products are not intended for use in life support, critical care, medical, safety equipment, or similar applications where product failure could result in loss of life or personal or physical harm, or any military or defense application, or any governmental procurement to which special terms or provisions may apply.
For updates or additional information about Samsung products, contact your nearest Samsung office.
All brand names, trademarks and registered trademarks belong to their respective owners.
ⓒ 2011 Samsung Electronics Co., Ltd. All rights reserved.
- 1 -
MMBTFxxGWBCA-xMExx
Revision History
Revision No.
1.0
1. Customer sample acquired
History datasheet
Draft Date
Jun, 02. 2011
Rev. 1.0
SD Card
Remark
Final
Editor
S.M.Lee
- 2 -
MMBTFxxGWBCA-xMExx datasheet
Table Of Contents
4.0 PRODUCT SPECIFICATION...................................................................................................................................... 6
4.1 Current Consumption .............................................................................................................................................. 6
Rev. 1.0
SD Card
- 3 -
MMBTFxxGWBCA-xMExx datasheet
1.0 INFORMATION
M X X X X X X X X X X X X X X X X
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18
1. Module: M
2. Module Configuration
C : Flash Card (SLC)
E : Flash Card (OneNAND)
M : Flash Card (MLC)
3~4. Flash Density
64 : 64M 28 : 128M
56 : 256M 2 : 512M
5D : 512M DDP 1G : 1G
1D : 1G DDP 2G : 2G
2D : 2G DDP 4G : 4G
8G : 8G AG : 16G
B3 : 32Gb 3bit BG: 32Gb 2bit
BA : 32Gb DDR BT : 32G(3Bit Toggle)
5. Feature
R : microSD
F : SD
6~8. Card Density
008 : 8M Byte 016 : 16M Byte
032 : 32M Byte 048 : 48M Byte
064 : 64M Byte 096 : 96M Byte
128 : 128M Byte 192 : 192M Byte
256 : 256M Byte 384 : 384M Byte
512 : 512M Byte 01G : 1G Byte
02G : 2G Byte 04G : 4G Byte
08G : 8G Byte 16G : 16G Byte
32G : 32G Byte
9. Card Type
U : microSD
W : SD
10. Component Generation
M : 1st Generation A : 2nd Generation
B : 3rd Generation C : 4th Generation
D : 5th Generation E : 6th Generation
12. PCB Revision and Production site.
A : None (SEC) B : 1st Rev. (SEC)
C : 2nd Rev. (SEC) D : 3rd Rev. (SEC)
P : None (STS) Q : 1st Rev. (STS)
R : 2nd Rev. (STS) U : None(ATP)
V : 1st Rev.(ATP) W : 2nd Rev.(ATP)
Y : None(SPIL)
13. " - "
14. Packing Type
0 : With Label
1 : With Label/Contents
2 : No Label
3 : With Label Class2
4 : With Label Class4
5 : With Label Class6
6 : With Label Class10
7 : With Label UHS-I Speed Class1
A : None
B : Blue
D : Dark Black
G : Gray
H : White
M : Module Type
N : Navy Blue
P : Class2(No Label)
Q : Class4(No Label)
R : Class6(No Label)
S : Class10(No Label)
T : Metal Blue
W : Wine
15 ~ 16. Controller
ME: SS6651ACWWE
17 ~ 18. Customer Grade
" Customer List Reference "
11. Flash Package
C : CHIP Y : TSOP1
V : WSOP B : TBGA
2.0 PRODUCT LINE-UP
Rev. 1.0
SD Card
Model Number
MMBTF04GWBCA-xMExx
MMBTF08GWBCA-xMExx
MMBTF16GWBCA-xMExx
Capacities
4GB
8GB
16GB
Remarks
SD Card
(x : Refer to the Ordering Information)
- 4 -
MMBTFxxGWBCA-xMExx datasheet Rev. 1.0
SD Card
3.0 INTRODUCTION
3.1 General Description
The SD/microSD is a memory card that is specifically designed to meet the security, capacity, performance and enviroment requirements inherent in newly emerging audio and video consumer electronic devices. The SD/microSD will include a copyright protection mechanism that complies with the security of the SDMI standard and will be faster and capable for higher Memory capacity. The SD/microSD security system uses mutual authentication and a "new ciper algorithm" to protect from illegal usage of the card content. A none secured access to the user’s own content is also available.
The SD/ microSD communication is based on an advanced 9 and 8-pin interface (SD:9pin, microSD:8pin)) designed to operate in at maximum operating frequency of 208MHz and 2.7V ~ 3.6V voltage range with 2 Type signaling(1.8V & 3.3V)*. More detail informations on the interface, and mechanical description is defined as a part of this specification.
* High Speed mode Limited on this Specification.
3.2 System Features
• Compliant with SD Memory Card Specifications PHYSICAL LAYER SPECIFICATION Version 3.00
- Based on SD Memory Card Specification 3.0 compatible Test Device.
- Bus speed only support up to High Speed Mode (3.3V signaling, frequency up to 50MHz)
• Targeted for portable and stationary applications
• Memory capacity:
1) Standard Capacity SD Memory Card(SDSC) : Up to and including 2 GB
2) High Capacity SD Memory Card(SDHC) : More than 2GB and up to and including 32GB
3) Extended Capacity SD Memory Card(SDXC) : More than 32GB and up to and including 2TB
• Voltage range:
High Voltage SD Memory Card – Operating voltage range: 2.7-3.6 V
• Designed for read-only and read/write cards.
• Bus Speed Mode
1) Default mode: Variable clock rate 0 - 25 MHz, up to 12.5 MB/sec interface speed (using 4 parallel data lines)
2) High-Speed mode: Variable clock rate 0 - 50 MHz, up to 25 MB/sec interface speed (using 4 parallel data lines)
• Switch function command supports High-Speed, and future functions
• Correction of memory field errors
• Card removal during read operation will never harm the content
• Content Protection Mechanism - Complies with highest security of SDMI standard.
• Password Protection of cards (CMD42 - LOCK_UNLOCK)
• Write Protect feature using mechanical switch
• Built-in write protection features (permanent and temporary)
• Card Detection (Insertion/Removal)
• Application specific commands
• Comfortable erase mechanism
• Weight : SD Card Max. 2.5g / microSD Card Max. 1g
3.3 System Block Diagram
<Host> <SD / microSD Card>
SD / SPI
Interface
Data
In/Out
SD
Controller
Control
/ CLK
NAND
Flash
- 5 -
MMBTFxxGWBCA-xMExx datasheet Rev. 1.0
SD Card
4.0 PRODUCT SPECIFICATION
4.1 Current Consumption
This information table below provides current consumption of Samsung SD/microSD Card. Current consumption is measured by averaging over 1 second.
[Table 4-1] : Current Consumption Table
Mode
Default Mode
High Speed Mode
Max. Interface Frequency
25Mhz
50Mhz
Operations
Read
Write
Read
Write
Max.
100mA
200mA
NOTE:
Current consumption on each device can be varied by NAND Flash, . of chips, test conditions and Etc. For specific information, refer to Samsung SD/microSD Card Qualification report.
4.2 System Performance
4.2.1 Product Performance & Speed Class Information
Product Performance and Speed Class Informations are based on TestMetrix compliance Tool. Note that the performance measured by TestMetrix does not represent real performance in various circumstances.
[Table 4-2] : Performance Information
Product Number
MMBTF04GWBCA-xMExx
MMBTF08GWBCA-xMExx
MMBTF16GWBCA-xMExx
Write Performance (MB/s)
7
13
13
Read Performance (MB/s)
24
Speed Class
1
Class 4
Class 6
Class 6
NOTE:
1) Five Speed Classes are defined and indicate minimum performance of the cards in Speed Class Test Mode. Speed Class compliant SDA
Physical Layer Specification, Version 3.00
.Class 0 - These Class cards do not specify performance. It includes all the legacy cards prior to this specification, regardless of its performance
.Class 2 - is more than or equal to 2MB/s performance
.Class 4 - is more than or equal to 4MB/s performance
.Class 6 - is more than or equal to 6MB/s performance
.Class 10 - is more than or equal to 10MB/s performance
4.2.2 Read, Write Timeout Error Conditions
SEC SD/microSD Card shall complete the command within the time period defined as follows or give up and return and error message. If the host does not get any response with the given timeout it should assume that the card is not going to respond and try recover. For more information, refer to Section
4.6 of the SDA Physical Layer Specification, Version 3.00
[Table 4-3] : Timeout Error Conditions
Timing
Block Read Access Time
Block Write Access Time
Initialization Time out(ACMD 41)
1
Max. Value
100ms
250ms(SDSC/SDHC), 500ms(SDXC)
1s
NOTE:
1) The host shall set ACMD41 timeout more than 1 second to abort repeat of issuing ACMD41 when the card does not indicate ready. The timeout count starts from the first
ACMD41 which is set voltage window in the argument.
- 6 -
MMBTFxxGWBCA-xMExx datasheet Rev. 1.0
SD Card
4.3 SD Mode Card Registers
Six registers are defined within the card interface: OCR, CID, CSD, RCA, DSR and SCR. These can be accessed only by corresponding commands. The
OCR, CID, CSD and SCR registers carry the card/content specific information, while the RCA and DSR registers are configuration registers storing actual configuration parameters.
4.3.1 OCR Register
• The 32-bit operation conditions register stores the V
DD
voltage profile of the card. Additionally, this register includes status information bits.
•See Section 5.1 of the SDA Physical Layer Specification, Version 3.00 for more information.
[Table 4-4] : OCR Register Definition
OCR bit
0-3
4
7
8
5
6
13
14
15
16
9
10
11
12
17
18
19
20
21
22
23
24
3
24 - 29
30
31
NOTE:
1) This bit is valid only when the card power up status bit is set.
2) This bit is set to LOW if the card has not finished the power up routine.
3) Only UHS-I card supports this bit.
VDD Voltage Window reserved reserved reserved reserved reserved for Low Voltage Range reserved reserved reserved reserved reserved reserved reserved
2.7 - 2.8
2.8 - 2.9
2.9 - 3.0
3.0 - 3.1
3.1 - 3.2
3.2 - 3.3
3.3 - 3.4
3.4 - 3.5
3.5 - 3.6
Switching to 1.8V Accepted (S18A) reserved
Card Capacity Staus(CCS)
1
Card power up status bit(busy)
2
1
1
0
1
0
0
0
0
OCR Value
0
0
0
0
0
0
0
1
1
1
1
1
1
0
0
-
-
- 7 -
MMBTFxxGWBCA-xMExx datasheet Rev. 1.0
SD Card
4.3.2 CID Register
The Card IDentification (CID) register is 128 bits wide. It contains the card identification information used during the card identification phase. Every individual Read/Write (RW) card shall have an unique identification number. It is programmed during manufacturing and cannot be changed by card hosts.
The structure of the CID register is defined in the following paragraphs:
[Table 4-5] : CID Register Fields
Name
Manufacturer ID
OEM/Application ID
Product name
Product revision
Product serial number
Reserved
Manufacturing date
CRC7 checksum not used, always ’1’
Field
MID
OID
PNM
PRV
PSN
-
MDT
CRC
-
Type
Binary
ASCII
ASCII
BCD
Binary
-
BCD
Binary
-
Width
32
4
12
7
1
8
16
40
8
4GB
CID Value
8GB 16GB
CID Register Value can be provided by Customer Request
- 8 -
MMBTFxxGWBCA-xMExx datasheet Rev. 1.0
SD Card
4.3.3 CSD Register (CSD Version 1.0)
The Card-Specific Data register provides information on how to access the card contents. The CSD defines the data format, error correction type, maximum data access time, data transfer speed, whether the DSR register can be used etc. The programmable part of the register (entries marked by W or E, see below) can be changed by CMD27. The type of the entries in the table below is coded as follows: R = readable, W(1) = writable once, W=multiple writable.
[Table 4-6] : The CSD Register Fields (CSD Version 1.0)
Name Field
CSD structure
Reserved
Data read access-time 1
Data read access-time 2 in CLK cycles (NSAC*100)
Max. Data transfer rate
Card command classes
Max. read data block length
Partial blocks for read allowed
Write block misalignment
Read block misalignment
DSR implemented
CSD_STRUCTURE
-
TAAC
NSAC
TRAN_SPEED
CCC
READ_BL_LEN
READ_BL_PARTIAL
WRITE_BLK_MISALIGN
READ_BLK_MISALIGN
DSR_IMP
Reserved
Device size
Max. read current @ V
DD
min
Max. read current @ V
DD
max
Permanent write protection
Temporary write protection
File format
Reserved
-
C_SIZE
VDD_R_CURR_MIN
VDD_R_CURR_MAX
Max. write current @ V
DD
min
Max. write current @ V
DD
max
Device size multiplier
VDD_W_CURR_MIN
VDD_W_CURR_MAX
Erase single block enable
Erase sector size
Write protect group size
Write protect group enable
C_SIZE_MULT
ERASE_BLK_EN
SECTOR_SIZE
WP_GRP_SIZE
WP_GRP_ENABLE
Reserved (Do Not Use)
Write speed factor
Max. write data block length
R2W_FACTOR
WRITE_BL_LEN
Partial blocks for write allowed
Reserved
File format group
Copy flag (OTP)
WRITE_BL_PARTIAL
-
FILE_FORMAT_GRP
COPY
PERM_WRITE_PROTECT
TMP_WRITE_PROTECT
FILE_FORMAT
CRC
Not used, always ’1’
CRC
-
Width
8
1
1
1
8
12
4
1
2
12
3
3
3
3
2
2
1
1
7
1
1
1
1
5
3
4
1
2
7
7
3
1
2
6
8
Cell
Type
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R/W(1)
R/W(1)
R/W(1)
R/W
R/W(1)
R/W
R/W
-
R
R
R
R
R
R
R
R
CSD-slice
[127:126]
[125:120]
[119:112]
[111:104]
[103:96]
[95:84]
[83:80]
[79:79]
[78:78]
[77:77]
[76:76]
[75:74]
[73:62]
[61:59]
[58:56]
[55:53]
[52:50]
[21:21]
[20:16]
[15:15]
[14:14]
[13:13]
[12:12]
[11:10]
[9:8]
[7:1]
[0:0]
[49:47]
[46:46]
[45:39]
[38:32]
[31:31]
[30:29]
[28:26]
[25:22]
4GB
CSD Value
8GB
Version 1.0
-
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
-
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
-
N/A
-
N/A
N/A
N/A
-
N/A
-
N/A
N/A
N/A
N/A
N/A
N/A
16GB
- 9 -
MMBTFxxGWBCA-xMExx datasheet Rev. 1.0
SD Card
4.3.4 CSD Register (CSD Version 2.0)
The following Table shows Definition of the CSD Version 2.0 for the High Capacity SD Memory Card and Extended Capacity SD Memory Card. The following sections describe the CSD fields and the relevant data types for the High Capacity SD Memory Card.
CSD Version 2.0 is applied to only the High Capacity SD Memory Card. The field name in parenthesis is set to fixed value and indicates that the host is not necessary to refer these fields. The fixed values enables host, which refers to these fields, to keep compatibility to CSD Version 1.0. The Cell Type field is coded as follows: R = readable, W(1) = writable once, W = multiple writable.
[Table 4-7] : The CSD Register Fields (CSD Version 2.0)
Name Field
CSD structure
Reserved
Data read access-time
Data read access-time in CLK cycles (NSAC*100)
Max. Data transfer rate
Card command classes
Max. read data block length
Partial blocks for read allowed
Write block misalignment
Read block misalignment
DSR implemented
Reserved
Device size
Reserved
Erase single block enable
Erase sector size
Write protect group size
Write protect group enable
Reserved
Write speed factor
Max. write data block length
Partial blocks for write allowed
Reserved
File format group
Copy flag (OTP)
Permanent write protection
Temporary write protection
File format
Reserved
CRC
Not used, always ’1’
CSD_STRUCTURE
-
(TAAC)
(NSAC)
(TRAN_SPEED)
CCC
(READ_BL_LEN)
(READ_BL_PARTIAL)
(WRITE_BLK_MISALIGN)
(READ_BLK_MISALIGN)
DSR_IMP
-
C_SIZE
-
(ERASE_BLK_EN)
(SECTOR_SIZE)
(WP_GRP_SIZE)
(WP_GRP_ENABLE)
-
(R2W_FACTOR)
(WRITE_BL_LEN)
(WRITE_BL_PARTIAL)
-
(FILE_FORMAT_GRP)
COPY
PERM_WRITE_PROTECT
TMP_WRITE_PROTECT
(FILE_FORMAT)
CRC
-
Width CSD-slice
[127:126]
[125:120]
[119:112]
[111:104]
[25:22]
[21:21]
[20:16]
[15:15]
[14:14]
[13:13]
[12:12]
[11:10]
[9:8]
[7:1]
[0:0]
[69:48]
[47:47]
[46:46]
[45:39]
[38:32]
[31:31]
[30:29]
[28:26]
[103:96]
[95:84]
[83:80]
[79:79]
[78:78]
[77:77]
[76:76]
[75:70]
8
1
2
1
1
5
1
4
1
2
7
1
2
3
7
1
22
1
1
7
1
6
1
1
8
12
4
1
2
6
8
Cell
Type
R
R
R
R
R
R
R
R
R/W(1)
R/W(1)
R/W
R
R
R/W
-
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
4GB
CSD Value
8GB
CSD Version 2.0
16GB
-
1000.00 us
0 cycles
25 Mbit/s or 50 Mbit/s class 0 2 4 5 7 8 10
512 bytes
0
0
-
0
0
7579 30531 15191
-
1
128 blocks
1 sectors
0
-
4
512 bytes
0
-
0
0
0
0
0
-
-
-
4.3.5 RCA Register
The writable 16-bit relative card address register carries the card address that is published by the card during the card identification. This address is used for the addressed host-card communication after the card identification procedure. The default value of the RCA register is 0x0000. The value 0x0000 is reserved to set all cards into the Stand-by State with CMD7.
- 10 -
MMBTFxxGWBCA-xMExx datasheet Rev. 1.0
SD Card
4.3.6 SCR Register
In addition to the CSD register, there is another configuration register named SD CARD Configuration Register (SCR). SCR provides information on the
SD Card’s special features that were configured into the given card. The size of SCR register is 64bits. The register shall be set in the factory by the SD
Card manufacturer. The following table describes the SCR register content.
[Table 4-8] : The SCR Fields
Name
SCR structure
SD Memory Card - Spec. Version data_status_after erases
SD Security Support
DAT Bus widths supported
Spec. Version 3.00 or Higher
Reserved
Command Support bits
Reserved for manufacturer usage
Field
SCR_STRUCTURE
SD_SPEC
DATA_STAT_AFTER_ERASE
SD_SECURITY
SD_BUS_WIDTHS
SD_SPEC3
CMD_SUPPORT
-
13
14
4
1
32
1
3
4
4
Width
Cell
Type
R
R
R
R
R
R
R
R
R
SCR-slice
[63:60]
[59:56]
[55:55]
[54:52]
[51:48]
[47]
[46:34]
[33:32]
[31:0]
4GB
SCR Value
8GB 16GB
SCR Version 1.0
Version 2.00 or Version 3.00
0
Version 2.00
1 bit(DAT0) + 4 bit(DAT0-3)
Version 3.00
-
Not Supported
-
- 11 -
MMBTFxxGWBCA-xMExx datasheet Rev. 1.0
SD Card
4.3.7 SD Status Register
The SD Status contains status bits that are related to the SD Memory Card proprietary features and may be used for future application specific usage. The size of the SD Status is one data block of 512bit. The content of this register is transmitted to the Host over the DAT bus along with 16bit CRC. The SD
Status is sent to the host over the DAT bus if ACMD13 is sent (CMD55 followed with CMD13). ACMD13 can be sent to a card only in ’tran_state’ (card is selected). SD Status structure is described in below. Unused reserved bits shall be set to 0.
511:510
509
508:502
501:496
495:480
479:448
447:440
439:432
431:428
427:424
423:408
407:402
401:400
[Table 4-9] : SD Status Register
Bits Field
DATA_BUS_WIDTH
SECURED_MODE
SD_CARD_TYPE
SIZE_OF_PROTECTED_AREA
SPEED_CLASS
PERFORMANCE_MOVE
AU_SIZE
Cell
Type
S R
S R
4GB
Data
8GB
0x00
0x00
16GB 4GB
Value
8GB
1bit width or 4bit width
16GB
-
Reserved for Security Functions (Refer to Part 3 Security Specification)
Reserved
S R
S R
S R
S R
S R
0x2000000 0x3000000 0x4000000
0x2
0x2
0x0000
0x3
0x3
Regular SD RD/WR Card
Class 4
2 [MB/sec]
-
Class 6
3 [MB/sec]
4MB
ERASE_SIZE
ERASE_TIMEOUT
ERASE_OFFSET
S R
S R
S R
0x9
Reserved
0x10
0x1
0x2
16 AU
1sec
2sec
399:312
311:0
Reserved
Reserved for Manufacturer
NOTE:
Speed Class that supports Class 10 shall not use the Pm value stored in the SD Status to calculate performance in any fragmented AU. Class 10 Performance is defined only for entirely free AUs
4.4 SPI Mode Card Registers
Unlike the SD Memory card protocol (where the register contents is sent as command response),reading the contents of the CSD and CID registers in
SPI mode is a simple read-block transaction. The card will respond with a standard response token followed by data block of 16 bytes suffixed with a 16bit CRC.
The data timeout for the CSD command cannot be set to the cards TAAC since this value is stored in the card‘s CSD. Therefore, the standard response timeout value(N
CR
) is used for read latency of the CSD register.
4.5 User Capacity
This information table below provides user capacity of Samsung SD/microSD Card.
Product user density is based on SD Formatter 2.0 tool with FAT File system.
SD Formatter 2.0 software formats all SD Cards and SDHC Cards using a formatting program that complies with official SD memory card requirements.
Product Number
MMBTF04GWBCA-xMExx
MMBTF08GWBCA-xMExx
MMBTF16GWBCA-xMExx
File System
FAT32
Tot. Sector No.
7,745,536
15,540,224
31,248,384
User Capacity[Byte]
3,965,714,432
7,956,594,688
15,999,172,608
NOTE :
SD or SDHC Card file systems formatted with generic operating system formatting software do not comply with official SD memory card requirement and optimum performance may not be experienced
- 12 -
MMBTFxxGWBCA-xMExx datasheet
5.0 INTERFACE DESCRIPTION
5.1 SD/microSD SD mode Bus Topology / SD/microSD SPI Bus Topology
Rev. 1.0
SD Card
Host
CLK
V
DD
V
SS
D0~3(A)
CMD(A)
CLK
V
DD
V
SS
D0~D3, CMD
SD Memory
Card(A)
Host
CS(A)
V
DD
V
SS
CS
V
DD
V
SS
D0~D3, CMD
SD Memory
CARD(A)
(SPI mode)
CLK
V
DD
V
SS
D0~D3, CMD
SD Memory
Card(B)
CS(B)
CS
V
DD
V
SS
CLK, DataIN, DataOut
SD Memory
CARD(B)
(SPI mode)
D0~3(B)
CMD(B)
CLK,
DataIN,
DataOut
SD Memory Card System Bus Topology
SD Memory Card system (SPI mode) Bus Topology
The SD/microSD Memory Card system defines two alternative communication protocols: SD and SPI. The host system can choose either one of modes. The card detects which mode is requested by the host when the reset command is received and expects all further communication to be in the same communication mode. Common bus signals for multiple card slots are not recommended. A single SD bus should connect a single SD card. Where the host system supports a high-speed mode, a single SD bus shall be connected to a single SD card.
The SD/microSD bus includes the following signals:
The SPI compatible communication mode of the SD/microSD Memory Card is designed to communicate with a SPI channel, commonly found in various microcontrollers in the market. The interface is selected during the first reset command after power up and cannot be changed as long as the part is powered on.
The SPI standard defines the physical link only, and not complete data transfer protocol. The SD/microSD Card SPI implementation uses the same command set of the SD mode. From the application point of view, the advantage of the SPI mode is the capability of using an off-the-shelf host, hence reducing the design-in effort to minimum. The disadvantage is the loss of performance, relatively to the SD mode which enables the wide bus option.
• CMD : Bidirectional Command/Response signal
• DAT0 - DAT3 : 4 Bidirectional data signals
• CLK : Host to card clock signal
• V
DD
, V
SS1,
V
SS2
: Power and ground signals
The SD/microSD Card SPI interface is compatible with SPI hosts available on the market. As any other SPI device the SD/microSD Card SPI channel consists the following four signals:
The SD/microSD Card bus has a single master (application), multiple slaves (cards), synchronous start topology (refer to Figure 5-2). Clock, power and ground signals are common to all cards. Command (CMD) and data (DAT0-DAT3) signals are dedicated to each card providing continues point to point connection to all the cards.
• CS : Host to card Chip Select signal
• CLK : Host to card clock signal
• DataIN : Host to card data signal
• DataOut: Card to host data signal
Another SPI common characteristic is byte transfers, which is implemented in the card as well. All data tokens are multiples of bytes (8 bit) and always byte aligned to the CS signal.
During initialization process, commands are sent to each card individually, allowing the application to detect the cards and assign logical addresses to the physical slots. Data is always sent (received) to (from) each card individually. However, in order to simplify the handling of the card stack, after initialization process, all commands may be sent concurrently to all cards.
Addressing information is provided in the command packet.
.
The card identification and addressing methods are replaced by a hardware
Chip Select (CS) signal. There are no broadcast commands. For every command, a card (slave) is selected by asserting (active low) the CS signal
SD Bus allows dynamic configuration of the number of data lines. After power-up, be default, the SD/microSD Card will use only DAT0 for data transfer. After initialization, the host can change the bus width(number of active data lines). This feature allows and easy trade off between hardware cost and system performance. Note that while DAT1-DAT3 are not in use, the related Host’s DAT lines should be in tri-state (input mode). For SDIO cards DAT1 and DAT2 are used for signaling.
The CS signal must be continuously active for the duration of the SPI transaction (command, response and data). The only exception occurs during card programming, when the host can de-assert the CS signal without affecting the programming process.
- 13 -
MMBTFxxGWBCA-xMExx datasheet
5.2 Bus Protocol
5.2.1 SD Bus
For more details, refer to Section 3.6.1 of the SDA Physical Layer Specification, Version 3.00
5.2.2 SPI Bus
For more details, refer to Chapter 7 of the SDA Physical Layer Specification, Version 3.00
5.3 SD/microSD Card Pin Assignment
5.3.1 SD Card Pin Assignment
9
1 2 3 4 5 6 7 8 wp
SD Memory
Card
Rev. 1.0
SD Card
Figure 5-1. SD Memory Card shape and interface (top view)
The SD Memory Card has the form factor 24 mm x 32 mm x 2.1 mm or 24 mm x 32 mm x 1.4 mm.
description are given in section 5.4.
The following Table defines the card contacts:
5
6
3
4
[Table 5-1] : SD Memory Card Pad Assignment
Pin # Name
Type
1
SD Mode
1
CD/DAT3
2
I/O/PP
3
2 CMD PP
Description
Card Detect /
Data Line [Bit 3]
Command/Response
7
8
9
V
V
CLK
V
SS1
DD
SS2
DAT0
DAT1
4
DAT2
5
I
S
S
S
I/O/PP
I/O/PP
I/O/PP
Supply voltage ground
Supply voltage
Clock
Supply voltage ground
Data Line [Bit 0]
Data Line [Bit 1]
Data Line [Bit 2]
SPI Mode
CS
DI
V SS
Name
V DD
SCLK
V SS2
DO
RSV
RSV
I
I
I
3
S
S
S
Type
O/PP
Data In
Supply voltage ground
Supply voltage
Clock
Supply voltage ground
Data Out
Description
Chip Select (neg true)
NOTE:
1) S: power supply; I: input; O: output using push-pull drivers; PP: I/O using push-pull drivers;
2) The extended DAT lines (DAT1-DAT3) are input on power up. They start to operate as DAT lines after SET_BUS_WIDTH command.
The Host shall keep its own DAT1-DAT3 lines in input mode, as well, while they are not used.
3) At power up this line has a 50KOhm pull up enabled in the card. This resistor serves two functions Card detection and Mode Selection.
For Mode Selection, the host can drive the line high or let it be pulled high to select SD mode. If the host wants to select SPI mode it should drive the
line low. For Card detection, the host detects that the line is pulled high. This pull-up should be disconnected by the user, during regular data transfer,
with SET_CLR_CARD_DETECT (ACMD42) command
4) DAT1 line may be used as Interrupt Output (from the Card) in SDIO mode during all the times that it is not in use for data transfer operations
(refer to "SDIO Card Specification" for further details).
5) DAT2 line may be used as Read Wait signal in SDIO mode (refer to "SDIO Card Specification" for further details).
- 14 -
MMBTFxxGWBCA-xMExx
5.3.2 microSD Card Assignment datasheet Rev. 1.0
SD Card
Figure 5-2. Contact Area
[Table 5-2] : microSD Contact Pad Assignment
SD Mode
Pin #
Name Type
1
1 DAT2
2.5
I/O/PP
Description
Data Line [Bit 2]
Name
RSV
Type
1
2
3
4
5
6
CD/DAT3
CMD
V
CLK
V
DD
SS
2
I/O/PP
PP
S
I
S
3
Card Detect /
Data Line [Bit 3]
Command/Response
Supply voltage
Clock
Supply voltage ground
CS
V
DI
DD
SCLK
V SS
I
3
7 DAT0 I/O/PP Data Line [Bit 0] DO
8 DAT1
2.4
I/O/PP Data Line [Bit 1] RSV
4
NOTE:
1) S: power supply; I: input; O: output using push-pull drivers; PP: I/O using push-pull drivers ;
2) The extended DAT lines (DAT1-DAT3) are input on power up. They start to operate as DAT lines after
SET_BUS_WIDTH command. The Host shall keep its own DAT1-DAT3 lines in input mode, as well,
while they are not used.
3) At power up this line has a 50KOhm pull up enabled in the card. This resistor serves two functions Card
detection and Mode Selection. For Mode Selection, the host can drive the line high or let it be pulled
high to select SD mode. If the host wants to select SPI mode it should drive the line low. For Card
detection, the host detects that the line is pulled high. This pull-up should be disconnected by the user,
during regular data transfer, with SET_CLR_CARD_DETECT (ACMD42)
4) DAT1 line may be used as Interrupt Output (from the Card) in SDIO mode during all the times that it
is not in use for data transfer operations (refer to "SDIO Card Specification" for further details).
5) DAT2 line may be used as Read Wait signal in SDIO mode (refer to "SDIO Card Specification" for further details).
O/PP
I
S
I
S
SPI Mode
Description
Reserved
Chip Select (neg true)
Data In
Supply voltage
Clock
Supply voltage ground
Data Out
- 15 -
MMBTFxxGWBCA-xMExx datasheet Rev. 1.0
SD Card
5.4 Mechanical Specification
This section describes the mechanical and electrical features, as well as SEC SD/microSD Card environmental reliability and durability specifications. For more details you can refer to Chapter 8 of SDA Physical Layer Specification, Version 2.00 and SDA ,microSD Card Addendum, Section 3.0 Mechanical
Specification for microSD Memory Card.
5.4.1 Mechanical Form Factor of microSD
1 3
C2
R20
ALL EDGES
B4 A1
R3
R4
DETAIL A
135
°
R1
R2
B1
C3
R7
R19
A
B
R11
R10 B3 B2
R6
R5
C
A
C1
VIEW A
B1
CONTACT
SURFACE
Figure 5-3. Mechanical Description: Top View
DETAIL A
- 16 -
MMBTFxxGWBCA-xMExx datasheet
7- A4
A2
A3
8- A5
B7 B8
B5 B6
B10
R18
B11 R17
A9
A8
45
°
A6
CL
Figure 5-4. : Mechanical Description: Bottom View
A7
D1 D2
B9
Rev. 1.0
SD Card
KEEP OUT AREA
D3
Figure 5-5. Mechanical Description: Keep Out Area
- 17 -
MMBTFxxGWBCA-xMExx datasheet Rev. 1.0
SD Card
0.75mm Minimum
Nonconductive Area in front of all 8 contact pads
Figure 5-6. Nonconductive Area in Front of Contact Pad
Figure 5-7. Nonconductive Area on Sides of Card
Nonconductive Area, on both sides of microSD card
- 18 -
MMBTFxxGWBCA-xMExx
[Table 5-3] : microSD Package: Dimensions
B5
B6
B7
B8
B9
B10
B11
C
C1
C2
C3
B1
B2
B3
B4
A7
A8
A9
B
SYMBOL
A
A1
A2
A3
A4
A5
A6
D1
D2
D3
R1
R2
R3
R4
R5
R6
R7
R10
R11
R17
R18
R19
R20
NOTES:
1) DIMENSIONING AND TOLERTANCING PER ASME Y14.5M-1994.
2) DIMENSIONS ARE IN MILLIMETERS.
3) COPLANARITY IS ADDITIVE TO C1 MAX THICKNESS.
2.80
5.50
0.20
1.00
-
7.80
1.10
0.90
0.60
0.20
0.00
0.90
0.60
0.80
14.90
6.30
1.64
1.30
0.42
MIN
10.90
9.60
-
7.60
-
0.75
-
1.00
1.00
1.00
0.20
0.20
0.70
0.70
0.70
0.70
29.50
-
-
0.10
0.20
0.05
0.02
datasheet
COMMON DIMENSIONS
NOM
11.00
9.70
3.85
7.70
1.10
0.80
-
-
0.70
-
15.00
6.40
1.84
1.50
0.52
2.90
-
0.30
1.10
-
7.90
1.20
1.00
0.70
0.30
-
-
-
-
0.40
0.40
0.80
0.80
0.80
0.80
30.00
0.20
0.20
0.20
0.40
-
-
3.00
-
0.40
1.20
9.00
8.00
1.30
1.10
0.80
0.40
0.15
-
0.80
-
15.10
6.50
2.04
1.70
0.62
MAX
11.10
9.80
-
7.80
-
0.85
8.50
-
-
-
0.60
0.60
0.90
0.90
0.90
0.90
30.50
-
-
0.30
0.60
0.20
0.15
Rev. 1.0
SD Card
NOTE
BASIC
BASIC
- 19 -
MMBTFxxGWBCA-xMExx
5.4.2 Mechanical Form Factor of SD Card datasheet
Min 1.5
Min 3.4
Min 1.5
Rev. 1.0
SD Card
Figure 5-8. Mechanical Description: Top View - Keep Out Area
- 20 -
MMBTFxxGWBCA-xMExx
0.7
0.2
datasheet
22.5
+0
-0.1
0.6
0.7
Cord Body
Corner
2-R0.5
±0.1
4
8.125
6 x 2.5 = 15
Contoct Pad
Surface
(4-R0.3)
Contoct Pad
Surface
1.4
+0.2
-0.1
0Min
Rev. 1.0
SD Card
0.75
9
DAT2
1 2 3 4 5 6 7 8
CD/ CMD Vss
DAT3
V
DD
CLK Vss DAT0 DAT1
LOCK
Position
2
-R
0
.3
24
±0.1
3-R1
±0.1
3-R1
±0.1
2-R0.5
General Tolerance
±0.15
Figure 5-9. Mechanical Description
- 21 -
MMBTFxxGWBCA-xMExx datasheet
9.75
1.4 Min
0.25 Min
6-1
8.05
6 X 2.5 =
4 Min
15
5.625
1.1 Min
0.9 Min
Rev. 1.0
SD Card
9
DAT2
1 2 3 4 5 6 7 8
CD/ CMD Vss V
DD
DAR
CLK VssDAT0 DAT1
Lock
Position
0.75
write protet write enable
Figure 5-10. Mechanical Description: Bottom View
General Tolerance
±0.15
5.4.3 Electrical features, Environmental Reliability and Durability
SEC SD/microSD Card Electrical features, Environmental Reliabilities and Durabilities conform to SDA Physical Layer Specification Version 2.00, Section
8.1. For more details and informations of SEC SD/microSD Card Data, refer to Product Qualification Report.
- 22 -
MMBTFxxGWBCA-xMExx datasheet Rev. 1.0
SD Card
5.5 Electrical Interface
The following sections provide valuable information about the electrical interface. See Chapter 6 of the SDA Physical Layer Specification, Version 3.00 for more detail information.
5.5.1 Power Up
The power-up of the SD/microSD Card bus is handled locally in each SD Card and in the host
Supply voltage
V
DD max
Host supply voltage
Valid voltage range for all commands
V
DD min
Power up time Supply ramp up time
Initialization sequence CMD0 CMD8
Time out value for initialization process = 1Sec
End of first ACMD41 to card ready time
ACMD
41
N
CC ACMD
41
N
CC ACMD
41
Optional repetitons of ACMD41 until no cards are responding with busy bit set
N
CC
CMD2
Initialization delay:
The maximum of
1 msec, 74 clock cycles and supply ramp up time
Figure 5-11. Power-up Diagram
.
• Power up time is defined as voltage rising time from 0 volt to VDD(min.) and depends on application parameters such as the maximum number of
SD Cards, the bus length and the characteristic of the power supply unit.
• Supply ramp up time provides the time that the power is built up to the operating level (the host supply voltage) and the time to wait until the SD card
can accept the first command,
• The host shall supply power to the card so that the voltage is reached to VDD(min.) within 250ms and start to supply at least 74 SD clocks to the
SD card with keeping CMD line to high. In case of SPI mode, CS shall be held to high during 74 clock cycles.
• After power up (including hot insertion, i.e. inserting a card when the bus is operating) the SD Card enters the idle state. In case of SD host, CMD0 is
not necessary. In case of SPI host, CMD0 shall be the first command to send the card to SPI mode.
• CMD8 is newly added in the Physical Layer Specification Version 2.00 to support multiple voltage ranges and used to check whether the card supports
supplied voltage. The version 2.00 host shall issue CMD8 and verify voltage before card initialization. The host that does not support CMD8 shall supply
high voltage range.
• ACMD41 is a synchronization command used to negotiate the operation voltage range and to poll the cards until they are out of their power-up
sequence. In case the host system connects multiple cards, the host shall check that all cards satisfy the supplied voltage. Otherwise, the host should
select one of the cards and initialize.
- 23 -
MMBTFxxGWBCA-xMExx datasheet
5.5.2 Reset Level Power Up
Host needs to keep power line level less than 0.5V and more than 1ms before power ramp up.
VDD Supply
Voltage
3.6V
V
DD
max
2.7V
V
DD
min
Operating Supply Range
Stable Supply voltage
Rev. 1.0
SD Card
0.5V
Power On/Cycle level/duration
1msec
Time(not to scale)
Power ramp up
Initialization delay The maximum of 1msec, 74 clock cycles and supply up time
Figure 5-12. change of Figure for power up
CMD0
• To assure a reliable SD Card hard reset of Power On and Power Cycle, Voltage level shall be below 0.5V and Time duration shall be at least 1ms.
• The power ramp up time is defined from 0.5V threshold level up to the operating supply voltage which is stable between VDD(min.) and VDD(max.) and
host can supply SDCLK.
Followings are recommendation of Power ramp up:
(1) Voltage of power ramp up should be monotonic as much as possible.
(2) The minimum ramp up time should be 0.1ms.
(3) The maximum ramp up time should be 35ms for 2.7~3.6V power supply.
5.5.3 Power Down and Power Cycle
•
When the host shuts down the power, the card VDD shall be lowered to less than 0.5Volt for a minimum period of 1ms. During power down, DAT, CMD, and CLK should be disconnected or driven to logical 0 by the host to avoid a situation that the operating current is drawn through the signal lines.
• If the host needs to change the operating voltage, a power cycle is required. Power cycle means the power is turned off and supplied again. Power cycle
is also needed for accessing cards that are already in Inactive State. To create a power cycle the host shall follow the power down description before
power up the card (i.e. the card VDD shall be once lowered to less than 0.5Volt for a minimum period of 1ms).
- 24 -
MMBTFxxGWBCA-xMExx datasheet Rev. 1.0
SD Card
5.5.4 Bus Operating Conditions for 3.3V Signaling
SPI Mode bus operating conditions are identical to SD Card mode bus operating conditions.
5.5.4.1 Threshold Level for High Voltage Range
[Table 5-4] : Threshold Level for High Voltage
Parameter
Supply Voltage
Output High Voltage
Output Low Voltage
Input High Voltage
Input Low Voltage
Power Up Time
Symbol
V
DD
V
OH
V
OL
V
IH
V
IL
=
Min
2.7
0.75*V
DD
0.625*V
DD
Vss-0.3
Max.
3.6
0.125*V
DD
V
DD
+0.3
0.25 *V
DD
250
Unit
V
V
V
V
V ms
Remark
I
OH
= -2mA V
DD
min
I
OL
= 2mA V
DD
min
From 0V to V
DD
min
5.5.4.2 Bus Signal Line Load
The total capacitance of the SD Memory Card bus is the sum of the bus host capacitance C
HOST
, the bus capacitance C
BUS
itself and the capacitance
C
CARD
of each card connected to this line:
Total bus capacitance = C
HOST
+ C
BUS
+ N * C
CARD
Where N is the number of connected cards .
[Table 5-5] : Bus Operating Conditions - Signal Line’s Load
Parameter
Pull-up resistance
Total bus capacitance for each signal line
Symbol
R
CMD
R
DAT
C
L
C
CARD
Capacitance of the card for each siginal pin
Maximum signal line inductance
Pull-up resistance inside card (pin1)
Capacity Connected to Power Line
R
DAT3
C C
Min
10
10
Max.
100
40
10
16
90
5
Unit
KOhm pF pF nH
KOhm uF
Remark to prevent bus floating
1 card
C
HOST
+C
BUS shall not exceed 30 pF
f
PP
<= 20 MHz
May be used for card detection
To Prevent inrush current
Note that the total capacitance of CMD and DAT lines will be consist of C
HOST
, C
BUS and one C
CARD only because they are connected separately to the SD
Memory Card host.
Host should consider total bus capacitance for each signal as the sum of C
HOST
, C
BUS
, and C
CARD
, these parameters are defined by per signal. The host can determine C
HOST and C
BUS so that total bus capacitance is less than the card estimated capacitance load (C
L
=40 pF). The SD Memory Card guarantees its bus timing when total bus capacitance is less than maximum value of C
L
(40 pF). To limit inrush current caused by host insertion, card maximum capacitance between VDD - VSS is defined as 5uF. To support host hot insertion, the host should consider decoupling capacitor connected to power line.
As SD/microSD card Cc is 5uF(Max.), 45uF(min.) is recommended for Decoupling capacitor. For more details, please refer to Appendix E of the SDA
Physical Layer Specification 3.00.
- 25 -
MMBTFxxGWBCA-xMExx datasheet
5.5.5 Bus Signal Levels
As the bus can be supplied with a variable supply voltage, all signal levels are related to the supply voltage.
Rev. 1.0
SD Card
Supply Voltage
Input
High Level
Input
Low Level
V
DD
V
OH
V
IH
Undefined
V
IL
V
OL
V
SS
Figure 5-13. Bus Signal Levels
Output
High Level
Output
Low Level
Time
To meet the requirements of the JEDEC specification JESD8-1A and JESD8-7, the card input and output voltages shall be within the specified ranges shown in Table 5-2 for any VDD of the allowed voltage range.
- 26 -
MMBTFxxGWBCA-xMExx
5.5.6 Bus Timing (Default Mode) datasheet Rev. 1.0
SD Card t
WL f
PP t
WH
Clock t
THL t
ISU t
TLH t
IH
V
IL
V
OH
Output
V
OL t
ODLY(max) t
ODLY (min)
Shaded areas are not valid
Figure 5-14. Timing diagram data input/output referenced to clock (Default)
V
IH
V
IL
V
IH
[Table 5-6] : Bus Timing - Parameter Values (Default)
Parameter Symbol Min Max.
Unit
Clock CLK ( All values are referred to min. (V
IH
) and max. (V
IL
)
Clock frequency Data Transfer Mode f
PP
0 25 MHz
Clock frequency Identification Mode
Clock low time
Clock high time t f
OD
WL t
WH
0
1)
/ 100
10
10
400 kHz ns ns
Clock rise time
Clock fall time t
TLH
10 t
THL
Inputs CMD, DAT (referenced to CLK)
10 ns ns
Input set-up time
Input hold time t
ISU t
IH
5
5
Output delay time during Data Transfer Mode
Outputs CMD, DAT (referenced to CLK) t
ODLY
0 14
Output delay time during Identification Mode t
ODLY
0 50 ns ns ns ns
NOTE:
1) OHz means to stop the clock. The given minimum frequency range is for cases where a continuous clock is required
Remark
C
CARD
<= 10 pF (1 card)
C
CARD
<= 10 pF (1 card)
C
CARD
<= 10 pF (1 card‘s)
C
CARD
<= 10 pF (1 card)
C
CARD
<= 10 pF (1 card)
C
CARD
<= 10 pF (1 card)
C
CARD
<= 10 pF (1 card)
C
CARD
<= 10 pF (1 card)
C
L
<= 40 pF (1 card)
C
L
<= 40 pF (1 card)
- 27 -
MMBTFxxGWBCA-xMExx
5.5.7 Bus Timing (High-speed Mode) datasheet Rev. 1.0
SD Card f
PP
50%V
DD t
WL t
WH
V
IH
Clock
V
IL t
THL t
ISU t
TLH t
IH
V
IH
Input
V
IL
V
OH
Output
V
OL t
ODLY t
OH
Shaded areas are not valid
Figure 5-15. Timing Diagram data Input/Output Refrenced to Clock (High-Speed)
[Table 5-7] : Bus Timing - Parameter Values (High-Speed)
Parameter Symbol Min Max.
Unit
Clock CLK ( All values are referred to min. (V
IH
) and max. (V
IL
)
Clock frequency Data Transfer Mode f
PP 0 50 MHz
Clock low time
Clock high time t
WL t
WH
7
7 ns ns
Clock rise time
Clock fall time
Input set-up time t
TLH t
THL
Inputs CMD, DAT (referenced to CLK)
3
3 t
ISU 6 ns ns ns
Input hold time
Output delay time during Data Transfer Mode t
IH 2
Outputs CMD, DAT (referenced to CLK) t
ODLY
14 ns ns
Output Hold time
Total Systme capacitance for each line
1) t
OH
C
L
2.5
40 ns pF
NOTE:
1) In order to satisfy severe timing, host shall drive only one card.
Remark
C
CARD
<= 10 pF (1 card)
C
CARD
<= 10 pF (1 card)
C
CARD
<= 10 pF (1 card)
C
CARD
<= 10 pF (1 card)
C
CARD
<= 10 pF (1 card)
C
CARD
<= 10 pF (1 card)
C
CARD
<= 10 pF (1 card)
C
L
<= 40 pF (1 card)
C
L
<= 15 pF (1 card)
1 card
- 28 -
MMBTFxxGWBCA-xMExx datasheet Rev. 1.0
SD Card
6.0 SD/MICROSD CARD FUNCTIONAL DESCRIPTION
6.1 General
SEC SD/microSD Card Functional Description contained in this chapter; Section 6.2~6.14; basically, comfort to SDA Physical Layer Specification, Version
3.00. See Chapter 4 of the SDA Physical Layer Specification, Version 3.00 for detail information and guide.
6.2 Card Identification Mode
While in Card Identification mode the host resets all the cards that are in card identification mode, validates operation voltage range, identifies cards and asks them to publish Relative Card Address(RCA). This operation is done to each card separately on its own CMD line. Refer to Section 4.2 of the SDA
Physical Layer Specification, Version 3.00 for detail information and guide
1)
NOTE :
1) The products on this specification does not support UHS-1 mode. For correct identification flow, please refer to Section 4.2 of the SDA Physical Layer Specification, Version
2.00.
6.3 Clock Control
The SD/microSD Memory Card bus clock signal can be used by the host to change the cards to energy saving mode or to control the data flow(to avoid under-run or over-run conditions) on the bus. Refer to Section 4.4 of the SDA Physical Layer Specification, Version 3.00 for detail information and guide
6.4 Cyclic Redundancy Code
The CRC is intended for protecting SD Card commands, responses and data transfer against transmission errors on the SD Card bus. One CRC is generated for every command and checked for every response on the CMD line. For data blocks one CRC per transferred block, per data line, is generated.
The CRC is generated and checked as described in the Section 4.5 of the SDA Physical Layer Specification, Version 3.0
6.5 Command
There are four kinds of commands defined to control the SD Card:
* Broadcast commands (bc), no response - The broadcast feature is only if all the CMD lines are connected together
in the host. If they are separated then each card will accept it separately on his turn.
* Broadcast commands with response (bcr) - response from all cards simultaneously. Since there is no Open Drain
mode in SD Card, this type of command is used only if all the CMD lines are separated. The command will
be accepted and responded to by every card seperately.
* Addressed (point-to-point) commands (ac) - no data transfer on DAT lines
* Addressed (point-to-point) data transfer commands (adtc), data transfer on DAT lines
All commands and responses are sent over the CMD line of the SD Card bus. The command transmission always starts with the left bit of the bitstring corresponding to the command code word. For more details, refer to the Section 4.7 of the SDA Physical Layer Specification, Version 3.0.
NOTE:
Limited Vendor CMD information, only for certain customer and application, can be provided under appropriate purpose of usage.
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MMBTFxxGWBCA-xMExx datasheet Rev. 1.0
SD Card
6.6 Memory Array Partitioning
The basic unit of data transfer to/from the SD Card is one byte. All data transfer operations which require a block size always define block lengths as integer multiples of bytes. Some special functions need other partition granularity.
SD Memory Card
WP Group 1
Sector 1
Block 1 Block 2 Block 3 Block n
Sector 2
Sector 3
Sector m
WP Group 2
WP Group K
Figure 6-1: Write Protection Hierarchy
For block oriented commands, the following definition is used:
• Block: is the unit that is related to the block oriented read and write commands. Its size is the number of bytes that will be transferred when one block
command is sent by the host. The size of a block is either programmable or fixed. The information about allowed block sizes and the programmability
is stored in the CSD.
• For devices that have erasable memory cells, special erase commands are defined. The granularity of the erasable units is in general not the same as
for the block oriented commands:
• Sector: is the unit that is related to the erase commands. Its size is the number of blocks that will be erased in one portion. The size of a sector is fixed
for each device. The information about the sector size (in blocks) is stored in the CSD. Note that if the card specifies AU size, sector size should
be ignored.
• AU (Allocation Unit): is a physical boundary of the card and consists of one or more blocks and its size depends on each card. The maximum AU size
is defined for memory capacity. Furthermore AU is the minimal unit in which the card guarantees its performance for devices which complies with Speed
Class Specification. The information about the size and the Speed Class are stored in the SD Status. AU is also used to calculate the erase timeout.
• WP-Group: is the minimal unit that may have individual write protection for devices which support write-protected group. Its size is the number of groups
that will be write-protected by one bit. The size of a WP-group is fixed for each device. The information about the size is stored in the CSD.
The High Capacity SD Memory Card does not support the write protect group command.
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MMBTFxxGWBCA-xMExx datasheet
6.7 Timings
Refer to Section 4.12 of the SDA Physical Layer Specification, Version 3.00 for detail information and guide
1)
NOTE :
1) The products on this specification does not support UHS-1 mode.
6.8 Speed Class Specification
Refer to Section 4.13 of the SDA Physical Layer Specification, Version 3.00 for detail information and guide
1)
NOTE :
1)The products on this specification does not support UHS-1 mode.
6.9 Erase Timeout Calculation
Refer to Section 4.14 of the SDA Physical Layer Specification, Version 3.00 for detail information and guide
1)
NOTE :
1) The products on this specification does not support UHS-1 mode.
Rev. 1.0
SD Card
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