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ST72334J/N,
ST72314J/N, ST72124J
8-BIT MCU WITH SINGLE VOLTAGE FLASH MEMORY,
ADC, 16-BIT TIMERS, SPI, SCI INTERFACES
■
■
■
■
■
■
Memories
– 8K or 16K Program memory (ROM or single voltage FLASH) with read-out protection and in-situ programming (remote ISP)
– 256 bytes EEPROM Data memory (with readout protection option in ROM devices)
– 384 or 512 bytes RAM
Clock, Reset and Supply Management
– Enhanced reset system
– Enhanced low voltage supply supervisor with
3 programmable levels
– Clock sources: crystal/ceramic resonator oscillators or RC oscillators, external clock, backup Clock Security System
– 4 Power Saving Modes: Halt, Active-Halt,
Wait and Slow
– Beep and clock-out capabilities
Interrupt Management
– 10 interrupt vectors plus TRAP and RESET
– 15 external interrupt lines (4 vectors)
44 or 32 I/O Ports
– 44 or 32 multifunctional bidirectional I/O lines:
– 21 or 19 alternate function lines
– 12 or 8 high sink outputs
4 Timers
– Configurable watchdog timer
– Realtime base
– Two 16-bit timers with: 2 input captures (only one on timer A), 2 output compares (only one on timer A), External clock input on timer A,
PWM and Pulse generator modes
2 Communications Interfaces
– SPI synchronous serial interface
– SCI asynchronous serial interface (LIN compatible)
Device Summary
■
■
■
PSDIP56
TQFP64
14 x 14
PSDIP42
TQFP44
10 x 10
1 Analog Peripheral
– 8-bit ADC with 8 input channels (6 only on
ST72334Jx, not available on ST72124J2)
Instruction Set
– 8-bit data manipulation
– 63 basic instructions
– 17 main addressing modes
– 8 x 8 unsigned multiply instruction
– True bit manipulation
Development Tools
– Full hardware/software development package
Features
Program memory - bytes
RAM (stack) - bytes
EEPROM - bytes
Peripherals
Operating Supply
CPU Frequency
Operating Temperature
Packages
ST72124J2 ST72314J2 ST72314J4 ST72314N2 ST72314N4 ST72334J2 ST72334J4 ST72334N2 ST72334N4
8K 8K 16K 8K 16K 8K 16K 8K
384 (256) 384 (256) 512 (256) 384 (256)
-
512 (256)
-
384 (256)
256
Watchdog, Two 16-bit Timers, SPI, SCI
512 (256)
256
384 (256)
256
ADC
TQFP44 / SDIP42
3.2V to 5.5 V
Up to 8 MHz (with up to 16 MHz oscillator)
-40°C to +85°C (-40°C to +105/125°C optional)
TQFP64 / SDIP56 TQFP44 / SDIP42
16K
512 (256)
256
TQFP64 / SDIP56
April 2003
Rev. 2.5
1/153
1
Table of Contents
1 PREAMBLE: ST72C334 VERSUS ST72E331 SPECIFICATION . . . . . . . . . . . . . . . . . . . . . . . . . 5
SUPPLY, RESET AND CLOCK REGISTER DESCRIPTION . . . . . . . . . . . . . . . . . . . . . 32
2/153
2
Table of Contents
14.2 MAIN CLOCK CONTROLLER WITH REAL TIME CLOCK TIMER (MCC/RTC) . . . . . . . 52
14.5 SERIAL COMMUNICATIONS INTERFACE (SCI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85
16.11 COMMUNICATION INTERFACE CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . 135
17.1 PACKAGE MECHANICAL DATA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 140
18 DEVICE CONFIGURATION AND ORDERING INFORMATION . . . . . . . . . . . . . . . . . . . . . . . 144
3/153
3
ST72334J/N, ST72314J/N, ST72124J
To obtain the most recent version of this datasheet, please check at www.st.com>products>technical literature>datasheet.
Please also pay special attention to the Section
4/153
ST72334J/N, ST72314J/N, ST72124J
1 PREAMBLE: ST72C334 VERSUS ST72E331 SPECIFICATION
New Features available on the ST72C334
■
8 or 16K FLASH/ROM with In-Situ
Programming and Read-out protection
■
■
New ADC with a better accuracy and conversion time
New configurable Clock, Reset and Supply system
■
■
■
New power saving mode with real time base:
Active Halt
Beep capability on PF1
New interrupt source: Clock security system
(CSS) or Main clock controller (MCC)
ST72C334 I/O Configuration and Pinout
■
Same pinout as ST72E331
■
■
■
PA6 and PA7 are true open drain I/O ports without pull-up (same as ST72E331)
PA3, PB3, PB4 and PF2 have no pull-up configuration (all I/Os present on TQFP44)
PA5:4, PC3:2, PE7:4 and PF7:6 have high sink capabilities (20mA on N-buffer, 2mA on P-buffer and pull-up). On the ST72E331, all these pads
(except PA5:4) were 2mA push-pull pads without high sink capabilities. PA4 and PA5 were 20mA true open drains.
New Memory Locations in ST72C334
■
20h: MISCR register becomes MISCR1 register
(naming change)
■
■
■
29h: new control/status register for the MCC module
2Bh: new control/status register for the Clock,
Reset and Supply control. This register replaces the WDGSR register keeping the WDOGF flag compatibility.
40h: new MISCR2 register
5/153
ST72334J/N, ST72314J/N, ST72124J
2 INTRODUCTION
The ST72334J/N, ST72314J/N and ST72124J devices are members of the ST7 microcontroller family. They can be grouped as follows:
– ST72334J/N devices are designed for mid-range applications with Data EEPROM, ADC, SPI and
SCI interface capabilities.
– ST72314J/N devices target the same range of applications but without Data EEPROM.
– ST72124J devices are for applications that do not need Data EEPROM and the ADC peripheral.
All devices are based on a common industrystandard 8-bit core, featuring an enhanced instruction set.
The ST72C334J/N, ST72C314J/N and
ST72C124J versions feature single-voltage
FLASH memory with byte-by-byte In-Situ Programming (ISP) capability.
Under software control, all devices can be placed in WAIT, SLOW, ACTIVE-HALT or HALT mode, reducing power consumption when the application is in idle or standby state.
The enhanced instruction set and addressing modes of the ST7 offer both power and flexibility to software developers, enabling the design of highly efficient and compact application code. In addition to standard 8-bit data management, all ST7 microcontrollers feature true bit manipulation, 8x8 unsigned multiplication and indirect addressing modes.
For easy reference, all parametric data are located in
.
Figure 1. General Block Diagram
RESET
ISPSEL
V
DD
V
SS
OSC1
OSC2
PF7,6,4,2:0
(6-BIT)
PE7:0
(6-BIT for N versions)
(2-BIT for J versions)
8-BIT CORE
ALU
CONTROL
LVD
MULTI OSC
+
CLOCK FILTER
MCC/RTC
PORT F
TIMER A
BEEP
PORT E
SCI
WATCHDOG
PROGRAM
MEMORY
(8K or 16K Bytes)
RAM
(384 or 512 Bytes)
EEPROM
(256 Bytes)
PORT A
PORT B
PORT C
TIMER B
SPI
PORT D
8-BIT ADC
PA7:0
(8-BIT for N versions)
(5-BIT for J versions)
PB7:0
(8-BIT for N versions)
(5-BIT for J versions)
PC7:0
(8-BIT)
PD7:0
(8-BIT for N versions)
(6-BIT for J versions)
V
DDA
V
SSA
6/153
3 PIN DESCRIPTION
Figure 2. 64-Pin TQFP Package Pinout (N versions)
ST72334J/N, ST72314J/N, ST72124J
(HS) PE4
(HS) PE5
(HS) PE6
(HS) PE7
PB0
PB1
PB2
PB3
PB4
PB5
PB6
PB7
AIN0 / PD0
AIN1 / PD1
AIN2 / PD2
AIN3 / PD3
1
64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49
48
2 47
3 46
4 45 ei0
5 44
6 43
7 ei2
42
8 41
9 40
10 39
11 ei3
38
12 37
13 36
14 35
15 ei1 34
16
17 18 19 20 21 22 23 24 25 26 27 28
33
29 30 31 32
V
SS_1
V
DD_1
PA3
PA2
PA1
PA0
PC7 / SS
PC6 / SCK / ISPCLK
PC5 / MOSI
PC4 / MISO / ISPDATA
PC3 (HS) / ICAP1_B
PC2 (HS) / ICAP2_B
PC1 / OCMP1_B
PC0 / OCMP2_B
V
SS_0
V
DD_0
(HS) 20mA high sink capability ei x associated external interrupt vector
7/153
ST72334J/N, ST72314J/N, ST72124J
PIN DESCRIPTION (Cont’d)
Figure 3. 56-Pin SDIP Package Pinout (N versions)
PB4
PB5
PB6
PB7
AIN0 / PD0
AIN1 / PD1
AIN2 / PD2
AIN3 / PD3
AIN4 / PD4
AIN5 / PD5
AIN6 / PD6
AIN7 / PD7
V
DDA
V
SSA
MCO / PF0
BEEP / PF1
PF2
OCMP1_A / PF4
ICAP1_A / (HS) PF6
EXTCLK_A / (HS) PF7
V
DD_0
V
SS_0
OCMP2_B / PC0
OCMP1_B / PC1
ICAP2_B / (HS) PC2
ICAP1_B / (HS) PC3
ISPDATA/ MISO / PC4
MOSI / PC5 ei2 ei0
43
42
41
40
39
47
46
45
44
56
55
54
53
52
51
50
49
48
34
33
32
31
38
37
36
35
30
29
6
7
8
9
10
1
2
3
4
5
15
16
17
18
11
12
13
14
24
25
26
27
28
19
20
21
22
23 ei3 ei1
PB3
PB2
PB1
PB0
PE7 (HS)
PE6 (HS)
PE5 (HS)
PE4 (HS)
PE1 / RDI
PE0 / TDO
V
DD
_2
OSC1
OSC2
V
SS
_2
RESET
ISPSEL
PA7 (HS)
PA6 (HS)I
PA5 (HS)
PA4 (HS)
V
SS_1
V
DD_1
PA3
PA2
PA1
PA0
PC7 / SS
PC6 / SCK / ISPCLK
(HS) 20mA high sink capability ei x associated external interrupt vector
8/153
ST72334J/N, ST72314J/N, ST72124J
PIN DESCRIPTION (Cont’d)
Figure 4. 44-Pin TQFP and 42-Pin SDIP Package Pinouts (J versions)
PE1 / RDI
PB0
PB1
PB2
PB3
PB4
AIN0 / PD0
AIN1 / PD1
AIN2 / PD2
AIN3 / PD3
AIN4 / PD4
1
44 43 42 41 40 39 38 37 36 35 34
33
2 32
3 31 ei2 ei0
4 30
5 29
6 ei3 28
7 27
8
9
26
25
10 ei1 24
11
12 13 14 15 16 17 18 19 20 21 22
23
V
SS_1
V
DD_1
PA3
PC7 / SS
PC6 / SCK / ISPCLK
PC5 / MOSI
PC4 / MISO / ISPDATA
PC3 (HS) / ICAP1_B
PC2 (HS) / ICAP2_B
PC1 / OCMP1_B
PC0 / OCMP2_B
PB4
AIN0 / PD0
AIN1 / PD1
AIN2 / PD2
AIN3 / PD3
AIN4 / PD4
AIN5 / PD5
V
DDA
V
SSA
MCO / PF0
BEEP / PF1
PF2
OCMP1_A / PF4
ICAP1_A / (HS) PF6
EXTCLK_A / (HS) PF7
OCMP2_B / PC0
OCMP1_B / PC1
ICAP2_B/ (HS) PC2
ICAP1_B / (HS) PC3
ISPDATA / MISO / PC4
MOSI / PC5 ei2 ei0
35
34
33
32
31
30
38
37
36
42
41
40
39
25
24
23
22
29
28
27
26
6
7
8
9
10
11
12
1
2
3
4
5
17
18
19
20
21
13
14
15
16
EI3 ei1
PB3
PB2
PB1
PB0
PE1 / RDI
PE0 / TDO
V
DD
_2
OSC1
OSC2
V
SS
_2
RESET
ISPSEL
PA7 (HS)
PA6 (HS)
PA5 (HS)
PA4 (HS)
V
SS_1
V
DD_1
PA3
PC7 / SS
PC6 / SCK / ISPCLK
(HS) 20mA high sink capability ei x associated external interrupt vector
9/153
ST72334J/N, ST72314J/N, ST72124J
PIN DESCRIPTION (Cont’d)
For external pin connection guidelines, refer to
Section 16 "ELECTRICAL CHARACTERISTICS" on page
Legend / Abbreviations for
Type:
Input level:
I = input, O = output, S = supply
A = Dedicated analog input
In/Output level: C = CMOS 0.3V
C
T
DD
= CMOS 0.3V
DD
/0.7V
DD
,
/0.7V
DD
with input trigger
Output level: HS = 20mA high sink (on N-buffer only)
Port and control configuration:
– Input: float = floating, wpu = weak pull-up, int = interrupt
1)
, ana = analog
– Output: OD = open drain
2)
, PP = push-pull
Refer to Section 12 "I/O PORTS" on page 39 for more details on the software configuration of the I/O
ports.
The RESET configuration of each pin is shown in bold. This configuration is valid as long as the device is in reset state.
Table 1. Device Pin Description
Pin n°
Pin Name
1 49
2 50
PE4 (HS)
PE5 (HS)
3 51
4 52
PE6 (HS)
PE7 (HS)
5 53 2 39 PB0
6 54 3 40 PB1
7 55 4 41 PB2
8 56 5 42 PB3
9 1 6 1 PB4
10 2 PB5
11 3
12 4
PB6
PB7
13 5 7 2 PD0/AIN0
14 6 8 3 PD1/AIN1
15 7 9 4 PD2/AIN2
16 8 10 5 PD3/AIN3
17 9 11 6 PD4/AIN4
18 10 12 7 PD5/AIN5
19 11
20 12
PD6/AIN6
PD7/AIN7
21 13 13 8 V
DDA
22 14 14 9 V
SSA
23 V
DD_3
Level
I/O C
T
I/O C
T
HS
HS
X
X
X
X
I/O C
T
I/O C
T
I/O C
T
HS X X
HS X X
X ei2
I/O X ei2
I/O
I/O
C
T
C
T
C
T
X
X ei2 ei2
I/O X ei3
I/O
I/O
I/O
I/O
I/O
I/O
C
T
C
T
C
T
C
T
C
T
C
T
C
T
X
X
X
X
X
X
X
X
X ei3 ei3 ei3
I/O
I/O
I/O
I/O
I/O
C
T
C
T
C
T
C
T
C
T
X X
X
X
X
X
X
X
X
X
S
S
S
Input
Port
Output
Main function
(after reset)
Alternate function
X X Port E4
X X Port E5
X X Port E6
X X Port E7
X X Port B0
X X Port B1
X X Port B2
X X Port B3
X X Port B4
X X Port B5
X X Port B6
X X Port B7
X X X Port D0 ADC Analog Input 0
X X X Port D1 ADC Analog Input 1
X X X Port D2 ADC Analog Input 2
X X X Port D3 ADC Analog Input 3
X X X Port D4 ADC Analog Input 4
X X X Port D5 ADC Analog Input 5
X X X Port D6 ADC Analog Input 6
X X X Port D7 ADC Analog Input 7
Analog Power Supply Voltage
Analog Ground Voltage
Digital Main Supply Voltage
10/153
ST72334J/N, ST72314J/N, ST72124J
Pin n°
Pin Name
Level
24 V
SS_3
25 15 15 10 PF0/MCO
26 16 16 11 PF1/BEEP
27 17 17 12 PF2
S
I/O
I/O
I/O
C
T
C
T
C
T
X
X
X ei1 ei1 ei1
28 NC
29 18 18 13 PF4/OCMP1_A I/O C
T
X X
30 NC
31 19 19 14 PF6 (HS)/ICAP1_A I/O C
T
32 20 20 15 PF7 (HS)/EXTCLK_A I/O C
T
33 21 21 V
DD_0
S
HS
HS
X
X
X
X
34 22 22 V
SS_0
35 23 23 16 PC0/OCMP2_B
36 24 24 17 PC1/OCMP1_B
S
I/O
I/O
37 25 25 18 PC2 (HS)/ICAP2_B I/O C
T
38 26 26 19 PC3 (HS)/ICAP1_B I/O C
T
C
T
C
T
X
X
X
X
HS X X
HS X X
39 27 27 20 PC4/MISO
40 28 28 21 PC5/MOSI
41 29 29 22 PC6/SCK
I/O
I/O
I/O
C
T
C
T
C
T
X X
X
X
X
X
42 30 30 23 PC7/SS I/O X X
43 31
44 32
45 33
PA0
PA1
PA2
46 34 31 24 PA3
I/O
I/O
I/O
I/O
C
T
C
T
C
T
C
T
C
T
X
X
X
X ei0 ei0 ei0 ei0
47 35 32 25 V
DD_1
48 36 33 26 V
SS_1
49 37 34 27 PA4 (HS)
S
S
HS X X
50 38 35 28 PA5 (HS)
51 39 36 29 PA6 (HS)
52 40 37 30 PA7 (HS)
I/O C
T
I/O C
T
I/O C
T
I/O C
T
HS
HS
HS
X
X
X
X
53 41 38 31 ISPSEL
54 42 39 32 RESET
I
I/O C
Input
Port
X
Output
Main function
(after reset)
Alternate function
Digital Ground Voltage
X X Port F0 Main clock output (f
OSC
/2)
X X Port F1 Beep signal output
X X Port F2
Not Connected
X X Port F4 Timer A Output Compare 1
Not Connected
X X Port F6 Timer A Input Capture 1
X X Port F7 Timer A External Clock Source
Digital Main Supply Voltage
Digital Ground Voltage
X X Port C0 Timer B Output Compare 2
X X Port C1 Timer B Output Compare 1
X X Port C2 Timer B Input Capture 2
X X Port C3 Timer B Input Capture 1
X X Port C4 SPI Master In / Slave Out Data
X X Port C5 SPI Master Out / Slave In Data
X X Port C6 SPI Serial Clock
X X Port C7 SPI Slave Select (active low)
X X Port A0
X X Port A1
X X Port A2
X X Port A3
Digital Main Supply Voltage
Digital Ground Voltage
X X Port A4
X X Port A5
T Port A6
T Port A7
Must be tied low in user mode. In programming mode when available, this pin acts as In-Situ Programming mode selection.
X
Top priority non maskable interrupt (active low)
55 NC
56 NC
57 43 40 33 V
SS_3
58 44 41 34 OSC2
3)
S
O
Not Connected
Digital Ground Voltage
Resonator oscillator inverter output or capacitor input for RC oscillator
11/153
ST72334J/N, ST72314J/N, ST72124J
Pin n°
Pin Name
59 45 42 35 OSC1
3)
60 46 43 36 V
DD_3
61 47 44 37 PE0/TDO
62 48 1 38 PE1/RDI
63
64
NC
NC
I
S
I/O
I/O
Level
C
C
T
T
X X
X X
Input
Port
Output
Main function
(after reset)
Alternate function
External clock input or Resonator oscillator inverter input or resistor input for RC oscillator
Digital Main Supply Voltage
X X Port E0 SCI Transmit Data Out
X X Port E1 SCI Receive Data In
Not Connected
Notes:
1. In the interrupt input column, “ei x
” defines the associated external interrupt vector. If the weak pull-up column (wpu) is merged with the interrupt column (int), then the I/O configuration is pull-up interrupt input, else the configuration is floating interrupt input.
2. In the open drain output column, “T” defines a true open drain I/O (P-Buffer and protection diode to V
DD are not implemented). See
Section 12 "I/O PORTS" on page 39 and
Section 16.8 "I/O PORT PIN CHAR-
ACTERISTICS" on page 128 for more details.
3. OSC1 and OSC2 pins connect a crystal or ceramic resonator, an external RC, or an external source to the on-chip oscillator see
Section 3 "PIN DESCRIPTION" on page 7
and Section 16.5 "CLOCK AND TIM-
ING CHARACTERISTICS" on page 116
for more details.
12/153
ST72334J/N, ST72314J/N, ST72124J
4 REGISTER & MEMORY MAP
As shown in the
, the MCU is capable of addressing 64K bytes of memories and I/O registers.
The available memory locations consist of 128 bytes of register locations, 384 or 512 bytes of
RAM, up to 256 bytes of data EEPROM and 4 or
8 Kbytes of user program memory. The RAM space includes up to 256 bytes for the stack from
0100h to 01FFh.
The highest address bytes contain the user reset and interrupt vectors.
IMPORTANT: Memory locations marked as “Reserved” must never be accessed. Accessing a reserved area can have unpredictable effects on the device.
Figure 5. Memory Map
0000h
HW Registers
007Fh
0080h
384 Bytes RAM
01FFh
512 Bytes RAM
027Fh
0200h / 0280h
Reserved
0BFFh
0C00h
0CFFh
0D00h
256 Bytes Data EEPROM
Reserved
BFFFh
C000h
E000h
16K Bytes
Program
Memory
FFDFh
FFE0h
Interrupt & Reset Vectors
(see
FFFFh
8K Bytes
Program
Memory
0080h
00FFh
0100h
01FFh
Short Addressing RAM
Zero page
(128 Bytes)
Stack or
16-bit Addressing RAM
(256 Bytes)
0080h
00FFh
0100h
01FFh
Short Addressing RAM
Zero page
(128 Bytes)
Stack or
16-bit Addressing RAM
(256 Bytes)
0200h
027Fh
16-bit Addressing
RAM
C000h
E000h
FFFFh
16 KBytes
8 KBytes
13/153
ST72334J/N, ST72314J/N, ST72124J
REGISTER & MEMORY MAP (Cont’d)
Table 2. Hardware Register Map
Address Block
Register
Label
0000h
0001h
0002h
0003h
0004h
0005h
0006h
0007h
0008h
0009h
000Ah
000Bh
000Ch
000Dh
000Eh
000Fh
0010h
0011h
0012h
0013h
0014h
0015h
0016h
0017h to
001Fh
0020h
0021h
0022h
0023h
0024h to
0028h
0029h
Port A
Port C
Port B
Port E
Port D
Port F
SPI
MCC
PADR
PADDR
PAOR
PCDR
PCDDR
PCOR
PBDR
PBDDR
PBOR
PEDR
PEDDR
PEOR
PDDR
PDDDR
PDOR
PFDR
PFDDR
PFOR
MISCR1
SPIDR
SPICR
SPISR
MCCSR
Register Name
Port A Data Register
Port A Data Direction Register
Port A Option Register
Reserved Area (1 Byte)
Port C Data Register
Port C Data Direction Register
Port C Option Register
Reserved Area (1 Byte)
Port B Data Register
Port B Data Direction Register
Port B Option Register
Reserved Area (1 Byte)
Port E Data Register
Port E Data Direction Register
Port E Option Register
Reserved Area (1 Byte)
Port D Data Register
Port D Data Direction Register
Port D Option Register
Reserved Area (1 Byte)
Port F Data Register
Port F Data Direction Register
Port F Option Register
Reserved Area (9 Bytes)
Miscellaneous Register 1
SPI Data I/O Register
SPI Control Register
SPI Status Register
Reserved Area (5 Bytes)
Main Clock Control / Status Register
14/153
Reset
Status
00h
1)
00h
00h
Remarks
R/W
R/W
R/W
2)
00h
1)
00h
00h
R/W
R/W
R/W
00h
1)
00h
00h
R/W
R/W
R/W
2)
00h
1)
00h
00h
R/W
R/W
R/W
2)
00h
1)
00h
00h
R/W
R/W
R/W
2)
00h
1)
00h
00h
R/W
R/W
R/W
00h xxh
0xh
00h
R/W
R/W
R/W
Read Only
01h R/W
ST72334J/N, ST72314J/N, ST72124J
Address Block
Register
Label
Register Name
Reset
Status
Remarks
0041h
0042h
0043h
0044h
0045h
0046h
0047h
0048h
0049h
004Ah
004Bh
004Ch
004Dh
004Eh
004Fh
0050h
0051h
0052h
0053h
0054h
0055h
0056h
0057h
0031h
0032h
0033h
0034h
0035h
0036h
0037h
0038h
0039h
003Ah
003Bh
003Ch
003Dh
003Eh
003Fh
0040h
002Ah
002Bh
WATCHDOG WDGCR
CRSR
002Ch Data-EEPROM EECSR
002Dh
0030h
TIMER A
TACR2
TACR1
TASR
TAIC1HR
TAIC1LR
TAOC1HR
TAOC1LR
TACHR
TACLR
TAACHR
TAACLR
TAIC2HR
TAIC2LR
TAOC2HR
TAOC2LR
MISCR2
TIMER B
SCI
TBCR2
TBCR1
TBSR
TBIC1HR
TBIC1LR
TBOC1HR
TBOC1LR
TBCHR
TBCLR
TBACHR
TBACLR
TBIC2HR
TBIC2LR
TBOC2HR
TBOC2LR
SCISR
SCIDR
SCIBRR
SCICR1
SCICR2
SCIERPR
SCIETPR
Watchdog Control Register 7Fh R/W
Clock, Reset, Supply Control / Status Register 000x 000x R/W
Data-EEPROM Control/Status Register 00h R/W
Reserved Area (4 Bytes)
Timer A Control Register 2
Timer A Control Register 1
Timer A Status Register
Timer A Input Capture 1 High Register
Timer A Input Capture 1 Low Register
Timer A Output Compare 1 High Register
Timer A Output Compare 1 Low Register
Timer A Counter High Register
Timer A Counter Low Register
Timer A Alternate Counter High Register
Timer A Alternate Counter Low Register
Timer A Input Capture 2 High Register
Timer A Input Capture 2 Low Register
Timer A Output Compare 2 High Register
Timer A Output Compare 2 Low Register
Miscellaneous Register 2
Timer B Control Register 2
Timer B Control Register 1
Timer B Status Register
Timer B Input Capture 1 High Register
Timer B Input Capture 1 Low Register
Timer B Output Compare 1 High Register
Timer B Output Compare 1 Low Register
Timer B Counter High Register
Timer B Counter Low Register
Timer B Alternate Counter High Register
Timer B Alternate Counter Low Register
Timer B Input Capture 2 High Register
Timer B Input Capture 2 Low Register
Timer B Output Compare 2 High Register
Timer B Output Compare 2 Low Register
SCI Status Register
SCI Data Register
SCI Baud Rate Register
SCI Control Register 1
SCI Control Register 2
SCI Extended Receive Prescaler Register
Reserved area
SCI Extended Transmit Prescaler Register
FFh
FCh
FFh
FCh xxh xxh
80h
00h
00h
00h xxh xxh xxh
80h
00h
00h
FFh
FCh
FFh
FCh xxh xxh
80h
00h
00h
00h xxh xxh xxh
80h
00h
R/W
R/W
Read Only
Read Only
Read Only
R/W
R/W
Read Only
Read Only
Read Only
Read Only
Read Only
Read Only
R/W
R/W
C0h xxh
00xx xxxx xxh
00h
00h
---
00h
Read Only
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Read Only
Read Only
Read Only
R/W
R/W
Read Only
Read Only
Read Only
Read Only
Read Only
Read Only
3)
3)
R/W
3)
R/W
3)
R/W
15/153
ST72334J/N, ST72314J/N, ST72124J
Address Block
Register
Label
Register Name
Reset
Status
Remarks
0058h
006Fh
0070h
0071h
0072h to
007Fh
ADC
ADCDR
ADCCSR
Reserved Area (24 Bytes)
Data Register
Control/Status Register
Reserved Area (14 Bytes) xxh
00h
Read Only
R/W
Legend: x=undefined, R/W=read/write
Notes:
1. The contents of the I/O port DR registers are readable only in output configuration. In input configuration, the values of the I/O pins are returned instead of the DR register contents.
2. The bits corresponding to unavailable pins are forced to 1 by hardware, affecting accordingly the reset status value. These bits must always keep their reset value.
3. External pin not available.
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ST72334J/N, ST72314J/N, ST72124J
5 FLASH PROGRAM MEMORY
5.1 INTRODUCTION
FLASH devices have a single voltage non-volatile
FLASH memory that may be programmed in-situ
(or plugged in a programming tool) on a byte-bybyte basis.
5.2 MAIN FEATURES
■
■
■
■
Remote In-Situ Programming (ISP) mode
Up to 16 bytes programmed in the same cycle
MTP memory (Multiple Time Programmable)
Read-out memory protection against piracy
5.3 STRUCTURAL ORGANISATION
The FLASH program memory is organised in a single 8-bit wide memory block which can be used for storing both code and data constants.
The FLASH program memory is mapped in the upper part of the ST7 addressing space and includes the reset and interrupt user vector area .
5.4 IN-SITU PROGRAMMING (ISP) MODE
The FLASH program memory can be programmed using Remote ISP mode. This ISP mode allows the contents of the ST7 program memory to be updated using a standard ST7 programming tools after the device is mounted on the application board.
This feature can be implemented with a minimum number of added components and board area impact.
An example Remote ISP hardware interface to the standard ST7 programming tool is described below. For more details on ISP programming, refer to the ST7 Programming Specification.
Remote ISP Overview
The Remote ISP mode is initiated by a specific sequence on the dedicated ISPSEL pin.
The Remote ISP is performed in three steps:
– Selection of the RAM execution mode
– Download of Remote ISP code in RAM
– Execution of Remote ISP code in RAM to program the user program into the FLASH
Remote ISP hardware configuration
In Remote ISP mode, the ST7 has to be supplied with power (V
DD
and V
SS
) and a clock signal (oscillator and application crystal circuit for example).
This mode needs five signals (plus the V
DD
signal if necessary) to be connected to the programming tool. This signals are:
– RESET: device reset
– V
SS
: device ground power supply
– ISPCLK: ISP output serial clock pin
– ISPDATA: ISP input serial data pin
– ISPSEL: Remote ISP mode selection. This pin must be connected to V
SS
on the application board through a pull-down resistor.
If any of these pins are used for other purposes on the application, a serial resistor has to be implemented to avoid a conflict if the other device forces the signal level.
Figure 6 shows a typical hardware interface to a standard ST7 programming tool. For more details on the pin locations, refer to the device pinout description.
Figure 6. Typical Remote ISP Interface
XTAL
HE10 CONNECTOR TYPE
TO PROGRAMMING TOOL
C
L0
ST7
C
L1
ISPSEL
V
SS
RESET
ISPCLK
ISPDATA
10K
Ω
47K
Ω
1
APPLICATION
5.5 MEMORY READ-OUT PROTECTION
The read-out protection is enabled through an option bit.
For FLASH devices, when this option is selected, the program and data stored in the FLASH memory are protected against read-out piracy (including a re-write protection). When this protection option is removed the entire FLASH program memory is first automatically erased. However, the E
2
PROM data memory (when available) can be protected only with ROM devices.
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ST72334J/N, ST72314J/N, ST72124J
6 DATA EEPROM
6.1 INTRODUCTION
The Electrically Erasable Programmable Read
Only Memory can be used as a non volatile backup for storing data. Using the EEPROM requires a basic access protocol described in this chapter.
6.2 MAIN FEATURES
■
■
■
■
■
■
Up to 16 Bytes programmed in the same cycle
EEPROM mono-voltage (charge pump)
Chained erase and programming cycles
Internal control of the global programming cycle duration
End of programming cycle interrupt flag
WAIT mode management
Figure 7. EEPROM Block Diagram
EEPROM INTERRUPT
FALLING
EDGE
DETECTOR
HIGH VOLTAGE
PUMP
EECSR
0 0
RESERVED
0 0 0
EEPROM
IE LAT PGM
ADDRESS
DECODER
4
ROW
DECODER
4
4
EEPROM
MEMORY MATRIX
(1 ROW = 16 x 8 BITS)
128
DATA
MULTIPLEXER
128
16 x 8 BITS
DATA LATCHES
ADDRESS BUS DATA BUS
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ST72334J/N, ST72314J/N, ST72124J
DATA EEPROM (Cont’d)
6.3 MEMORY ACCESS
The Data EEPROM memory read/write access modes are controlled by the LAT bit of the EEP-
ROM Control/Status register (EECSR). The flowchart in Figure 8 describes these different memory access modes.
Read Operation (LAT=0)
The EEPROM can be read as a normal ROM location when the LAT bit of the EECSR register is cleared. In a read cycle, the byte to be accessed is put on the data bus in less than 1 CPU clock cycle.
This means that reading data from EEPROM takes the same time as reading data from
EPROM, but this memory cannot be used to execute machine code.
Write Operation (LAT=1)
To access the write mode, the LAT bit has to be set by software (the PGM bit remains cleared).
When a write access to the EEPROM area occurs, the value is latched inside the 16 data latches according to its address.
Figure 8. Data EEPROM Programming Flowchart
When PGM bit is set by the software, all the previous bytes written in the data latches (up to 16) are programmed in the EEPROM cells. The effective high address (row) is determined by the last EEP-
ROM write sequence. To avoid wrong programming, the user must take care that all the bytes written between two programming sequences have the same high address: only the four Least
Significant Bits of the address can change.
At the end of the programming cycle, the PGM and
LAT bits are cleared simultaneously, and an interrupt is generated if the IE bit is set. The Data EEP-
ROM interrupt request is cleared by hardware when the Data EEPROM interrupt vector is fetched.
Note: Care should be taken during the programming cycle. Writing to the same memory location will over-program the memory (logical AND between the two write access data result) because the data latches are only cleared at the end of the programming cycle and by the falling edge of LAT bit.
It is not possible to read the latched data.
This note is ilustrated by the Figure 9 .
READ MODE
LAT=0
PGM=0
WRITE MODE
LAT=1
PGM=0
READ BYTES
IN EEPROM AREA
INTERRUPT GENERATION
IF IE=1
CLEARED BY HARDWARE
WRITE UP TO 16 BYTES
IN EEPROM AREA
(with the same 11 MSB of the address)
START PROGRAMMING CYCLE
LAT=1
PGM=1 (set by software)
0
LAT
1
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ST72334J/N, ST72314J/N, ST72124J
DATA EEPROM (Cont’d)
6.4 POWER SAVING MODES
Wait mode
The DATA EEPROM can enter WAIT mode on execution of the WFI instruction of the microcontroller. The DATA EEPROM will immediately enter this mode if there is no programming in progress, otherwise the DATA EEPROM will finish the cycle and then enter WAIT mode.
Halt mode
The DATA EEPROM immediatly enters HALT mode if the microcontroller executes the HALT instruction. Therefore the EEPROM will stop the function in progress, and data may be corrupted.
6.5 ACCESS ERROR HANDLING
If a read access occurs while LAT=1, then the data bus will not be driven.
If a write access occurs while LAT=0, then the data on the bus will not be latched.
If a programming cycle is interrupted (by software/
RESET action), the memory data will not be guaranteed.
Figure 9. Data EEPROM Programming Cycle
READ OPERATION NOT POSSIBLE READ OPERATION POSSIBLE
INTERNAL
PROGRAMMING
VOLTAGE
ERASE CYCLE WRITE CYCLE
WRITE OF
DATA LATCHES t
PROG
LAT
PGM
EEPROM INTERRUPT
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ST72334J/N, ST72314J/N, ST72124J
DATA EEPROM (Cont’d)
6.6 REGISTER DESCRIPTION
CONTROL/STATUS REGISTER (CSR)
Read /Write
Reset Value: 0000 0000 (00h)
7
0 0 0 0 0 IE
0
LAT PGM
Bit 7:3 = Reserved, forced by hardware to 0.
Bit 2 = IE
Interrupt enable
This bit is set and cleared by software. It enables the
Data EEPROM interrupt capability when the PGM bit is cleared by hardware. The interrupt request is automatically cleared when the software enters the interrupt routine.
0: Interrupt disabled
1: Interrupt enabled
Bit 1 = LAT
Latch Access Transfer
This bit is set by software. It is cleared by hardware at the end of the programming cycle. It can only be cleared by software if PGM bit is cleared.
0: Read mode
1: Write mode
Bit 0 = PGM
Programming control and status
This bit is set by software to begin the programming cycle. At the end of the programming cycle, this bit is cleared by hardware and an interrupt is generated if the ITE bit is set.
0: Programming finished or not yet started
1: Programming cycle is in progress
Note: if the PGM bit is cleared during the programming cycle, the memory data is not guaranteed
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ST72334J/N, ST72314J/N, ST72124J
7 DATA EEPROM Register Map and Reset Values
Address
(Hex.)
002Ch
Register
Label
EECSR
Reset Value
7
0
6
0
5
0
4
0
3
0
2
IE
0
1
RWM
0
0
PGM
0
7.1 READ-OUT PROTECTION OPTION
The Data EEPROM can be optionally read-out protected in ST72334 ROM devices (see option list on
page 146 ). ST72C334 Flash devices do not
have this protection option.
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ST72334J/N, ST72314J/N, ST72124J
8 CENTRAL PROCESSING UNIT
8.1 INTRODUCTION
This CPU has a full 8-bit architecture and contains six internal registers allowing efficient 8-bit data manipulation.
8.2 MAIN FEATURES
■
■
■
■
■
■
■
■
63 basic instructions
Fast 8-bit by 8-bit multiply
17 main addressing modes
Two 8-bit index registers
16-bit stack pointer
Low power modes
Maskable hardware interrupts
Non-maskable software interrupt
8.3 CPU REGISTERS
The 6 CPU registers shown in Figure 10 are not present in the memory mapping and are accessed by specific instructions.
Figure 10. CPU Registers
7 0
Accumulator (A)
The Accumulator is an 8-bit general purpose register used to hold operands and the results of the arithmetic and logic calculations and to manipulate data.
Index Registers (X and Y)
In indexed addressing modes, these 8-bit registers are used to create either effective addresses or temporary storage areas for data manipulation.
(The Cross-Assembler generates a precede instruction (PRE) to indicate that the following instruction refers to the Y register.)
The Y register is not affected by the interrupt automatic procedures (not pushed to and popped from the stack).
Program Counter (PC)
The program counter is a 16-bit register containing the address of the next instruction to be executed by the CPU. It is made of two 8-bit registers PCL
(Program Counter Low which is the LSB) and PCH
(Program Counter High which is the MSB).
ACCUMULATOR
RESET VALUE = XXh
7 0
RESET VALUE = XXh
7 0
X INDEX REGISTER
Y INDEX REGISTER
15 PCH 8
RESET VALUE = XXh
7 PCL 0
RESET VALUE = RESET VECTOR @ FFFEh-FFFFh
7
1
RESET VALUE = 1
1 1 H I N Z
1 1 X 1 X X X
0
C
15 8 7 0
PROGRAM COUNTER
CONDITION CODE REGISTER
STACK POINTER
RESET VALUE = STACK HIGHER ADDRESS
X = Undefined Value
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ST72334J/N, ST72314J/N, ST72124J
CPU REGISTERS (Cont’d)
CONDITION CODE REGISTER (CC)
Read/Write
Reset Value: 111x1xxx
7
1 1 1 H I N Z
0
C
The 8-bit Condition Code register contains the interrupt mask and four flags representative of the result of the instruction just executed. This register can also be handled by the PUSH and POP instructions.
These bits can be individually tested and/or controlled by specific instructions.
Bit 2 = N
Negative
.
This bit is set and cleared by hardware. It is representative of the result sign of the last arithmetic, logical or data manipulation. It is a copy of the 7 th bit of the result.
0: The result of the last operation is positive or null.
1: The result of the last operation is negative
(i.e. the most significant bit is a logic 1).
This bit is accessed by the JRMI and JRPL instructions.
Bit 4 = H
Half carry
.
This bit is set by hardware when a carry occurs between bits 3 and 4 of the ALU during an ADD or
ADC instruction. It is reset by hardware during the same instructions.
0: No half carry has occurred.
1: A half carry has occurred.
This bit is tested using the JRH or JRNH instruction. The H bit is useful in BCD arithmetic subroutines.
Bit 1 = Z
Zero
.
This bit is set and cleared by hardware. This bit indicates that the result of the last arithmetic, logical or data manipulation is zero.
0: The result of the last operation is different from zero.
1: The result of the last operation is zero.
This bit is accessed by the JREQ and JRNE test instructions.
Bit 0 = C
Carry/borrow.
This bit is set and cleared by hardware and software. It indicates an overflow or an underflow has occurred during the last arithmetic operation.
0: No overflow or underflow has occurred.
1: An overflow or underflow has occurred.
This bit is driven by the SCF and RCF instructions and tested by the JRC and JRNC instructions. It is also affected by the “bit test and branch”, shift and rotate instructions.
Bit 3 = I
Interrupt mask
.
This bit is set by hardware when entering in interrupt or by software to disable all interrupts except the TRAP software interrupt. This bit is cleared by software.
0: Interrupts are enabled.
1: Interrupts are disabled.
This bit is controlled by the RIM, SIM and IRET instructions and is tested by the JRM and JRNM instructions.
Note: Interrupts requested while I is set are latched and can be processed when I is cleared.
By default an interrupt routine is not interruptable because the I bit is set by hardware at the start of the routine and reset by the IRET instruction at the end of the routine. If the I bit is cleared by software in the interrupt routine, pending interrupts are serviced regardless of the priority level of the current interrupt routine.
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ST72334J/N, ST72314J/N, ST72124J
CENTRAL PROCESSING UNIT (Cont’d)
Stack Pointer (SP)
Read/Write
Reset Value: 01 FFh
15 8
1 0 0 0 0 0 0 0
7 0
SP7 SP6 SP5 SP4 SP3 SP2 SP1 SP0
The Stack Pointer is a 16-bit register which is always pointing to the next free location in the stack.
It is then decremented after data has been pushed onto the stack and incremented before data is popped from the stack (see
Since the stack is 256 bytes deep, the 8th most significant bits are forced by hardware. Following an MCU Reset, or after a Reset Stack Pointer instruction (RSP), the Stack Pointer contains its reset value (the SP7 to SP0 bits are set) which is the stack higher address.
Figure 11. Stack Manipulation Example
@ 0100h
CALL
Subroutine
Interrupt
Event
PUSH Y
The least significant byte of the Stack Pointer
(called S) can be directly accessed by a LD instruction.
Note: When the lower limit is exceeded, the Stack
Pointer wraps around to the stack upper limit, without indicating the stack overflow. The previously stored information is then overwritten and therefore lost. The stack also wraps in case of an underflow.
The stack is used to save the return address during a subroutine call and the CPU context during an interrupt. The user may also directly manipulate the stack by means of the PUSH and POP instructions. In the case of an interrupt, the PCL is stored at the first location pointed to by the SP. Then the other registers are stored in the next locations as
– When an interrupt is received, the SP is decremented and the context is pushed on the stack.
– On return from interrupt, the SP is incremented and the context is popped from the stack.
A subroutine call occupies two locations and an interrupt five locations in the stack area.
POP Y IRET RET or RSP
SP
SP
@ 01FFh
PCH
PCL
CC
A
X
PCH
PCL
PCH
PCL
Stack Higher Address = 01FFh
Stack Lower Address = 0100h
SP
Y
CC
A
X
PCH
PCL
PCH
PCL
SP
CC
A
X
PCH
PCL
PCH
PCL
SP
PCH
PCL
SP
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ST72334J/N, ST72314J/N, ST72124J
9 SUPPLY, RESET AND CLOCK MANAGEMENT
The ST72334J/N, ST72314J/N and ST72124J microcontrollers include a range of utility features for securing the application in critical situations (for example in case of a power brown-out), and reducing the number of external components. An overview is shown in
See
Section 16 "ELECTRICAL CHARACTERIS-
TICS" on page 107 for more details.
■
■
Multi-Oscillator (MO)
– 4 Crystal/Ceramic resonator oscillators
– 1 External RC oscillator
– 1 Internal RC oscillator
Clock Security System (CSS)
– Clock Filter
– Backup Safe Oscillator
Main Features
■
■
Supply Manager with main supply low voltage detection (LVD)
Reset Sequence Manager (RSM)
Figure 12. Clock, Reset and Supply Block Diagram
OSC2
OSC1
RESET
VDD
VSS
MULTI-
OSCILLATOR
(MO)
CLOCK SECURITY SYSTEM
(CSS)
CLOCK
FILTER
SAFE
OSC f
OSC
TO
MAIN CLOCK
CONTROLLER
RESET SEQUENCE
MANAGER
(RSM)
FROM
WATCHDOG
PERIPHERAL
LOW VOLTAGE
DETECTOR
(LVD)
CRSR
0 0 0 RF
LVD
0 IE
CSS
D
WDG
RF
CSS INTERRUPT
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ST72334J/N, ST72314J/N, ST72124J
9.1 LOW VOLTAGE DETECTOR (LVD)
To allow the integration of power management features in the application, the Low Voltage Detector function (LVD) generates a static reset when the V
DD
supply voltage is below a V
IT-
reference value. This means that it secures the power-up as well as the power-down keeping the ST7 in reset.
The V
IT-
reference value for a voltage drop is lower than the V
IT+
reference value for power-on in order to avoid a parasitic reset when the MCU starts running and sinks current on the supply (hysteresis).
The LVD Reset circuitry generates a reset when
V
DD
is below:
– V
IT+
when V
DD
is rising
– V
IT-
when V
DD
is falling
The LVD function is illustrated in the Figure 13 .
Provided the minimum V
DD
value (guaranteed for the oscillator frequency) is above V
ITcan only be in two modes:
, the MCU
– under full software control
– in static safe reset
Figure 13. Low Voltage Detector vs Reset
V
DD
In these conditions, secure operation is always ensured for the application without the need for external reset hardware.
During a Low Voltage Detector Reset, the RESET pin is held low, thus permitting the MCU to reset other devices.
Notes:
1. The LVD allows the device to be used without any external RESET circuitry.
2. Three different reference levels are selectable through the option byte according to the application requirement.
LVD application note
Application software can detect a reset caused by the LVD by reading the LVDRF bit in the CRSR register.
This bit is set by hardware when a LVD reset is generated and cleared by software (writing zero).
V hyst
V
IT+
V
IT-
RESET
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ST72334J/N, ST72314J/N, ST72124J
9.2 RESET SEQUENCE MANAGER (RSM)
9.2.1 Introduction
The reset sequence manager includes three RE-
SET sources as shown in Figure 15 :
■
■
■
External RESET source pulse
Internal LVD RESET (Low Voltage Detection)
Internal WATCHDOG RESET
These sources act on the RESET pin and it is always kept low during the delay phase.
The RESET service routine vector is fixed at addresses FFFEh-FFFFh in the ST7 memory map.
The basic RESET sequence consists of 3 phases as shown in Figure 14 :
■
Delay depending on the RESET source
■
■
4096 CPU clock cycle delay
RESET vector fetch
Figure 15. Reset Block Diagram
The 4096 CPU clock cycle delay allows the oscillator to stabilise and ensures that recovery has taken place from the Reset state.
The RESET vector fetch phase duration is 2 clock cycles.
Figure 14. RESET Sequence Phases
DELAY
RESET
INTERNAL RESET
4096 CLOCK CYCLES
FETCH
VECTOR
V
DD
R
ON f
CPU
INTERNAL
RESET
RESET
WATCHDOG RESET
LVD RESET
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ST72334J/N, ST72314J/N, ST72124J
RESET SEQUENCE MANAGER (Cont’d)
9.2.2 Asynchronous External RESET pin
The RESET pin is both an input and an open-drain output with integrated R
ON
weak pull-up resistor.
This pull-up has no fixed value but varies in accordance with the input voltage. It can be pulled low by external circuitry to reset the device. See electrical characteristics section for more details.
A RESET signal originating from an external source must have a duration of at least t h(RSTL)in
in order to be recognized. This detection is asynchronous and therefore the MCU can enter reset state even in HALT mode.
The RESET pin is an asynchronous signal which plays a major role in EMS performance. In a noisy environment, it is recommended to follow the guidelines mentioned in the electrical characteristics section.
Two RESET sequences can be associated with this RESET source: short or long external reset pulse (see Figure 16 ).
Starting from the external RESET pulse recognition, the device RESET pin acts as an output that is pulled low during at least t w(RSTL)out
.
Figure 16. RESET Sequences
V
DD
V
IT+
V
IT-
9.2.3 Internal Low Voltage Detection RESET
Two different RESET sequences caused by the internal LVD circuitry can be distinguished:
■
■
Power-On RESET
Voltage Drop RESET
The device RESET pin acts as an output that is pulled low when V
V
DD
<V
DD
<V
IT+
(rising edge) or
IT-
(falling edge) as shown in Figure 16 .
The LVD filters spikes on V
DD avoid parasitic resets.
larger than t g(VDD) to
9.2.4 Internal Watchdog RESET
The RESET sequence generated by a internal
Watchdog counter overflow is shown in Figure 16 .
Starting from the Watchdog counter underflow, the device RESET pin acts as an output that is pulled low during at least t w(RSTL)out
.
RUN
LVD
RESET
DELAY
0000000000
0000000000
000
000 RUN
SHORT EXT.
RESET
DELAY
00000000000
00000000000
000
000 RUN
LONG EXT.
00000000000
00000000000
DELAY
000
000 RUN
WATCHDOG
0000000000
0000000000
DELAY
0000
0000 RUN t w(RSTL)out t h(RSTL)in t h(RSTL)in t w(RSTL)out
EXTERNAL
RESET
SOURCE
RESET PIN
WATCHDOG
RESET
0000000000000
0000000000000 INTERNAL RESET (4096 T
FETCH VECTOR
CPU
)
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ST72334J/N, ST72314J/N, ST72124J
9.3 MULTI-OSCILLATOR (MO)
The main clock of the ST7 can be generated by four different source types coming from the multioscillator block:
■
■ an external source
4 crystal or ceramic resonator oscillators
■
■ an external RC oscillator an internal high frequency RC oscillator
Each oscillator is optimized for a given frequency range in terms of consumption and is selectable through the option byte. The associated hardware configuration are shown in Table 3 . Refer to the electrical characteristics section for more details.
External Clock Source
In this external clock mode, a clock signal (square, sinus or triangle) with ~50% duty cycle has to drive the OSC1 pin while the OSC2 pin is tied to ground.
Crystal/Ceramic Oscillators
This family of oscillators has the advantage of producing a very accurate rate on the main clock of the ST7. The selection within a list of 4 oscillators with different frequency ranges has to be done by option byte in order to reduce consumption. In this mode of the multi-oscillator, the resonator and the load capacitors have to be placed as close as possible to the oscillator pins in order to minimize output distortion and start-up stabilization time. The loading capacitance values must be adjusted according to the selected oscillator.
These oscillators are not stopped during the
RESET phase to avoid losing time in the oscillator start-up phase.
External RC Oscillator
This oscillator allows a low cost solution for the main clock of the ST7 using only an external resistor and an external capacitor. The frequency of the external RC oscillator (in the range of some MHz.) is fixed by the resistor and the capacitor values.
Consequently in this MO mode, the accuracy of the clock is directly linked to the accuracy of the discrete components. The corresponding formula is f
OSC
=4/(R
EX
C
EX
)
Internal RC Oscillator
The internal RC oscillator mode is based on the same principle as the external RC oscillator including the resistance and the capacitance of the device. This mode is the most cost effective one with the drawback of a lower frequency accuracy. Its frequency is in the range of several MHz.
In this mode, the two oscillator pins have to be tied to ground.
Table 3. ST7 Clock Sources
Hardware Configuration
C
L1
LOAD
CAPACITORS
OSC1
ST7
OSC2
C
L2
R
OSC1
ST7
OSC2
EXTERNAL
SOURCE
EX
OSC1
ST7
OSC2
OSC1
ST7
OSC2
C
EX
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9.4 CLOCK SECURITY SYSTEM (CSS)
The Clock Security System (CSS) protects the
ST7 against main clock problems. To allow the integration of the security features in the applications, it is based on a clock filter control and an Internal safe oscillator. The CSS can be enabled or disabled by option byte.
9.4.1 Clock Filter Control
The clock filter is based on a clock frequency limitation function.
This filter function is able to detect and filter high frequency spikes on the ST7 main clock.
If the oscillator is not working properly (e.g. working at a harmonic frequency of the resonator), the current active oscillator clock can be totally filtered, and then no clock signal is available for the
ST7 from this oscillator anymore. If the original clock source recovers, the filtering is stopped automatically and the oscillator supplies the ST7 clock.
9.4.2 Safe Oscillator Control
The safe oscillator of the CSS block is a low frequency back-up clock source (see Figure 17 ).
If the clock signal disappears (due to a broken or disconnected resonator...) during a safe oscillator period, the safe oscillator delivers a low frequency clock signal which allows the ST7 to perform some rescue operations.
Automatically, the ST7 clock source switches back from the safe oscillator if the original clock source recovers.
Limitation detection
The automatic safe oscillator selection is notified by hardware setting the CSSD bit of the CRSR register. An interrupt can be generated if the CS-
SIE bit has been previously set.
These two bits are described in the CRSR register description.
9.4.3 Low Power Modes
Mode Description
WAIT
HALT
No effect on CSS. CSS interrupt cause the device to exit from Wait mode.
The CRSR register is frozen. The CSS (including the safe oscillator) is disabled until
HALT mode is exited. The previous CSS configuration resumes when the MCU is woken up by an interrupt with “exit from
HALT mode” capability or from the counter reset value when the MCU is woken up by a
RESET.
9.4.4 Interrupts
The CSS interrupt event generates an interrupt if the corresponding Enable Control Bit (CSSIE) is set and the interrupt mask in the CC register is reset (RIM instruction).
Interrupt Event
Event
Flag
Enable
Control
Bit
Exit from
Wait
CSS event detection
(safe oscillator activated as main clock)
CSSD CSSIE Yes
Exit from
Halt
1)
No
Note 1: This interrupt allows to exit from active-halt mode if this mode is available in the MCU.
Figure 17. Clock Filter Function and Safe Oscillator Function f
OSC
/2 f
CPU f
OSC
/2 f
SFOSC f
CPU
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9.5 SUPPLY, RESET AND CLOCK REGISTER DESCRIPTION
Read /Write
Reset Value: 000x 000x (xxh)
7
0 0 0
LVD
RF
0
CSS
IE
Bit 7:5 = Reserved, always read as 0.
0
CSS
D
WDG
RF
Bit 1 = CSSD
Clock security system detection
This bit indicates that the safe oscillator of the clock security system block has been selected by hardware due to a disturbance on the main clock signal (f
OSC
). It is set by hardware and cleared by reading the CRSR register when the original oscillator recovers.
0: Safe oscillator is not active
1: Safe oscillator has been activated
When the CSS is disabled by option byte, the
CSSD bit value is forced to 0.
Bit 4 = LVDRF
LVD reset flag
This bit indicates that the last RESET was generated by the LVD block. It is set by hardware (LVD reset) and cleared by software (writing zero). See
WDGRF flag description for more details. When the LVD is disabled by option byte, the LVDRF bit value is undefined.
Bit 3 = Reserved, always read as 0.
Bit 0 = WDGRF
Watchdog reset flag
This bit indicates that the last RESET was generated by the watchdog peripheral. It is set by hardware (Watchdog RESET) and cleared by software
(writing zero) or an LVD RESET (to ensure a stable cleared state of the WDGRF flag when the
CPU starts).
Combined with the LVDRF flag information, the flag description is given by the following table.
Bit 2 = CSSIE
Clock security syst
.
interrupt enable
This bit enables the interrupt when a disturbance is detected by the clock security system (CSSD bit set). It is set and cleared by software.
0: Clock security system interrupt disabled
1: Clock security system interrupt enabled
Refer to Table 5, “Interrupt mapping,” on page 34
for more details on the CSS interrupt vector. When the CSS is disabled by option byte, the CSSIE bit has no effect.
RESET Sources
External RESET pin
Watchdog
LVD
LVDRF WDGRF
0
0
1
0
1
X
Application notes
The LVDRF flag is not cleared when another RE-
SET type occurs (external or watchdog), the
LVDRF flag remains set to keep trace of the original failure.
In this case, a watchdog reset can be detected by software while an external reset can not.
Table 4. Clock, Reset and Supply Register Map and Reset Values
Address
(Hex.)
002Bh
Register
Label
CRSR
Reset Value
7
0
6
0
5
0
4
LVDRF x
3
0
2
CFIE
0
1
CSSD
0
0
WDGRF x
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10 INTERRUPTS
The ST7 core may be interrupted by one of two different methods: maskable hardware interrupts as listed in the Interrupt Mapping Table and a nonmaskable software interrupt (TRAP). The Interrupt processing flowchart is shown in Figure 18 .
The maskable interrupts must be enabled by clearing the I bit in order to be serviced. However, disabled interrupts may be latched and processed when they are enabled (see external interrupts subsection).
Note: After reset, all interrupts are disabled.
When an interrupt has to be serviced:
– Normal processing is suspended at the end of the current instruction execution.
– The PC, X, A and CC registers are saved onto the stack.
– The I bit of the CC register is set to prevent additional interrupts.
– The PC is then loaded with the interrupt vector of the interrupt to service and the first instruction of the interrupt service routine is fetched (refer to the Interrupt Mapping Table for vector addresses).
The interrupt service routine should finish with the
IRET instruction which causes the contents of the saved registers to be recovered from the stack.
Note: As a consequence of the IRET instruction, the I bit will be cleared and the main program will resume.
Priority Management
By default, a servicing interrupt cannot be interrupted because the I bit is set by hardware entering in interrupt routine.
In the case when several interrupts are simultaneously pending, an hardware priority defines which one will be serviced first (see the Interrupt Mapping Table).
Interrupts and Low Power Mode
All interrupts allow the processor to leave the
WAIT low power mode. Only external and specifically mentioned interrupts allow the processor to leave the HALT low power mode (refer to the “Exit from HALT“ column in the Interrupt Mapping Table).
10.1 NON MASKABLE SOFTWARE
INTERRUPT
This interrupt is entered when the TRAP instruction is executed regardless of the state of the I bit.
It will be serviced according to the flowchart on
Figure 18 .
10.2 EXTERNAL INTERRUPTS
External interrupt vectors can be loaded into the
PC register if the corresponding external interrupt occurred and if the I bit is cleared. These interrupts allow the processor to leave the Halt low power mode.
The external interrupt polarity is selected through the miscellaneous register or interrupt register (if available).
An external interrupt triggered on edge will be latched and the interrupt request automatically cleared upon entering the interrupt service routine.
If several input pins, connected to the same interrupt vector, are configured as interrupts, their signals are logically NANDed before entering the edge/level detection block.
Caution: The type of sensitivity defined in the Miscellaneous or Interrupt register (if available) applies to the ei source. In case of a NANDed source
(as described on the I/O ports section), a low level on an I/O pin configured as input with interrupt, masks the interrupt request even in case of risingedge sensitivity.
10.3 PERIPHERAL INTERRUPTS
Different peripheral interrupt flags in the status register are able to cause an interrupt when they are active if both:
– The I bit of the CC register is cleared.
– The corresponding enable bit is set in the control register.
If any of these two conditions is false, the interrupt is latched and thus remains pending.
Clearing an interrupt request is done by:
– Writing “0” to the corresponding bit in the status register or
– Access to the status register while the flag is set followed by a read or write of an associated register.
Note: the clearing sequence resets the internal latch. A pending interrupt (i.e. waiting for being enabled) will therefore be lost if the clear sequence is executed.
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INTERRUPTS (Cont’d)
Figure 18. Interrupt Processing Flowchart
FROM RESET
I BIT SET?
Y
N
FETCH NEXT INSTRUCTION
N INTERRUPT
PENDING?
Y
N
IRET?
Y
STACK PC, X, A, CC
SET I BIT
LOAD PC FROM INTERRUPT VECTOR
EXECUTE INSTRUCTION
RESTORE PC, X, A, CC FROM STACK
THIS CLEARS I BIT BY DEFAULT
Table 5. Interrupt mapping
N°
0
1
4
5
6
2
3
7
8
9
10
11 Data-EEPROM Data EEPROM Interrupt
12
13
Source
Block
RESET
TRAP
MCC/RTC
CSS ei0 ei1 ei2 ei3
SPI
TIMER A
TIMER B
SCI
Reset
Software Interrupt
Not used
Main Clock Controller Time Base Interrupt or Clock Security System Interrupt
External Interrupt Port A3..0
External Interrupt Port F2..0
External Interrupt Port B3..0
External Interrupt Port B7..4
Not used
SPI Peripheral Interrupts
TIMER A Peripheral Interrupts
TIMER B Peripheral Interrupts
SCI Peripheral Interrupts
Not used
Description
Register
Label
N/A
MCCSR
CRSR
N/A
SPISR
TASR
TBSR
SCISR
EECSR
Priority
Order
Highest
Priority
Lowest
Priority
Exit from
HALT
1) yes no yes no
Address
Vector
FFFEh-FFFFh
FFFCh-FFFDh
FFFAh-FFFBh
FFF8h-FFF9h
FFF6h-FFF7h
FFF4h-FFF5h
FFF2h-FFF3h
FFF0h-FFF1h
FFEEh-FFEFh
FFECh-FFEDh
FFEAh-FFEBh
FFE8h-FFE9h
FFE6h-FFE7h
FFE4h-FFE5h
FFE2h-FFE3h
FFE0h-FFE1h
Note 1. Valid for HALT and ACTIVE-HALT modes except for the MCC/RTC or CSS interrupt source which exits from
ACTIVE-HALT mode only.
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11 POWER SAVING MODES
11.1 INTRODUCTION
To give a large measure of flexibility to the application in terms of power consumption, four main power saving modes are implemented in the ST7
(see Figure 19 ): SLOW, WAIT (SLOW WAIT), AC-
TIVE HALT and HALT.
After a RESET the normal operating mode is selected by default (RUN mode). This mode drives the device (CPU and embedded peripherals) by means of a master clock which is based on the main oscillator frequency divided by 2 (f
CPU
).
From RUN mode, the different power saving modes may be selected by setting the relevant register bits or by calling the specific ST7 software instruction whose action depends on the oscillator status.
Figure 19. Power Saving Mode Transitions
High
RUN
11.2 SLOW MODE
This mode has two targets:
– To reduce power consumption by decreasing the internal clock in the device,
– To adapt the internal clock frequency (f
CPU the available supply voltage.
) to
SLOW mode is controlled by three bits in the
MISCR1 register: the SMS bit which enables or disables Slow mode and two CPx bits which select the internal slow frequency (f
CPU
).
In this mode, the oscillator frequency can be divided by 4, 8, 16 or 32 instead of 2 in normal operating mode. The CPU and peripherals are clocked at this lower frequency.
Note: SLOW-WAIT mode is activated when entering the WAIT mode while the device is already in
SLOW mode.
Figure 20. SLOW Mode Clock Transitions f
OSC
/4 f
OSC
/8 f
OSC
/2 f
CPU
SLOW
WAIT f
OSC
/2
CP1:0
SMS
00 01
SLOW WAIT
NORMAL RUN MODE
REQUEST
ACTIVE HALT
NEW SLOW
FREQUENCY
REQUEST
HALT
Low
POWER CONSUMPTION
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POWER SAVING MODES (Cont’d)
11.3 WAIT MODE
WAIT mode places the MCU in a low power consumption mode by stopping the CPU.
This power saving mode is selected by calling the
‘WFI’ instruction.
All peripherals remain active. During WAIT mode, the I bit of the CC register is cleared, to enable all interrupts. All other registers and memory remain unchanged. The MCU remains in WAIT mode until an interrupt or RESET occurs, whereupon the Program Counter branches to the starting address of the interrupt or Reset service routine.
The MCU will remain in WAIT mode until a Reset or an Interrupt occurs, causing it to wake up.
Refer to
Figure 21. WAIT Mode Flow-chart
WFI INSTRUCTION
OSCILLATOR
PERIPHERALS
CPU
I BIT
ON
ON
OFF
0
N
N
RESET
Y
INTERRUPT
Y
OSCILLATOR
PERIPHERALS
CPU
I BIT
ON
OFF
ON
0
4096 CPU CLOCK CYCLE
DELAY
OSCILLATOR
PERIPHERALS
CPU
I BIT
ON
ON
ON
X
1)
FETCH RESET VECTOR
OR SERVICE INTERRUPT
Note:
1. Before servicing an interrupt, the CC register is pushed on the stack. The I bit of the CC register is set during the interrupt routine and cleared when the CC register is popped.
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POWER SAVING MODES (Cont’d)
11.4 ACTIVE-HALT AND HALT MODES
ACTIVE-HALT and HALT modes are the two lowest power consumption modes of the MCU. They are both entered by executing the ‘HALT’ instruction. The decision to enter either in ACTIVE-HALT or HALT mode is given by the MCC/RTC interrupt enable flag (OIE bit in MCCSR register).
MCCSR
OIE bit
0
1
Power Saving Mode entered when HALT instruction is executed
HALT mode
ACTIVE-HALT mode
11.4.1 ACTIVE-HALT MODE
ACTIVE-HALT mode is the lowest power consumption mode of the MCU with a real time clock available. It is entered by executing the ‘HALT’ instruction when the OIE bit of the Main Clock Con-
troller Status register (MCCSR) is set (see Section
14.2 "MAIN CLOCK CONTROLLER WITH REAL
TIME CLOCK TIMER (MCC/RTC)" on page 52
for more details on the MCCSR register).
The MCU can exit ACTIVE-HALT mode on reception of either an MCC/RTC interrupt, a specific interrupt (see
Table 5, “Interrupt mapping,” on page 34 ) or a RESET. When exiting ACTIVE-
HALT mode by means of a RESET or an interrupt, a 4096 CPU cycle delay occurs. After the start up delay, the CPU resumes operation by servicing the interrupt or by fetching the reset vector which woke it up (see
When entering ACTIVE-HALT mode, the I bit in the CC register is cleared to enable interrupts.
Therefore, if an interrupt is pending, the MCU wakes up immediately.
In ACTIVE-HALT mode, only the main oscillator and its associated counter (MCC/RTC) are running to keep a wake-up time base. All other peripherals are not clocked except those which get their clock supply from another clock generator (such as external or auxiliary oscillator).
The safeguard against staying locked in ACTIVE-
HALT mode is provided by the oscillator interrupt.
Note: As soon as the interrupt capability of one of the oscillators is selected (MCCSR.OIE bit set), entering ACTIVE-HALT mode while the Watchdog is active does not generate a RESET.
This means that the device cannot spend more than a defined delay in this power saving mode.
Figure 22. ACTIVE-HALT Timing Overview
RUN
ACTIVE
HALT
4096 CPU CYCLE
DELAY
RUN
HALT
INSTRUCTION
[MCCSR.OIE=1]
RESET
OR
INTERRUPT
FETCH
VECTOR
Figure 23. ACTIVE-HALT Mode Flow-chart
HALT INSTRUCTION
(MCCSR.OIE=1)
OSCILLATOR
PERIPHERALS
CPU
I BIT
ON
1)
OFF
OFF
0
N
N
RESET
Y
INTERRUPT 2)
Y OSCILLATOR
PERIPHERALS
CPU
I BIT
ON
1)
OFF
ON
X 3)
4096 CPU CLOCK CYCLE
DELAY
OSCILLATOR
PERIPHERALS
CPU
I BITS
ON
ON
ON
X 3)
FETCH RESET VECTOR
OR SERVICE INTERRUPT
Notes:
1. Peripheral clocked with an external clock source can still be active.
2. Only the MCC/RTC interrupt and some specific interrupts can exit the MCU from ACTIVE-HALT mode (such as external interrupt). Refer to
Table 5, “Interrupt mapping,” on page 34
for more details.
3. Before servicing an interrupt, the CC register is pushed on the stack. The I bit of the CC register is set during the interrupt routine and cleared when the CC register is popped.
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POWER SAVING MODES (Cont’d)
11.4.2 HALT MODE
The HALT mode is the lowest power consumption mode of the MCU. It is entered by executing the
‘HALT’ instruction when the OIE bit of the Main
Clock Controller Status register (MCCSR) is
cleared (see Section 14.2 "MAIN CLOCK CON-
TROLLER WITH REAL TIME CLOCK TIMER
(MCC/RTC)" on page 52 for more details on the
MCCSR register).
The MCU can exit HALT mode on reception of either a specific interrupt (see
Table 5, “Interrupt mapping,” on page 34 ) or a RESET. When exiting
HALT mode by means of a RESET or an interrupt, the oscillator is immediately turned on and the
4096 CPU cycle delay is used to stabilize the oscillator. After the start up delay, the CPU resumes operation by servicing the interrupt or by fetching the reset vector which woke it up (see
).
When entering HALT mode, the I bit in the CC register is forced to 0 to enable interrupts. Therefore, if an interrupt is pending, the MCU wakes immediately.
In HALT mode, the main oscillator is turned off causing all internal processing to be stopped, including the operation of the on-chip peripherals.
All peripherals are not clocked except the ones which get their clock supply from another clock generator (such as an external or auxiliary oscillator).
The compatibility of Watchdog operation with
HALT mode is configured by the “WDGHALT” option bit of the option byte. The HALT instruction when executed while the Watchdog system is enabled, can generate a Watchdog RESET (see
Section 18.1 on page 144 for more details).
Figure 24. HALT Timing Overview
RUN HALT
HALT
INSTRUCTION
[MCCSR.OIE=0]
4096 CPU CYCLE
DELAY
RESET
OR
INTERRUPT
RUN
FETCH
VECTOR
Figure 25. HALT Mode Flow-chart
HALT INSTRUCTION
(MCCSR.OIE=0)
ENABLE
0
WATCHDOG
DISABLE
WDGHALT 1)
1
WATCHDOG
RESET
OSCILLATOR
PERIPHERALS
CPU
I BIT
OFF
2)
OFF
OFF
0
N
N
RESET
Y
INTERRUPT 3)
Y OSCILLATOR
PERIPHERALS
CPU
I BIT
ON
OFF
ON
X 4)
4096 CPU CLOCK CYCLE
DELAY
OSCILLATOR
PERIPHERALS
CPU
I BITS
ON
ON
ON
X 4)
FETCH RESET VECTOR
OR SERVICE INTERRUPT
Notes:
1. WDGHALT is an option bit. See option byte section for more details.
2. Peripheral clocked with an external clock source can still be active.
3. Only some specific interrupts can exit the MCU from HALT mode (such as external interrupt). Refer to
Table 5, “Interrupt mapping,” on page 34 for
more details.
4. Before servicing an interrupt, the CC register is pushed on the stack. The I bit of the CC register is set during the interrupt routine and cleared when the CC register is popped.
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12 I/O PORTS
12.1 INTRODUCTION
The I/O ports offer different functional modes:
– transfer of data through digital inputs and outputs and for specific pins:
– external interrupt generation
– alternate signal input/output for the on-chip peripherals.
An I/O port contains up to 8 pins. Each pin can be programmed independently as digital input (with or without interrupt generation) or digital output.
12.2 FUNCTIONAL DESCRIPTION
Each port has 2 main registers:
– Data Register (DR)
– Data Direction Register (DDR) and one optional register:
– Option Register (OR)
Each I/O pin may be programmed using the corresponding register bits in the DDR and OR registers: bit X corresponding to pin X of the port. The same correspondence is used for the DR register.
The following description takes into account the
OR register, (for specific ports which do not provide this register refer to the I/O Port Implementation section). The generic I/O block diagram is shown in Figure 26
12.2.1 Input Modes
The input configuration is selected by clearing the corresponding DDR register bit.
In this case, reading the DR register returns the digital value applied to the external I/O pin.
Different input modes can be selected by software through the OR register.
Notes:
1. Writing the DR register modifies the latch value but does not affect the pin status.
2. When switching from input to output mode, the
DR register has to be written first to drive the correct level on the pin as soon as the port is configured as an output.
3. Do not use read/modify/write instructions (BSET or BRES) to modify the DR register
External interrupt function
When an I/O is configured as Input with Interrupt, an event on this I/O can generate an external interrupt request to the CPU.
Each pin can independently generate an interrupt request. The interrupt sensitivity is independently programmable using the sensitivity bits in the Miscellaneous register.
Each external interrupt vector is linked to a dedicated group of I/O port pins (see pinout description and interrupt section). If several input pins are selected simultaneously as interrupt source, these are logically NANDed. For this reason if one of the interrupt pins is tied low, it masks the other ones.
In case of a floating input with interrupt configuration, special care must be taken when changing the configuration (see Figure 27 ).
The external interrupts are hardware interrupts, which means that the request latch (not accessible directly by the application) is automatically cleared when the corresponding interrupt vector is fetched. To clear an unwanted pending interrupt by software, the sensitivity bits in the Miscellaneous register must be modified.
12.2.2 Output Modes
The output configuration is selected by setting the corresponding DDR register bit. In this case, writing the DR register applies this digital value to the
I/O pin through the latch. Then reading the DR register returns the previously stored value.
Two different output modes can be selected by software through the OR register: Output push-pull and open-drain.
DR register value and output pin status:
DR
0
1
Push-pull
V
SS
V
DD
Open-drain
Vss
Floating
12.2.3 Alternate Functions
When an on-chip peripheral is configured to use a pin, the alternate function is automatically selected. This alternate function takes priority over the standard I/O programming.
When the signal is coming from an on-chip peripheral, the I/O pin is automatically configured in output mode (push-pull or open drain according to the peripheral).
When the signal is going to an on-chip peripheral, the I/O pin must be configured in input mode. In this case, the pin state is also digitally readable by addressing the DR register.
Note: Input pull-up configuration can cause unexpected value at the input of the alternate peripheral input. When an on-chip peripheral use a pin as input and output, this pin has to be configured in input floating mode.
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I/O PORTS (Cont’d)
Figure 26. I/O Port General Block Diagram
REGISTER
ACCESS
ALTERNATE
OUTPUT
1
0
ALTERNATE
ENABLE
DR
DDR
OR
OR SEL
If implemented
V
DD
P-BUFFER
(see table below)
PULL-UP
(see table below)
V
DD
PULL-UP
CONFIGURATION
PAD
N-BUFFER
DDR SEL
DIODES
(see table below)
ANALOG
INPUT
DR SEL
1
0
EXTERNAL
INTERRUPT
SOURCE (ei x
)
POLARITY
SELECTION
FROM
OTHER
BITS
CMOS
SCHMITT
TRIGGER
ALTERNATE
INPUT
Table 6. I/O Port Mode Options
Configuration Mode
Input
Output
Floating with/without Interrupt
Pull-up with/without Interrupt
Push-pull
Open Drain (logic level)
True Open Drain
Legend: NI - not implemented
Off - implemented not activated
On - implemented and activated
Diodes
Pull-Up P-Buffer to V
DD to V
SS
Off
On
Off
NI
Off
On
Off
NI
On
On
NI (see note)
Note: The diode to V
DD
is not implemented in the true open drain pads. A local protection between the pad and V
SS
is implemented to protect the device against positive stress.
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I/O PORTS (Cont’d)
Table 7. I/O Port Configurations
NOT IMPLEMENTED IN
TRUE OPEN DRAIN
I/O PORTS
V
DD
R
PU
PAD
NOT IMPLEMENTED IN
TRUE OPEN DRAIN
I/O PORTS
V
DD
R
PU
PAD
Hardware Configuration
PULL-UP
CONFIGURATION
DR REGISTER ACCESS
DR
REGISTER
W
R
DATA BUS
FROM
OTHER
PINS
INTERRUPT
CONFIGURATION
ALTERNATE INPUT
EXTERNAL INTERRUPT
SOURCE (ei x
)
POLARITY
SELECTION
ANALOG INPUT
DR REGISTER ACCESS
DR
REGISTER
R/W
DATA BUS
NOT IMPLEMENTED IN
TRUE OPEN DRAIN
I/O PORTS
V
DD
R
PU
PAD
ALTERNATE
ENABLE
ALTERNATE
OUTPUT
DR REGISTER ACCESS
DR
REGISTER
R/W
DATA BUS
ALTERNATE
ENABLE
ALTERNATE
OUTPUT
Notes:
1. When the I/O port is in input configuration and the associated alternate function is enabled as an output, reading the DR register will read the alternate function output status.
2. When the I/O port is in output configuration and the associated alternate function is enabled as an input, the alternate function reads the pin status given by the DR register content.
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I/O PORTS (Cont’d)
CAUTION: The alternate function must not be activated as long as the pin is configured as input with interrupt, in order to avoid generating spurious interrupts.
Analog alternate function
When the pin is used as an ADC input, the I/O must be configured as floating input. The analog multiplexer (controlled by the ADC registers) switches the analog voltage present on the selected pin to the common analog rail which is connected to the ADC input.
It is recommended not to change the voltage level or loading on any port pin while conversion is in progress. Furthermore it is recommended not to have clocking pins located close to a selected analog pin.
WARNING: The analog input voltage level must be within the limits stated in the absolute maximum ratings.
12.3 I/O PORT IMPLEMENTATION
The hardware implementation on each I/O port depends on the settings in the DDR and OR registers and specific feature of the I/O port such as ADC Input or true open drain.
Switching these I/O ports from one state to another should be done in a sequence that prevents unwanted side effects. Recommended safe transitions are illustrated in Figure 27 Other transitions are potentially risky and should be avoided, since they are likely to present unwanted side-effects such as spurious interrupt generation.
Figure 27. Interrupt I/O Port State Transitions
Standard Ports
PA5:4, PC7:0, PD7:0, PE7:4, PE1:0, PF7:6, PF4
MODE floating input pull-up input open drain output push-pull output
DDR
0
0
1
1
OR
0
1
0
1
Interrupt Ports
PA2:0, PB7:5, PB2:0, PF1:0 (with pull-up)
MODE floating input pull-up interrupt input open drain output push-pull output
DDR
1
1
0
0
OR
0
1
0
1
PA3, PB4, PB3, PF2 (without pull-up)
MODE floating input floating interrupt input open drain output push-pull output
DDR
1
1
0
0
True Open Drain Ports
PA7:6
MODE floating input open drain (high sink ports)
OR
0
1
0
1
DDR
0
1
01 00
INPUT floating/pull-up interrupt
INPUT floating
(reset state)
10
OUTPUT open-drain
11
OUTPUT push-pull
XX = DDR, OR
The I/O port register configurations are summarized as follows.
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I/O PORTS (Cont’d)
12.4 LOW POWER MODES 12.5 INTERRUPTS
Mode Description
WAIT
HALT
No effect on I/O ports. External interrupts cause the device to exit from WAIT mode.
No effect on I/O ports. External interrupts cause the device to exit from HALT mode.
The external interrupt event generates an interrupt if the corresponding configuration is selected with
DDR and OR registers and the I-bit in the CC register is reset (RIM instruction).
Interrupt Event
Event
Flag
Enable
Control
Bit
Exit from
Wait
Exit from
Halt
External interrupt on selected external event
-
DDRx
ORx
Yes Yes
Table 8. Port Configuration
Port
Port A
Port B
Port C
Port D
Port E
Port F
Pin name
PA7:6
PA5:4
PA3
PA2:0
PB4:3
PB7:5, PB2:0
PC7:4, PC1:0
PC3:2
PD7:0
PE7:4
PE1:0
PF7:6
PF4
PF2
PF1:0 floating floating floating floating floating floating floating floating floating floating floating floating floating floating
OR = 0
Input
OR = 1 floating pull-up floating interrupt pull-up interrupt floating interrupt pull-up interrupt pull-up pull-up pull-up pull-up pull-up pull-up pull-up floating interrupt pull-up interrupt
Output
OR = 0 OR = 1 true open-drain open drain push-pull open drain open drain push-pull push-pull open drain open drain open drain open drain push-pull push-pull push-pull push-pull open drain open drain open drain open drain open drain open drain open drain push-pull push-pull push-pull push-pull push-pull push-pull push-pull
High-Sink
Yes
No
Yes
No
Yes
No
Yes
No
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I/O PORTS (Cont’d)
12.5.1 Register Description
DATA REGISTER (DR)
Port x Data Register
PxDR with x = A, B, C, D, E or F.
Read /Write
Reset Value: 0000 0000 (00h)
7
D7 D6 D5 D4 D3 D2 D1
0
D0
Bit 7:0 = D[7:0]
Data register 8 bits.
The DR register has a specific behaviour according to the selected input/output configuration. Writing the DR register is always taken into account even if the pin is configured as an input; this allows to always have the expected level on the pin when toggling to output mode. Reading the DR register returns either the DR register latch content (pin configured as output) or the digital value applied to the I/O pin (pin configured as input).
DATA DIRECTION REGISTER (DDR)
Port x Data Direction Register
PxDDR with x = A, B, C, D, E or F.
Read /Write
Reset Value: 0000 0000 (00h)
7 0
DD7 DD6 DD5 DD4 DD3 DD2 DD1 DD0
Bit 7:0 = O[7:0]
Option register 8 bits.
For specific I/O pins, this register is not implemented. In this case the DDR register is enough to select the I/O pin configuration.
The OR register allows to distinguish: in input mode if the pull-up with interrupt capability or the basic pull-up configuration is selected, in output mode if the push-pull or open drain configuration is selected.
Each bit is set and cleared by software.
Input mode:
0: floating input
1: pull-up input with or without interrupt
Output mode:
0: output open drain (with P-Buffer deactivated)
1: output push-pull
Bit 7:0 = DD[7:0]
Data direction register 8 bits.
The DDR register gives the input/output direction configuration of the pins. Each bits is set and cleared by software.
0: Input mode
1: Output mode
OPTION REGISTER (OR)
Port x Option Register
PxOR with x = A, B, C, D, E or F.
Read /Write
Reset Value: 0000 0000 (00h)
7
O7 O6 O5 O4 O3 O2 O1
0
O0
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I/O PORTS (Cont’d)
Table 9. I/O Port Register Map and Reset Values
Address
(Hex.)
Register
Label
7 6 5 4 3 2 1
Reset Value of all IO port registers
0000h PADR
0001h
0002h
0004h
0005h
PADDR
PAOR
PCDR
1)
PCDDR
0
MSB
0 0 0 0 0 0
MSB
0006h
0008h
0009h
000Ah
000Ch
000Dh
000Eh
0010h
0011h
0012h
0014h
0015h
PCOR
PBDR
PBDDR
PBOR
1)
PEDR
PEDDR
PEOR
1)
PDDR
PDDDR
PDOR
1)
PFDR
PFDDR
MSB
MSB
MSB
MSB
0016h PFOR
Notes:
1) The bits corresponding to unavailable pins are forced to 1 by hardware, this affects the reset status value.
0
0
LSB
LSB
LSB
LSB
LSB
LSB
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13 MISCELLANEOUS REGISTERS
The miscellaneous registers allow control over several different features such as the external interrupts or the I/O alternate functions.
13.1 I/O PORT INTERRUPT SENSITIVITY
The external interrupt sensitivity is controlled by the ISxx bits of the MISCR1 miscellaneous register. This control allows to have two fully independent external interrupt source sensitivities.
Each external interrupt source can be generated on four different events on the pin:
■
Falling edge
■
■
■
Rising edge
Falling and rising edge
Falling edge and low level
To guarantee correct functionality, the sensitivity bits in the MISCR1 register must be modified only when the I bit of the CC register is set to 1 (interrupt masked). See I/O port register and Miscellaneous register descriptions for more details on the programming.
13.2 I/O PORT ALTERNATE FUNCTIONS
The MISCR registers manage four I/O port miscellaneous alternate functions:
■
■
■
Main clock signal (f
CPU
) output on PF0
A beep signal output on PF1 (with 3 selectable audio frequencies)
SPI pin configuration:
– SS pin internal control to use the PC7 I/O port function while the SPI is active.
These functions are described in detail in the
Section 13 "MISCELLANEOUS REGISTERS" on page 46 .
Figure 28. Ext. Interrupt Sensitivity
PA0
PA1
PA2
PA3
PF0
PF1
PF2
PB0
PB1
PB2
PB3
PB4
PB5
PB6
PB7
MISCR1
IS10 IS11
INTERRUPT
SOURCE ei2 ei3
SENSITIVITY
CONTROL
MISCR1
IS20 IS21
INTERRUPT
SOURCE ei0 ei1
SENSITIVITY
CONTROL
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MISCELLANEOUS REGISTERS (Cont’d)
13.3 REGISTERS DESCRIPTION
MISCELLANEOUS REGISTER 1 (MISCR1)
Read /Write
Reset Value: 0000 0000 (00h)
7 0
IS11 IS10 MCO IS21 IS20 CP1 CP0 SMS
Bit 4:3 = IS2[1:0]
ei0 and ei1 sensitivity
The interrupt sensitivity, defined using the IS2[1:0] bits, is applied to the following external interrupts:ei0 (port A3..0) and ei1 (port F2..0). These 2 bits can be written only when the I bit of the CC register is set to 1 (interrupt disabled).
Bit 7:6 = IS1[1:0]
ei2 and ei3 sensitivity
The interrupt sensitivity, defined using the IS1[1:0] bits, is applied to the following external interrupts: ei2 (port B3..0) and ei3 (port B7..4). These 2 bits can be written only when the I bit of the CC register is set to 1 (interrupt disabled).
External Interrupt Sensitivity
Falling edge & low level
Rising edge only
Falling edge only
Rising and falling edge
IS11 IS10
0
0
0
1
1
1
0
1
Bit 2:1 = CP[1:0]
CPU clock prescaler
These bits select the CPU clock prescaler which is applied in the different slow modes. Their action is conditioned by the setting of the SMS bit. These two bits are set and cleared by software f
OSC
/ 4 f
OSC
/ 8 f
OSC
/ 16 f
OSC
/ 32 f
CPU
in SLOW mode CP1 CP0
0 0
1
0
1
0
1
1
Bit 5 = MCO
Main clock out selection
This bit enables the MCO alternate function on the
I/O port. It is set and cleared by software.
0: MCO alternate function disabled
(I/O pin free for general-purpose I/O)
1: MCO alternate function enabled
(f
OSC
/2 on I/O port)
Note: To reduce power consumption, the MCO function is not active in ACTIVE-HALT mode.
Bit 0 = SMS
Slow mode select
This bit is set and cleared by software.
0: Normal mode. f
CPU
1: Slow mode. f
CPU
= f
OSC
/ 2
is given by CP1, CP0
See low power consumption mode and MCC chapters for more details.
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MISCELLANEOUS REGISTERS (Cont’d)
MISCELLANEOUS REGISTER 2 (MISCR2)
Read /Write
Reset Value: 0000 0000 (00h)
7 0
BC1 BC0 SSM SSI
Bit 7:6 = Reserved
Must always be cleared
Bit 5:4 = BC[1:0]
Beep control
These 2 bits select the PF1 pin beep capability.
BC1 BC0 Beep mode with f
OSC
=16MHz
Off
~2-KHz
Output
0
0
0
1
0
~50% duty cycle
~500-Hz 1 1
The beep output signal is available in ACTIVE-
HALT mode but has to be disabled to reduce the consumption.
Bit 3:2 = Reserved
Must always be cleared
Bit 1 = SSM
SS mode selection
It is set and cleared by software.
0: Normal mode - SS uses information coming from the SS pin of the SPI.
1: I/O mode, the SPI uses the information stored into bit SSI.
Bit 0 = SSI
SS internal mode
This bit replaces pin SS of the SPI when bit SSM is set to 1. (see SPI description). It is set and cleared by software.
Table 10. Miscellaneous Register Map and Reset Values
Address
(Hex.)
0020h
0040h
Register
7
Label
6 5
MISCR1
Reset Value
MISCR2
Reset Value
IS11
0
0
IS10
0
0
MCO
0
BC1
0
4
IS21
0
BC0
0
3
IS20
0
0
2
CP1
0
0
1
CP0
0
SSM
0
0
SMS
0
SSI
0
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14 ON-CHIP PERIPHERALS
14.1 WATCHDOG TIMER (WDG)
14.1.1 Introduction
The Watchdog timer is used to detect the occurrence of a software fault, usually generated by external interference or by unforeseen logical conditions, which causes the application program to abandon its normal sequence. The Watchdog circuit generates an MCU reset on expiry of a programmed time period, unless the program refreshes the counter’s contents before the T6 bit becomes cleared.
14.1.2 Main Features
■
■
■
Programmable timer (64 increments of 12288
CPU cycles)
Programmable reset
Reset (if watchdog activated) after a HALT instruction or when the T6 bit reaches zero
Figure 29. Watchdog Block Diagram
■
■
Hardware Watchdog selectable by option byte
Watchdog Reset indicated by status flag (in versions with Safe Reset option only)
14.1.3 Functional Description
The counter value stored in the CR register (bits
T[6:0]), is decremented every 12,288 machine cycles, and the length of the timeout period can be programmed by the user in 64 increments.
If the watchdog is activated (the WDGA bit is set) and when the 7-bit timer (bits T[6:0]) rolls over from 40h to 3Fh (T6 becomes cleared), it initiates a reset cycle pulling low the reset pin for typically
500ns.
RESET f
CPU
WDGA T6
WATCHDOG CONTROL REGISTER (CR)
T5 T4 T3 T2
7-BIT DOWNCOUNTER
T1 T0
CLOCK DIVIDER
÷
12288
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WATCHDOG TIMER (Cont’d)
The application program must write in the CR register at regular intervals during normal operation to prevent an MCU reset. The value to be stored in the CR register must be between FFh and C0h
(see Table 11 .Watchdog Timing (fCPU = 8 MHz) ):
– The WDGA bit is set (watchdog enabled)
– The T6 bit is set to prevent generating an immediate reset
– The T[5:0] bits contain the number of increments which represents the time delay before the watchdog produces a reset.
Table 11.Watchdog Timing (f
CPU
= 8 MHz)
Max
Min
CR Register initial value
FFh
C0h
WDG timeout period
(ms)
98.304
1.536
14.1.7 Register Description
CONTROL REGISTER (CR)
Read /Write
Reset Value: 0111 1111 (7F h)
7
WDGA T6 T5 T4 T3 T2 T1
0
T0
Bit 7 = WDGA
Activation bit
.
This bit is set by software and only cleared by hardware after a reset. When WDGA = 1, the watchdog can generate a reset.
0: Watchdog disabled
1: Watchdog enabled
Note: This bit is not used if the hardware watchdog option is enabled by option byte.
Bit 6:0 = T[6:0]
7-bit timer (MSB to LSB).
These bits contain the decremented value. A reset is produced when it rolls over from 40h to 3Fh (T6 becomes cleared).
Notes: Following a reset, the watchdog is disabled. Once activated it cannot be disabled, except by a reset.
The T6 bit can be used to generate a software reset (the WDGA bit is set and the T6 bit is cleared).
If the watchdog is activated, the HALT instruction will generate a Reset.
14.1.4 Hardware Watchdog Option
If Hardware Watchdog is selected by option byte, the watchdog is always active and the WDGA bit in the CR is not used.
Refer to the device-specific Option Byte description.
14.1.5 Low Power Modes
Mode Description
WAIT No effect on Watchdog.
HALT
Immediate reset generation as soon as the HALT instruction is executed if the
Watchdog is activated (WDGA bit is set).
STATUS REGISTER (SR)
Read /Write
Reset Value*: 0000 0000 (00h)
7
-
0
WDOGF
Bit 0 = WDOGF
Watchdog flag
.
This bit is set by a watchdog reset and cleared by software or a power on/off reset. This bit is useful for distinguishing power/on off or external reset and watchdog reset.
0: No Watchdog reset occurred
1: Watchdog reset occurred
* Only by software and power on/off reset
Note: This register is not used in versions without
LVD Reset.
14.1.6 Interrupts
None.
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WATCHDOG TIMER (Cont’d)
Table 12. Watchdog Timer Register Map and Reset Values
Address
(Hex.)
002Ah
Register
Label
WDGCR
Reset Value
7
WDGA
0
6
T6
1
5
T5
1
4
T4
1
3
T3
1
2
T2
1
1
T1
1
0
T0
1
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14.2 MAIN CLOCK CONTROLLER WITH REAL TIME CLOCK TIMER (MCC/RTC)
The Main Clock Controller consists of three different functions:
■
■ a programmable CPU clock prescaler a clock-out signal to supply external devices
■ a real time clock timer with interrupt capability
Each function can be used independently and simultaneously.
14.2.1 Programmable CPU clock prescaler
The programmable CPU clock prescaler supplies the clock for the ST7 CPU and its internal peripherals. It manages SLOW power saving mode (See
Section 11.2 "SLOW MODE" on page 35 for more
details).
The prescaler selects the f
CPU
main clock frequency and is controlled by three bits in the MISCR1 register: CP[1:0] and SMS.
CAUTION: The prescaler does not act on the CAN peripheral clock source. This peripheral is always supplied by the f
OSC
/2 clock source.
14.2.2 Clock-out capability
The clock-out capability is an alternate function of an I/O port pin that outputs a f
OSC
/2 clock to drive external devices. It is controlled by the MCO bit in the MISCR1 register.
CAUTION: When selected, the clock out pin suspends the clock during ACTIVE-HALT mode.
14.2.3 Real time clock timer (RTC)
The counter of the real time clock timer allows an interrupt to be generated based on an accurate real time clock. Four different time bases depending directly on f
OSC
are available. The whole functionality is controlled by four bits of the MCCSR register: TB[1:0], OIE and OIF.
When the RTC interrupt is enabled (OIE bit set), the ST7 enters ACTIVE-HALT mode when the
HALT instruction is executed. See Section 11.4
"ACTIVE-HALT AND HALT MODES" on page 37
for more details.
Figure 30. Main Clock Controller (MCC/RTC) Block Diagram f
OSC
/2
PORT
ALTERNATE
FUNCTION MCO
MISCR1
MCO CP1 CP0 SMS f
OSC
DIV 2
RTC
COUNTER
MCCSR
0 0 0 0 TB1 TB0 OIE OIF
MCC/RTC INTERRUPT
DIV 2, 4, 8, 16 f
CPU
CPU CLOCK
TO CPU AND
PERIPHERALS
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MAIN CLOCK CONTROLLER WITH REAL TIME CLOCK TIMER (Cont’d)
MISCELLANEOUS REGISTER 1 (MISCR1)
See
MAIN CLOCK CONTROL/STATUS REGISTER
(MCCSR)
Read /Write
Reset Value: 0000 0001 (01h)
7 0
Bit 0 = OIF
Oscillator interrupt flag
This bit is set by hardware and cleared by software reading the CSR register. It indicates when set that the main oscillator has measured the selected elapsed time (TB1:0).
0: Timeout not reached
1: Timeout reached
CAUTION: The BRES and BSET instructions must not be used on the MCCSR register to avoid unintentionally clearing the OIF bit.
0 0 0 0 TB1 TB0 OIE OIF
14.2.4 Low Power Modes
Bit 7:4 = Reserved, always read as 0.
Bit 3:2 = TB[1:0]
Time base control
These bits select the programmable divider time base. They are set and cleared by software.
Counter
Prescaler
32000
64000
160000
400000
Time Base f
OSC
=8MHz f
OSC
=16MHz
4ms
8ms
20ms
50ms
2ms
4ms
10ms
25ms
TB1 TB0
0
0
1
1
0
1
0
1
Mode Description
WAIT
ACTIVE-
HALT
HALT
No effect on MCC/RTC peripheral.
MCC/RTC interrupt cause the device to exit from WAIT mode.
No effect on MCC/RTC counter (OIE bit is set), the registers are frozen.
MCC/RTC interrupt cause the device to exit from ACTIVE-HALT mode.
MCC/RTC counter and registers are frozen.
MCC/RTC operation resumes when the
MCU is woken up by an interrupt with “exit from HALT” capability.
A modification of the time base is taken into account at the end of the current period (previously set) to avoid unwanted time shift. This allows to use this time base as a real time clock.
14.2.5 Interrupts
The MCC/RTC interrupt event generates an interrupt if the OIE bit of the MCCSR register is set and the interrupt mask in the CC register is not active
(RIM instruction).
Interrupt Event
Time base overflow event
Event
Flag
Enable
Control
Bit
Exit from
Wait
OIF OIE Yes
Exit from
Halt
No
1)
Bit 1 = OIE
Oscillator interrupt enable
This bit set and cleared by software.
0: Oscillator interrupt disabled
1: Oscillator interrupt enabled
This interrupt allows to exit from ACTIVE-HALT mode.
When this bit is set, calling the ST7 software HALT instruction enters the ACTIVE-HALT power saving mode
.
Note:
1. The MCC/RTC interrupt allows to exit from AC-
TIVE-HALT mode, not from HALT mode.
Table 13. MCC Register Map and Reset Values
Address
(Hex.)
0029h
Register
Label
MCCSR
Reset Value
7
0
6
0
5
0
4
0
3
TB1
0
2
TB0
0
1
OIE
0
0
OIF
1
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14.3 16-BIT TIMER
14.3.1 Introduction
The timer consists of a 16-bit free-running counter driven by a programmable prescaler.
It may be used for a variety of purposes, including measuring the pulse lengths of up to two input signals (
input capture
) or generating up to two output waveforms (
output compare
and
PWM
).
Pulse lengths and waveform periods can be modulated from a few microseconds to several milliseconds using the timer prescaler and the CPU clock prescaler.
Some ST7 devices have two on-chip 16-bit timers.
They are completely independent, and do not share any resources. They are synchronized after a MCU reset as long as the timer clock frequencies are not modified.
This description covers one or two 16-bit timers. In
ST7 devices with two timers, register names are prefixed with TA (Timer A) or TB (Timer B).
14.3.2 Main Features
■
■
■
■
Programmable prescaler: f
CPU
divided by 2, 4 or 8.
Overflow status flag and maskable interrupt
External clock input (must be at least 4 times slower than the CPU clock speed) with the choice of active edge
Output compare functions with:
– 2 dedicated 16-bit registers
– 2 dedicated programmable signals
■
■
■
■
– 2 dedicated status flags
– 1 dedicated maskable interrupt
Input capture functions with:
– 2 dedicated 16-bit registers
– 2 dedicated active edge selection signals
– 2 dedicated status flags
– 1 dedicated maskable interrupt
Pulse Width Modulation mode (PWM)
One Pulse mode
5 alternate functions on I/O ports (ICAP1, ICAP2,
OCMP1, OCMP2, EXTCLK)*
The Block Diagram is shown in Figure 31 .
*Note: Some timer pins may not be available (not bonded) in some ST7 devices. Refer to the device pin out description.
When reading an input signal on a non-bonded pin, the value will always be ‘1’.
14.3.3 Functional Description
14.3.3.1 Counter
The main block of the Programmable Timer is a
16-bit free running upcounter and its associated
16-bit registers. The 16-bit registers are made up of two 8-bit registers called high & low.
Counter Register (CR):
– Counter High Register (CHR) is the most significant byte (MS Byte).
– Counter Low Register (CLR) is the least significant byte (LS Byte).
Alternate Counter Register (ACR)
– Alternate Counter High Register (ACHR) is the most significant byte (MS Byte).
– Alternate Counter Low Register (ACLR) is the least significant byte (LS Byte).
These two read-only 16-bit registers contain the same value but with the difference that reading the
ACLR register does not clear the TOF bit (Timer overflow flag), located in the Status register (SR).
(See note at the end of paragraph titled 16-bit read sequence).
Writing in the CLR register or ACLR register resets the free running counter to the FFFCh value.
Both counters have a reset value of FFFCh (this is the only value which is reloaded in the 16-bit timer). The reset value of both counters is also
FFFCh in One Pulse mode and PWM mode.
The timer clock depends on the clock control bits of the CR2 register, as illustrated in Table 14 Clock
Control Bits . The value in the counter register repeats every 131072, 262144 or 524288 CPU clock cycles depending on the CC[1:0] bits.
The timer frequency can be f
CPU or an external frequency.
/2, f
CPU
/4, f
CPU
/8
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16-BIT TIMER (Cont’d)
Figure 31. Timer Block Diagram
ST7 INTERNAL BUS
EXTCLK pin f
CPU
MCU-PERIPHERAL INTERFACE
8 high 8 low
8-bit buffer
1/2
1/4
1/8
EXEDG
16
COUNTER
REGISTER
ALTERNATE
COUNTER
REGISTER
16
CC[1:0]
8 8 8 8 8 8 8 8
OUTPUT
COMPARE
REGISTER
1
OUTPUT
COMPARE
REGISTER
2
INPUT
CAPTURE
REGISTER
1
INPUT
CAPTURE
REGISTER
2
16 16
TIMER INTERNAL BUS
16 16
OVERFLOW
DETECT
CIRCUIT
OUTPUT COMPARE
CIRCUIT
EDGE DETECT
CIRCUIT1
ICAP1 pin
6
EDGE DETECT
CIRCUIT2
ICAP2 pin
ICF1 OCF1 TOF ICF2 OCF2 0 0 0
(Status Register) SR
LATCH1
LATCH2
OCMP1 pin
OCMP2 pin
ICIE OCIE TOIE FOLV2 FOLV1 OLVL2 IEDG1 OLVL1
(Control Register 1) CR1
OC1E OC2E OPM PWM CC1 CC0 IEDG2 EXEDG
(Control Register 2) CR2
(See note)
TIMER INTERRUPT Note: If IC, OC and TO interrupt requests have separate vectors then the last OR is not present (See device Interrupt Vector Table)
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16-BIT TIMER (Cont’d)
16-bit Read Sequence: (from either the Counter
Register or the Alternate Counter Register).
Beginning of the sequence
At t0
Read
MS Byte
LS Byte is buffered
Other instructions
At t0 +
∆ t
Read
LS Byte
Sequence completed
Returns the buffered
LS Byte value at t0
The user must read the MS Byte first, then the LS
Byte value is buffered automatically.
This buffered value remains unchanged until the
16-bit read sequence is completed, even if the user reads the MS Byte several times.
After a complete reading sequence, if only the
CLR register or ACLR register are read, they return the LS Byte of the count value at the time of the read.
Whatever the timer mode used (input capture, output compare, One Pulse mode or PWM mode) an overflow occurs when the counter rolls over from
FFFFh to 0000h then:
– The TOF bit of the SR register is set.
– A timer interrupt is generated if:
– TOIE bit of the CR1 register is set and
– I bit of the CC register is cleared.
If one of these conditions is false, the interrupt remains pending to be issued as soon as they are both true.
Clearing the overflow interrupt request is done in two steps:
1. Reading the SR register while the TOF bit is set.
2. An access (read or write) to the CLR register.
Note: The TOF bit is not cleared by accessing the
ACLR register. The advantage of accessing the
ACLR register rather than the CLR register is that it allows simultaneous use of the overflow function and reading the free running counter at random times (for example, to measure elapsed time) without the risk of clearing the TOF bit erroneously.
The timer is not affected by WAIT mode.
In HALT mode, the counter stops counting until the mode is exited. Counting then resumes from the previous count (MCU awakened by an interrupt) or from the reset count (MCU awakened by a Reset).
14.3.3.2 External Clock
The external clock (where available) is selected if
CC0=1 and CC1=1 in the CR2 register.
The status of the EXEDG bit in the CR2 register determines the type of level transition on the external clock pin EXTCLK that will trigger the free running counter.
The counter is synchronised with the falling edge of the internal CPU clock.
A minimum of four falling edges of the CPU clock must occur between two consecutive active edges of the external clock; thus the external clock frequency must be less than a quarter of the CPU clock frequency.
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16-BIT TIMER (Cont’d)
Figure 32. Counter Timing Diagram, internal clock divided by 2
CPU CLOCK
INTERNAL RESET
TIMER CLOCK
COUNTER REGISTER
TIMER OVERFLOW FLAG (TOF)
FFFD FFFE FFFF 0000 0001 0002 0003
Figure 33. Counter Timing Diagram, internal clock divided by 4
CPU CLOCK
INTERNAL RESET
TIMER CLOCK
COUNTER REGISTER
FFFC
TIMER OVERFLOW FLAG (TOF)
FFFD 0000 0001
Figure 34. Counter Timing Diagram, internal clock divided by 8
CPU CLOCK
INTERNAL RESET
TIMER CLOCK
COUNTER REGISTER
FFFC FFFD 0000
TIMER OVERFLOW FLAG (TOF)
Note: The MCU is in reset state when the internal reset signal is high. When it is low, the MCU is running.
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16-BIT TIMER (Cont’d)
14.3.3.3 Input Capture
In this section, the index,
i
, may be 1 or 2 because there are 2 input capture functions in the 16-bit timer.
The two input capture 16-bit registers (IC1R and
IC2R) are used to latch the value of the free running counter after a transition is detected by the
ICAP
i
pin (see figure 5).
ICiR
MS Byte
IC i HR
LS Byte
IC i LR
The IC
i
R register is a read-only register.
The active transition is software programmable through the IEDG
i
bit of Control Registers (CR
i
).
Timing resolution is one count of the free running counter: ( f
CPU
/ CC[1:0]).
Procedure:
To use the input capture function, select the following in the CR2 register:
– Select the timer clock (CC[1:0]) (see Table 14
Clock Control Bits ).
– Select the edge of the active transition on the
ICAP2 pin with the IEDG2 bit (the ICAP2 pin must be configured as a floating input or input with pull-up without interrupt if this configuration is available).
And select the following in the CR1 register:
– Set the ICIE bit to generate an interrupt after an input capture coming from either the ICAP1 pin or the ICAP2 pin
– Select the edge of the active transition on the
ICAP1 pin with the IEDG1 bit (the ICAP1 pin must be configured as a floating input or input with pull-up without interrupt if this configuration is available).
When an input capture occurs:
– The ICF
i
bit is set.
– The IC
i
R register contains the value of the free running counter on the active transition on the
ICAP
i
pin (see Figure 36 ).
– A timer interrupt is generated if the ICIE bit is set and the I bit is cleared in the CC register. Otherwise, the interrupt remains pending until both conditions become true.
Clearing the Input Capture interrupt request (i.e.
clearing the ICF
i
bit) is done in two steps:
1. Reading the SR register while the ICF
i
bit is set.
2. An access (read or write) to the IC
i
LR register.
Notes:
1. After reading the IC
i
HR register, the transfer of input capture data is inhibited and ICF
i
will never be set until the IC
i
LR register is also read.
2. The IC
i
R register contains the free running counter value which corresponds to the most recent input capture.
3. The 2 input capture functions can be used together even if the timer also uses the 2 output compare functions.
4. In One Pulse mode and PWM mode only the input capture 2 function can be used.
5. The alternate inputs (ICAP1 & ICAP2) are always directly connected to the timer. So any transitions on these pins activate the input capture function.
Moreover if one of the ICAP
i
pin is configured as an input and the second one as an output, an interrupt can be generated if the user toggles the output pin and if the ICIE bit is set.
This can be avoided if the input capture function
i
is disabled by reading the IC
i
HR (see note
1).
6. The TOF bit can be used with an interrupt in order to measure events that exceed the timer range (FFFFh).
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16-BIT TIMER (Cont’d)
Figure 35. Input Capture Block Diagram
ICAP1 pin
ICAP2 pin
EDGE DETECT
CIRCUIT2
EDGE DETECT
CIRCUIT1
IC2R Register IC1R Register
16-BIT
16-BIT FREE RUNNING
COUNTER
ICIE
ICF1
ST72334J/N, ST72314J/N, ST72124J
(Control Register 1) CR1
IEDG1
ICF2
(Status Register) SR
0 0 0
(Control Register 2) CR2
CC1 CC0 IEDG2
Figure 36. Input Capture Timing Diagram
TIMER CLOCK
COUNTER REGISTER
ICAPi PIN
ICAPi FLAG
FF01
ICAPi REGISTER
Note: A ctive edge is rising edge.
FF02 FF03
FF03
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16-BIT TIMER (Cont’d)
14.3.3.4 Output Compare
In this section, the index,
i
, may be 1 or 2 because there are 2 output compare functions in the 16-bit timer.
This function can be used to control an output waveform or indicate when a period of time has elapsed.
When a match is found between the Output Compare register and the free running counter, the output compare function:
– Assigns pins with a programmable value if the
OC
i
E bit is set
– Sets a flag in the status register
– Generates an interrupt if enabled
Two 16-bit registers Output Compare Register 1
(OC1R) and Output Compare Register 2 (OC2R) contain the value to be compared to the counter register each timer clock cycle.
OC i R
MS Byte
OC i HR
LS Byte
OC i LR
These registers are readable and writable and are not affected by the timer hardware. A reset event changes the OC i R value to 8000h.
Timing resolution is one count of the free running counter: ( f
CPU/ CC[1:0]
).
Procedure:
To use the output compare function, select the following in the CR2 register:
– Set the OC
i
E bit if an output is needed then the
OCMP
i
pin is dedicated to the output compare
i
signal.
– Select the timer clock (CC[1:0]) (see Table 14
Clock Control Bits ).
And select the following in the CR1 register:
– Select the OLVL
i
bit to applied to the OCMP
i
pins after the match occurs.
– Set the OCIE bit to generate an interrupt if it is needed.
When a match is found between OCRi register and CR register:
– OCF
i
bit is set.
– The OCMP
i
pin takes OLVL
i
bit value (OCMP
i
pin latch is forced low during reset).
– A timer interrupt is generated if the OCIE bit is set in the CR1 register and the I bit is cleared in the CC register (CC).
The OC i R register value required for a specific timing application can be calculated using the following formula:
∆
OC
i
R =
∆ t
*
f
CPU
PRESC
Where:
∆ t = Output compare period (in seconds) f
CPU
= CPU clock frequency (in hertz)
PRESC
= Timer prescaler factor (2, 4 or 8 depending on CC[1:0] bits, see Table 14
Clock Control Bits )
If the timer clock is an external clock, the formula is:
∆
OC
i
R =
∆ t
*
f
EXT
Where:
∆ t = Output compare period (in seconds) f
EXT
= External timer clock frequency (in hertz)
Clearing the output compare interrupt request (i.e.
clearing the OCF
i
bit) is done by:
1. Reading the SR register while the OCF
i
bit is set.
2. An access (read or write) to the OC
i
LR register.
The following procedure is recommended to prevent the OCF
i
bit from being set between the time it is read and the write to the OC i R register:
– Write to the OC
i
HR register (further compares are inhibited).
– Read the SR register (first step of the clearance of the OCF
i
bit, which may be already set).
– Write to the OC
i
LR register (enables the output compare function and clears the OCF
i
bit).
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16-BIT TIMER (Cont’d)
Notes:
1. After a processor write cycle to the OC
i
HR register, the output compare function is inhibited until the OC
i
LR register is also written.
2. If the OC
i
E bit is not set, the OCMP
i
pin is a general I/O port and the OLVL
i
bit will not appear when a match is found but an interrupt could be generated if the OCIE bit is set.
3. When the timer clock is f
CPU
OCMP
/2, OCF
i
and
i
are set while the counter value equals the OC
i
R register value (see Figure 38 on page
62 ). This behaviour is the same in OPM or
PWM mode.
When the timer clock is f
CPU external clock mode, OCF
i
/4, f
CPU
/8 or in
and OCMP
i
are set while the counter value equals the OC
i
R register value plus 1 (see Figure 39 on page 62 ).
4. The output compare functions can be used both for generating external events on the OCMP
i
pins even if the input capture mode is also used.
5. The value in the 16-bit OC i R register and the
OLV
i
bit should be changed after each successful comparison in order to control an output waveform or establish a new elapsed timeout.
Figure 37. Output Compare Block Diagram
Forced Compare Output capability
When the FOLV
i
bit is set by software, the OLVL
i
bit is copied to the OCMP
i
pin. The OLV
i
bit has to be toggled in order to toggle the OCMP
i
pin when it is enabled (OC
i
E bit=1). The OCF
i
bit is then not set by hardware, and thus no interrupt request is generated.
FOLVL
i
bits have no effect in either One-Pulse mode or PWM mode.
16 BIT FREE RUNNING
COUNTER
16-bit
OUTPUT COMPARE
CIRCUIT
16-bit 16-bit
OC1R Register
OC2R Register
OC1E OC2E
OCIE
CC1 CC0
(Control Register 2) CR2
(Control Register 1) CR1
FOLV2 FOLV1 OLVL2 OLVL1
Latch
1
Latch
2
OCF1 OCF2 0 0 0
(Status Register) SR
OCMP1
Pin
OCMP2
Pin
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16-BIT TIMER (Cont’d)
Figure 38. Output Compare Timing Diagram, f
TIMER
=f
CPU
/2
INTERNAL CPU CLOCK
TIMER CLOCK
COUNTER REGISTER
OUTPUT COMPARE REGISTER i (OCR i )
OUTPUT COMPARE FLAG i (OCF i )
OCMP i PIN (OLVL i =1)
2ECF 2ED0 2ED1 2ED2 2ED3 2ED4
2ED3
Figure 39. Output Compare Timing Diagram, f
TIMER
=f
CPU
/4
INTERNAL CPU CLOCK
TIMER CLOCK
COUNTER REGISTER
OUTPUT COMPARE REGISTER i (OCR i )
COMPARE REGISTER i LATCH
2ECF 2ED0 2ED1 2ED2 2ED3 2ED4
2ED3
OUTPUT COMPARE FLAG i (OCF i )
OCMP i PIN (OLVL i =1)
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16-BIT TIMER (Cont’d)
14.3.3.5 One Pulse Mode
One Pulse mode enables the generation of a pulse when an external event occurs. This mode is selected via the OPM bit in the CR2 register.
The One Pulse mode uses the Input Capture1 function and the Output Compare1 function.
Procedure:
To use One Pulse mode:
1. Load the OC1R register with the value corresponding to the length of the pulse (see the formula in the opposite column).
2. Select the following in the CR1 register:
– Using the OLVL1 bit, select the level to be applied to the OCMP1 pin after the pulse.
– Using the OLVL2 bit, select the level to be applied to the OCMP1 pin during the pulse.
– Select the edge of the active transition on the
ICAP1 pin with the IEDG1 bit (the ICAP1 pin must be configured as floating input).
3. Select the following in the CR2 register:
– Set the OC1E bit, the OCMP1 pin is then dedicated to the Output Compare 1 function.
– Set the OPM bit.
– Select the timer clock CC[1:0] (see Table 14
Clock Control Bits ).
Clearing the Input Capture interrupt request (i.e.
clearing the ICF
i
bit) is done in two steps:
1. Reading the SR register while the ICF
i
bit is set.
2. An access (read or write) to the IC
i
LR register.
The OC1R register value required for a specific timing application can be calculated using the following formula:
OC
i
R Value = t
* f
CPU - 5
PRESC
Where: t = Pulse period (in seconds) f
CPU
= CPU clock frequency (in hertz)
PRESC
= Timer prescaler factor (2, 4 or 8 depending on the CC[1:0] bits, see Table 14
Clock Control Bits )
If the timer clock is an external clock the formula is:
OC
i
R = t
*
f
EXT
-5
Where: t = Pulse period (in seconds) f
EXT
= External timer clock frequency (in hertz)
When the value of the counter is equal to the value of the contents of the OC1R register, the OLVL1 bit is output on the OCMP1 pin (see Figure 40 ).
When event occurs on ICAP1
When
Counter
= OC1R
One Pulse mode cycle
OCMP1 = OLVL2
Counter is reset to FFFCh
ICF1 bit is set
OCMP1 = OLVL1
Then, on a valid event on the ICAP1 pin, the counter is initialized to FFFCh and the OLVL2 bit is loaded on the OCMP1 pin, the ICF1 bit is set and the value FFFDh is loaded in the IC1R register.
Because the ICF1 bit is set when an active edge occurs, an interrupt can be generated if the ICIE bit is set.
Notes:
1. The OCF1 bit cannot be set by hardware in
One Pulse mode but the OCF2 bit can generate an Output Compare interrupt.
2. When the Pulse Width Modulation (PWM) and
One Pulse mode (OPM) bits are both set, the
PWM mode is the only active one.
3. If OLVL1=OLVL2 a continuous signal will be seen on the OCMP1 pin.
4. The ICAP1 pin can not be used to perform input capture. The ICAP2 pin can be used to perform input capture (ICF2 can be set and IC2R can be loaded) but the user must take care that the counter is reset each time a valid edge occurs on the ICAP1 pin and ICF1 can also generates interrupt if ICIE is set.
5. When One Pulse mode is used OC1R is dedicated to this mode. Nevertheless OC2R and
OCF2 can be used to indicate that a period of time has elapsed but cannot generate an output waveform because the OLVL2 level is dedicated to One Pulse mode.
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16-BIT TIMER (Cont’d)
Figure 40. One Pulse Mode Timing Example
COUNTER
ICAP1
FFFC FFFD FFFE 2ED0 2ED1 2ED2
2ED3
FFFC FFFD
OCMP1
OLVL2
Note: IEDG1=1, OC1R=2ED0h, OLVL1=0, OLVL2=1 compare1
OLVL1 OLVL2
Figure 41. Pulse Width Modulation Mode Timing Example
COUNTER 34E2
FFFC FFFD FFFE
OLVL2
OCMP1
compare2
2ED0 2ED1 2ED2 34E2 FFFC
compare1
OLVL1 OLVL2
compare2
Note: OC1R=2ED0h, OC2R=34E2, OLVL1=0, OLVL2= 1
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16-BIT TIMER (Cont’d)
14.3.3.6 Pulse Width Modulation Mode
Pulse Width Modulation (PWM) mode enables the generation of a signal with a frequency and pulse length determined by the value of the OC1R and
OC2R registers.
The Pulse Width Modulation mode uses the complete Output Compare 1 function plus the OC2R register, and so these functions cannot be used when the PWM mode is activated.
Procedure
To use Pulse Width Modulation mode:
1. Load the OC2R register with the value corresponding to the period of the signal using the formula in the opposite column.
2. Load the OC1R register with the value corresponding to the period of the pulse if OLVL1=0 and OLVL2=1, using the formula in the opposite column.
3. Select the following in the CR1 register:
– Using the OLVL1 bit, select the level to be applied to the OCMP1 pin after a successful comparison with OC1R register.
– Using the OLVL2 bit, select the level to be applied to the OCMP1 pin after a successful comparison with OC2R register.
4. Select the following in the CR2 register:
– Set OC1E bit: the OCMP1 pin is then dedicated to the output compare 1 function.
– Set the PWM bit.
– Select the timer clock (CC[1:0]) (see Table 14
Clock Control Bits ).
If OLVL1=1 and OLVL2=0, the length of the positive pulse is the difference between the OC2R and
OC1R registers.
If OLVL1=OLVL2 a continuous signal will be seen on the OCMP1 pin.
Pulse Width Modulation cycle
When
Counter
= OC1R
OCMP1 = OLVL1
The OC i R register value required for a specific timing application can be calculated using the following formula:
OC
i
R Value = t
* f
CPU - 5
PRESC
Where: t = Signal or pulse period (in seconds) f
CPU
= CPU clock frequency (in hertz)
PRESC
= Timer prescaler factor (2, 4 or 8 depending on CC[1:0] bits, see Table 14 Clock
Control Bits )
If the timer clock is an external clock the formula is:
OC
i
R = t
*
f
EXT
-5
Where: t = Signal or pulse period (in seconds) f
EXT
= External timer clock frequency (in hertz)
The Output Compare 2 event causes the counter to be initialized to FFFCh (See Figure 41 )
Notes:
1. After a write instruction to the OC
i
HR register, the output compare function is inhibited until the
OC
i
LR register is also written.
2. The OCF1 and OCF2 bits cannot be set by hardware in PWM mode, therefore the Output
Compare interrupt is inhibited.
3. The ICF1 bit is set by hardware when the counter reaches the OC2R value and can produce a timer interrupt if the ICIE bit is set and the I bit is cleared.
4. In PWM mode the ICAP1 pin can not be used to perform input capture because it is disconnected from the timer. The ICAP2 pin can be used to perform input capture (ICF2 can be set and IC2R can be loaded) but the user must take care that the counter is reset after each period and ICF1 can also generate an interrupt if ICIE is set.
5. When the Pulse Width Modulation (PWM) and
One Pulse mode (OPM) bits are both set, the
PWM mode is the only active one.
When
Counter
= OC2R
OCMP1 = OLVL2
Counter is reset to FFFCh
ICF1 bit is set
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16-BIT TIMER (Cont’d)
14.3.4 Low Power Modes
Mode Description
WAIT
No effect on 16-bit Timer.
Timer interrupts cause the device to exit from WAIT mode.
16-bit Timer registers are frozen.
HALT
In HALT mode, the counter stops counting until Halt mode is exited. Counting resumes from the previous count when the MCU is woken up by an interrupt with “exit from HALT mode” capability or from the counter reset value when the MCU is woken up by a RESET.
If an input capture event occurs on the ICAP i pin, the input capture detection circuitry is armed. Consequently, when the MCU is woken up by an interrupt with “exit from HALT mode” capability, the ICF i bit is set, and the counter value present when exiting from HALT mode is captured into the IC i R register.
14.3.5 Interrupts
Interrupt Event
Input Capture 1 event/Counter reset in PWM mode
Input Capture 2 event
Output Compare 1 event (not available in PWM mode)
Output Compare 2 event (not available in PWM mode)
Timer Overflow event
Event
Flag
Enable
Control
Bit
ICF1
ICF2
OCF1
OCF2
TOF
ICIE
OCIE
TOIE
Exit from
Wait
Yes
Yes
Yes
Yes
Yes
Exit from
Halt
No
No
No
No
No
Note: The 16-bit Timer interrupt events are connected to the same interrupt vector (see Interrupts chapter). These events generate an interrupt if the corresponding Enable Control Bit is set and the interrupt mask in the CC register is reset (RIM instruction).
14.3.6 Summary of Timer modes
MODES
Input Capture (1 and/or 2)
Output Compare (1 and/or 2)
One Pulse mode
PWM Mode
Input Capture 1
Yes
Yes
No
No
AVAILABLE RESOURCES
Input Capture 2
Yes
Yes
Not Recommended
1)
Not Recommended
3)
Output Compare 1 Output Compare 2
Yes
Yes
No
No
Yes
Yes
Partially
No
2)
1)
See note 4 in Section 14.3.3.5 "One Pulse Mode" on page 63
2)
See note 5 in Section 14.3.3.5 "One Pulse Mode" on page 63
3)
See note 4 in Section 14.3.3.6 "Pulse Width Modulation Mode" on page 65
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16-BIT TIMER (Cont’d)
14.3.7 Register Description
Each Timer is associated with three control and status registers, and with six pairs of data registers
(16-bit values) relating to the two input captures, the two output compares, the counter and the alternate counter.
Bit 4 = FOLV2
Forced Output Compare 2.
This bit is set and cleared by software.
0: No effect on the OCMP2 pin.
1: Forces the OLVL2 bit to be copied to the
OCMP2 pin, if the OC2E bit is set and even if there is no successful comparison.
CONTROL REGISTER 1 (CR1)
Read/Write
Reset Value: 0000 0000 (00h)
7 0
ICIE OCIE TOIE FOLV2 FOLV1 OLVL2 IEDG1 OLVL1
Bit 3 = FOLV1
Forced Output Compare 1.
This bit is set and cleared by software.
0: No effect on the OCMP1 pin.
1: Forces OLVL1 to be copied to the OCMP1 pin, if the OC1E bit is set and even if there is no successful comparison.
Bit 7 = ICIE
Input Capture Interrupt Enable.
0: Interrupt is inhibited.
1: A timer interrupt is generated whenever the
ICF1 or ICF2 bit of the SR register is set.
Bit 6 = OCIE
Output Compare Interrupt Enable.
0: Interrupt is inhibited.
1: A timer interrupt is generated whenever the
OCF1 or OCF2 bit of the SR register is set.
Bit 5 = TOIE
Timer Overflow Interrupt Enable.
0: Interrupt is inhibited.
1: A timer interrupt is enabled whenever the TOF bit of the SR register is set.
Bit 2 = OLVL2
Output Level 2.
This bit is copied to the OCMP2 pin whenever a successful comparison occurs with the OC2R register and OCxE is set in the CR2 register. This value is copied to the OCMP1 pin in One Pulse mode and Pulse Width Modulation mode.
Bit 1 = IEDG1
Input Edge 1.
This bit determines which type of level transition on the ICAP1 pin will trigger the capture.
0: A falling edge triggers the capture.
1: A rising edge triggers the capture.
Bit 0 = OLVL1
Output Level 1.
The OLVL1 bit is copied to the OCMP1 pin whenever a successful comparison occurs with the
OC1R register and the OC1E bit is set in the CR2 register.
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16-BIT TIMER (Cont’d)
CONTROL REGISTER 2 (CR2)
Read/Write
Reset Value: 0000 0000 (00h)
7 0
OC1E OC2E OPM PWM CC1 CC0 IEDG2 EXEDG
Bit 4 = PWM
Pulse Width Modulation.
0: PWM mode is not active.
1: PWM mode is active, the OCMP1 pin outputs a programmable cyclic signal; the length of the pulse depends on the value of OC1R register; the period depends on the value of OC2R register.
Bit 7 = OC1E
Output Compare 1 Pin Enable.
This bit is used only to output the signal from the timer on the OCMP1 pin (OLV1 in Output Compare mode, both OLV1 and OLV2 in PWM and one-pulse mode). Whatever the value of the OC1E bit, the internal Output Compare 1 function of the timer remains active.
0: OCMP1 pin alternate function disabled (I/O pin free for general-purpose I/O).
1: OCMP1 pin alternate function enabled.
Bit 6 = OC2E
Output Compare 2 Pin Enable.
This bit is used only to output the signal from the timer on the OCMP2 pin (OLV2 in Output Compare mode). Whatever the value of the OC2E bit, the internal Output Compare 2 function of the timer remains active.
0: OCMP2 pin alternate function disabled (I/O pin free for general-purpose I/O).
1: OCMP2 pin alternate function enabled.
Bit 5 = OPM
One Pulse mode.
0: One Pulse mode is not active.
1: One Pulse mode is active, the ICAP1 pin can be used to trigger one pulse on the OCMP1 pin; the active transition is given by the IEDG1 bit. The length of the generated pulse depends on the contents of the OC1R register.
Bits 3:2 = CC[1:0]
Clock Control.
The timer clock mode depends on these bits:
Table 14. Clock Control Bits
Timer Clock f
CPU
/ 4 f
CPU
/ 2 f
CPU
/ 8
External Clock (where available)
1
CC1
0
0
1
CC0
0
1
0
1
Note: If the external clock pin is not available, programming the external clock configuration stops the counter.
Bit 1 = IEDG2
Input Edge 2.
This bit determines which type of level transition on the ICAP2 pin will trigger the capture.
0: A falling edge triggers the capture.
1: A rising edge triggers the capture.
Bit 0 = EXEDG
External Clock Edge.
This bit determines which type of level transition on the external clock pin (EXTCLK) will trigger the counter register.
0: A falling edge triggers the counter register.
1: A rising edge triggers the counter register.
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16-BIT TIMER (Cont’d)
STATUS REGISTER (SR)
Read Only
Reset Value: 0000 0000 (00h)
The three least significant bits are not used.
7
ICF1 OCF1 TOF ICF2 OCF2 0 0
0
0
INPUT CAPTURE 1 HIGH REGISTER (IC1HR)
Read Only
Reset Value: Undefined
This is an 8-bit read only register that contains the high part of the counter value (transferred by the input capture 1 event).
7 0
MSB LSB
Bit 7 = ICF1
Input Capture Flag 1.
0: No input capture (reset value).
1: An input capture has occurred on the ICAP1 pin or the counter has reached the OC2R value in
PWM mode. To clear this bit, first read the SR register, then read or write the low byte of the
IC1R (IC1LR) register.
Bit 6 = OCF1
Output Compare Flag 1.
0: No match (reset value).
1: The content of the free running counter matches the content of the OC1R register. To clear this bit, first read the SR register, then read or write the low byte of the OC1R (OC1LR) register.
Bit 5 = TOF
Timer Overflow Flag.
0: No timer overflow (reset value).
1: The free running counter has rolled over from
FFFFh to 0000h. To clear this bit, first read the
SR register, then read or write the low byte of the CR (CLR) register.
Note: Reading or writing the ACLR register does not clear TOF.
Bit 4 = ICF2
Input Capture Flag 2.
0: No input capture (reset value).
1: An input capture has occurred on the ICAP2 pin. To clear this bit, first read the SR register, then read or write the low byte of the IC2R
(IC2LR) register.
Bit 3 = OCF2
Output Compare Flag 2.
0: No match (reset value).
1: The content of the free running counter matches the content of the OC2R register. To clear this bit, first read the SR register, then read or write the low byte of the OC2R (OC2LR) register.
Bit 2-0 = Reserved, forced by hardware to 0.
INPUT CAPTURE 1 LOW REGISTER (IC1LR)
Read Only
Reset Value: Undefined
This is an 8-bit read only register that contains the low part of the counter value (transferred by the input capture 1 event).
7 0
MSB LSB
OUTPUT COMPARE 1 HIGH REGISTER
(OC1HR)
Read/Write
Reset Value: 1000 0000 (80h)
This is an 8-bit register that contains the high part of the value to be compared to the CHR register.
7 0
MSB LSB
OUTPUT COMPARE 1 LOW REGISTER
(OC1LR)
Read/Write
Reset Value: 0000 0000 (00h)
This is an 8-bit register that contains the low part of the value to be compared to the CLR register.
7 0
MSB LSB
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16-BIT TIMER (Cont’d)
OUTPUT COMPARE 2 HIGH REGISTER
(OC2HR)
Read/Write
Reset Value: 1000 0000 (80h)
This is an 8-bit register that contains the high part of the value to be compared to the CHR register.
7 0
MSB LSB
ALTERNATE COUNTER HIGH REGISTER
(ACHR)
Read Only
Reset Value: 1111 1111 (FFh)
This is an 8-bit register that contains the high part of the counter value.
7 0
MSB LSB
OUTPUT COMPARE 2 LOW REGISTER
(OC2LR)
Read/Write
Reset Value: 0000 0000 (00h)
This is an 8-bit register that contains the low part of the value to be compared to the CLR register.
7 0
MSB LSB
ALTERNATE COUNTER LOW REGISTER
(ACLR)
Read Only
Reset Value: 1111 1100 (FCh)
This is an 8-bit register that contains the low part of the counter value. A write to this register resets the counter. An access to this register after an access to SR register does not clear the TOF bit in SR register.
7 0
MSB LSB
COUNTER HIGH REGISTER (CHR)
Read Only
Reset Value: 1111 1111 (FFh)
This is an 8-bit register that contains the high part of the counter value.
7 0
MSB LSB
INPUT CAPTURE 2 HIGH REGISTER (IC2HR)
Read Only
Reset Value: Undefined
This is an 8-bit read only register that contains the high part of the counter value (transferred by the
Input Capture 2 event).
7
MSB
0
LSB
COUNTER LOW REGISTER (CLR)
Read Only
Reset Value: 1111 1100 (FCh)
This is an 8-bit register that contains the low part of the counter value. A write to this register resets the counter. An access to this register after accessing the SR register clears the TOF bit.
7 0
MSB LSB
INPUT CAPTURE 2 LOW REGISTER (IC2LR)
Read Only
Reset Value: Undefined
This is an 8-bit read only register that contains the low part of the counter value (transferred by the Input Capture 2 event).
7
MSB
0
LSB
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16-BIT TIMER (Cont’d)
Table 15. 16-Bit Timer Register Map and Reset Values
Address
(Hex.)
Register
Label
Timer A: 32
Timer B: 42
CR1
Reset Value
Timer A: 31
Timer B: 41
CR2
Reset Value
Timer A: 33
Timer B: 43
SR
Reset Value
Timer A: 34
Timer B: 44
ICHR1
Reset Value
Timer A: 35
Timer B: 45
ICLR1
Reset Value
Timer A: 36
Timer B: 46
OCHR1
Reset Value
Timer A: 37
Timer B: 47
OCLR1
Reset Value
Timer A: 3E
Timer B: 4E
OCHR2
Reset Value
Timer A: 3F
Timer B: 4F
OCLR2
Reset Value
Timer A: 38
Timer B: 48
CHR
Reset Value
Timer A: 39
Timer B: 49
CLR
Reset Value
Timer A: 3A
Timer B: 4A
ACHR
Reset Value
Timer A: 3B
Timer B: 4B
ACLR
Reset Value
Timer A: 3C
Timer B: 4C
ICHR2
Reset Value
Timer A: 3D
Timer B: 4D
ICLR2
Reset Value
7
MSB
-
MSB
-
MSB
1
MSB
1
MSB
1
MSB
1
ICIE
0
OC1E
0
ICF1
0
MSB
-
MSB
-
MSB
-
MSB
-
MSB
-
MSB
-
6
OCIE
0
OC2E
0
OCF1
0
-
-
-
-
-
-
1
1
1
1
-
-
5
TOIE
0
OPM
0
TOF
0
-
-
-
-
-
-
1
1
1
1
-
-
4
FOLV2
0
PWM
0
ICF2
0
-
-
-
-
-
-
-
-
1
1
1
1
3
FOLV1
0
CC1
0
OCF2
0
-
-
-
-
-
-
-
-
1
1
1
1
2 1 0
OLVL2
0
CC0
0
-
0
-
1
-
-
-
-
-
-
-
1
1
1
IEDG1
0
IEDG2
0
-
0
-
-
-
-
-
-
-
-
1
0
1
0
LSB
-
LSB
-
LSB
1
LSB
0
LSB
1
LSB
0
OLVL1
0
EXEDG
0
-
0
LSB
-
LSB
-
LSB
-
LSB
-
LSB
-
LSB
-
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14.4 SERIAL PERIPHERAL INTERFACE (SPI)
14.4.1 Introduction
The Serial Peripheral Interface (SPI) allows fullduplex, synchronous, serial communication with external devices. An SPI system may consist of a master and one or more slaves or a system in which devices may be either masters or slaves.
The SPI is normally used for communication between the microcontroller and external peripherals or another microcontroller.
Refer to the Pin Description chapter for the devicespecific pin-out.
14.4.3 General description
The SPI is connected to external devices through
4 alternate pins:
– MISO: Master In Slave Out pin
– MOSI: Master Out Slave In pin
– SCK: Serial Clock pin
– SS: Slave select pin
14.4.2 Main Features
■
Full duplex, three-wire synchronous transfers
■
■
■
■
■
■
■
■
Master or slave operation
Four master mode frequencies
Maximum slave mode frequency = f
CPU
/4.
Four programmable master bit rates
Programmable clock polarity and phase
End of transfer interrupt flag
Write collision flag protection
Master mode fault protection capability.
Figure 42. Serial Peripheral Interface Master/Slave
A basic example of interconnections between a single master and a single slave is illustrated on
Figure 42 .
The MOSI pins are connected together as are
MISO pins. In this way data is transferred serially between master and slave (most significant bit first).
When the master device transmits data to a slave device via MOSI pin, the slave device responds by sending data to the master device via the MISO pin. This implies full duplex transmission with both data out and data in synchronized with the same clock signal (which is provided by the master device via the SCK pin).
Thus, the byte transmitted is replaced by the byte received and eliminates the need for separate transmit-empty and receiver-full bits. A status flag is used to indicate that the I/O operation is complete.
Four possible data/clock timing relationships may be chosen (see Figure 45 ) but master and slave must be programmed with the same timing mode.
MASTER
MSBit LSBit
8-BIT SHIFT REGISTER
MISO MISO
SLAVE
MSBit
8-BIT SHIFT REGISTER
LSBit
MOSI MOSI
SPI
CLOCK
GENERATOR
SCK
SS
+5V
SCK
SS
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SERIAL PERIPHERAL INTERFACE (Cont’d)
Figure 43. Serial Peripheral Interface Block Diagram
Internal Bus
Read
Read Buffer
DR
MOSI
MISO
8-Bit Shift Register
IT request
SPIF WCOL MODF -
SR
-
Write
SCK
SS
SPI
STATE
CONTROL
CR
SPIE SPE SPR2 MSTR CPOL CPHA SPR1 SPR0
MASTER
CONTROL
SERIAL
CLOCK
GENERATOR
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SERIAL PERIPHERAL INTERFACE (Cont’d)
14.4.4 Functional Description
Figure 42 shows the serial peripheral interface
(SPI) block diagram.
This interface contains 3 dedicated registers:
– A Control Register (CR)
– A Status Register (SR)
– A Data Register (DR)
Refer to the CR, SR and DR registers in
14.4.7
for the bit definitions.
Section
In this configuration the MOSI pin is a data output and to the MISO pin is a data input.
Transmit sequence
The transmit sequence begins when a byte is written the DR register.
The data byte is parallel loaded into the 8-bit shift register (from the internal bus) during a write cycle and then shifted out serially to the MOSI pin most significant bit first.
14.4.4.1 Master Configuration
In a master configuration, the serial clock is generated on the SCK pin.
Procedure
– Select the SPR0 & SPR1 bits to define the serial clock baud rate (see CR register).
– Select the CPOL and CPHA bits to define one of the four relationships between the data transfer and the serial clock (see Figure 45 ).
– The SS pin must be connected to a high level signal during the complete byte transmit sequence.
– The MSTR and SPE bits must be set (they remain set only if the SS pin is connected to a high level signal).
When data transfer is complete:
– The SPIF bit is set by hardware
– An interrupt is generated if the SPIE bit is set and the I bit in the CCR register is cleared.
During the last clock cycle the SPIF bit is set, a copy of the data byte received in the shift register is moved to a buffer. When the DR register is read, the SPI peripheral returns this buffered value.
Clearing the SPIF bit is performed by the following software sequence:
1. An access to the SR register while the SPIF bit is set
2. A read to the DR register.
Note: While the SPIF bit is set, all writes to the DR register are inhibited until the SR register is read.
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SERIAL PERIPHERAL INTERFACE (Cont’d)
14.4.4.2 Slave Configuration
In slave configuration, the serial clock is received on the SCK pin from the master device.
The value of the SPR0 & SPR1 bits is not used for the data transfer.
Procedure
– For correct data transfer, the slave device must be in the same timing mode as the master device (CPOL and CPHA bits). See Figure
45 .
– The SS pin must be connected to a low level signal during the complete byte transmit sequence.
– Clear the MSTR bit and set the SPE bit to assign the pins to alternate function.
In this configuration the MOSI pin is a data input and the MISO pin is a data output.
Transmit Sequence
The data byte is parallel loaded into the 8-bit shift register (from the internal bus) during a write cycle and then shifted out serially to the MISO pin most significant bit first.
The transmit sequence begins when the slave device receives the clock signal and the most significant bit of the data on its MOSI pin.
When data transfer is complete:
– The SPIF bit is set by hardware
– An interrupt is generated if SPIE bit is set and
I bit in CCR register is cleared.
During the last clock cycle the SPIF bit is set, a copy of the data byte received in the shift register is moved to a buffer. When the DR register is read, the SPI peripheral returns this buffered value.
Clearing the SPIF bit is performed by the following software sequence:
1. An access to the SR register while the SPIF bit is set.
2.A read to the DR register.
Notes: While the SPIF bit is set, all writes to the
DR register are inhibited until the SR register is read.
The SPIF bit can be cleared during a second transmission; however, it must be cleared before the second SPIF bit in order to prevent an overrun condition (see Section 14.4.4.6
).
Depending on the CPHA bit, the SS pin has to be set to write to the DR register between each data byte transfer to avoid a write collision (see Section
14.4.4.4
).
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SERIAL PERIPHERAL INTERFACE (Cont’d)
14.4.4.3 Data Transfer Format
During an SPI transfer, data is simultaneously transmitted (shifted out serially) and received
(shifted in serially). The serial clock is used to synchronize the data transfer during a sequence of eight clock pulses.
The SS pin allows individual selection of a slave device; the other slave devices that are not selected do not interfere with the SPI transfer.
The master device applies data to its MOSI pinclock edge before the capture clock edge.
CPHA bit is set
The second edge on the SCK pin (falling edge if the CPOL bit is reset, rising edge if the CPOL bit is set) is the MSBit capture strobe. Data is latched on the occurrence of the second clock transition.
No write collision should occur even if the SS pin stays low during a transfer of several bytes (see
Figure 44 ).
Clock Phase and Clock Polarity
Four possible timing relationships may be chosen by software, using the CPOL and CPHA bits.
The CPOL (clock polarity) bit controls the steady state value of the clock when no data is being transferred. This bit affects both master and slave modes.
The combination between the CPOL and CPHA
(clock phase) bits selects the data capture clock edge.
Figure 45 , shows an SPI transfer with the four combinations of the CPHA and CPOL bits. The diagram may be interpreted as a master or slave timing diagram where the SCK pin, the MISO pin, the MOSI pin are directly connected between the master and the slave device.
The SS pin is the slave device select input and can be driven by the master device.
CPHA bit is reset
The first edge on the SCK pin (falling edge if CPOL bit is set, rising edge if CPOL bit is reset) is the
MSBit capture strobe. Data is latched on the occurrence of the first clock transition.
The SS pin must be toggled high and low between each byte transmitted (see Figure 44 ).
To protect the transmission from a write collision a low value on the SS pin of a slave device freezes the data in its DR register and does not allow it to be altered. Therefore the SS pin must be high to write a new data byte in the DR without producing a write collision.
Figure 44. CPHA / SS Timing Diagram
Byte 1 MOSI/MISO
Master SS
Slave SS
(CPHA=0)
Slave SS
(CPHA=1)
Byte 2 Byte 3
VR02131A
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SERIAL PERIPHERAL INTERFACE (Cont’d)
Figure 45. Data Clock Timing Diagram
SCLK (with
CPOL = 1)
SCLK (with
CPOL = 0)
CPHA =1
MISO
(from master)
MSBit Bit 6
MOSI
(from slave)
SS
(to slave)
CAPTURE STROBE
MSBit Bit 6
Bit 5 Bit 4
Bit 5 Bit 4
Bit3 Bit 2 Bit 1 LSBit
Bit3 Bit 2 Bit 1 LSBit
CPHA =0
CPOL = 1
CPOL = 0
MISO
(from master)
MOSI
(from slave)
MSBit
SS
(to slave)
CAPTURE STROBE
MSBit Bit 6
Bit 6
Bit 5 Bit 4
Bit 5 Bit 4
Bit3 Bit 2 Bit 1 LSBit
Bit3 Bit 2 Bit 1 LSBit
Note: This figure should not be used as a replacement for parametric information.
Refer to the Electrical Characteristics chapter.
VR02131B
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SERIAL PERIPHERAL INTERFACE (Cont’d)
14.4.4.4 Write Collision Error
A write collision occurs when the software tries to write to the DR register while a data transfer is taking place with an external device. When this happens, the transfer continues uninterrupted; and the software write will be unsuccessful.
Write collisions can occur both in master and slave mode.
Note: a "read collision" will never occur since the received data byte is placed in a buffer in which access is always synchronous with the MCU operation.
In Slave mode
When the CPHA bit is set:
The slave device will receive a clock (SCK) edge prior to the latch of the first data transfer. This first clock edge will freeze the data in the slave device
DR register and output the MSBit on to the external MISO pin of the slave device.
The SS pin low state enables the slave device but the output of the MSBit onto the MISO pin does not take place until the first data transfer clock edge.
When the CPHA bit is reset:
Data is latched on the occurrence of the first clock transition. The slave device does not have any way of knowing when that transition will occur; therefore, the slave device collision occurs when software attempts to write the DR register after its
SS pin has been pulled low.
For this reason, the SS pin must be high, between each data byte transfer, to allow the CPU to write in the DR register without generating a write collision.
In Master mode
Collision in the master device is defined as a write of the DR register while the internal serial clock
(SCK) is in the process of transfer.
The SS pin signal must be always high on the master device.
WCOL bit
The WCOL bit in the SR register is set if a write collision occurs.
No SPI interrupt is generated when the WCOL bit is set (the WCOL bit is a status flag only).
Clearing the WCOL bit is done through a software sequence (see Figure 46 ).
Figure 46. Clearing the WCOL bit (Write Collision Flag) Software Sequence
Clearing sequence after SPIF = 1 (end of a data byte transfer)
1st Step
Read SR
THEN
SPIF =0
WCOL=0
OR
Read SR
2nd Step
Read DR Write DR
THEN
SPIF =0
WCOL=0 if no transfer has started
WCOL=1 if a transfer has started before the 2nd step
Clearing sequence before SPIF = 1 (during a data byte transfer)
1st Step
Read SR
2nd Step
Read DR
THEN
WCOL=0
Note: Writing to the DR register instead of reading in it does not reset the WCOL bit
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SERIAL PERIPHERAL INTERFACE (Cont’d)
14.4.4.5 Master Mode Fault
Master mode fault occurs when the master device has its SS pin pulled low, then the MODF bit is set.
Master mode fault affects the SPI peripheral in the following ways:
– The MODF bit is set and an SPI interrupt is generated if the SPIE bit is set.
– The SPE bit is reset. This blocks all output from the device and disables the SPI peripheral.
– The MSTR bit is reset, thus forcing the device into slave mode.
may be restored to their original state during or after this clearing sequence.
Hardware does not allow the user to set the SPE and MSTR bits while the MODF bit is set except in the MODF bit clearing sequence.
In a slave device the MODF bit can not be set, but in a multi master configuration the device can be in slave mode with this MODF bit set.
The MODF bit indicates that there might have been a multi-master conflict for system control and allows a proper exit from system operation to a reset or default system state using an interrupt routine.
Clearing the MODF bit is done through a software sequence:
1. A read or write access to the SR register while the MODF bit is set.
2. A write to the CR register.
Notes: To avoid any multiple slave conflicts in the case of a system comprising several MCUs, the
SS pin must be pulled high during the clearing sequence of the MODF bit. The SPE and MSTR bits
14.4.4.6 Overrun Condition
An overrun condition occurs when the master device has sent several data bytes and the slave device has not cleared the SPIF bit issuing from the previous data byte transmitted.
In this case, the receiver buffer contains the byte sent after the SPIF bit was last cleared. A read to the DR register returns this byte. All other bytes are lost.
This condition is not detected by the SPI peripheral.
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SERIAL PERIPHERAL INTERFACE (Cont’d)
14.4.4.7 Single Master and Multimaster Configurations
There are two types of SPI systems:
– Single Master System
– Multimaster System
For more security, the slave device may respond to the master with the received data byte. Then the master will receive the previous byte back from the slave device if all MISO and MOSI pins are connected and the slave has not written its DR register.
Single Master System
A typical single master system may be configured, using an MCU as the master and four MCUs as slaves (see Figure 47 ).
Other transmission security methods can use ports for handshake lines or data bytes with command fields.
Multi-master System
The master device selects the individual slave devices by using four pins of a parallel port to control the four SS pins of the slave devices.
The SS pins are pulled high during reset since the master device ports will be forced to be inputs at that time, thus disabling the slave devices.
Note: To prevent a bus conflict on the MISO line the master allows only one active slave device during a transmission.
A multi-master system may also be configured by the user. Transfer of master control could be implemented using a handshake method through the
I/O ports or by an exchange of code messages through the serial peripheral interface system.
The multi-master system is principally handled by the MSTR bit in the CR register and the MODF bit in the SR register.
Figure 47. Single Master Configuration
SCK
Slave
MCU
MOSI
SS
MISO
SCK
Slave
MCU
MOSI
SS
MISO
SCK
Slave
MCU
SS
MOSI MISO
SCK
Slave
MCU
MOSI
SS
MISO
5V
MOSI MISO
SCK
Master
MCU
SS
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SERIAL PERIPHERAL INTERFACE (Cont’d)
14.4.5 Low Power Modes
Mode Description
WAIT
HALT
No effect on SPI.
SPI interrupt events cause the device to exit from WAIT mode.
SPI registers are frozen.
In HALT mode, the SPI is inactive. SPI operation resumes when the MCU is woken up by an interrupt with
“exit from HALT mode” capability.
14.4.6 Interrupts
Interrupt Event
SPI End of Transfer Event
Master Mode Fault Event
Note: The SPI interrupt events are connected to the same interrupt vector (see Interrupts chapter).
They generate an interrupt if the corresponding
Enable Control Bit is set and the interrupt mask in the CC register is reset (RIM instruction).
Event
Flag
Enable
Control
Bit
SPIF
MODF
SPIE
Exit from
Wait
Yes
Yes
Exit from
Halt
No
No
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SERIAL PERIPHERAL INTERFACE (Cont’d)
14.4.7 Register Description
CONTROL REGISTER (CR)
Read/Write
Reset Value: 0000xxxx (0xh)
7 0
SPIE SPE SPR2 MSTR CPOL CPHA SPR1 SPR0
Bit 7 = SPIE
Serial peripheral interrupt enable.
This bit is set and cleared by software.
0: Interrupt is inhibited
1: An SPI interrupt is generated whenever SPIF=1 or MODF=1 in the SR register
Bit 6 = SPE
Serial peripheral output enable.
This bit is set and cleared by software. It is also cleared by hardware when, in master mode, SS=0
(see Section 14.4.4.5 "Master Mode Fault" on page 79 ).
0: I/O port connected to pins
1: SPI alternate functions connected to pins
The SPE bit is cleared by reset, so the SPI peripheral is not initially connected to the external pins.
Bit 5 = SPR2
Divider Enable
.
this bit is set and cleared by software and it is cleared by reset. It is used with the SPR[1:0] bits to set the baud rate. Refer to Table 16 .
0: Divider by 2 enabled
1: Divider by 2 disabled
Bit 4 = MSTR
Master.
This bit is set and cleared by software. It is also cleared by hardware when, in master mode, SS=0
(see Section 14.4.4.5 "Master Mode Fault" on page 79 ).
0: Slave mode is selected
1: Master mode is selected, the function of the
SCK pin changes from an input to an output and the functions of the MISO and MOSI pins are reversed.
Bit 3 = CPOL
Clock polarity.
This bit is set and cleared by software. This bit determines the steady state of the serial Clock. The
CPOL bit affects both the master and slave modes.
0: The steady state is a low value at the SCK pin.
1: The steady state is a high value at the SCK pin.
Bit 2 = CPHA
Clock phase.
This bit is set and cleared by software.
0: The first clock transition is the first data capture edge.
1: The second clock transition is the first capture edge.
Bit 1:0 = SPR[1:0]
Serial peripheral rate.
These bits are set and cleared by software.Used
with the SPR2 bit, they select one of six baud rates to be used as the serial clock when the device is a master.
These 2 bits have no effect in slave mode.
Table 16. Serial Peripheral Baud Rate
Serial Clock f
CPU
/4 f
CPU
/8 f
CPU
/16 f
CPU
/32 f
CPU
/64 f
CPU
/128
SPR2 SPR1 SPR0
1 0 0
0 0 0
0
0
0
1
0
1
1
1
0
1
1
0
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SERIAL PERIPHERAL INTERFACE (Cont’d)
STATUS REGISTER (SR)
Read Only
Reset Value: 0000 0000 (00h)
7 0
SPIF WCOL MODF -
Bit 7 = SPIF
Serial Peripheral data transfer flag.
This bit is set by hardware when a transfer has been completed. An interrupt is generated if
SPIE=1 in the CR register. It is cleared by a software sequence (an access to the SR register followed by a read or write to the DR register).
0: Data transfer is in progress or has been approved by a clearing sequence.
1: Data transfer between the device and an external device has been completed.
Note: While the SPIF bit is set, all writes to the DR register are inhibited.
Bit 6 = WCOL
Write Collision status.
This bit is set by hardware when a write to the DR register is done during a transmit sequence. It is cleared by a software sequence (see Figure 46 ).
0: No write collision occurred
1: A write collision has been detected
Bit 5 = Unused.
DATA I/O REGISTER (DR)
Read/Write
Reset Value: Undefined
7
D7 D6 D5 D4 D3 D2 D1
0
D0
The DR register is used to transmit and receive data on the serial bus. In the master device only a write to this register will initiate transmission/reception of another byte.
Notes: During the last clock cycle the SPIF bit is set, a copy of the received data byte in the shift register is moved to a buffer. When the user reads the serial peripheral data I/O register, the buffer is actually being read.
Warning:
A write to the DR register places data directly into the shift register for transmission.
A read to the the DR register returns the value located in the buffer and not the contents of the shift register (See Figure 43 ).
Bit 4 = MODF
Mode Fault flag.
This bit is set by hardware when the SS pin is pulled low in master mode (see Section 14.4.4.5
"Master Mode Fault" on page 79 ). An SPI interrupt can be generated if SPIE=1 in the CR register.
This bit is cleared by a software sequence (An access to the SR register while MODF=1 followed by a write to the CR register).
0: No master mode fault detected
1: A fault in master mode has been detected
Bits 3-0 = Unused.
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SERIAL PERIPHERAL INTERFACE (Cont’d)
Table 17. SPI Register Map and Reset Values
Address
(Hex.)
0021h
0022h
0023h
Register
Label
SPIDR
Reset Value
SPICR
Reset Value
SPISR
Reset Value
7
MSB x
SPIE
0
SPIF
0
6 x
SPE
0
WCOL
0
5 x
SPR2
0
0
4 x
MSTR
0
MODF
0
3 x
CPOL x
0
2 x
CPHA x
0
1 x
SPR1 x
0
0
LSB x
SPR0 x
0
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14.5 SERIAL COMMUNICATIONS INTERFACE (SCI)
14.5.1 Introduction
The Serial Communications Interface (SCI) offers a flexible means of full-duplex data exchange with external equipment requiring an industry standard
NRZ asynchronous serial data format. The SCI offers a very wide range of baud rates using two baud rate generator systems.
14.5.2 Main Features
■
Full duplex, asynchronous communications
■
NRZ standard format (Mark/Space)
■
■
■
■
Dual baud rate generator systems
Independently programmable transmit and receive baud rates up to 250K baud using conventional baud rate generator and up to
500K baud using the extended baud rate generator.
Programmable data word length (8 or 9 bits)
Receive buffer full, Transmit buffer empty and
End of Transmission flags
■
■
■
■
■
■
Two receiver wake-up modes:
– Address bit (MSB)
– Idle line
Muting function for multiprocessor configurations
LIN compatible (if MCU clock frequency tolerance 2%)
Separate enable bits for Transmitter and
Receiver
Three error detection flags:
– Overrun error
– Noise error
– Frame error
Five interrupt sources with flags:
– Transmit data register empty
– Transmission complete
– Receive data register full
– Idle line received
– Overrun error detected
14.5.3 General Description
The interface is externally connected to another device by two pins (see Figure 2.):
– TDO: Transmit Data Output. When the transmitter is disabled, the output pin returns to its I/O port configuration. When the transmitter is enabled and nothing is to be transmitted, the TDO pin is at high level.
– RDI: Receive Data Input is the serial data input.
Oversampling techniques are used for data recovery by discriminating between valid incoming data and noise.
Through this pins, serial data is transmitted and received as frames comprising:
– An Idle Line prior to transmission or reception
– A start bit
– A data word (8 or 9 bits) least significant bit first
– A Stop bit indicating that the frame is complete.
This interface uses two types of baud rate generator:
– A conventional type for commonly-used baud rates,
– An extended type with a prescaler offering a very wide range of baud rates even with non-standard oscillator frequencies.
14.5.4 LIN Protocol support
For LIN applications where resynchronization is not required (application clock tolerance less than or equal to 2%) the LIN protocol can be efficiently implemented with this standard SCI.
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SERIAL COMMUNICATIONS INTERFACE (Cont’d)
Figure 48. SCI Block Diagram
Write
Transmit Data Register (TDR)
Read
(DATA REGISTER) DR
Received Data Register (RDR)
TDO
RDI
Transmit Shift Register Received Shift Register
R8 T8 M WAKE
-
CR1
f
CPU
TRANSMIT
CONTROL
WAKE
UP
UNIT
CR2
TIE TCIE RIE ILIE TE RE RWU SBK
SCI
INTERRUPT
CONTROL
TRANSMITTER
CLOCK
/16 /2 /PR
RECEIVER
CONTROL
RECEIVER
CLOCK
TDRE TC RDRF IDLE OR NF FE
SR
-
TRANSMITTER RATE
CONTROL
BRR
SCP1 SCP0 SCT2 SCT1 SCT0 SCR2 SCR1SCR0
RECEIVER RATE
CONTROL
CONVENTIONAL BAUD RATE GENERATOR
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SERIAL COMMUNICATIONS INTERFACE (Cont’d)
14.5.5 Functional Description
The block diagram of the Serial Control Interface, is shown in Figure 1.. It contains 6 dedicated registers:
– Two control registers (CR1 & CR2)
– A status register (SR)
– A baud rate register (BRR)
– An extended prescaler receiver register (ERPR)
– An extended prescaler transmitter register (ETPR)
Refer to the register descriptions in Section 0.1.8
for the definitions of each bit.
14.5.5.1 Serial Data Format
Word length may be selected as being either 8 or 9 bits by programming the M bit in the CR1 register
(see Figure 1.).
The TDO pin is in low state during the start bit.
The TDO pin is in high state during the stop bit.
An Idle character is interpreted as an entire frame of “1”s followed by the start bit of the next frame which contains data.
A Break character is interpreted on receiving “0”s for some multiple of the frame period. At the end of the last break frame the transmitter inserts an extra “1” bit to acknowledge the start bit.
Transmission and reception are driven by their own baud rate generator.
Figure 49. Word length programming
9-bit Word length (M bit is set)
Start
Bit Bit0 Bit1
Data Frame
Bit2 Bit3 Bit4 Bit5 Bit6 Bit7
Possible
Parity
Bit
Bit8
Next Data Frame
Stop
Bit
Next
Start
Bit
Idle Frame
Start
Bit
Break Frame Extra
’1’
Start
Bit
8-bit Word length (M bit is reset)
Start
Bit Bit0
Data Frame
Bit1 Bit2 Bit3 Bit4 Bit5 Bit6
Possible
Parity
Bit
Bit7
Stop
Bit
Next Data Frame
Next
Start
Bit
Idle Frame
Start
Bit
Break Frame Extra
’1’
Start
Bit
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SERIAL COMMUNICATIONS INTERFACE (Cont’d)
14.5.5.2 Transmitter
The transmitter can send data words of either 8 or
9 bits depending on the M bit status. When the M bit is set, word length is 9 bits and the 9th bit (the
MSB) has to be stored in the T8 bit in the CR1 register.
Character Transmission
During an SCI transmission, data shifts out least significant bit first on the TDO pin. In this mode, the DR register consists of a buffer (TDR) between the internal bus and the transmit shift register (see
Figure 1.).
Procedure
– Select the M bit to define the word length.
– Select the desired baud rate using the BRR and the ETPR registers.
– Set the TE bit to assign the TDO pin to the alternate function and to send a idle frame as first transmission.
– Access the SR register and write the data to send in the DR register (this sequence clears the
TDRE bit). Repeat this sequence for each data to be transmitted.
Clearing the TDRE bit is always performed by the following software sequence:
1. An access to the SR register
2. A write to the DR register
The TDRE bit is set by hardware and it indicates:
– The TDR register is empty.
– The data transfer is beginning.
– The next data can be written in the DR register without overwriting the previous data.
This flag generates an interrupt if the TIE bit is set and the I bit is cleared in the CCR register.
When a transmission is taking place, a write instruction to the DR register stores the data in the
TDR register and which is copied in the shift register at the end of the current transmission.
When no transmission is taking place, a write instruction to the DR register places the data directly in the shift register, the data transmission starts, and the TDRE bit is immediately set.
When a frame transmission is complete (after the stop bit or after the break frame) the TC bit is set and an interrupt is generated if the TCIE is set and the I bit is cleared in the CCR register.
Clearing the TC bit is performed by the following software sequence:
1. An access to the SR register
2. A write to the DR register
Note: The TDRE and TC bits are cleared by the same software sequence.
Break Characters
Setting the SBK bit loads the shift register with a break character. The break frame length depends on the M bit (see Figure 2.).
As long as the SBK bit is set, the SCI send break frames to the TDO pin. After clearing this bit by software the SCI insert a logic 1 bit at the end of the last break frame to guarantee the recognition of the start bit of the next frame.
Idle Characters
Setting the TE bit drives the SCI to send an idle frame before the first data frame.
Clearing and then setting the TE bit during a transmission sends an idle frame after the current word.
Note: Resetting and setting the TE bit causes the data in the TDR register to be lost. Therefore the best time to toggle the TE bit is when the TDRE bit is set i.e. before writing the next byte in the DR.
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SERIAL COMMUNICATIONS INTERFACE (Cont’d)
14.5.5.3 Receiver
The SCI can receive data words of either 8 or 9 bits. When the M bit is set, word length is 9 bits and the MSB is stored in the R8 bit in the CR1 register.
Character reception
During a SCI reception, data shifts in least significant bit first through the RDI pin. In this mode, DR register consists in a buffer (RDR) between the internal bus and the received shift register (see Figure 1.).
Procedure
– Select the M bit to define the word length.
– Select the desired baud rate using the BRR and the ERPR registers.
– Set the RE bit, this enables the receiver which begins searching for a start bit.
When a character is received:
– The RDRF bit is set. It indicates that the content of the shift register is transferred to the RDR.
– An interrupt is generated if the RIE bit is set and the I bit is cleared in the CCR register.
– The error flags can be set if a frame error, noise or an overrun error has been detected during reception.
Clearing the RDRF bit is performed by the following software sequence done by:
1. An access to the SR register
2. A read to the DR register.
The RDRF bit must be cleared before the end of the reception of the next character to avoid an overrun error.
Break Character
When a break character is received, the SCI handles it as a framing error.
Idle Character
When a idle frame is detected, there is the same procedure as a data received character plus an interrupt if the ILIE bit is set and the I bit is cleared in the CCR register.
Overrun Error
An overrun error occurs when a character is received when RDRF has not been reset. Data can not be transferred from the shift register to the
TDR register as long as the RDRF bit is not cleared.
When a overrun error occurs:
– The OR bit is set.
– The RDR content will not be lost.
– The shift register will be overwritten.
– An interrupt is generated if the RIE bit is set and the I bit is cleared in the CCR register.
The OR bit is reset by an access to the SR register followed by a DR register read operation.
Noise Error
Oversampling techniques are used for data recovery by discriminating between valid incoming data and noise.
When noise is detected in a frame:
– The NF is set at the rising edge of the RDRF bit.
– Data is transferred from the Shift register to the
DR register.
– No interrupt is generated. However this bit rises at the same time as the RDRF bit which itself generates an interrupt.
The NF bit is reset by a SR register read operation followed by a DR register read operation.
Framing Error
A framing error is detected when:
– The stop bit is not recognized on reception at the expected time, following either a de-synchronization or excessive noise.
– A break is received.
When the framing error is detected:
– the FE bit is set by hardware
– Data is transferred from the Shift register to the
DR register.
– No interrupt is generated. However this bit rises at the same time as the RDRF bit which itself generates an interrupt.
The FE bit is reset by a SR register read operation followed by a DR register read operation.
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SERIAL COMMUNICATIONS INTERFACE (Cont’d)
Figure 50. SCI Baud Rate and Extended Prescaler Block Diagram
EXTENDED PRESCALER TRANSMITTER RATE CONTROL
ETPR
EXTENDED TRANSMITTER PRESCALER REGISTER
ERPR
EXTENDED RECEIVER PRESCALER REGISTER
EXTENDED PRESCALER RECEIVER RATE CONTROL
EXTENDED PRESCALER f
CPU
/16 /2 /PR
TRANSMITTER RATE
CONTROL
BRR
SCP1 SCP0 SCT2 SCT1 SCT0 SCR2 SCR1SCR0
RECEIVER RATE
CONTROL
CONVENTIONAL BAUD RATE GENERATOR
TRANSMITTER
CLOCK
RECEIVER
CLOCK
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SERIAL COMMUNICATIONS INTERFACE (Cont’d)
14.5.5.4 Conventional Baud Rate Generation
The baud rate for the receiver and transmitter (Rx and Tx) are set independently and calculated as follows:
Tx = f
CPU
(32
*
PR)
*
TR f
CPU
Rx =
(32
*
PR)
*
RR with:
PR = 1, 3, 4 or 13 (see SCP0 & SCP1 bits)
TR = 1, 2, 4, 8, 16, 32, 64,128
(see SCT0, SCT1 & SCT2 bits)
RR = 1, 2, 4, 8, 16, 32, 64,128
(see SCR0,SCR1 & SCR2 bits)
All this bits are in the BRR register.
Example: If f
CPU
is 8 MHz (normal mode) and if
PR=13 and TR=RR=1, the transmit and receive baud rates are 19200 baud.
Caution: The baud rate register (SCIBRR) MUST
NOT be written to (changed or refreshed) while the transmitter or the receiver is enabled.
14.5.5.5 Extended Baud Rate Generation
The extended prescaler option gives a very fine tuning on the baud rate, using a 255 value prescaler, whereas the conventional Baud Rate Generator retains industry standard software compatibility.
The extended baud rate generator block diagram is described in the Figure 3..
The output clock rate sent to the transmitter or to the receiver will be the output from the 16 divider divided by a factor ranging from 1 to 255 set in the
ERPR or the ETPR register.
Note: the extended prescaler is activated by setting the ETPR or ERPR register to a value other than zero. The baud rates are calculated as follows:
Tx = f
CPU
16
*
ETPR
Rx = f
CPU
16
*
ERPR with:
ETPR = 1,..,255 (see ETPR register)
ERPR = 1,.. 255 (see ERPR register)
14.5.5.6 Receiver Muting and Wake-up Feature
In multiprocessor configurations it is often desirable that only the intended message recipient should actively receive the full message contents, thus reducing redundant SCI service overhead for all non addressed receivers.
The non addressed devices may be placed in sleep mode by means of the muting function.
Setting the RWU bit by software puts the SCI in sleep mode:
All the reception status bits can not be set.
All the receive interrupt are inhibited.
A muted receiver may be awakened by one of the following two ways:
– by Idle Line detection if the WAKE bit is reset,
– by Address Mark detection if the WAKE bit is set.
Receiver wakes-up by Idle Line detection when the Receive line has recognised an Idle Frame.
Then the RWU bit is reset by hardware but the
IDLE bit is not set.
Receiver wakes-up by Address Mark detection when it received a “1” as the most significant bit of a word, thus indicating that the message is an address. The reception of this particular word wakes up the receiver, resets the RWU bit and sets the
RDRF bit, which allows the receiver to receive this word normally and to use it as an address word.
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SERIAL COMMUNICATIONS INTERFACE (Cont’d)
14.5.6 Low Power Modes
Mode Description
No effect on SCI.
WAIT
SCI interrupts cause the device to exit from Wait mode.
SCI registers are frozen.
HALT
In Halt mode, the SCI stops transmitting/receiving until Halt mode is exited.
14.5.7 Interrupts
Interrupt Event
Transmit Data Register Empty
Transmission Complete
Received Data Ready to be Read
Overrrun Error Detected
Idle Line Detected
The SCI interrupt events are connected to the same interrupt vector (see Interrupts chapter).
Event
Flag
TDRE
TC
RDRF
OR
IDLE
Enable
Control
Bit
TIE
TCIE
RIE
ILIE
Exit from
Wait
Yes
Yes
Yes
Yes
Yes
Exit from
Halt
No
No
No
No
No
These events generate an interrupt if the corresponding Enable Control Bit is set and the interrupt mask in the CC register is reset (RIM instruction).
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SERIAL COMMUNICATIONS INTERFACE (Cont’d)
14.5.8 Register Description
STATUS REGISTER (SR)
Read Only
Reset Value: 1100 0000 (C0h)
Note: The IDLE bit will not be set again until the
RDRF bit has been set itself (i.e. a new idle line occurs). This bit is not set by an idle line when the receiver wakes up from wake-up mode.
7
TDRE TC RDRF IDLE OR
Bit 7 = TDRE
This bit is set by hardware when the content of the
TDR register has been transferred into the shift register. An interrupt is generated if the TIE =1 in the CR2 register. It is cleared by a software sequence (an access to the SR register followed by a write to the DR register).
0: Data is not transferred to the shift register
1: Data is transferred to the shift register
Note: data will not be transferred to the shift register as long as the TDRE bit is not reset.
Bit 6 = TC
NF
Transmit data register empty.
Transmission complete.
FE
0
-
This bit is set by hardware when transmission of a frame containing Data, a Preamble or a Break is complete. An interrupt is generated if TCIE=1 in the CR2 register. It is cleared by a software sequence (an access to the SR register followed by a write to the DR register).
0: Transmission is not complete
1: Transmission is complete
Bit 3 = OR
Overrun error.
This bit is set by hardware when the word currently being received in the shift register is ready to be transferred into the RDR register while RDRF=1.
An interrupt is generated if RIE=1 in the CR2 register. It is cleared by a software sequence (an access to the SR register followed by a read to the
DR register).
0: No Overrun error
1: Overrun error is detected
Note: When this bit is set RDR register content will not be lost but the shift register will be overwritten.
Bit 2 = NF
Noise flag.
This bit is set by hardware when noise is detected on a received frame. It is cleared by a software sequence (an access to the SR register followed by a read to the DR register).
0: No noise is detected
1: Noise is detected
Note: This bit does not generate interrupt as it appears at the same time as the RDRF bit which itself generates an interrupt.
Bit 5 = RDRF
Received data ready flag.
This bit is set by hardware when the content of the
RDR register has been transferred into the DR register. An interrupt is generated if RIE=1 in the
CR2 register. It is cleared by a software sequence
(an access to the SR register followed by a read to the DR register).
0: Data is not received
1: Received data is ready to be read
Bit 1 = FE
Framing error.
This bit is set by hardware when a de-synchronization, excessive noise or a break character is detected. It is cleared by a software sequence (an access to the SR register followed by a read to the
DR register).
0: No Framing error is detected
1: Framing error or break character is detected
Note: This bit does not generate interrupt as it appears at the same time as the RDRF bit which itself generates an interrupt. If the word currently being transferred causes both frame error and overrun error, it will be transferred and only the OR bit will be set.
Bit 4 = IDLE
Idle line detect.
This bit is set by hardware when a Idle Line is detected. An interrupt is generated if the ILIE=1 in the CR2 register. It is cleared by a software sequence (an access to the SR register followed by a read to the DR register).
0: No Idle Line is detected
1: Idle Line is detected
Bit 0 = Unused.
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SERIAL COMMUNICATIONS INTERFACE (Cont’d)
CONTROL REGISTER 1 (CR1)
Read/Write
Reset Value: Undefined
1: An SCI interrupt is generated whenever TC=1 in the SR register
7
R8 T8 M WAKE -
0
-
Bit 5 = RIE
Receiver interrupt enable
.
This bit is set and cleared by software.
0: interrupt is inhibited
1: An SCI interrupt is generated whenever OR=1 or RDRF=1 in the SR register
Bit 7 = R8
Receive data bit 8.
This bit is used to store the 9th bit of the received word when M=1.
Bit 4 = ILIE
Idle line interrupt enable.
This bit is set and cleared by software.
0: interrupt is inhibited
1: An SCI interrupt is generated whenever IDLE=1 in the SR register.
Bit 6 = T8
Transmit data bit 8.
This bit is used to store the 9th bit of the transmitted word when M=1.
Bit 4 = M
Word length.
This bit determines the word length. It is set or cleared by software.
0: 1 Start bit, 8 Data bits, 1 Stop bit
1: 1 Start bit, 9 Data bits, 1 Stop bit
Bit 3 = TE
Transmitter enable.
This bit enables the transmitter and assigns the
TDO pin to the alternate function. It is set and cleared by software.
0: Transmitter is disabled, the TDO pin is back to the I/O port configuration.
1: Transmitter is enabled
Note: during transmission, a “0” pulse on the TE bit (“0” followed by “1”) sends a preamble after the current word.
Bit 3 = WAKE
Wake-Up method.
This bit determines the SCI Wake-Up method, it is set or cleared by software.
0: Idle Line
1: Address Mark
CONTROL REGISTER 2 (CR2)
Read/Write
Reset Value: 0000 0000 (00 h)
Bit 2 = RE
Receiver enable.
This bit enables the receiver. It is set and cleared by software.
0: Receiver is disabled.
1: Receiver is enabled and begins searching for a start bit.
7
TIE TCIE RIE ILIE TE RE RWU
0
SBK
Bit 1 = RWU
Receiver wake-up.
This bit determines if the SCI is in mute mode or not. It is set and cleared by software and can be cleared by hardware when a wake-up sequence is recognized.
0: Receiver in active mode
1: Receiver in mute mode
Bit 7 = TIE
Transmitter interrupt enable
.
This bit is set and cleared by software.
0: interrupt is inhibited
1: An SCI interrupt is generated whenever
TDRE=1 in the SR register.
Bit 6 = TCIE
Transmission complete interrupt enable
This bit is set and cleared by software.
0: interrupt is inhibited
Bit 0 = SBK
Send break.
This bit set is used to send break characters. It is set and cleared by software.
0: No break character is transmitted
1: Break characters are transmitted
Note: If the SBK bit is set to “1” and then to “0”, the transmitter will send a BREAK word at the end of the current word.
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SERIAL COMMUNICATIONS INTERFACE (Cont’d)
DATA REGISTER (DR)
Read/Write
Reset Value: Undefined
Contains the Received or Transmitted data character, depending on whether it is read from or written to.
Bit 5:3 = SCT[2:0]
SCI Transmitter rate divisor
These 3 bits, in conjunction with the SCP1 & SCP0 bits define the total division applied to the bus clock to yield the transmit rate clock in conventional Baud Rate Generator mode.
7 0
DR7 DR6 DR5 DR4 DR3 DR2 DR1 DR0
The Data register performs a double function (read and write) since it is composed of two registers, one for transmission (TDR) and one for reception
(RDR).
The TDR register provides the parallel interface between the internal bus and the output shift register (see Figure 1.).
The RDR register provides the parallel interface between the input shift register and the internal bus (see Figure 1.).
BAUD RATE REGISTER (BRR)
Read/Write
Reset Value: 00xx xxxx (XXh)
TR dividing factor
1
2
4
8
16
32
64
128
SCT2
0
0
1
0
0
1
1
1
SCT1
0
1
0
0
1
0
1
1
SCT0
0
1
0
1
0
1
0
1
Note: this TR factor is used only when the ETPR fine tuning factor is equal to 00h; otherwise, TR is replaced by the ETPR dividing factor.
Bit 2:0 = SCR[2:0]
SCI Receiver rate divisor.
These 3 bits, in conjunction with the SCP1 & SCP0 bits define the total division applied to the bus clock to yield the receive rate clock in conventional
Baud Rate Generator mode.
7 0
SCP1 SCP0 SCT2 SCT1 SCT0 SCR2 SCR1 SCR0
Bit 7:6= SCP[1:0]
First SCI Prescaler
These 2 prescaling bits allow several standard clock division ranges:
PR Prescaling factor
1
3
4
13
SCP1
0
0
1
1
SCP0
0
1
0
1
RR dividing factor
1
2
4
8
16
32
64
128
SCR2
0
0
0
0
1
1
1
1
SCR1
0
0
1
1
0
0
1
1
SCR0
0
1
0
1
0
1
0
1
Note: this RR factor is used only when the ERPR fine tuning factor is equal to 00h; otherwise, RR is replaced by the ERPR dividing factor.
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SERIAL COMMUNICATIONS INTERFACE (Cont’d)
EXTENDED RECEIVE PRESCALER DIVISION
REGISTER (ERPR)
Read/Write
Reset Value: 0000 0000 (00 h)
Allows setting of the Extended Prescaler rate division factor for the receive circuit.
EXTENDED TRANSMIT PRESCALER DIVISION
REGISTER (ETPR)
Read/Write
Reset Value:0000 0000 (00h)
Allows setting of the External Prescaler rate division factor for the transmit circuit.
7 0
ERPR
7
ERPR
6
ERPR
5
ERPR
4
ERPR
3
ERPR
2
ERPR
1
ERPR
0
7 0
ETPR
7
ETPR
6
ETPR
5
ETPR
4
ETPR
3
ETPR
2
ETPR
1
ETPR
0
Bit 7:1 = ERPR[7:0]
8-bit Extended Receive Prescaler Register.
The extended Baud Rate Generator is activated when a value different from 00h is stored in this register. Therefore the clock frequency issued from the 16 divider (see Figure 3.) is divided by the binary factor set in the ERPR register (in the range
1 to 255).
The extended baud rate generator is not used after a reset.
Bit 7:1 = ETPR[7:0]
8-bit Extended Transmit Prescaler Register.
The extended Baud Rate Generator is activated when a value different from 00h is stored in this register. Therefore the clock frequency issued from the 16 divider (see Figure 3.) is divided by the binary factor set in the ETPR register (in the range
1 to 255).
The extended baud rate generator is not used after a reset.
Table 18. SCI Register Map and Reset Values
Address
(Hex.)
0050h
0051h
0052h
0053h
0054h
0055h
0057h
Register
Label
SCISR
Reset Value
SCIDR
Reset Value
SCIBRR
Reset Value
SCICR1
Reset Value
SCICR2
Reset Value
SCIPBRR
Reset Value
SCIPBRT
Reset Value
7
TDRE
1
MSB x
SOG
0
R8 x
TIE
0
MSB
0
MSB
0
6
TC
1 x
0
T8 x
TCIE
0
0
0
5
RDRF
0 x
VPOL x
0
RIE
0
0
0
4 3 2 1 0
IDLE
0
OR
0
NF
0
FE
0 x
2FHDET x
M x
ILIE
0 x
HVSEL x
WAKE x
TE
0 x x
VCORDIS x
CLPINV x
0
RE
0
0
RWU
0
0
LSB x
BLKINV x
0
0
0
0
0
0
0
0
0
SBK
0
LSB
0
LSB
0
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14.6 8-BIT A/D CONVERTER (ADC)
14.6.1 Introduction
The on-chip Analog to Digital Converter (ADC) peripheral is a 8-bit, successive approximation converter with internal sample and hold circuitry. This peripheral has up to 16 multiplexed analog input channels (refer to device pin out description) that allow the peripheral to convert the analog voltage levels from up to 16 different sources.
The result of the conversion is stored in a 8-bit
Data Register. The A/D converter is controlled through a Control/Status Register.
14.6.2 Main Features
■
■
■
■
■
■
8-bit conversion
Up to 16 channels with multiplexed input
Linear successive approximation
Data register (DR) which contains the results
Conversion complete status flag
On/off bit (to reduce consumption)
The block diagram is shown in Figure 51 .
Figure 51. ADC Block Diagram
14.6.3 Functional Description
14.6.3.1 Analog Power Supply
V
DDA
and V
SSA
are the high and low level reference voltage pins. In some devices (refer to device pin out description) they are internally connected to the V
DD
and V
SS
pins.
Conversion accuracy may therefore be impacted by voltage drops and noise in the event of heavily loaded or badly decoupled power supply lines.
See electrical characteristics section for more details.
f
CPU f
ADC
DIV 2
AIN0
AIN1
AINx
COCO 0 ADON 0 CH3 CH2 CH1 CH0 ADCCSR
4
HOLD CONTROL
ANALOG
MUX
R
ADC
ANALOG TO DIGITAL
CONVERTER
C
ADC
ADCDR
D7 D6 D5 D4 D3 D2 D1 D0
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8-BIT A/D CONVERTER (ADC) (Cont’d)
14.6.3.2 Digital A/D Conversion Result
The conversion is monotonic, meaning that the result never decreases if the analog input does not and never increases if the analog input does not.
If the input voltage (V
AIN to V
DDA
) is greater than or equal
(high-level voltage reference) then the conversion result in the DR register is FFh (full scale) without overflow indication.
If input voltage (V
AIN
V
SSA
) is lower than or equal to
(low-level voltage reference) then the conversion result in the DR register is 00h.
The A/D converter is linear and the digital result of the conversion is stored in the ADCDR register.
The accuracy of the conversion is described in the parametric section.
R
AIN
is the maximum recommended impedance for an analog input signal. If the impedance is too high, this will result in a loss of accuracy due to leakage and sampling not being completed in the alloted time.
14.6.3.3 A/D Conversion Phases
The A/D conversion is based on two conversion phases as shown in Figure 52 :
■
Sample capacitor loading [duration: t
LOAD
During this phase, the V
AIN
]
input voltage to be measured is loaded into the C
ADC capacitor.
sample
■
A/D conversion [duration: t
CONV
]
During this phase, the A/D conversion is computed (8 successive approximations cycles) and the C
ADC
sample capacitor is disconnected from the analog input pin to get the optimum analog to digital conversion accuracy.
While the ADC is on, these two phases are continuously repeated.
At the end of each conversion, the sample capacitor is kept loaded with the previous measurement load. The advantage of this behaviour is that it minimizes the current consumption on the analog pin in case of single input channel measurement.
14.6.3.4 Software Procedure
Refer to the control/status register (CSR) and data register (DR) in Section 14.6.6
for the bit definitions and to Figure 52 for the timings.
ADC Configuration
The total duration of the A/D conversion is 12 ADC clock periods (1/f
ADC
=2/f
CPU
).
The analog input ports must be configured as input, no pull-up, no interrupt. Refer to the «I/O ports» chapter. Using these pins as analog inputs does not affect the ability of the port to be read as a logic input.
In the CSR register:
– Select the CH[3:0] bits to assign the analog channel to be converted.
ADC Conversion
In the CSR register:
– Set the ADON bit to enable the A/D converter and to start the first conversion. From this time on, the ADC performs a continuous conversion of the selected channel.
When a conversion is complete
– The COCO bit is set by hardware.
– No interrupt is generated.
– The result is in the DR register and remains valid until the next conversion has ended.
A write to the CSR register (with ADON set) aborts the current conversion, resets the COCO bit and starts a new conversion.
Figure 52. ADC Conversion Timings
ADON
HOLD
CONTROL t
LOAD t
CONV
ADCCSR WRITE
OPERATION
COCO BIT SET
14.6.4 Low Power Modes
Mode Description
WAIT
HALT
No effect on A/D Converter
A/D Converter disabled.
After wakeup from Halt mode, the A/D Converter requires a stabilisation time before accurate conversions can be performed.
Note: The A/D converter may be disabled by resetting the ADON bit. This feature allows reduced power consumption when no conversion is needed and between single shot conversions.
14.6.5 Interrupts
None
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8-BIT A/D CONVERTER (ADC) (Cont’d)
14.6.6 Register Description
CONTROL/STATUS REGISTER (CSR)
Read /Write
Reset Value: 0000 0000 (00h)
7
COCO 0 ADON 0
0
CH3 CH2 CH1 CH0
Bit 7 = COCO
Conversion Complete
This bit is set by hardware. It is cleared by software reading the result in the DR register or writing to the CSR register.
0: Conversion is not complete
1: Conversion can be read from the DR register
DATA REGISTER (DR)
Read Only
Reset Value: 0000 0000 (00h)
7
D7 D6 D5 D4 D3 D2 D1
0
D0
Bits 7:0 = D[7:0]
Analog Converted Value
This register contains the converted analog value in the range 00h to FFh.
Note: Reading this register reset the COCO flag.
Bit 6 = Reserved.
must always be cleared.
Bit 5 = ADON
A/D Converter On
This bit is set and cleared by software.
0: A/D converter is switched off
1: A/D converter is switched on
Bit 4 = Reserved.
must always be cleared.
Bits 3:0 = CH[3:0]
Channel Selection
These bits are set and cleared by software. They select the analog input to convert.
Channel Pin*
AIN0
AIN1
AIN2
AIN3
AIN4
AIN5
AIN6
AIN7
AIN8
AIN9
AIN10
AIN11
AIN12
AIN13
AIN14
AIN15
1
1
1
0
1
0
0
0
0
0
0
0
1
1
1
1
CH3 CH2 CH1 CH0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
1
1
1
0
0
0
1
1
1
0
0
0
0
1
1
1
0
1
1
0
0
1
0
0
1
0
1
0
1
0
1
*Note: The number of pins AND the channel selection varies according to the device. Refer to the device pinout.
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8-BIT A/D CONVERTER (ADC) (Cont’d)
Table 19. ADC Register Map and Reset Values
Address
(Hex.)
0070h
0071h
Register
Label
ADCDR
Reset Value
ADCCSR
Reset Value
7
D7
0
COCO
0
6
D6
0
0
5
D5
0
ADON
0
4
D4
0
0
3
D3
0
CH3
0
2
D2
0
CH2
0
1
D1
0
CH1
0
0
D0
0
CH0
0
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15 INSTRUCTION SET
15.1 ST7 ADDRESSING MODES
The ST7 Core features 17 different addressing modes which can be classified in 7 main groups:
Addressing Mode
Inherent
Immediate
Direct
Indexed
Indirect
Relative
Bit operation
Inherent
Immediate
Short
Long
No Offset
Short
Long
Short
Long
Short
Long
Relative
Relative
Bit
Bit
Bit
Bit
Example nop ld A,#$55 ld A,$55 ld A,($55,X) ld A,([$55],X) jrne loop bset byte,#5 so, most of the addressing modes may be subdivided in two sub-modes called long and short:
– Long addressing mode is more powerful because it can use the full 64 Kbyte address space, however it uses more bytes and more CPU cycles.
– Short addressing mode is less powerful because it can generally only access page zero (0000h -
00FFh range), but the instruction size is more compact, and faster. All memory to memory instructions use short addressing modes only
(CLR, CPL, NEG, BSET, BRES, BTJT, BTJF,
INC, DEC, RLC, RRC, SLL, SRL, SRA, SWAP)
The ST7 Assembler optimizes the use of long and short addressing modes.
The ST7 Instruction set is designed to minimize the number of bytes required per instruction: To do
Table 20. ST7 Addressing Mode Overview
Mode
Direct
Direct
Direct Indexed nop
Syntax ld A,#$55 ld A,$10 ld A,$1000 ld A,(X)
Destination/
Source
00..FF
0000..FFFF
00..FF
Direct
Direct
Indirect
Indexed ld A,($10,X) 00..1FE
Indexed ld A,($1000,X) 0000..FFFF
ld A,[$10] 00..FF
Indirect ld A,[$10.w]
Indirect Indexed ld A,([$10],X)
0000..FFFF
00..1FE
Indirect Indexed ld A,([$10.w],X) 0000..FFFF
Direct jrne loop PC-128/PC+127
1)
Indirect jrne [$10] PC-128/PC+127
1)
Direct bset $10,#7 00..FF
Indirect bset [$10],#7 00..FF
Direct Relative btjt $10,#7,skip 00..FF
Indirect Relative btjt [$10],#7,skip 00..FF
00..FF
00..FF
00..FF
00..FF
00..FF
00..FF
00..FF
Pointer
Address
(Hex.)
Pointer
Size
(Hex.) byte word byte word byte byte byte
Length
(Bytes)
+ 2
+ 1
+ 2
+ 2
+ 3
+ 1
+ 2
+ 2
+ 2
+ 2
+ 2
+ 1
+ 0
+ 1
+ 1
+ 2
+ 0 (with X register)
+ 1 (with Y register)
Note 1. At the time the instruction is executed, the Program Counter (PC) points to the instruction following JRxx.
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ST7 ADDRESSING MODES (Cont’d)
15.1.1 Inherent
All Inherent instructions consist of a single byte.
The opcode fully specifies all the required information for the CPU to process the operation.
Inherent Instruction
NOP
TRAP
WFI
HALT
RET
IRET
SIM
RIM
SCF
RCF
RSP
LD
CLR
PUSH/POP
INC/DEC
TNZ
CPL, NEG
MUL
SLL, SRL, SRA, RLC,
RRC
SWAP
Function
No operation
S/W Interrupt
Wait For Interrupt (Low Power
Mode)
Halt Oscillator (Lowest Power
Mode)
Sub-routine Return
Interrupt Sub-routine Return
Set Interrupt Mask
Reset Interrupt Mask
Set Carry Flag
Reset Carry Flag
Reset Stack Pointer
Load
Clear
Push/Pop to/from the stack
Increment/Decrement
Test Negative or Zero
1 or 2 Complement
Byte Multiplication
Shift and Rotate Operations
Swap Nibbles
15.1.2 Immediate
Immediate instructions have two bytes, the first byte contains the opcode, the second byte contains the operand value.
Immediate Instruction
LD
CP
Load
Compare
Function
BCP
AND, OR, XOR
Bit Compare
Logical Operations
ADC, ADD, SUB, SBC Arithmetic Operations
15.1.3 Direct
In Direct instructions, the operands are referenced by their memory address.
The direct addressing mode consists of two submodes:
Direct (short)
The address is a byte, thus requires only one byte after the opcode, but only allows 00 - FF addressing space.
Direct (long)
The address is a word, thus allowing 64 Kbyte addressing space, but requires 2 bytes after the opcode.
15.1.4 Indexed (No Offset, Short, Long)
In this mode, the operand is referenced by its memory address, which is defined by the unsigned addition of an index register (X or Y) with an offset.
The indirect addressing mode consists of three sub-modes:
Indexed (No Offset)
There is no offset, (no extra byte after the opcode), and allows 00 - FF addressing space.
Indexed (Short)
The offset is a byte, thus requires only one byte after the opcode and allows 00 - 1FE addressing space.
Indexed (long)
The offset is a word, thus allowing 64 Kbyte addressing space and requires 2 bytes after the opcode.
15.1.5 Indirect (Short, Long)
The required data byte to do the operation is found by its memory address, located in memory (pointer).
The pointer address follows the opcode. The indirect addressing mode consists of two sub-modes:
Indirect (short)
The pointer address is a byte, the pointer size is a byte, thus allowing 00 - FF addressing space, and requires 1 byte after the opcode.
Indirect (long)
The pointer address is a byte, the pointer size is a word, thus allowing 64 Kbyte addressing space, and requires 1 byte after the opcode.
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ST7 ADDRESSING MODES (Cont’d)
15.1.6 Indirect Indexed (Short, Long)
This is a combination of indirect and short indexed addressing modes. The operand is referenced by its memory address, which is defined by the unsigned addition of an index register value (X or Y) with a pointer value located in memory. The pointer address follows the opcode.
The indirect indexed addressing mode consists of two sub-modes:
Indirect Indexed (Short)
The pointer address is a byte, the pointer size is a byte, thus allowing 00 - 1FE addressing space, and requires 1 byte after the opcode.
Indirect Indexed (Long)
The pointer address is a byte, the pointer size is a word, thus allowing 64 Kbyte addressing space, and requires 1 byte after the opcode.
Table 21. Instructions Supporting Direct,
Indexed, Indirect and Indirect Indexed
Addressing Modes
Long and Short
Instructions
LD
CP
AND, OR, XOR
ADC, ADD, SUB, SBC
BCP
Function
Load
Compare
Logical Operations
Arithmetic Addition/subtraction operations
Bit Compare
SWAP
CALL, JP
Swap Nibbles
Call or Jump subroutine
15.1.7 Relative Mode (Direct, Indirect)
This addressing mode is used to modify the PC register value by adding an 8-bit signed offset to it.
Available Relative Direct/
Indirect Instructions
JRxx
CALLR
Function
Conditional Jump
Call Relative
The relative addressing mode consists of two submodes:
Relative (Direct)
The offset follows the opcode.
Relative (Indirect)
The offset is defined in memory, of which the address follows the opcode.
Short Instructions Only
CLR
INC, DEC
TNZ
CPL, NEG
BSET, BRES
BTJT, BTJF
Function
Clear
Increment/Decrement
Test Negative or Zero
1 or 2 Complement
Bit Operations
Bit Test and Jump Operations
SLL, SRL, SRA, RLC,
RRC
Shift and Rotate Operations
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15.2 INSTRUCTION GROUPS
The ST7 family devices use an Instruction Set consisting of 63 instructions. The instructions may
Load and Transfer
Stack operation
Increment/Decrement
Compare and Tests
Logical operations
Bit Operation
Conditional Bit Test and Branch
Arithmetic operations
Shift and Rotates
Unconditional Jump or Call
Conditional Branch
Interruption management
Condition Code Flag modification
LD
PUSH
INC
CP
AND
BSET
BTJT
ADC
SLL
JRA
JRxx
TRAP
SIM
CLR
POP
DEC
TNZ
OR
BRES
BTJF
ADD
SRL
JRT
WFI
RIM be subdivided into 13 main groups as illustrated in the following table:
RSP
BCP
XOR
SUB
SRA
JRF
HALT
SCF
CPL
SBC
RLC
JP
IRET
RCF
NEG
MUL
RRC SWAP
CALL CALLR
SLA
NOP RET
Using a pre-byte
The instructions are described with one to four bytes.
In order to extend the number of available opcodes for an 8-bit CPU (256 opcodes), three different prebyte opcodes are defined. These prebytes modify the meaning of the instruction they precede.
The whole instruction becomes:
PC-2 End of previous instruction
PC-1 Prebyte
PC Opcode
PC+1 Additional word (0 to 2) according to the number of bytes required to compute the effective address
These prebytes enable instruction in Y as well as indirect addressing modes to be implemented.
They precede the opcode of the instruction in X or the instruction using direct addressing mode. The prebytes are:
PDY 90 Replace an X based instruction using immediate, direct, indexed, or inherent addressing mode by a Y one.
PIX 92 Replace an instruction using direct, direct bit, or direct relative addressing mode to an instruction using the corresponding indirect addressing mode.
It also changes an instruction using X indexed addressing mode to an instruction using indirect X indexed addressing mode.
PIY 91 Replace an instruction using X indirect indexed addressing mode by a Y one.
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INSTRUCTION GROUPS (Cont’d)
Mnemo
ADC
ADD
AND
BCP
BRES
BSET
BTJF
Description
Add with Carry
Addition
Logical And
Bit compare A, Memory
Bit Reset
Bit Set
Jump if bit is false (0)
BTJT
CALL
Jump if bit is true (1)
Call subroutine
CALLR Call subroutine relative
CLR Clear
CP
CPL
DEC
HALT
Arithmetic Compare
One Complement
Decrement
Halt
Function/Example
A = A + M + C
A = A + M
A = A . M tst (A . M) bres Byte, #3 bset Byte, #3 btjf Byte, #3, Jmp1 btjt Byte, #3, Jmp1 tst(Reg - M)
A = FFH-A dec Y
JRH
JRNH
JRM
JRNM
JRMI
JRPL
JREQ
JRNE
IRET
INC
JP
JRA
JRT
JRF
JRIH
JRIL
Interrupt routine return
Increment
Absolute Jump
Jump relative always
Jump relative
Never jump
Jump if ext. interrupt = 1
Jump if ext. interrupt = 0
Jump if H = 1
Jump if H = 0
Jump if I = 1
Jump if I = 0
JRC
JRNC
Jump if C = 1
Jump if C = 0
JRULT Jump if C = 1
JRUGE Jump if C = 0
JRUGT Jump if (C + Z = 0)
Pop CC, A, X, PC inc X jp [TBL.w] jrf *
H = 1 ?
H = 0 ?
I = 1 ?
I = 0 ?
Jump if N = 1 (minus)
Jump if N = 0 (plus)
N = 1 ?
N = 0 ?
Jump if Z = 1 (equal) Z = 1 ?
Jump if Z = 0 (not equal) Z = 0 ?
C = 1 ?
C = 0 ?
Unsigned <
Jmp if unsigned >=
Unsigned >
A
M
M
M
M
A
A
A
Dst reg, M reg reg, M reg, M reg, M
M
M
M
M
Src
M
H
H
H
I
N
N
N
N
N
Z
Z
Z
Z
Z
C
C
C
H
0
I N
N
0
N
N
N
1
Z
Z
Z
C
1
Z
Z
C
C
C
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RSP
SBC
SCF
SIM
SLA
SLL
SRL
SRA
PUSH
RCF
RET
RIM
RLC
RRC
SUB
SWAP
TNZ
TRAP
WFI
XOR
INSTRUCTION GROUPS (Cont’d)
Mnemo Description
JRULE Jump if (C + Z = 1)
LD Load
MUL
NEG
NOP
OR
POP
Multiply
Negate (2's compl)
No Operation
OR operation
Pop from the Stack
Function/Example
Unsigned <= dst <= src
X,A = X * A neg $10
A = A + M pop reg pop CC push Y
C = 0
Push onto the Stack
Reset carry flag
Subroutine Return
Enable Interrupts
Rotate left true C
Rotate right true C
Reset Stack Pointer
Subtract with Carry
Set carry flag
Disable Interrupts
Shift left Arithmetic
Shift left Logic
Shift right Logic
Shift right Arithmetic
Subtraction
SWAP nibbles
Test for Neg & Zero
S/W trap
Wait for Interrupt
Exclusive OR
A reg
CC
M reg, M
A, X, Y reg, M
A
Dst
I = 0
C <= Dst <= C
C => Dst => C
S = Max allowed
A = A - M - C
C = 1
I = 1
C <= Dst <= 0 reg, M reg, M
A
C <= Dst <= 0
0 => Dst => C
Dst7 => Dst => C reg, M reg, M reg, M reg, M
A = A - M A
Dst[7..4] <=> Dst[3..0] reg, M tnz lbl1
S/W interrupt
A = A XOR M
Src
M, reg
X, Y, A
M
M
M reg, CC
M
M
M
H I N Z C
0
N
N
Z
Z
0
C
N Z
H I N Z C
0
0
N
N
Z
Z
C
C
1
0
1
N Z C
1
N
N
0
N
N
N
N
Z
Z
Z
Z
Z
Z
Z
C
C
C
C
C
N Z
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16 ELECTRICAL CHARACTERISTICS
16.1 PARAMETER CONDITIONS
Unless otherwise specified, all voltages are referred to V
SS
.
16.1.1 Minimum and Maximum values
Unless otherwise specified the minimum and maximum values are guaranteed in the worst conditions of ambient temperature, supply voltage and frequencies by tests in production on 100% of the devices with an ambient temperature at T
A and T
A range).
=T
A
=25°C max (given by the selected temperature
Data based on characterization results, design simulation and/or technology characteristics are indicated in the table footnotes and are not tested in production. Based on characterization, the minimum and maximum values refer to sample tests and represent the mean value plus or minus three times the standard deviation (mean±3
Σ
).
16.1.2 Typical values
Unless otherwise specified, typical data are based on T
A
=25°C, V
DD
=5V (for the 4.5V
≤
V voltage range) and V
DD
DD
≤
5.5V
=3.3V (for the 3V
≤
V
DD
≤
4V voltage range). They are given only as design guidelines and are not tested.
16.1.3 Typical curves
Unless otherwise specified, all typical curves are given only as design guidelines and are not tested.
16.1.4 Loading capacitor
The loading conditions used for pin parameter measurement are shown in Figure 53 .
Figure 53. Pin loading conditions
16.1.5 Pin input voltage
The input voltage measurement on a pin of the device is described in Figure 54 .
Figure 54. Pin input voltage
V
IN
ST7 PIN
ST7 PIN
C
L
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16.2 ABSOLUTE MAXIMUM RATINGS
Stresses above those listed as “absolute maximum ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device under these condi-
16.2.1 Voltage Characteristics tions is not implied. Exposure to maximum rating conditions for extended periods may affect device reliability.
Symbol Ratings
V
DD
- V
SS
Supply voltage
V
DDA
- V
SSA
Analog Reference Voltage
Input voltage on true open drain pin
V
IN
1) & 2)
Input voltage on any other pin
|
∆
V
DDx
| and |
∆
V
SSx
| Variations between different digital power pins
V
DDX
- V
DDA
|V
SSA
- V
SSx
|
V
ESD(HBM)
V
ESD(MM)
Variations between digital and analog power pins
Electro-static discharge voltage (Human Body Model)
Electro-static discharge voltage (Machine Model)
16.2.2 Current Characteristics
Maximum value
6.5
6.5
V
SS
-0.3 to 6.5
V
SS
-0.3 to V
DD
+0.3
50
50
Unit
V mV see Section 16.7.2 "Absolute Electrical Sensitivity" on page 124
I
Symbol
I
VDD
I
VSS
I
IO
INJ(PIN)
2) & 4)
Ratings
Total current into V
DD
power lines (source)
3)
Total current out of V
SS
ground lines (sink)
3)
Output current sunk by any standard I/O and control pin
Output current sunk by any high sink I/O pin
Output current source by any I/Os and control pin
Injected current on ISPSEL pin
Injected current on RESET pin
Injected current on OSC1 and OSC2 pins
Injected current on any other pin
5) & 6)
Total injected current (sum of all I/O and control pins)
5)
Maximum value
150
150
25
50
- 25
± 5
± 5
± 5
± 5
± 20
Unit mA
Σ
I
INJ(PIN)
2)
Notes:
1. Directly connecting the RESET and I/O pins to V is generated or an unexpected change of the I/O configuration occurs (for example, due to a corrupted program counter).
To guarantee safe operation, this connection has to be done through a pull-up or pull-down resistor (typical: 4.7k
Ω
for
RESET, 10k
I
INJ(PIN)
Ω
DD
or V
SS could damage the device if an unintentional internal reset
for I/Os). Unused I/O pins must be tied in the same way to V
2. When the current limitation is not possible, the V
DD
according to their reset configuration.
IN
absolute maximum rating must be respected, otherwise refer to
specification. A positive injection is induced by V
IN
3. All power (V
DD
) and ground (V
SS
>V
DD
or V
SS
while a negative injection is induced by V
) lines must always be connected to the external supply.
IN
<V
SS
.
4. Negative injection disturbs the analog performance of the device. In particular, it induces leakage currents throughout the device including the analog inputs. To avoid undesirable effects on the analog functions, care must be taken:
- Analog input pins must have a negative injection less than 0.8 mA (assuming that the impedance of the analog voltage is lower than the specified limits)
- Pure digital pins must have a negative injection less than 1.6mA. In addition, it is recommended to inject the current as far as possible from the analog input pins.
5. When several inputs are submitted to a current injection, the maximum and negative injected currents (instantaneous values). These results are based on characterisation with mum current injection on four I/O port pins of the device.
Σ
I
INJ(PIN)
is the absolute sum of the positive
Σ
I
INJ(PIN)
maxi-
6. True open drain I/O port pins do not accept positive injection.
108/153
ST72334J/N, ST72314J/N, ST72124J
ABSOLUTE MAXIMUM RATINGS (Cont’d)
16.2.3 Thermal Characteristics
Symbol
T
STG
T
J
Ratings
Storage temperature range
Value
-65 to +150
Unit
°C
Maximum junction temperature (see
Section 18 "DEVICE CONFIGURATION AND ORDER-
)
109/153
ST72334J/N, ST72314J/N, ST72124J
16.3 OPERATING CONDITIONS
16.3.1 General Operating Conditions
Symbol
V
DD f
OSC
T
A
Supply voltage
Parameter
External clock frequency
Ambient temperature range
Conditions see Figure 55 and Figure 56
V
DD
V
DD
≥
3.5V for ROM devices
≥
4.5V for FLASH devices
V
DD
≥
3.2V
1 Suffix Version
6 Suffix Version
7 Suffix Version
3 Suffix Version
Min
3.2
0
1)
0
1)
0
-40
-40
-40
Max
5.5
16
8
70
85
105
125
Unit
V
MHz
°C
Figure 55. f
OSC
Maximum Operating Frequency Versus V
DD
Supply Voltage for ROM devices
2) f
OSC
[MHz]
FUNCTIONALITY
NOT GUARANTEED
IN THIS AREA AT T
A
> 85°C
FUNCTIONALITY
GUARANTEED
IN THIS AREA
16
FUNCTIONALITY
NOT GUARANTEED
IN THIS AREA
12
8
FUNCTIONALITY
NOT GUARANTEED
IN THIS AREA
WITH RESONATOR
1)
4
1
0
2.5
3.2
3.5
3.85
4 4.5
5 5.5
SUPPLY VOLTAGE [V]
Figure 56. f
OSC
Maximum Operating Frequency Versus V
DD
Supply Voltage for FLASH devices
2) f
OSC
[MHz]
FUNCTIONALITY
NOT GUARANTEED
IN THIS AREA AT T
A
> 85°C FUNCTIONALITY
GUARANTEED
IN THIS AREA
3)
16
FUNCTIONALITY
NOT GUARANTEED
IN THIS AREA
12
8
FUNCTIONALITY
NOT GUARANTEED
IN THIS AREA
WITH RESONATOR
1)
4
1
0
2.5
3.2
3.5
3.85
4 4.5
5 5.5
SUPPLY VOLTAGE [V]
Notes:
1. Guaranteed by construction. A/D operation and resonator oscillator start-up are not guaranteed below 1MHz.
2. Operating conditions with T
A
=-40 to +125°C.
3. FLASH programming tested in production at maximum T
A
V
DD
=3.2V, f
CPU
=4MHz.
with two different conditions: V
DD
=5.5V, f
CPU
=6MHz and
110/153
ST72334J/N, ST72314J/N, ST72124J
OPERATING CONDITIONS (Cont’d)
16.3.2 Operating Conditions with Low Voltage Detector (LVD)
Subject to general operating conditions for V
DD
, f
OSC
, and T
A
.
Symbol
V
IT+
V
IT-
V hys
Vt
POR t g(VDD)
Parameter
Reset release threshold (V
DD
rise)
Reset generation threshold (V
DD
fall)
Conditions
High Threshold
Med. Threshold
Low Threshold
High Threshold
Med. Threshold
Low Threshold
4)
V
IT+
-V
IT-
LVD voltage threshold hysteresis
V
DD
rise time rate
3)
Filtered glitch delay on V
DD
2)
Not detected by the LVD
Min
4.10
2)
3.75
2)
3.25
2)
3.85
2)
3.50
2)
3.00
200
0.2
Figure 57. High LVD Threshold Versus V
DD and f
OSC
for FLASH devices
3)
DEVICE UNDER
RESET
IN THIS AREA
FUNCTIONALITY AND RESET NOT GUARANTEED IN THIS AREA
FOR TEMPERATURES HIGHER THAN 85°C f
OSC
[MHz]
16
12
8
0
00000000000000000000000000000000000000000000000000000000000000
00000000000000000000000000000000000000000000000000000000000000
00000000000000000000000000000000000000000000000000000000000000
00000000000000000000000000000000000000000000000000000000000000
00000000000000000000000000000000000000000000000000000000000000
V
IT-
≥
3.85
2.5
3 3.5
4 4.5
5 5.5
Typ
1)
4.30
3.90
3.35
4.05
3.65
3.10
250
Max
4.50
4.05
3.55
4.30
3.95
3.35
300
50
40
Unit
V mV
V/ms ns
FUNCTIONALITY
NOT GUARANTEED
IN THIS AREA
FUNCTIONAL AREA
SUPPLY VOLTAGE [V]
Figure 58. Medium LVD Threshold Versus V
DD and f
OSC
for FLASH devices
3)
DEVICE UNDER
RESET
IN THIS AREA f
OSC
[MHz]
FUNCTIONALITY AND RESET NOT GUARANTEED IN THIS AREA
FOR TEMPERATURES HIGHER THAN 85°C
16
12
8
0000000000000000000000000000000000000000000000
0000000000000000000000000000000000000000000000
0000000000000000000000000000000000000000000000
0000000000000000000000000000000000000000000000
0
2.5
3 V
IT-
≥
3.5V
4 4.5
5 5.5
FUNCTIONALITY
NOT GUARANTEED
IN THIS AREA
FUNCTIONAL AREA
SUPPLY VOLTAGE [V]
Figure 59. Low LVD Threshold Versus V
DD and f
OSC
for FLASH devices
2)4) f
OSC
[MHz]
FUNCTIONALITY NOT GUARANTEED IN THIS AREA
FOR TEMPERATURES HIGHER THAN 85°C
FUNCTIONALITY
NOT GUARANTEED
IN THIS AREA
DEVICE UNDER
RESET
IN THIS AREA
16
12
8
0
000000000000000000000000
000000000000000000000000
000000000000000000000000
2.5
V
IT-
≥
3V 3.2
SEE NOTE 4
3.5
4 4.5
5 5.5
FUNCTIONAL AREA
SUPPLY VOLTAGE [V]
Notes:
1. LVD typical data are based on T
A
=25°C. They are given only as design guidelines and are not tested.
2. Data based on characterization results, not tested in production.
3. The V
DD
rise time rate condition is needed to insure a correct device power-on and LVD reset. Not tested in production.
4.If the low LVD threshold is selected, when V
DD
falls below 3.2V, (V
DD
minimum operating voltage), the device is guaranteed to continue functioning until it goes into reset state. The specified V
DD
min. value is necessary in the device power on phase, but during a power down phase or voltage drop the device will function below this min. level.
111/153
ST72334J/N, ST72314J/N, ST72124J
FUNCTIONAL OPERATING CONDITIONS (Cont’d)
Figure 60. High LVD Threshold Versus V
DD and f
OSC
for ROM devices
2)
DEVICE UNDER
RESET
IN THIS AREA f
OSC
[MHz]
16
8
0
0000000000000000000000000000000000000000000000000000000000000000
0000000000000000000000000000000000000000000000000000000000000000
0000000000000000000000000000000000000000000000000000000000000000
0000000000000000000000000000000000000000000000000000000000000000
0000000000000000000000000000000000000000000000000000000000000000
V
IT-
≥
3.85
2.5
3 3.5
4 4.5
5
Figure 61. Medium LVD Threshold Versus V
DD and f
OSC
for ROM devices
2)
FUNCTIONALITY
NOT GUARANTEED
IN THIS AREA
FUNCTIONAL AREA
5.5
SUPPLY VOLTAGE [V]
DEVICE UNDER
RESET
IN THIS AREA f
OSC
[MHz]
16
8
0000000000000000000000000000000000000000000000
0000000000000000000000000000000000000000000000
0000000000000000000000000000000000000000000000
0000000000000000000000000000000000000000000000
0000000000000000000000000000000000000000000000
0
2.5
3 V
IT-
≥
3.5V
4 4.5
5
Figure 62. Low LVD Threshold Versus V
DD and f
OSC
for ROM devices
2)3)
FUNCTIONALITY
NOT GUARANTEED
IN THIS AREA
FUNCTIONAL AREA
5.5
SUPPLY VOLTAGE [V]
DEVICE UNDER
RESET
IN THIS AREA f
OSC
[MHz]
16
8
000000000000000000000000
000000000000000000000000
000000000000000000000000
0
2.5
V
IT-
≥
3.00V
3.5
4 4.5
5
FUNCTIONALITY
NOT GUARANTEED
IN THIS AREA
FUNCTIONAL AREA
5.5
SUPPLY VOLTAGE [V]
Notes:
1. LVD typical data are based on T
A
=25°C. They are given only as design guidelines and are not tested.
2. The minimum V
DD
rise time rate is needed to insure a correct device power-on and LVD reset. Not tested in production.
3. If the low LVD threshold is selected, when V
DD
falls below 3.2V, (V
DD
minimum operating voltage), the device is guaranteed to continue functioning until it goes into reset state. The specified V
DD
min. value is necessary in the device power on phase, but during a power down phase or voltage drop the device will function below this min. level.
112/153
ST72334J/N, ST72314J/N, ST72124J
16.4 SUPPLY CURRENT CHARACTERISTICS
The following current consumption specified for the ST7 functional operating modes over temperature range does not take into account the clock source current consumption. To get the total de-
Symbol
∆
I
DD(
∆
Ta)
Parameter
Supply current variation vs. temperature
16.4.1 RUN and SLOW Modes
Symbol Parameter
I
DD
Supply current in RUN mode
3)
(see Figure 63 )
Supply current in SLOW mode
4)
(see Figure 64 )
Supply current in RUN mode
3)
(see Figure 63 )
Supply current in SLOW mode
4)
(see Figure 64 ) vice consumption, the two current values must be added (except for HALT mode for which the clock is stopped).
Conditions
Constant V
DD
and f
CPU
Conditions f
OSC f
OSC
=2MHz, f
CPU
=4MHz, f
CPU f
OSC
=8MHz, f
CPU
=1MHz
=2MHz
=4MHz f
OSC
=16MHz, f
CPU
=8MHz f
OSC f
OSC
=2MHz, f
CPU
=4MHz, f
CPU f
OSC
=8MHz, f
CPU
=62.5kHz
=125kHz
=250kHz f
OSC
=16MHz, f
CPU
=500kHz f
OSC f
OSC
=2MHz, f
CPU
=4MHz, f
CPU f
OSC
=8MHz, f
CPU
=1MHz
=2MHz
=4MHz f
OSC
=16MHz, f
CPU
=8MHz f
OSC f
OSC
=2MHz, f
CPU
=4MHz, f
CPU f
OSC
=8MHz, f
CPU
=62.5kHz
=125kHz
=250kHz f
OSC
=16MHz, f
CPU
=500kHz
Typ
1)
0.3
0.8
1.6
3.5
0.1
0.2
0.3
0.5
1.2
2.1
3.9
7.4
0.4
0.5
0.7
1.0
Max
10
Max
2)
1
1.5
3
7
0.3
0.5
0.6
1.0
1.8
3.5
7.0
14.0
0.9
1.1
1.4
2.0
Unit
%
Unit mA
Figure 63. Typical I
DD
in RUN vs. f
CPU
IDD [mA]
8
Figure 64. Typical I
DD
in SLOW vs. f
CPU
IDD [mA]
1.2
500kHz
250kHz
125kHz
62.5kHz
7
8MHz
4MHz
2MHz
1MHz
1
6
0.8
5
4
0.6
3
2
1
0.4
0.2
0 0
3.2
3.5
4
VDD [V]
4.5
5 5.5
3.2
3.5
4 4.5
VDD [V]
5 5.5
Notes:
1. Typical data are based on T
A
=25°C, V
DD
=5V (4.5V
≤
V
DD
≤
5.5V range) and V
DD
=3.4V (3.2V
≤
V
DD
≤
3.6V range).
2. Data based on characterization results, tested in production at V
DD
max. and f
CPU
max.
3. CPU running with memory access, all I/O pins in input mode with a static value at V
DD
or V
SS
(no load), all peripherals in reset state; clock input (OSC1) driven by external square wave, CSS and LVD disabled.
4. SLOW mode selected with f
CPU
V
SS
based on f
OSC
divided by 32. All I/O pins in input mode with a static value at V
DD
or
(no load), all peripherals in reset state; clock input (OSC1) driven by external square wave, CSS and LVD disabled.
113/153
ST72334J/N, ST72314J/N, ST72124J
SUPPLY CURRENT CHARACTERISTICS (Cont’d)
16.4.2 WAIT and SLOW WAIT Modes
Symbol Parameter
I
DD
Supply current in WAIT mode
3)
(see Figure 65 )
Supply current in SLOW WAIT mode
4)
(see Figure 66 )
Supply current in WAIT mode
3)
(see Figure 65 )
Supply current in SLOW WAIT mode
4)
(see Figure 66 )
Conditions f
OSC f
OSC
=2MHz, f
CPU
=4MHz, f
CPU f
OSC
=8MHz, f
CPU
=1MHz
=2MHz
=4MHz f
OSC
=16MHz, f
CPU
=8MHz f
OSC f
OSC
=2MHz, f
CPU
=4MHz, f
CPU f
OSC
=8MHz, f
CPU
=62.5kHz
=125kHz
=250kHz f
OSC
=16MHz, f
CPU
=500kHz f
OSC f
OSC
=2MHz, f
CPU
=4MHz, f
CPU f
OSC
=8MHz, f
CPU
=1MHz
=2MHz
=4MHz f
OSC
=16MHz, f
CPU
=8MHz f
OSC f
OSC
=2MHz, f
CPU
=4MHz, f
CPU f
OSC
=8MHz, f
CPU
=62.5kHz
=125kHz
=250kHz f
OSC
=16MHz, f
CPU
=500kHz
Figure 65. Typical I
DD
in WAIT vs. f
CPU
Typ
1)
45
150
300
500
6
40
80
120
0.35
0.7
1.3
2.5
0.05
0.1
0.2
0.5
Max
2)
100
300
600
1000
20
100
160
250
0.6
1.2
2.1
4.0
0.1
0.2
0.4
1.0
Unit mA
µA
Figure 66. Typical I
DD
in SLOW-WAIT vs. f
CPU
IDD [mA]
3
8MHz
4MHz
2MHz
1MHz
2.5
2
1.5
1
0.5
0
3.2
3.5
4
VDD [V]
4.5
5 5.5
IDD [mA]
0.35
0.3
0.25
0.2
0.15
0.1
0.05
0
3.2
3.5
500kHz
250kHz
4 4.5
VDD [V]
125kHz
62.5kHz
5 5.5
Notes:
1. Typical data are based on T
A
=25°C, V
DD
=5V (4.5V
≤
V
DD
≤
5.5V range) and V
DD
=3.4V (3.2V
≤
V
DD
≤
3.6V range).
2. Data based on characterization results, tested in production at V
DD
max. and f
CPU
max.
3. All I/O pins in input mode with a static value at V
DD
or V driven by external square wave, CSS and LVD disabled.
SS
(no load), all peripherals in reset state; clock input (OSC1)
4. SLOW-WAIT mode selected with f
CPU
V
DD
or V disabled.
SS
based on f
OSC
divided by 32. All I/O pins in input mode with a static value at
(no load), all peripherals in reset state; clock input (OSC1) driven by external square wave, CSS and LVD
114/153
ST72334J/N, ST72314J/N, ST72124J
SUPPLY CURRENT CHARACTERISTICS (Cont’d)
16.4.3 HALT and ACTIVE-HALT Modes
Symbol
I
DD
Parameter
Supply current in HALT mode
2)
V
DD
=5.5V
V
DD
=3.6V
Conditions
-40°C
≤
T
A
≤
+85°C
-40°C
≤
T
A
-40°C
≤
T
A
≤
+125°C
≤
+85°C
-40°C
≤
T
A
≤
+125°C
Supply current in ACTIVE-HALT mode
3)
Typ
1)
<2
50
Max
10
150
6
100
150
Unit
µ
A
16.4.4 Supply and Clock Managers
The previous current consumption specified for the ST7 functional operating modes over temperature range does not take into account the clock
Symbol
I
DD(CK)
I
DD(LVD)
Parameter
Supply current of internal RC oscillator
Supply current of external RC oscillator
5)
Supply current of resonator oscillator
5) & 6)
LP: Low power oscillator
MP: Medium power oscillator
MS: Medium speed oscillator
HS: High speed oscillator
Clock security system supply current
LVD supply current source current consumption. To get the total device consumption, the two current values must be added (except for HALT mode).
Conditions
HALT mode
Typ
1)
500
525
200
300
450
700
150
100
Max
4)
750
750
400
550
750
1000
350
150
Unit
µ
A
16.4.5 On-Chip Peripherals
Symbol Parameter
I
I
I
DD(TIM)
DD(SPI)
DD(ADC)
16-bit Timer supply current
SPI supply current
8)
7)
ADC supply current when converting
9) f f f
CPU
CPU
ADC
Conditions
=8MHz
=8MHz
=4MHz
V
DD
V
DD
=
3.4V
=
5.0V
V
DD
=
3.4V
V
DD
V
DD
=
5.0V
=
3.4V
V
DD
=
5.0V
Typ
50
150
250
350
800
1100
Unit
µ
A
Notes:
1. Typical data are based on T
A
=25°C.
2. All I/O pins in input mode with a static value at V
DD
or V
SS terization results, tested in production at V
DD
max. and f
CPU
(no load), CSS and LVD disabled. Data based on charac-
max.
3. Data based on design simulation and/or technology characteristics, not tested in production. All I/O pins in input mode with a static value at V
DD
or V
SS
(no load); clock input (OSC1) driven by external square wave, LVD disabled.
4. Data based on characterization results, not tested in production.
5. Data based on characterization results done with the external components specified in Section 16.5.3
and Section
16.5.4
, not tested in production.
6. As the oscillator is based on a current source, the consumption does not depend on the voltage.
7. Data based on a differential I
DD
measurement between reset configuration (timer counter running at f
CPU
/4) and timer counter stopped (selecting external clock capability). Data valid for one timer.
8. Data based on a differential I
DD tion (data sent equal to 55h).
measurement between reset configuration and a permanent SPI master communica-
9. Data based on a differential I
DD
measurement between reset configuration and continuous A/D conversions.
115/153
ST72334J/N, ST72314J/N, ST72124J
16.5 CLOCK AND TIMING CHARACTERISTICS
Subject to general operating conditions for V
DD
, f
OSC
, and T
A
.
16.5.1 General Timings
Symbol Parameter Conditions t c(INST)
Instruction cycle time f
CPU
=8MHz t v(IT) t
Interrupt reaction time v(IT)
=
∆ t c(INST)
+ 10
2) f
CPU
=8MHz
16.5.2 External Clock Source
Symbol
V
OSC1H
V
OSC1L t w(OSC1H) t w(OSC1L) t r(OSC1) t f(OSC1)
I
L
Parameter
OSC1 input pin high level voltage
OSC1 input pin low level voltage
OSC1 high or low time
3)
OSC1 rise or fall time
3)
OSCx Input leakage current
Conditions see Figure 67
V
SS
≤
V
IN
≤
V
DD
Figure 67. Typical Application with an External Clock Source
V
OSC1H
90%
10%
V
OSC1L t r(OSC1) t f(OSC1) t w(OSC1H)
Min
2
250
10
1.25
Typ
1)
3
375
Max
12
1500
22
2.75
Min
0.7xV
DD
V
SS
15
Typ Max
V
DD
0.3xV
DD
Unit
V ns
15
±1
µ
A t w(OSC1L)
Unit t
CPU ns t
CPU
µ s
EXTERNAL
CLOCK SOURCE
OSC2
OSC1
Not connected internally f
OSC
I
L
ST72XXX
Notes:
1. Data based on typical application software.
2. Time measured between interrupt event and interrupt vector fetch.
∆ t c(INST) the current instruction execution.
is the number of t
CPU
cycles needed to finish
3. Data based on design simulation and/or technology characteristics, not tested in production.
116/153
ST72334J/N, ST72314J/N, ST72124J
CLOCK AND TIMING CHARACTERISTICS (Cont’d)
16.5.3 Crystal and Ceramic Resonator Oscillators
The ST7 internal clock can be supplied with four different Crystal/Ceramic resonator oscillators. All the information given in this paragraph are based on characterization results with specified typical external components. In the application, the resonator and the load capacitors have to be placed as close as possible to the oscillator pins in order to minimize output distortion and start-up stabilization time. Refer to the crystal/ceramic resonator manufacturer for more details (frequency, package, accuracy...).
Symbol f
OSC
R
F
C
L1
C
L2 i
2
Parameter
Oscillator Frequency
3)
Conditions
LP: Low power oscillator
MP: Medium power oscillator
MS: Medium speed oscillator
HS: High speed oscillator
Feedback resistor
Recommended load capacitance versus equivalent serial resistance of the crystal or ceramic resonator (R
S
)
OSC2 driving current
R
S
R
S
=200
Ω
=200
Ω
R
R
S
S
=200
Ω
=100
Ω
V
DD
=5V
V
IN
=V
SS
LP oscillator
MP oscillator
MS oscillator
HS oscillator
LP oscillator
MP oscillator
MS oscillator
HS oscillator
Min
20
38
32
18
15
1
>2
>4
>8
40
110
180
400
Max
40
56
46
26
21
2
4
8
16
100
190
360
700
Unit
MHz k
Ω pF
µ
A
16.5.3.1 Typical Crystal Resonators
Option
Byte
Config.
LP
MP
MS
HS
Reference
S-200-30-30/50
SS3-400-30-30/30
SS3-800-30-30/30
SS3-1600-30-30/30
Freq.
Characteristic
1)
2MHz
∆ f
OSC
=[±30ppm
25°C
,±30ppm ∆
Ta
4MHz
∆ f
OSC
=[±30ppm
25°C
,±30ppm ∆
Ta
8MHz
∆ f
OSC
=[±30ppm
25°C
,±30ppm ∆
Ta
16MHz
∆ f
OSC
=[±30ppm
25°C
,±30ppm ∆
Ta
]
]
, Typ. R
S
=200
Ω
]
, Typ. R
S
=60
Ω
, Typ. R
]
, Typ. R
S
S
=25
=15
Ω
Ω
Figure 68. Application with a Crystal Resonator
C
L1
[pF]
C
L2
[pF] t
SU(osc)
[ms]
2)
33 34 10~15
33 34 7~10
33 34 2.5~3
33 34 1~1.5
i
2 f
OSC
C
L1 OSC1
RESONATOR R
F
C
L2
OSC2
ST72XXX
Notes:
1. Resonator characteristics given by the crystal manufacturer.
2. t
SU(OSC) quick V
DD
is the typical oscillator start-up time measured between V
ramp-up from 0 to 5V (<50
µ s).
DD
=2.8V and the fetch of the first instruction (with a
3. The oscillator selection can be optimized in terms of supply current using an high quality resonator with small R
S
Refer to crystal manufacturer for more details.
value.
117/153
ST72334J/N, ST72314J/N, ST72124J
CLOCK AND TIMING CHARACTERISTICS (Cont’d)
16.5.3.2 Typical Ceramic Resonators
Symbol Parameter t
SU(osc)
Ceramic resonator start-up time
LP
Conditions
2MHz
MP
MS
4MHz
8MHz
HS 16MHz
Typ
4.2
2.1
1.1
0.7
Unit ms
Note: t
SU(OSC)
is the typical oscillator start-up time measured between V quick V
DD
ramp-up from 0 to 5V (<50
µ s).
DD
=2.8V and the fetch of the first instruction (with a
Figure 69. Application with Ceramic Resonator
WHEN RESONATOR WITH
INTEGRATED CAPACITORS i
2 f
OSC
C
L1 OSC1
RESONATOR
R
F(EXT)
R
F
C
L2
OSC2
ST72XXX
R
D
Notes:
1. Resonator characteristics given by the ceramic resonator manufacturer.
2. t
SU(OSC) quick V
DD
is the typical oscillator start-up time measured between V
ramp-up from 0 to 5V (<50
µ s).
DD
=2.8V and the fetch of the first instruction (with a
3. The oscillator selection can be optimized in terms of supply current using an high quality resonator with small R
S
Refer to Table 22 and Table 23 and to the ceramic resonator manufacturer’s documentation for more details.
value.
118/153
ST72334J/N, ST72314J/N, ST72124J
CLOCK AND TIMING CHARACTERISTICS (Cont’d)
Table 22. Typical Ceramic Resonators
Option Byte
Config.
f
OSC
(MHz)
Resonator Part Number
1)
LP
MP
MS
HS
1
2
2
4
4
8
8
10
12
16
2)
CSB1000JA
CSBF1000JA
CSTS0200MGA06
CSTCC2.00MGA0H6
CSTS0200MGA06
CSTCC2.00MGA0H6
CSTS0400MGA06
CSTCC4.00MGA0H6
CSTS0400MGA06
CSTCC4.00MGA0H6
CSTS0800MGA06
CSTCC8.00MGA0H6
CSTS0800MGA06
CSTCC8.00MGA0H6
CST10.0MTWA
CSTCC10.0MGA
CST12.0MTWA
CSTCS12.0MTA
CSA16.00MXZA040
CST16.00MXWA0C3
CSACV16.00MXA040Q
CSTCV16.00MXA0H3Q
C
L1
[pF]
3
100
(47)
30
(15)
30
(30)
15
(15)
15
(15)
C
L2
[pF]
3
100
(47)
30
(15)
30
(30)
15
(15)
15
(15)
R
FEXT k
Ω
Open
10
Table 23. Resonator Frequency Correlation Factor
Option
Byte
Config.
LP
MP
Resonator
1)
CSB1000JA
CSTS0200MGA06
CSTCC2.00MGA0H6
CSTS0200MGA06
CSTCC2.00MGA0H6
CSTS0400MGA06
CSTCC4.00MGA0H6
Correlation
%
Reference IC
+0.03
4069UBE
-0.20
-0.16
-0.21
-0.19
0.02
-0.05
74HCU04
Option
Byte
Config.
MS
HS
Resonator
1)
CSTS0400MGA06
CSTCC4.00MGA0H6
CSTS0800MGA06
CSTCC4.00MGA0H6
CSTS0800MGA06
CSTCC8.00MGA0H6
CSTS10.0MTWA
CSTCC10.0MGA
CST12.0MTWA
CSTCS12.0MTA
CSA16.00MXZA040
+0.42
+0.10
CSACV16.00MXA040Q +0.08
Correlation
%
-0.03
-0.05
+0.03
+0.02
+0.02
+0.01
+0.38
+0.61
+0.38
R
D
[k
Ω
]
3.3
0
Reference IC
74HCU04
4069UBE
74HCU04
Notes:
1. Murata Ceralock
2. V
DD
4.5 to 5.5V
3. Values in parentheses refer to the capacitors integrated in the resonator
119/153
ST72334J/N, ST72314J/N, ST72124J
CLOCK CHARACTERISTICS (Cont’d)
16.5.4 RC Oscillators
The ST7 internal clock can be supplied with an RC oscillator. This oscillator can be used with internal
Symbol f
OSC t
SU(OSC)
R
EX
C
EX or external components (selectable by option byte).
Typ Unit Parameter
Internal RC oscillator frequency
1)
External RC oscillator frequency
2)
Internal RC Oscillator Start-up Time
3) see
Conditions
Figure 71
External RC Oscillator Start-up Time
3)
Oscillator external resistor
4)
Oscillator external capacitor
R
EX
=47K
Ω,
C
EX
=”0”pF
R
EX
=47K
Ω,
C
EX
=100pF
R
EX
=10K
Ω,
C
EX
=6.8pF
R
EX
=10K
Ω,
C
EX
=470pF see Figure 72
Min
3.60
1
10
0
5)
2.0
1.0
6.5
0.7
3.0
Max
5.10
14
47
470
MHz ms
K
Ω pF
Figure 70. Typical Application with RC oscillator
ST72XXX
INTERNAL RC
V
DD
Current copy
EXTERNAL RC
R
EX
OSC1
C
EX
OSC2
V
REF
+
f
OSC
Voltage generator
C
EX discharge
Figure 71. Typical Internal RC Oscillator fosc [MHz]
4.3
4.2
4.1
-40°C
+25°C
+85°C
+125°C
Figure 72. Typical External RC Oscillator fosc [MHz]
20
15
10
Rex=10KOhm
Rex=15KOhm
Rex=22KOhm
Rex=33KOhm
Rex=39KOhm
Rex=47KOhm
4
3.9
5
3.8
3.2
5.5
0
0 6.8
22 47 100 270 470
VDD [V]
Cex [pF]
Notes:
1. Data based on characterization results.
2. Guaranteed frequency range with the specified C
EX
Data based on design simulation.
and R
EX
ranges taking into account the device process variation.
3. Data based on characterization results done with V
DD
nominal at 5V, not tested in production.
4. R
EX
must have a positive temperature coefficient (ppm/°C), carbon resistors should therefore not be used.
5. Important: when no external C
EX
is applied, the capacitance to be considered is the global parasitic capacitance which is subject to high variation (package, application...). In this case, the RC oscillator frequency tuning has to be done by trying out several resistor values.
120/153
ST72334J/N, ST72314J/N, ST72124J
CLOCK CHARACTERISTICS (Cont’d)
16.5.5 Clock Security System (CSS)
Symbol f
SFOSC f
GFOSC
Parameter
Safe Oscillator Frequency
1)
Glitch Filtered Frequency
2)
Conditions
T
A
T
A
=
25°C, V
DD
=
25°C, V
DD
=
5.0V
=
3.4V
Figure 73. Typical Safe Oscillator Frequencies
Min
250
190
Typ
340
260
30
Max
550
450 fosc [kHz]
400
350
300
-40°C
+25°C
+85°C
+125°C
250
200
3.2
5.5
VDD [V]
Note:
1. Data based on characterization results, tested in production between 90KHz and 600KHz.
2. Filtered glitch on the f
OSC
signal. See functional description in Section 9.4 on page 31 for more details.
Unit kHz
MHz
121/153
ST72334J/N, ST72314J/N, ST72124J
16.6 MEMORY CHARACTERISTICS
16.6.1 RAM and Hardware Registers
Symbol
V
RM
Parameter
Data retention mode
1)
Conditions
HALT mode (or RESET)
16.6.2 EEPROM Data Memory
Symbol t prog t ret
N
RW
Parameter
Programming time for 1~16 bytes
3)
Data retention
5)
Write erase cycles
5)
Conditions
-40°C
≤
T
A
≤
+85°C
-40°C
≤
T
A
≤
+125°C
T
A
=
+55°C
4)
T
A
=
+25°C
Min
1.6
Min
20
300 000
Typ
Typ
Max
Max
20
25
Unit
V
Unit ms
Years
Cycles
16.6.3 FLASH Program Memory
Symbol
T
A(prog) t prog t ret
N
RW
Parameter Conditions
Programming temperature range
2)
Programming time for 1~16 bytes
3)
T
A
=
+25°C
Programming time for 4 or 8kBytes T
A
=
+25°C
Data retention
5)
Write erase cycles
5)
T
A
=+55°C
T
A
=
+25°C
4)
Min
0
20
100
Typ
25
8
2.1
Max
70
25
6.4
Unit
°C ms sec years cycles
Notes:
1. Minimum V
DD
supply voltage without losing data stored in RAM (in HALT mode or under RESET) or in hardware registers (only in HALT mode). Guaranteed by construction, not tested in production.
2. Data based on characterization results, tested in production at T
A
=25°C.
3. Up to 16 bytes can be programmed at a time for a 4kBytes FLASH block (then up to 32 bytes at a time for an 8k device)
4. The data retention time increases when the T
A
decreases.
5. Data based on reliability test results and monitored in production.
122/153
ST72334J/N, ST72314J/N, ST72124J
16.7 EMC CHARACTERISTICS
Susceptibility tests are performed on a sample basis during product characterization.
16.7.1 Functional EMS
(Electro Magnetic Susceptibility)
Based on a simple running application on the product (toggling 2 LEDs through I/O ports), the product is stressed by two electro magnetic events until a failure occurs (indicated by the LEDs).
Symbol
V
FESD
V
FFTB
■
■
ESD: Electro-Static Discharge (positive and negative) is applied on all pins of the device until a functional disturbance occurs. This test conforms with the IEC 1000-4-2 standard.
FTB: A Burst of Fast Transient voltage (positive and negative) is applied to V
DD
and V
SS
through a 100pF capacitor, until a functional disturbance occurs. This test conforms with the IEC 1000-4-
4 standard.
A device reset allows normal operations to be resumed.
Neg
1)
Pos
1)
Unit Parameter
Voltage limits to be applied on any I/O pin to induce a functional disturbance
Fast transient voltage burst limits to be applied through 100pF on V
DD
and V
DD pins to induce a functional disturbance
Conditions
V
DD
=
5V, T
A
=
+25°C, f
OSC conforms to IEC 1000-4-2
=
8MHz
V
DD
=
5V, T
A
=
+25°C, f
OSC conforms to IEC 1000-4-4
=
8MHz
-1
-4
1
4 kV
Figure 74. EMC Recommended star network power supply connection
2)
ST72XXX
10
µ
F 0.1
µ
F
V
DD
ST7
DIGITAL NOISE
FILTERING
V
SS
V
DD
POWER
SUPPLY
SOURCE
V
SSA
EXTERNAL
NOISE
FILTERING
V
DDA
0.1
µ
F
Notes:
1. Data based on characterization results, not tested in production.
2. The suggested 10
µ
F and 0.1
µ
F decoupling capacitors on the power supply lines are proposed as a good price vs. EMC performance trade-off. They have to be put as close as possible to the device power supply pins. Other EMC recommendations are given in other sections (I/Os, RESET, OSCx pin characteristics).
123/153
ST72334J/N, ST72314J/N, ST72124J
EMC CHARACTERISTICS (Cont’d)
16.7.2 Absolute Electrical Sensitivity
Based on three different tests (ESD, LU and DLU) using specific measurement methods, the product is stressed in order to determine its performance in terms of electrical sensitivity. For more details, refer to the AN1181 ST7 application note.
16.7.2.1 Electro-Static Discharge (ESD)
Electro-Static Discharges (3 positive then 3 negative pulses separated by 1 second) are applied to the pins of each sample according to each pin combination. The sample size depends of the number of supply pins of the device (3 parts*(n+1) supply pin). Two models are usually simulated:
Human Body Model and Machine Model. This test conforms to the JESD22-A114A/A115A standard.
See Figure 75 and the following test sequences.
Human Body Model Test Sequence
– C
L
is loaded through S1 by the HV pulse generator.
– S1 switches position from generator to R.
– A discharge from C
L to the ST7 occurs.
through R (body resistance)
– S2 must be closed 10 to 100ms after the pulse delivery period to ensure the ST7 is not left in charge state. S2 must be opened at least 10ms prior to the delivery of the next pulse.
Absolute Maximum Ratings
Symbol
V
ESD(HBM)
V
ESD(MM)
Ratings
Electro-static discharge voltage
(Human Body Model)
Electro-static discharge voltage
(Machine Model)
T
A
=
+25°C
T
A
=
+25°C
Machine Model Test Sequence
– C
L
is loaded through S1 by the HV pulse generator.
– S1 switches position from generator to ST7.
– A discharge from C
L
to the ST7 occurs.
– S2 must be closed 10 to 100ms after the pulse delivery period to ensure the ST7 is not left in charge state. S2 must be opened at least 10ms prior to the delivery of the next pulse.
– R (machine resistance), in series with S2, ensures a slow discharge of the ST7.
Conditions Maximum value
1)
Unit
3000
400
V
Figure 75. Typical Equivalent ESD Circuits
S1 R=1500
Ω
S1
HIGH VOLTAGE
PULSE
GENERATOR
C
L
=
100pF
ST7
S2
HIGH VOLTAGE
PULSE
GENERATOR
ST7
C
L
=
200pF
MACHINE MODEL
S2
HUMAN BODY MODEL
Notes:
1. Data based on characterization results, not tested in production.
124/153
ST72334J/N, ST72314J/N, ST72124J
EMC CHARACTERISTICS (Cont’d)
16.7.2.2 Static and Dynamic Latch-Up
■
■
LU: 3 complementary static tests are required on 10 parts to assess the latch-up performance.
A supply overvoltage (applied to each power supply pin), a current injection (applied to each input, output and configurable I/O pin) and a power supply switch sequence are performed on each sample. This test conforms to the EIA/
JESD 78 IC latch-up standard. For more details, refer to the AN1181 ST7 application note.
DLU: Electro-Static Discharges (one positive then one negative test) are applied to each pin of 3 samples when the micro is running to assess the latch-up performance in dynamic mode. Power supplies are set to the typical values, the oscillator is connected as near as possible to the pins of the micro and the component is put in reset mode. This test conforms to the IEC1000-4-2 and SAEJ1752/3 standards and is described in Figure 76 . For more details, refer to the AN1181 ST7 application note.
16.7.2.3 Designing hardened software to avoid noise problems
EMC characterization and optimization are performed at component level with a typical application environment and simplified MCU software. It
Electrical Sensitivities
Symbol
LU
DLU
Parameter
Static latch-up class
Dynamic latch-up class should be noted that good EMC performance is highly dependent on the user application and the software in particular.
Therefore it is recommended that the user applies
EMC software optimization and prequalification tests in relation with the EMC level requested for his application.
Software recommendations:
The software flowchart must include the management of runaway conditions such as:
– Corrupted program counter
– Unexpected reset
– Critical Data corruption (control registers...)
Prequalification trials:
Most of the common failures (unexpected reset and program counter corruption) can be reproduced by manually forcing a low state on the RE-
SET pin or the Oscillator pins for 1 second.
To complete these trials, ESD stress can be applied directly on the device, over the range of specification values. When unexpected behaviour is detected, the software can be hardened to prevent unrecoverable errors occurring (see application note AN1015).
Conditions
T
A
T
A
=
+25°C
=
+85°C
V
DD
=
5.5V, f
OSC
=
4MHz, T
A
=
+25°C
Class
1)
A
A
A
Figure 76. Simplified Diagram of the ESD Generator for DLU
R
CH
=50M
Ω
ESD
GENERATOR
2)
C
S
=
150pF
R
D
=330
Ω
DISCHARGE TIP
HV RELAY
DISCHARGE
RETURN CONNECTION
ST7
V
DD
V
SS
Notes:
1. Class description: A Class is an STMicroelectronics internal specification. All its limits are higher than the JEDEC specifications, that means when a device belongs to Class A it exceeds the JEDEC standard. B Class strictly covers all the
JEDEC criteria (international standard).
2. Schaffner NSG435 with a pointed test finger.
125/153
ST72334J/N, ST72314J/N, ST72124J
EMC CHARACTERISTICS (Cont’d)
16.7.3 ESD Pin Protection Strategy
To protect an integrated circuit against Electro-
Static Discharge the stress must be controlled to prevent degradation or destruction of the circuit elements. The stress generally affects the circuit elements which are connected to the pads but can also affect the internal devices when the supply pads receive the stress. The elements to be protected must not receive excessive current, voltage or heating within their structure.
An ESD network combines the different input and output ESD protections. This network works, by allowing safe discharge paths for the pins subjected to ESD stress. Two critical ESD stress cases are presented in Figure 77 and Figure 78 for standard pins and in Figure 79 and Figure 80 for true open drain pins.
Figure 77. Positive Stress on a Standard Pad vs. V
SS
V
DD
Standard Pin Protection
To protect the output structure the following elements are added:
– A diode to V
DD
(3a) and a diode from V
SS
(3b)
– A protection device between V
DD
and V
SS
(4)
To protect the input structure the following elements are added:
– A resistor in series with the pad (1)
– A diode to V
DD
(2a) and a diode from V
SS
(2b)
– A protection device between V
DD
and V
SS
(4)
V
DD
(3a) (2a)
(1)
OUT
Main path
Path to avoid
(3b)
V
SS
Figure 78. Negative Stress on a Standard Pad vs. V
DD
V
DD
(4)
(3a)
IN
(2b)
V
SS
V
DD
(2a)
(1)
OUT (4) IN
Main path
(3b) (2b)
V
SS
V
SS
126/153
ST72334J/N, ST72314J/N, ST72124J
EMC CHARACTERISTICS (Cont’d)
True Open Drain Pin Protection
The centralized protection (4) is not involved in the discharge of the ESD stresses applied to true open drain pads due to the fact that a P-Buffer and diode to V
DD
are not implemented. An additional local protection between the pad and V
SS
(5a &
5b) is implemented to completely absorb the positive ESD discharge.
Multisupply Configuration
When several types of ground (V power supply (V
DD
, V
DDA
SS
, V
SSA
, ...) and
, ...) are available for any reason (better noise immunity...), the structure shown in Figure 81 is implemented to protect the device against ESD.
Figure 79. Positive Stress on a True Open Drain Pad vs. V
SS
V
DD
V
DD
Main path
Path to avoid OUT (4) IN
(1)
(5a)
(3b) (2b)
(5b)
V
SS
V
SS
Figure 80. Negative Stress on a True Open Drain Pad vs. V
DD
V
DD
Main path
OUT (4) IN
(3b) (3b)
(1)
(2b)
(3b)
V
DD
V
SS
Figure 81. Multisupply Configuration
V
DD V
DDA
V
SS
V
DDA
V
SS
BACK TO BACK DIODE
BETWEEN GROUNDS
V
SSA V
SSA
127/153
ST72334J/N, ST72314J/N, ST72124J
16.8 I/O PORT PIN CHARACTERISTICS
16.8.1 General Characteristics
Subject to general operating conditions for V
DD
, f
OSC
, and T
A
unless otherwise specified.
Symbol
V
IL
V
IH
V hys
I
L
I
S
Parameter
Input low level voltage
2)
Input high level voltage
2)
Schmitt trigger voltage hysteresis
3)
Input leakage current
Static current consumption
4)
Conditions
V
SS
≤
V
IN
≤
V
DD
Floating input mode
Min
0.7xV
DD
Typ
1)
400
Max
0.3xV
DD
±1
200
R
PU
Weak pull-up equivalent resistor
5)
V
IN
=
V
SS
V
DD
=5V
V
DD
=3.3V
62
170
120
200
250
300
C
IO t f(IO)out t r(IO)out t w(IT)in
I/O pin capacitance
Output high to low level fall time
6)
Output low to high level rise time
6)
External interrupt pulse time
7)
C
L
=50pF
Between 10% and 90%
1
5
25
25
Figure 82. Two typical Applications with unused I/O Pin
V
DD
10k
Ω
ST72XXX
UNUSED I/O PORT
10k
Ω
UNUSED I/O PORT
ST72XXX
Figure 83. Typical I
PU
vs. V
DD
with V
IN
=V
SS
Unit
V mV
µ
A k
Ω pF ns t
CPU
40
30
20
10
0
Ipu [µA]
70
60
50
3.2
Ta=-40°C
Ta=25°C
3.5
Ta=85°C
Ta=125°C
4
Vdd [V]
4.5
5 5.5
Notes:
1. Unless otherwise specified, typical data are based on T
A
=25°C and V
DD
=5V.
2. Data based on characterization results, not tested in production.
3. Hysteresis voltage between Schmitt trigger switching levels. Based on characterization results, not tested.
4. Configuration not recommended, all unused pins must be kept at a fixed voltage: using the output mode of the I/O for example or an external pull-up or pull-down resistor (see Figure 82 ). Data based on design simulation and/or technology characteristics, not tested in production.
5. The R
PU
pull-up equivalent resistor is based on a resistive transistor (corresponding I
PU current characteristics described in Figure 83 ). This data is based on characterization results, tested in production at V
DD
max.
6. Data based on characterization results, not tested in production.
7. To generate an external interrupt, a minimum pulse width has to be applied on an I/O port pin configured as an external interrupt source.
128/153
ST72334J/N, ST72314J/N, ST72124J
I/O PORT PIN CHARACTERISTICS (Cont’d)
16.8.2 Output Driving Current
Subject to general operating conditions for V
DD
, f
OSC
, and T
A
unless otherwise specified.
Symbol Parameter
V
OL
1)
V
OH
2)
Output low level voltage for a standard I/O pin when 8 pins are sunk at same time
(see Figure 84 and Figure 87 )
Output low level voltage for a high sink I/O pin when 4 pins are sunk at same time
(see Figure 85 and Figure 88 )
Output high level voltage for an I/O pin when 4 pins are sourced at same time
(see Figure 86 and Figure 89 )
Conditions
I
IO
=+5mA T
A
T
A
≤
85°C
≥
85°C
I
IO
=+2mA T
A
T
A
≤
85°C
≥
85°C
I
IO
=+20mA, T
A
T
A
≤
85°C
≥
85°C
I
IO
=+8mA T
A
T
A
≤
85°C
≥
85°C
I
IO
=-5mA, T
A
T
A
≤
85°C
≥
85°C
I
IO
=-2mA T
A
T
A
≤
85°C
≥
85°C
Min
V
DD
V
DD
-1.6
-1.7
V
DD
-0.8
V
DD
-1.0
Max
1.3
1.5
0.65
0.75
1.5
1.7
0.75
0.85
Figure 84. Typical V
OL
at V
DD
=5V (standard)
Vol [V] at Vdd=5V
2.5
2
1.5
Ta=-40°C
Ta=25°C
Ta=85°C
Ta=125°C
Figure 86. Typical V
OH
at V
DD
=5V
Voh [V] at Vdd=5V
6
5
4
1 3
Ta=-40°C
Unit
Ta=85°C
V
0.5
2
Ta=25°C Ta=125°C
1
-8 -6 -4
Iio [mA]
-2 0
0
0 2 4
Iio [mA]
6 8 10
Figure 85. Typical V
OL
at V
DD
=5V (high-sink)
Vol [V] at Vdd=5V
2
Ta=-40°C
1.5
Ta=25°C
Ta=85°C
Ta=125°C
1
0.5
0
0 5 10 15 20 25 30
Iio [mA]
Notes:
1. The I
IO
current sunk must always respect the absolute maximum rating specified in Section 16.2.2
and the sum of I
IO
(I/O ports and control pins) must not exceed I
VSS
.
2. The I
IO
current sourced must always respect the absolute maximum rating specified in Section 16.2.2
and the sum of
I
IO
(I/O ports and control pins) must not exceed I
VDD
. True open drain I/O pins does not have V
OH
.
129/153
ST72334J/N, ST72314J/N, ST72124J
I/O PORT PIN CHARACTERISTICS (Cont’d)
Figure 87. Typical V
OL
vs. V
DD
(standard I/Os)
0.35
0.3
0.25
0.2
Vol [V] at Iio=2mA
0.5
0.45
0.4
3.2
3.5
Ta=-40°C Ta=85°C
Ta=25°C
4
Vdd [V]
4.5
Ta=125°C
5 5.5
Figure 88. Typical V
OL
vs. V
DD
(high-sink I/Os)
Vol [V] at Iio=8mA
0.55
0.5
0.45
0.4
0.35
0.3
0.25
0.2
3.2
3.5
Ta=-40°C Ta=85°C
Ta=25°C Ta=125°C
4
Vdd [V]
4.5
5 5.5
Vol [V] at Iio=5mA
1.4
1.3
1.2
1.1
0.9
1
0.8
0.7
0.6
0.5
3.2
3.5
Vol [V] at Iio=20mA
1.5
1.3
1.1
0.9
0.7
0.5
3.2
3.5
Figure 89. Typical V
OH
vs. V
DD
Voh [V] at Iio=-2mA
5.5
5
4.5
4
3.5
3
2.5
2
3.2
3.5
4
Vdd [V]
4.5
Ta=-40°C Ta=85°C
Ta=25°C Ta=125°C
5 5.5
3
2
Voh [V] at Iio=-5mA
5
4
1
0
3.5
4
Ta=-40°C Ta=85°C
Ta=25°C Ta=125°C
4
Vdd [V]
4.5
Ta=-40°C Ta=85°C
Ta=25°C Ta=125°C
4
Vdd [V]
4.5
4.5
Vdd [V]
5
5
5
5.5
5.5
Ta=-40°C Ta=85°C
Ta=25°C Ta=125°C
5.5
130/153
ST72334J/N, ST72314J/N, ST72124J
16.9 CONTROL PIN CHARACTERISTICS
16.9.1 Asynchronous RESET Pin
Subject to general operating conditions for V
DD
, f
OSC
, and T
A
unless otherwise specified.
Symbol
V
IL
V
IH
V hys
Parameter
Input low level voltage
2)
Input high level voltage
2)
Schmitt trigger voltage hysteresis
3)
Conditions Min
0.7xV
DD
Typ
1)
400
Max
0.3xV
DD
V
OL
R
ON t w(RSTL)out
Output low level voltage
4)
(see Figure 92 , Figure 93 )
Weak pull-up equivalent resistor
5)
Generated reset pulse duration
V
DD
=5V
I
IO
=+5mA
I
IO
=+2mA
V
IN
=
V
SS
V
DD
=5V
V
DD
=3.4V
External pin or internal reset sources
20
80
0.68
0.28
40
100
6
30
0.95
0.45
60
120 t h(RSTL)in t g(RSTL)in
External reset pulse hold time
6)
Filtered glitch duration
7)
20
100
Figure 90. Typical Application with RESET pin
8)
Unit
V mV
V k
Ω
1/f
SFOSC
µ s
µ s ns
ST72XXX
V
DD
OP
TI
ON
AL
USER
EXTERNAL
RESET
CIRCUIT
8)
V
DD
0.1
µ
F
0.1
µ
F
V
DD
4.7k
Ω
R
ON
RESET
INTERNAL
RESET CONTROL
WATCHDOG RESET
LVD RESET
Notes:
1. Unless otherwise specified, typical data are based on T
A
=25°C and V
DD
=5V.
2. Data based on characterization results, not tested in production.
3. Hysteresis voltage between Schmitt trigger switching levels. Based on characterization results, not tested.
4. The I
IO
current sunk must always respect the absolute maximum rating specified in Section 16.2.2
and the sum of I
IO
(I/O ports and control pins) must not exceed I
VSS
.
5. The R
ON
pull-up equivalent resistor is based on a resistive transistor (corresponding I
ON scribed in Figure 91 ). This data is based on characterization results, not tested in production.
current characteristics de-
6. To guarantee the reset of the device, a minimum pulse has to be applied to RESET pin. All short pulses applied on
RESET pin with a duration below t h(RSTL)in
can be ignored.
7. The reset network (the resistor and two capacitors) protects the device against parasitic resets, especially in a noisy environments.
8. The output of the external reset circuit must have an open-drain output to drive the ST7 reset pad. Otherwise the device can be damaged when the ST7 generates an internal reset (LVD or watchdog).
131/153
ST72334J/N, ST72314J/N, ST72124J
CONTROL PIN CHARACTERISTICS (Cont’d)
Figure 91. Typical I
ON
vs. V
DD
with V
IN
=V
SS
Ion [µA]
200
150
100
50
0
3.2
Ta=-40°C
Ta=25°C
Ta=85°C
Ta=125°C
Figure 92. Typical V
OL
at V
DD
=5V (RESET)
Vol [V] at Vdd=5V
2
Ta=-40°C
Ta=25°C
1.5
Ta=85°C
Ta=125°C
1
0.5
0
0 1 2 3 4
Iio [mA]
5 6 7 8
3.5
4
Vdd [V]
4.5
5 5.5
Figure 93. Typical V
OL
vs. V
DD
(RESET)
Vol [V] at Iio=2mA
0.55
0.5
0.45
0.4
0.35
0.3
0.25
0.2
0.15
3.2
3.5
4
Vdd [V]
Ta=-40°C Ta=85°C
Ta=25°C Ta=125°C
4.5
5 5.5
Vol [V] at Iio=5mA
1.2
0.8
1
0.6
0.4
3.2
3.5
Ta=-40°C Ta=85°C
Ta=25°C Ta=125°C
4
Vdd [V]
4.5
5 5.5
132/153
ST72334J/N, ST72314J/N, ST72124J
CONTROL PIN CHARACTERISTICS (Cont’d)
16.9.2 ISPSEL Pin
Subject to general operating conditions for V
DD
, f
OSC
, and T
A
unless otherwise specified.
Symbol
V
IL
V
IH
I
L
Parameter
Input low level voltage
1)
Input high level voltage
1)
Input leakage current V
IN
=V
SS
Figure 94. Two typical Applications with ISPSEL Pin
2)
Conditions Min Max
V
SS
0.2
V
DD
-0.1
12.6
±1
Unit
V
µ
A
ISPSEL
ST72XXX
PROGRAMMING
TOOL
10k
Ω
ISPSEL
ST72XXX
Notes:
1. Data based on design simulation and/or technology characteristics, not tested in production.
2. When the ISP Remote mode is not required by the application ISPSEL pin must be tied to V
SS
.
133/153
ST72334J/N, ST72314J/N, ST72124J
16.10 TIMER PERIPHERAL CHARACTERISTICS
Subject to general operating conditions for V
DD f
OSC
, and T
A
unless otherwise specified.
, Refer to I/O port characteristics for more details on the input/output alternate function characteristics
(output compare, input capture, external clock,
PWM output...).
16.10.1 Watchdog Timer
Symbol Parameter t w(WDG)
Watchdog time-out duration
Conditions f
CPU
=8MHz
Min
12,288
1.54
Typ Max
786,432
98.3
Unit t
CPU ms
16.10.2 16-Bit Timer
Symbol t w(ICAP)in
Parameter
Input capture pulse time t res(PWM)
PWM resolution time f
EXT f
PWM
Res
PWM
Timer external clock frequency
PWM repetition rate
PWM resolution
Conditions f
CPU
=8MHz
Min
1
2
250
0
0
Typ Max f
CPU
/4 f
CPU
/4
16
Unit t
CPU t
CPU ns
MHz
MHz bit
134/153
ST72334J/N, ST72314J/N, ST72124J
16.11 COMMUNICATION INTERFACE CHARACTERISTICS
16.11.1 SPI - Serial Peripheral Interface
Subject to general operating conditions for V
DD
, f
OSC
, and T
A
unless otherwise specified.
Refer to I/O port characteristics for more details on the input/output alternate function characteristics
(SS, SCK, MOSI, MISO).
Symbol f
SCK
1/t c(SCK)
Parameter
SPI clock frequency
Master
Slave
Conditions f
CPU
=8MHz f
CPU
=8MHz
Min f
CPU
/128
0.0625
0
Max f
CPU
2
/4 f
CPU
/2
4
Unit
MHz t r(SCK) t f(SCK) t su(SS) t h(SS) t w(SCKH) t w(SCKL) t su(MI) t su(SI) t h(MI) t h(SI) t a(SO) t dis(SO) t v(SO) t h(SO) t v(MO) t h(MO)
SPI clock rise and fall time
SS setup time
SS hold time
SCK high and low time
Data input setup time
Data input hold time
Data output access time
Data output disable time
Data output valid time
Data output hold time
Data output valid time
Data output hold time
Slave
Slave
Master
Slave
Master
Slave
Master
Slave
Slave
Slave
Slave (after enable edge)
Master (before capture edge) see I/O port pin description
120
120
100
90
100
100
100
100
0
0
0.25
0.25
120
240
120 ns t
CPU
Figure 95. SPI Slave Timing Diagram with CPHA=0 3)
SS
INPUT t su(SS) t c(SCK) t h(SS)
CPHA=0
CPOL=0
CPHA=0
CPOL=1 t a(SO) t w(SCKH) t w(SCKL) t v(SO) t h(SO) t r(SCK) t f(SCK) t dis(SO)
MISO
OUTPUT see note 2 t su(SI)
MSB OUT t h(SI)
BIT6 OUT LSB OUT see note 2
MOSI
INPUT
MSB IN BIT1 IN LSB IN
Notes:
1. Data based on design simulation and/or characterisation results, not tested in production.
2. When no communication is on-going the data output line of the SPI (MOSI in master mode, MISO in slave mode) has its alternate function capability released. In this case, the pin status depends on the I/O port configuration.
3. Measurement points are done at CMOS levels: 0.3xV
DD
and 0.7xV
DD
.
135/153
ST72334J/N, ST72314J/N, ST72124J
COMMUNICATION INTERFACE CHARACTERISTICS (Cont’d)
Figure 96. SPI Slave Timing Diagram with CPHA=1 1)
SS
INPUT t su(SS) t c(SCK)
CPHA=0
CPOL=0
CPHA=0
CPOL=1 t a(SO) t w(SCKH) t w(SCKL) t v(SO)
MISO
OUTPUT see note 2
HZ t su(SI)
MSB OUT t h(SI)
BIT6 OUT
MOSI
INPUT
MSB IN BIT1 IN t h(SS) t h(SO) t t r(SCK) f(SCK)
LSB OUT
LSB IN
Figure 97. SPI Master Timing Diagram 1)
SS
INPUT t c(SCK)
CPHA=0
CPOL=0
CPHA=0
CPOL=1
CPHA=1
CPOL=0
CPHA=1
CPOL=1 t w(SCKH) t w(SCKL) t su(MI) t h(MI)
MISO
INPUT t v(MO)
MSB IN t h(MO)
BIT6 IN
MOSI
OUTPUT see note 2 MSB OUT BIT6 OUT t r(SCK) t f(SCK)
LSB IN
LSB OUT t dis(SO) see note 2 see note 2
Notes:
1. Measurement points are done at CMOS levels: 0.3xV
DD
and 0.7xV
DD
.
2. When no communication is on-going the data output line of the SPI (MOSI in master mode, MISO in slave mode) has its alternate function capability released. In this case, the pin status depends of the I/O port configuration.
136/153
ST72334J/N, ST72314J/N, ST72124J
COMMUNICATIONS INTERFACE CHARACTERISTICS (Cont’d)
16.11.2 SCI - Serial Communications Interface
Subject to general operating condition for V
DD
SC
, and T
A
unless otherwise specified.
, f
O-
Refer to I/O port characteristics for more details on the input/output alternate function characteristics
(RDI and TDO).
Symbol f f
Tx
Rx
Parameter f
CPU
Communication frequency 8MHz
Conditions
Accuracy vs. Standard
Prescaler
~0.16%
~0.79%
Conventional Mode
TR (or RR)=64, PR=13
TR (or RR)=16, PR=13
TR (or RR)= 8, PR=13
TR (or RR)= 4, PR=13
TR (or RR)= 2, PR=13
TR (or RR)= 8, PR= 3
TR (or RR)= 1, PR=13
Extended Mode
ETPR (or ERPR) = 13
Extended Mode
ETPR (or ERPR) = 35
Standard
Baud
Rate
Unit
300
1200
2400
4800
9600
10400
19200
~300.48
~1201.92
~2403.84
~4807.69
~9615.38
~10416.67
~19230.77
Hz
38400 ~38461.54
14400 ~14285.71
137/153
ST72334J/N, ST72314J/N, ST72124J
16.12 8-BIT ADC CHARACTERISTICS
Subject to general operating conditions for V
DD
, f
OSC
, and T
A
unless otherwise specified.
Symbol Parameter Conditions Min Typ
1)
Max f
ADC
V
AIN
R
AIN
C
ADC t
STAB t
ADC
ADC clock frequency
Conversion range voltage
2)
External input resistor
Internal sample and hold capacitor
Stabilization time after ADC enable
Conversion time (Sample+Hold)
- Sample capacitor loading time
- Hold conversion time f
CPU
=8MHz, f
ADC
=4MHz
V
SSA
6
0
4)
3
4
8
4
V
DDA
10
3)
Figure 98. Typical Application with ADC
V
DD
V
T
0.6V
R
AIN AINx
V
AIN
ADC
C
IO
~2pF
V
T
0.6V
I
L
±1
µ
A
V
DD
V
DDA
0.1
µ
F
V
SSA
ST72XXX
Unit
MHz
V k
Ω pF
µ s
1/f
ADC
Notes:
1. Unless otherwise specified, typical data are based on T
A lines and are not tested.
=25°C and V
DD
-V
SS
=5V. They are given only as design guide-
2. When V
DDA and V
SSA pins are not available on the pinout, the ADC refer to V
DD and V
SS
.
3. Any added external serial resistor will downgrade the ADC accuracy (especially for resistance greater than 10k
Ω
). Data based on characterization results, not tested in production.
4. The stabilization time of the AD converter is masked by the first t
LOAD always valid.
. The first conversion after the enable is then
138/153
ST72334J/N, ST72314J/N, ST72124J
8-BIT ADC CHARACTERISTICS (Cont’d)
ADC Accuracy
Symbol Parameter
|E
T
| Total unadjusted error
1)
E
O
Offset error
1)
E
G
Gain Error
1)
|E
D
| Differential linearity error
1)
|E
L
| Integral linearity error
1)
3
2
5
4
1
7
6
Figure 99. ADC Accuracy Characteristics
Digital Result ADCDR
255
254
253
1LSB
IDEAL
=
V
DDA
–
256
V
SSA
(2)
E
T
E
O
E
L
1 LSB
IDEAL
E
D
(3)
V
DD
=5V,
2) f
CPU
=1MHz
Typ.
Max
2.0
1.5
1.5
1.5
1.5
(1)
E
G
0
V
SSA
1 2 3 4 5 6 7 253 254 255 256
V
DDA
V
DD
=5.0V,
3) f
CPU
=8MHz
Typ.
Max
2.0
1.5
1.5
1.5
1.5
V
DD
=3.3V,
3) f
CPU
=8MHz
Typ Max
2.0
1.5
1.5
1.5
1.5
(1) Example of an actual transfer curve
(2) The ideal transfer curve
(3) End point correlation line
Unit
LSB
E
T
=Total Unadjusted Error: maximum deviation between the actual and the ideal transfer curves.
E
O
=Offset Error: deviation between the first actual transition and the first ideal one.
E
G
=Gain Error: deviation between the last ideal transition and the last actual one.
E
D
=Differential Linearity Error: maximum deviation between actual steps and the ideal one.
E
L
=Integral Linearity Error: maximum deviation between any actual transition and the end point correlation line.
V in
(LSB
IDEAL
)
Notes:
1. ADC Accuracy vs. Negative Injection Current:
For I
INJ-
=0.8mA, the typical leakage induced inside the die is 1.6µA and the effect on the ADC accuracy is a loss of 1 LSB for each 10K
Ω
increase of the external analog source impedance. This effect on the ADC accuracy has been observed under worst-case conditions for injection:
- negative injection
- injection to an Input with analog capability, adjacent to the enabled Analog Input
- at 5V V
DD
supply, and worst case temperature.
2. Data based on characterization results with T
A
=25°C.
3. Data based on characterization results over the whole temperature range.
139/153
ST72334J/N, ST72314J/N, ST72124J
17 PACKAGE CHARACTERISTICS
17.1 PACKAGE MECHANICAL DATA
Figure 100. 64-Pin Thin Quad Flat Package
D
D1
E1 E b e
L1
L
A1
A
A2 h c
Dim.
mm inches
Min Typ Max Min Typ Max
A 1.60
0.063
A1 0.05
0.15 0.002
0.006
A2 1.35
1.40
1.45 0.053 0.055 0.057
b 0.30
0.37
0.45 0.012 0.015 0.018
c 0.09
0.20 0.004
0.008
D
D1
E
16.00
14.00
16.00
0.630
0.551
0.630
E1 e
θ
14.00
0°
0.80
3.5° 7° 0°
0.551
0.031
3.5° 7°
L 0.45
0.60
0.75 0.018 0.024 0.030
L1 1.00
0.039
Number of Pins
N 64
Figure 101. 56-Pin Plastic Dual In-Line Package, Shrink 600-mil Width b2
D e
A1
A2 A
C
E
E1 eA eB eB
0.015
GAGE PLANE
Dim.
mm inches
Min Typ Max Min Typ Max
A
A1 0.38
A2 3.18
b
6.35
0.015
4.95 0.125
0.250
0.195
b2
0.41
0.89
0.016
0.035
C 0.20
D 50.29
E 15.01
0.38 0.008
53.21 1.980
0.591
0.015
2.095
E1 12.32
e eA
1.78
15.24
14.73 0.485
0.070
0.600
0.580
eB
L 2.92
17.78
5.08 0.115
0.700
0.200
N
Number of Pins
56
140/153
ST72334J/N, ST72314J/N, ST72124J
PACKAGE MECHANICAL DATA (Cont’d)
Figure 102. 44-Pin Thin Quad Flat Package
D
D1
E1 E
L1
L
A1 b e
A
A2 h c
Dim.
A
A1 0.05
mm
1.60
0.15 0.002
inches
Min Typ Max Min Typ Max
0.063
0.006
A2 1.35
1.40
1.45 0.053 0.055 0.057
b 0.30
0.37
0.45 0.012 0.015 0.018
C 0.09
D
0.20 0.004 0.000 0.008
12.00
0.472
D1
E
10.00
12.00
0.394
0.472
E1 e
θ
10.00
0°
0.80
3.5° 7° 0°
0.394
0.031
3.5° 7°
L 0.45
0.60
0.75 0.018 0.024 0.030
L1 1.00
0.039
Number of Pins
N 44
Figure 103. 42-Pin Plastic Dual In-Line Package, Shrink 600-mil Width b2
D b e
A2 A
A1 L c
E
E1 eA eB
E eB eC
0.015
GAGE PLANE
Dim.
mm inches
Min Typ Max Min Typ Max
A 5.08
0.200
A1 0.51
0.020
A2 3.05
3.81
4.57 0.120 0.150 0.180
b 0.38
0.46
0.56 0.015 0.018 0.022
b2 0.89
1.02
1.14 0.035 0.040 0.045
c 0.23
0.25
0.38 0.009 0.010 0.015
D 36.58 36.83 37.08 1.440 1.450 1.460
E 15.24
16.00 0.600
0.630
E1 12.70 13.72 14.48 0.500 0.540 0.570
e 1.78
0.070
eA eB eC
15.24
18.54
1.52 0.000
0.600
0.730
0.060
L 2.54
3.30
3.56 0.100 0.130 0.140
Number of Pins
N 42
1. The power dissipation is obtained from the formula P
D
=P
INT
+P
PORT
where P
INT
is the chip internal power (I
DD xV
DD
)
141/153
ST72334J/N, ST72314J/N, ST72124J
Symbol
R thJA
P
D
T
Jmax
Ratings
Package thermal resistance (junction to ambient)
Power dissipation
1)
Maximum junction temperature
2)
TQFP64
SDIP56
TQFP44
SDIP42
Value
60
45
52
55
500
150 and P
PORT
is the port power dissipation determined by the user.
2. The average chip-junction temperature can be obtained from the formula T
J
= T
A
+ P
D
x RthJA.
Unit
°C/W mW
°C
142/153
ST72334J/N, ST72314J/N, ST72124J
17.2 SOLDERING AND GLUEABILITY INFORMATION
Recommended soldering information given only as design guidelines in Figure 105 and Figure 106 .
Recommended glue for SMD plastic packages dedicated to molding compound with silicone:
■
■
Heraeus: PD945, PD955
Loctite: 3615, 3298
Figure 105. Recommended Wave Soldering Profile (with 37% Sn and 63% Pb)
Temp. [°C]
250
200
150
100
50
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0
20 40 60 80 100 120 140 160
Time [sec]
Figure 106. Recommended Reflow Soldering Oven Profile (MID JEDEC)
250
Tmax=220+/-5°C for 25 sec
200
150 sec above 183°C
Temp. [°C]
150
100
90 sec at 125°C
50 ramp up
2°C/sec for 50sec ramp down natural
2°C/sec max
0
100 200 300 400
Time [sec]
143/153
ST72334J/N, ST72314J/N, ST72124J
18 DEVICE CONFIGURATION AND ORDERING INFORMATION
Each device is available for production in user programmable versions (FLASH) as well as in factory coded versions (ROM). E
2
PROM data memory and FLASH devices are shipped to customers with a default content (FFh), while ROM factory coded parts contain the code supplied by the customer.
This implies that FLASH devices have to be configured by the customer using the Option Bytes while the ROM devices are factory-configured.
18.1 OPTION BYTES
The two option bytes allow the hardware configuration of the microcontroller to be selected.
The option bytes have no address in the memory map and can be accessed only in programming mode (for example using a standard ST7 programming tool). The default content of the FLASH is fixed to FFh.
In masked ROM devices, the option bytes are fixed in hardware by the ROM code (see option list).
USER OPTION BYTE 0
Bit 7:2 = Reserved, must always be 1.
Bit 1 = 56/42
Package Configuration
.
This option bit allows to configured the device according to the package.
0: 42 or 44 pin packages
1: 56 or 64 pin packages
Bit 0 = FMP
Full memory protection.
This option bit enables or disables external access to the internal program memory (read-out protection). Clearing this bit causes the erasing (by overwriting with the currently latched values) of the whole memory (not including the option bytes).
0: Program memory not read-out protected
1: Program memory read-out protected
Note: The data E2PROM is not protected by this bit in flash devices. In ROM devices, a protection can be selected in the Option List (see
USER OPTION BYTE 1
Bit 7 = CSS
Clock Security System disable
This option bit enables or disables the CSS features.
0: CSS enabled
1: CSS disabled
Bit 6:4 = OSC[2:0]
Oscillator selection
These three option bits can be used to select the main oscillator as shown in Table 24 .
Bit 3:2 = LVD[1:0]
Low voltage detection selection
These option bits enable the LVD block with a selected threshold as shown in Table 25 .
Bit 1 = WDG HALT
Watchdog Reset on HALTt mode
This option bit determines if a RESET is generated when entering HALT mode while the Watchdog is active.
0: No Reset generation when entering Halt mode
1: Reset generation when entering Halt mode
Bit 0 = WDG SW
Hardware or software watchdog
This option bit selects the watchdog type.
0: Hardware (watchdog always enabled)
1: Software (watchdog to be enabled by software)
Table 24. Main Oscillator Configuration
Selected Oscillator
External Clock (Stand-by)
~4 MHz Internal RC
1~14 MHz External RC
Low Power Resonator (LP)
Medium Power Resonator (MP)
Medium Speed Resonator (MS)
High Speed Resonator (HS)
OSC2 OSC1 OSC0
1 1 1
1 1 0
1
0
0
0
0
0
1
1
0
0
0
1
X
1
0
Table 25. LVD Threshold Configuration
Configuration
LVD Off
Highest Voltage Threshold (
∼
4.50V)
Medium Voltage Threshold (
∼
4.05V)
Lowest Voltage Threshold (
∼
3.45V)
LVD1 LVD0
1 1
1 0
0
0
1
0
7
Default
Value
1 1
USER OPTION BYTE 0
Reserved
0 7
56/42 FMP CSS
OSC
2
USER OPTION BYTE 1
OSC
1
OSC
0
0
LVD1 LVD0
WDG
HALT
WDG
SW
1 1 1 1 X 0 1 1 1 0 1 1 1 1
144/153
ST72334J/N, ST72314J/N, ST72124J
DEVICE CONFIGURATION AND ORDERING INFORMATION (Cont’d)
18.2 TRANSFER OF CUSTOMER CODE
Customer code is made up of the ROM contents and the list of the selected options (if any). The
ROM contents are to be sent on diskette, or by electronic means, with the hexadecimal file in .S19
format generated by the development tool. All unused bytes must be set to FFh.
Figure 107. ROM Factory Coded Device Types
The selected options are communicated to STMicroelectronics using the correctly completed OP-
TION LIST appended.
The STMicroelectronics Sales Organization will be pleased to provide detailed information on contractual points.
DEVICE PACKAGE
TEMP.
RANGE / XXX
Code name (defined by STMicroelectronics)
1 = standard 0 to +70 °C
6 = industrial -40 to +85 °C
7 = automotive -40 to +105 °C
3 = automotive -40 to +125 °C
B = Plastic DIP
T = Plastic TQFP
ST72334J2, ST72334J4, ST72334N2, ST72334N4,
ST72314J2, ST72314J4, ST72314N2, ST72314N4,
ST72124J2
Figure 108. FLASH User Programmable Device Types
DEVICE PACKAGE
TEMP.
RANGE XXX
Code name (defined by STMicroelectronics)
1 = standard 0 to +70 °C
6 = industrial -40 to +85 °C
7 = automotive -40 to +105 °C
3 = automotive -40 to +125 °C
B = Plastic DIP
T = Plastic TQFP
ST72C334J2, ST72C334J4, ST72C334N2, ST72C334N4,
ST72C314J2, ST72C314J4, ST72C314N2, ST72C314N4,
ST72C124J2
145/153
ST72334J/N, ST72314J/N, ST72124J
Customer:
Address:
MICROCONTROLLER OPTION LIST
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Contact:
Phone No:
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Reference/ROM code*:. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
*The ROM or FASTROM code name is assigned by STMicroelectronics.
ROM or FASTROM code must be sent in .S19 format. .Hex extension cannot be processed.
STMicroelectronics references
ROM Type/Memory Size/Package (check only 1 option):
-------------------------------------------------------------------------------------------
| 8K | 16K |
SDIP42:
TQFP44:
| [ ] ST72124J2B |
| [ ] ST72314J2B | [ ] ST72314J4B
| [ ] ST72334J2B | [ ] ST72334J4B
| [ ] ST72124J2T |
| [ ] ST72314J2T | [ ] ST72314J4T
SDIP56:
| [ ] ST72334J2T | [ ] ST72334J4T
| [ ] ST72314N2B | [ ] ST72314N4B
| [ ] ST72334N2B | [ ] ST72334N4B
TQFP64: | [ ] ST72314N2T | [ ] ST72314N4T
| [ ] ST72334N2T | [ ] ST72334N4T
-------------------------------------------------------------------------------------------
8K | 16K |
|
|
|
|
|
|
|
|
|
|
SDIP42:
TQFP44:
SDIP56:
TQFP64:
| [ ] ST72P124J2B |
| [ ] ST72P314J2B | [ ] ST72P314J4B
| [ ] ST72P334J2B | [ ] ST72P334J4B
| [ ] ST72P124J2T |
| [ ] ST72P314J2T | [ ] ST72P314J4T
| [ ] ST72P334J2T | [ ] ST72P334J4T
| [ ] ST72P314N2B | [ ] ST72P314N4B |
|
|
| [ ] ST72P334N2B | [ ] ST72P334N4B |
| [ ] ST72P314N2T | [ ] ST72P314N4T |
| [ ] ST72P334N2T | [ ] ST72P334N4T |
|
|
|
|
Conditioning (specify for TQFP only): [ ] Tape & Reel [ ] Tray
Marking: [ ] Standard marking [ ] Special marking (ROM only):
TQFP (10 char. max) : _ _ _ _ _ _ _ _ _ _
SDIP (16 char. max) : _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
Authorized characters are letters, digits, '.', '-', '/' and spaces only.
Please consult your local STMicroelectronics sales office for other marking details if required.
[ ] -40°C to +125°C Temperature Range: [ ] 0°C to +70°C [ ] -40°C to +85°C
Clock Source Selection:
Resonator:
[ ] -40°C to +105°C
[ ] LP: Low power resonator (1 to 2 MHz)
[ ] MP: Medium power resonator (2 to 4 MHz)
RC Network:
External Clock:
[ ] MS: Medium speed resonator (4 to 8 MHz)
[ ] HS: High speed resonator (8 to 16 MHz)
[ ] Internal
[ ]
[ ] External
Clock Security System:
LVD Reset:
Watchdog Selection:
Watchdog Reset on Halt:
Program Readout Protection:
Data E2PROM Readout Protection*:
*available on ST72334 only
[ ] Disabled
[ ] Disabled
[ ] Software Activation
[ ] Reset
[ ] Disabled
[ ] Disabled
[ ] Enabled
[ ] Enabled: [ ] Highest threshold
[ ] Medium threshold
[ ] Lowest threshold
[ ] Hardware Activation
[ ] No reset
[ ] Enabled
[ ] Enabled
Comments:
Supply Operating Range in the application:
Notes:
Date:
Signature:
146/153
ST72334J/N, ST72314J/N, ST72124J
18.3 DEVELOPMENT TOOLS
STMicroelectronics offers a range of hardware and software development tools for the ST7 microcontroller family. Full details of tools available for the ST7 from third party manufacturers can be obtain from the STMicroelectronics Internet site:
➟ http//mcu.st.com.
Tools from these manufacturers include C compliers, emulators and gang programmers.
STMicroelectronics Tools
Three types of development tool are offered by
ST, all of them connect to a PC via a parallel (LPT) port: see Table 26 and Table 27 for more details.
Table 26. STMicroelectronics Tool Features
ST7 Development Kit
ST7 HDS2 Emulator
ST7 Programming Board No
In-Circuit Emulation
Yes. (Same features as
HDS2 emulator but without logic analyzer)
Yes, powerful emulation features including trace/ logic analyzer
Programming Capability
1)
Yes (DIP packages only)
No
Yes (All packages)
Software Included
ST7 CD ROM with:
– ST7 Assembly toolchain
– STVD7 and WGDB7 powerful
Source Level Debugger for Win
3.1, Win 95 and NT
– C compiler demo versions
– ST Realizer for Win 3.1 and Win
95.
– Windows Programming Tools for Win 3.1, Win 95 and NT
Table 27. Dedicated STMicroelectronics Development Tools
Supported Products ST7 Development Kit ST7 HDS2 Emulator ST7 Programming Board
ST72(C)334J2,
ST72(C)334J4,
ST72(C)334N2,
ST72(C)334N4,
ST72(C)314J2,
ST72(C)314J4,
ST72(C)314N2,
ST72(C)314N4,
ST72(C)124J2
ST7MDT2-DVP2 ST7MDT2-EMU2B
ST7MDT2-EPB2/EU
ST7MDT2-EPB2/US
ST7MDT2-EPB2/UK
Note:
1. In-Situ Programming (ISP) interface for FLASH devices.
147/153
ST72334J/N, ST72314J/N, ST72124J
DEVELOPMENT TOOLS (Cont’d)
18.3.1 Suggested List Of Socket Types
Table 28. Suggested List of TQFP64 Socket Types
Package / Probe
TQFP64
EMU PROBE
ENPLAS
YAMAICHI
YAMAICHI
Adaptor / Socket Reference
OTQ-64-0.8-02
IC51-0644-1240.KS-14584
IC149-064-008-S5
Socket type
Open Top
Clamshell
SMC
Suggested List of TQFP44 Socket Types
Package / Probe Adaptor / Socket Reference
TQFP44
ENPLAS
YAMAICHI
Socket type
IC51-0444-467-KS-11787 Clamshell
TQFP44
EMU PROBE
YAMAICHI IC149-044-*52-S5 SMC
148/153
ST72334J/N, ST72314J/N, ST72124J
18.4 ST7 APPLICATION NOTES
AN 979
AN 980
AN1017
AN1041
AN1042
AN1044
AN1045
AN1046
AN1047
AN1048
AN1078
AN1082
AN1083
AN1105
AN1129
IDENTIFICATION
EXAMPLE DRIVERS
AN 969
AN 970
DESCRIPTION
SCI COMMUNICATION BETWEEN ST7 AND PC
SPI COMMUNICATION BETWEEN ST7 AND EEPROM
AN 971
AN 972
AN 973
AN 974
AN 976
I²C COMMUNICATING BETWEEN ST7 AND M24CXX EEPROM
ST7 SOFTWARE SPI MASTER COMMUNICATION
SCI SOFTWARE COMMUNICATION WITH A PC USING ST72251 16-BIT TIMER
REAL TIME CLOCK WITH ST7 TIMER OUTPUT COMPARE
DRIVING A BUZZER THROUGH ST7 TIMER PWM FUNCTION
DRIVING AN ANALOG KEYBOARD WITH THE ST7 ADC
ST7 KEYPAD DECODING TECHNIQUES, IMPLEMENTING WAKE-UP ON KEYSTROKE
USING THE ST7 UNIVERSAL SERIAL BUS MICROCONTROLLER
USING ST7 PWM SIGNAL TO GENERATE ANALOG OUTPUT (SINUSOID)
ST7 ROUTINE FOR I²C SLAVE MODE MANAGEMENT
MULTIPLE INTERRUPT SOURCES MANAGEMENT FOR ST7 MCUS
ST7 S/W IMPLEMENTATION OF I²C BUS MASTER
UART EMULATION SOFTWARE
MANAGING RECEPTION ERRORS WITH THE ST7 SCI PERIPHERALS
ST7 SOFTWARE LCD DRIVER
PWM DUTY CYCLE SWITCH IMPLEMENTING TRUE 0% & 100% DUTY CYCLE
DESCRIPTION OF THE ST72141 MOTOR CONTROL PERIPHERAL REGISTERS
ST72141 BLDC MOTOR CONTROL SOFTWARE AND FLOWCHART EXAMPLE
ST7 PCAN PERIPHERAL DRIVER
PERMANENT MAGNET DC MOTOR DRIVE.
AN1130
AN1148
AN1149
AN1180
AN1276
AN1321
AN1325
AN1445
AN INTRODUCTION TO SENSORLESS BRUSHLESS DC MOTOR DRIVE APPLICATIONS
WITH THE ST72141
USING THE ST7263 FOR DESIGNING A USB MOUSE
HANDLING SUSPEND MODE ON A USB MOUSE
USING THE ST7263 KIT TO IMPLEMENT A USB GAME PAD
BLDC MOTOR START ROUTINE FOR THE ST72141 MICROCONTROLLER
USING THE ST72141 MOTOR CONTROL MCU IN SENSOR MODE
USING THE ST7 USB LOW-SPEED FIRMWARE V4.X
USING THE ST7 SPI TO EMULATE A 16-BIT SLAVE
AN1475
AN1504
DEVELOPING AN ST7265X MASS STORAGE APPLICATION
STARTING A PWM SIGNAL DIRECTLY AT HIGH LEVEL USING THE ST7 16-BIT TIMER
PRODUCT EVALUATION
AN 910 PERFORMANCE BENCHMARKING
AN 990
AN1077
ST7 BENEFITS VERSUS INDUSTRY STANDARD
OVERVIEW OF ENHANCED CAN CONTROLLERS FOR ST7 AND ST9 MCUS
AN1086
AN1150
AN1151
AN1278
U435 CAN-DO SOLUTIONS FOR CAR MULTIPLEXING
BENCHMARK ST72 VS PC16
PERFORMANCE COMPARISON BETWEEN ST72254 & PC16F876
LIN (LOCAL INTERCONNECT NETWORK) SOLUTIONS
PRODUCT MIGRATION
AN1131 MIGRATING APPLICATIONS FROM ST72511/311/214/124 TO ST72521/321/324
AN1322
AN1365
MIGRATING AN APPLICATION FROM ST7263 REV.B TO ST7263B
GUIDELINES FOR MIGRATING ST72C254 APPLICATION TO ST72F264
PRODUCT OPTIMIZATION
149/153
ST72334J/N, ST72314J/N, ST72124J
IDENTIFICATION
AN 982
AN1014
AN1015
AN1040
AN1070
AN1324
AN1477
AN1502
AN1529
AN1530
DESCRIPTION
USING ST7 WITH CERAMIC RESONATOR
HOW TO MINIMIZE THE ST7 POWER CONSUMPTION
SOFTWARE TECHNIQUES FOR IMPROVING MICROCONTROLLER EMC PERFORMANCE
MONITORING THE VBUS SIGNAL FOR USB SELF-POWERED DEVICES
ST7 CHECKSUM SELF-CHECKING CAPABILITY
CALIBRATING THE RC OSCILLATOR OF THE ST7FLITE0 MCU USING THE MAINS
EMULATED DATA EEPROM WITH XFLASH MEMORY
EMULATED DATA EEPROM WITH ST7 HDFLASH MEMORY
EXTENDING THE CURRENT & VOLTAGE CAPABILITY ON THE ST7265 VDDF SUPPLY
ACCURATE TIMEBASE FOR LOW-COST ST7 APPLICATIONS WITH INTERNAL RC OSCIL-
LATOR
PROGRAMMING AND TOOLS
AN 978 KEY FEATURES OF THE STVD7 ST7 VISUAL DEBUG PACKAGE
AN 983 KEY FEATURES OF THE COSMIC ST7 C-COMPILER PACKAGE
AN 985
AN 986
AN 987
AN 988
AN 989
AN1039
EXECUTING CODE IN ST7 RAM
USING THE INDIRECT ADDRESSING MODE WITH ST7
ST7 SERIAL TEST CONTROLLER PROGRAMMING
STARTING WITH ST7 ASSEMBLY TOOL CHAIN
GETTING STARTED WITH THE ST7 HIWARE C TOOLCHAIN
ST7 MATH UTILITY ROUTINES
AN1064
AN1071
AN1106
AN1179
AN1446
AN1478
AN1527
AN1575
WRITING OPTIMIZED HIWARE C LANGUAGE FOR ST7
HALF DUPLEX USB-TO-SERIAL BRIDGE USING THE ST72611 USB MICROCONTROLLER
TRANSLATING ASSEMBLY CODE FROM HC05 TO ST7
PROGRAMMING ST7 FLASH MICROCONTROLLERS IN REMOTE ISP MODE (IN-SITU PRO-
GRAMMING)
USING THE ST72521 EMULATOR TO DEBUG A ST72324 TARGET APPLICATION
PORTING AN ST7 PANTA PROJECT TO CODEWARRIOR IDE
DEVELOPING A USB SMARTCARD READER WITH ST7SCR
ON-BOARD PROGRAMMING METHODS FOR XFLASH AND HDFLASH ST7 MCUS
150/153
19 IMPORTANT NOTES
19.1 SCI Baud rate registers
Caution: The SCI baud rate register (SCIBRR)
MUST NOT be written to (changed or refreshed) while the transmitter or the receiver is enabled.
ST72334J/N, ST72314J/N, ST72124J
151/153
ST72334J/N, ST72314J/N, ST72124J
20 SUMMARY OF CHANGES
Description of the changes between the current release of the specification and the previous one.
Revision
2.5
“Conventional Baud Rate Generation” on page 91
Changed Watchdog and Halt mode Option to read “Watchdog reset on Halt” in Section 18
Please read carefully the Section
Date
April-03
152/153
Notes:
ST72334J/N, ST72314J/N, ST72124J
Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not authorized for use as critical components in life support devices or systems without the express written approval of STMicroelectronics.
The ST logo is a registered trademark of STMicroelectronics
2003 STMicroelectronics - All Rights Reserved.
Purchase of I
2
C Components by STMicroelectronics conveys a license under the Philips I
2
I
2
C system is granted provided that the system conforms to the I
2
C Patent. Rights to use these components in an
C Standard Specification as defined by Philips.
STMicroelectronics Group of Companies
Australia - Brazil - Canada - China - Finland - France - Germany - Hong Kong - India - Israel - Italy - Japan
Malaysia - Malta - Morocco - Singapore - Spain - Sweden - Switzerland - United Kingdom - U.S.A.
http://www.st.com
153/153
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Table of contents
- 43 12.4 LOW POWER MODES
- 43 12.5 INTERRUPTS
- 46 13 MISCELLANEOUS REGISTERS
- 46 13.1 I/O PORT INTERRUPT SENSITIVITY
- 46 13.2 I/O PORT ALTERNATE FUNCTIONS
- 47 13.3 REGISTERS DESCRIPTION
- 49 14 ON-CHIP PERIPHERALS
- 49 14.1 WATCHDOG TIMER (WDG)
- 52 14.2 MAIN CLOCK CONTROLLER WITH REAL TIME CLOCK TIMER (MCC/RTC)
- 54 14.3 16-BIT TIMER
- 72 14.4 SERIAL PERIPHERAL INTERFACE (SPI)
- 85 14.5 SERIAL COMMUNICATIONS INTERFACE (SCI)
- 97 14.6 8-BIT A/D CONVERTER (ADC)
- 101 15 INSTRUCTION SET
- 101 15.1 ST7 ADDRESSING MODES
- 104 15.2 INSTRUCTION GROUPS
- 107 16 ELECTRICAL CHARACTERISTICS
- 107 16.1 PARAMETER CONDITIONS
- 108 16.2 ABSOLUTE MAXIMUM RATINGS
- 110 16.3 OPERATING CONDITIONS
- 113 16.4 SUPPLY CURRENT CHARACTERISTICS
- 116 16.5 CLOCK AND TIMING CHARACTERISTICS
- 122 16.6 MEMORY CHARACTERISTICS
- 123 16.7 EMC CHARACTERISTICS
- 128 16.8 I/O PORT PIN CHARACTERISTICS
- 131 16.9 CONTROL PIN CHARACTERISTICS
- 134 16.10 TIMER PERIPHERAL CHARACTERISTICS
- 135 16.11 COMMUNICATION INTERFACE CHARACTERISTICS
- 138 16.12 8-BIT ADC CHARACTERISTICS
- 140 17 PACKAGE CHARACTERISTICS
- 140 17.1 PACKAGE MECHANICAL DATA
- 143 17.2 SOLDERING AND GLUEABILITY INFORMATION
- 144 18 DEVICE CONFIGURATION AND ORDERING INFORMATION
- 144 18.1 OPTION BYTES
- 145 18.2 TRANSFER OF CUSTOMER CODE
- 147 18.3 DEVELOPMENT TOOLS
- 149 18.4 ST7 APPLICATION NOTES
- 151 19 IMPORTANT NOTES
- 151 19.1 SCI BAUD RATE REGISTERS
- 152 20 SUMMARY OF CHANGES