Massive Audio D2500.1 block series User`s manual

Automatic Projector Tilt Compensation
System
Ganesh Ajjanagadde
Shantanu Jain
James Thomas
December 10, 2014
Abstract
We designed a system that corrects the input to a projector if it is
tilted so that its output appears unskewed. We read input from a NTSC
(National Television System Committee) video camera and store it in an
internal block memory. We then process the frame stored in memory
using a perspective transformation to pre-warp the image that is sent to
the projector via a VGA (Video Graphics Array) signal. The parameters
of the perspective transformation are obtained from an accelerometer,
which senses two axes of tilt. This allows automatic keystone correction
in the two directions sensed by the accelerometer provided the output
screen is vertical. Our method also includes options for manual keystone
correction to any degree desired, for any projector and screen orientations.
For ease of manual correction, we provide the option of using a test pattern
(a checkerboard). We also play some useful audio for the percentage of
pixels kept by the transformation.
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Acknowledgments
First and foremost, we would like to thank our 6.111 instructor Gim Hom for his
tremendous patience, experience, and intuition regarding digital systems. This
project would never have been possible without him, and countless number of
times he saved our group a huge amount of time by some very crucial observations. Not only that, he also played a very important role in our choice of
project topic. Initially, we were planning to create some sort of Bitcoin miner.
I think it is safe to say that we are all glad that we chose this topic instead on
his suggestion.
We would also like to thank all the teaching assistants, lab assistants, and
CI-M writing instructors for their very useful suggestions and feedback. We
particularly appreciate the guidance of one of our TA’s Jos´e E. Cruz Serall´es for
his wealth of experience with Verilog and Xilinx’s tools. His project on recursive
augmented reality was also very useful as a reference point for certain aspects,
such as generation of clocks of different frequencies and the correct timing of
sync and blank signals for a 640 × 480 @60 Hz VGA display. Furthermore, he
was able to identify a subtle bug with our memory address computation.
Last, but not least, we would like to thank all our peers in this class. Their
thoughtful questions during our proposal presentation raised issues that we had
not anticipated. Furthermore, they often were willing to help with some commonly faced issues in the lab, thereby avoiding duplication of effort. We particularly appreciate the note on Piazza (our online discussion forum) by Andres
Erbsen regarding test benches and use of Icarus Verilog.
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Contents
1 Introduction
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2 Previous Work
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3 Module Architecture
3.1 Accelerometer interface . . .
3.2 Perspective transformation .
3.3 I/O (Input/Output) interface
3.4 Audio system . . . . . . . . .
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4 Design Decisions
4.1 Use of 640 × 480 @60 Hz VGA
4.2 Use of NTSC Camera as Input
4.3 Choice of Memory Architecture
4.4 Choice of clocks . . . . . . . . .
4.5 User interface considerations .
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5 Module Descriptions
5.1 par to ser (James) . . . . . .
5.2 ser to par (James) . . . . . .
5.3 moving avg (James) . . . . .
5.4 acc (James) . . . . . . . . . .
5.5 accel lut (Ganesh) . . . . . .
5.6 pixels kept (Ganesh) . . . . .
5.7 bram (Ganesh) . . . . . . . .
5.8 addr map (Ganesh) . . . . . .
5.9 slow clk (Ganesh, James) . .
5.10 move cursor (Ganesh) . . . .
5.11 perspective params (Ganesh)
5.12 pixel map (Ganesh) . . . . .
5.13 ntsc to bram (James) . . . .
5.14 audioManager (Shantanu) . .
5.15 BCD (Shantanu) . . . . . . .
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6 Final Product and User Interface
7 Testing And Debugging
7.1 Icarus Verilog test benches/verification . .
7.2 Xilinx ModelSim test benches/verification
7.3 Julia implementations/tests of algorithms
7.4 Labkit I/O . . . . . . . . . . . . . . . . .
7.5 Staring at code/data-sheets . . . . . . . .
7.6 USB input to flash memory issues . . . .
7.7 Integration tests . . . . . . . . . . . . . .
3
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8 Future Work
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9 Conclusion
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A Source Code
A.1 Staff Modules . . . . . . . . .
A.1.1 debounce.v . . . . . .
A.1.2 delay.v . . . . . . . . .
A.1.3 display 16hex.v . . . .
A.1.4 vga.v . . . . . . . . .
A.1.5 divider.v . . . . . . . .
A.1.6 ycrcb2rgb.v . . . . . .
A.1.7 ntsc2zbt.v . . . . . . .
A.1.8 video decoder.v . . . .
A.1.9 flash int.v . . . . . . .
A.1.10 flash manager.v . . . .
A.1.11 test fsm.v . . . . . . .
A.1.12 usb input.v . . . . . .
A.1.13 usb transfer script.py
A.2 Labkit . . . . . . . . . . . . .
A.2.1 labkit.v . . . . . . . .
A.2.2 labkit.ucf . . . . . . .
A.3 Our Modules . . . . . . . . .
A.3.1 acc.v . . . . . . . . . .
A.3.2 accel lut.v . . . . . . .
A.3.3 accel lut.jl . . . . . . .
A.3.4 accel lut.txt . . . . . .
A.3.5 pixels kept.v . . . . .
A.3.6 bram.v . . . . . . . . .
A.3.7 addr map.v . . . . . .
A.3.8 slow clk.v . . . . . . .
A.3.9 move cursor.v . . . . .
A.3.10 perspective params.v .
A.3.11 pixel map.v . . . . . .
A.3.12 audioManager.v . . .
A.3.13 binaryToDecimal.py .
A.3.14 BCD.v . . . . . . . . .
A.3.15 ClockDivider.v . . . .
A.3.16 Square.v . . . . . . . .
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1
Introduction
Due to the advances in semiconductor technology, today’s display projectors
can incorporate fairly sophisticated digital processing algorithms for various
enhancements to the visual appearance. Moreover, there is an increasing prevalence of portable projectors that benefit from fast, automated setup. One desired
functionality is keystone/tilt correction. In other words, even when the projector is tilted, the projector should be able to “pre-warp” the image so that its
output appears unskewed. Figure 1 shows what is meant by the keystone effect
and what its desired correction should look like 1 .
Figure 1: Keystone Correction In Vertical Direction
In this project, we project the output of a camera, connect the camera’s
output to the FPGA (Field Programmable Gate Array) board, and the FPGA
board’s VGA output to the projector. We mount an accelerometer on the
projector and measure its signals to determine the projector’s tilt angle on two
axes. We then run a perspective transformation algorithm on the FPGA that
warps the camera output based on the tilt angles and produces the results at the
VGA output for the projector to display. We also provide a manual correction
mode so that any desired correction can be achieved. This manual correction
mode is exposed to the user via the arrow keys and switches on the FPGA kit.
This is of use in mainly two cases:
• The automatic correction obtained using the accelerometer readings is
unsatisfactory or inadequate.
• The user desires to correct for projector orientation in the third axis, or
in the case when the screen is non-vertical.
1 https://en.wikipedia.org/wiki/File:Vertical-keystone.jpg
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Finally, we also provide a useful voice output for the percentage of pixels kept
after the perspective transformation (this is a lossy transformation in general).
The audio is triggered by pressing a button on the FPGA kit.
2
Previous Work
Given the practical importance of keystone correction, there has been significant
research on doing automatic keystone correction. While Raskar and Beardsley
[2001] and Sukthankar et al. [2001] provide a solution to this problem, their
methods suffer from one principal weakness, already noted in Li and Sezan
[2004], namely that their algorithms are not well suited for implementation
in an embedded system. For instance, their methods require solving an 8x8
system of linear equations via Gaussian elimination or similar methods, which
is not suitable for embedded platforms, particularly those with slow dividers.
Our key technical contribution is the elimination of the Gaussian elimination
algorithm, and instead replacing it with closed form solutions for the equations.
Moreover, we implement our algorithm on a 6 million gate Xilinx Virtex 2
FPGA, demonstrating that our algorithm is suitable for embedded systems use.
The work done in Li and Sezan [2004] subsumes most of this work. However,
their system is much more complex, as evidenced by the use of a camera for
computing the precise perspective transformation. For the scope of this term
final project, we use a simpler accelerometer based approach instead, paying the
price of loss of automatic correction along one axis. Note that we still retain
fully general manual correction ability.
3
Module Architecture
Figure 2 shows a block diagram including all of the major modules in our
system, which are explained further below and in later sections:
6
Figure 2: Block Diagram
Our keystone correction system can be divided into roughly four functional
components:
1. Accelerometer interface
2. Perspective transformation
3. I/O (Input/Output) interface
4. Audio system
Each functional component handles a specific collection of tasks, and is further broken down into a set of one or more modules.
3.1
Accelerometer interface
The accelerometer presents a SPI interface for data transfer. The par to ser
module converts a multi-bit value to a serial stream of bits for transfer to the
accelerometer. The ser to par module converts a serial stream of bits read
from the accelerometer to a multi-bit value of desired width. The moving avg
module computes the average of 32 accelerometer readings. This is done to
counteract some of the noise in the accelerometer readings. The acc module
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uses the par to ser and ser to par modules to initialize the accelerometer and
fetch x and y acceleration readings from it in a loop, averaging them using the
moving avg module.
3.2
Perspective transformation
The perspective transformation component is where all core computations are
performed. The accel lut module accepts the accelerometer readings from the
accelerometer as an index into a ROM (read-only memory) containing coordinates of four coordinates of a quadrilateral. The corners of the quadrilateral
(after multiplexing with manual override parameters) are fed into the perspective params module, which computes necessary perspective transformation parameters. The perspective parameters are then fed into pixel map, which maps
the screen rectangle onto the quadrilateral described above via a perspective
transformation. The pixels kept module is a side module that accepts the corners of the quadrilateral, and computes the percentage of pixels kept during the
transformation. This is of use in the audio system.
3.3
I/O (Input/Output) interface
The input/output interface to various buttons/switches is contained in the toplevel labkit.v file. Here, the hardware of the labkit is mapped to the modules, and the functional components are connected together. The relevant buttons/switches are passed to move cursor module, which manipulates the corners
of the quadrilateral when the user wishes to manually adjust the correction. The
bram module implements a very simple 2 port block memory on the FPGA. Two
instances of this are created, one called ntsc buf storing the camera input, and
one called vga buf containing the processed output (from the perspective transformation). Essentially, we have a pipeline formed: input camera writes to
ntsc buf, perspective transformation reads from ntsc buf and writes to vga buf,
and the output VGA signal is formed by looping over the vga buf.
3.4
Audio system
The audio system is responsible for receiving, saving, and playing back audio.
This requires interacting with several different pieces of hardware and external
modules. The top-level module of this functional component is audioManager.
When triggered by a switch setting, audioManager prepares itself for receiving
the audio tracks as a continuous stream of data from the external USB input
hardware. Because of the difficult-to-implement timing requirements of the
external hardware, we use the 6.111 staff provided usb input module to simplify
receiving data over USB. As audio data is being received over USB, it is written
to the labkit’s on-board flash memory. Flash memory is also difficult to use,
since a time-sensitive start up sequence needs to be followed to enable proper
use of the flash hardware. We made use of the staff provided flash manager,
test fsm, and flash int modules. This set of modules greatly abstracts away the
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low-level details of working with the flash. When the audio is triggered via an
external button input, audioManager handles queuing up the appropriate set
of tracks for sequential playback. The percentage of pixels used is an external
input to audioManager from the pixels kept module.
4
Design Decisions
There are several noteworthy design decisions.
4.1
Use of 640 × 480 @60 Hz VGA
The first of them is the use of a 640 × 480 @60 Hz VGA display. The use of
640 × 480 as opposed to the more common higher resolutions found today is
due to the memory and computational limitations of our FPGA kit. Initially,
we hoped that we could get away with generic code that does not explicitly tie
in heavily with the specific screen resolution. Unfortunately, this is not easy,
since the choice of resolution influences many different aspects. Chief among
these are the sizes of memory vs available memory trade-off, the bit widths
of x and y coordinates, the size of the accel lut ROM, and the bit widths of
numerous other quantities such as the dividers and the multipliers in pixel map
and perspective params respectively. The choice of 60 Hz was made on the
basis of its almost guaranteed availability: almost all VGA displays support
this refresh rate.
4.2
Use of NTSC Camera as Input
Also related to input/output is our decision to use an NTSC camera feed as
the input to the FPGA. Ideally, we would have liked to hook up a computer’s
VGA signal to the FPGA, so that we can demonstrate the correction system
in a more realistic setting. Unfortunately, the labkit in this course has only a
single VGA port, ruling out this option.
4.3
Choice of Memory Architecture
Another major design decision made is the choice of memory architecture. We
initially planned on using the available 36 Mbits of ZBT memory spread across 2
banks. This would allow us to store at least 4 frames at full 640 × 480 resolution
and 24 bit color (8 bit R, 8 bit G, 8 bit B). Unfortunately, it turns out that
ZBT memory is not dual-ported, so read and write on the same bank can’t be
achieved simultaneously. Since the perspective transform (operating pixel by
pixel) turns out to be a huge computational bottleneck, we did not want to waste
additional time waiting for read/write on ZBT. Moreover, coordination between
the memory banks storing processed and unprocessed data would require some
sort of arbiter, adding complexity to our project. Thus, we chose instead to go
with the block memory on the FPGA. This can be made into true dual-port
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memory, and has a single read/write cycle latency, as opposed to the multicycle latency of ZBT memory. However, the amount of block memory available
on the FPGA is only 2.5 Mbits. This required sacrifice on image quality. We
chose a combination of image down-sampling and color depth reduction. More
specifically, we chose a 320x240 sized memory, with 12 bits per line (4 bit R, 4
bit G, 4 bit B). This results in approximately 1 Mbit per buffer, and we use 2
buffers, leaving us with nearly 512k for the accel lut ROM. That is more than
sufficient for our accel lut. It is certainly possible to squeeze some more color
depth, e.g a 14 bit asymmetrical division among R, G, and B. This should help
the image quality, but our visual tests indicated no substantial improvement,
and hence we omitted this.
4.4
Choice of clocks
A technically noteworthy design decision is our choice of clocks. To avoid clock
domain issues, as much as possible we used multiples of a common system clock.
Using the Xilinx DCM (Digital Clock Manager), we synthesized a 50 MHz clock
from the labkit’s standard 27 MHz clock. We used this as a global sys clk.
640 × 480 @60Hz needs to be driven at nearly 25 MHz, and was thus obtained
by multiplying the time period of sys clk by 2. The NTSC camera must be
driven at around 27 MHz, and the appropriate clock is already generated by
the labkit - clock 27mhz. To avoid change of the perspective parameters midframe, we also needed a slow clk signal, i.e one who’s time period is on the
order of seconds. This can’t be accomplished through the use of DCM that
easily. Moreover, since actual timing violations for this signal are not really
that important, we implemented a simple “flip clock on reaching a count” style
“clock divider”.
The audio system used the native clock 27mhz for all logic excluding providing data to the AC97 audio codec hardware. The operation of providing audio
samples to the AC97 operated on the AC97’s external clock. This is required
because the AC97 plays back audio at a 48kHz rate, a common audio sampling
rate. On spare cycles between the AC97’s external clock and the native clock,
the system performed all other operations, including track queueing and track
switching.
4.5
User interface considerations
An important factor in the quality of the projected image is the percentage
of pixels used. The more correction is applied to the image, the more image
quality suffers and the dimmer the resulting projection. We wanted to provide
the user of the system this information. They could act on this feedback by
further adjusting the projector if possible. We realized only power users would
be able to make use of this feedback, so we wanted to provide it in a nonintrusive manner - audio was the most natural candidate. The decision to use
audio was not without drawbacks. Hearing-impaired users would unfortunately
not be able to make use of the feedback. Since the labkit’s on-board display
10
was already used for the manual correction system, there was no other way to
display the percentage of pixels used without showing it on the projected screen,
which we had earlier eliminated considering it was only useful to power users.
The manual adjustment functionality relies on the user being able to select
the corner to be manipulated via a set of switches. While this binary representation would be natural to computer engineers and mathematicians, it would not
be self-explanatory to non-technical users. We were again constrained by the
labkit’s limited hardware input devices from making a more natural interface.
Of course, in theory we could have hooked up an external keyboard to another
one of the labkit’s ports, but this would have increased the complexity of our
project.
5
Module Descriptions
In this section, we give a more detailed description of each module, along with
the respective contributors.
5.1
par to ser (James)
This module converts a word of some size W (e.g. reg[W-1:0]) to a stream of
bits, one at each clock cycle, to be sent to the accelerometer. The higher-order
bits are produced first. This module is necessitated by the SPI communication
protocol of the accelerometer.
5.2
ser to par (James)
This module converts a stream of bits received from the accelerometer, one per
clock cycle, to a word of desired width. It expects that the higher-order bits
will be received first.
5.3
moving avg (James)
This module uses a ring buffer to store the last 32 acceleration readings received
from the accelerometer for a particular dimension. When a new sample is received, the oldest sample is removed, the sum of the last 32 samples is adjusted
accordingly, and the average is recomputed. Since we compute the average over
32 (25 ) samples, we do not need dividers and can use bit shifts for the needed
divisions. This module is meant to smooth acceleration readings, which are
expected to fluctuate slightly even when the accelerometer is held fixed.
5.4
acc (James)
The timing diagram for 4-wire SPI interaction with the accelerometer is shown
below:
11
This module first initializes the accelerometer and then reads x and y acceleration values from it in a loop. The clock used for accelerometer communications
is our 50 MHz system clock slowed by a factor of 20, which meets the the max
clock frequency spec of 5 MHz. Most of the default configurations for the accelerometer are acceptable for our purposes; the only initialization we need to
do is set the measure bit of the POWER CTL register (each register contains a
single byte). Since this register is at address 0x2D, and since we want to perform
a single-byte write to it, we first drive the SDI pin with the serial bit stream
8’b00101101 (see Figure 5 in the timing diagram upper two bits for mode and
lower six bits for register address). This specifies the mode and register address,
and can then be used to drive it with the data to be stored in the register. By
default, the accelerometer can measure acceleration values in the range of ±2g.
This is sufficient for our purposes since we care only about static acceleration
(which is in the range ±1g).
After 16 accelerometer clock cycles have passed, we know that we have sent
all of the necessary initialization data to the accelerometer. We then transition our accelerometer state machine to the x-y read loop. Since the x and y
acceleration readings are 16 bits (two registers’ worth, since the accelerometer
gives us 10 bits of precision), we want to perform a multi-byte read of the x and
y registers. This can be done in the manner shown in Figure 6 of the timing
diagram. We simply assert the R and MB bits, continue driving SDI with the
address bits for the first x or first y register (the second registers for x and y
immediately follow the first, which is why the multi-byte read of contiguous
12
registers is acceptable), and then wait 16 additional cycles for all of our data
to be produced on the SDO line. We rotate between a state for reading the x
registers and a state for reading the y registers. We feed the produced x and
y readings into instantiations of the moving avg filter. The output of the acc
module is the output of these filters.
One challenge we faced was getting the accelerometer clock period correct.
Even though the spec states that the maximum clock frequency is 5 MHz, if we
use a 5 MHz clock and then use a single clock cycle to implement the tCS,DIS
waiting period shown in Figures 5 and 6 of the timing diagram, we will not meet
the minimum tCS,DIS spec of 250ns. So we had to pick a clock frequency lower
1s
= 4 MHz to use a one-cycle wait to meet the tCS,DIS spec. This bug
than 250ns
took quite a while to find.
The picture below shows the accelerometer module working in isolation, with
averaged accelerometer readings displayed on the hex display:
Figure 3: Accelerometer readings on hex display
13
5.5
accel lut (Ganesh)
The accel lut module provides a look-up table from the accelerometer readings
in two directions to the four corners of the quadrilateral. The output is synchronized to the global sys clk. The module is essentially implemented as a giant
case statement, from which Xilinx’s tools are able to infer a ROM of the appropriate size. Although the data coming out of the accelerometer has 10 bits of
precision in each axis, using the full precision would require too much space for
the ROM. Instead, we use 6 bits for each of the 2 axes, for a total of 12 bits as
an index into the ROM. Each word of the ROM is 76 bits wide. This is because
each x coordinate is 10 bits wide (0 to 639), each y coordinate is 9 bits wide
(0 to 479), and there are 4 corners. Since each entry corresponds to a choice
of quadrilateral corners, and there are 212 = 4096 entries, manual entry of the
look-up table is infeasible. Instead, we wrote a code generator accel lut.jl in the
Julia programming language (julialang.org). Essentially, the code generator
accepts an input CSV (comma separated values) file containing some entries
of the desired look-up table obtained via manual testing. The code generator
then does a mathematical interpolation to obtain the remaining values of the
look-up table, and writes out the accel lut.v file. Of course, it may be argued
that the interpolation is not sufficient to get fine grained accuracy. Indeed,
our demonstration did show that our look-up table could use some refinement.
However, we believe that this is not an inherent deficiency of the approach; it
just means that we need more data points and sufficient polynomial degree of
the interpolator. Also related to this is another merit to this method: as the
user obtains more and more entries, he/she can simply populate the CSV file
with them. The quality of interpolation can then only improve.
5.6
pixels kept (Ganesh)
The pixels kept module accepts the four corners of the quadrilateral, computes
its area, and expresses it as a percentage of the total area. The area formula of
a quadrilateral in terms of the coordinates of its four corners is a simple determinant expansion, and may be found easily in elementary geometry references.
For a quadrilateral with coordinates (x1 , y1 ), (x2 , y2 ), (x3 , y3 ), (x4 , y4 ), its area
A is given by the expression:
2A = |(x1 − x3 )(y2 − y4 ) − (y1 − y3 )(x2 − x4 )|.
(1)
The division by 640 × 480, and subsequent multiplication by 100 is accomplished without doing either a hardware division or multiplication for efficiency
reasons. The key observation here is that 64 × 48 = 210 × 3. Thus, it suffices to
figure out how to divide by 3 without performing a hardware division. For this,
21
we approximate 3 by 64
, giving us the result correct to the nearest percent. The
output is then a 7 bit value expressing the percentage from 0 to 100.
14
5.7
bram (Ganesh)
The bram module is a very simple true dual port memory module, with exactly
enough storage for a down-sampled frame (320x240) with 12 bit color depth
per pixel. By convention, the first port is always a write port, triggered by
a WE (write enable) signal. The second port is a read port. The ports have
their own individual address lines and clock signals in order to achieve the dual
ported-ness. The advantages of a dual port memory over a single port memory
were clear in our case, and have already been outlined. One more advantage
of a dual port memory is that the two ports can be driven at different clocks.
The only place where the dual ported abstraction breaks down is when one
tries to read and write to the same address simultaneously. It is clear that
there is no reasonable behavior in that case. Our design takes this into account,
and guarantees that at most one pixel in each frame stores a garbage value.
Given the large fraction of displays with at least one defective pixel, this is
an extremely minor issue. We initially used Xilinx’s proprietary IP Coregen
application to synthesize the BRAM (block random access memory) module.
However, in order to maximize portability and minimize the use of proprietary
files, we studied this a little more and found out that with the appropriate
Verilog code, Xilinx’s tools will automatically infer the presence of a BRAM.
This allowed us to use our own very simple BRAM implementation. It also
gave us one additional benefit: Coregen modules often take significantly longer
to synthesize as compared to inferred ones.
5.8
addr map (Ganesh)
The addr map is a critical single-line module that abstracts away memory address computations, allowing one to address the correct location in memory by
providing the x coordinate and y coordinate locations. This is a pure combinational logic module, with no synchronization to any clock. Essentially, it takes
in an x coordinate in [0, 639] and a y coordinate in [0, 479], and computes the
memory address in the 320x240 line BRAM buffer. This is achieved by taking
the integer part of a division by 2 of the x and y coordinates, followed by a
standard mapping of a 2 dimensional matrix address to a flat array, an exact
analog of manipulating a matrix that has been heap allocated in the C programming language. We unfortunately had a somewhat subtle bug in our memory
address computation. At its core, it boils down to the fact that integer division
by two followed by a multiplication is not the same as multiplication followed
by integer division by two. Fortunately, we tested this early on, and noticed a
checkerboard pattern with horizontal stripes on the VGA display instead of a
neat checkerboard. The credit for finding that bug goes to our TA Jos´e.
5.9
slow clk (Ganesh, James)
The slow clk is a simple module that takes in a high frequency clock signal
(on the order of MHz) and generates a signal with a much lower frequency.
15
For us, this was of use in generating a clock with a frequency on the order
of a Hz for synchronizing the quadrilateral corner locations and perspective
transform parameters. It was also of use in generating a clock signal that met the
manufacturer specs for the accelerometer (see the acc section). It is implemented
by having a looping counter that would result in an inversion of the clock signal
every time the counter hit a certain number of “ticks”. Note that this method
is not a robust way of generating an in-phase clock with no skew. It is, however,
quite well suited for the task of generating much lower frequency clocks, such as
a 1000 times lower frequency. For other applications, such as dividing a clock
frequency by a factor of 2, we used Xilinx’s DCM (Digital Clock Manager)
instead.
5.10
move cursor (Ganesh)
The move cursor module is a user interface module for manipulating the four
corners of a quadrilateral. It allows one to move the four corners of a quadrilateral by pressing the four arrow keys and selecting the corner index through
the switches on the labkit. To avoid accidental manual adjustment of keystone
correction, the movement can only be done when an override switch is on. This
module is very similar to the controls used to move the paddle in the Pong game
that we designed for Lab 3, and no tricky debugging was needed for this.
5.11
perspective params (Ganesh)
The perspective params module lies at the very heart of this project. It accepts
a list of the four corners of the quadrilateral (x1 , y1 ), (x2 , y2 ), (x3 , y3 ), (x4 , y4 )
and finds the parameters pi , 1 ≤ i ≤ 9 such that the general perspective transformation:
p1 x + p2 y + p3 p4 x + p5 y + p6
(x, y) →
,
(2)
p7 x + p8 y + p9 p7 x + p8 y + p9
maps the outer coordinates of the screen (0, 0), (0, 480), (640, 480), (640, 0) onto
(x1 , y1 ), (x2 , y2 ), (x3 , y3 ), (x4 , y4 ) respectively. The module also computes the
coefficients pinvi of the inverse mapping, which is also a perspective transformation (due to the algebraic group structure of perspective transformations
which can be checked by direct calculation). The reason for computing the
pinvi is mainly due to our initial goal of having a “memory-less” output transformation, in the sense that given the desired VGA coordinate, we can compute
the pre-image of that point. This in turn was due to an inadequate understanding of the FPGA memory and VGA behavior. For instance, we assumed
that the VGA frame rate can be controlled simply by adjusting the VGA clock,
an assumption that is incorrect. This lack of understanding at one point almost threatened the successful completion of our project, and thus we strongly
recommend future 6.111 students to think and discuss very hard the hardware
limitations before starting actual implementation work. We were fortunately
able to come up with the BRAM design, which although suffers from poorer
image quality, nevertheless demonstrates the soundness of our algorithm. It
16
turns out that the BRAM design can work equally well with either pi or pinvi .
However, at this point of the project, we had already started using pinvi and
did not want to take the risk of going back to pi . Computing both pi and pinvi
takes up approximately 80 % of the 144 available 18x18 bit signed multipliers
on the FPGA. This may be easily reduced to around 20 % by eliminating the
computation of pinvi , something we would have done with additional time for
the project.
Note that the pi (or pinvi ) may be scaled by an arbitrary constant, so without
loss of generality, we assumed that p3 = 1. However, to avoid needless divisions,
in the actual solutions implemented on the FPGA, we scale all parameters to
ensure that they are all integers. The closed-form solution to the set of equations
(2) (as implemented on the FPGA) is given below:
p7 = 3[(x1 − x4 )(y2 − y3 ) + (y1 − y4 )(x3 − x2 )]
(3)
p8 = 4[(x1 = x2 )(y3 − y4 ) + (x4 − x3 )(y1 − y2 )]
(4)
d = x4 (y2 − y3 ) + x2 (y3 − y4 ) + x3 (y4 − y2 )
(5)
p9 = 1920d
(6)
p3 = 1920x1 d
(7)
p6 = 1920y1 d
(8)
p1 = x4 p7 + 3(x4 − x1 )d
(9)
p2 = x2 p8 + 4(x2 − x1 )d
(10)
p4 = y4 p7 + 3(y4 − y1 )d
(11)
p5 = y2 p8 + 4(y2 − y1 )d
(12)
pinv1 = p6 p8 − p5 p9
(13)
pinv2 = p2 p9 − p3 p8
(14)
pinv3 = p3 p5 − p2 p6
(15)
pinv4 = p4 p9 − p6 p7
(16)
pinv5 = p3 p7 − p1 p9
(17)
pinv6 = p1 p6 − p3 p4
(18)
pinv7 = p5 p7 − p4 p8
(19)
pinv8 = p1 p8 − p2 p7
(20)
pinv9 = p2 p4 − p1 p5
(21)
dx = 639pinv1
(22)
dy = 639pinv4
(23)
dd = 639pinv7
(24)
dx , dy , dd are a couple of parameters used to avoid multiplications in the actual mapping described by the perspective transformation (2). More precisely,
they allow clients of this module (such as pixel map in our case) to simply execute a two dimensional loop over the image, incrementing/decrementing the
numerator and denominator on each iteration as opposed to performing a fresh
17
multiplication. Essentially, they correspond to the decrements needed at the
end of each horizontal scan line. Note the use of 480, 640 (i.e 1920
and 1920
4
4 )
as opposed to the more precise 479, 639. The reason for this is that 480, 640
are multiples of sizable powers of two, reducing the bit width needed for certain
multiplications required in the solution. Moreover, the difference caused by this
slight error can be ignored, due to the continuity of the perspective transformation. Quite crucial to the ease of solving this set of equations symbolically by
hand was a good choice of basis. We were fortunate that the “natural basis” in
terms of the screen coordinates is actually a pretty good one in that sense.
The outputs of this module are synchronized on a slow clk signal. The
rationale for this is two fold:
1. Due to large number of multiplications, even with pipe-lining, it is unlikely
that we can meet timing requirements of sys clk (50 MHz).
2. It is undesirable to change the parameters mid-frame anyway, and having
a huge latency in changing these parameters may thus in fact be desirable.
5.12
pixel map (Ganesh)
The pixel map module uses the parameters pinvi and dx , dy , dd obtained in the
perspective params module to do the actual perspective transformation pixel
by pixel. At a high level, it is doing a simple loop through x and y through
[0, 639] and [0, 479] respectively, computing
pinv1 x + pinv2 y + pinv3 pinv4 x + pinv5 y + pinv6
,
pinv7 x + pinv8 y + pinv9 pinv7 x + pinv8 y + pinv9
at each x and y. It then uses the results to obtain the memory address via
addr map in the ntsc buffer, and uses another addr map to write the data
found in the ntsc buffer to the VGA buffer. When the coordinates of the inverse transformation are out of range, the module writes a black pixel. A state
machine is used to start the divider and keep track of the general state of the
computation. The divider used is based on the restoring division algorithm, and
was provided by the staff. There was a subtle bug in the staff-provided divider,
resulting in incomplete divisions being written out. For us, that translated into
always reading an address of 0 of the ntsc buffer, leading to a uniform color over
the whole frame. Essentially, the bug boiled down to an insufficient width for a
counter register in the divider. Tracking down the bug was pretty difficult, since
it first required verifying that our pixel map module was providing the correct
numerator and denominator. A test bench (runnable under the free software
Icarus Verilog simulator) confirmed that there was something wrong with the
divider. Another test bench then verified that the results of the division were
indeed incorrect. Finally, a close examination of the divider code resulted in the
identification of the bug. Once this bug was fixed, the module worked correctly.
Unfortunately, the divider needs a width of 79 bits, and the staff provided divider is not pipe-lined. Xilinx’s IP Coregen provides pipe-lined dividers up to a
18
width of 32 bits, which is insufficient for our needs. Furthermore, they discourage creation of pipe-lined dividers of greater width due to the high area cost.
As such, we require 80 clock cycles per pixel, resulting in a frame rate of 1-2
frames per second. Note that with sufficient hardware resources, this may be
easily converted into a real-time system.
5.13
ntsc to bram (James)
Most of the staff code from the zbt 6111 example was kept intact, including the
ADV7185 initialization module and the NTSC decoding module. ntsc to zbt
was converted to ntsc to bram, which involved a few changes. First off, ROW START
and COL START were changed to be 0, since we want our image to fill the entire screen (as opposed to the staff example, where the upper left corner of the
image does not start at pixel (0,0)). We expanded all of the registers holding
NTSC data to have widths of 30 bits (as opposed to 8), since we want 12-bit
color and need the full YCrCb data. We maintained the original approach of
reading only scan lines from field 0 and alternately writing them to even and
odd screen rows. Since we stored pixels in BRAM, which has a maximum capacity of 2.5 Mbits, and we needed to store a frame from the camera and another
frame with the transformed output in addition to the look-up table (discussed
above), we only had space to store a 320 by 240 frame with 12 bits of color per
pixel. So we cropped the NTSC input by taking only the upper left 320 by 240
rectangle.
Since we now store one pixel per memory location as opposed to four (we
were able to size our BRAM so that each location was 12 bits), we write to
BRAM whenever the x address is less than 320 and the y address is less than
240 and we are at a write enable positive edge, given by the we edge signal in
the code. (In the staff code, we wrote to ZBT only when the x address was a
multiple of 4 since we stored 4 pixels per memory location). We determined
the BRAM address from the x and y coordinates by treating BRAM as a 2D
array with 240 rows and 320 columns laid out in row-major order (row 1 in
the first 320 locations, row 2 in the next 320, etc.). So we simply multiplied
the y coordinate by 320 and added the x coordinate to get the BRAM address.
Finally, since we needed to convert the YCrCb data to RGB using the staffprovided module, which takes 3 clock cycles, we needed to delay the BRAM
address and BRAM write enable signals by three clock cycles as well using the
staff-provided synchronize module so that we wrote the right data to the right
addresses.
Since our BRAM has both read and write ports, we were able to write camera
data to the BRAM at the same time that our transformation code fetched pixels
from this BRAM, eliminating the need for any coordination mechanisms.
One major challenge in designing this module was eliminating the appearance of randomly colored pixels in the video output. We expected the video to
be grainy because we were scaling a 320 by 240 image to 640 by 480 resolution
for projection, but the random pixels were unexplained until Gim pointed out
that we were writing the BRAM at a different clock rate (the system clock rate)
19
than the NTSC data was coming to us (the tv in line clock1 rate). This was
causing some setup times at the BRAM to be violated when clocks were out of
phase and the BRAM to be written with unstable values.
Below is an image of the ntsc to bram code working in isolation:
Figure 4: camera output using bram
5.14
audioManager (Shantanu)
The audioManager module is the core module in the audio playback component.
It handles the whole life-cycle of audio, from receiving over USB, to storing into
flash, queuing tracks, and playback. It interfaces with three external hardware
components - the flash chip, the USB interface, and the AC97 audio codec
hardware.
The module is centered around its interaction with the flash hardware, since
the flash memory is manipulated any time the module is active. Depending
on the input of the switches, it either sets the flash memory to “read mode”
or “write mode.” To prevent the module from resetting the flash memory and
20
deleting its contents, which the labkit automatically does when it is powered
on, the module also has a “reset disable” switch.
When in “write mode”, the labkit prepares itself to receive data from the usb
hardware, via the usb input module provided by the staff. Whenever usb input
indicates a new data sample is available, the “dowrite” input to the staff provided flash manager module is asserted to be true, in order to trigger the write
operation. The system continues in this cycle until the user’s computer indicates
all data has been transmitted, at which time he must exit write mode by manipulating the switches to “read mode.” Due to the limitations of flash manager,
data must be written in one session - the user does not have the ability to leave
“write mode,” analyze the data on the flash memory, and re-enter “write mode”
to continue writing, without first resetting the flash and deleting all the data
it contains. As a result, this module inherits these limitations, and so a user
may have to manually disable the “reset disable” switch to trigger a reset if his
data transfer was to fail. When in “read mode” the flash memory’s contents
can be retrived one location at a time, by setting the read address parameter
“raddr”. We keep this value at address 0, until we receive the signal to begin
audio playback. Based on the percentage of pixels kept, an input signal to the
module, the sequence of audio tracks to be played is decided. For example, if
eighty-nine percent of pixels are used, four audio tracks are queued for playback:
“Eighty,” “Nine,” “Percent,” “Used.” In particular, the number eighty nine is
constructed out of two separate sequential tracks instead of a single recording.
This system allows us to save memory, reducing transfer time and accumulated
error, at the expense of additional complexity in the module.
Having decided what tracks are to be played back, playback begins by calculating the address of the currently playing track, and retriving the contents
of that memory location. While many schemes may be used to calculate the
location of the track, we made our recording so that every track is exactly one
second long. We then used a simple multiplication of one second of samples by a
track index to calculate the track address. Based on the AC97’s external 48kHz
clock, we provided a new audio sample to the AC97 to acheive audio playback.
After one second of samples had been played back, we calculated the address of
the next track queued and began playback. A special end of playback marker
called “UNUSED TRACK” halted playback.
5.15
BCD (Shantanu)
This module converts from a binary representation to a decimal representation.
It was used within the audioManager module to convert the percentage of pixels kept from binary to a decimal representation in order to assign the tracks
to be played. This was necessary since digital systems naturally use binary
representations, but our audio output was necessarily in decimal.
Technically, we opted to implement this module as a look-up table that assigned the decimal ones and tens place based on the input value. The alternative
was to use a computational algorithm implemented in Verilog, which was widely
available. We used the look-up table because we thought it provided more clar21
ity to the user than the seemingly-opaque efficient algorithms, at the expense
of utilizing more of the scarce look-up tables on the hardware.
6
Final Product and User Interface
Below is an image of our working system automatically correcting the input to
a tilted projector so that it appears rectangular:
Figure 5: Automatic Keystone Correction
Below is an image of the user interface (UI) to our correction system:
22
Figure 6: User Interface
When pressed, button 0 triggers the audio system, which announces the
percentage of screen pixels currently used for the corrected image. LEDs 7-1
show the binary representation of this value. Buttons 2 and 3 adjust the volume
of the audio system up or down. The first four digits on the hex display show the
current x acceleration value, the next four show the current y acceleration value,
the next four show the x coordinate of the corner of the quadrilateral selected
by switches 0 and 1, and the last four show the y coordinate of this corner.
If switch 7 is high, we are in manual correction mode, and the accelerometer
readings are ignored. In this mode, we can manually adjust the corner of the
quadrilateral selected by switches 0 and 1 by pressing the up and down buttons
(to adjust the x coordinate) and the left and right buttons (to adjust the y
coordinate). When switch 5 is high, we display a checkerboard on the screen
instead of the NTSC camera input.
7
Testing And Debugging
Testing and debugging Verilog-defined hardware is complicated due to the large
synthesis times. Unlike software, where one can change a single line of code, and
23
trigger an incremental build that can complete on the order of seconds, synthesis
of FPGA hardware is a lengthy process, taking on the order of minutes or even
hours depending on the amount of logic. Our complete avoidance of Coregen
modules definitely served us well in this respect. We also consciously often
commented out unnecessary modules. This provided dual benefits:
• Much shorter synthesis times
• Ensuring that the bug is being isolated as much as possible.
Nevertheless, these two steps are certainly not sufficient in efficient debugging.
As such, we adopted a multi-pronged testing and debugging approach. Broadly
speaking, we used the following methods:
• Icarus Verilog test benches/verification
• Xilinx ModelSim test benches/verification
• Julia implementations/tests of algorithms
• Labkit I/O, e.g led’s, hex display, logic analyzer probes
• Staring at code/data-sheets
• Integration tests
7.1
Icarus Verilog test benches/verification
By far the most effective and efficient way of testing simple modules in our
experience was the use of Icarus Verilog. We are extremely grateful to a fellow
student Andres for posting a note on our online discussion forum (Piazza) regarding the benefits and use of Icarus Verilog. Defining and using test benches
through Icarus Verilog is extremely easy and efficient. In our experience, this
was most useful for verifying long and complicated chains of combinational logic,
such as mathematical algorithms. It was also very useful for checking the syntax
of our Verilog code. As an example of its utility, we found a bug with perspective params that originated from incorrect mixed use of signed and unsigned
arithmetic. The main drawbacks of Icarus Verilog are its lack of visualizations
of waveforms when invoked on the command line, and its decreasing utility with
complex state machines and other sequential logic. The first of these drawbacks
is addressed quite well by Xilinx ModelSim.
7.2
Xilinx ModelSim test benches/verification
ModelSim helped us to discover a bug in the staff-provided divider module.
We instantiated a 79-bit divider and were not getting correct results. When we
examined waveforms in ModelSim, we saw that the ready bit was being asserted
far fewer than 79 cycles after we started the division. Upon closer examination
of the module, it turned out that the counter the module was using to keep
24
track of the current bit was only 6 bits wide, which supports only operand bit
widths up to 63. We extended the width of this counter to 7 bits to solve this
issue.
ModelSim was also used to verify the functionality of the BCD module. After
uncovering a bug in the percentage of pixels kept during integration, the first
area of investigation was the BCD module, since it was the least tested module.
It was trivial to write a test bench for the module and verify the output was
correct using ModelSim.
7.3
Julia implementations/tests of algorithms
Prior to implementing the perspective transforms on the FPGA, we definitely
wanted to verify the soundness of our approach in software first. We settled
on the use of the Julia programming language for this purpose, though in all
likelihood MATLAB or Python(+numpy/scipy/matplotlib) would have served
just as well. This was by far the most effective means of testing whether an algorithm is correct or not, since one can rely on the benefits of fast debug/iterate
cycles in software. This is particularly true in the case of languages featuring a
REPL (read, evaluate, print loop) based interpreter, such as Julia. Correcting
code is as simple as making some changes, re-including the file in the REPL,
and rerunning. This helped us particularly in the verification of the pixels kept
and perspective params module. As an aside, to avoid using too many languages for software implementations, we used Julia for our code generator for
the accel lut as well. As a concrete example of a serious bug caught using the
help of our software implementations, we were able to track and correct an error
in the computation of p1 and p2 using this method. Essentially, the bug was
an interchange of two terms in the closed form expressions that occurred while
transcribing the closed form solutions we found for p1 and p2 from paper to the
computer code.
7.4
Labkit I/O
We wired up the logic analyzer to the accelerometer pins to verify that the acc
module was correctly initializing the accelerometer (e.g. the par to ser module
was producing the correct serial bit stream for the register address and data).
It turned out that the bug in the accelerometer was elsewhere (see the next
section).
7.5
Staring at code/data-sheets
This is definitely a questionable inclusion, and we do not recommend this
method in general. Nevertheless, it is often effective when done correctly and in
the right spirit, since it forces one to rethink and step through the logic again,
questioning all assumptions. For instance, once we confirmed that the divider
implementation was incorrect, we had to examine the divider code line by line.
25
It did not take us too long to realize the mistake in the implementation, and
looking back we do not see any other way of correcting the mistake.
As described in the section on the acc module, taking a second pass through
the data-sheet for the accelerometer helped us to identify an issue with a violated
timing constraint (tCS,DIS ).
7.6
USB input to flash memory issues
The most challenging issue in the audio component of the project was receiving
data over USB and storing the samples into flash memory. When we received
data over USB, we wrote it immediately to the flash memory. However, after a
data transfer, we noticed that many of the bytes were missing.
The flash memory is already difficult to work with because of its tight timing
constraints. It is also an old piece of hardware, with read and write times
considered slow at the time of manufacture of the labkit over ten years ago. We
theorized that the flash memory was too slow to be able to write data at the
rate it was being received.
To isolate the device at fault, a series of unit tests were developed. One test
took data from a look-up table coded into the device via Verilog and placed
it into the flash memory. When we analyzed the flash memory contents, we
found it was exactly the same as the look-up table. From this test we were able
to conclude that the flash memory was functional. We developed another test
that counted the number of bytes received over the USB module before writing
them to flash. We found that while the number of bytes received was exactly
the number of bytes transmitted from the computer, the number of bytes in
memory was still off by a factor between two and three. Even while buffering
the data from the USB input device, itself also a buffer, we could not improve
the performance of the system.
Despite repeatedly consulting with instructor Gim Hom, teaching assistant
Luis Fernandez (who previously implemented a working audio system), and the
author of the staff-provided flash manager module, and in spite of our best efforts to understand and modify the code, we could not improve the performance
enough to record all samples. We did improve our system so that the audio was
intelligible. With Gim’s approval, we closed this issue as not resolvable in the
scope of our project and moved forward.
7.7
Integration tests
In addition to testing modules in isolation, we obviously also needed to test
whether the modules work together or not. Fortunately, the audio system could
be quite easily separated from the rest of the system, so we anticipated easy
integration here. Ironically, we faced a strange problem here, which we never
understood. The issue was with the percentage value computed by pixels kept.
Initially, pixels kept was actually named pixels lost, and was computing 100 minus the percentage of pixels kept. The audio module was written for percentage
of pixels kept however, so initially the audio module did a second subtraction
26
from 100 to get the correct value. The playback of the percentage was often
incorrect for some reason (never identified). Initially, we were keen on fixing
the issue from the audio end, since pixels lost was a known correct module.
However, we had no luck fixing it from the audio end, so instead we renamed
pixels lost to pixels kept and removed the subtraction from 100. This somehow
fixed the issue.
Much easier was the integration with the accelerometer. This went flawlessly after we agreed upon the clock frequencies used by the accelerometer and
the system. We made sure that the clocks used by the accelerometer and the
accel lut (to which the accelerometer readings are sent) were integer multiples
of one another to prevent any setup or hold time violations when clocks were
out of phase.
Integration of the transformation logic with the memory interface was also
extremely smooth, apart from the subtle bug in address computation uncovered
by our TA Jos´e.
One of the most tedious aspects was the collection of data values for the lookup table. It took around 2 hours of fiddling with the manual correction to get
12 readings for doing the interpolation. Lacking the appropriate measurement
equipment, it is difficult to verify that the vertical edges of the checkerboard are
exactly parallel to the vertical edges of the screen. Furthermore, we also needed
to ensure that the 4:3 aspect ratio was not distorted.
8
Future Work
Although our projector tilt compensation system met most of our initial goals,
there are a wide variety of extensions and modifications to the project that we
would have liked to implement.
On the image side, we would like to take some steps to improve the quality
of the projected image. As noted earlier, one of our key design decisions was
the use of reduced resolution (320 × 240) and reduced color depth (12 bit as
opposed to 24 bit). This can be achieved with either a labkit with more dualported memory, or our existing labkit with a sophisticated ZBT based memory
design (with an arbiter). Another improvement that can be made to the images
is the use of some sort of anti-aliasing filter. For instance, when we compute
the coordinates in the pixel map module, we only look at the integer part of
the division (corresponding to a single pixel index). By looking at the fractional
part, we could interpolate the color values at neighboring pixels and use that to
reduce the “jagged edges” associated with aliasing in images.
Another significant unknown is how well the accelerometer approach works
when the projector is not kept at a fixed distance from the screen. We have
not tested whether this would affect the quality of the automatic correction. If
this does affect quality, we are confident that by adding an additional distance
sensor, we could simply incorporate the distance values into the lookup table
and make the automatic correction usable again. Of course, the lookup table
could become very large if we do this. There are two avenues around this:
27
• Store the look-up table in a larger memory, e.g ZBT.
• A more scalable approach is to start doing interpolation in the hardware
itself. This will require additional hardware resources and more logic, but
the size of the logic will only grow with the number of data points, as
opposed to the number of bits coming from the sensors.
Within the audio component, there are many avenues for substantial improvement. The major unresolved issue was the loss of data samples when
transferring data over USB and recording it to flash memory. The preferred
alternative would be a more modern hardware platform with an updated flash
hardware component, as well as an on-board USB module and reference code
supplied from the manufacturer. This would likely solve whatever bottleneck
stopped us. Another alternative would be to use the serial port instead of the
USB hardware, since the labkit already has a serial port built in. This would
require a moderately complex Verilog module to implement the serial protocol,
although Xilinx may provide some reference code.
Another opportunity for improvement would be variable length tracks. Every track was one second long, which resulted in artificial sounding two digit
numbers because some portion of the one second track was silence. A variable
length track would reduce the length of silence and sound overall more natural.
Our implementation barred us from pursing this improvement as it requires an
end-of-track marker for the track. Since we were randomly losing data samples,
we could not reliably determine when the track ended, and so were forced into
the fixed-length option.
Another useful feature which we unfortunately did not have time to implement is persistent storage of a user’s manual correction settings. After all, no
matter how good the accel lut is, it is extremely likely that with certain extreme
orientations, the settings obtained through the look-up table are unsatisfactory.
One option for dealing with this would be saving manual override settings into
some non-volatile storage such as flash, and using them on the next power cycle.
Given our issues with compact flash in the audio domain, progress on this front
would likely be negligible. Hopefully, with an improved labkit, we would not
run into the flash issues.
9
Conclusion
Our projector tilt compensation system used digital logic to successfully perform a perspective transform on an image. This enables fully general manual
correction of distortions of the projected image on the screen. Moreover, we
also created an automatic correction system for correction of distortion resulting from 2 axes of tilt via the usage of an accelerometer that would sense the
angle of tilt along these two axes. We also implemented a useful audio features
regarding the percentage of pixels kept by our correction system.
We believe that there were a number of factors that allowed us to succeed
with this project. First and foremost, we started early and tackled potential
28
issues as early as possible, with a consistent time commitment every week.
Second, we spent a lot of time doing software simulations/verifications before
diving in and writing Verilog. The rationale behind this is that correction and
testing in software is much faster than synthesis on the FPGA. Third, we had
regular meetings among ourselves to ensure that issues some member of our
team had would be addressed collectively.
Overall, we are satisfied with the quality of this system, especially considering the time limitations/scope of this project. We are confident that with some
additional work, this system could truly rival commercial offerings in this space.
References
Baoxin Li and I. Sezan. Automatic keystone correction for smart projectors with
embedded camera. In Image Processing, 2004. ICIP ’04. 2004 International
Conference on, volume 4, pages 2829–2832 Vol. 4, Oct 2004. doi: 10.1109/
ICIP.2004.1421693.
Ramesh Raskar and Paul Beardsley. A self-correcting projector. In Computer
Vision and Pattern Recognition, 2001. CVPR 2001. Proceedings of the 2001
IEEE Computer Society Conference on, volume 2, pages II–504. IEEE, 2001.
Rahul Sukthankar, Robert G Stockton, and Matthew D Mullin. Smarter presentations: Exploiting homography in camera-projector systems. In Computer
Vision, 2001. ICCV 2001. Proceedings. Eighth IEEE International Conference on, volume 1, pages 247–253. IEEE, 2001.
29
A
Source Code
Source code for the project may be obtained on GitHub: https://github.com/
gajjanag/6111_Project. For completeness, we include all source code here as
well. For ease of browsing through the code, we have divided the modules into
roughly three categories:
• Staff Modules: modules that are essentially the same as staff provided
modules, with minor modifications for our specific needs.
• Labkit: top level labkit module with general instantiations, including clock
generators, and ucf file
• Our Modules: modules created by us for our project
A.1
A.1.1
1
2
3
4
5
6
Staff Modules
debounce.v
// Switch Debounce Module
// use your system clock for the clock input
// to produce a synchronous, debounced output
module debounce #(parameter DELAY=270000)
// .01 sec with a 27Mhz clock
(input reset, clock, noisy,
output reg clean);
7
8
9
reg [18:0] count;
reg new;
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
always @(posedge clock)
if (reset)
begin
count <= 0;
new <= noisy;
clean <= noisy;
end
else if (noisy != new)
begin
new <= noisy;
count <= 0;
end
else if (count == DELAY)
clean <= new;
else
count <= count+1;
27
28
endmodule
30
A.1.2
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
delay.v
‘timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date:
23:13:26 12/02/2014
// Design Name:
// Module Name:
delay
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
// pulse synchronizer
module synchronize #(parameter NSYNC = 2, parameter W = 1) // number of sync flops.
(input clk, input [W-1:0] in,
output reg [W-1:0] out);
25
26
reg [(NSYNC-1)*W-1:0] sync;
27
28
29
30
31
32
always @ (posedge clk)
begin
{out,sync} <= {sync[(NSYNC-1)*W-1:0],in};
end
endmodule
A.1.3
1
2
3
4
5
6
7
8
9
display 16hex.v
///////////////////////////////////////////////////////////////////////////////
//
// 6.111 FPGA Labkit -- Hex display driver
//
// File:
display_16hex.v
// Date:
24-Sep-05
//
// Created: April 27, 2004
// Author: Nathan Ickes
31
must b
10
11
12
13
14
15
16
17
18
//
// 24-Sep-05 Ike: updated to use new reset-once state machine, remove clear
// 28-Nov-06 CJT: fixed race condition between CE and RS (thanks Javier!)
//
// This verilog module drives the labkit hex dot matrix displays, and puts
// up 16 hexadecimal digits (8 bytes). These are passed to the module
// through a 64 bit wire ("data"), asynchronously.
//
///////////////////////////////////////////////////////////////////////////////
19
20
21
22
module display_16hex (reset, clock_27mhz, data,
disp_blank, disp_clock, disp_rs, disp_ce_b,
disp_reset_b, disp_data_out);
23
24
25
input reset, clock_27mhz;
input [63:0] data;
// clock and reset (active high reset)
// 16 hex nibbles to display
26
27
28
output disp_blank, disp_clock, disp_data_out, disp_rs, disp_ce_b,
disp_reset_b;
29
30
reg disp_data_out, disp_rs, disp_ce_b, disp_reset_b;
31
32
33
34
35
36
37
38
////////////////////////////////////////////////////////////////////////////
//
// Display Clock
//
// Generate a 500kHz clock for driving the displays.
//
////////////////////////////////////////////////////////////////////////////
39
40
41
42
43
reg [4:0] count;
reg [7:0] reset_count;
reg clock;
wire dreset;
44
45
46
47
48
49
50
51
52
53
54
55
always @(posedge clock_27mhz)
begin
if (reset)
begin
count = 0;
clock = 0;
end
else if (count == 26)
begin
clock = ~clock;
count = 5’h00;
32
56
57
58
59
end
else
count = count+1;
end
60
61
62
63
64
65
always @(posedge clock_27mhz)
if (reset)
reset_count <= 100;
else
reset_count <= (reset_count==0) ? 0 : reset_count-1;
66
67
assign dreset = (reset_count != 0);
68
69
assign disp_clock = ~clock;
70
71
72
73
74
75
////////////////////////////////////////////////////////////////////////////
//
// Display State Machine
//
////////////////////////////////////////////////////////////////////////////
76
77
78
79
80
81
82
reg
reg
reg
reg
reg
reg
[7:0] state;
[9:0] dot_index;
[31:0] control;
[3:0] char_index;
[39:0] dots;
[3:0] nibble;
// FSM state
// index to current dot being clocked out
// control register
// index of current character
// dots for a single digit
// hex nibble of current character
83
84
assign disp_blank = 1’b0; // low <= not blanked
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
always @(posedge clock)
if (dreset)
begin
state <= 0;
dot_index <= 0;
control <= 32’h7F7F7F7F;
end
else
casex (state)
8’h00:
begin
// Reset displays
disp_data_out <= 1’b0;
disp_rs <= 1’b0; // dot register
disp_ce_b <= 1’b1;
disp_reset_b <= 1’b0;
33
102
103
104
dot_index <= 0;
state <= state+1;
end
105
106
107
108
109
110
111
8’h01:
begin
// End reset
disp_reset_b <= 1’b1;
state <= state+1;
end
112
113
114
115
116
117
118
119
120
121
122
8’h02:
begin
// Initialize dot register (set all dots to zero)
disp_ce_b <= 1’b0;
disp_data_out <= 1’b0; // dot_index[0];
if (dot_index == 639)
state <= state+1;
else
dot_index <= dot_index+1;
end
123
124
125
126
127
128
129
130
131
8’h03:
begin
// Latch dot data
disp_ce_b <= 1’b1;
dot_index <= 31;
// re-purpose to init ctrl reg
disp_rs <= 1’b1; // Select the control register
state <= state+1;
end
132
133
134
135
136
137
138
139
140
141
142
143
8’h04:
begin
// Setup the control register
disp_ce_b <= 1’b0;
disp_data_out <= control[31];
control <= {control[30:0], 1’b0};
if (dot_index == 0)
state <= state+1;
else
dot_index <= dot_index-1;
end
// shift left
144
145
146
147
8’h05:
begin
// Latch the control register data / dot data
34
148
149
150
151
152
153
disp_ce_b <= 1’b1;
dot_index <= 39;
char_index <= 15;
state <= state+1;
disp_rs <= 1’b0;
end
// init for single char
// start with MS char
// Select the dot register
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
8’h06:
begin
// Load the user’s dot data into the dot reg, char by char
disp_ce_b <= 1’b0;
disp_data_out <= dots[dot_index]; // dot data from msb
if (dot_index == 0)
if (char_index == 0)
state <= 5;
// all done, latch data
else
begin
char_index <= char_index - 1;
// goto next char
dot_index <= 39;
end
else
dot_index <= dot_index-1;
// else loop thru all dots
end
171
172
endcase
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
always @ (data or char_index)
case (char_index)
4’h0:
nibble
4’h1:
nibble
4’h2:
nibble
4’h3:
nibble
4’h4:
nibble
4’h5:
nibble
4’h6:
nibble
4’h7:
nibble
4’h8:
nibble
4’h9:
nibble
4’hA:
nibble
4’hB:
nibble
4’hC:
nibble
4’hD:
nibble
4’hE:
nibble
4’hF:
nibble
endcase
193
35
<=
<=
<=
<=
<=
<=
<=
<=
<=
<=
<=
<=
<=
<=
<=
<=
data[3:0];
data[7:4];
data[11:8];
data[15:12];
data[19:16];
data[23:20];
data[27:24];
data[31:28];
data[35:32];
data[39:36];
data[43:40];
data[47:44];
data[51:48];
data[55:52];
data[59:56];
data[63:60];
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
always @(nibble)
case (nibble)
4’h0: dots <=
4’h1: dots <=
4’h2: dots <=
4’h3: dots <=
4’h4: dots <=
4’h5: dots <=
4’h6: dots <=
4’h7: dots <=
4’h8: dots <=
4’h9: dots <=
4’hA: dots <=
4’hB: dots <=
4’hC: dots <=
4’hD: dots <=
4’hE: dots <=
4’hF: dots <=
endcase
40’b00111110_01010001_01001001_01000101_00111110;
40’b00000000_01000010_01111111_01000000_00000000;
40’b01100010_01010001_01001001_01001001_01000110;
40’b00100010_01000001_01001001_01001001_00110110;
40’b00011000_00010100_00010010_01111111_00010000;
40’b00100111_01000101_01000101_01000101_00111001;
40’b00111100_01001010_01001001_01001001_00110000;
40’b00000001_01110001_00001001_00000101_00000011;
40’b00110110_01001001_01001001_01001001_00110110;
40’b00000110_01001001_01001001_00101001_00011110;
40’b01111110_00001001_00001001_00001001_01111110;
40’b01111111_01001001_01001001_01001001_00110110;
40’b00111110_01000001_01000001_01000001_00100010;
40’b01111111_01000001_01000001_01000001_00111110;
40’b01111111_01001001_01001001_01001001_01000001;
40’b01111111_00001001_00001001_00001001_00000001;
213
214
endmodule
A.1.4
1
2
3
4
5
6
7
vga.v
‘default_nettype none
////////////////////////////////////////////////////////////////////////////////////////////
// vga: Generate XVGA display signals (640 x 480 @ 60Hz)
// essentially a copy of staff xvga module with different timings
// Credits: timings from Jose’s project (Fall 2011),
// general code from staff xvga module (e.g Lab 3 - pong game)
////////////////////////////////////////////////////////////////////////////////////////////
8
9
10
11
12
module vga(input vclock,
output reg [9:0] hcount, // pixel number on current line
output reg [9:0] vcount, // line number
output reg vsync,hsync,blank);
13
14
15
16
17
18
19
20
21
22
// VGA (640x480) @ 60 Hz
parameter VGA_HBLANKON =
parameter VGA_HSYNCON
=
parameter VGA_HSYNCOFF =
parameter VGA_HRESET
=
parameter VGA_VBLANKON =
parameter VGA_VSYNCON
=
parameter VGA_VSYNCOFF =
parameter VGA_VRESET
=
10’d639;
10’d655;
10’d751;
10’d799;
10’d479;
10’d490;
10’d492;
10’d523;
36
23
24
25
26
27
28
29
30
31
// horizontal: 800 pixels total
// display 640 pixels per line
reg hblank,vblank;
wire hsyncon,hsyncoff,hreset,hblankon;
assign hblankon = (hcount == VGA_HBLANKON);
assign hsyncon = (hcount == VGA_HSYNCON);
assign hsyncoff = (hcount == VGA_HSYNCOFF);
assign hreset = (hcount == VGA_HRESET);
32
33
34
35
36
37
38
39
// vertical: 524 lines total
// display 480 lines
wire vsyncon,vsyncoff,vreset,vblankon;
assign vblankon = hreset & (vcount == VGA_VBLANKON);
assign vsyncon = hreset & (vcount == VGA_VSYNCON);
assign vsyncoff = hreset & (vcount == VGA_VSYNCOFF);
assign vreset = hreset & (vcount == VGA_VRESET);
40
41
42
43
44
45
46
47
48
// sync and blanking
wire next_hblank,next_vblank;
assign next_hblank = hreset ? 0 : hblankon ? 1 : hblank;
assign next_vblank = vreset ? 0 : vblankon ? 1 : vblank;
always @(posedge vclock) begin
hcount <= hreset ? 0 : hcount + 1;
hblank <= next_hblank;
hsync <= hsyncon ? 0 : hsyncoff ? 1 : hsync; // active low
49
vcount <= hreset ? (vreset ? 0 : vcount + 1) : vcount;
vblank <= next_vblank;
vsync <= vsyncon ? 0 : vsyncoff ? 1 : vsync; // active low
50
51
52
53
54
55
56
blank <= next_vblank | (next_hblank & ~hreset);
end
endmodule
A.1.5
1
2
3
4
5
//
//
//
//
//
divider.v
The divider module divides one number by another. It
produces a signal named "ready" when the quotient output
is ready, and takes a signal named "start" to indicate
the the input dividend and divider is ready.
sign -- 0 for unsigned, 1 for twos complement
6
7
8
// It uses a simple restoring divide algorithm.
// http://en.wikipedia.org/wiki/Division_(digital)#Restoring_division
9
37
10
11
12
13
14
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module divider #(parameter WIDTH = 8)
(input clk, sign, start,
input [WIDTH-1:0] dividend,
input [WIDTH-1:0] divider,
output reg [WIDTH-1:0] quotient,
output [WIDTH-1:0] remainder,
output ready);
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reg [WIDTH-1:0] quotient_temp;
reg [WIDTH*2-1:0] dividend_copy, divider_copy, diff;
reg negative_output;
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assign remainder = (!negative_output) ?
dividend_copy[WIDTH-1:0] : ~dividend_copy[WIDTH-1:0] + 1’b1;
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reg [6:0] bit;
reg del_ready = 1;
assign ready = (!bit) & ~del_ready;
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wire [WIDTH-2:0] zeros = 0;
initial bit = 0;
initial negative_output = 0;
always @( posedge clk ) begin
del_ready <= !bit;
if( start ) begin
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bit = WIDTH;
quotient = 0;
quotient_temp = 0;
dividend_copy = (!sign || !dividend[WIDTH-1]) ?
{1’b0,zeros,dividend} :
{1’b0,zeros,~dividend + 1’b1};
divider_copy = (!sign || !divider[WIDTH-1]) ?
{1’b0,divider,zeros} :
{1’b0,~divider + 1’b1,zeros};
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negative_output = sign &&
((divider[WIDTH-1] && !dividend[WIDTH-1])
||(!divider[WIDTH-1] && dividend[WIDTH-1]));
end
else if ( bit > 0 ) begin
diff = dividend_copy - divider_copy;
quotient_temp = quotient_temp << 1;
if( !diff[WIDTH*2-1] ) begin
dividend_copy = diff;
quotient_temp[0] = 1’d1;
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end
quotient = (!negative_output) ?
quotient_temp :
~quotient_temp + 1’b1;
divider_copy = divider_copy >> 1;
bit = bit - 1’b1;
end
end
endmodule
A.1.6
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ycrcb2rgb.v
‘timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date:
18:05:46 12/02/2014
// Design Name:
// Module Name:
ycrcb2rgb
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module ycrcb2rgb ( R, G, B, clk, rst, Y, Cr, Cb );
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output [7:0]
R, G, B;
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input clk,rst;
input[9:0] Y, Cr, Cb;
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wire [7:0] R,G,B;
reg [20:0] R_int,G_int,B_int,X_int,A_int,B1_int,B2_int,C_int;
reg [9:0] const1,const2,const3,const4,const5;
reg[9:0] Y_reg, Cr_reg, Cb_reg;
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//registering constants
always @ (posedge clk)
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begin
const1
const2
const3
const4
const5
end
=
=
=
=
=
10’b
10’b
10’b
10’b
10’b
0100101010;
0110011000;
0011010000;
0001100100;
1000000100;
//1.164
//1.596
//0.813
//0.392
//2.017
=
=
=
=
=
01.00101010
01.10011000
00.11010000
00.01100100
10.00000100
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always @ (posedge clk or posedge rst)
if (rst)
begin
Y_reg <= 0; Cr_reg <= 0; Cb_reg <= 0;
end
else
begin
Y_reg <= Y; Cr_reg <= Cr; Cb_reg <= Cb;
end
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always @ (posedge clk or posedge rst)
if (rst)
begin
A_int <= 0; B1_int <= 0; B2_int <= 0; C_int <= 0; X_int <= 0;
end
else
begin
X_int <= (const1 * (Y_reg - ’d64)) ;
A_int <= (const2 * (Cr_reg - ’d512));
B1_int <= (const3 * (Cr_reg - ’d512));
B2_int <= (const4 * (Cb_reg - ’d512));
C_int <= (const5 * (Cb_reg - ’d512));
end
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always @ (posedge clk or posedge rst)
if (rst)
begin
R_int <= 0; G_int <= 0; B_int <= 0;
end
else
begin
R_int <= X_int + A_int;
G_int <= X_int - B1_int - B2_int;
B_int <= X_int + C_int;
end
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/*always @ (posedge clk or posedge rst)
if (rst)
begin
R_int <= 0; G_int <= 0; B_int <=
end
else
begin
X_int <= (const1 * (Y_reg - ’d64))
R_int <= X_int + (const2 * (Cr_reg
G_int <= X_int - (const3 * (Cr_reg
B_int <= X_int + (const5 * (Cb_reg
end
0;
;
- ’d512));
- ’d512)) - (const4 * (Cb_reg - ’d512));
- ’d512));
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*/
/* limit
assign R
assign G
assign B
output to 0 = (R_int[20])
= (G_int[20])
= (B_int[20])
4095,
? 0 :
? 0 :
? 0 :
<0 equals o and >4095 equals 4095 */
(R_int[19:18] == 2’b0) ? R_int[17:10] : 8’b11111111;
(G_int[19:18] == 2’b0) ? G_int[17:10] : 8’b11111111;
(B_int[19:18] == 2’b0) ? B_int[17:10] : 8’b11111111;
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endmodule
A.1.7
1
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3
ntsc2zbt.v
/**
NOTE: Code borrowed heavily from Pranav Kaundinya, et. al. (2012).
*/
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module ntsc_to_bram(clk, vclk, fvh, dv, din, ntsc_addr, ntsc_data, ntsc_we, sw);
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input
clk;
// system clock
input
vclk;
// video clock from camera
input [2:0]
fvh;
input
dv;
input [29:0]
din;
input sw;
output reg [16:0] ntsc_addr;
output reg [11:0] ntsc_data;
output
ntsc_we;
// write enable for NTSC data
parameter
COL_START = 10’d0;
parameter
ROW_START = 10’d0;
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reg [9:0]
reg [9:0]
reg [29:0]
reg
reg
col = 0;
row = 0;
vdata = 0;
vwe;
old_dv;
41
24
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reg
reg
old_frame;
even_odd;
// frames are even / odd interlaced
// decode interlaced frame to this wire
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wire
wire
frame = fvh[2];
frame_edge = frame & ~old_frame;
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always @ (posedge vclk) begin//LLC1 is reference
31
old_dv <= dv;
vwe <= dv && !fvh[2] & ~old_dv; // if data valid, write it
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old_frame <= frame;
even_odd = frame_edge ? ~even_odd : even_odd;
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if (!fvh[2]) begin
col <= fvh[0] ?
(!fvh[2]
row <= fvh[1] ?
(!fvh[2]
vdata <= (dv &&
end
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COL_START :
&& !fvh[1] && dv && (col < 1024)) ? col + 1 : c
ROW_START :
&& fvh[0] && (row < 768)) ? row + 1 : row;
!fvh[2]) ? din : vdata;
end
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// synchronize with system clock
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reg [9:0] x[1:0],y[1:0];
reg [29:0] data[1:0];
reg
we[1:0];
reg
eo[1:0];
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always @(posedge clk)begin
55
{x[1],x[0]} <= {x[0],col};
{y[1],y[0]} <= {y[0],row};
{data[1],data[0]} <= {data[0],vdata};
{we[1],we[0]} <= {we[0],vwe};
{eo[1],eo[0]} <= {eo[0],even_odd};
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end
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// edge detection on write enable signal
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reg old_we;
wire we_edge = we[1] & ~old_we;
always @(posedge clk) old_we <= we[1];
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// shift each set of four bytes into a large register for the ZBT
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// compute address to store data in
wire [9:0] y_addr = {y[1][8:0], eo[1]};
wire [9:0] x_addr = x[1];
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wire [7:0] R, G, B;
ycrcb2rgb conv( R, G, B, clk, 1’b0, data[1][29:20],
data[1][19:10], data[1][9:0] );
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wire [16:0] myaddr_o = (y_addr[7:0] << 8) + (y_addr[7:0] << 6) + x_addr[8:0];
wire [16:0] myaddr;
synchronize #(.NSYNC(3), .W(17)) myaddr_sync(clk, myaddr_o, myaddr);
// update the output address and data only when four bytes ready
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wire ntsc_we_o = (x_addr < COL_START + 10’d320 && y_addr < ROW_START + 10’d240) &
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synchronize #(.NSYNC(3)) we_sync(clk, ntsc_we_o, ntsc_we);
always @(posedge clk)
if ( ntsc_we ) begin
ntsc_addr <= myaddr;
// normal and expanded modes
ntsc_data <= ~sw ? {R[7:4], G[7:4], B[7:4]} :
{x_addr[9], 3’b0, x_addr[8], 3’b0, x_addr[7], 3’b0};
end
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endmodule // ntsc_to_zbt
A.1.8
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//
//
//
//
//
//
//
//
//
//
//
video decoder.v
File:
video_decoder.v
Date:
31-Oct-05
Author: J. Castro (MIT 6.111, fall 2005)
This file contains the ntsc_decode and adv7185init modules
These modules are used to grab input NTSC video data from the RCA
phono jack on the right hand side of the 6.111 labkit (connect
the camera to the LOWER jack).
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/////////////////////////////////////////////////////////////////////////////
//
// NTSC decode - 16-bit CCIR656 decoder
// By Javier Castro
// This module takes a stream of LLC data from the adv7185
// NTSC/PAL video decoder and generates the corresponding pixels,
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// that are encoded within the stream, in YCrCb format.
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// Make sure that the adv7185 is set to run in 16-bit LLC2 mode.
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module ntsc_decode(clk, reset, tv_in_ycrcb, ycrcb, f, v, h, data_valid);
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//
//
//
//
//
//
//
clk - line-locked clock (in this case, LLC1 which runs at 27Mhz)
reset - system reset
tv_in_ycrcb - 10-bit input from chip. should map to pins [19:10]
ycrcb - 24 bit luminance and chrominance (8 bits each)
f - field: 1 indicates an even field, 0 an odd field
v - vertical sync: 1 means vertical sync
h - horizontal sync: 1 means horizontal sync
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input clk;
input reset;
input [9:0] tv_in_ycrcb; // modified for 10 bit input - should be P[19:10]
output [29:0] ycrcb;
output
f;
output
v;
output
h;
output
data_valid;
// output [4:0] state;
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parameter
parameter
parameter
parameter
parameter
parameter
parameter
parameter
parameter
parameter
parameter
parameter
parameter
parameter
parameter
parameter
parameter
SYNC_1 = 0;
SYNC_2 = 1;
SYNC_3 = 2;
SAV_f1_cb0 = 3;
SAV_f1_y0 = 4;
SAV_f1_cr1 = 5;
SAV_f1_y1 = 6;
EAV_f1 = 7;
SAV_VBI_f1 = 8;
EAV_VBI_f1 = 9;
SAV_f2_cb0 = 10;
SAV_f2_y0 = 11;
SAV_f2_cr1 = 12;
SAV_f2_y1 = 13;
EAV_f2 = 14;
SAV_VBI_f2 = 15;
EAV_VBI_f2 = 16;
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// In the start state, the module doesn’t know where
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// in the sequence of pixels, it is looking.
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// Once we determine where to start, the FSM goes through a normal
// sequence of SAV process_YCrCb EAV... repeat
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// The data stream looks as follows
// SAV_FF | SAV_00 | SAV_00 | SAV_XY | Cb0 | Y0 | Cr1 | Y1 | Cb2 | Y2 | ... | EAV sequenc
// There are two things we need to do:
//
1. Find the two SAV blocks (stands for Start Active Video perhaps?)
//
2. Decode the subsequent data
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reg
reg
reg
reg
[4:0]
[9:0]
[9:0]
[9:0]
current_state
y = 10’h000;
cr = 10’h000;
cb = 10’h000;
= 5’h00;
// luminance
// chrominance
// more chrominance
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assign
state = current_state;
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always @ (posedge clk)
begin
if (reset)
begin
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end
else
begin
// these states don’t do much except allow us to know
// whenever the synchronization code is seen, go back
// transitioning to the new state
case (current_state)
SYNC_1: current_state <= (tv_in_ycrcb == 10’h000) ?
SYNC_2: current_state <= (tv_in_ycrcb == 10’h000) ?
SYNC_3: current_state <= (tv_in_ycrcb == 10’h200) ?
(tv_in_ycrcb == 10’h274) ?
(tv_in_ycrcb == 10’h2ac) ?
(tv_in_ycrcb == 10’h2d8) ?
(tv_in_ycrcb == 10’h31c) ?
(tv_in_ycrcb == 10’h368) ?
(tv_in_ycrcb == 10’h3b0) ?
(tv_in_ycrcb == 10’h3c4) ?
where we are in the strea
to the sync_state before
SYNC_2 : SYNC_1;
SYNC_3 : SYNC_1;
SAV_f1_cb0 :
EAV_f1 :
SAV_VBI_f1 :
EAV_VBI_f1 :
SAV_f2_cb0 :
EAV_f2 :
SAV_VBI_f2 :
EAV_VBI_f2 : SYNC_1;
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SAV_f1_cb0: current_state <= (tv_in_ycrcb == 10’h3ff) ? SYNC_1 : SAV_f1_y0;
SAV_f1_y0: current_state <= (tv_in_ycrcb == 10’h3ff) ? SYNC_1 : SAV_f1_cr1;
SAV_f1_cr1: current_state <= (tv_in_ycrcb == 10’h3ff) ? SYNC_1 : SAV_f1_y1;
SAV_f1_y1: current_state <= (tv_in_ycrcb == 10’h3ff) ? SYNC_1 : SAV_f1_cb0;
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SAV_f2_cb0: current_state <= (tv_in_ycrcb == 10’h3ff) ? SYNC_1 : SAV_f2_y0;
SAV_f2_y0: current_state <= (tv_in_ycrcb == 10’h3ff) ? SYNC_1 : SAV_f2_cr1;
SAV_f2_cr1: current_state <= (tv_in_ycrcb == 10’h3ff) ? SYNC_1 : SAV_f2_y1;
SAV_f2_y1: current_state <= (tv_in_ycrcb == 10’h3ff) ? SYNC_1 : SAV_f2_cb0;
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// These states are here in the event that we want to cover these signals
// in the future. For now, they just send the state machine back to SYNC_1
EAV_f1: current_state <= SYNC_1;
SAV_VBI_f1: current_state <= SYNC_1;
EAV_VBI_f1: current_state <= SYNC_1;
EAV_f2: current_state <= SYNC_1;
SAV_VBI_f2: current_state <= SYNC_1;
EAV_VBI_f2: current_state <= SYNC_1;
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endcase
end
end // always @ (posedge clk)
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// implement our decoding mechanism
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wire y_enable;
wire cr_enable;
wire cb_enable;
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// if y is coming in, enable the register
// likewise for cr and cb
assign y_enable = (current_state == SAV_f1_y0) ||
(current_state == SAV_f1_y1) ||
(current_state == SAV_f2_y0) ||
(current_state == SAV_f2_y1);
assign cr_enable = (current_state == SAV_f1_cr1) ||
(current_state == SAV_f2_cr1);
assign cb_enable = (current_state == SAV_f1_cb0) ||
(current_state == SAV_f2_cb0);
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// f, v, and h only go high when active
assign {v,h} = (current_state == SYNC_3) ? tv_in_ycrcb[7:6] : 2’b00;
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// data is valid when we have all three values: y, cr, cb
assign data_valid = y_enable;
assign ycrcb = {y,cr,cb};
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reg
f = 0;
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always @ (posedge clk)
begin
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y <= y_enable ? tv_in_ycrcb : y;
cr <= cr_enable ? tv_in_ycrcb : cr;
cb <= cb_enable ? tv_in_ycrcb : cb;
f <= (current_state == SYNC_3) ? tv_in_ycrcb[8] : f;
end
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endmodule
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///////////////////////////////////////////////////////////////////////////////
//
// 6.111 FPGA Labkit -- ADV7185 Video Decoder Configuration Init
//
// Created:
// Author: Nathan Ickes
//
///////////////////////////////////////////////////////////////////////////////
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///////////////////////////////////////////////////////////////////////////////
// Register 0
///////////////////////////////////////////////////////////////////////////////
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‘define INPUT_SELECT
4’h0
// 0: CVBS on AIN1 (composite video in)
// 7: Y on AIN2, C on AIN5 (s-video in)
// (These are the only configurations supported by the 6.111 labkit hardware)
‘define INPUT_MODE
4’h0
// 0: Autodetect: NTSC or PAL (BGHID), w/o pedestal
// 1: Autodetect: NTSC or PAL (BGHID), w/pedestal
// 2: Autodetect: NTSC or PAL (N), w/o pedestal
// 3: Autodetect: NTSC or PAL (N), w/pedestal
// 4: NTSC w/o pedestal
// 5: NTSC w/pedestal
// 6: NTSC 4.43 w/o pedestal
// 7: NTSC 4.43 w/pedestal
// 8: PAL BGHID w/o pedestal
// 9: PAL N w/pedestal
// A: PAL M w/o pedestal
// B: PAL M w/pedestal
// C: PAL combination N
// D: PAL combination N w/pedestal
// E-F: [Not valid]
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‘define ADV7185_REGISTER_0 {‘INPUT_MODE, ‘INPUT_SELECT}
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205
///////////////////////////////////////////////////////////////////////////////
// Register 1
///////////////////////////////////////////////////////////////////////////////
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‘define
// 0:
// 1:
// 2:
// 3:
‘define
// 0:
// 1:
‘define
// 0:
// 1:
‘define
// 0:
// 1:
‘define
// 0:
// 1:
‘define
// 0:
// 1:
VIDEO_QUALITY
2’h0
Broadcast quality
TV quality
VCR quality
Surveillance quality
SQUARE_PIXEL_IN_MODE
1’b0
Normal mode
Square pixel mode
DIFFERENTIAL_INPUT
1’b0
Single-ended inputs
Differential inputs
FOUR_TIMES_SAMPLING
1’b0
Standard sampling rate
4x sampling rate (NTSC only)
BETACAM
1’b0
Standard video input
Betacam video input
AUTOMATIC_STARTUP_ENABLE
1’b1
Change of input triggers reacquire
Change of input does not trigger reacquire
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‘define ADV7185_REGISTER_1 {‘AUTOMATIC_STARTUP_ENABLE, 1’b0, ‘BETACAM, ‘FOUR_TIMES_SAMPLING,
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///////////////////////////////////////////////////////////////////////////////
// Register 2
///////////////////////////////////////////////////////////////////////////////
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‘define
// 0:
// 1:
// 2:
// 3:
// 4:
// 5:
// 6:
// 7:
‘define
// 0:
// 1:
// 2:
// 3:
Y_PEAKING_FILTER
Composite = 4.5dB, s-video
Composite = 4.5dB, s-video
Composite = 4.5dB, s-video
Composite = 1.25dB, s-video
Composite = 0.0dB, s-video
Composite = -1.25dB, s-video
Composite = -1.75dB, s-video
Composite = -3.0dB, s-video
CORING
No coring
Truncate if Y < black+8
Truncate if Y < black+16
Truncate if Y < black+32
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3’h4
= 9.25dB
= 9.25dB
= 5.75dB
= 3.3dB
= 0.0dB
= -3.0dB
= -8.0dB
= -8.0dB
2’h0
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‘define ADV7185_REGISTER_2 {3’b000, ‘CORING, ‘Y_PEAKING_FILTER}
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///////////////////////////////////////////////////////////////////////////////
// Register 3
///////////////////////////////////////////////////////////////////////////////
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‘define INTERFACE_SELECT
2’h0
// 0: Philips-compatible
// 1: Broktree API A-compatible
// 2: Broktree API B-compatible
// 3: [Not valid]
‘define OUTPUT_FORMAT
4’h0
// 0: 10-bit @ LLC, 4:2:2 CCIR656
// 1: 20-bit @ LLC, 4:2:2 CCIR656
// 2: 16-bit @ LLC, 4:2:2 CCIR656
// 3: 8-bit @ LLC, 4:2:2 CCIR656
// 4: 12-bit @ LLC, 4:1:1
// 5-F: [Not valid]
// (Note that the 6.111 labkit hardware provides only a 10-bit interface to
// the ADV7185.)
‘define TRISTATE_OUTPUT_DRIVERS
1’b0
// 0: Drivers tristated when ~OE is high
// 1: Drivers always tristated
‘define VBI_ENABLE
1’b0
// 0: Decode lines during vertical blanking interval
// 1: Decode only active video regions
275
276
‘define ADV7185_REGISTER_3 {‘VBI_ENABLE, ‘TRISTATE_OUTPUT_DRIVERS, ‘OUTPUT_FORMAT, ‘INTERFAC
277
278
279
280
///////////////////////////////////////////////////////////////////////////////
// Register 4
///////////////////////////////////////////////////////////////////////////////
281
282
283
284
285
286
287
‘define
// 0:
// 1:
‘define
// 0:
// 1:
OUTPUT_DATA_RANGE
1’b0
Output values restricted to CCIR-compliant range
Use full output range
BT656_TYPE
1’b0
BT656-3-compatible
BT656-4-compatible
288
289
‘define ADV7185_REGISTER_4 {‘BT656_TYPE, 3’b000, 3’b110, ‘OUTPUT_DATA_RANGE}
290
291
292
293
///////////////////////////////////////////////////////////////////////////////
// Register 5
///////////////////////////////////////////////////////////////////////////////
294
49
295
296
297
298
299
300
301
302
303
304
305
306
307
308
‘define
‘define
// 0:
// 1:
‘define
// 0:
// 1:
‘define
// 0:
// 1:
‘define
// 0:
// 1:
GENERAL_PURPOSE_OUTPUTS
4’b0000
GPO_0_1_ENABLE
1’b0
General purpose outputs 0 and 1 tristated
General purpose outputs 0 and 1 enabled
GPO_2_3_ENABLE
1’b0
General purpose outputs 2 and 3 tristated
General purpose outputs 2 and 3 enabled
BLANK_CHROMA_IN_VBI
1’b1
Chroma decoded and output during vertical blanking
Chroma blanked during vertical blanking
HLOCK_ENABLE
1’b0
GPO 0 is a general purpose output
GPO 0 shows HLOCK status
309
310
‘define ADV7185_REGISTER_5 {‘HLOCK_ENABLE, ‘BLANK_CHROMA_IN_VBI, ‘GPO_2_3_ENABLE, ‘GPO_0_1_E
311
312
313
314
///////////////////////////////////////////////////////////////////////////////
// Register 7
///////////////////////////////////////////////////////////////////////////////
315
316
317
318
319
320
321
322
323
324
325
326
‘define FIFO_FLAG_MARGIN
5’h10
// Sets the locations where FIFO almost-full and almost-empty flags are set
‘define FIFO_RESET
1’b0
// 0: Normal operation
// 1: Reset FIFO. This bit is automatically cleared
‘define AUTOMATIC_FIFO_RESET
1’b0
// 0: No automatic reset
// 1: FIFO is autmatically reset at the end of each video field
‘define FIFO_FLAG_SELF_TIME
1’b1
// 0: FIFO flags are synchronized to CLKIN
// 1: FIFO flags are synchronized to internal 27MHz clock
327
328
‘define ADV7185_REGISTER_7 {‘FIFO_FLAG_SELF_TIME, ‘AUTOMATIC_FIFO_RESET, ‘FIFO_RESET, ‘FIFO_
329
330
331
332
///////////////////////////////////////////////////////////////////////////////
// Register 8
///////////////////////////////////////////////////////////////////////////////
333
334
‘define INPUT_CONTRAST_ADJUST
8’h80
335
336
‘define ADV7185_REGISTER_8 {‘INPUT_CONTRAST_ADJUST}
337
338
339
340
///////////////////////////////////////////////////////////////////////////////
// Register 9
///////////////////////////////////////////////////////////////////////////////
50
341
342
‘define INPUT_SATURATION_ADJUST
8’h8C
343
344
‘define ADV7185_REGISTER_9 {‘INPUT_SATURATION_ADJUST}
345
346
347
348
///////////////////////////////////////////////////////////////////////////////
// Register A
///////////////////////////////////////////////////////////////////////////////
349
350
‘define INPUT_BRIGHTNESS_ADJUST
8’h00
351
352
‘define ADV7185_REGISTER_A {‘INPUT_BRIGHTNESS_ADJUST}
353
354
355
356
///////////////////////////////////////////////////////////////////////////////
// Register B
///////////////////////////////////////////////////////////////////////////////
357
358
‘define INPUT_HUE_ADJUST
8’h00
359
360
‘define ADV7185_REGISTER_B {‘INPUT_HUE_ADJUST}
361
362
363
364
///////////////////////////////////////////////////////////////////////////////
// Register C
///////////////////////////////////////////////////////////////////////////////
365
366
367
368
369
370
371
372
373
‘define DEFAULT_VALUE_ENABLE
// 0: Use programmed Y, Cr, and Cb values
// 1: Use default values
‘define DEFAULT_VALUE_AUTOMATIC_ENABLE
// 0: Use programmed Y, Cr, and Cb values
// 1: Use default values if lock is lost
‘define DEFAULT_Y_VALUE
// Default Y value
1’b0
1’b0
6’h0C
374
375
‘define ADV7185_REGISTER_C {‘DEFAULT_Y_VALUE, ‘DEFAULT_VALUE_AUTOMATIC_ENABLE, ‘DEFAULT_VALU
376
377
378
379
///////////////////////////////////////////////////////////////////////////////
// Register D
///////////////////////////////////////////////////////////////////////////////
380
381
382
383
384
‘define DEFAULT_CR_VALUE
4’h8
// Most-significant four bits of default Cr value
‘define DEFAULT_CB_VALUE
4’h8
// Most-significant four bits of default Cb value
385
386
‘define ADV7185_REGISTER_D {‘DEFAULT_CB_VALUE, ‘DEFAULT_CR_VALUE}
51
387
388
389
390
///////////////////////////////////////////////////////////////////////////////
// Register E
///////////////////////////////////////////////////////////////////////////////
391
392
393
394
395
396
397
398
399
400
401
‘define TEMPORAL_DECIMATION_ENABLE
// 0: Disable
// 1: Enable
‘define TEMPORAL_DECIMATION_CONTROL
// 0: Supress frames, start with even field
// 1: Supress frames, start with odd field
// 2: Supress even fields only
// 3: Supress odd fields only
‘define TEMPORAL_DECIMATION_RATE
// 0-F: Number of fields/frames to skip
1’b0
2’h0
4’h0
402
403
‘define ADV7185_REGISTER_E {1’b0, ‘TEMPORAL_DECIMATION_RATE, ‘TEMPORAL_DECIMATION_CONTROL, ‘
404
405
406
407
///////////////////////////////////////////////////////////////////////////////
// Register F
///////////////////////////////////////////////////////////////////////////////
408
409
410
411
412
413
414
415
416
417
418
419
420
421
422
423
424
425
426
427
428
429
430
431
‘define
// 0:
// 1:
// 2:
// 3:
‘define
// 0:
// 1:
‘define
// 0:
// 1:
‘define
// 0:
// 1:
‘define
// 0:
// 1:
‘define
// 0:
// 1:
‘define
// 0:
// 1:
POWER_SAVE_CONTROL
2’h0
Full operation
CVBS only
Digital only
Power save mode
POWER_DOWN_SOURCE_PRIORITY
1’b0
Power-down pin has priority
Power-down control bit has priority
POWER_DOWN_REFERENCE
1’b0
Reference is functional
Reference is powered down
POWER_DOWN_LLC_GENERATOR
1’b0
LLC generator is functional
LLC generator is powered down
POWER_DOWN_CHIP
1’b0
Chip is functional
Input pads disabled and clocks stopped
TIMING_REACQUIRE
1’b0
Normal operation
Reacquire video signal (bit will automatically reset)
RESET_CHIP
1’b0
Normal operation
Reset digital core and I2C interface (bit will automatically reset)
432
52
433
‘define ADV7185_REGISTER_F {‘RESET_CHIP, ‘TIMING_REACQUIRE, ‘POWER_DOWN_CHIP, ‘POWER_DOWN_LL
434
435
436
437
///////////////////////////////////////////////////////////////////////////////
// Register 33
///////////////////////////////////////////////////////////////////////////////
438
439
440
441
442
443
444
445
446
447
448
449
450
451
452
453
454
455
‘define PEAK_WHITE_UPDATE
// 0: Update gain once per line
// 1: Update gain once per field
‘define AVERAGE_BIRIGHTNESS_LINES
// 0: Use lines 33 to 310
// 1: Use lines 33 to 270
‘define MAXIMUM_IRE
// 0: PAL: 133, NTSC: 122
// 1: PAL: 125, NTSC: 115
// 2: PAL: 120, NTSC: 110
// 3: PAL: 115, NTSC: 105
// 4: PAL: 110, NTSC: 100
// 5: PAL: 105, NTSC: 100
// 6-7: PAL: 100, NTSC: 100
‘define COLOR_KILL
// 0: Disable color kill
// 1: Enable color kill
1’b1
1’b1
3’h0
1’b1
456
457
‘define ADV7185_REGISTER_33 {1’b1, ‘COLOR_KILL, 1’b1, ‘MAXIMUM_IRE, ‘AVERAGE_BIRIGHTNESS_LIN
458
459
460
461
462
463
464
465
466
467
468
469
470
471
472
473
474
475
476
477
478
‘define
‘define
‘define
‘define
‘define
‘define
‘define
‘define
‘define
‘define
‘define
‘define
‘define
‘define
‘define
‘define
‘define
‘define
‘define
‘define
ADV7185_REGISTER_10
ADV7185_REGISTER_11
ADV7185_REGISTER_12
ADV7185_REGISTER_13
ADV7185_REGISTER_14
ADV7185_REGISTER_15
ADV7185_REGISTER_16
ADV7185_REGISTER_17
ADV7185_REGISTER_18
ADV7185_REGISTER_19
ADV7185_REGISTER_1A
ADV7185_REGISTER_1B
ADV7185_REGISTER_1C
ADV7185_REGISTER_1D
ADV7185_REGISTER_1E
ADV7185_REGISTER_1F
ADV7185_REGISTER_20
ADV7185_REGISTER_21
ADV7185_REGISTER_22
ADV7185_REGISTER_23
8’h00
8’h00
8’h00
8’h45
8’h18
8’h60
8’h00
8’h01
8’h00
8’h10
8’h10
8’hF0
8’h16
8’h01
8’h00
8’h3D
8’hD0
8’h09
8’h8C
8’hE2
53
479
480
481
482
483
484
485
486
487
488
489
490
491
492
493
494
495
496
497
498
499
500
501
‘define
‘define
‘define
‘define
‘define
‘define
‘define
‘define
‘define
‘define
‘define
‘define
‘define
‘define
‘define
‘define
‘define
‘define
‘define
‘define
‘define
‘define
‘define
ADV7185_REGISTER_24
ADV7185_REGISTER_25
ADV7185_REGISTER_26
ADV7185_REGISTER_27
ADV7185_REGISTER_28
ADV7185_REGISTER_29
ADV7185_REGISTER_2A
ADV7185_REGISTER_2B
ADV7185_REGISTER_2C
ADV7185_REGISTER_2D
ADV7185_REGISTER_2E
ADV7185_REGISTER_2F
ADV7185_REGISTER_30
ADV7185_REGISTER_31
ADV7185_REGISTER_32
ADV7185_REGISTER_34
ADV7185_REGISTER_35
ADV7185_REGISTER_36
ADV7185_REGISTER_37
ADV7185_REGISTER_38
ADV7185_REGISTER_39
ADV7185_REGISTER_3A
ADV7185_REGISTER_3B
8’h1F
8’h07
8’hC2
8’h58
8’h3C
8’h00
8’h00
8’hA0
8’hCE
8’hF0
8’h00
8’hF0
8’h00
8’h70
8’h00
8’h0F
8’h01
8’h00
8’h00
8’h00
8’h00
8’h00
8’h00
502
503
504
‘define ADV7185_REGISTER_44 8’h41
‘define ADV7185_REGISTER_45 8’hBB
505
506
507
‘define ADV7185_REGISTER_F1 8’hEF
‘define ADV7185_REGISTER_F2 8’h80
508
509
510
511
module adv7185init (reset, clock_27mhz, source, tv_in_reset_b,
tv_in_i2c_clock, tv_in_i2c_data);
512
513
514
515
516
517
518
input reset;
input clock_27mhz;
output tv_in_reset_b; // Reset signal to ADV7185
output tv_in_i2c_clock; // I2C clock output to ADV7185
output tv_in_i2c_data; // I2C data line to ADV7185
input source; // 0: composite, 1: s-video
519
520
521
522
523
524
initial begin
$display("ADV7185 Initialization values:");
$display(" Register 0: 0x%X", ‘ADV7185_REGISTER_0);
$display(" Register 1: 0x%X", ‘ADV7185_REGISTER_1);
$display(" Register 2: 0x%X", ‘ADV7185_REGISTER_2);
54
525
526
527
528
529
530
531
532
533
534
535
536
537
538
$display("
$display("
$display("
$display("
$display("
$display("
$display("
$display("
$display("
$display("
$display("
$display("
$display("
end
Register
Register
Register
Register
Register
Register
Register
Register
Register
Register
Register
Register
Register
3:
4:
5:
7:
8:
9:
A:
B:
C:
D:
E:
F:
33:
0x%X",
0x%X",
0x%X",
0x%X",
0x%X",
0x%X",
0x%X",
0x%X",
0x%X",
0x%X",
0x%X",
0x%X",
0x%X",
‘ADV7185_REGISTER_3);
‘ADV7185_REGISTER_4);
‘ADV7185_REGISTER_5);
‘ADV7185_REGISTER_7);
‘ADV7185_REGISTER_8);
‘ADV7185_REGISTER_9);
‘ADV7185_REGISTER_A);
‘ADV7185_REGISTER_B);
‘ADV7185_REGISTER_C);
‘ADV7185_REGISTER_D);
‘ADV7185_REGISTER_E);
‘ADV7185_REGISTER_F);
‘ADV7185_REGISTER_33);
539
540
541
542
//
// Generate a 1MHz for the I2C driver (resulting I2C clock rate is 250kHz)
//
543
544
545
546
reg [7:0] clk_div_count, reset_count;
reg clock_slow;
wire reset_slow;
547
548
549
550
551
552
553
554
initial
begin
clk_div_count <= 8’h00;
// synthesis attribute init of clk_div_count is "00";
clock_slow <= 1’b0;
// synthesis attribute init of clock_slow is "0";
end
555
556
557
558
559
560
561
562
563
always @(posedge clock_27mhz)
if (clk_div_count == 26)
begin
clock_slow <= ~clock_slow;
clk_div_count <= 0;
end
else
clk_div_count <= clk_div_count+1;
564
565
566
567
568
569
always @(posedge clock_27mhz)
if (reset)
reset_count <= 100;
else
reset_count <= (reset_count==0) ? 0 : reset_count-1;
570
55
571
assign reset_slow = reset_count != 0;
572
573
574
575
//
// I2C driver
//
576
577
578
579
reg load;
reg [7:0] data;
wire ack, idle;
580
581
582
583
i2c i2c(.reset(reset_slow), .clock4x(clock_slow), .data(data), .load(load),
.ack(ack), .idle(idle), .scl(tv_in_i2c_clock),
.sda(tv_in_i2c_data));
584
585
586
587
//
// State machine
//
588
589
590
591
reg [7:0] state;
reg tv_in_reset_b;
reg old_source;
592
593
594
595
596
597
598
599
600
601
602
603
604
605
606
607
608
609
610
611
612
613
614
615
616
always @(posedge clock_slow)
if (reset_slow)
begin
state <= 0;
load <= 0;
tv_in_reset_b <= 0;
old_source <= 0;
end
else
case (state)
8’h00:
begin
// Assert reset
load <= 1’b0;
tv_in_reset_b <= 1’b0;
if (!ack)
state <= state+1;
end
8’h01:
state <= state+1;
8’h02:
begin
// Release reset
tv_in_reset_b <= 1’b1;
56
617
618
619
620
621
622
623
624
625
626
627
628
629
630
631
632
633
634
635
636
637
638
639
640
641
642
643
644
645
646
647
648
649
650
651
652
653
654
655
656
657
658
659
660
661
662
state <= state+1;
end
8’h03:
begin
// Send ADV7185 address
data <= 8’h8A;
load <= 1’b1;
if (ack)
state <= state+1;
end
8’h04:
begin
// Send subaddress of first register
data <= 8’h00;
if (ack)
state <= state+1;
end
8’h05:
begin
// Write to register 0
data <= ‘ADV7185_REGISTER_0 | {5’h00, {3{source}}};
if (ack)
state <= state+1;
end
8’h06:
begin
// Write to register 1
data <= ‘ADV7185_REGISTER_1;
if (ack)
state <= state+1;
end
8’h07:
begin
// Write to register 2
data <= ‘ADV7185_REGISTER_2;
if (ack)
state <= state+1;
end
8’h08:
begin
// Write to register 3
data <= ‘ADV7185_REGISTER_3;
if (ack)
state <= state+1;
end
8’h09:
57
663
664
665
666
667
668
669
670
671
672
673
674
675
676
677
678
679
680
681
682
683
684
685
686
687
688
689
690
691
692
693
694
695
696
697
698
699
700
701
702
703
704
705
706
707
708
begin
// Write to register 4
data <= ‘ADV7185_REGISTER_4;
if (ack)
state <= state+1;
end
8’h0A:
begin
// Write to register 5
data <= ‘ADV7185_REGISTER_5;
if (ack)
state <= state+1;
end
8’h0B:
begin
// Write to register 6
data <= 8’h00; // Reserved register, write all zeros
if (ack)
state <= state+1;
end
8’h0C:
begin
// Write to register 7
data <= ‘ADV7185_REGISTER_7;
if (ack)
state <= state+1;
end
8’h0D:
begin
// Write to register 8
data <= ‘ADV7185_REGISTER_8;
if (ack)
state <= state+1;
end
8’h0E:
begin
// Write to register 9
data <= ‘ADV7185_REGISTER_9;
if (ack)
state <= state+1;
end
8’h0F: begin
// Write to register A
data <= ‘ADV7185_REGISTER_A;
if (ack)
state <= state+1;
58
709
710
711
712
713
714
715
716
717
718
719
720
721
722
723
724
725
726
727
728
729
730
731
732
733
734
735
736
737
738
739
740
741
742
743
744
745
746
747
748
749
750
751
752
753
754
end
8’h10:
begin
// Write to register B
data <= ‘ADV7185_REGISTER_B;
if (ack)
state <= state+1;
end
8’h11:
begin
// Write to register C
data <= ‘ADV7185_REGISTER_C;
if (ack)
state <= state+1;
end
8’h12:
begin
// Write to register D
data <= ‘ADV7185_REGISTER_D;
if (ack)
state <= state+1;
end
8’h13:
begin
// Write to register E
data <= ‘ADV7185_REGISTER_E;
if (ack)
state <= state+1;
end
8’h14:
begin
// Write to register F
data <= ‘ADV7185_REGISTER_F;
if (ack)
state <= state+1;
end
8’h15:
begin
// Wait for I2C transmitter to finish
load <= 1’b0;
if (idle)
state <= state+1;
end
8’h16:
begin
// Write address
59
755
756
757
758
759
760
761
762
763
764
765
766
767
768
769
770
771
772
773
774
775
776
777
data <= 8’h8A;
load <= 1’b1;
if (ack)
state <= state+1;
end
8’h17:
begin
data <= 8’h33;
if (ack)
state <= state+1;
end
8’h18:
begin
data <= ‘ADV7185_REGISTER_33;
if (ack)
state <= state+1;
end
8’h19:
begin
load <= 1’b0;
if (idle)
state <= state+1;
end
778
779
780
781
782
783
784
785
786
787
788
789
790
791
792
793
794
795
796
797
798
799
800
8’h1A: begin
data <= 8’h8A;
load <= 1’b1;
if (ack)
state <= state+1;
end
8’h1B:
begin
data <= 8’h33;
if (ack)
state <= state+1;
end
8’h1C:
begin
load <= 1’b0;
if (idle)
state <= state+1;
end
8’h1D:
begin
load <= 1’b1;
data <= 8’h8B;
60
801
802
803
804
805
806
807
808
809
810
811
812
813
814
815
816
817
818
819
820
821
822
823
824
825
826
827
828
829
830
831
832
833
834
835
836
837
838
839
840
841
842
843
if (ack)
state <= state+1;
end
8’h1E:
begin
data <= 8’hFF;
if (ack)
state <= state+1;
end
8’h1F:
begin
load <= 1’b0;
if (idle)
state <= state+1;
end
8’h20:
begin
// Idle
if (old_source != source) state <= state+1;
old_source <= source;
end
8’h21: begin
// Send ADV7185 address
data <= 8’h8A;
load <= 1’b1;
if (ack) state <= state+1;
end
8’h22: begin
// Send subaddress of register 0
data <= 8’h00;
if (ack) state <= state+1;
end
8’h23: begin
// Write to register 0
data <= ‘ADV7185_REGISTER_0 | {5’h00, {3{source}}};
if (ack) state <= state+1;
end
8’h24: begin
// Wait for I2C transmitter to finish
load <= 1’b0;
if (idle) state <= 8’h20;
end
endcase
844
845
endmodule
846
61
847
// i2c module for use with the ADV7185
848
849
module i2c (reset, clock4x, data, load, idle, ack, scl, sda);
850
851
852
853
854
855
856
857
858
input reset;
input clock4x;
input [7:0] data;
input load;
output ack;
output idle;
output scl;
output sda;
859
860
861
862
863
reg
reg
reg
reg
[7:0] ldata;
ack, idle;
scl;
sdai;
864
865
reg [7:0] state;
866
867
assign sda = sdai ? 1’bZ : 1’b0;
868
869
870
871
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887
888
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890
891
892
always @(posedge clock4x)
if (reset)
begin
state <= 0;
ack <= 0;
end
else
case (state)
8’h00: // idle
begin
scl <= 1’b1;
sdai <= 1’b1;
ack <= 1’b0;
idle <= 1’b1;
if (load)
begin
ldata <= data;
ack <= 1’b1;
state <= state+1;
end
end
8’h01: // Start
begin
ack <= 1’b0;
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895
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900
901
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931
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936
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938
idle <= 1’b0;
sdai <= 1’b0;
state <= state+1;
end
8’h02:
begin
scl <= 1’b0;
state <= state+1;
end
8’h03: // Send bit 7
begin
ack <= 1’b0;
sdai <= ldata[7];
state <= state+1;
end
8’h04:
begin
scl <= 1’b1;
state <= state+1;
end
8’h05:
begin
state <= state+1;
end
8’h06:
begin
scl <= 1’b0;
state <= state+1;
end
8’h07:
begin
sdai <= ldata[6];
state <= state+1;
end
8’h08:
begin
scl <= 1’b1;
state <= state+1;
end
8’h09:
begin
state <= state+1;
end
8’h0A:
begin
scl <= 1’b0;
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983
984
state <= state+1;
end
8’h0B:
begin
sdai <= ldata[5];
state <= state+1;
end
8’h0C:
begin
scl <= 1’b1;
state <= state+1;
end
8’h0D:
begin
state <= state+1;
end
8’h0E:
begin
scl <= 1’b0;
state <= state+1;
end
8’h0F:
begin
sdai <= ldata[4];
state <= state+1;
end
8’h10:
begin
scl <= 1’b1;
state <= state+1;
end
8’h11:
begin
state <= state+1;
end
8’h12:
begin
scl <= 1’b0;
state <= state+1;
end
8’h13:
begin
sdai <= ldata[3];
state <= state+1;
end
8’h14:
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1021
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1024
1025
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1030
begin
scl <= 1’b1;
state <= state+1;
end
8’h15:
begin
state <= state+1;
end
8’h16:
begin
scl <= 1’b0;
state <= state+1;
end
8’h17:
begin
sdai <= ldata[2];
state <= state+1;
end
8’h18:
begin
scl <= 1’b1;
state <= state+1;
end
8’h19:
begin
state <= state+1;
end
8’h1A:
begin
scl <= 1’b0;
state <= state+1;
end
8’h1B:
begin
sdai <= ldata[1];
state <= state+1;
end
8’h1C:
begin
scl <= 1’b1;
state <= state+1;
end
8’h1D:
begin
state <= state+1;
end
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1038
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1074
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8’h1E:
begin
scl <= 1’b0;
state <= state+1;
end
8’h1F:
begin
sdai <= ldata[0];
state <= state+1;
end
8’h20:
begin
scl <= 1’b1;
state <= state+1;
end
8’h21:
begin
state <= state+1;
end
8’h22:
begin
scl <= 1’b0;
state <= state+1;
end
8’h23: // Acknowledge bit
begin
state <= state+1;
end
8’h24:
begin
scl <= 1’b1;
state <= state+1;
end
8’h25:
begin
state <= state+1;
end
8’h26:
begin
scl <= 1’b0;
if (load)
begin
ldata <= data;
ack <= 1’b1;
state <= 3;
end
66
else
state <= state+1;
end
8’h27:
begin
sdai <= 1’b0;
state <= state+1;
end
8’h28:
begin
scl <= 1’b1;
state <= state+1;
end
8’h29:
begin
sdai <= 1’b1;
state <= 0;
end
endcase
1077
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1097
endmodule
1098
1099
A.1.9
1
2
3
4
flash int.v
//flash interface
module flash_int(reset, clock, op, address, wdata, rdata, busy, flash_data,
flash_address, flash_ce_b, flash_oe_b, flash_we_b,
flash_reset_b, flash_sts, flash_byte_b);
5
6
7
8
parameter access_cycles = 5;
parameter reset_assert_cycles = 1000;
parameter reset_recovery_cycles = 30;
9
10
11
12
13
14
15
16
17
18
19
20
input reset, clock; // Reset and clock for the flash interface
input [1:0] op; // Flash operation select (read, write, idle)
input [22:0] address;
input [15:0] wdata;
output [15:0] rdata;
output busy;
inout [15:0] flash_data;
output [23:0] flash_address;
output flash_ce_b, flash_oe_b, flash_we_b;
output flash_reset_b, flash_byte_b;
input flash_sts;
67
21
22
23
24
25
26
27
28
reg
reg
reg
reg
reg
reg
reg
[1:0] lop;
[15:0] rdata;
busy;
[15:0] flash_wdata;
flash_ddata;
[23:0] flash_address;
flash_oe_b, flash_we_b, flash_reset_b;
29
30
31
assign flash_ce_b = flash_oe_b && flash_we_b;
assign flash_byte_b = 1; // 1 = 16-bit mode (A0 ignored)
32
33
assign flash_data = flash_ddata ? flash_wdata : 16’hZ;
34
35
36
initial
flash_reset_b <= 1’b1;
37
38
reg [9:0] state;
39
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41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
always @(posedge clock)
if (reset)
begin
state <= 0;
flash_reset_b <= 0;
flash_we_b <= 1;
flash_oe_b <= 1;
flash_ddata <= 0;
busy <= 1;
end
else if (flash_reset_b == 0)
if (state == reset_assert_cycles)
begin
flash_reset_b <= 1;
state <= 1023-reset_recovery_cycles;
end
else
state <= state+1;
else if ((state == 0) && !busy)
// The flash chip and this state machine are both idle. Latch the user’s
// address and write data inputs. Deassert OE and WE, and stop driving
// the data buss ourselves. If a flash operation (read or write) is
// requested, move to the next state.
begin
flash_address <= {address, 1’b0};
flash_we_b <= 1;
flash_oe_b <= 1;
68
67
68
69
70
71
72
73
74
75
76
77
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98
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102
103
104
105
106
107
108
109
110
111
112
//
//
//
//
flash_ddata <= 0;
flash_wdata <= wdata;
lop <= op;
if (op != ‘FLASHOP_IDLE)
begin
busy <= 1;
state <= state+1;
end
else
busy <= 0;
end
else if ((state==0) && flash_sts)
busy <= 0;
else if (state == 1)
The first stage of a flash operation. The address bus is already set,
so, if this is a read, we assert OE. For a write, we start driving
the user’s data onto the flash databus (the value was latched in the
previous state.
begin
if (lop == ‘FLASHOP_WRITE)
flash_ddata <= 1;
else if (lop == ‘FLASHOP_READ)
flash_oe_b <= 0;
state <= state+1;
end
else if (state == 2)
// The second stage of a flash operation. Nothing to do for a read. For
// a write, we assert WE.
begin
if (lop == ‘FLASHOP_WRITE)
flash_we_b <= 0;
state <= state+1;
end
else if (state == access_cycles+1)
// The third stage of a flash operation. For a read, we latch the data
// from the flash chip. For a write, we deassert WE.
begin
if (lop == ‘FLASHOP_WRITE)
flash_we_b <= 1;
if (lop == ‘FLASHOP_READ)
rdata <= flash_data;
state <= 0;
end
else
begin
if (!flash_sts)
69
busy <= 1;
state <= state+1;
113
114
end
115
116
117
endmodule
A.1.10
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
flash manager.v
//manages all the stuff needed to read and write to the flash ROM
module flash_manager(
clock, reset,
dots,
writemode,
wdata,
dowrite,
raddr,
frdata,
doread,
busy,
flash_data,
flash_address,
flash_ce_b,
flash_oe_b,
flash_we_b,
flash_reset_b,
flash_sts,
flash_byte_b,
fsmstate);
21
22
23
24
25
26
27
28
29
30
31
32
input reset, clock;
output [639:0] dots;
input writemode;
input [15:0] wdata;
input dowrite;
input [22:0] raddr;
output[15:0] frdata;
reg[15:0]
rdata;
input doread;
output busy;
reg busy;
//clock and reset
//outputs to dot-matrix to help debug flash, not
//if true then we’re in write mode, else we’
//data to be written
//putting this high tells the manager
//address to read from
//data being read
//putting this high tells the manager t
//and an output to tell folks we’re stil
33
34
35
36
37
38
inout [15:0] flash_data;
output [23:0] flash_address;
output flash_ce_b, flash_oe_b, flash_we_b;
output flash_reset_b, flash_byte_b;
input flash_sts;
70
//direct passthrough
39
40
41
42
43
44
wire flash_busy;
wire[15:0] fwdata;
wire[15:0] frdata;
wire[22:0] address;
wire [1:0] op;
//except these, which are internal to the interface
45
46
47
reg [1:0] mode;
wire fsm_busy;
48
49
reg[2:0] state;
//210
50
51
52
53
output[11:0] fsmstate;
wire [7:0] fsmstateinv;
assign fsmstate = {state,flash_busy,fsm_busy,fsmstateinv[4:0],mode};
//for de
54
55
56
57
58
//this guy
flash_int flash(reset, clock, op, address, fwdata, frdata, flash_busy, flash_data,
//and this
test_fsm fsm (reset, clock, op, address, fwdata, frdata, flash_busy, dots, mode,
t
f
g
f
59
60
61
62
63
parameter
parameter
parameter
parameter
MODE_IDLE
MODE_INIT
MODE_WRITE = 2;
MODE_READ
= 0;
= 1;
parameter
parameter
parameter
parameter
parameter
parameter
parameter
HOME
= 3’d0;
MEM_INIT
= 3’d1;
MEM_WAIT
= 3’d2;
WRITE_READY= 3’d3;
WRITE_WAIT
= 3’d4;
READ_READY
= 3’d5;
READ_WAIT
= 3’d6;
= 3;
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
always @ (posedge clock)
if(reset)
begin
busy <= 1;
state <= HOME;
mode <= MODE_IDLE;
end
else begin
case(state)
HOME://0
if(!fsm_busy)
begin
71
//we always start he
busy <= 0;
if(writemode)
begin
85
86
87
busy <= 1;
state <= MEM_INIT;
88
89
end
90
else
91
begin
92
busy <= 1;
state <= READ_READY;
93
94
end
95
end
96
else
97
mode <= MODE_IDLE;
98
99
100
101
MEM_INIT://1
begin
busy <= 1;
mode <= MODE_INIT;
if(fsm_busy)
state <= MEM_WAIT;
102
103
104
105
end
106
107
108
109
110
MEM_WAIT://2
if(!fsm_busy)
begin
busy <= 0;
state<= WRITE_READY;
111
112
end
113
else
114
mode <= MODE_IDLE;
115
116
117
118
119
WRITE_READY://3
if(dowrite)
begin
//wai
busy <= 1;
mode <= MODE_WRITE;
120
121
end
else if(busy)
state <= WRITE_WAIT;
else if(!writemode)
state <= READ_READY;
122
123
124
125
126
127
128
129
130
WRITE_WAIT://4
if(!fsm_busy)
begin
72
//waiting for
busy <= 0;
state <= WRITE_READY;
131
132
end
133
else
134
mode <= MODE_IDLE;
135
136
READ_READY://5
if(doread)
begin
137
138
139
//ready to rea
busy <= 1;
mode <= MODE_READ;
if(busy)
state <= READ_WAIT;
140
141
142
143
//le
end
144
else
145
busy <= 0;
146
147
READ_WAIT://6
if(!fsm_busy)
begin
148
149
150
//waiting for flash to
busy <= 0;
state <= READ_READY;
151
152
end
153
else
154
mode <= MODE_IDLE;
155
156
default: begin
state <= 3’d7;
end
157
158
159
endcase
160
161
162
1
2
3
4
5
6
7
8
9
10
11
end
endmodule
A.1.11
test fsm.v
‘define
‘define
‘define
‘define
‘define
‘define
‘define
‘define
‘define
‘define
‘define
STATUS_RESET
STATUS_READ_ID
STATUS_CLEAR_LOCKS
STATUS_ERASING
STATUS_WRITING
STATUS_READING
STATUS_SUCCESS
STATUS_BAD_MANUFACTURER
STATUS_BAD_SIZE
STATUS_LOCK_BIT_ERROR
STATUS_ERASE_BLOCK_ERROR
4’h0
4’h1
4’h2
4’h3
4’h4
4’h5
4’h6
4’h7
4’h8
4’h9
4’hA
73
//should never happen...
12
13
‘define STATUS_WRITE_ERROR
‘define STATUS_READ_WRONG_DATA
4’hB
4’hC
14
15
16
17
18
‘define
‘define
‘define
‘define
NUM_BLOCKS 128
BLOCK_SIZE 64*1024
LAST_BLOCK_ADDRESS ((‘NUM_BLOCKS-1)*‘BLOCK_SIZE)
LAST_ADDRESS (‘NUM_BLOCKS*‘BLOCK_SIZE-1)
19
20
21
22
‘define FLASHOP_IDLE 2’b00
‘define FLASHOP_READ 2’b01
‘define FLASHOP_WRITE 2’b10
23
24
25
26
27
28
29
30
31
32
33
34
35
36
module test_fsm (reset, clock, fop, faddress, fwdata, frdata, fbusy, dots, mode, busy, datai
input reset, clock;
output [1:0] fop;
output [22:0] faddress;
output [15:0] fwdata;
input [15:0] frdata;
input fbusy;
output [639:0] dots;
input [1:0] mode;
output busy;
input [15:0] datain;
input [22:0] addrin;
output state;
37
38
39
40
41
42
43
reg
reg
reg
reg
reg
reg
[1:0] fop;
[22:0] faddress;
[15:0] fwdata;
[639:0] dots;
busy;
[15:0] data_to_store;
44
45
46
47
48
49
////////////////////////////////////////////////////////////////////////////
//
// State Machine
//
////////////////////////////////////////////////////////////////////////////
50
51
52
reg [7:0] state;
reg [3:0] status;
53
54
55
56
57
parameter
parameter
parameter
parameter
MODE_IDLE
MODE_INIT
MODE_WRITE = 2;
MODE_READ
= 0;
= 1;
= 3;
74
58
59
parameter MAX_ADDRESS = 23’h200000;
60
61
parameter HOME = 8’h12;
62
63
64
65
66
67
68
69
70
71
72
73
74
always @(posedge clock)
if (reset)
begin
state <= HOME;
status <= ‘STATUS_RESET;
faddress <= 0;
fop <= ‘FLASHOP_IDLE;
busy <= 1;
end
else if (!fbusy && (fop == ‘FLASHOP_IDLE))
case (state)
75
76
77
78
79
80
81
HOME://12
case(mode)
MODE_INIT: begin
state <= 8’h00;
busy <= 1;
end
82
MODE_WRITE: begin
state <= 8’h0C;
busy <= 1;
end
83
84
85
86
87
MODE_READ: begin
busy <= 1;
if(status == ‘STATUS_READING)
state <= 8’h11;
else
state <= 8’h10;
end
88
89
90
91
92
93
94
95
default: begin
state <= HOME;
busy <= 0;
end
96
97
98
99
100
endcase
101
102
103
//////////////////////////////////////////////////////////////////////
// Wipe It
75
104
105
106
107
108
109
110
111
112
113
//////////////////////////////////////////////////////////////////////
8’h00:
begin
// Issue "read id codes" command
status <= ‘STATUS_READ_ID;
faddress <= 0;
fwdata <= 16’h0090;
fop <= ‘FLASHOP_WRITE;
state <= state+1;
end
114
115
116
117
118
119
120
121
8’h01:
begin
// Read manufacturer code
faddress <= 0;
fop <= ‘FLASHOP_READ;
state <= state+1;
end
122
123
124
125
126
127
128
129
130
131
132
8’h02:
if (frdata != 16’h0089) // 16’h0089 = Intel
status <= ‘STATUS_BAD_MANUFACTURER;
else
begin
// Read the device size code
faddress <= 1;
fop <= ‘FLASHOP_READ;
state <= state+1;
end
133
134
135
136
137
138
139
140
141
142
143
8’h03:
if (frdata != 16’h0018) // 16’h0018 = 128Mbit
status <= ‘STATUS_BAD_SIZE;
else
begin
faddress <= 0;
fwdata <= 16’hFF;
fop <= ‘FLASHOP_WRITE;
state <= state+1;
end
144
145
146
147
148
149
8’h04:
begin
// Issue "clear lock bits" command
status <= ‘STATUS_CLEAR_LOCKS;
faddress <= 0;
76
150
151
152
153
fwdata <= 16’h60;
fop <= ‘FLASHOP_WRITE;
state <= state+1;
end
154
155
156
157
158
159
160
161
162
8’h05:
begin
// Issue "confirm clear lock bits" command
faddress <= 0;
fwdata <= 16’hD0;
fop <= ‘FLASHOP_WRITE;
state <= state+1;
end
163
164
165
166
167
168
169
170
8’h06:
begin
// Read status
faddress <= 0;
fop <= ‘FLASHOP_READ;
state <= state+1;
end
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
8’h07:
if (frdata[7] == 1) // Done clearing lock bits
if (frdata[6:1] == 0) // No errors
begin
faddress <= 0;
fop <= ‘FLASHOP_IDLE;
state <= state+1;
end
else
status <= ‘STATUS_LOCK_BIT_ERROR;
else // Still busy, reread status register
begin
faddress <= 0;
fop <= ‘FLASHOP_READ;
end
187
188
189
190
191
192
193
194
195
//////////////////////////////////////////////////////////////////////
// Block Erase Sequence
//////////////////////////////////////////////////////////////////////
8’h08:
begin
status <= ‘STATUS_ERASING;
fwdata <= 16’h20; // Issue "erase block" command
fop <= ‘FLASHOP_WRITE;
77
196
197
state <= state+1;
end
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
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214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
8’h09:
begin
fwdata <= 16’hD0; // Issue "confirm erase" command
fop <= ‘FLASHOP_WRITE;
state <= state+1;
end
8’h0A:
begin
fop <= ‘FLASHOP_READ;
state <= state+1;
end
8’h0B:
if (frdata[7] == 1) // Done erasing block
if (frdata[6:1] == 0) // No errors
if (faddress != MAX_ADDRESS) // ‘LAST_BLOCK_ADDRESS)
begin
faddress <= faddress+‘BLOCK_SIZE;
fop <= ‘FLASHOP_IDLE;
state <= state-3;
end
else
begin
faddress <= 0;
fop <= ‘FLASHOP_IDLE;
state <= HOME;
//done erasing, go home
end
else // Erase error detected
status <= ‘STATUS_ERASE_BLOCK_ERROR;
else // Still busy
fop <= ‘FLASHOP_READ;
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//////////////////////////////////////////////////////////////////////
// Write Mode
//////////////////////////////////////////////////////////////////////
8’h0C:
begin
data_to_store <= datain;
status <= ‘STATUS_WRITING;
fwdata <= 16’h40; // Issue "setup write" command
fop <= ‘FLASHOP_WRITE;
state <= state+1;
end
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8’h0D:
begin
fwdata <= data_to_store; // Finish write
fop <= ‘FLASHOP_WRITE;
state <= state+1;
end
8’h0E:
begin
// Read status register
fop <= ‘FLASHOP_READ;
state <= state+1;
end
8’h0F:
if (frdata[7] == 1) // Done writing
if (frdata[6:1] == 0) // No errors
if (faddress != 23’h7FFFFF) // ‘LAST_ADDRESS)
begin
faddress <= faddress+1;
fop <= ‘FLASHOP_IDLE;
state <= HOME;
end
else
status <= ‘STATUS_WRITE_ERROR;
else // Write error detected
status <= ‘STATUS_WRITE_ERROR;
else // Still busy
fop <= ‘FLASHOP_READ;
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//////////////////////////////////////////////////////////////////////
// Read Mode INIT
//////////////////////////////////////////////////////////////////////
8’h10:
begin
status <= ‘STATUS_READING;
fwdata <= 16’hFF; // Issue "read array" command
fop <= ‘FLASHOP_WRITE;
faddress <= 0;
state <= state+1;
end
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//////////////////////////////////////////////////////////////////////
// Read Mode
//////////////////////////////////////////////////////////////////////
8’h11:
begin
faddress <= addrin;
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fop <= ‘FLASHOP_READ;
state <= HOME;
end
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default:
begin
status <= ‘STATUS_BAD_MANUFACTURER;
faddress <= 0;
state <= HOME;
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end
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endcase
else
fop <= ‘FLASHOP_IDLE;
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function [39:0] nib2char;
input [3:0] nib;
begin
case (nib)
4’h0: nib2char = 40’b00111110_01010001_01001001_01000101_00111110;
4’h1: nib2char = 40’b00000000_01000010_01111111_01000000_00000000;
4’h2: nib2char = 40’b01100010_01010001_01001001_01001001_01000110;
4’h3: nib2char = 40’b00100010_01000001_01001001_01001001_00110110;
4’h4: nib2char = 40’b00011000_00010100_00010010_01111111_00010000;
4’h5: nib2char = 40’b00100111_01000101_01000101_01000101_00111001;
4’h6: nib2char = 40’b00111100_01001010_01001001_01001001_00110000;
4’h7: nib2char = 40’b00000001_01110001_00001001_00000101_00000011;
4’h8: nib2char = 40’b00110110_01001001_01001001_01001001_00110110;
4’h9: nib2char = 40’b00000110_01001001_01001001_00101001_00011110;
4’hA: nib2char = 40’b01111110_00001001_00001001_00001001_01111110;
4’hB: nib2char = 40’b01111111_01001001_01001001_01001001_00110110;
4’hC: nib2char = 40’b00111110_01000001_01000001_01000001_00100010;
4’hD: nib2char = 40’b01111111_01000001_01000001_01000001_00111110;
4’hE: nib2char = 40’b01111111_01001001_01001001_01001001_01000001;
4’hF: nib2char = 40’b01111111_00001001_00001001_00001001_00000001;
endcase
end
endfunction
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wire [159:0] data_dots;
assign data_dots = {nib2char(frdata[15:12]), nib2char(frdata[11:8]),
nib2char(frdata[7:4]), nib2char(frdata[3:0])};
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wire [239:0] address_dots;
assign address_dots = {nib2char({ 1’b0, faddress[22:20]}),
nib2char(faddress[19:16]),
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nib2char(faddress[15:12]),
nib2char(faddress[11:8]),
nib2char(faddress[7:4]),
nib2char(faddress[3:0])};
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always @(status or address_dots or data_dots)
case (status)
‘STATUS_RESET:
dots <= {40’b01111111_00001001_00011001_00101001_01000110, //
40’b01111111_01001001_01001001_01001001_01000001, //
40’b00100110_01001001_01001001_01001001_00110010, //
40’b01111111_01001001_01001001_01001001_01000001, //
40’b00000001_00000001_01111111_00000001_00000001, //
40’b00000000_00000000_00000000_00000000_00000000, //
40’b00000000_00000000_00000000_00000000_00000000, //
40’b00000000_00000000_00000000_00000000_00000000, //
40’b00000000_00000000_00000000_00000000_00000000, //
40’b00000000_00000000_00000000_00000000_00000000, //
40’b00001000_00001000_00001000_00001000_00001000, //
40’b00001000_00001000_00001000_00001000_00001000, //
40’b00001000_00001000_00001000_00001000_00001000, //
40’b00001000_00001000_00001000_00001000_00001000, //
40’b00001000_00001000_00001000_00001000_00001000, //
40’b00001000_00001000_00001000_00001000_00001000};//
‘STATUS_READ_ID:
dots <= {40’b01111111_00001001_00011001_00101001_01000110, //
40’b01111111_01001001_01001001_01001001_01000001, //
40’b01111110_00001001_00001001_00001001_01111110, //
40’b01111111_01000001_01000001_01000001_00111110, //
40’b00000000_00000000_00000000_00000000_00000000, //
40’b00000000_01000001_01111111_01000001_00000000, //
40’b01111111_01000001_01000001_01000001_00111110, //
40’b00000000_00000000_00000000_00000000_00000000, //
40’b00000000_00000000_00000000_00000000_00000000, //
40’b00000000_00000000_00000000_00000000_00000000, //
address_dots};
‘STATUS_CLEAR_LOCKS:
dots <= {40’b00111110_01000001_01000001_01000001_00100010, //
40’b01111111_01000000_01000000_01000000_01000000, //
40’b01111111_00001001_00011001_00101001_01000110, //
40’b00000000_00000000_00000000_00000000_00000000, //
40’b01111111_01000000_01000000_01000000_01000000, //
40’b00111110_01000001_01000001_01000001_00111110, //
40’b00111110_01000001_01000001_01000001_00100010, //
40’b01111111_00001000_00010100_00100010_01000001, //
40’b00100110_01001001_01001001_01001001_00110010, //
81
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40’b00000000_00000000_00000000_00000000_00000000,
address_dots};
‘STATUS_ERASING:
dots <= {40’b01111111_01001001_01001001_01001001_01000001,
40’b01111111_00001001_00011001_00101001_01000110,
40’b01111110_00001001_00001001_00001001_01111110,
40’b00100110_01001001_01001001_01001001_00110010,
40’b00000000_01000001_01111111_01000001_00000000,
40’b01111111_00000010_00000100_00001000_01111111,
40’b00111110_01000001_01001001_01001001_00111010,
40’b00000000_00000000_00000000_00000000_00000000,
40’b00000000_00000000_00000000_00000000_00000000,
40’b00000000_00000000_00000000_00000000_00000000,
address_dots};
‘STATUS_WRITING:
dots <= {40’b01111111_00100000_00011000_00100000_01111111,
40’b01111111_00001001_00011001_00101001_01000110,
40’b00000000_01000001_01111111_01000001_00000000,
40’b00000001_00000001_01111111_00000001_00000001,
40’b00000000_01000001_01111111_01000001_00000000,
40’b01111111_00000010_00000100_00001000_01111111,
40’b00111110_01000001_01001001_01001001_00111010,
40’b00000000_00000000_00000000_00000000_00000000,
40’b00000000_00000000_00000000_00000000_00000000,
40’b00000000_00000000_00000000_00000000_00000000,
address_dots};
‘STATUS_READING:
dots <= {40’b01111111_00001001_00011001_00101001_01000110,
40’b01111111_01001001_01001001_01001001_01000001,
40’b01111110_00001001_00001001_00001001_01111110,
40’b01111111_01000001_01000001_01000001_00111110,
40’b00000000_01000001_01111111_01000001_00000000,
40’b01111111_00000010_00000100_00001000_01111111,
40’b00111110_01000001_01001001_01001001_00111010,
40’b00000000_00000000_00000000_00000000_00000000,
40’b00000000_00000000_00000000_00000000_00000000,
40’b00000000_00000000_00000000_00000000_00000000,
address_dots};
‘STATUS_SUCCESS:
dots <= {40’b00000000_00000000_00000000_00000000_00000000,
40’b00101010_00011100_01111111_00011100_00101010,
40’b00101010_00011100_01111111_00011100_00101010,
40’b00101010_00011100_01111111_00011100_00101010,
40’b00000000_00000000_00000000_00000000_00000000,
40’b01111111_00001001_00001001_00001001_00000110,
40’b01111110_00001001_00001001_00001001_01111110,
82
//
//
//
//
//
//
//
//
//
//
//
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G
//
//
//
//
//
//
//
//
//
//
W
R
I
T
I
N
G
//
//
//
//
//
//
//
//
//
//
R
E
A
D
I
N
G
//
//
//
//
//
//
//
*
*
*
P
A
426
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40’b00100110_01001001_01001001_01001001_00110010, //
40’b00100110_01001001_01001001_01001001_00110010, //
40’b01111111_01001001_01001001_01001001_01000001, //
40’b01111111_01000001_01000001_01000001_00111110, //
40’b00000000_00000000_00000000_00000000_00000000, //
40’b00101010_00011100_01111111_00011100_00101010, //
40’b00101010_00011100_01111111_00011100_00101010, //
40’b00101010_00011100_01111111_00011100_00101010, //
40’b00000000_00000000_00000000_00000000_00000000};//
‘STATUS_BAD_MANUFACTURER:
dots <= {40’b01111111_01001001_01001001_01001001_01000001, //
40’b01111111_00001001_00011001_00101001_01000110, //
40’b01111111_00001001_00011001_00101001_01000110, //
40’b00000000_00110110_00110110_00000000_00000000, //
40’b00000000_00000000_00000000_00000000_00000000, //
40’b01111111_00000010_00001100_00000010_01111111, //
40’b01111110_00001001_00001001_00001001_01111110, //
40’b01111111_00000010_00000100_00001000_01111111, //
40’b01111111_00001001_00001001_00001001_00000001, //
40’b01111111_00001001_00001001_00001001_00000001, //
40’b00000000_00000000_00000000_00000000_00000000, //
40’b00000000_00000000_00000000_00000000_00000000, //
data_dots};
‘STATUS_BAD_SIZE:
dots <= {40’b01111111_01001001_01001001_01001001_01000001, //
40’b01111111_00001001_00011001_00101001_01000110, //
40’b01111111_00001001_00011001_00101001_01000110, //
40’b00000000_00110110_00110110_00000000_00000000, //
40’b00000000_00000000_00000000_00000000_00000000, //
40’b00100110_01001001_01001001_01001001_00110010, //
40’b00000000_01000001_01111111_01000001_00000000, //
40’b01100001_01010001_01001001_01000101_01000011, //
40’b01111111_01001001_01001001_01001001_01000001, //
40’b00000000_00000000_00000000_00000000_00000000,
40’b00000000_00000000_00000000_00000000_00000000,
40’b00000000_00000000_00000000_00000000_00000000,
data_dots};
‘STATUS_LOCK_BIT_ERROR:
dots <= {40’b01111111_01001001_01001001_01001001_01000001, //
40’b01111111_00001001_00011001_00101001_01000110, //
40’b01111111_00001001_00011001_00101001_01000110, //
40’b00000000_00110110_00110110_00000000_00000000, //
40’b00000000_00000000_00000000_00000000_00000000, //
40’b01111111_01000000_01000000_01000000_01000000, //
40’b00111110_01000001_01000001_01000001_00111110, //
40’b00111110_01000001_01000001_01000001_00100010, //
83
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D
*
*
*
E
R
R
:
M
A
N
U
F
E
R
R
:
S
I
Z
E
E
R
R
:
L
O
C
472
473
474
475
476
477
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479
480
481
482
483
484
485
486
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488
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40’b01111111_00001000_00010100_00100010_01000001, // K
40’b00100110_01001001_01001001_01001001_00110010, // S
40’b00000000_00000000_00000000_00000000_00000000,
40’b00000000_00000000_00000000_00000000_00000000,
data_dots};
‘STATUS_ERASE_BLOCK_ERROR:
dots <= {40’b01111111_01001001_01001001_01001001_01000001, // E
40’b01111111_00001001_00011001_00101001_01000110, // R
40’b01111111_00001001_00011001_00101001_01000110, // R
40’b00000000_00110110_00110110_00000000_00000000, // :
40’b00000000_00000000_00000000_00000000_00000000, //
40’b01111111_01001001_01001001_01001001_01000001, // E
40’b01111111_00001001_00011001_00101001_01000110, // R
40’b01111110_00001001_00001001_00001001_01111110, // A
40’b00100110_01001001_01001001_01001001_00110010, // S
40’b01111111_01001001_01001001_01001001_01000001, // E
40’b00000000_00000000_00000000_00000000_00000000,
40’b00000000_00000000_00000000_00000000_00000000,
data_dots};
‘STATUS_WRITE_ERROR:
dots <= {40’b01111111_01001001_01001001_01001001_01000001, // E
40’b01111111_00001001_00011001_00101001_01000110, // R
40’b01111111_00001001_00011001_00101001_01000110, // R
40’b00000000_00110110_00110110_00000000_00000000, // :
40’b00000000_00000000_00000000_00000000_00000000, //
40’b01111111_00100000_00011000_00100000_01111111, // W
40’b01111111_00001001_00011001_00101001_01000110, // R
40’b00000000_01000001_01111111_01000001_00000000, // I
40’b00000001_00000001_01111111_00000001_00000001, // T
40’b01111111_01001001_01001001_01001001_01000001, // E
40’b00000000_00000000_00000000_00000000_00000000,
40’b00000000_00000000_00000000_00000000_00000000,
data_dots};
‘STATUS_READ_WRONG_DATA:
dots <= {40’b01111111_01001001_01001001_01001001_01000001, // E
40’b01111111_00001001_00011001_00101001_01000110, // R
40’b01111111_00001001_00011001_00101001_01000110, // R
40’b00000000_00110110_00110110_00000000_00000000, // :
40’b00000000_00000000_00000000_00000000_00000000,
address_dots,
40’b00000000_00000000_00000000_00000000_00000000,
data_dots};
default:
dots <= {16{40’b01010101_00101010_01010101_00101010_01010101}};
endcase
517
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518
endmodule
A.1.12
1
2
3
4
5
6
7
usb input.v
//reads data and puts it on out
module usb_input(clk,reset,data,rd,rxf,out,newout,hold,state);
input clk, reset;
//clock and reset
input [7:0] data;
//the data pins from the USB fifo
input rxf;
//the rxf pin from the USB fifo
output rd;
//the rd pin from the USB fifo
reg rd;
8
9
10
11
12
13
output[7:0] out;
reg[7:0] out;
output newout;
reg newout;
input hold;
//this is where data goes when it has been read from the fif
//when this is high, out contains a new chunk of data
//as long as hold is high, this module sits
//still module and will not accept new data
14
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17
output state;
reg[3:0] state;
//for debugging purposes
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parameter
parameter
parameter
parameter
parameter
parameter
parameter
parameter
parameter
parameter
parameter
parameter
parameter
parameter
parameter
parameter
RESET
= 0;
WAIT
WAIT2
WAIT3
DATA_COMING
= 4;
DATA_COMING_2
= 5;
DATA_COMING_3
= 6;
DATA_COMING_4
= 7;
DATA_COMING_5
= 8;
DATA_HERE
= 9;
DATA_LEAVING
=10;
DATA_LEAVING_2=11;
DATA_LEAVING_3=12;
DATA_LEAVING_4=13;
DATA_LEAVING_5=14;
DATA_LEAVING_6=15;
35
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37
initial
state <= WAIT;
38
39
40
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42
always @ (posedge clk)
if(reset)
begin
newout <= 0;
85
//state data
= 1;
= 2;
= 3;
rd <= 1;
state <= WAIT;
43
44
end
45
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48
//we can’t read data
else
if(~hold)
begin
newout <= 0;
case(state)
WAIT:
if(~rxf)
begin
49
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53
//if rxf is low and
rd <= 1;
state <= WAIT2;
54
55
//and
end
56
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WAIT2:
58
if(~rxf)
begin
59
60
//double check
rd <= 1;
state <= WAIT3;
61
62
end
63
else
64
state <= WAIT;
65
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WAIT3:
67
if(~rxf)
begin
68
69
//and triple check (
rd <= 0;
state <= DATA_COMING;
70
71
end
72
else
73
state <= WAIT;
74
75
DATA_COMING:
//once rd goes low we go
state <= DATA_COMING_2;
76
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DATA_COMING_2:
state <= DATA_COMING_3;
79
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DATA_COMING_3:
state <= DATA_HERE;
82
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DATA_HERE:
begin
85
86
out <= data;
//the data is va
state <= DATA_LEAVING;
87
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newout <= 1;
89
//let folks know
end
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DATA_LEAVING:
begin
92
93
//wait a cycle
//rd <= 1; // ORIGINAL
state <= DATA_LEAVING_2;
newout <= 0;
//let folks know
94
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end
97
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DATA_LEAVING_2:
//wait another cycle
state <= DATA_LEAVING_3;
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101
DATA_LEAVING_3:
//wait another cycle
state <= DATA_LEAVING_4;
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DATA_LEAVING_4:
//wait another cycle
state <= DATA_LEAVING_5;
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DATA_LEAVING_5:
//wait another cycle
state <= DATA_LEAVING_6;
108
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110
DATA_LEAVING_6:
begin
111
112
state <= WAIT;
rd <= 1;
113
114
end
115
default:
116
state <= WAIT;
117
endcase
118
end
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endmodule
A.1.13
1
usb transfer script.py
#! /usr/bin/env python
2
3
4
5
6
import
import
import
import
serial
wave
struct
scipy
7
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//wait another cycle
’’’
6.111 USB transfer script
Luis Fernandez
87
12
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14
15
Script runs through a coe file (basically row after row of 8 bit values) and
sends line by line.
’’’
16
17
ser = serial.Serial(port=’/dev/tty.usbserial-FTDHKA57’)
18
19
a = open(’audio_convert/Fa48k8bit.coe’,’r’)
20
21
for line in a:
22
line = line.rstrip()[0:-1]
line = int(line, base=2)
23
24
25
b = struct.pack("<H", line)
26
27
r = ser.write(b[0])
28
29
30
ser.close()
A.2
A.2.1
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7
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Labkit
labkit.v
‘default_nettype none
////////////////////////////////////////////////////////////////////////////////
//
// 6.111 FPGA Labkit -- Template Toplevel Module
//
// For Labkit Revision 004
//
//
// Created: October 31, 2004, from revision 003 file
// Author: Nathan Ickes
//
///////////////////////////////////////////////////////////////////////////////
//
// CHANGES FOR BOARD REVISION 004
//
// 1) Added signals for logic analyzer pods 2-4.
// 2) Expanded "tv_in_ycrcb" to 20 bits.
// 3) Renamed "tv_out_data" to "tv_out_i2c_data" and "tv_out_sclk" to
//
"tv_out_i2c_clock".
// 4) Reversed disp_data_in and disp_data_out signals, so that "out" is an
//
output of the FPGA, and "in" is an input.
//
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// CHANGES FOR BOARD REVISION 003
//
// 1) Combined flash chip enables into a single signal, flash_ce_b.
//
// CHANGES FOR BOARD REVISION 002
//
// 1) Added SRAM clock feedback path input and output
// 2) Renamed "mousedata" to "mouse_data"
// 3) Renamed some ZBT memory signals. Parity bits are now incorporated into
//
the data bus, and the byte write enables have been combined into the
//
4-bit ram#_bwe_b bus.
// 4) Removed the "systemace_clock" net, since the SystemACE clock is now
//
hardwired on the PCB to the oscillator.
//
///////////////////////////////////////////////////////////////////////////////
//
// Complete change history (including bug fixes)
//
// 2006-Mar-08: Corrected default assignments to "vga_out_red", "vga_out_green"
//
and "vga_out_blue". (Was 10’h0, now 8’h0.)
//
// 2005-Sep-09: Added missing default assignments to "ac97_sdata_out",
//
"disp_data_out", "analyzer[2-3]_clock" and
//
"analyzer[2-3]_data".
//
// 2005-Jan-23: Reduced flash address bus to 24 bits, to match 128Mb devices
//
actually populated on the boards. (The boards support up to
//
256Mb devices, with 25 address lines.)
//
// 2004-Oct-31: Adapted to new revision 004 board.
//
// 2004-May-01: Changed "disp_data_in" to be an output, and gave it a default
//
value. (Previous versions of this file declared this port to
//
be an input.)
//
// 2004-Apr-29: Reduced SRAM address busses to 19 bits, to match 18Mb devices
//
actually populated on the boards. (The boards support up to
//
72Mb devices, with 21 address lines.)
//
// 2004-Apr-29: Change history started
//
///////////////////////////////////////////////////////////////////////////////
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module labkit (beep, audio_reset_b, ac97_sdata_out, ac97_sdata_in, ac97_synch,
ac97_bit_clock,
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vga_out_red, vga_out_green, vga_out_blue, vga_out_sync_b,
vga_out_blank_b, vga_out_pixel_clock, vga_out_hsync,
vga_out_vsync,
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tv_out_ycrcb, tv_out_reset_b, tv_out_clock, tv_out_i2c_clock,
tv_out_i2c_data, tv_out_pal_ntsc, tv_out_hsync_b,
tv_out_vsync_b, tv_out_blank_b, tv_out_subcar_reset,
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tv_in_ycrcb, tv_in_data_valid, tv_in_line_clock1,
tv_in_line_clock2, tv_in_aef, tv_in_hff, tv_in_aff,
tv_in_i2c_clock, tv_in_i2c_data, tv_in_fifo_read,
tv_in_fifo_clock, tv_in_iso, tv_in_reset_b, tv_in_clock,
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ram0_data, ram0_address, ram0_adv_ld, ram0_clk, ram0_cen_b,
ram0_ce_b, ram0_oe_b, ram0_we_b, ram0_bwe_b,
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ram1_data, ram1_address, ram1_adv_ld, ram1_clk, ram1_cen_b,
ram1_ce_b, ram1_oe_b, ram1_we_b, ram1_bwe_b,
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clock_feedback_out, clock_feedback_in,
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flash_data, flash_address, flash_ce_b, flash_oe_b, flash_we_b,
flash_reset_b, flash_sts, flash_byte_b,
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rs232_txd, rs232_rxd, rs232_rts, rs232_cts,
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mouse_clock, mouse_data, keyboard_clock, keyboard_data,
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97
clock_27mhz, clock1, clock2,
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disp_blank, disp_data_out, disp_clock, disp_rs, disp_ce_b,
disp_reset_b, disp_data_in,
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button0, button1, button2, button3, button_enter, button_right,
button_left, button_down, button_up,
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switch,
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led,
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user1, user2, user3, user4,
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daughtercard,
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systemace_data, systemace_address, systemace_ce_b,
systemace_we_b, systemace_oe_b, systemace_irq, systemace_mpbrdy,
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analyzer1_data, analyzer1_clock,
analyzer2_data, analyzer2_clock,
analyzer3_data, analyzer3_clock,
analyzer4_data, analyzer4_clock);
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output beep, audio_reset_b, ac97_synch, ac97_sdata_out;
input ac97_bit_clock, ac97_sdata_in;
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output [7:0] vga_out_red, vga_out_green, vga_out_blue;
output vga_out_sync_b, vga_out_blank_b, vga_out_pixel_clock,
vga_out_hsync, vga_out_vsync;
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output [9:0] tv_out_ycrcb;
output tv_out_reset_b, tv_out_clock, tv_out_i2c_clock, tv_out_i2c_data,
tv_out_pal_ntsc, tv_out_hsync_b, tv_out_vsync_b, tv_out_blank_b,
tv_out_subcar_reset;
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input
input
[19:0] tv_in_ycrcb;
tv_in_data_valid, tv_in_line_clock1, tv_in_line_clock2, tv_in_aef,
tv_in_hff, tv_in_aff;
output tv_in_i2c_clock, tv_in_fifo_read, tv_in_fifo_clock, tv_in_iso,
tv_in_reset_b, tv_in_clock;
inout
tv_in_i2c_data;
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inout
output
output
output
[35:0] ram0_data;
[18:0] ram0_address;
ram0_adv_ld, ram0_clk, ram0_cen_b, ram0_ce_b, ram0_oe_b, ram0_we_b;
[3:0] ram0_bwe_b;
inout
output
output
output
[35:0] ram1_data;
[18:0] ram1_address;
ram1_adv_ld, ram1_clk, ram1_cen_b, ram1_ce_b, ram1_oe_b, ram1_we_b;
[3:0] ram1_bwe_b;
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input
output
clock_feedback_in;
clock_feedback_out;
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inout [15:0] flash_data;
output [23:0] flash_address;
output flash_ce_b, flash_oe_b, flash_we_b, flash_reset_b, flash_byte_b;
input
flash_sts;
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output rs232_txd, rs232_rts;
input rs232_rxd, rs232_cts;
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input
mouse_clock, mouse_data, keyboard_clock, keyboard_data;
input
clock_27mhz, clock1, clock2;
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output
input
output
disp_blank, disp_clock, disp_rs, disp_ce_b, disp_reset_b;
disp_data_in;
disp_data_out;
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input button0, button1, button2, button3, button_enter, button_right,
button_left, button_down, button_up;
input [7:0] switch;
output [7:0] led;
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inout [31:0] user1, user2, user3, user4;
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inout [43:0] daughtercard;
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inout [15:0] systemace_data;
output [6:0] systemace_address;
output systemace_ce_b, systemace_we_b, systemace_oe_b;
input systemace_irq, systemace_mpbrdy;
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output [15:0] analyzer1_data, analyzer2_data, analyzer3_data,
analyzer4_data;
output analyzer1_clock, analyzer2_clock, analyzer3_clock, analyzer4_clock;
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////////////////////////////////////////////////////////////////////////////
//
// I/O Assignments
//
////////////////////////////////////////////////////////////////////////////
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// Audio Input and Output
assign beep= 1’b0;
// assign audio_reset_b = 1’b0;
// assign ac97_synch = 1’b0;
// assign ac97_sdata_out = 1’b0;
// ac97_sdata_in is an input
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// Video Output
assign tv_out_ycrcb = 10’h0;
assign tv_out_reset_b = 1’b0;
assign tv_out_clock = 1’b0;
assign tv_out_i2c_clock = 1’b0;
assign tv_out_i2c_data = 1’b0;
assign tv_out_pal_ntsc = 1’b0;
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assign
assign
assign
assign
tv_out_hsync_b = 1’b1;
tv_out_vsync_b = 1’b1;
tv_out_blank_b = 1’b1;
tv_out_subcar_reset = 1’b0;
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// Video Input
//assign tv_in_i2c_clock = 1’b0;
assign tv_in_fifo_read = 1’b1;
assign tv_in_fifo_clock = 1’b0;
assign tv_in_iso = 1’b1;
//assign tv_in_reset_b = 1’b0;
assign tv_in_clock = clock_27mhz;//1’b0;
//assign tv_in_i2c_data = 1’bZ;
// tv_in_ycrcb, tv_in_data_valid, tv_in_line_clock1, tv_in_line_clock2,
// tv_in_aef, tv_in_hff, and tv_in_aff are inputs
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// SRAMs
assign ram0_data = 36’hZ;
assign ram0_address = 19’h0;
assign ram0_adv_ld = 1’b0;
assign ram0_clk = 1’b0;
assign ram0_cen_b = 1’b1;
assign ram0_ce_b = 1’b1;
assign ram0_oe_b = 1’b1;
assign ram0_we_b = 1’b1;
assign ram0_bwe_b = 4’hF;
assign ram1_data = 36’hZ;
assign ram1_address = 19’h0;
assign ram1_adv_ld = 1’b0;
assign ram1_clk = 1’b0;
assign ram1_cen_b = 1’b1;
assign ram1_ce_b = 1’b1;
assign ram1_oe_b = 1’b1;
assign ram1_we_b = 1’b1;
assign ram1_bwe_b = 4’hF;
assign clock_feedback_out = 1’b0;
// clock_feedback_in is an input
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//
//
//
//
//
//
//
//
Flash ROM
assign flash_data = 16’hZ;
assign flash_address = 24’h0;
assign flash_ce_b = 1’b1;
assign flash_oe_b = 1’b1;
assign flash_we_b = 1’b1;
assign flash_reset_b = 1’b0;
assign flash_byte_b = 1’b1;
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// // flash_sts is an input
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// RS-232 Interface
assign rs232_txd = 1’b1;
assign rs232_rts = 1’b1;
// rs232_rxd and rs232_cts are inputs
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// PS/2 Ports
// mouse_clock, mouse_data, keyboard_clock, and keyboard_data are inputs
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// Buttons, Switches, and Individual LEDs
//assign led = 8’hFF;
// button0, button1, button2, button3, button_enter, button_right,
// button_left, button_down, button_up, and switches are inputs
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// User I/Os
assign user1[21:4] = 28’hZ;
assign user2 = 32’hZ;
assign user3 = 32’hZ;
assign user4 = 32’hZ;
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// Daughtercard Connectors
assign daughtercard = 44’hZ;
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// SystemACE Microprocessor Port
assign systemace_data = 16’hZ;
assign systemace_address = 7’h0;
assign systemace_ce_b = 1’b1;
assign systemace_we_b = 1’b1;
assign systemace_oe_b = 1’b1;
// systemace_irq and systemace_mpbrdy are inputs
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// Logic Analyzer
assign analyzer1_data = 16’h0;
assign analyzer1_clock = 1’b1;
assign analyzer2_data = 16’h0;
assign analyzer2_clock = 1’b1;
assign analyzer3_data = 16’h0;
assign analyzer3_clock = 1’b1;
assign analyzer4_data = 16’h0;
assign analyzer4_clock = 1’b1;
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////////////////////////////////////////////////////////////////////////////
//
// Reset Generation
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//
// A shift register primitive is used to generate an active-high reset
// signal that remains high for 16 clock cycles after configuration finishes
// and the FPGA’s internal clocks begin toggling.
//
////////////////////////////////////////////////////////////////////////////
wire reset;
SRL16 reset_sr(.D(1’b0), .CLK(clock_27mhz), .Q(reset),
.A0(1’b1), .A1(1’b1), .A2(1’b1), .A3(1’b1));
defparam reset_sr.INIT = 16’hFFFF;
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////////////////////////////////////////////////////////////////////////////////////////////
// create clocks
// use FPGA’s digital clock manager to produce a 50 MHz clock
// this clock is our system clock
// to drive VGA at 640x480 (60 Hz), we need a 25 MHz vga clock
// credits to Jose for computing the required clock values
// and use of ramclock module
////////////////////////////////////////////////////////////////////////////////////////////
wire sys_clk_unbuf, sys_clk, vga_clk, vga_clk_unbuf;
wire slow_clk;
wire clk_locked;
DCM vclk1(.CLKIN(clock_27mhz),.CLKFX(sys_clk_unbuf));
// synthesis attribute CLKFX_DIVIDE of vclk1 is 15
// synthesis attribute CLKFX_MULTIPLY of vclk1 is 28
// synthesis attribute CLK_FEEDBACK of vclk1 is NONE
// synthesis attribute CLKIN_PERIOD of vclk1 is 37
BUFG vclk2(.O(sys_clk),.I(sys_clk_unbuf));
DCM int_dcm(.CLKIN(sys_clk), .CLKFX(vga_clk_unbuf), .LOCKED(clk_locked));
// synthesis attribute CLKFX_DIVIDE of int_dcm is 4
// synthesis attribute CLKFX_MULTIPLY of int_dcm is 2
// synthesis attribute CLK_FEEDBACK of int_dcm is NONE
// synthesis attribute CLKIN_PERIOD of int_dcm is 20
BUFG int_dcm2(.O(vga_clk), .I(vga_clk_unbuf));
// assign led[7] = ~clk_locked;
// assign led[5:1] = {6{1’b1}};
slow_clk slow(.clk(sys_clk),
.slow_clk(slow_clk));
// assign led[6] = ~slow_clk;
wire[6:0] percent_kept;
assign led[7:1] = ~percent_kept;
wire busy;
assign led[0] = ~busy;
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////////////////////////////////////////////////////////////////////////////////////////////
// create debounced buttons
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////////////////////////////////////////////////////////////////////////////////////////////
wire btn_up_clean, btn_down_clean, btn_left_clean, btn_right_clean;
wire btn_up_sw, btn_down_sw, btn_left_sw, btn_right_sw;
debounce btn_up_debounce(.reset(reset), .clock(clock_27mhz), .noisy(button_up), .clean(btn_u
debounce btn_down_debounce(.reset(reset), .clock(clock_27mhz), .noisy(button_down), .clean(b
debounce btn_left_debounce(.reset(reset), .clock(clock_27mhz), .noisy(button_left), .clean(b
debounce btn_right_debounce(.reset(reset), .clock(clock_27mhz), .noisy(button_right), .clean
assign btn_up_sw = ~btn_up_clean;
assign btn_down_sw = ~btn_down_clean;
assign btn_left_sw = ~btn_left_clean;
assign btn_right_sw = ~btn_right_clean;
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////////////////////////////////////////////////////////////////////////////////////////////
// create switches
////////////////////////////////////////////////////////////////////////////////////////////
wire override_sw;
wire[1:0] quad_corner_sw;
assign override_sw = switch[7];
assign quad_corner_sw = switch[1:0];
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////////////////////////////////////////////////////////////////////////////////////////////
// instantiate vga
////////////////////////////////////////////////////////////////////////////////////////////
wire[9:0] hcount;
wire[9:0] vcount;
wire vsync, hsync, blank;
vga vga(.vclock(vga_clk),
.hcount(hcount),
.vcount(vcount),
.vsync(vsync),
.hsync(hsync),
.blank(blank));
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reg old_btn_up, old_btn_down, old_btn_left, old_btn_right;
always @(posedge vsync) begin
old_btn_up <= btn_up_sw;
old_btn_down <= btn_down_sw;
old_btn_left <= btn_left_sw;
old_btn_right <= btn_right_sw;
end
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////////////////////////////////////////////////////////////////////////////////////////////
// instantiate accel_lut and move_cursor
// essentially, corners of quadrilateral logic
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////////////////////////////////////////////////////////////////////////////////////////////
wire acc_ready;
wire signed [15:0] acc_x;
wire signed [15:0] acc_y;
reg signed [15:0] acc_x_reg;
reg signed [15:0] acc_y_reg;
acc a(.clk(sys_clk), .sdo(user1[0]), .reset(reset),
.ncs(user1[1]), .sda(user1[2]), .scl(user1[3]),
.ready(acc_ready), .x(acc_x), .y(acc_y));
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always @(posedge slow_clk) begin
acc_x_reg <= acc_ready ? acc_x : 0;
acc_y_reg <= acc_ready ? acc_y : 0;
end
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wire[11:0] accel_val;
wire[75:0] quad_corners;
wire[9:0] x1_raw;
wire[8:0] y1_raw;
wire[9:0] x2_raw;
wire[8:0] y2_raw;
wire[9:0] x3_raw;
wire[8:0] y3_raw;
wire[9:0] x4_raw;
wire[8:0] y4_raw;
wire[9:0] x1;
wire[8:0] y1;
wire[9:0] x2;
wire[8:0] y2;
wire[9:0] x3;
wire[8:0] y3;
wire[9:0] x4;
wire[8:0] y4;
wire[9:0] display_x;
wire[8:0] display_y;
assign accel_val = {~acc_x_reg[15], acc_x_reg[7:4], 1’b0,
~acc_y_reg[15], acc_y_reg[7:4], 1’b0};
accel_lut accel_lut(.clk(slow_clk),
.accel_val(accel_val),
.quad_corners(quad_corners));
assign y4_raw = quad_corners[8:0];
assign x4_raw = quad_corners[18:9];
assign y3_raw = quad_corners[27:19];
assign x3_raw = quad_corners[37:28];
assign y2_raw = quad_corners[46:38];
assign x2_raw = quad_corners[56:47];
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assign y1_raw = quad_corners[65:57];
assign x1_raw = quad_corners[75:66];
move_cursor move_cursor(.clk(vsync),
.up(btn_up_sw & ~old_btn_up),
.down(btn_down_sw & ~old_btn_down),
.left(btn_left_sw & ~old_btn_left),
.right(btn_right_sw & ~old_btn_right),
.override(override_sw),
.switch(quad_corner_sw),
.x1_raw(x1_raw),
.y1_raw(y1_raw),
.x2_raw(x2_raw),
.y2_raw(y2_raw),
.x3_raw(x3_raw),
.y3_raw(y3_raw),
.x4_raw(x4_raw),
.y4_raw(y4_raw),
.x1(x1),
.y1(y1),
.x2(x2),
.y2(y2),
.x3(x3),
.y3(y3),
.x4(x4),
.y4(y4),
.display_x(display_x),
.display_y(display_y));
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////////////////////////////////////////////////////////////////////////////////////////////
// instantiate pixels_kept module
////////////////////////////////////////////////////////////////////////////////////////////
pixels_kept pixels_kept(
.x1(x1),
.y1(y1),
.x2(x2),
.y2(y2),
.x3(x3),
.y3(y3),
.x4(x4),
.y4(y4),
.percent_kept(percent_kept));
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////////////////////////////////////////////////////////////////////////////////////////////
// instantiate perspective_params module
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////////////////////////////////////////////////////////////////////////////////////////////
wire signed[67:0] p1_inv;
wire signed[68:0] p2_inv;
wire signed[78:0] p3_inv;
wire signed[67:0] p4_inv;
wire signed[68:0] p5_inv;
wire signed[78:0] p6_inv;
wire signed[58:0] p7_inv;
wire signed[59:0] p8_inv;
wire signed[70:0] p9_inv;
wire signed[78:0] dec_numx_horiz;
wire signed[78:0] dec_numy_horiz;
wire signed[70:0] dec_denom_horiz;
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perspective_params perspective_params(.clk(slow_clk),
.x1(x1),
.y1(y1),
.x2(x2),
.y2(y2),
.x3(x3),
.y3(y3),
.x4(x4),
.y4(y4),
.p1_inv(p1_inv),
.p2_inv(p2_inv),
.p3_inv(p3_inv),
.p4_inv(p4_inv),
.p5_inv(p5_inv),
.p6_inv(p6_inv),
.p7_inv(p7_inv),
.p8_inv(p8_inv),
.p9_inv(p9_inv),
.dec_numx_horiz(dec_numx_horiz),
.dec_numy_horiz(dec_numy_horiz),
.dec_denom_horiz(dec_denom_horiz));
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////////////////////////////////////////////////////////////////////////////////////////////
// instantiate bram blocks
////////////////////////////////////////////////////////////////////////////////////////////
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// declarations of necessary stuff
reg[16:0] ntsc_cb_in_addr = 0;
wire[16:0] ntsc_out_addr;
wire[16:0] vga_in_addr;
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wire[16:0] vga_out_addr;
wire[11:0] ntsc_cb_din;
wire[11:0] ntsc_dout;
wire[11:0] vga_din;
wire[11:0] vga_dout;
wire ntsc_cb_in_wr;
wire vga_in_wr;
assign ntsc_cb_in_wr = 1;
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// ntsc
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adv7185init adv7185(.reset(reset), .clock_27mhz(clock_27mhz),
.source(1’b0), .tv_in_reset_b(tv_in_reset_b),
.tv_in_i2c_clock(tv_in_i2c_clock),
.tv_in_i2c_data(tv_in_i2c_data));
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wire [29:0] ycrcb;
wire [2:0] fvh;
wire
dv;
// video data (luminance, chrominance)
// sync for field, vertical, horizontal
// data valid
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ntsc_decode decode (.clk(tv_in_line_clock1), .reset(reset),
.tv_in_ycrcb(tv_in_ycrcb[19:10]),
.ycrcb(ycrcb), .f(fvh[2]),
.v(fvh[1]), .h(fvh[0]), .data_valid(dv));
553
554
// code to write NTSC data to video memory
555
556
557
558
559
560
wire [16:0] ntsc_addr;
wire [11:0] ntsc_data;
wire
ntsc_we;
ntsc_to_bram n2b (tv_in_line_clock1, tv_in_line_clock1, fvh, dv,
ycrcb, ntsc_addr, ntsc_data, ntsc_we, switch[6]);
561
562
563
564
565
566
567
568
569
570
571
572
573
574
// dump a checkerboard into "ntsc" buffer
reg[9:0] cur_x = 0;
reg[9:0] cur_y = 0;
wire[2:0] checkerboard;
assign checkerboard = cur_x[7:5] + cur_y[7:5];
assign ntsc_cb_din = {{4{checkerboard[2]}}, {4{checkerboard[1]}}, {4{checkerboard[0]}}};
always @(posedge tv_in_line_clock1) begin
ntsc_cb_in_addr <= (ntsc_cb_in_addr < 76799) ? (ntsc_cb_in_addr + 1) : 0;
cur_x <= (cur_x < 319) ? (cur_x + 1) : 0;
if ((cur_x == 319) && (cur_y == 239)) begin
cur_y <= 0;
end
else if (cur_x == 319) begin
100
cur_y <= cur_y + 1;
575
end
576
577
end
578
579
580
581
582
583
584
585
586
587
588
589
590
591
592
593
594
595
596
597
// instantiate the pixel_map module
pixel_map pixel_map(.clk(sys_clk),
.p1_inv(p1_inv),
.p2_inv(p2_inv),
.p3_inv(p3_inv),
.p4_inv(p4_inv),
.p5_inv(p5_inv),
.p6_inv(p6_inv),
.p7_inv(p7_inv),
.p8_inv(p8_inv),
.p9_inv(p9_inv),
.dec_numx_horiz(dec_numx_horiz),
.dec_numy_horiz(dec_numy_horiz),
.dec_denom_horiz(dec_denom_horiz),
.pixel_in(ntsc_dout),
.pixel_out(vga_din),
.ntsc_out_addr(ntsc_out_addr),
.vga_in_wr(vga_in_wr),
.vga_in_addr(vga_in_addr));
598
599
600
601
602
// read from vga buffer for display
addr_map addr_map(.hcount(hcount),
.vcount(vcount),
.addr(vga_out_addr));
603
604
605
606
607
608
/*always @(posedge sys_clk) begin
vga_in_addr <= (vga_in_addr < 76799) ? (vga_in_addr + 1) : 0;
ntsc_out_addr <= (ntsc_out_addr < 76799) ? (ntsc_out_addr + 1) : 0;
vga_in_wr <= 1;
end*/
609
610
611
612
613
614
615
616
617
// create the brams
bram ntsc_buf(.a_clk(tv_in_line_clock1),
.a_wr(switch[5] ? ntsc_cb_in_wr : ntsc_we),
.a_addr(switch[5] ? ntsc_cb_in_addr : ntsc_addr),
.a_din(switch[5] ? ntsc_cb_din : ntsc_data),
.b_clk(sys_clk),
.b_addr(ntsc_out_addr),
.b_dout(ntsc_dout));
618
619
620
bram vga_buf(.a_clk(sys_clk),
.a_wr(vga_in_wr),
101
.a_addr(vga_in_addr),
.a_din(vga_din),
.b_clk(vga_clk),
.b_addr(vga_out_addr),
.b_dout(vga_dout));
621
622
623
624
625
626
627
628
629
630
631
632
633
634
635
636
637
638
////////////////////////////////////////////////////////////////////////////////////////////
// Create VGA output signals
// In order to meet the setup and hold times of AD7125, we send it ~vga_clk
////////////////////////////////////////////////////////////////////////////////////////////
assign vga_out_red = {vga_dout[11:8], 4’b0};
assign vga_out_green = {vga_dout[7:4], 4’b0};
assign vga_out_blue = {vga_dout[3:0], 4’b0};
assign vga_out_sync_b = 1’b1;
// not used
assign vga_out_blank_b = ~blank;
assign vga_out_pixel_clock = ~vga_clk;
assign vga_out_hsync = hsync;
assign vga_out_vsync = vsync;
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640
641
642
643
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645
646
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651
652
653
654
655
656
657
658
659
660
////////////////////////////////////////////////////////////////////////////////////////////
// instantiate hex display
////////////////////////////////////////////////////////////////////////////////////////////
wire[63:0] hex_disp_data;
// lower 32 bits, keep nice separator of 0 between x, y
assign hex_disp_data[8:0] = display_y;
assign hex_disp_data[15:9] = 7’d0;
assign hex_disp_data[25:16] = display_x;
assign hex_disp_data[31:26] = 6’d0;
// higher bits, put the percent_kept
assign hex_disp_data[63:32] = {10’b0, accel_val[11:6], 10’b0, accel_val[5:0]};
display_16hex display_16hex(.reset(reset),
.clock_27mhz(clock_27mhz),
.data(hex_disp_data),
.disp_blank(disp_blank),
.disp_clock(disp_clock),
.disp_data_out(disp_data_out),
.disp_rs(disp_rs),
.disp_ce_b(disp_ce_b),
.disp_reset_b(disp_reset_b));
661
662
// AC97
663
664
665
wire [7:0] from_ac97_data, to_ac97_data;
wire ready;
666
102
667
668
669
670
671
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680
681
// allow user to adjust volume
wire vup,vdown;
reg old_vup,old_vdown;
debounce bup(.reset(reset),.clock(clock_27mhz),.noisy(~button3),.clean(vup));
debounce bdown(.reset(reset),.clock(clock_27mhz),.noisy(~button_down),.clean(vdown));
reg [4:0] volume;
always @ (posedge clock_27mhz) begin
if (reset) volume <= 5’d8;
else begin
if (vup & ~old_vup & volume != 5’d31) volume <= volume+1;
if (vdown & ~old_vdown & volume != 5’d0) volume <= volume-1;
end
old_vup <= vup;
old_vdown <= vdown;
end
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683
684
685
686
// AC97 driver
lab5audio labaudio(clock_27mhz, reset, volume, from_ac97_data, to_ac97_data, ready,
audio_reset_b, ac97_sdata_out, ac97_sdata_in,
ac97_synch, ac97_bit_clock);
687
688
689
690
// writeSwitch UP to write, DOWN to read
wire writeSwitch;
debounce sw7(.reset(reset),.clock(clock_27mhz),.noisy(switch[3]),.clean(writeSwitch));
691
692
693
wire startSwitch;
debounce sw6(.reset(reset),.clock(clock_27mhz),.noisy(switch[2]),.clean(startSwitch));
694
695
696
wire memReset;
debounce benter(.reset(reset),.clock(clock_27mhz),.noisy(~button_enter),.clean(memReset));
697
698
699
wire audioTrigger;
debounce b3(.reset(reset),.clock(clock_27mhz),.noisy(~button0),.clean(audioTrigger));
700
701
wire [63:0] hexdisp;
702
703
704
705
706
// Receive and Playback module
audioManager management(
.clock(clock_27mhz),
.reset(memReset),
707
708
709
710
711
712
// User I/O
.startSwitch(startSwitch),
.audioSelector(percent_kept),
.writeSwitch(writeSwitch),
// .hexdisp(hexdisp),
103
.audioTrigger(audioTrigger),
713
714
// AC97 I/O
.ready(ready),
.from_ac97_data(from_ac97_data),
.to_ac97_data(to_ac97_data),
715
716
717
718
719
// Flash I/O
.flash_data(flash_data),
.flash_address(flash_address),
.flash_ce_b(flash_ce_b),
.flash_oe_b(flash_oe_b),
.flash_we_b(flash_we_b),
.flash_reset_b(flash_reset_b),
.flash_byte_b(flash_byte_b),
.flash_sts(flash_sts),
.busy(busy),
720
721
722
723
724
725
726
727
728
729
730
// USB I/O
.data(user1[31:24]), //the data pins from the USB fifo
.rxf(user1[23]), //the rxf pin from the USB fifo
.rd(user1[22]) //the rd pin TO the USB FIFO (OUTPUT)
731
732
733
734
735
);
736
737
endmodule
A.2.2
1
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3
4
5
6
7
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9
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14
15
16
17
18
labkit.ucf
###############################################################################
#
# 6.111 FPGA Labkit -- Constraints File
#
# For Labkit Revision 004
#
#
# Created: Oct 30, 2004 from revision 003 contraints file
# Author: Nathan Ickes and Isaac Cambron
#
###############################################################################
#
# CHANGES FOR BOARD REVISION 004
#
# 1) Added signals for logic analyzer pods 2-4.
# 2) Expanded tv_in_ycrcy bus to 20 bits.
# 3) Renamed tv_out_sclk to tv_out_i2c_clock for consistency
# 4) Renamed tv_out_data to tv_out_i2c_data for consistency
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# 5) Reversed disp_data_in and disp_data_out signals, so that "out" is an
#
output of the FPGA, and "in" is an input.
#
# CHANGES FOR BOARD REVISION 003
#
# 1) Combined flash chip enables into a single signal, flash_ce_b.
# 2) Moved SRAM feedback clock loop to FPGA pins AL28 (out) and AJ16 (in).
# 3) Moved rs232_rts to FPGA pin R3.
# 4) Moved flash_address<1> to AE14.
#
# CHANGES FOR BOARD REVISION 002
#
# 1) Moved ZBT_BANK1_CLK signal to pin Y9.
# 2) Moved user1<30> to J14.
# 3) Moved user3<29> to J13.
# 4) Added SRAM clock feedback loop between D15 and H15.
# 5) Renamed ram#_parity and ram#_we#_b signals.
# 6) Removed the constraint on "systemace_clock", since this net no longer
#
exists. The SystemACE clock is now hardwired to the 27MHz oscillator
#
on the PCB.
#
###############################################################################
#
# Complete change history (including bug fixes)
#
# 2007-Aug-16: Fixed revision history. (flash_address<1> was actually changed
#
to AE14 for revision 003.)
#
# 2005-Sep-09: Added missing IOSTANDARD attribute to "disp_data_out".
#
# 2005-Jan-23: Added a pullup to FLASH_STS
#
# 2005-Jan-23: Reduced flash address bus to 24 bits, to match 128Mb devices
#
actually populated on the boards. (The boards support up to
#
256Mb devices, with 25 address lines.)
#
# 2005-Jan-23: Change history started.
#
###############################################################################
58
59
60
61
#
# Audio CODEC
#
62
63
64
NET "beep"
NET "audio_reset_b"
LOC="ac19" | IOSTANDARD=LVDCI_33;
LOC="ae18" | IOSTANDARD=LVTTL;
105
65
66
67
68
NET
NET
NET
NET
"ac97_sdata_out"
"ac97_sdata_in"
"ac97_synch"
"ac97_bit_clock"
LOC="ac18" | IOSTANDARD=LVDCI_33;
LOC="aj24";
LOC="ac17" | IOSTANDARD=LVDCI_33;
LOC="ah24";
69
70
71
NET "sys_clk" TNM_NET = sys_clk;
TIMESPEC TS_sys_clk = PERIOD "sys_clk" 20 ns HIGH 50%;
72
73
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75
76
77
NET "vga_clk" TNM_NET = vga_clk;
TIMESPEC TS_vga_clk = PERIOD "vga_clk" 40 ns HIGH 50%;
#
# VGA Output
#
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79
80
81
82
83
84
85
86
NET
NET
NET
NET
NET
NET
NET
NET
"vga_out_red<7>"
"vga_out_red<6>"
"vga_out_red<5>"
"vga_out_red<4>"
"vga_out_red<3>"
"vga_out_red<2>"
"vga_out_red<1>"
"vga_out_red<0>"
LOC="ae9"
LOC="ae8"
LOC="ad12"
LOC="af8"
LOC="af9"
LOC="ag9"
LOC="ag10"
LOC="af11"
NET
NET
NET
NET
NET
NET
NET
NET
"vga_out_green<7>"
"vga_out_green<6>"
"vga_out_green<5>"
"vga_out_green<4>"
"vga_out_green<3>"
"vga_out_green<2>"
"vga_out_green<1>"
"vga_out_green<0>"
NET
NET
NET
NET
NET
NET
NET
NET
"vga_out_blue<7>"
"vga_out_blue<6>"
"vga_out_blue<5>"
"vga_out_blue<4>"
"vga_out_blue<3>"
"vga_out_blue<2>"
"vga_out_blue<1>"
"vga_out_blue<0>"
NET
NET
NET
NET
NET
"vga_out_sync_b"
"vga_out_blank_b"
"vga_out_pixel_clock"
"vga_out_hsync"
"vga_out_vsync"
|
|
|
|
|
|
|
|
IOSTANDARD=LVTTL;
IOSTANDARD=LVTTL;
IOSTANDARD=LVTTL;
IOSTANDARD=LVTTL;
IOSTANDARD=LVTTL;
IOSTANDARD=LVTTL;
IOSTANDARD=LVTTL;
IOSTANDARD=LVTTL;
87
88
89
90
91
92
93
94
95
LOC="ah8"
LOC="ah7"
LOC="aj6"
LOC="ah6"
LOC="ad15"
LOC="ac14"
LOC="ag8"
LOC="ac12"
|
|
|
|
|
|
|
|
IOSTANDARD=LVTTL;
IOSTANDARD=LVTTL;
IOSTANDARD=LVTTL;
IOSTANDARD=LVTTL;
IOSTANDARD=LVTTL;
IOSTANDARD=LVTTL;
IOSTANDARD=LVTTL;
IOSTANDARD=LVTTL;
96
97
98
99
100
101
102
103
104
LOC="ag15"
LOC="ag14"
LOC="ag13"
LOC="ag12"
LOC="aj11"
LOC="ah11"
LOC="aj10"
LOC="ah9"
|
|
|
|
|
|
|
|
IOSTANDARD=LVTTL;
IOSTANDARD=LVTTL;
IOSTANDARD=LVTTL;
IOSTANDARD=LVTTL;
IOSTANDARD=LVTTL;
IOSTANDARD=LVTTL;
IOSTANDARD=LVTTL;
IOSTANDARD=LVTTL;
105
106
107
108
109
110
LOC="aj9"
LOC="aj8"
LOC="ac10"
LOC="ac13"
LOC="ac11"
106
|
|
|
|
|
IOSTANDARD=LVTTL;
IOSTANDARD=LVTTL;
IOSTANDARD=LVTTL;
IOSTANDARD=LVTTL;
IOSTANDARD=LVTTL;
111
112
113
114
#
# Video Output
#
115
116
117
118
119
120
121
122
123
124
125
NET
NET
NET
NET
NET
NET
NET
NET
NET
NET
"tv_out_ycrcb<9>"
"tv_out_ycrcb<8>"
"tv_out_ycrcb<7>"
"tv_out_ycrcb<6>"
"tv_out_ycrcb<5>"
"tv_out_ycrcb<4>"
"tv_out_ycrcb<3>"
"tv_out_ycrcb<2>"
"tv_out_ycrcb<1>"
"tv_out_ycrcb<0>"
LOC="p27"
LOC="r27"
LOC="t29"
LOC="h26"
LOC="j26"
LOC="l26"
LOC="m26"
LOC="n26"
LOC="p26"
LOC="r26"
|
|
|
|
|
|
|
|
|
|
IOSTANDARD=LVDCI_33;
IOSTANDARD=LVDCI_33;
IOSTANDARD=LVDCI_33;
IOSTANDARD=LVDCI_33;
IOSTANDARD=LVDCI_33;
IOSTANDARD=LVDCI_33;
IOSTANDARD=LVDCI_33;
IOSTANDARD=LVDCI_33;
IOSTANDARD=LVDCI_33;
IOSTANDARD=LVDCI_33;
NET
NET
NET
NET
NET
NET
NET
NET
NET
"tv_out_reset_b" LOC="g27" | IOSTANDARD=LVDCI_33;
"tv_out_clock" LOC="l27" | IOSTANDARD=LVDCI_33;
"tv_out_i2c_clock" LOC="j27" | IOSTANDARD=LVDCI_33;
"tv_out_i2c_data" LOC="h27" | IOSTANDARD=LVDCI_33;
"tv_out_pal_ntsc" LOC="j25" | IOSTANDARD=LVDCI_33;
"tv_out_hsync_b" LOC="n27" | IOSTANDARD=LVDCI_33;
"tv_out_vsync_b" LOC="m27" | IOSTANDARD=LVDCI_33;
"tv_out_blank_b" LOC="h25" | IOSTANDARD=LVDCI_33;
"tv_out_subcar_reset" LOC="k27" | IOSTANDARD=LVDCI_33;
126
127
128
129
130
131
132
133
134
135
136
137
138
139
#
# Video Input
#
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
NET
NET
NET
NET
NET
NET
NET
NET
NET
NET
NET
NET
NET
NET
NET
NET
"tv_in_ycrcb<19>" LOC="ag17";
"tv_in_ycrcb<18>" LOC="ag18";
"tv_in_ycrcb<17>" LOC="ag19";
"tv_in_ycrcb<16>" LOC="ag20";
"tv_in_ycrcb<15>" LOC="ae20";
"tv_in_ycrcb<14>" LOC="af21";
"tv_in_ycrcb<13>" LOC="ad20";
"tv_in_ycrcb<12>" LOC="ag23";
"tv_in_ycrcb<11>" LOC="aj26";
"tv_in_ycrcb<10>" LOC="ah26";
"tv_in_ycrcb<9>" LOC="w23";
"tv_in_ycrcb<8>" LOC="v23";
"tv_in_ycrcb<7>" LOC="u23";
"tv_in_ycrcb<6>" LOC="t23";
"tv_in_ycrcb<5>" LOC="t26";
"tv_in_ycrcb<4>" LOC="t24";
107
157
158
159
160
NET
NET
NET
NET
"tv_in_ycrcb<3>"
"tv_in_ycrcb<2>"
"tv_in_ycrcb<1>"
"tv_in_ycrcb<0>"
LOC="r25";
LOC="l30";
LOC="m31";
LOC="m30";
NET
NET
NET
NET
NET
NET
NET
NET
NET
NET
NET
NET
NET
"tv_in_data_valid" LOC="ah25";
"tv_in_line_clock1" LOC="ad16" | IOSTANDARD=LVDCI_33;
"tv_in_line_clock2" LOC="ad17" | IOSTANDARD=LVDCI_33;
"tv_in_aef" LOC="aj23";
"tv_in_hff" LOC="ah23";
"tv_in_aff" LOC="aj22";
"tv_in_i2c_clock" LOC="ad21" | IOSTANDARD=LVDCI_33;
"tv_in_i2c_data" LOC="ad19" | IOSTANDARD=LVDCI_33;
"tv_in_fifo_read" LOC="ac22" | IOSTANDARD=LVDCI_33;
"tv_in_fifo_clock" LOC="ag22" | IOSTANDARD=LVDCI_33;
"tv_in_iso" LOC="aj27" | IOSTANDARD=LVDCI_33;
"tv_in_reset_b" LOC="ag25" | IOSTANDARD=LVDCI_33;
"tv_in_clock" LOC="ab21" | IOSTANDARD=LVDCI_33;
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
#
# SRAMs
#
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
NET
NET
NET
NET
NET
NET
NET
NET
NET
NET
NET
NET
NET
NET
NET
NET
NET
NET
NET
NET
NET
NET
NET
"ram0_data<35>"
"ram0_data<34>"
"ram0_data<33>"
"ram0_data<32>"
"ram0_data<31>"
"ram0_data<30>"
"ram0_data<29>"
"ram0_data<28>"
"ram0_data<27>"
"ram0_data<26>"
"ram0_data<25>"
"ram0_data<24>"
"ram0_data<23>"
"ram0_data<22>"
"ram0_data<21>"
"ram0_data<20>"
"ram0_data<19>"
"ram0_data<18>"
"ram0_data<17>"
"ram0_data<16>"
"ram0_data<15>"
"ram0_data<14>"
"ram0_data<13>"
LOC="ab25"
LOC="ah29"
LOC="ag28"
LOC="ag29"
LOC="af27"
LOC="af29"
LOC="af28"
LOC="ae28"
LOC="ad25"
LOC="aa25"
LOC="ah30"
LOC="ah31"
LOC="ag30"
LOC="ag31"
LOC="af30"
LOC="af31"
LOC="ae30"
LOC="ae31"
LOC="y27"
LOC="aa28"
LOC="y29"
LOC="y28"
LOC="w29"
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
IOSTANDARD=LVDCI_33
IOSTANDARD=LVDCI_33
IOSTANDARD=LVDCI_33
IOSTANDARD=LVDCI_33
IOSTANDARD=LVDCI_33
IOSTANDARD=LVDCI_33
IOSTANDARD=LVDCI_33
IOSTANDARD=LVDCI_33
IOSTANDARD=LVDCI_33
IOSTANDARD=LVDCI_33
IOSTANDARD=LVDCI_33
IOSTANDARD=LVDCI_33
IOSTANDARD=LVDCI_33
IOSTANDARD=LVDCI_33
IOSTANDARD=LVDCI_33
IOSTANDARD=LVDCI_33
IOSTANDARD=LVDCI_33
IOSTANDARD=LVDCI_33
IOSTANDARD=LVDCI_33
IOSTANDARD=LVDCI_33
IOSTANDARD=LVDCI_33
IOSTANDARD=LVDCI_33
IOSTANDARD=LVDCI_33
108
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
NODELAY;
NODELAY;
NODELAY;
NODELAY;
NODELAY;
NODELAY;
NODELAY;
NODELAY;
NODELAY;
NODELAY;
NODELAY;
NODELAY;
NODELAY;
NODELAY;
NODELAY;
NODELAY;
NODELAY;
NODELAY;
NODELAY;
NODELAY;
NODELAY;
NODELAY;
NODELAY;
203
204
205
206
207
208
209
210
211
212
213
214
215
NET
NET
NET
NET
NET
NET
NET
NET
NET
NET
NET
NET
NET
"ram0_data<12>"
"ram0_data<11>"
"ram0_data<10>"
"ram0_data<9>"
"ram0_data<8>"
"ram0_data<7>"
"ram0_data<6>"
"ram0_data<5>"
"ram0_data<4>"
"ram0_data<3>"
"ram0_data<2>"
"ram0_data<1>"
"ram0_data<0>"
LOC="w28"
LOC="v28"
LOC="u29"
LOC="u28"
LOC="aa27"
LOC="ad31"
LOC="ac30"
LOC="ac31"
LOC="ab30"
LOC="ab31"
LOC="aa30"
LOC="aa31"
LOC="y30"
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IOSTANDARD=LVDCI_33
IOSTANDARD=LVDCI_33
IOSTANDARD=LVDCI_33
IOSTANDARD=LVDCI_33
IOSTANDARD=LVDCI_33
IOSTANDARD=LVDCI_33
IOSTANDARD=LVDCI_33
IOSTANDARD=LVDCI_33
IOSTANDARD=LVDCI_33
IOSTANDARD=LVDCI_33
IOSTANDARD=LVDCI_33
IOSTANDARD=LVDCI_33
IOSTANDARD=LVDCI_33
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NODELAY;
NODELAY;
NODELAY;
NODELAY;
NODELAY;
NODELAY;
NODELAY;
NODELAY;
NODELAY;
NODELAY;
NODELAY;
NODELAY;
NODELAY;
NET
NET
NET
NET
NET
NET
NET
NET
NET
NET
NET
NET
NET
NET
NET
NET
NET
NET
NET
"ram0_address<18>" LOC="v31" | IOSTANDARD=LVDCI_33;
"ram0_address<17>" LOC="w31" | IOSTANDARD=LVDCI_33;
"ram0_address<16>" LOC="ad28" | IOSTANDARD=LVDCI_33;
"ram0_address<15>" LOC="ad29" | IOSTANDARD=LVDCI_33;
"ram0_address<14>" LOC="ac24" | IOSTANDARD=LVDCI_33;
"ram0_address<13>" LOC="ad26" | IOSTANDARD=LVDCI_33;
"ram0_address<12>" LOC="ad27" | IOSTANDARD=LVDCI_33;
"ram0_address<11>" LOC="ac27" | IOSTANDARD=LVDCI_33;
"ram0_address<10>" LOC="ab27" | IOSTANDARD=LVDCI_33;
"ram0_address<9>" LOC="y31" | IOSTANDARD=LVDCI_33;
"ram0_address<8>" LOC="w30" | IOSTANDARD=LVDCI_33;
"ram0_address<7>" LOC="y26" | IOSTANDARD=LVDCI_33;
"ram0_address<6>" LOC="y25" | IOSTANDARD=LVDCI_33;
"ram0_address<5>" LOC="ab24" | IOSTANDARD=LVDCI_33;
"ram0_address<4>" LOC="ac25" | IOSTANDARD=LVDCI_33;
"ram0_address<3>" LOC="aa26" | IOSTANDARD=LVDCI_33;
"ram0_address<2>" LOC="aa24" | IOSTANDARD=LVDCI_33;
"ram0_address<1>" LOC="ab29" | IOSTANDARD=LVDCI_33;
"ram0_address<0>" LOC="ac26" | IOSTANDARD=LVDCI_33;
NET
NET
NET
NET
NET
NET
NET
NET
NET
NET
"ram0_adv_ld" LOC="v26" | IOSTANDARD=LVDCI_33;
"ram0_clk" LOC="u30" | IOSTANDARD=LVDCI_33;
"ram0_cen_b" LOC="u25" | IOSTANDARD=LVDCI_33;
"ram0_ce_b" LOC="w26" | IOSTANDARD=LVDCI_33;
"ram0_oe_b" LOC="v25" | IOSTANDARD=LVDCI_33;
"ram0_we_b" LOC="u31" | IOSTANDARD=LVDCI_33;
"ram0_bwe_b<0>" LOC="v27" | IOSTANDARD=LVDCI_33;
"ram0_bwe_b<1>" LOC="u27" | IOSTANDARD=LVDCI_33;
"ram0_bwe_b<2>" LOC="w27" | IOSTANDARD=LVDCI_33;
"ram0_bwe_b<3>" LOC="u26" | IOSTANDARD=LVDCI_33;
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
240
241
242
243
244
245
246
247
248
NET "ram1_data<35>" LOC="aa9" | IOSTANDARD=LVDCI_33 | NODELAY;
109
249
250
251
252
253
254
255
256
257
258
259
260
261
262
263
264
265
266
267
268
269
270
271
272
273
274
275
276
277
278
279
280
281
282
283
NET
NET
NET
NET
NET
NET
NET
NET
NET
NET
NET
NET
NET
NET
NET
NET
NET
NET
NET
NET
NET
NET
NET
NET
NET
NET
NET
NET
NET
NET
NET
NET
NET
NET
NET
"ram1_data<34>"
"ram1_data<33>"
"ram1_data<32>"
"ram1_data<31>"
"ram1_data<30>"
"ram1_data<29>"
"ram1_data<28>"
"ram1_data<27>"
"ram1_data<26>"
"ram1_data<25>"
"ram1_data<24>"
"ram1_data<23>"
"ram1_data<22>"
"ram1_data<21>"
"ram1_data<20>"
"ram1_data<19>"
"ram1_data<18>"
"ram1_data<17>"
"ram1_data<16>"
"ram1_data<15>"
"ram1_data<14>"
"ram1_data<13>"
"ram1_data<12>"
"ram1_data<11>"
"ram1_data<10>"
"ram1_data<9>"
"ram1_data<8>"
"ram1_data<7>"
"ram1_data<6>"
"ram1_data<5>"
"ram1_data<4>"
"ram1_data<3>"
"ram1_data<2>"
"ram1_data<1>"
"ram1_data<0>"
LOC="ah2"
LOC="ah1"
LOC="ag2"
LOC="ag1"
LOC="af2"
LOC="af1"
LOC="ae2"
LOC="ae1"
LOC="ab9"
LOC="ah3"
LOC="ag4"
LOC="ag3"
LOC="af4"
LOC="af3"
LOC="ae4"
LOC="ae5"
LOC="ad5"
LOC="v2"
LOC="ad1"
LOC="ac2"
LOC="ac1"
LOC="ab2"
LOC="ab1"
LOC="aa2"
LOC="aa1"
LOC="y2"
LOC="v4"
LOC="ac3"
LOC="ac4"
LOC="aa5"
LOC="aa3"
LOC="aa4"
LOC="y3"
LOC="y4"
LOC="w3"
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IOSTANDARD=LVDCI_33
IOSTANDARD=LVDCI_33
IOSTANDARD=LVDCI_33
IOSTANDARD=LVDCI_33
IOSTANDARD=LVDCI_33
IOSTANDARD=LVDCI_33
IOSTANDARD=LVDCI_33
IOSTANDARD=LVDCI_33
IOSTANDARD=LVDCI_33
IOSTANDARD=LVDCI_33
IOSTANDARD=LVDCI_33
IOSTANDARD=LVDCI_33
IOSTANDARD=LVDCI_33
IOSTANDARD=LVDCI_33
IOSTANDARD=LVDCI_33
IOSTANDARD=LVDCI_33
IOSTANDARD=LVDCI_33
IOSTANDARD=LVDCI_33
IOSTANDARD=LVDCI_33
IOSTANDARD=LVDCI_33
IOSTANDARD=LVDCI_33
IOSTANDARD=LVDCI_33
IOSTANDARD=LVDCI_33
IOSTANDARD=LVDCI_33
IOSTANDARD=LVDCI_33
IOSTANDARD=LVDCI_33
IOSTANDARD=LVDCI_33
IOSTANDARD=LVDCI_33
IOSTANDARD=LVDCI_33
IOSTANDARD=LVDCI_33
IOSTANDARD=LVDCI_33
IOSTANDARD=LVDCI_33
IOSTANDARD=LVDCI_33
IOSTANDARD=LVDCI_33
IOSTANDARD=LVDCI_33
|
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|
NODELAY;
NODELAY;
NODELAY;
NODELAY;
NODELAY;
NODELAY;
NODELAY;
NODELAY;
NODELAY;
NODELAY;
NODELAY;
NODELAY;
NODELAY;
NODELAY;
NODELAY;
NODELAY;
NODELAY;
NODELAY;
NODELAY;
NODELAY;
NODELAY;
NODELAY;
NODELAY;
NODELAY;
NODELAY;
NODELAY;
NODELAY;
NODELAY;
NODELAY;
NODELAY;
NODELAY;
NODELAY;
NODELAY;
NODELAY;
NODELAY;
NET
NET
NET
NET
NET
NET
NET
NET
NET
NET
"ram1_address<18>" LOC="ab3" | IOSTANDARD=LVDCI_33;
"ram1_address<17>" LOC="ac5" | IOSTANDARD=LVDCI_33;
"ram1_address<16>" LOC="u6" | IOSTANDARD=LVDCI_33;
"ram1_address<15>" LOC="v6" | IOSTANDARD=LVDCI_33;
"ram1_address<14>" LOC="w6" | IOSTANDARD=LVDCI_33;
"ram1_address<13>" LOC="y6" | IOSTANDARD=LVDCI_33;
"ram1_address<12>" LOC="aa7" | IOSTANDARD=LVDCI_33;
"ram1_address<11>" LOC="ab7" | IOSTANDARD=LVDCI_33;
"ram1_address<10>" LOC="ac6" | IOSTANDARD=LVDCI_33;
"ram1_address<9>" LOC="ad3" | IOSTANDARD=LVDCI_33;
284
285
286
287
288
289
290
291
292
293
294
110
295
296
297
298
299
300
301
302
303
NET
NET
NET
NET
NET
NET
NET
NET
NET
"ram1_address<8>"
"ram1_address<7>"
"ram1_address<6>"
"ram1_address<5>"
"ram1_address<4>"
"ram1_address<3>"
"ram1_address<2>"
"ram1_address<1>"
"ram1_address<0>"
LOC="ad4" | IOSTANDARD=LVDCI_33;
LOC="u3" | IOSTANDARD=LVDCI_33;
LOC="w4" | IOSTANDARD=LVDCI_33;
LOC="ac8" | IOSTANDARD=LVDCI_33;
LOC="ab8" | IOSTANDARD=LVDCI_33;
LOC="aa8" | IOSTANDARD=LVDCI_33;
LOC="y7" | IOSTANDARD=LVDCI_33;
LOC="y8" | IOSTANDARD=LVDCI_33;
LOC="ad7" | IOSTANDARD=LVDCI_33;
NET
NET
NET
NET
NET
NET
NET
NET
NET
NET
"ram1_adv_ld" LOC="y5" | IOSTANDARD=LVDCI_33;
"ram1_clk" LOC="y9" | IOSTANDARD=LVDCI_33;
"ram1_cen_b" LOC="v5" | IOSTANDARD=LVDCI_33;
"ram1_ce_b" LOC="u4" | IOSTANDARD=LVDCI_33;
"ram1_oe_b" LOC="w5" | IOSTANDARD=LVDCI_33;
"ram1_we_b" LOC="aa6" | IOSTANDARD=LVDCI_33;
"ram1_bwe_b<0>" LOC="u2" | IOSTANDARD=LVDCI_33;
"ram1_bwe_b<1>" LOC="u1" | IOSTANDARD=LVDCI_33;
"ram1_bwe_b<2>" LOC="v1" | IOSTANDARD=LVDCI_33;
"ram1_bwe_b<3>" LOC="u5" | IOSTANDARD=LVDCI_33;
304
305
306
307
308
309
310
311
312
313
314
315
316
317
NET "clock_feedback_out" LOC="al28" | IOSTANDARD=LVDCI_33;
NET "clock_feedback_in" LOC="aj16";
318
319
320
321
#
# Flash
#
322
323
324
325
326
327
328
329
330
331
332
333
334
335
336
337
338
NET
NET
NET
NET
NET
NET
NET
NET
NET
NET
NET
NET
NET
NET
NET
NET
"flash_data<15>"
"flash_data<14>"
"flash_data<13>"
"flash_data<12>"
"flash_data<11>"
"flash_data<10>"
"flash_data<9>"
"flash_data<8>"
"flash_data<7>"
"flash_data<6>"
"flash_data<5>"
"flash_data<4>"
"flash_data<3>"
"flash_data<2>"
"flash_data<1>"
"flash_data<0>"
LOC="ak10"
LOC="ak11"
LOC="ak12"
LOC="ak13"
LOC="ak14"
LOC="ak15"
LOC="ah12"
LOC="ah13"
LOC="al10"
LOC="al11"
LOC="al12"
LOC="al13"
LOC="al14"
LOC="al15"
LOC="aj12"
LOC="aj13"
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IOSTANDARD=LVTTL;
IOSTANDARD=LVTTL;
IOSTANDARD=LVTTL;
IOSTANDARD=LVTTL;
IOSTANDARD=LVTTL;
IOSTANDARD=LVTTL;
IOSTANDARD=LVTTL;
IOSTANDARD=LVTTL;
IOSTANDARD=LVTTL;
IOSTANDARD=LVTTL;
IOSTANDARD=LVTTL;
IOSTANDARD=LVTTL;
IOSTANDARD=LVTTL;
IOSTANDARD=LVTTL;
IOSTANDARD=LVTTL;
IOSTANDARD=LVTTL;
339
340
NET "flash_address<24>" LOC="al7";
111
341
342
343
344
345
346
347
348
349
350
351
352
353
354
355
356
357
358
359
360
361
362
363
364
NET
NET
NET
NET
NET
NET
NET
NET
NET
NET
NET
NET
NET
NET
NET
NET
NET
NET
NET
NET
NET
NET
NET
NET
"flash_address<23>"
"flash_address<22>"
"flash_address<21>"
"flash_address<20>"
"flash_address<19>"
"flash_address<18>"
"flash_address<17>"
"flash_address<16>"
"flash_address<15>"
"flash_address<14>"
"flash_address<13>"
"flash_address<12>"
"flash_address<11>"
"flash_address<10>"
"flash_address<9>"
"flash_address<8>"
"flash_address<7>"
"flash_address<6>"
"flash_address<5>"
"flash_address<4>"
"flash_address<3>"
"flash_address<2>"
"flash_address<1>"
"flash_address<0>"
LOC="aj15";
LOC="al25";
LOC="ak23";
LOC="al23";
LOC="ak22";
LOC="al22";
LOC="ak21";
LOC="al21";
LOC="ak20";
LOC="al20";
LOC="ak19";
LOC="al19";
LOC="al18";
LOC="ak17";
LOC="al17";
LOC="ah21";
LOC="aj20";
LOC="ah20";
LOC="aj19";
LOC="ah19";
LOC="ah18";
LOC="aj17";
LOC="ae14";
LOC="ah14";
365
366
NET "flash_ce_b" LOC="aj21" | IOSTANDARD=LVDCI_33;
367
368
369
370
371
372
NET
NET
NET
NET
NET
"flash_oe_b" LOC="ak9" | IOSTANDARD=LVDCI_33;
"flash_we_b" LOC="al8" | IOSTANDARD=LVDCI_33;
"flash_reset_b" LOC="ak18" | IOSTANDARD=LVDCI_33;
"flash_sts" LOC="al9" | PULLUP;
"flash_byte_b" LOC="ah15" | IOSTANDARD=LVDCI_33;
373
374
375
376
#
# RS-232
#
377
378
379
380
381
NET
NET
NET
NET
"rs232_txd"
"rs232_rxd"
"rs232_rts"
"rs232_cts"
LOC="p4" | IOSTANDARD=LVDCI_33;
LOC="p6";
LOC="r3" | IOSTANDARD=LVDCI_33;
LOC="n8";
382
383
384
385
#
# Mouse and Keyboard
#
386
112
387
388
389
390
NET
NET
NET
NET
"mouse_clock" LOC="ac16";
"mouse_data" LOC="ac15";
"keyboard_clock" LOC="ag16";
"keyboard_data" LOC="af16";
391
392
393
394
#
# Clocks
#
395
396
397
398
NET "clock_27mhz" LOC="c16";
NET "clock1" LOC="h16";
NET "clock2" LOC="c15";
399
400
401
402
#
# Alphanumeric Display
#
403
404
405
406
407
408
409
410
NET
NET
NET
NET
NET
NET
NET
"disp_blank" LOC="af12" | IOSTANDARD=LVDCI_33;
"disp_data_in" LOC="ae12";
"disp_clock" LOC="af14" | IOSTANDARD=LVDCI_33;
"disp_rs" LOC="af15" | IOSTANDARD=LVDCI_33;
"disp_ce_b" LOC="af13" | IOSTANDARD=LVDCI_33;
"disp_reset_b" LOC="ag11" | IOSTANDARD=LVDCI_33;
"disp_data_out" LOC="ae15" | IOSTANDARD=LVDCI_33;
411
412
413
414
#
# Buttons and Switches
#
415
416
417
418
419
420
421
422
423
424
NET
NET
NET
NET
NET
NET
NET
NET
NET
"button0" LOC="ae11";
"button1" LOC="ae10";
"button2" LOC="ad11";
"button3" LOC="ab12";
"button_enter" LOC="ak7";
"button_right" LOC="al6";
"button_left" LOC="al5";
"button_up" LOC="al4";
"button_down" LOC="ak6";
NET
NET
NET
NET
NET
NET
NET
"switch<7>"
"switch<6>"
"switch<5>"
"switch<4>"
"switch<3>"
"switch<2>"
"switch<1>"
425
426
427
428
429
430
431
432
LOC="ad22";
LOC="ae23";
LOC="ac20";
LOC="ab20";
LOC="ac21";
LOC="ak25";
LOC="al26";
113
433
NET "switch<0>" LOC="ak26";
434
435
436
437
#
# Discrete LEDs
#
438
439
440
441
442
443
444
445
446
NET
NET
NET
NET
NET
NET
NET
NET
"led<7>"
"led<6>"
"led<5>"
"led<4>"
"led<3>"
"led<2>"
"led<1>"
"led<0>"
LOC="ae17"
LOC="af17"
LOC="af18"
LOC="af19"
LOC="af20"
LOC="ag21"
LOC="ae21"
LOC="ae22"
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|
IOSTANDARD=LVTTL;
IOSTANDARD=LVTTL;
IOSTANDARD=LVTTL;
IOSTANDARD=LVTTL;
IOSTANDARD=LVTTL;
IOSTANDARD=LVTTL;
IOSTANDARD=LVTTL;
IOSTANDARD=LVTTL;
447
448
449
450
451
#
# User Pins
#
452
453
454
455
456
457
458
459
460
461
462
463
464
465
466
467
468
469
470
471
472
473
474
475
476
477
478
NET
NET
NET
NET
NET
NET
NET
NET
NET
NET
NET
NET
NET
NET
NET
NET
NET
NET
NET
NET
NET
NET
NET
NET
NET
NET
"user1<31>" LOC="j15" | IOSTANDARD=LVTTL;
"user1<30>" LOC="j14" | IOSTANDARD=LVTTL;
"user1<29>" LOC="g15" | IOSTANDARD=LVTTL;
"user1<28>" LOC="f14" | IOSTANDARD=LVTTL;
"user1<27>" LOC="f12" | IOSTANDARD=LVTTL;
"user1<26>" LOC="h11" | IOSTANDARD=LVTTL;
"user1<25>" LOC="g9" | IOSTANDARD=LVTTL;
"user1<24>" LOC="h9" | IOSTANDARD=LVTTL;
"user1<23>" LOC="b15" | IOSTANDARD=LVTTL;
"user1<22>" LOC="b14" | IOSTANDARD=LVTTL;
"user1<21>" LOC="f15" | IOSTANDARD=LVTTL;
"user1<20>" LOC="e13" | IOSTANDARD=LVTTL;
"user1<19>" LOC="e11" | IOSTANDARD=LVTTL;
"user1<18>" LOC="e9" | IOSTANDARD=LVTTL;
"user1<17>" LOC="f8" | IOSTANDARD=LVTTL;
"user1<16>" LOC="f7" | IOSTANDARD=LVTTL;
"user1<15>" LOC="c13" | IOSTANDARD=LVTTL;
"user1<14>" LOC="c12" | IOSTANDARD=LVTTL;
"user1<13>" LOC="c11" | IOSTANDARD=LVTTL;
"user1<12>" LOC="c10" | IOSTANDARD=LVTTL;
"user1<11>" LOC="c9" | IOSTANDARD=LVTTL;
"user1<10>" LOC="c8" | IOSTANDARD=LVTTL;
"user1<9>" LOC="c6" | IOSTANDARD=LVTTL;
"user1<8>" LOC="e6" | IOSTANDARD=LVTTL;
"user1<7>" LOC="a11" | IOSTANDARD=LVTTL;
"user1<6>" LOC="a10" | IOSTANDARD=LVTTL;
114
479
480
481
482
483
484
NET
NET
NET
NET
NET
NET
"user1<5>"
"user1<4>"
"user1<3>"
"user1<2>"
"user1<1>"
"user1<0>"
LOC="a9"
LOC="a8"
LOC="b6"
LOC="b5"
LOC="c5"
LOC="b3"
|
|
|
|
|
|
IOSTANDARD=LVTTL;
IOSTANDARD=LVTTL;
IOSTANDARD=LVTTL;
IOSTANDARD=LVTTL;
IOSTANDARD=LVTTL;
IOSTANDARD=LVTTL;
NET
NET
NET
NET
NET
NET
NET
NET
NET
NET
NET
NET
NET
NET
NET
NET
NET
NET
NET
NET
NET
NET
NET
NET
NET
NET
NET
NET
NET
NET
NET
NET
"user2<31>" LOC="b27" | IOSTANDARD=LVTTL;
"user2<30>" LOC="b26" | IOSTANDARD=LVTTL;
"user2<29>" LOC="b25" | IOSTANDARD=LVTTL;
"user2<28>" LOC="a24" | IOSTANDARD=LVTTL;
"user2<27>" LOC="a23" | IOSTANDARD=LVTTL;
"user2<26>" LOC="a22" | IOSTANDARD=LVTTL;
"user2<25>" LOC="a21" | IOSTANDARD=LVTTL;
"user2<24>" LOC="a20" | IOSTANDARD=LVTTL;
"user2<23>" LOC="d26" | IOSTANDARD=LVTTL;
"user2<22>" LOC="d25" | IOSTANDARD=LVTTL;
"user2<21>" LOC="c24" | IOSTANDARD=LVTTL;
"user2<20>" LOC="d23" | IOSTANDARD=LVTTL;
"user2<19>" LOC="d21" | IOSTANDARD=LVTTL;
"user2<18>" LOC="d20" | IOSTANDARD=LVTTL;
"user2<17>" LOC="d19" | IOSTANDARD=LVTTL;
"user2<16>" LOC="d18" | IOSTANDARD=LVTTL;
"user2<15>" LOC="f24" | IOSTANDARD=LVTTL;
"user2<14>" LOC="f23" | IOSTANDARD=LVTTL;
"user2<13>" LOC="e22" | IOSTANDARD=LVTTL;
"user2<12>" LOC="e20" | IOSTANDARD=LVTTL;
"user2<11>" LOC="e18" | IOSTANDARD=LVTTL;
"user2<10>" LOC="e16" | IOSTANDARD=LVTTL;
"user2<9>" LOC="a19" | IOSTANDARD=LVTTL;
"user2<8>" LOC="a18" | IOSTANDARD=LVTTL;
"user2<7>" LOC="h22" | IOSTANDARD=LVTTL;
"user2<6>" LOC="g22" | IOSTANDARD=LVTTL;
"user2<5>" LOC="f21" | IOSTANDARD=LVTTL;
"user2<4>" LOC="f19" | IOSTANDARD=LVTTL;
"user2<3>" LOC="f17" | IOSTANDARD=LVTTL;
"user2<2>" LOC="h19" | IOSTANDARD=LVTTL;
"user2<1>" LOC="g20" | IOSTANDARD=LVTTL;
"user2<0>" LOC="h21" | IOSTANDARD=LVTTL;
NET
NET
NET
NET
NET
"user3<31>"
"user3<30>"
"user3<29>"
"user3<28>"
"user3<27>"
485
486
487
488
489
490
491
492
493
494
495
496
497
498
499
500
501
502
503
504
505
506
507
508
509
510
511
512
513
514
515
516
517
518
519
520
521
522
523
524
LOC="g12"
LOC="h13"
LOC="j13"
LOC="g14"
LOC="f13"
|
|
|
|
|
IOSTANDARD=LVTTL;
IOSTANDARD=LVTTL;
IOSTANDARD=LVTTL;
IOSTANDARD=LVTTL;
IOSTANDARD=LVTTL;
115
525
526
527
528
529
530
531
532
533
534
535
536
537
538
539
540
541
542
543
544
545
546
547
548
549
550
551
NET
NET
NET
NET
NET
NET
NET
NET
NET
NET
NET
NET
NET
NET
NET
NET
NET
NET
NET
NET
NET
NET
NET
NET
NET
NET
NET
"user3<26>" LOC="f11" | IOSTANDARD=LVTTL;
"user3<25>" LOC="g10" | IOSTANDARD=LVTTL;
"user3<24>" LOC="h10" | IOSTANDARD=LVTTL;
"user3<23>" LOC="a15" | IOSTANDARD=LVTTL;
"user3<22>" LOC="a14" | IOSTANDARD=LVTTL;
"user3<21>" LOC="e15" | IOSTANDARD=LVTTL;
"user3<20>" LOC="e14" | IOSTANDARD=LVTTL;
"user3<19>" LOC="e12" | IOSTANDARD=LVTTL;
"user3<18>" LOC="e10" | IOSTANDARD=LVTTL;
"user3<17>" LOC="f9" | IOSTANDARD=LVTTL;
"user3<16>" LOC="g8" | IOSTANDARD=LVTTL;
"user3<15>" LOC="d14" | IOSTANDARD=LVTTL;
"user3<14>" LOC="d13" | IOSTANDARD=LVTTL;
"user3<13>" LOC="d12" | IOSTANDARD=LVTTL;
"user3<12>" LOC="d11" | IOSTANDARD=LVTTL;
"user3<11>" LOC="d9" | IOSTANDARD=LVTTL;
"user3<10>" LOC="d8" | IOSTANDARD=LVTTL;
"user3<9>" LOC="d7" | IOSTANDARD=LVTTL;
"user3<8>" LOC="d6" | IOSTANDARD=LVTTL;
"user3<7>" LOC="b12" | IOSTANDARD=LVTTL;
"user3<6>" LOC="b11" | IOSTANDARD=LVTTL;
"user3<5>" LOC="b10" | IOSTANDARD=LVTTL;
"user3<4>" LOC="b9" | IOSTANDARD=LVTTL;
"user3<3>" LOC="a7" | IOSTANDARD=LVTTL;
"user3<2>" LOC="a6" | IOSTANDARD=LVTTL;
"user3<1>" LOC="a5" | IOSTANDARD=LVTTL;
"user3<0>" LOC="a4" | IOSTANDARD=LVTTL;
NET
NET
NET
NET
NET
NET
NET
NET
NET
NET
NET
NET
NET
NET
NET
NET
NET
NET
"user4<31>"
"user4<30>"
"user4<29>"
"user4<28>"
"user4<27>"
"user4<26>"
"user4<25>"
"user4<24>"
"user4<23>"
"user4<22>"
"user4<21>"
"user4<20>"
"user4<19>"
"user4<18>"
"user4<17>"
"user4<16>"
"user4<15>"
"user4<14>"
552
553
554
555
556
557
558
559
560
561
562
563
564
565
566
567
568
569
570
LOC="a28"
LOC="a27"
LOC="a26"
LOC="a25"
LOC="b23"
LOC="b22"
LOC="b21"
LOC="b20"
LOC="e25"
LOC="c26"
LOC="d24"
LOC="c23"
LOC="c22"
LOC="c21"
LOC="c20"
LOC="c19"
LOC="g24"
LOC="e24"
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
IOSTANDARD=LVTTL;
IOSTANDARD=LVTTL;
IOSTANDARD=LVTTL;
IOSTANDARD=LVTTL;
IOSTANDARD=LVTTL;
IOSTANDARD=LVTTL;
IOSTANDARD=LVTTL;
IOSTANDARD=LVTTL;
IOSTANDARD=LVTTL;
IOSTANDARD=LVTTL;
IOSTANDARD=LVTTL;
IOSTANDARD=LVTTL;
IOSTANDARD=LVTTL;
IOSTANDARD=LVTTL;
IOSTANDARD=LVTTL;
IOSTANDARD=LVTTL;
IOSTANDARD=LVTTL;
IOSTANDARD=LVTTL;
116
571
572
573
574
575
576
577
578
579
580
581
582
583
584
NET
NET
NET
NET
NET
NET
NET
NET
NET
NET
NET
NET
NET
NET
"user4<13>" LOC="e23" | IOSTANDARD=LVTTL;
"user4<12>" LOC="e21" | IOSTANDARD=LVTTL;
"user4<11>" LOC="e19" | IOSTANDARD=LVTTL;
"user4<10>" LOC="e17" | IOSTANDARD=LVTTL;
"user4<9>" LOC="b19" | IOSTANDARD=LVTTL;
"user4<8>" LOC="b18" | IOSTANDARD=LVTTL;
"user4<7>" LOC="h23" | IOSTANDARD=LVTTL;
"user4<6>" LOC="g23" | IOSTANDARD=LVTTL;
"user4<5>" LOC="g21" | IOSTANDARD=LVTTL;
"user4<4>" LOC="f20" | IOSTANDARD=LVTTL;
"user4<3>" LOC="f18" | IOSTANDARD=LVTTL;
"user4<2>" LOC="f16" | IOSTANDARD=LVTTL;
"user4<1>" LOC="g18" | IOSTANDARD=LVTTL;
"user4<0>" LOC="g17" | IOSTANDARD=LVTTL;
585
586
587
588
#
# Daughter Card
#
589
590
591
592
593
594
595
596
597
598
599
600
601
602
603
604
605
606
607
608
609
610
611
612
613
614
615
616
NET
NET
NET
NET
NET
NET
NET
NET
NET
NET
NET
NET
NET
NET
NET
NET
NET
NET
NET
NET
NET
NET
NET
NET
NET
NET
NET
"daughtercard<43>"
"daughtercard<42>"
"daughtercard<41>"
"daughtercard<40>"
"daughtercard<39>"
"daughtercard<38>"
"daughtercard<37>"
"daughtercard<36>"
"daughtercard<35>"
"daughtercard<34>"
"daughtercard<33>"
"daughtercard<32>"
"daughtercard<31>"
"daughtercard<30>"
"daughtercard<29>"
"daughtercard<28>"
"daughtercard<27>"
"daughtercard<26>"
"daughtercard<25>"
"daughtercard<24>"
"daughtercard<23>"
"daughtercard<22>"
"daughtercard<21>"
"daughtercard<20>"
"daughtercard<19>"
"daughtercard<18>"
"daughtercard<17>"
LOC="L7"
LOC="H1"
LOC="J2"
LOC="J1"
LOC="K2"
LOC="M7"
LOC="M6"
LOC="M3"
LOC="M4"
LOC="L3"
LOC="K1"
LOC="L4"
LOC="K3"
LOC="K9"
LOC="L9"
LOC="K8"
LOC="K7"
LOC="L8"
LOC="L6"
LOC="M5"
LOC="N5"
LOC="P5"
LOC="D3"
LOC="E4"
LOC="E3"
LOC="F4"
LOC="F3"
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
IOSTANDARD=LVTTL;
IOSTANDARD=LVTTL;
IOSTANDARD=LVTTL;
IOSTANDARD=LVTTL;
IOSTANDARD=LVTTL;
IOSTANDARD=LVTTL;
IOSTANDARD=LVTTL;
IOSTANDARD=LVTTL;
IOSTANDARD=LVTTL;
IOSTANDARD=LVTTL;
IOSTANDARD=LVTTL;
IOSTANDARD=LVTTL;
IOSTANDARD=LVTTL;
IOSTANDARD=LVTTL;
IOSTANDARD=LVTTL;
IOSTANDARD=LVTTL;
IOSTANDARD=LVTTL;
IOSTANDARD=LVTTL;
IOSTANDARD=LVTTL;
IOSTANDARD=LVTTL;
IOSTANDARD=LVTTL;
IOSTANDARD=LVTTL;
IOSTANDARD=LVTTL;
IOSTANDARD=LVTTL;
IOSTANDARD=LVTTL;
IOSTANDARD=LVTTL;
IOSTANDARD=LVTTL;
117
617
618
619
620
621
622
623
624
625
626
627
628
629
630
631
632
633
NET
NET
NET
NET
NET
NET
NET
NET
NET
NET
NET
NET
NET
NET
NET
NET
NET
"daughtercard<16>" LOC="G4" | IOSTANDARD=LVTTL;
"daughtercard<15>" LOC="H4" | IOSTANDARD=LVTTL;
"daughtercard<14>" LOC="J3" | IOSTANDARD=LVTTL;
"daughtercard<13>" LOC="J4" | IOSTANDARD=LVTTL;
"daughtercard<12>" LOC="D2" | IOSTANDARD=LVTTL;
"daughtercard<11>" LOC="D1" | IOSTANDARD=LVTTL;
"daughtercard<10>" LOC="E2" | IOSTANDARD=LVTTL;
"daughtercard<9>" LOC="E1" | IOSTANDARD=LVTTL;
"daughtercard<8>" LOC="F5" | IOSTANDARD=LVTTL;
"daughtercard<7>" LOC="G5" | IOSTANDARD=LVTTL;
"daughtercard<6>" LOC="H5" | IOSTANDARD=LVTTL;
"daughtercard<5>" LOC="J5" | IOSTANDARD=LVTTL;
"daughtercard<4>" LOC="K5" | IOSTANDARD=LVTTL;
"daughtercard<3>" LOC="H7" | IOSTANDARD=LVTTL;
"daughtercard<2>" LOC="J8" | IOSTANDARD=LVTTL;
"daughtercard<1>" LOC="J6" | IOSTANDARD=LVTTL;
"daughtercard<0>" LOC="J7" | IOSTANDARD=LVTTL;
634
635
636
637
#
# System Ace
#
638
639
640
641
642
643
644
645
646
647
648
649
650
651
652
653
654
NET
NET
NET
NET
NET
NET
NET
NET
NET
NET
NET
NET
NET
NET
NET
NET
"systemace_data<15>" LOC="F29" | IOSTANDARD=LVTTL;
"systemace_data<14>" LOC="G28" | IOSTANDARD=LVTTL;
"systemace_data<13>" LOC="H29" | IOSTANDARD=LVTTL;
"systemace_data<12>" LOC="H28" | IOSTANDARD=LVTTL;
"systemace_data<11>" LOC="J29" | IOSTANDARD=LVTTL;
"systemace_data<10>" LOC="J28" | IOSTANDARD=LVTTL;
"systemace_data<9>" LOC="K29" | IOSTANDARD=LVTTL;
"systemace_data<8>" LOC="L29" | IOSTANDARD=LVTTL;
"systemace_data<7>" LOC="L28" | IOSTANDARD=LVTTL;
"systemace_data<6>" LOC="M29" | IOSTANDARD=LVTTL;
"systemace_data<5>" LOC="M28" | IOSTANDARD=LVTTL;
"systemace_data<4>" LOC="N29" | IOSTANDARD=LVTTL;
"systemace_data<3>" LOC="N28" | IOSTANDARD=LVTTL;
"systemace_data<2>" LOC="P28" | IOSTANDARD=LVTTL;
"systemace_data<1>" LOC="R29" | IOSTANDARD=LVTTL;
"systemace_data<0>" LOC="R28" | IOSTANDARD=LVTTL;
NET
NET
NET
NET
NET
NET
NET
"systemace_address<6>"
"systemace_address<5>"
"systemace_address<4>"
"systemace_address<3>"
"systemace_address<2>"
"systemace_address<1>"
"systemace_address<0>"
655
656
657
658
659
660
661
662
LOC="E29"
LOC="F28"
LOC="H31"
LOC="J30"
LOC="J31"
LOC="K30"
LOC="K31"
118
|
|
|
|
|
|
|
IOSTANDARD=LVTTL;
IOSTANDARD=LVTTL;
IOSTANDARD=LVTTL;
IOSTANDARD=LVTTL;
IOSTANDARD=LVTTL;
IOSTANDARD=LVTTL;
IOSTANDARD=LVTTL;
663
664
665
666
667
668
NET
NET
NET
NET
NET
"systemace_ce_b" LOC="E28" | IOSTANDARD=LVTTL;
"systemace_we_b" LOC="P31" | IOSTANDARD=LVTTL;
"systemace_oe_b" LOC="R31" | IOSTANDARD=LVTTL;
"systemace_irq" LOC="D29";
"systemace_mpbrdy" LOC="L31";
669
670
671
672
#
# Logic Analyzer
#
673
674
675
676
677
678
679
680
681
682
683
684
685
686
687
688
689
690
NET
NET
NET
NET
NET
NET
NET
NET
NET
NET
NET
NET
NET
NET
NET
NET
NET
"analyzer1_data<15>" LOC="G1" | IOSTANDARD=LVTTL;
"analyzer1_data<14>" LOC="H3" | IOSTANDARD=LVTTL;
"analyzer1_data<13>" LOC="M9" | IOSTANDARD=LVTTL;
"analyzer1_data<12>" LOC="M8" | IOSTANDARD=LVTTL;
"analyzer1_data<11>" LOC="L5" | IOSTANDARD=LVTTL;
"analyzer1_data<10>" LOC="L1" | IOSTANDARD=LVTTL;
"analyzer1_data<9>" LOC="L2" | IOSTANDARD=LVTTL;
"analyzer1_data<8>" LOC="N9" | IOSTANDARD=LVTTL;
"analyzer1_data<7>" LOC="M1" | IOSTANDARD=LVTTL;
"analyzer1_data<6>" LOC="M2" | IOSTANDARD=LVTTL;
"analyzer1_data<5>" LOC="N1" | IOSTANDARD=LVTTL;
"analyzer1_data<4>" LOC="N2" | IOSTANDARD=LVTTL;
"analyzer1_data<3>" LOC="P1" | IOSTANDARD=LVTTL;
"analyzer1_data<2>" LOC="P2" | IOSTANDARD=LVTTL;
"analyzer1_data<1>" LOC="R1" | IOSTANDARD=LVTTL;
"analyzer1_data<0>" LOC="R2" | IOSTANDARD=LVTTL;
"analyzer1_clock" LOC="G2" | IOSTANDARD=LVTTL;
NET
NET
NET
NET
NET
NET
NET
NET
NET
NET
NET
NET
NET
NET
NET
NET
NET
"analyzer2_data<15>" LOC="f2" | IOSTANDARD=LVTTL;
"analyzer2_data<14>" LOC="k10" | IOSTANDARD=LVTTL;
"analyzer2_data<13>" LOC="l10" | IOSTANDARD=LVTTL;
"analyzer2_data<12>" LOC="m10" | IOSTANDARD=LVTTL;
"analyzer2_data<11>" LOC="r7" | IOSTANDARD=LVTTL;
"analyzer2_data<10>" LOC="n3" | IOSTANDARD=LVTTL;
"analyzer2_data<9>" LOC="r8" | IOSTANDARD=LVTTL;
"analyzer2_data<8>" LOC="r9" | IOSTANDARD=LVTTL;
"analyzer2_data<7>" LOC="p9" | IOSTANDARD=LVTTL;
"analyzer2_data<6>" LOC="n6" | IOSTANDARD=LVTTL;
"analyzer2_data<5>" LOC="p7" | IOSTANDARD=LVTTL;
"analyzer2_data<4>" LOC="n4" | IOSTANDARD=LVTTL;
"analyzer2_data<3>" LOC="t8" | IOSTANDARD=LVTTL;
"analyzer2_data<2>" LOC="t9" | IOSTANDARD=LVTTL;
"analyzer2_data<1>" LOC="r6" | IOSTANDARD=LVTTL;
"analyzer2_data<0>" LOC="r5" | IOSTANDARD=LVTTL;
"analyzer2_clock" LOC="f1" | IOSTANDARD=LVTTL;
691
692
693
694
695
696
697
698
699
700
701
702
703
704
705
706
707
708
119
709
710
711
712
713
714
715
716
717
718
719
720
721
722
723
724
725
726
NET
NET
NET
NET
NET
NET
NET
NET
NET
NET
NET
NET
NET
NET
NET
NET
NET
"analyzer3_data<15>" LOC="k24" | IOSTANDARD=LVTTL;
"analyzer3_data<14>" LOC="k25" | IOSTANDARD=LVTTL;
"analyzer3_data<13>" LOC="k22" | IOSTANDARD=LVTTL;
"analyzer3_data<12>" LOC="l24" | IOSTANDARD=LVTTL;
"analyzer3_data<11>" LOC="l25" | IOSTANDARD=LVTTL;
"analyzer3_data<10>" LOC="l22" | IOSTANDARD=LVTTL;
"analyzer3_data<9>" LOC="l23" | IOSTANDARD=LVTTL;
"analyzer3_data<8>" LOC="m23" | IOSTANDARD=LVTTL;
"analyzer3_data<7>" LOC="m24" | IOSTANDARD=LVTTL;
"analyzer3_data<6>" LOC="m25" | IOSTANDARD=LVTTL;
"analyzer3_data<5>" LOC="k23" | IOSTANDARD=LVTTL;
"analyzer3_data<4>" LOC="m22" | IOSTANDARD=LVTTL;
"analyzer3_data<3>" LOC="n23" | IOSTANDARD=LVTTL;
"analyzer3_data<2>" LOC="p23" | IOSTANDARD=LVTTL;
"analyzer3_data<1>" LOC="r23" | IOSTANDARD=LVTTL;
"analyzer3_data<0>" LOC="r24" | IOSTANDARD=LVTTL;
"analyzer3_clock" LOC="j24" | IOSTANDARD=LVTTL;
NET
NET
NET
NET
NET
NET
NET
NET
NET
NET
NET
NET
NET
NET
NET
NET
NET
"analyzer4_data<15>" LOC="ag7" | IOSTANDARD=LVTTL;
"analyzer4_data<14>" LOC="ak3" | IOSTANDARD=LVTTL;
"analyzer4_data<13>" LOC="aj5" | IOSTANDARD=LVTTL;
"analyzer4_data<12>" LOC="ak29" | IOSTANDARD=LVTTL;
"analyzer4_data<11>" LOC="ak28" | IOSTANDARD=LVTTL;
"analyzer4_data<10>" LOC="af25" | IOSTANDARD=LVTTL;
"analyzer4_data<9>" LOC="ag24" | IOSTANDARD=LVTTL;
"analyzer4_data<8>" LOC="af24" | IOSTANDARD=LVTTL;
"analyzer4_data<7>" LOC="af23" | IOSTANDARD=LVTTL;
"analyzer4_data<6>" LOC="al27" | IOSTANDARD=LVTTL;
"analyzer4_data<5>" LOC="ak27" | IOSTANDARD=LVTTL;
"analyzer4_data<4>" LOC="ah17" | IOSTANDARD=LVTTL;
"analyzer4_data<3>" LOC="ad13" | IOSTANDARD=LVTTL;
"analyzer4_data<2>" LOC="v7" | IOSTANDARD=LVTTL;
"analyzer4_data<1>" LOC="u7" | IOSTANDARD=LVTTL;
"analyzer4_data<0>" LOC="u8" | IOSTANDARD=LVTTL;
"analyzer4_clock" LOC="ad9" | IOSTANDARD=LVTTL;
727
728
729
730
731
732
733
734
735
736
737
738
739
740
741
742
743
744
A.3
A.3.1
1
2
3
4
5
Our Modules
acc.v
‘timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
120
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
// Create Date:
16:26:11 11/16/2014
// Design Name:
// Module Name:
acc
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
/*
output starts on same cycle start is asserted
high-order bits produced first
input only needs to be supplied on the cycle that start is high
produces zeros if input exhausted
assume W > 1
*/
module par_to_ser #(parameter W=8)
(input clk /* device clock */ , input[W-1:0] par,
input start, output ser);
reg[W-1:0] par_reg = 0;
32
always @(posedge clk) begin
if (start) begin
par_reg <= {par[W-2:0], 1’b0};
end
else begin
par_reg <= {par_reg[W-2:0], 1’b0};
end
end
33
34
35
36
37
38
39
40
41
42
43
assign ser = start ? par[W-1] : par_reg[W-1];
endmodule
44
45
46
47
48
49
50
51
/*
output
assume
assume
*/
module
appears W-1 clock cycles after first serial bit sent
high-order bits are input first
W > 2
ser_to_par #(parameter W=8)
(input clk /* device clock */ , input ser,
121
52
53
output[W-1:0] par);
reg[W-2:0] par_reg = 0;
54
55
56
57
always @(posedge clk) begin
par_reg <= {par_reg[W-3:0], ser};
end
58
59
60
assign par = {par_reg, ser};
endmodule
61
62
63
64
65
66
/*
reduces the system clock by a factor of 6
*/
module acc_clk(input clk /* system clock */ , output dev_clk);
parameter TICKS = 9;
67
68
69
reg [3:0] count = 0;
reg sig_reg = 0;
70
71
72
73
74
75
76
77
78
79
80
81
82
always @(posedge clk) begin
if (count == TICKS) begin
// flip at half period
sig_reg <= ~sig_reg;
count <= 0;
end
else begin
count <= count + 1;
end
end
assign dev_clk = sig_reg;
endmodule
83
84
85
86
87
88
89
90
91
92
93
94
95
/*
assert in_ready when a new datapoint is available, avg_ready will
be signalled after 32 data points have been folded into the average
*/
module moving_avg(
input clock, in_ready, reset,
input signed [15:0] data,
output signed [15:0] avg,
output avg_ready
);
// circular buffer
reg signed [15:0] samples [31:0];
96
97
reg [4:0] offset = 0;
122
98
99
100
reg signed [15:0] accum = 0;
reg [5:0] num_samples = 0;
reg signed [15:0] data_right_shift;
101
102
103
104
105
always @(*) begin
data_right_shift = {data[15], data[15], data[15], data[15],
data[15], data[15:5]};
end
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always @(posedge clock) begin
if (reset) begin
accum <= 0;
num_samples <= 0;
offset <= 0;
end
else if (in_ready) begin
num_samples <= (num_samples == 6’d32) ? num_samples : num_samples +
samples[offset] <= data_right_shift;
if (num_samples == 6’d32) begin
accum <= accum + data_right_shift - samples[offset];
end
else begin
accum <= accum + data_right_shift;
end
offset <= offset + 1;
end
end
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assign avg = accum;
assign avg_ready = (num_samples == 6’d32) ? 1 : 0;
endmodule
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/*
ready permanently asserted after initialization completed
acc operates completely with the slowed accelerometer clock
*/
module acc(input clk /* system clock */ , sdo, reset,
output ncs, sda, scl, ready, output signed [15:0] x, y);
// TODO use state machine -- transition through all of the initiatialization states
// register), then rotate through the value reading states
// one cycle gap between states to allow for CS deassertion
parameter MEASURE_INIT = 0;
parameter X_READ = 1;
parameter Y_READ = 2;
reg[1:0] state = MEASURE_INIT; // TODO: set the right number of bits for this
reg[4:0] count = 0; // TODO: set the right number of bits for this
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reg ncs_reg;
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wire dev_clk;
acc_clk ac(.clk(clk), .dev_clk(dev_clk));
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reg[7:0] par_in;
reg pts_start;
par_to_ser pts(.clk(dev_clk), .par(par_in), .start(pts_start), .ser(sda));
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wire[7:0] par_out;
ser_to_par stp(.clk(dev_clk), .ser(sdo), .par(par_out));
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reg ma_x_in_ready;
reg [7:0] x_low_bits = 0;
reg signed [15:0] ma_x_in;
wire ma_x_avg_ready;
wire signed [15:0] ma_x_avg;
moving_avg ma_x(
.clock(dev_clk), .in_ready(ma_x_in_ready), .reset(reset),
.data(ma_x_in),
.avg(ma_x_avg),
.avg_ready(ma_x_avg_ready)
);
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reg ma_y_in_ready;
reg [7:0] y_low_bits = 0;
reg signed [15:0] ma_y_in;
wire ma_y_avg_ready;
wire signed [15:0] ma_y_avg;
moving_avg ma_y(
.clock(dev_clk), .in_ready(ma_y_in_ready), .reset(reset),
.data(ma_y_in),
.avg(ma_y_avg),
.avg_ready(ma_y_avg_ready)
);
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// invariants: when transitioning out of a state always set counter to 0
always @(posedge dev_clk) begin
case (state)
MEASURE_INIT: begin
if (count == 5’d18) begin
count <= 0;
state <= X_READ;
end
else begin
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count <= count + 1;
190
end
191
end
X_READ: begin
if (count == 5’d25) begin
count <= 0;
state <= Y_READ;
end
else begin
count <= count + 1;
end
if (count == 5’d17) begin
x_low_bits <= par_out;
end
end
Y_READ: begin
if (count == 5’d25) begin
count <= 0;
state <= X_READ;
end
else begin
count <= count + 1;
end
if (count == 5’d17) begin
y_low_bits <= par_out;
end
end
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endcase
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end
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always @(*) begin
case (state)
MEASURE_INIT: begin
pts_start = (count == 5’d2 || count == 5’d10) ? 1 : 0;
if (count == 5’d2) begin
par_in = 8’h2D; // 0 for W, 0 for MB
end
else if (count == 5’d10) begin
par_in = 8’h08; // set measure bit
end
else begin
par_in = 0;
end
ma_x_in_ready = 0; ma_x_in = 0;
ma_y_in_ready = 0; ma_y_in = 0;
ncs_reg = (count == 5’d18 || count == 5’d0) ? 1 : 0;
125
end
X_READ: begin
pts_start = (count == 5’d1) ? 1 : 0;
par_in = (count == 5’d1) ? 8’hF2 : 0; // 1 for R, 1 for MB
ma_x_in_ready = (count == 5’d25) ? 1 : 0;
ma_x_in = (count == 5’d25) ? {par_out, x_low_bits} : 0;
ma_y_in_ready = 0; ma_y_in = 0;
ncs_reg = (count == 5’d25) ? 1 : 0;
end
Y_READ: begin
pts_start = (count == 5’d1) ? 1 : 0;
par_in = (count == 5’d1) ? 8’hF4 : 0; // 1 for R, 1 for MB
ma_y_in_ready = (count == 5’d25) ? 1 : 0;
ma_y_in = (count == 5’d25) ? {par_out, y_low_bits} : 0;
ma_x_in_ready = 0; ma_x_in = 0;
ncs_reg = (count == 5’d25) ? 1 : 0;
end
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endcase
253
end
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assign scl = (ncs_reg == 1 || (state == MEASURE_INIT && count == 5’d1
|| state != MEASURE_INIT && count == 5’d0)) ? 1 : dev_clk;
assign ncs = ncs_reg;
assign ready = ma_x_avg_ready && ma_y_avg_ready;
assign x = ma_x_avg;
assign y = ma_y_avg;
endmodule
A.3.2
1
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accel lut.v
////////////////////////////////////////////////////////////////////////////////
//This file was autogenerated by accel_lut.jl.
//DO NOT MANUALLY EDIT THIS FILE!!!
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//This file implements accel_lut rom for lookup of quadrilateral corners
//based on accelerometer readings
////////////////////////////////////////////////////////////////////////////////
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module accel_lut(input clk, input[11:0] accel_val, output reg[75:0] quad_corners);
always @(posedge clk) begin
case (accel_val)
12’d0: quad_corners = 76’d166903815503556664320;
12’d1: quad_corners = 76’d166903815503556664320;
12’d2: quad_corners = 76’d166903815503556664320;
12’d3: quad_corners = 76’d166903815503556664320;
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12’d4: quad_corners = 76’d166903815503556664320;
12’d5: quad_corners = 76’d166903815503556664320;
12’d6: quad_corners = 76’d166903815503556664320;
12’d7: quad_corners = 76’d166903815503556664320;
12’d8: quad_corners = 76’d166903815503556664320;
12’d9: quad_corners = 76’d166903815503556664320;
12’d10: quad_corners = 76’d166903815503556664320;
12’d11: quad_corners = 76’d166903815503556664320;
12’d12: quad_corners = 76’d166903815503556664320;
12’d13: quad_corners = 76’d166903815503556664320;
12’d14: quad_corners = 76’d166903815503556664320;
12’d15: quad_corners = 76’d166903815503556664320;
12’d16: quad_corners = 76’d166903815503556664320;
12’d17: quad_corners = 76’d166903815503556664320;
12’d18: quad_corners = 76’d166903815503556664320;
12’d19: quad_corners = 76’d166903815503556664320;
12’d20: quad_corners = 76’d166903815503556664320;
12’d21: quad_corners = 76’d166903815503556664320;
12’d22: quad_corners = 76’d166903815503556664320;
12’d23: quad_corners = 76’d166903815503556664320;
12’d24: quad_corners = 76’d166903815503556664320;
12’d25: quad_corners = 76’d166759137365526861312;
12’d26: quad_corners = 76’d92683508482071876096;
12’d27: quad_corners = 76’d92538830344042597376;
12’d28: quad_corners = 76’d92394292943501150208;
12’d29: quad_corners = 76’d92249614805471871489;
12’d30: quad_corners = 76’d92104936667442592770;
12’d31: quad_corners = 76’d91960398992023762435;
12’d32: quad_corners = 76’d165458581135586242565;
12’d33: quad_corners = 76’d165313902172117936646;
12’d34: quad_corners = 76’d165169223208381195272;
12’d35: quad_corners = 76’d238811520539482660361;
12’d36: quad_corners = 76’d238666841575745918475;
12’d37: quad_corners = 76’d312165023443625184781;
12’d38: quad_corners = 76’d312020344479620007951;
12’d39: quad_corners = 76’d385662500798086774801;
12’d40: quad_corners = 76’d459304797854041896980;
12’d41: quad_corners = 76’d532802979996530634774;
12’d42: quad_corners = 76’d606445136314729490457;
12’d43: quad_corners = 76’d680087433370416177180;
12’d44: quad_corners = 76’d753729730151224956958;
12’d45: quad_corners = 76’d827227771281079520801;
12’d46: quad_corners = 76’d900870068061619865125;
12’d47: quad_corners = 76’d1048299200674119531560;
12’d48: quad_corners = 76’d1121941356717172044332;
12’d49: quad_corners = 76’d1195439397571879741487;
127
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12’d50:
12’d51:
12’d52:
12’d53:
12’d54:
12’d55:
12’d56:
12’d57:
12’d58:
12’d59:
12’d60:
12’d61:
12’d62:
12’d63:
12’d64:
12’d65:
12’d66:
12’d67:
12’d68:
12’d69:
12’d70:
12’d71:
12’d72:
12’d73:
12’d74:
12’d75:
12’d76:
12’d77:
12’d78:
12’d79:
12’d80:
12’d81:
12’d82:
12’d83:
12’d84:
12’d85:
12’d86:
12’d87:
12’d88:
12’d89:
12’d90:
12’d91:
12’d92:
12’d93:
12’d94:
12’d95:
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
128
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
76’d1342868670646990380595;
76’d1490297802984343704631;
76’d1563795843838783490619;
76’d1563795843838783490619;
76’d1563795843838783490619;
76’d1563795843838783490619;
76’d1563795843838783490619;
76’d1563795843838783490619;
76’d1563795843838783490619;
76’d1563795843838783490619;
76’d1563795843838783490619;
76’d1563795843838783490619;
76’d1563795843838783490619;
76’d1563795843838783490619;
76’d166903815503556664320;
76’d166903815503556664320;
76’d166903815503556664320;
76’d166903815503556664320;
76’d166903815503556664320;
76’d166903815503556664320;
76’d166903815503556664320;
76’d166903815503556664320;
76’d166903815503556664320;
76’d166903815503556664320;
76’d166903815503556664320;
76’d166903815503556664320;
76’d166903815503556664320;
76’d166903815503556664320;
76’d166903815503556664320;
76’d166903815503556664320;
76’d166903815503556664320;
76’d166903815503556664320;
76’d166903815503556664320;
76’d166903815503556664320;
76’d166903815503556664320;
76’d166903815503556664320;
76’d166903815503556664320;
76’d166903815503556664320;
76’d166903815503556664320;
76’d166759137365526861312;
76’d92683508482071876096;
76’d92538830344042597376;
76’d92394292943501150208;
76’d92249614805471871489;
76’d92104936667442592770;
76’d91960398992023762435;
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12’d96: quad_corners = 76’d165458581135586242565;
12’d97: quad_corners = 76’d165313902172117936646;
12’d98: quad_corners = 76’d165169223208381195272;
12’d99: quad_corners = 76’d238811520539482660361;
12’d100: quad_corners = 76’d238666841575745918475;
12’d101: quad_corners = 76’d312165023443625184781;
12’d102: quad_corners = 76’d312020344479620007951;
12’d103: quad_corners = 76’d385662500798086774801;
12’d104: quad_corners = 76’d459304797854041896980;
12’d105: quad_corners = 76’d532802979996530634774;
12’d106: quad_corners = 76’d606445136314729490457;
12’d107: quad_corners = 76’d680087433370416177180;
12’d108: quad_corners = 76’d753729730151224956958;
12’d109: quad_corners = 76’d827227771281079520801;
12’d110: quad_corners = 76’d900870068061619865125;
12’d111: quad_corners = 76’d1048299200674119531560;
12’d112: quad_corners = 76’d1121941356717172044332;
12’d113: quad_corners = 76’d1195439397571879741487;
12’d114: quad_corners = 76’d1342868670646990380595;
12’d115: quad_corners = 76’d1490297802984343704631;
12’d116: quad_corners = 76’d1563795843838783490619;
12’d117: quad_corners = 76’d1563795843838783490619;
12’d118: quad_corners = 76’d1563795843838783490619;
12’d119: quad_corners = 76’d1563795843838783490619;
12’d120: quad_corners = 76’d1563795843838783490619;
12’d121: quad_corners = 76’d1563795843838783490619;
12’d122: quad_corners = 76’d1563795843838783490619;
12’d123: quad_corners = 76’d1563795843838783490619;
12’d124: quad_corners = 76’d1563795843838783490619;
12’d125: quad_corners = 76’d1563795843838783490619;
12’d126: quad_corners = 76’d1563795843838783490619;
12’d127: quad_corners = 76’d1563795843838783490619;
12’d128: quad_corners = 76’d166903815503556664320;
12’d129: quad_corners = 76’d166903815503556664320;
12’d130: quad_corners = 76’d166903815503556664320;
12’d131: quad_corners = 76’d166903815503556664320;
12’d132: quad_corners = 76’d166903815503556664320;
12’d133: quad_corners = 76’d166903815503556664320;
12’d134: quad_corners = 76’d166903815503556664320;
12’d135: quad_corners = 76’d166903815503556664320;
12’d136: quad_corners = 76’d166903815503556664320;
12’d137: quad_corners = 76’d166903815503556664320;
12’d138: quad_corners = 76’d166903815503556664320;
12’d139: quad_corners = 76’d166903815503556664320;
12’d140: quad_corners = 76’d166903815503556664320;
12’d141: quad_corners = 76’d166903815503556664320;
129
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12’d142:
12’d143:
12’d144:
12’d145:
12’d146:
12’d147:
12’d148:
12’d149:
12’d150:
12’d151:
12’d152:
12’d153:
12’d154:
12’d155:
12’d156:
12’d157:
12’d158:
12’d159:
12’d160:
12’d161:
12’d162:
12’d163:
12’d164:
12’d165:
12’d166:
12’d167:
12’d168:
12’d169:
12’d170:
12’d171:
12’d172:
12’d173:
12’d174:
12’d175:
12’d176:
12’d177:
12’d178:
12’d179:
12’d180:
12’d181:
12’d182:
12’d183:
12’d184:
12’d185:
12’d186:
12’d187:
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
130
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=
=
=
=
=
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=
=
=
=
=
=
=
=
=
=
=
=
=
=
76’d166903815503556664320;
76’d166903815503556664320;
76’d166903815503556664320;
76’d166903815503556664320;
76’d166903815503556664320;
76’d166903815503556664320;
76’d166903815503556664320;
76’d166903815503556664320;
76’d166903815503556664320;
76’d166903815503556664320;
76’d166903815503556664320;
76’d166759137365526861312;
76’d92683508482071876096;
76’d92538830344042597376;
76’d92394292943501150208;
76’d92249614805471871489;
76’d92104936667442592770;
76’d91960398992023762435;
76’d165458581135586242565;
76’d165313902172117936646;
76’d165169223208381195272;
76’d238811520539482660361;
76’d238666841575745918475;
76’d312165023443625184781;
76’d312020344479620007951;
76’d385662500798086774801;
76’d459304797854041896980;
76’d532802979996530634774;
76’d606445136314729490457;
76’d680087433370416177180;
76’d753729730151224956958;
76’d827227771281079520801;
76’d900870068061619865125;
76’d1048299200674119531560;
76’d1121941356717172044332;
76’d1195439397571879741487;
76’d1342868670646990380595;
76’d1490297802984343704631;
76’d1563795843838783490619;
76’d1563795843838783490619;
76’d1563795843838783490619;
76’d1563795843838783490619;
76’d1563795843838783490619;
76’d1563795843838783490619;
76’d1563795843838783490619;
76’d1563795843838783490619;
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
240
241
242
243
244
245
12’d188:
12’d189:
12’d190:
12’d191:
12’d192:
12’d193:
12’d194:
12’d195:
12’d196:
12’d197:
12’d198:
12’d199:
12’d200:
12’d201:
12’d202:
12’d203:
12’d204:
12’d205:
12’d206:
12’d207:
12’d208:
12’d209:
12’d210:
12’d211:
12’d212:
12’d213:
12’d214:
12’d215:
12’d216:
12’d217:
12’d218:
12’d219:
12’d220:
12’d221:
12’d222:
12’d223:
12’d224:
12’d225:
12’d226:
12’d227:
12’d228:
12’d229:
12’d230:
12’d231:
12’d232:
12’d233:
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
131
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
76’d1563795843838783490619;
76’d1563795843838783490619;
76’d1563795843838783490619;
76’d1563795843838783490619;
76’d166903815503556664320;
76’d166903815503556664320;
76’d166903815503556664320;
76’d166903815503556664320;
76’d166903815503556664320;
76’d166903815503556664320;
76’d166903815503556664320;
76’d166903815503556664320;
76’d166903815503556664320;
76’d166903815503556664320;
76’d166903815503556664320;
76’d166903815503556664320;
76’d166903815503556664320;
76’d166903815503556664320;
76’d166903815503556664320;
76’d166903815503556664320;
76’d166903815503556664320;
76’d166903815503556664320;
76’d166903815503556664320;
76’d166903815503556664320;
76’d166903815503556664320;
76’d166903815503556664320;
76’d166903815503556664320;
76’d166903815503556664320;
76’d166903815503556664320;
76’d166759137365526861312;
76’d92683508482071876096;
76’d92538830344042597376;
76’d92394292943501150208;
76’d92249614805471871489;
76’d92104936667442592770;
76’d91960398992023762435;
76’d165458581135586242565;
76’d165313902172117936646;
76’d165169223208381195272;
76’d238811520539482660361;
76’d238666841575745918475;
76’d312165023443625184781;
76’d312020344479620007951;
76’d385662500798086774801;
76’d459304797854041896980;
76’d532802979996530634774;
246
247
248
249
250
251
252
253
254
255
256
257
258
259
260
261
262
263
264
265
266
267
268
269
270
271
272
273
274
275
276
277
278
279
280
281
282
283
284
285
286
287
288
289
290
291
12’d234:
12’d235:
12’d236:
12’d237:
12’d238:
12’d239:
12’d240:
12’d241:
12’d242:
12’d243:
12’d244:
12’d245:
12’d246:
12’d247:
12’d248:
12’d249:
12’d250:
12’d251:
12’d252:
12’d253:
12’d254:
12’d255:
12’d256:
12’d257:
12’d258:
12’d259:
12’d260:
12’d261:
12’d262:
12’d263:
12’d264:
12’d265:
12’d266:
12’d267:
12’d268:
12’d269:
12’d270:
12’d271:
12’d272:
12’d273:
12’d274:
12’d275:
12’d276:
12’d277:
12’d278:
12’d279:
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
132
=
=
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=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
76’d606445136314729490457;
76’d680087433370416177180;
76’d753729730151224956958;
76’d827227771281079520801;
76’d900870068061619865125;
76’d1048299200674119531560;
76’d1121941356717172044332;
76’d1195439397571879741487;
76’d1342868670646990380595;
76’d1490297802984343704631;
76’d1563795843838783490619;
76’d1563795843838783490619;
76’d1563795843838783490619;
76’d1563795843838783490619;
76’d1563795843838783490619;
76’d1563795843838783490619;
76’d1563795843838783490619;
76’d1563795843838783490619;
76’d1563795843838783490619;
76’d1563795843838783490619;
76’d1563795843838783490619;
76’d1563795843838783490619;
76’d166903815503556664320;
76’d166903815503556664320;
76’d166903815503556664320;
76’d166903815503556664320;
76’d166903815503556664320;
76’d166903815503556664320;
76’d166903815503556664320;
76’d166903815503556664320;
76’d166903815503556664320;
76’d166903815503556664320;
76’d166903815503556664320;
76’d166903815503556664320;
76’d166903815503556664320;
76’d166903815503556664320;
76’d166903815503556664320;
76’d166903815503556664320;
76’d166903815503556664320;
76’d166903815503556664320;
76’d166903815503556664320;
76’d166903815503556664320;
76’d166903815503556664320;
76’d166903815503556664320;
76’d166903815503556664320;
76’d166903815503556664320;
292
293
294
295
296
297
298
299
300
301
302
303
304
305
306
307
308
309
310
311
312
313
314
315
316
317
318
319
320
321
322
323
324
325
326
327
328
329
330
331
332
333
334
335
336
337
12’d280:
12’d281:
12’d282:
12’d283:
12’d284:
12’d285:
12’d286:
12’d287:
12’d288:
12’d289:
12’d290:
12’d291:
12’d292:
12’d293:
12’d294:
12’d295:
12’d296:
12’d297:
12’d298:
12’d299:
12’d300:
12’d301:
12’d302:
12’d303:
12’d304:
12’d305:
12’d306:
12’d307:
12’d308:
12’d309:
12’d310:
12’d311:
12’d312:
12’d313:
12’d314:
12’d315:
12’d316:
12’d317:
12’d318:
12’d319:
12’d320:
12’d321:
12’d322:
12’d323:
12’d324:
12’d325:
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
133
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
76’d166903815503556664320;
76’d166759137365526861312;
76’d92683508482071876096;
76’d92538830344042597376;
76’d92394292943501150208;
76’d92249614805471871489;
76’d92104936667442592770;
76’d91960398992023762435;
76’d165458581135586242565;
76’d165313902172117936646;
76’d165169223208381195272;
76’d238811520539482660361;
76’d238666841575745918475;
76’d312165023443625184781;
76’d312020344479620007951;
76’d385662500798086774801;
76’d459304797854041896980;
76’d532802979996530634774;
76’d606445136314729490457;
76’d680087433370416177180;
76’d753729730151224956958;
76’d827227771281079520801;
76’d900870068061619865125;
76’d1048299200674119531560;
76’d1121941356717172044332;
76’d1195439397571879741487;
76’d1342868670646990380595;
76’d1490297802984343704631;
76’d1563795843838783490619;
76’d1563795843838783490619;
76’d1563795843838783490619;
76’d1563795843838783490619;
76’d1563795843838783490619;
76’d1563795843838783490619;
76’d1563795843838783490619;
76’d1563795843838783490619;
76’d1563795843838783490619;
76’d1563795843838783490619;
76’d1563795843838783490619;
76’d1563795843838783490619;
76’d166903815503556664320;
76’d166903815503556664320;
76’d166903815503556664320;
76’d166903815503556664320;
76’d166903815503556664320;
76’d166903815503556664320;
338
339
340
341
342
343
344
345
346
347
348
349
350
351
352
353
354
355
356
357
358
359
360
361
362
363
364
365
366
367
368
369
370
371
372
373
374
375
376
377
378
379
380
381
382
383
12’d326:
12’d327:
12’d328:
12’d329:
12’d330:
12’d331:
12’d332:
12’d333:
12’d334:
12’d335:
12’d336:
12’d337:
12’d338:
12’d339:
12’d340:
12’d341:
12’d342:
12’d343:
12’d344:
12’d345:
12’d346:
12’d347:
12’d348:
12’d349:
12’d350:
12’d351:
12’d352:
12’d353:
12’d354:
12’d355:
12’d356:
12’d357:
12’d358:
12’d359:
12’d360:
12’d361:
12’d362:
12’d363:
12’d364:
12’d365:
12’d366:
12’d367:
12’d368:
12’d369:
12’d370:
12’d371:
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
134
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
76’d166903815503556664320;
76’d166903815503556664320;
76’d166903815503556664320;
76’d166903815503556664320;
76’d166903815503556664320;
76’d166903815503556664320;
76’d166903815503556664320;
76’d166903815503556664320;
76’d166903815503556664320;
76’d166903815503556664320;
76’d166903815503556664320;
76’d166903815503556664320;
76’d166903815503556664320;
76’d166903815503556664320;
76’d166903815503556664320;
76’d166903815503556664320;
76’d166903815503556664320;
76’d166903815503556664320;
76’d166903815503556664320;
76’d166759137365526861312;
76’d92683508482071876096;
76’d92538830344042597376;
76’d92394292943501150208;
76’d92249614805471871489;
76’d92104936667442592770;
76’d91960398992023762435;
76’d165458581135586242565;
76’d165313902172117936646;
76’d165169223208381195272;
76’d238811520539482660361;
76’d238666841575745918475;
76’d312165023443625184781;
76’d312020344479620007951;
76’d385662500798086774801;
76’d459304797854041896980;
76’d532802979996530634774;
76’d606445136314729490457;
76’d680087433370416177180;
76’d753729730151224956958;
76’d827227771281079520801;
76’d900870068061619865125;
76’d1048299200674119531560;
76’d1121941356717172044332;
76’d1195439397571879741487;
76’d1342868670646990380595;
76’d1490297802984343704631;
384
385
386
387
388
389
390
391
392
393
394
395
396
397
398
399
400
401
402
403
404
405
406
407
408
409
410
411
412
413
414
415
416
417
418
419
420
421
422
423
424
425
426
427
428
429
12’d372:
12’d373:
12’d374:
12’d375:
12’d376:
12’d377:
12’d378:
12’d379:
12’d380:
12’d381:
12’d382:
12’d383:
12’d384:
12’d385:
12’d386:
12’d387:
12’d388:
12’d389:
12’d390:
12’d391:
12’d392:
12’d393:
12’d394:
12’d395:
12’d396:
12’d397:
12’d398:
12’d399:
12’d400:
12’d401:
12’d402:
12’d403:
12’d404:
12’d405:
12’d406:
12’d407:
12’d408:
12’d409:
12’d410:
12’d411:
12’d412:
12’d413:
12’d414:
12’d415:
12’d416:
12’d417:
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
135
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
76’d1563795843838783490619;
76’d1563795843838783490619;
76’d1563795843838783490619;
76’d1563795843838783490619;
76’d1563795843838783490619;
76’d1563795843838783490619;
76’d1563795843838783490619;
76’d1563795843838783490619;
76’d1563795843838783490619;
76’d1563795843838783490619;
76’d1563795843838783490619;
76’d1563795843838783490619;
76’d166903815503556664320;
76’d166903815503556664320;
76’d166903815503556664320;
76’d166903815503556664320;
76’d166903815503556664320;
76’d166903815503556664320;
76’d166903815503556664320;
76’d166903815503556664320;
76’d166903815503556664320;
76’d166903815503556664320;
76’d166903815503556664320;
76’d166903815503556664320;
76’d166903815503556664320;
76’d166903815503556664320;
76’d166903815503556664320;
76’d166903815503556664320;
76’d166903815503556664320;
76’d166903815503556664320;
76’d166903815503556664320;
76’d166903815503556664320;
76’d166903815503556664320;
76’d166903815503556664320;
76’d166903815503556664320;
76’d166903815503556664320;
76’d166903815503556664320;
76’d166759137365526861312;
76’d92683508482071876096;
76’d92538830344042597376;
76’d92394292943501150208;
76’d92249614805471871489;
76’d92104936667442592770;
76’d91960398992023762435;
76’d165458581135586242565;
76’d165313902172117936646;
430
431
432
433
434
435
436
437
438
439
440
441
442
443
444
445
446
447
448
449
450
451
452
453
454
455
456
457
458
459
460
461
462
463
464
465
466
467
468
469
470
471
472
473
474
475
12’d418:
12’d419:
12’d420:
12’d421:
12’d422:
12’d423:
12’d424:
12’d425:
12’d426:
12’d427:
12’d428:
12’d429:
12’d430:
12’d431:
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quad_corners
quad_corners
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quad_corners
quad_corners
quad_corners
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136
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76’d165169223208381195272;
76’d238811520539482660361;
76’d238666841575745918475;
76’d312165023443625184781;
76’d312020344479620007951;
76’d385662500798086774801;
76’d459304797854041896980;
76’d532802979996530634774;
76’d606445136314729490457;
76’d680087433370416177180;
76’d753729730151224956958;
76’d827227771281079520801;
76’d900870068061619865125;
76’d1048299200674119531560;
76’d1121941356717172044332;
76’d1195439397571879741487;
76’d1342868670646990380595;
76’d1490297802984343704631;
76’d1563795843838783490619;
76’d1563795843838783490619;
76’d1563795843838783490619;
76’d1563795843838783490619;
76’d1563795843838783490619;
76’d1563795843838783490619;
76’d1563795843838783490619;
76’d1563795843838783490619;
76’d1563795843838783490619;
76’d1563795843838783490619;
76’d1563795843838783490619;
76’d1563795843838783490619;
76’d166903815503556664320;
76’d166903815503556664320;
76’d166903815503556664320;
76’d166903815503556664320;
76’d166903815503556664320;
76’d166903815503556664320;
76’d166903815503556664320;
76’d166903815503556664320;
76’d166903815503556664320;
76’d166903815503556664320;
76’d166903815503556664320;
76’d166903815503556664320;
76’d166903815503556664320;
76’d166903815503556664320;
76’d166903815503556664320;
76’d166903815503556664320;
476
477
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502
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505
506
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508
509
510
511
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514
515
516
517
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519
520
521
12’d464:
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quad_corners
quad_corners
quad_corners
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quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
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137
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76’d166903815503556664320;
76’d166903815503556664320;
76’d166903815503556664320;
76’d166903815503556664320;
76’d166903815503556664320;
76’d166903815503556664320;
76’d166903815503556664320;
76’d166903815503556664320;
76’d166903815503556664320;
76’d166759137365526861312;
76’d92683508482071876096;
76’d92538830344042597376;
76’d92394292943501150208;
76’d92249614805471871489;
76’d92104936667442592770;
76’d91960398992023762435;
76’d165458581135586242565;
76’d165313902172117936646;
76’d165169223208381195272;
76’d238811520539482660361;
76’d238666841575745918475;
76’d312165023443625184781;
76’d312020344479620007951;
76’d385662500798086774801;
76’d459304797854041896980;
76’d532802979996530634774;
76’d606445136314729490457;
76’d680087433370416177180;
76’d753729730151224956958;
76’d827227771281079520801;
76’d900870068061619865125;
76’d1048299200674119531560;
76’d1121941356717172044332;
76’d1195439397571879741487;
76’d1342868670646990380595;
76’d1490297802984343704631;
76’d1563795843838783490619;
76’d1563795843838783490619;
76’d1563795843838783490619;
76’d1563795843838783490619;
76’d1563795843838783490619;
76’d1563795843838783490619;
76’d1563795843838783490619;
76’d1563795843838783490619;
76’d1563795843838783490619;
76’d1563795843838783490619;
522
523
524
525
526
527
528
529
530
531
532
533
534
535
536
537
538
539
540
541
542
543
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547
548
549
550
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552
553
554
555
556
557
558
559
560
561
562
563
564
565
566
567
12’d510:
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12’d550:
12’d551:
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12’d553:
12’d554:
12’d555:
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
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quad_corners
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quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
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quad_corners
quad_corners
quad_corners
quad_corners
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quad_corners
quad_corners
138
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=
76’d1563795843838783490619;
76’d1563795843838783490619;
76’d166903815503556664320;
76’d166903815503556664320;
76’d166903815503556664320;
76’d166903815503556664320;
76’d166903815503556664320;
76’d166903815503556664320;
76’d166903815503556664320;
76’d166903815503556664320;
76’d166903815503556664320;
76’d166903815503556664320;
76’d166903815503556664320;
76’d166903815503556664320;
76’d166903815503556664320;
76’d166903815503556664320;
76’d166903815503556664320;
76’d166903815503556664320;
76’d166903815503556664320;
76’d166903815503556664320;
76’d166903815503556664320;
76’d166903815503556664320;
76’d166903815503556664320;
76’d166903815503556664320;
76’d166903815503556664320;
76’d166903815503556664320;
76’d166903815503556664320;
76’d166759137365526861312;
76’d92683508482071876096;
76’d92538830344042597376;
76’d92394292943501150208;
76’d92249614805471871489;
76’d92104936667442592770;
76’d91960398992023762435;
76’d165458581135586242565;
76’d165313902172117936646;
76’d165169223208381195272;
76’d238811520539482660361;
76’d238666841575745918475;
76’d312165023443625184781;
76’d312020344479620007951;
76’d385662500798086774801;
76’d459304797854041896980;
76’d532802979996530634774;
76’d606445136314729490457;
76’d680087433370416177180;
568
569
570
571
572
573
574
575
576
577
578
579
580
581
582
583
584
585
586
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593
594
595
596
597
598
599
600
601
602
603
604
605
606
607
608
609
610
611
612
613
12’d556:
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12’d599:
12’d600:
12’d601:
quad_corners
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quad_corners
quad_corners
quad_corners
quad_corners
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quad_corners
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quad_corners
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quad_corners
quad_corners
139
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76’d753729730151224956958;
76’d827227771281079520801;
76’d900870068061619865125;
76’d1048299200674119531560;
76’d1121941356717172044332;
76’d1195439397571879741487;
76’d1342868670646990380595;
76’d1490297802984343704631;
76’d1563795843838783490619;
76’d1563795843838783490619;
76’d1563795843838783490619;
76’d1563795843838783490619;
76’d1563795843838783490619;
76’d1563795843838783490619;
76’d1563795843838783490619;
76’d1563795843838783490619;
76’d1563795843838783490619;
76’d1563795843838783490619;
76’d1563795843838783490619;
76’d1563795843838783490619;
76’d166903815503556664320;
76’d166903815503556664320;
76’d166903815503556664320;
76’d166903815503556664320;
76’d166903815503556664320;
76’d166903815503556664320;
76’d166903815503556664320;
76’d166903815503556664320;
76’d166903815503556664320;
76’d166903815503556664320;
76’d166903815503556664320;
76’d166903815503556664320;
76’d166903815503556664320;
76’d166903815503556664320;
76’d166903815503556664320;
76’d166903815503556664320;
76’d166903815503556664320;
76’d166903815503556664320;
76’d166903815503556664320;
76’d166903815503556664320;
76’d166903815503556664320;
76’d166903815503556664320;
76’d166903815503556664320;
76’d166903815503556664320;
76’d166903815503556664320;
76’d166759137365526861312;
614
615
616
617
618
619
620
621
622
623
624
625
626
627
628
629
630
631
632
633
634
635
636
637
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639
640
641
642
643
644
645
646
647
648
649
650
651
652
653
654
655
656
657
658
659
12’d602:
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12’d647:
quad_corners
quad_corners
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quad_corners
quad_corners
quad_corners
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quad_corners
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quad_corners
quad_corners
quad_corners
140
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=
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=
76’d92683508482071876096;
76’d92538830344042597376;
76’d92394292943501150208;
76’d92249614805471871489;
76’d92104936667442592770;
76’d91960398992023762435;
76’d165458581135586242565;
76’d165313902172117936646;
76’d165169223208381195272;
76’d238811520539482660361;
76’d238666841575745918475;
76’d312165023443625184781;
76’d312020344479620007951;
76’d385662500798086774801;
76’d459304797854041896980;
76’d532802979996530634774;
76’d606445136314729490457;
76’d680087433370416177180;
76’d753729730151224956958;
76’d827227771281079520801;
76’d900870068061619865125;
76’d1048299200674119531560;
76’d1121941356717172044332;
76’d1195439397571879741487;
76’d1342868670646990380595;
76’d1490297802984343704631;
76’d1563795843838783490619;
76’d1563795843838783490619;
76’d1563795843838783490619;
76’d1563795843838783490619;
76’d1563795843838783490619;
76’d1563795843838783490619;
76’d1563795843838783490619;
76’d1563795843838783490619;
76’d1563795843838783490619;
76’d1563795843838783490619;
76’d1563795843838783490619;
76’d1563795843838783490619;
76’d166903815503556664320;
76’d166903815503556664320;
76’d166903815503556664320;
76’d166903815503556664320;
76’d166903815503556664320;
76’d166903815503556664320;
76’d166903815503556664320;
76’d166903815503556664320;
660
661
662
663
664
665
666
667
668
669
670
671
672
673
674
675
676
677
678
679
680
681
682
683
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685
686
687
688
689
690
691
692
693
694
695
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697
698
699
700
701
702
703
704
705
12’d648:
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12’d687:
12’d688:
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12’d693:
quad_corners
quad_corners
quad_corners
quad_corners
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76’d166903815503556664320;
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12’d694:
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76’d1563795843838783490619;
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76’d166903815503556664320;
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752
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12’d740:
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76’d238666841575745918475;
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76’d900870068061619865125;
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76’d1342868670646990380595;
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76’d166903815503556664320;
76’d166903815503556664320;
76’d166903815503556664320;
76’d166903815503556664320;
76’d166903815503556664320;
76’d166903815503556664320;
76’d166903815503556664320;
76’d166903815503556664320;
76’d166903815503556664320;
76’d166903815503556664320;
76’d166903815503556664320;
76’d166903815503556664320;
798
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12’d786:
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144
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76’d166903815503556664320;
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76’d1563795843838783490619;
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76’d1563795843838783490619;
76’d1563795843838783490619;
76’d1563795843838783490619;
844
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76’d166903815503556664320;
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890
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quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
146
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
76’d900870068061619865125;
76’d1048299200674119531560;
76’d1121941356717172044332;
76’d1195439397571879741487;
76’d1342868670646990380595;
76’d1490297802984343704631;
76’d1563795843838783490619;
76’d1563795843838783490619;
76’d1563795843838783490619;
76’d1563795843838783490619;
76’d1563795843838783490619;
76’d1563795843838783490619;
76’d1563795843838783490619;
76’d1563795843838783490619;
76’d1563795843838783490619;
76’d1563795843838783490619;
76’d1563795843838783490619;
76’d1563795843838783490619;
76’d166903815503556664320;
76’d166903815503556664320;
76’d166903815503556664320;
76’d166903815503556664320;
76’d166903815503556664320;
76’d166903815503556664320;
76’d166903815503556664320;
76’d166903815503556664320;
76’d166903815503556664320;
76’d166903815503556664320;
76’d166903815503556664320;
76’d166903815503556664320;
76’d166903815503556664320;
76’d166903815503556664320;
76’d166903815503556664320;
76’d166903815503556664320;
76’d166903815503556664320;
76’d166903815503556664320;
76’d166903815503556664320;
76’d166903815503556664320;
76’d166903815503556664320;
76’d166903815503556664320;
76’d166903815503556664320;
76’d166903815503556664320;
76’d166903815503556664320;
76’d166759137365526861312;
76’d92683508482071876096;
76’d92538830344042597376;
936
937
938
939
940
941
942
943
944
945
946
947
948
949
950
951
952
953
954
955
956
957
958
959
960
961
962
963
964
965
966
967
968
969
970
971
972
973
974
975
976
977
978
979
980
981
12’d924:
12’d925:
12’d926:
12’d927:
12’d928:
12’d929:
12’d930:
12’d931:
12’d932:
12’d933:
12’d934:
12’d935:
12’d936:
12’d937:
12’d938:
12’d939:
12’d940:
12’d941:
12’d942:
12’d943:
12’d944:
12’d945:
12’d946:
12’d947:
12’d948:
12’d949:
12’d950:
12’d951:
12’d952:
12’d953:
12’d954:
12’d955:
12’d956:
12’d957:
12’d958:
12’d959:
12’d960:
12’d961:
12’d962:
12’d963:
12’d964:
12’d965:
12’d966:
12’d967:
12’d968:
12’d969:
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
147
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
76’d92394292943501150208;
76’d92249614805471871489;
76’d92104936667442592770;
76’d91960398992023762435;
76’d165458581135586242565;
76’d165313902172117936646;
76’d165169223208381195272;
76’d238811520539482660361;
76’d238666841575745918475;
76’d312165023443625184781;
76’d312020344479620007951;
76’d385662500798086774801;
76’d459304797854041896980;
76’d532802979996530634774;
76’d606445136314729490457;
76’d680087433370416177180;
76’d753729730151224956958;
76’d827227771281079520801;
76’d900870068061619865125;
76’d1048299200674119531560;
76’d1121941356717172044332;
76’d1195439397571879741487;
76’d1342868670646990380595;
76’d1490297802984343704631;
76’d1563795843838783490619;
76’d1563795843838783490619;
76’d1563795843838783490619;
76’d1563795843838783490619;
76’d1563795843838783490619;
76’d1563795843838783490619;
76’d1563795843838783490619;
76’d1563795843838783490619;
76’d1563795843838783490619;
76’d1563795843838783490619;
76’d1563795843838783490619;
76’d1563795843838783490619;
76’d166903815503556664320;
76’d166903815503556664320;
76’d166903815503556664320;
76’d166903815503556664320;
76’d166903815503556664320;
76’d166903815503556664320;
76’d166903815503556664320;
76’d166903815503556664320;
76’d166903815503556664320;
76’d166903815503556664320;
982
983
984
985
986
987
988
989
990
991
992
993
994
995
996
997
998
999
1000
1001
1002
1003
1004
1005
1006
1007
1008
1009
1010
1011
1012
1013
1014
1015
1016
1017
1018
1019
1020
1021
1022
1023
1024
1025
1026
1027
12’d970: quad_corners = 76’d166903815503556664320;
12’d971: quad_corners = 76’d166903815503556664320;
12’d972: quad_corners = 76’d166903815503556664320;
12’d973: quad_corners = 76’d166903815503556664320;
12’d974: quad_corners = 76’d166903815503556664320;
12’d975: quad_corners = 76’d166903815503556664320;
12’d976: quad_corners = 76’d166903815503556664320;
12’d977: quad_corners = 76’d166903815503556664320;
12’d978: quad_corners = 76’d166903815503556664320;
12’d979: quad_corners = 76’d166903815503556664320;
12’d980: quad_corners = 76’d166903815503556664320;
12’d981: quad_corners = 76’d166903815503556664320;
12’d982: quad_corners = 76’d166903815503556664320;
12’d983: quad_corners = 76’d166903815503556664320;
12’d984: quad_corners = 76’d166903815503556664320;
12’d985: quad_corners = 76’d166759137365526861312;
12’d986: quad_corners = 76’d92683508482071876096;
12’d987: quad_corners = 76’d92538830344042597376;
12’d988: quad_corners = 76’d92394292943501150208;
12’d989: quad_corners = 76’d92249614805471871489;
12’d990: quad_corners = 76’d92104936667442592770;
12’d991: quad_corners = 76’d91960398992023762435;
12’d992: quad_corners = 76’d165458581135586242565;
12’d993: quad_corners = 76’d165313902172117936646;
12’d994: quad_corners = 76’d165169223208381195272;
12’d995: quad_corners = 76’d238811520539482660361;
12’d996: quad_corners = 76’d238666841575745918475;
12’d997: quad_corners = 76’d312165023443625184781;
12’d998: quad_corners = 76’d312020344479620007951;
12’d999: quad_corners = 76’d385662500798086774801;
12’d1000: quad_corners = 76’d459304797854041896980;
12’d1001: quad_corners = 76’d532802979996530634774;
12’d1002: quad_corners = 76’d606445136314729490457;
12’d1003: quad_corners = 76’d680087433370416177180;
12’d1004: quad_corners = 76’d753729730151224956958;
12’d1005: quad_corners = 76’d827227771281079520801;
12’d1006: quad_corners = 76’d900870068061619865125;
12’d1007: quad_corners = 76’d1048299200674119531560;
12’d1008: quad_corners = 76’d1121941356717172044332;
12’d1009: quad_corners = 76’d1195439397571879741487;
12’d1010: quad_corners = 76’d1342868670646990380595;
12’d1011: quad_corners = 76’d1490297802984343704631;
12’d1012: quad_corners = 76’d1563795843838783490619;
12’d1013: quad_corners = 76’d1563795843838783490619;
12’d1014: quad_corners = 76’d1563795843838783490619;
12’d1015: quad_corners = 76’d1563795843838783490619;
148
1028
1029
1030
1031
1032
1033
1034
1035
1036
1037
1038
1039
1040
1041
1042
1043
1044
1045
1046
1047
1048
1049
1050
1051
1052
1053
1054
1055
1056
1057
1058
1059
1060
1061
1062
1063
1064
1065
1066
1067
1068
1069
1070
1071
1072
1073
12’d1016:
12’d1017:
12’d1018:
12’d1019:
12’d1020:
12’d1021:
12’d1022:
12’d1023:
12’d1024:
12’d1025:
12’d1026:
12’d1027:
12’d1028:
12’d1029:
12’d1030:
12’d1031:
12’d1032:
12’d1033:
12’d1034:
12’d1035:
12’d1036:
12’d1037:
12’d1038:
12’d1039:
12’d1040:
12’d1041:
12’d1042:
12’d1043:
12’d1044:
12’d1045:
12’d1046:
12’d1047:
12’d1048:
12’d1049:
12’d1050:
12’d1051:
12’d1052:
12’d1053:
12’d1054:
12’d1055:
12’d1056:
12’d1057:
12’d1058:
12’d1059:
12’d1060:
12’d1061:
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
149
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
76’d1563795843838783490619;
76’d1563795843838783490619;
76’d1563795843838783490619;
76’d1563795843838783490619;
76’d1563795843838783490619;
76’d1563795843838783490619;
76’d1563795843838783490619;
76’d1563795843838783490619;
76’d166903815503556664320;
76’d166903815503556664320;
76’d166903815503556664320;
76’d166903815503556664320;
76’d166903815503556664320;
76’d166903815503556664320;
76’d166903815503556664320;
76’d166903815503556664320;
76’d166903815503556664320;
76’d166903815503556664320;
76’d166903815503556664320;
76’d166903815503556664320;
76’d166903815503556664320;
76’d166903815503556664320;
76’d166903815503556664320;
76’d166903815503556664320;
76’d166903815503556664320;
76’d166903815503556664320;
76’d166903815503556664320;
76’d166903815503556664320;
76’d166903815503556664320;
76’d166903815503556664320;
76’d166903815503556664320;
76’d166903815503556664320;
76’d166903815503556664320;
76’d166759137365526861312;
76’d92683508482071876096;
76’d92538830344042597376;
76’d92394292943501150208;
76’d92249614805471871489;
76’d92104936667442592770;
76’d91960398992023762435;
76’d165458581135586242565;
76’d165313902172117936646;
76’d165169223208381195272;
76’d238811520539482660361;
76’d238666841575745918475;
76’d312165023443625184781;
1074
1075
1076
1077
1078
1079
1080
1081
1082
1083
1084
1085
1086
1087
1088
1089
1090
1091
1092
1093
1094
1095
1096
1097
1098
1099
1100
1101
1102
1103
1104
1105
1106
1107
1108
1109
1110
1111
1112
1113
1114
1115
1116
1117
1118
1119
12’d1062:
12’d1063:
12’d1064:
12’d1065:
12’d1066:
12’d1067:
12’d1068:
12’d1069:
12’d1070:
12’d1071:
12’d1072:
12’d1073:
12’d1074:
12’d1075:
12’d1076:
12’d1077:
12’d1078:
12’d1079:
12’d1080:
12’d1081:
12’d1082:
12’d1083:
12’d1084:
12’d1085:
12’d1086:
12’d1087:
12’d1088:
12’d1089:
12’d1090:
12’d1091:
12’d1092:
12’d1093:
12’d1094:
12’d1095:
12’d1096:
12’d1097:
12’d1098:
12’d1099:
12’d1100:
12’d1101:
12’d1102:
12’d1103:
12’d1104:
12’d1105:
12’d1106:
12’d1107:
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
150
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
76’d312020344479620007951;
76’d385662500798086774801;
76’d459304797854041896980;
76’d532802979996530634774;
76’d606445136314729490457;
76’d680087433370416177180;
76’d753729730151224956958;
76’d827227771281079520801;
76’d900870068061619865125;
76’d1048299200674119531560;
76’d1121941356717172044332;
76’d1195439397571879741487;
76’d1342868670646990380595;
76’d1490297802984343704631;
76’d1563795843838783490619;
76’d1563795843838783490619;
76’d1563795843838783490619;
76’d1563795843838783490619;
76’d1563795843838783490619;
76’d1563795843838783490619;
76’d1563795843838783490619;
76’d1563795843838783490619;
76’d1563795843838783490619;
76’d1563795843838783490619;
76’d1563795843838783490619;
76’d1563795843838783490619;
76’d17455098831505222144;
76’d17455098831505222144;
76’d17455098831505222144;
76’d17455098831505222144;
76’d17455098831505222144;
76’d17455098831505222144;
76’d17455098831505222144;
76’d17455098831505222144;
76’d17455098831505222144;
76’d17455098831505222144;
76’d17455098831505222144;
76’d17455098831505222144;
76’d17455098831505222144;
76’d17455098831505222144;
76’d17455098831505222144;
76’d17455098831505222144;
76’d17455098831505222144;
76’d17455098831505222144;
76’d17455098831505222144;
76’d17455098831505222144;
1120
1121
1122
1123
1124
1125
1126
1127
1128
1129
1130
1131
1132
1133
1134
1135
1136
1137
1138
1139
1140
1141
1142
1143
1144
1145
1146
1147
1148
1149
1150
1151
1152
1153
1154
1155
1156
1157
1158
1159
1160
1161
1162
1163
1164
1165
12’d1108:
12’d1109:
12’d1110:
12’d1111:
12’d1112:
12’d1113:
12’d1114:
12’d1115:
12’d1116:
12’d1117:
12’d1118:
12’d1119:
12’d1120:
12’d1121:
12’d1122:
12’d1123:
12’d1124:
12’d1125:
12’d1126:
12’d1127:
12’d1128:
12’d1129:
12’d1130:
12’d1131:
12’d1132:
12’d1133:
12’d1134:
12’d1135:
12’d1136:
12’d1137:
12’d1138:
12’d1139:
12’d1140:
12’d1141:
12’d1142:
12’d1143:
12’d1144:
12’d1145:
12’d1146:
12’d1147:
12’d1148:
12’d1149:
12’d1150:
12’d1151:
12’d1152:
12’d1153:
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
151
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
76’d17455098831505222144;
76’d17455098831505222144;
76’d17455098831505222144;
76’d17455098831505222144;
76’d17455098831505222144;
76’d17310420693475419648;
76’d17165883292934496768;
76’d17021205154905218048;
76’d16876667754364295168;
76’d16731989616334492160;
76’d16731567403869424640;
76’d16586889265840146432;
76’d16442351590421316098;
76’d16297672901830917123;
76’d89939970233200817669;
76’d89795291269464075783;
76’d163581844526129752073;
76’d163437165562393010699;
76’d237079462893494475277;
76’d310721759949718033423;
76’d384508172468626918418;
76’d458150469524582040597;
76’d531792766855146634264;
76’d605579179099178136603;
76’d679221476154864823326;
76’d752863773210283074593;
76’d900437021011395992612;
76’d974079318066814243880;
76’d1121508591417071225388;
76’d1195294862648199070256;
76’d1342724135998187616308;
76’d1490153409073566166584;
76’d1637726656874142213180;
76’d1637726656874142213180;
76’d1637726656874142213180;
76’d1637726656874142213180;
76’d1637726656874142213180;
76’d1637726656874142213180;
76’d1637726656874142213180;
76’d1637726656874142213180;
76’d1637726656874142213180;
76’d1637726656874142213180;
76’d1637726656874142213180;
76’d1637726656874142213180;
76’d15724449937206048768;
76’d15724449937206048768;
1166
1167
1168
1169
1170
1171
1172
1173
1174
1175
1176
1177
1178
1179
1180
1181
1182
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1184
1185
1186
1187
1188
1189
1190
1191
1192
1193
1194
1195
1196
1197
1198
1199
1200
1201
1202
1203
1204
1205
1206
1207
1208
1209
1210
1211
12’d1154:
12’d1155:
12’d1156:
12’d1157:
12’d1158:
12’d1159:
12’d1160:
12’d1161:
12’d1162:
12’d1163:
12’d1164:
12’d1165:
12’d1166:
12’d1167:
12’d1168:
12’d1169:
12’d1170:
12’d1171:
12’d1172:
12’d1173:
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12’d1175:
12’d1176:
12’d1177:
12’d1178:
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12’d1180:
12’d1181:
12’d1182:
12’d1183:
12’d1184:
12’d1185:
12’d1186:
12’d1187:
12’d1188:
12’d1189:
12’d1190:
12’d1191:
12’d1192:
12’d1193:
12’d1194:
12’d1195:
12’d1196:
12’d1197:
12’d1198:
12’d1199:
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
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quad_corners
quad_corners
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quad_corners
quad_corners
quad_corners
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quad_corners
quad_corners
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quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
152
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=
=
=
=
=
=
=
=
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=
=
=
=
=
=
=
=
=
=
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=
=
=
=
=
=
=
=
76’d15724449937206048768;
76’d15724449937206048768;
76’d15724449937206048768;
76’d15724449937206048768;
76’d15724449937206048768;
76’d15724449937206048768;
76’d15724449937206048768;
76’d15724449937206048768;
76’d15724449937206048768;
76’d15724449937206048768;
76’d15724449937206048768;
76’d15724449937206048768;
76’d15724449937206048768;
76’d15724449937206048768;
76’d15724449937206048768;
76’d15724449937206048768;
76’d15724449937206048768;
76’d15724449937206048768;
76’d15724449937206048768;
76’d15724449937206048768;
76’d15724449937206048768;
76’d15724449937206048768;
76’d15724449937206048768;
76’d15579771799176246272;
76’d15435234398635323392;
76’d15434812186169732096;
76’d15290134048140453376;
76’d15145596647599530496;
76’d15145174435134462976;
76’d15000496297105184768;
76’d15000074084639592960;
76’d14855395946341878785;
76’d14854972908437784067;
76’d14710293944969478149;
76’d14709871181943290375;
76’d88496283701120611337;
76’d162138581032222075915;
76’d235925134288887752206;
76’d309711546808065073169;
76’d383497959326974482452;
76’d457140397120417959959;
76’d530926809639326845466;
76’d678500198453073936925;
76’d752286610696837003809;
76’d826073022940867981860;
76’d973646411754078202408;
1212
1213
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1215
1216
1217
1218
1219
1220
1221
1222
1223
1224
1225
1226
1227
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1234
1235
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1244
1245
1246
1247
1248
1249
1250
1251
1252
1253
1254
1255
1256
1257
12’d1200:
12’d1201:
12’d1202:
12’d1203:
12’d1204:
12’d1205:
12’d1206:
12’d1207:
12’d1208:
12’d1209:
12’d1210:
12’d1211:
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12’d1213:
12’d1214:
12’d1215:
12’d1216:
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12’d1233:
12’d1234:
12’d1235:
12’d1236:
12’d1237:
12’d1238:
12’d1239:
12’d1240:
12’d1241:
12’d1242:
12’d1243:
12’d1244:
12’d1245:
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
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quad_corners
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quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
153
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=
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=
=
=
=
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=
=
=
=
=
=
=
=
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=
=
=
=
=
=
=
=
=
=
76’d1121219941030167831084;
76’d1195006353273661937712;
76’d1342579741812263211061;
76’d1490153130350327088697;
76’d1637726518613782019646;
76’d1637726518613782019646;
76’d1637726518613782019646;
76’d1637726518613782019646;
76’d1637726518613782019646;
76’d1637726518613782019646;
76’d1637726518613782019646;
76’d1637726518613782019646;
76’d1637726518613782019646;
76’d1637726518613782019646;
76’d1637726518613782019646;
76’d1637726518613782019646;
76’d13993801042906351104;
76’d13993801042906351104;
76’d13993801042906351104;
76’d13993801042906351104;
76’d13993801042906351104;
76’d13993801042906351104;
76’d13993801042906351104;
76’d13993801042906351104;
76’d13993801042906351104;
76’d13993801042906351104;
76’d13993801042906351104;
76’d13993801042906351104;
76’d13993801042906351104;
76’d13993801042906351104;
76’d13993801042906351104;
76’d13993801042906351104;
76’d13993801042906351104;
76’d13993801042906351104;
76’d13993801042906351104;
76’d13993801042906351104;
76’d13993801042906351104;
76’d13993801042906351104;
76’d13993801042906351104;
76’d13993801042906351104;
76’d13993801042906351104;
76’d13993378830440759808;
76’d13848841429899836928;
76’d13848419217434769920;
76’d13703741079404967424;
76’d13703318866939899904;
1258
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1300
1301
1302
1303
12’d1246:
12’d1247:
12’d1248:
12’d1249:
12’d1250:
12’d1251:
12’d1252:
12’d1253:
12’d1254:
12’d1255:
12’d1256:
12’d1257:
12’d1258:
12’d1259:
12’d1260:
12’d1261:
12’d1262:
12’d1263:
12’d1264:
12’d1265:
12’d1266:
12’d1267:
12’d1268:
12’d1269:
12’d1270:
12’d1271:
12’d1272:
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12’d1274:
12’d1275:
12’d1276:
12’d1277:
12’d1278:
12’d1279:
12’d1280:
12’d1281:
12’d1282:
12’d1283:
12’d1284:
12’d1285:
12’d1286:
12’d1287:
12’d1288:
12’d1289:
12’d1290:
12’d1291:
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
154
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=
=
=
=
=
=
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=
=
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=
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=
=
=
=
=
=
=
=
=
=
=
=
76’d13702896654474832896;
76’d13558359253933909504;
76’d13557796303979962880;
76’d13557374091514895360;
76’d13556951878512956929;
76’d13556388378266849283;
76’d13555965340362754565;
76’d13555542577336566791;
76’d87341955096513887754;
76’d161128508353447999501;
76’d234914920872625320464;
76’d308845589592245283347;
76’d456418978405992375318;
76’d530205531662658051097;
76’d603992084919055291933;
76’d751709588646000332320;
76’d825496141902398096932;
76’d973213645903952609320;
76’d1120787175180042237997;
76’d1268504679181596749873;
76’d1416222182908273354293;
76’d1563795712184094547514;
76’d1711513215910771152447;
76’d1711513215910771152447;
76’d1711513215910771152447;
76’d1711513215910771152447;
76’d1711513215910771152447;
76’d1711513215910771152447;
76’d1711513215910771152447;
76’d1711513215910771152447;
76’d1711513215910771152447;
76’d1711513215910771152447;
76’d1711513215910771152447;
76’d1711513215910771152447;
76’d12407408074170340352;
76’d12407408074170340352;
76’d12407408074170340352;
76’d12407408074170340352;
76’d12407408074170340352;
76’d12407408074170340352;
76’d12407408074170340352;
76’d12407408074170340352;
76’d12407408074170340352;
76’d12407408074170340352;
76’d12407408074170340352;
76’d12407408074170340352;
1304
1305
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1307
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1310
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1313
1314
1315
1316
1317
1318
1319
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1335
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1337
1338
1339
1340
1341
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1344
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1346
1347
1348
1349
12’d1292:
12’d1293:
12’d1294:
12’d1295:
12’d1296:
12’d1297:
12’d1298:
12’d1299:
12’d1300:
12’d1301:
12’d1302:
12’d1303:
12’d1304:
12’d1305:
12’d1306:
12’d1307:
12’d1308:
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12’d1310:
12’d1311:
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12’d1313:
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12’d1320:
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12’d1323:
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12’d1325:
12’d1326:
12’d1327:
12’d1328:
12’d1329:
12’d1330:
12’d1331:
12’d1332:
12’d1333:
12’d1334:
12’d1335:
12’d1336:
12’d1337:
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
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quad_corners
quad_corners
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quad_corners
quad_corners
quad_corners
quad_corners
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quad_corners
quad_corners
quad_corners
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quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
155
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=
=
=
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=
=
=
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=
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=
=
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=
=
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=
=
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=
76’d12407408074170340352;
76’d12407408074170340352;
76’d12407408074170340352;
76’d12407408074170340352;
76’d12407408074170340352;
76’d12407408074170340352;
76’d12407408074170340352;
76’d12407408074170340352;
76’d12407408074170340352;
76’d12407408074170340352;
76’d12407408074170340352;
76’d12407408074170340352;
76’d12407408074170340352;
76’d12406985861705273344;
76’d12262448461164350464;
76’d12262026248698759168;
76’d12261604036233691648;
76’d12261041086280269312;
76’d12260618873814678016;
76’d12260196661349610496;
76’d12259774448884543488;
76’d12259352236419475968;
76’d12258930023954408960;
76’d12402622999028326401;
76’d12402200236002138628;
76’d12401636735756030982;
76’d86332305180765999113;
76’d160118858712309582348;
76’d234049527157319549455;
76’d307980195876938988562;
76’d381766749133873100309;
76’d529484394148062310425;
76’d603414921855316011037;
76’d751132566594895749665;
76’d825063235039368845861;
76’d972780879778680149033;
76’d1120498524517991975981;
76’d1268216028519546487858;
76’d1415933673258858315319;
76’d1563795432911099131451;
76’d1711513077650142522945;
76’d1711513077650142522945;
76’d1711513077650142522945;
76’d1711513077650142522945;
76’d1711513077650142522945;
76’d1711513077650142522945;
1350
1351
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1353
1354
1355
1356
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1358
1359
1360
1361
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1364
1365
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1371
1372
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1384
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1386
1387
1388
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1390
1391
1392
1393
1394
1395
12’d1338:
12’d1339:
12’d1340:
12’d1341:
12’d1342:
12’d1343:
12’d1344:
12’d1345:
12’d1346:
12’d1347:
12’d1348:
12’d1349:
12’d1350:
12’d1351:
12’d1352:
12’d1353:
12’d1354:
12’d1355:
12’d1356:
12’d1357:
12’d1358:
12’d1359:
12’d1360:
12’d1361:
12’d1362:
12’d1363:
12’d1364:
12’d1365:
12’d1366:
12’d1367:
12’d1368:
12’d1369:
12’d1370:
12’d1371:
12’d1372:
12’d1373:
12’d1374:
12’d1375:
12’d1376:
12’d1377:
12’d1378:
12’d1379:
12’d1380:
12’d1381:
12’d1382:
12’d1383:
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
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quad_corners
quad_corners
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quad_corners
quad_corners
quad_corners
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quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
156
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=
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76’d1711513077650142522945;
76’d1711513077650142522945;
76’d1711513077650142522945;
76’d1711513077650142522945;
76’d1711513077650142522945;
76’d1711513077650142522945;
76’d10821015105434329088;
76’d10821015105434329088;
76’d10821015105434329088;
76’d10821015105434329088;
76’d10821015105434329088;
76’d10821015105434329088;
76’d10821015105434329088;
76’d10821015105434329088;
76’d10821015105434329088;
76’d10821015105434329088;
76’d10821015105434329088;
76’d10821015105434329088;
76’d10821015105434329088;
76’d10821015105434329088;
76’d10821015105434329088;
76’d10821015105434329088;
76’d10821015105434329088;
76’d10821015105434329088;
76’d10821015105434329088;
76’d10821015105434329088;
76’d10821015105434329088;
76’d10821015105434329088;
76’d10821015105434329088;
76’d10821015105434329088;
76’d10821015105434329088;
76’d10820592892969262080;
76’d10820170680504195072;
76’d10819748468038603776;
76’d10819326255573536768;
76’d10818904043108469760;
76’d10962597018718734336;
76’d10962174806253666816;
76’d10961752593788599808;
76’d11105445569399388672;
76’d11105023356934321152;
76’d11248716332545110016;
76’d11248294119274736131;
76’d11392127282081195013;
76’d11535819707399299080;
76’d85466488427287173643;
1396
1397
1398
1399
1400
1401
1402
1403
1404
1405
1406
1407
1408
1409
1410
1411
1412
1413
1414
1415
1416
1417
1418
1419
1420
1421
1422
1423
1424
1425
1426
1427
1428
1429
1430
1431
1432
1433
1434
1435
1436
1437
1438
1439
1440
1441
12’d1384:
12’d1385:
12’d1386:
12’d1387:
12’d1388:
12’d1389:
12’d1390:
12’d1391:
12’d1392:
12’d1393:
12’d1394:
12’d1395:
12’d1396:
12’d1397:
12’d1398:
12’d1399:
12’d1400:
12’d1401:
12’d1402:
12’d1403:
12’d1404:
12’d1405:
12’d1406:
12’d1407:
12’d1408:
12’d1409:
12’d1410:
12’d1411:
12’d1412:
12’d1413:
12’d1414:
12’d1415:
12’d1416:
12’d1417:
12’d1418:
12’d1419:
12’d1420:
12’d1421:
12’d1422:
12’d1423:
12’d1424:
12’d1425:
12’d1426:
12’d1427:
12’d1428:
12’d1429:
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
157
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=
=
=
=
=
=
=
=
=
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=
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=
=
=
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=
=
=
=
=
=
=
=
=
=
76’d233184133442013254670;
76’d307114802161901129234;
76’d381045470606642661397;
76’d528763115621368742425;
76’d602837899529064037405;
76’d750555544268644299809;
76’d898273329745712393765;
76’d1046135089947977459753;
76’d1193852734687557722158;
76’d1341714494614944881203;
76’d1489576254817210470968;
76’d1637438014744329194045;
76’d1785299915409204708418;
76’d1785299915409204708418;
76’d1785299915409204708418;
76’d1785299915409204708418;
76’d1785299915409204708418;
76’d1785299915409204708418;
76’d1785299915409204708418;
76’d1785299915409204708418;
76’d1785299915409204708418;
76’d1785299915409204708418;
76’d1785299915409204708418;
76’d1785299915409204708418;
76’d9522993250338384896;
76’d9522993250338384896;
76’d9522993250338384896;
76’d9522993250338384896;
76’d9522993250338384896;
76’d9522993250338384896;
76’d9522993250338384896;
76’d9522993250338384896;
76’d9522993250338384896;
76’d9522993250338384896;
76’d9522993250338384896;
76’d9522993250338384896;
76’d9522993250338384896;
76’d9522993250338384896;
76’d9522993250338384896;
76’d9522993250338384896;
76’d9522993250338384896;
76’d9522993250338384896;
76’d9522993250338384896;
76’d9522993250338384896;
76’d9522993250338384896;
76’d9522993250338384896;
1442
1443
1444
1445
1446
1447
1448
1449
1450
1451
1452
1453
1454
1455
1456
1457
1458
1459
1460
1461
1462
1463
1464
1465
1466
1467
1468
1469
1470
1471
1472
1473
1474
1475
1476
1477
1478
1479
1480
1481
1482
1483
1484
1485
1486
1487
12’d1430:
12’d1431:
12’d1432:
12’d1433:
12’d1434:
12’d1435:
12’d1436:
12’d1437:
12’d1438:
12’d1439:
12’d1440:
12’d1441:
12’d1442:
12’d1443:
12’d1444:
12’d1445:
12’d1446:
12’d1447:
12’d1448:
12’d1449:
12’d1450:
12’d1451:
12’d1452:
12’d1453:
12’d1454:
12’d1455:
12’d1456:
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12’d1458:
12’d1459:
12’d1460:
12’d1461:
12’d1462:
12’d1463:
12’d1464:
12’d1465:
12’d1466:
12’d1467:
12’d1468:
12’d1469:
12’d1470:
12’d1471:
12’d1472:
12’d1473:
12’d1474:
12’d1475:
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
158
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=
=
=
=
=
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=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
76’d9522993250338384896;
76’d9522993250338384896;
76’d9522993250338384896;
76’d9522571037873317888;
76’d9522148825407726592;
76’d9521726612942659584;
76’d9521304400477068288;
76’d9520882188012001280;
76’d9664575163622790144;
76’d9664293688646078464;
76’d9807986664256343040;
76’d9951679639867131904;
76’d9951257427402064384;
76’d10094950403012853248;
76’d10238784115843561474;
76’d10382477090917479429;
76’d10526169791113489928;
76’d84601094436834011659;
76’d232318739451560092686;
76’d306249408171716402706;
76’d380324332817168488469;
76’d528186093019970949657;
76’d675903878771916950557;
76’d749978662679880680993;
76’d897840422607536275494;
76’d1045702323547558656554;
76’d1193564083750092157999;
76’d1341425984415236107828;
76’d1489287744617501697593;
76’d1711080736765291274302;
76’d1858942637705045219396;
76’d1858942637705045219396;
76’d1858942637705045219396;
76’d1858942637705045219396;
76’d1858942637705045219396;
76’d1858942637705045219396;
76’d1858942637705045219396;
76’d1858942637705045219396;
76’d1858942637705045219396;
76’d1858942637705045219396;
76’d1858942637705045219396;
76’d1858942637705045219396;
76’d8080715469677704704;
76’d8080715469677704704;
76’d8080715469677704704;
76’d8080715469677704704;
1488
1489
1490
1491
1492
1493
1494
1495
1496
1497
1498
1499
1500
1501
1502
1503
1504
1505
1506
1507
1508
1509
1510
1511
1512
1513
1514
1515
1516
1517
1518
1519
1520
1521
1522
1523
1524
1525
1526
1527
1528
1529
1530
1531
1532
1533
12’d1476:
12’d1477:
12’d1478:
12’d1479:
12’d1480:
12’d1481:
12’d1482:
12’d1483:
12’d1484:
12’d1485:
12’d1486:
12’d1487:
12’d1488:
12’d1489:
12’d1490:
12’d1491:
12’d1492:
12’d1493:
12’d1494:
12’d1495:
12’d1496:
12’d1497:
12’d1498:
12’d1499:
12’d1500:
12’d1501:
12’d1502:
12’d1503:
12’d1504:
12’d1505:
12’d1506:
12’d1507:
12’d1508:
12’d1509:
12’d1510:
12’d1511:
12’d1512:
12’d1513:
12’d1514:
12’d1515:
12’d1516:
12’d1517:
12’d1518:
12’d1519:
12’d1520:
12’d1521:
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
159
=
=
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=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
76’d8080715469677704704;
76’d8080715469677704704;
76’d8080715469677704704;
76’d8080715469677704704;
76’d8080715469677704704;
76’d8080715469677704704;
76’d8080715469677704704;
76’d8080715469677704704;
76’d8080715469677704704;
76’d8080715469677704704;
76’d8080715469677704704;
76’d8080715469677704704;
76’d8080715469677704704;
76’d8080715469677704704;
76’d8080715469677704704;
76’d8080715469677704704;
76’d8080715469677704704;
76’d8080715469677704704;
76’d8080715469677704704;
76’d8080715469677704704;
76’d8080715469677704704;
76’d8080433994700993536;
76’d8080011782235402240;
76’d8223704757846191104;
76’d8223282545380599808;
76’d8367116258479744000;
76’d8366694046014676992;
76’d8510387021625465856;
76’d8654220734724085760;
76’d8797913710334874624;
76’d8941606685945663488;
76’d9085440399044807680;
76’d9229133374655596034;
76’d9517082275562160645;
76’d9660775250904514056;
76’d157522676466341148683;
76’d231453345461106930190;
76’d305528270106827451922;
76’d453390171047386179606;
76’d527464954955350434841;
76’d675326856170518634014;
76’d823188757110808926242;
76’d971050517313610863142;
76’d1119056533441709100075;
76’d1266918434381999392304;
76’d1414924450510097104949;
1534
1535
1536
1537
1538
1539
1540
1541
1542
1543
1544
1545
1546
1547
1548
1549
1550
1551
1552
1553
1554
1555
1556
1557
1558
1559
1560
1561
1562
1563
1564
1565
1566
1567
1568
1569
1570
1571
1572
1573
1574
1575
1576
1577
1578
1579
12’d1522:
12’d1523:
12’d1524:
12’d1525:
12’d1526:
12’d1527:
12’d1528:
12’d1529:
12’d1530:
12’d1531:
12’d1532:
12’d1533:
12’d1534:
12’d1535:
12’d1536:
12’d1537:
12’d1538:
12’d1539:
12’d1540:
12’d1541:
12’d1542:
12’d1543:
12’d1544:
12’d1545:
12’d1546:
12’d1547:
12’d1548:
12’d1549:
12’d1550:
12’d1551:
12’d1552:
12’d1553:
12’d1554:
12’d1555:
12’d1556:
12’d1557:
12’d1558:
12’d1559:
12’d1560:
12’d1561:
12’d1562:
12’d1563:
12’d1564:
12’d1565:
12’d1566:
12’d1567:
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
160
=
=
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=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
76’d1562930466363317434938;
76’d1784579343598177498176;
76’d1932585359726007299653;
76’d1932585359726007299653;
76’d1932585359726007299653;
76’d1932585359726007299653;
76’d1932585359726007299653;
76’d1932585359726007299653;
76’d1932585359726007299653;
76’d1932585359726007299653;
76’d1932585359726007299653;
76’d1932585359726007299653;
76’d1932585359726007299653;
76’d1932585359726007299653;
76’d6782834352069067264;
76’d6782834352069067264;
76’d6782834352069067264;
76’d6782834352069067264;
76’d6782834352069067264;
76’d6782834352069067264;
76’d6782834352069067264;
76’d6782834352069067264;
76’d6782834352069067264;
76’d6782834352069067264;
76’d6782834352069067264;
76’d6782834352069067264;
76’d6782834352069067264;
76’d6782834352069067264;
76’d6782834352069067264;
76’d6782834352069067264;
76’d6782834352069067264;
76’d6782834352069067264;
76’d6782834352069067264;
76’d6782834352069067264;
76’d6782834352069067264;
76’d6782834352069067264;
76’d6782834352069067264;
76’d6782834352069067264;
76’d6782834352069067264;
76’d6926527327679856128;
76’d6926105115214789120;
76’d6925682902749198336;
76’d7069516615848342528;
76’d7213209591459131392;
76’d7212928116481895424;
76’d7356621092092684288;
1580
1581
1582
1583
1584
1585
1586
1587
1588
1589
1590
1591
1592
1593
1594
1595
1596
1597
1598
1599
1600
1601
1602
1603
1604
1605
1606
1607
1608
1609
1610
1611
1612
1613
1614
1615
1616
1617
1618
1619
1620
1621
1622
1623
1624
1625
12’d1568:
12’d1569:
12’d1570:
12’d1571:
12’d1572:
12’d1573:
12’d1574:
12’d1575:
12’d1576:
12’d1577:
12’d1578:
12’d1579:
12’d1580:
12’d1581:
12’d1582:
12’d1583:
12’d1584:
12’d1585:
12’d1586:
12’d1587:
12’d1588:
12’d1589:
12’d1590:
12’d1591:
12’d1592:
12’d1593:
12’d1594:
12’d1595:
12’d1596:
12’d1597:
12’d1598:
12’d1599:
12’d1600:
12’d1601:
12’d1602:
12’d1603:
12’d1604:
12’d1605:
12’d1606:
12’d1607:
12’d1608:
12’d1609:
12’d1610:
12’d1611:
12’d1612:
12’d1613:
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
161
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=
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=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
76’d7500454805191828480;
76’d7788262968878473216;
76’d7932096681977617408;
76’d8075789657588406272;
76’d8363738558763406338;
76’d8507572271862550533;
76’d82582497467607321096;
76’d156657281925863736843;
76’d230732207121340072463;
76’d378594108061898800146;
76’d452669032982497228822;
76’d600675049111131812378;
76’d748536950326300012062;
76’d896398851266859264035;
76’d1044404867395225412135;
76’d1192410883798469467692;
76’d1340416899926835615793;
76’d1488422916054933852726;
76’d1636428932183300000827;
76’d1858221924881114351169;
76’d2006228081746700419143;
76’d2006228081746700419143;
76’d2006228081746700419143;
76’d2006228081746700419143;
76’d2006228081746700419143;
76’d2006228081746700419143;
76’d2006228081746700419143;
76’d2006228081746700419143;
76’d2006228081746700419143;
76’d2006228081746700419143;
76’d2006228081746700419143;
76’d2006228081746700419143;
76’d5628927685047929344;
76’d5628927685047929344;
76’d5628927685047929344;
76’d5628927685047929344;
76’d5628927685047929344;
76’d5628927685047929344;
76’d5628927685047929344;
76’d5628927685047929344;
76’d5628927685047929344;
76’d5628927685047929344;
76’d5628927685047929344;
76’d5628927685047929344;
76’d5628927685047929344;
76’d5628927685047929344;
1626
1627
1628
1629
1630
1631
1632
1633
1634
1635
1636
1637
1638
1639
1640
1641
1642
1643
1644
1645
1646
1647
1648
1649
1650
1651
1652
1653
1654
1655
1656
1657
1658
1659
1660
1661
1662
1663
1664
1665
1666
1667
1668
1669
1670
1671
12’d1614:
12’d1615:
12’d1616:
12’d1617:
12’d1618:
12’d1619:
12’d1620:
12’d1621:
12’d1622:
12’d1623:
12’d1624:
12’d1625:
12’d1626:
12’d1627:
12’d1628:
12’d1629:
12’d1630:
12’d1631:
12’d1632:
12’d1633:
12’d1634:
12’d1635:
12’d1636:
12’d1637:
12’d1638:
12’d1639:
12’d1640:
12’d1641:
12’d1642:
12’d1643:
12’d1644:
12’d1645:
12’d1646:
12’d1647:
12’d1648:
12’d1649:
12’d1650:
12’d1651:
12’d1652:
12’d1653:
12’d1654:
12’d1655:
12’d1656:
12’d1657:
12’d1658:
12’d1659:
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
162
=
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=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
76’d5628927685047929344;
76’d5628927685047929344;
76’d5628927685047929344;
76’d5628927685047929344;
76’d5628927685047929344;
76’d5628927685047929344;
76’d5628927685047929344;
76’d5628927685047929344;
76’d5628927685047929344;
76’d5628927685047929344;
76’d5628927685047929344;
76’d5628505472582862848;
76’d5772339185681482752;
76’d5771916973216416256;
76’d5915750686315560448;
76’d6059443661926349312;
76’d6203277375024969728;
76’d6346970350635758592;
76’d6490804063734902784;
76’d6778752964909902848;
76’d6922586678009047040;
76’d7210394841695691776;
76’d7498343742870691842;
76’d7642177455969836037;
76’d155504078946821249033;
76’d229723119330910311436;
76’d303798044526386647055;
76’d451659946016969624083;
76’d525878986125643908631;
76’d673740887341080543771;
76’d821747044207203482655;
76’d969753060610716497956;
76’d1117759077013960553000;
76’d1265765233880083492397;
76’d1413771250283328071730;
76’d1561921381599770076216;
76’d1783714515035340693053;
76’d1931864646351783221315;
76’d2153657779787085402696;
76’d2153657779787085402696;
76’d2153657779787085402696;
76’d2153657779787085402696;
76’d2153657779787085402696;
76’d2153657779787085402696;
76’d2153657779787085402696;
76’d2153657779787085402696;
1672
1673
1674
1675
1676
1677
1678
1679
1680
1681
1682
1683
1684
1685
1686
1687
1688
1689
1690
1691
1692
1693
1694
1695
1696
1697
1698
1699
1700
1701
1702
1703
1704
1705
1706
1707
1708
1709
1710
1711
1712
1713
1714
1715
1716
1717
12’d1660:
12’d1661:
12’d1662:
12’d1663:
12’d1664:
12’d1665:
12’d1666:
12’d1667:
12’d1668:
12’d1669:
12’d1670:
12’d1671:
12’d1672:
12’d1673:
12’d1674:
12’d1675:
12’d1676:
12’d1677:
12’d1678:
12’d1679:
12’d1680:
12’d1681:
12’d1682:
12’d1683:
12’d1684:
12’d1685:
12’d1686:
12’d1687:
12’d1688:
12’d1689:
12’d1690:
12’d1691:
12’d1692:
12’d1693:
12’d1694:
12’d1695:
12’d1696:
12’d1697:
12’d1698:
12’d1699:
12’d1700:
12’d1701:
12’d1702:
12’d1703:
12’d1704:
12’d1705:
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
163
=
=
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=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
76’d2153657779787085402696;
76’d2153657779787085402696;
76’d2153657779787085402696;
76’d2153657779787085402696;
76’d4475161754978276352;
76’d4475161754978276352;
76’d4475161754978276352;
76’d4475161754978276352;
76’d4475161754978276352;
76’d4475161754978276352;
76’d4475161754978276352;
76’d4475161754978276352;
76’d4475161754978276352;
76’d4475161754978276352;
76’d4475161754978276352;
76’d4475161754978276352;
76’d4475161754978276352;
76’d4475161754978276352;
76’d4475161754978276352;
76’d4475161754978276352;
76’d4475161754978276352;
76’d4475161754978276352;
76’d4475161754978276352;
76’d4475161754978276352;
76’d4475161754978276352;
76’d4475161754978276352;
76’d4475161754978276352;
76’d4475161754978276352;
76’d4475161754978276352;
76’d4618854731125412352;
76’d4618573256148700672;
76’d4762266231759490048;
76’d4906099944858109952;
76’d5049933657957254144;
76’d5193626633568043520;
76’d5337460346667187712;
76’d5625409247841663488;
76’d5769242960940808192;
76’d6057191862115808256;
76’d6345140763290808320;
76’d6633089664465808387;
76’d80708014860479014918;
76’d154782940056492221449;
76’d302644841547343634445;
76’d376863881931432696848;
76’d524725924159504029716;
1718
1719
1720
1721
1722
1723
1724
1725
1726
1727
1728
1729
1730
1731
1732
1733
1734
1735
1736
1737
1738
1739
1740
1741
1742
1743
1744
1745
1746
1747
1748
1749
1750
1751
1752
1753
1754
1755
1756
1757
1758
1759
1760
1761
1762
1763
12’d1706:
12’d1707:
12’d1708:
12’d1709:
12’d1710:
12’d1711:
12’d1712:
12’d1713:
12’d1714:
12’d1715:
12’d1716:
12’d1717:
12’d1718:
12’d1719:
12’d1720:
12’d1721:
12’d1722:
12’d1723:
12’d1724:
12’d1725:
12’d1726:
12’d1727:
12’d1728:
12’d1729:
12’d1730:
12’d1731:
12’d1732:
12’d1733:
12’d1734:
12’d1735:
12’d1736:
12’d1737:
12’d1738:
12’d1739:
12’d1740:
12’d1741:
12’d1742:
12’d1743:
12’d1744:
12’d1745:
12’d1746:
12’d1747:
12’d1748:
12’d1749:
12’d1750:
12’d1751:
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
164
=
=
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=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
76’d598944964543056221208;
76’d746950980946837671964;
76’d894957138087838517792;
76’d1042963154491351008805;
76’d1191113426820427711018;
76’d1339119443223940725807;
76’d1487269715553017428020;
76’d1709062848988588045369;
76’d1857213121317665271358;
76’d2005363252634107275844;
76’d2227300501257754272842;
76’d2227300501257754272842;
76’d2227300501257754272842;
76’d2227300501257754272842;
76’d2227300501257754272842;
76’d2227300501257754272842;
76’d2227300501257754272842;
76’d2227300501257754272842;
76’d2227300501257754272842;
76’d2227300501257754272842;
76’d2227300501257754272842;
76’d2227300501257754272842;
76’d3465511012983430144;
76’d3465511012983430144;
76’d3465511012983430144;
76’d3465511012983430144;
76’d3465511012983430144;
76’d3465511012983430144;
76’d3465511012983430144;
76’d3465511012983430144;
76’d3465511012983430144;
76’d3465511012983430144;
76’d3465511012983430144;
76’d3465511012983430144;
76’d3465511012983430144;
76’d3465511012983430144;
76’d3465511012983430144;
76’d3465511012983430144;
76’d3465511012983430144;
76’d3465511012983430144;
76’d3465511012983430144;
76’d3465511012983430144;
76’d3465511012983430144;
76’d3465511012983430144;
76’d3465511012983430144;
76’d3465511012983430144;
1764
1765
1766
1767
1768
1769
1770
1771
1772
1773
1774
1775
1776
1777
1778
1779
1780
1781
1782
1783
1784
1785
1786
1787
1788
1789
1790
1791
1792
1793
1794
1795
1796
1797
1798
1799
1800
1801
1802
1803
1804
1805
1806
1807
1808
1809
12’d1752:
12’d1753:
12’d1754:
12’d1755:
12’d1756:
12’d1757:
12’d1758:
12’d1759:
12’d1760:
12’d1761:
12’d1762:
12’d1763:
12’d1764:
12’d1765:
12’d1766:
12’d1767:
12’d1768:
12’d1769:
12’d1770:
12’d1771:
12’d1772:
12’d1773:
12’d1774:
12’d1775:
12’d1776:
12’d1777:
12’d1778:
12’d1779:
12’d1780:
12’d1781:
12’d1782:
12’d1783:
12’d1784:
12’d1785:
12’d1786:
12’d1787:
12’d1788:
12’d1789:
12’d1790:
12’d1791:
12’d1792:
12’d1793:
12’d1794:
12’d1795:
12’d1796:
12’d1797:
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
165
=
=
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=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
76’d3465511012983430144;
76’d3609344726351010304;
76’d3608922514154379264;
76’d3752756227789870080;
76’d3896589940889014784;
76’d4040282916499803648;
76’d4328231817674804224;
76’d4472065530773424128;
76’d4760014431948424192;
76’d4903848145047568896;
76’d5191797046222568960;
76’d5479745947397569026;
76’d79554671143410776068;
76’d227416713371750544391;
76’d301635753755839606795;
76’d375710678951852813326;
76’d449929860073430231058;
76’d597935876752357499925;
76’d745942034168505212953;
76’d820161074552325839901;
76’d968167231968473028642;
76’d1116317504297549730854;
76’d1264323661438819536939;
76’d1412473933767896239152;
76’d1634411182391811147317;
76’d1782561454995766280763;
76’d1930711727324842982976;
76’d2152648975948489455686;
76’d2374730339760480744524;
76’d2374730339760480744524;
76’d2374730339760480744524;
76’d2374730339760480744524;
76’d2374730339760480744524;
76’d2374730339760480744524;
76’d2374730339760480744524;
76’d2374730339760480744524;
76’d2374730339760480744524;
76’d2374730339760480744524;
76’d2374730339760480744524;
76’d2374730339760480744524;
76’d2600116196284883968;
76’d2600116196284883968;
76’d2600116196284883968;
76’d2600116196284883968;
76’d2600116196284883968;
76’d2600116196284883968;
1810
1811
1812
1813
1814
1815
1816
1817
1818
1819
1820
1821
1822
1823
1824
1825
1826
1827
1828
1829
1830
1831
1832
1833
1834
1835
1836
1837
1838
1839
1840
1841
1842
1843
1844
1845
1846
1847
1848
1849
1850
1851
1852
1853
1854
1855
12’d1798:
12’d1799:
12’d1800:
12’d1801:
12’d1802:
12’d1803:
12’d1804:
12’d1805:
12’d1806:
12’d1807:
12’d1808:
12’d1809:
12’d1810:
12’d1811:
12’d1812:
12’d1813:
12’d1814:
12’d1815:
12’d1816:
12’d1817:
12’d1818:
12’d1819:
12’d1820:
12’d1821:
12’d1822:
12’d1823:
12’d1824:
12’d1825:
12’d1826:
12’d1827:
12’d1828:
12’d1829:
12’d1830:
12’d1831:
12’d1832:
12’d1833:
12’d1834:
12’d1835:
12’d1836:
12’d1837:
12’d1838:
12’d1839:
12’d1840:
12’d1841:
12’d1842:
12’d1843:
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
166
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
76’d2600116196284883968;
76’d2600116196284883968;
76’d2600116196284883968;
76’d2600116196284883968;
76’d2600116196284883968;
76’d2600116196284883968;
76’d2600116196284883968;
76’d2600116196284883968;
76’d2600116196284883968;
76’d2600116196284883968;
76’d2600116196284883968;
76’d2600116196284883968;
76’d2600116196284883968;
76’d2600116196284883968;
76’d2600116196284883968;
76’d2600116196284883968;
76’d2600116196284883968;
76’d2600116196284883968;
76’d2600116196284883968;
76’d2599693984356164096;
76’d2743527697723744256;
76’d2887361411091323904;
76’d3031195124726815232;
76’d3174888100606040064;
76’d3462837001781040128;
76’d3606670714880184832;
76’d3894619616055184896;
76’d4182709254718540800;
76’d78257634450731747328;
76’d152332559646744953859;
76’d226407484842758160902;
76’d300626665964335578633;
76’d374701591160348785164;
76’d522707748576764409872;
76’d596926788960853472275;
76’d744932946377269096471;
76’d819152127498846514203;
76’d967158284915262138399;
76’d1115308557519485707299;
76’d1263314714935632896040;
76’d1411464987539587505197;
76’d1559615259868932642866;
76’d1707765532198009869367;
76’d1929702781097071120444;
76’d2077997309351712558146;
76’d2299934557975627466824;
1856
1857
1858
1859
1860
1861
1862
1863
1864
1865
1866
1867
1868
1869
1870
1871
1872
1873
1874
1875
1876
1877
1878
1879
1880
1881
1882
1883
1884
1885
1886
1887
1888
1889
1890
1891
1892
1893
1894
1895
1896
1897
1898
1899
1900
1901
12’d1844:
12’d1845:
12’d1846:
12’d1847:
12’d1848:
12’d1849:
12’d1850:
12’d1851:
12’d1852:
12’d1853:
12’d1854:
12’d1855:
12’d1856:
12’d1857:
12’d1858:
12’d1859:
12’d1860:
12’d1861:
12’d1862:
12’d1863:
12’d1864:
12’d1865:
12’d1866:
12’d1867:
12’d1868:
12’d1869:
12’d1870:
12’d1871:
12’d1872:
12’d1873:
12’d1874:
12’d1875:
12’d1876:
12’d1877:
12’d1878:
12’d1879:
12’d1880:
12’d1881:
12’d1882:
12’d1883:
12’d1884:
12’d1885:
12’d1886:
12’d1887:
12’d1888:
12’d1889:
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
167
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
76’d2448229086505146811469;
76’d2448229086505146811469;
76’d2448229086505146811469;
76’d2448229086505146811469;
76’d2448229086505146811469;
76’d2448229086505146811469;
76’d2448229086505146811469;
76’d2448229086505146811469;
76’d2448229086505146811469;
76’d2448229086505146811469;
76’d2448229086505146811469;
76’d2448229086505146811469;
76’d1734721379585289216;
76’d1734721379585289216;
76’d1734721379585289216;
76’d1734721379585289216;
76’d1734721379585289216;
76’d1734721379585289216;
76’d1734721379585289216;
76’d1734721379585289216;
76’d1734721379585289216;
76’d1734721379585289216;
76’d1734721379585289216;
76’d1734721379585289216;
76’d1734721379585289216;
76’d1734721379585289216;
76’d1734721379585289216;
76’d1734721379585289216;
76’d1734721379585289216;
76’d1734721379585289216;
76’d1734721379585289216;
76’d1734721379585289216;
76’d1734721379585289216;
76’d1734721379585289216;
76’d1734721379585289216;
76’d1734721379585289216;
76’d1734721379585289216;
76’d1734299167657093632;
76’d1878132881024673280;
76’d2021966594660164608;
76’d2165800308027744768;
76’d2453749209471180800;
76’d2597582923107195904;
76’d2885531824550631936;
76’d76960457020563838976;
76’d151035382216577045504;
1902
1903
1904
1905
1906
1907
1908
1909
1910
1911
1912
1913
1914
1915
1916
1917
1918
1919
1920
1921
1922
1923
1924
1925
1926
1927
1928
1929
1930
1931
1932
1933
1934
1935
1936
1937
1938
1939
1940
1941
1942
1943
1944
1945
1946
1947
12’d1890:
12’d1891:
12’d1892:
12’d1893:
12’d1894:
12’d1895:
12’d1896:
12’d1897:
12’d1898:
12’d1899:
12’d1900:
12’d1901:
12’d1902:
12’d1903:
12’d1904:
12’d1905:
12’d1906:
12’d1907:
12’d1908:
12’d1909:
12’d1910:
12’d1911:
12’d1912:
12’d1913:
12’d1914:
12’d1915:
12’d1916:
12’d1917:
12’d1918:
12’d1919:
12’d1920:
12’d1921:
12’d1922:
12’d1923:
12’d1924:
12’d1925:
12’d1926:
12’d1927:
12’d1928:
12’d1929:
12’d1930:
12’d1931:
12’d1932:
12’d1933:
12’d1934:
12’d1935:
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
168
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
76’d225110448150078607874;
76’d299185373346091290117;
76’d373260439279593376776;
76’d447479479663682439179;
76’d521698660785259857422;
76’d595773726718761419281;
76’d743779884135177043477;
76’d818143039707341962265;
76’d966149197123757586461;
76’d1114299469728249066529;
76’d1188518791587315363877;
76’d1336669064191806843946;
76’d1484819336796029889071;
76’d1706756585694823228980;
76’d1854906999036534628921;
76’d2003201386553955622462;
76’d2225138776190237317700;
76’d2373433304445146666569;
76’d2595514668532015862351;
76’d2595514668532015862351;
76’d2595514668532015862351;
76’d2595514668532015862351;
76’d2595514668532015862351;
76’d2595514668532015862351;
76’d2595514668532015862351;
76’d2595514668532015862351;
76’d2595514668532015862351;
76’d2595514668532015862351;
76’d2595514668532015862351;
76’d2595514668532015862351;
76’d74656302857723900416;
76’d74656302857723900416;
76’d74656302857723900416;
76’d74656302857723900416;
76’d74656302857723900416;
76’d74656302857723900416;
76’d74656302857723900416;
76’d74656302857723900416;
76’d74656302857723900416;
76’d74656302857723900416;
76’d74656302857723900416;
76’d74656302857723900416;
76’d74656302857723900416;
76’d74656302857723900416;
76’d74656302857723900416;
76’d74656302857723900416;
1948
1949
1950
1951
1952
1953
1954
1955
1956
1957
1958
1959
1960
1961
1962
1963
1964
1965
1966
1967
1968
1969
1970
1971
1972
1973
1974
1975
1976
1977
1978
1979
1980
1981
1982
1983
1984
1985
1986
1987
1988
1989
1990
1991
1992
1993
12’d1936:
12’d1937:
12’d1938:
12’d1939:
12’d1940:
12’d1941:
12’d1942:
12’d1943:
12’d1944:
12’d1945:
12’d1946:
12’d1947:
12’d1948:
12’d1949:
12’d1950:
12’d1951:
12’d1952:
12’d1953:
12’d1954:
12’d1955:
12’d1956:
12’d1957:
12’d1958:
12’d1959:
12’d1960:
12’d1961:
12’d1962:
12’d1963:
12’d1964:
12’d1965:
12’d1966:
12’d1967:
12’d1968:
12’d1969:
12’d1970:
12’d1971:
12’d1972:
12’d1973:
12’d1974:
12’d1975:
12’d1976:
12’d1977:
12’d1978:
12’d1979:
12’d1980:
12’d1981:
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
169
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
76’d74656302857723900416;
76’d74656302857723900416;
76’d74656302857723900416;
76’d74656302857723900416;
76’d74656302857723900416;
76’d74656302857723900416;
76’d74656302857723900416;
76’d74656302857723900416;
76’d74656302857723900416;
76’d74800136571359916032;
76’d74943829547507576320;
76’d75087663260875156480;
76’d75231496974510647296;
76’d149306422170792289792;
76’d149450396621648225280;
76’d223525321818198303232;
76’d223813270719641739264;
76’d297888336653143301122;
76’d371963261849424943620;
76’d446038327782926505991;
76’d520257368167015568394;
76’d594332434100517130765;
76’d668551615222094548496;
76’d742770796343671966739;
76’d890776953760087590935;
76’d965140250069741389339;
76’d1113146407486157013535;
76’d1261296680090648493603;
76’d1335660117137790123047;
76’d1483810389742282127404;
76’d1631960662346773607473;
76’d1853898051983323214389;
76’d2002192580513110994491;
76’d2150342853117334039104;
76’d2372424357941960025669;
76’d2520718886471747281483;
76’d2742800391296373268561;
76’d2742800391296373268561;
76’d2742800391296373268561;
76’d2742800391296373268561;
76’d2742800391296373268561;
76’d2742800391296373268561;
76’d2742800391296373268561;
76’d2742800391296373268561;
76’d2742800391296373268561;
76’d2742800391296373268561;
1994
1995
1996
1997
1998
1999
2000
2001
2002
2003
2004
2005
2006
2007
2008
2009
2010
2011
2012
2013
2014
2015
2016
2017
2018
2019
2020
2021
2022
2023
2024
2025
2026
2027
2028
2029
2030
2031
2032
2033
2034
2035
2036
2037
2038
2039
12’d1982:
12’d1983:
12’d1984:
12’d1985:
12’d1986:
12’d1987:
12’d1988:
12’d1989:
12’d1990:
12’d1991:
12’d1992:
12’d1993:
12’d1994:
12’d1995:
12’d1996:
12’d1997:
12’d1998:
12’d1999:
12’d2000:
12’d2001:
12’d2002:
12’d2003:
12’d2004:
12’d2005:
12’d2006:
12’d2007:
12’d2008:
12’d2009:
12’d2010:
12’d2011:
12’d2012:
12’d2013:
12’d2014:
12’d2015:
12’d2016:
12’d2017:
12’d2018:
12’d2019:
12’d2020:
12’d2021:
12’d2022:
12’d2023:
12’d2024:
12’d2025:
12’d2026:
12’d2027:
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
170
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
76’d2742800391296373268561;
76’d2742800391296373268561;
76’d221508975818776573952;
76’d221508975818776573952;
76’d221508975818776573952;
76’d221508975818776573952;
76’d221508975818776573952;
76’d221508975818776573952;
76’d221508975818776573952;
76’d221508975818776573952;
76’d221508975818776573952;
76’d221508975818776573952;
76’d221508975818776573952;
76’d221508975818776573952;
76’d221508975818776573952;
76’d221508975818776573952;
76’d221508975818776573952;
76’d221508975818776573952;
76’d221508975818776573952;
76’d221508975818776573952;
76’d221508975818776573952;
76’d221508975818776573952;
76’d221508975818776573952;
76’d221508975818776573952;
76’d221508975818776573952;
76’d221508975818776573952;
76’d221508975818776573952;
76’d221652809532412589568;
76’d221796643246048605184;
76’d221940476959415661056;
76’d295871286967889883136;
76’d296159235869601754624;
76’d296447325508533545984;
76’d370378135516739332096;
76’d370666225155939558914;
76’d444741150352221201413;
76’d518960331474067055111;
76’d593035256670080262154;
76’d667254437791926115340;
76’d741329503725427677711;
76’d815548684847005095955;
76’d963554842263420720150;
76’d1037918138573074518553;
76’d1112137460432140291613;
76’d1260287733036631772193;
76’d1408438005641123252261;
2040
2041
2042
2043
2044
2045
2046
2047
2048
2049
2050
2051
2052
2053
2054
2055
2056
2057
2058
2059
2060
2061
2062
2063
2064
2065
2066
2067
2068
2069
2070
2071
2072
2073
2074
2075
2076
2077
2078
2079
2080
2081
2082
2083
2084
2085
12’d2028:
12’d2029:
12’d2030:
12’d2031:
12’d2032:
12’d2033:
12’d2034:
12’d2035:
12’d2036:
12’d2037:
12’d2038:
12’d2039:
12’d2040:
12’d2041:
12’d2042:
12’d2043:
12’d2044:
12’d2045:
12’d2046:
12’d2047:
12’d2048:
12’d2049:
12’d2050:
12’d2051:
12’d2052:
12’d2053:
12’d2054:
12’d2055:
12’d2056:
12’d2057:
12’d2058:
12’d2059:
12’d2060:
12’d2061:
12’d2062:
12’d2063:
12’d2064:
12’d2065:
12’d2066:
12’d2067:
12’d2068:
12’d2069:
12’d2070:
12’d2071:
12’d2072:
12’d2073:
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
171
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
76’d1556444303795027756586;
76’d1704738691587595092526;
76’d1852889104929574928435;
76’d2001039518271555288120;
76’d2149334046801610979901;
76’d2297628575331398235714;
76’d2519565964967948366407;
76’d2668004608685811478093;
76’d2890086113510437465171;
76’d2890086113510437465171;
76’d2890086113510437465171;
76’d2890086113510437465171;
76’d2890086113510437465171;
76’d2890086113510437465171;
76’d2890086113510437465171;
76’d2890086113510437465171;
76’d2890086113510437465171;
76’d2890086113510437465171;
76’d2890086113510437465171;
76’d2890086113510437465171;
76’d442725226289312365568;
76’d442725226289312365568;
76’d442725226289312365568;
76’d442725226289312365568;
76’d442725226289312365568;
76’d442725226289312365568;
76’d442725226289312365568;
76’d442725226289312365568;
76’d442725226289312365568;
76’d442725226289312365568;
76’d442725226289312365568;
76’d442725226289312365568;
76’d442725226289312365568;
76’d442725226289312365568;
76’d442725226289312365568;
76’d442725226289312365568;
76’d442725226289312365568;
76’d442725226289312365568;
76’d442725226289312365568;
76’d442725226289312365568;
76’d442725226289312365568;
76’d442725226289312365568;
76’d442725226289312365568;
76’d442725226289312365568;
76’d442725226289312365568;
76’d442724944539994618880;
2086
2087
2088
2089
2090
2091
2092
2093
2094
2095
2096
2097
2098
2099
2100
2101
2102
2103
2104
2105
2106
2107
2108
2109
2110
2111
2112
2113
2114
2115
2116
2117
2118
2119
2120
2121
2122
2123
2124
2125
2126
2127
2128
2129
2130
2131
12’d2074:
12’d2075:
12’d2076:
12’d2077:
12’d2078:
12’d2079:
12’d2080:
12’d2081:
12’d2082:
12’d2083:
12’d2084:
12’d2085:
12’d2086:
12’d2087:
12’d2088:
12’d2089:
12’d2090:
12’d2091:
12’d2092:
12’d2093:
12’d2094:
12’d2095:
12’d2096:
12’d2097:
12’d2098:
12’d2099:
12’d2100:
12’d2101:
12’d2102:
12’d2103:
12’d2104:
12’d2105:
12’d2106:
12’d2107:
12’d2108:
12’d2109:
12’d2110:
12’d2111:
12’d2112:
12’d2113:
12’d2114:
12’d2115:
12’d2116:
12’d2117:
12’d2118:
12’d2119:
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
172
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
76’d442724663065554778624;
76’d442724381591114938368;
76’d442868356042238785024;
76’d516943281238788862976;
76’d517087114952156443138;
76’d517375204591356669955;
76’d591450129787638312453;
76’d665525195721408309768;
76’d739744376843522598922;
76’d740032466482454390285;
76’d814251506866543977487;
76’d962257805020716392978;
76’d1036476986142562246677;
76’d1110696167539017571353;
76’d1184915348660594989596;
76’d1333065762002574825504;
76’d1407284943124152767524;
76’d1555435356466132603432;
76’d1703585769808112439340;
76’d1851736183150092799024;
76’d2000030711955026397749;
76’d2148181125297006233146;
76’d2296475653827062449215;
76’d2444770182357118140484;
76’d2666851687182012038729;
76’d2815146215711799294543;
76’d3037227720536424756821;
76’d3037227720536424756821;
76’d3037227720536424756821;
76’d3037227720536424756821;
76’d3037227720536424756821;
76’d3037227720536424756821;
76’d3037227720536424756821;
76’d3037227720536424756821;
76’d3037227720536424756821;
76’d3037227720536424756821;
76’d3037227720536424756821;
76’d3037227720536424756821;
76’d664085591123558202880;
76’d664085591123558202880;
76’d664085591123558202880;
76’d664085591123558202880;
76’d664085591123558202880;
76’d664085591123558202880;
76’d664085591123558202880;
76’d664085591123558202880;
2132
2133
2134
2135
2136
2137
2138
2139
2140
2141
2142
2143
2144
2145
2146
2147
2148
2149
2150
2151
2152
2153
2154
2155
2156
2157
2158
2159
2160
2161
2162
2163
2164
2165
2166
2167
2168
2169
2170
2171
2172
2173
2174
2175
2176
2177
12’d2120:
12’d2121:
12’d2122:
12’d2123:
12’d2124:
12’d2125:
12’d2126:
12’d2127:
12’d2128:
12’d2129:
12’d2130:
12’d2131:
12’d2132:
12’d2133:
12’d2134:
12’d2135:
12’d2136:
12’d2137:
12’d2138:
12’d2139:
12’d2140:
12’d2141:
12’d2142:
12’d2143:
12’d2144:
12’d2145:
12’d2146:
12’d2147:
12’d2148:
12’d2149:
12’d2150:
12’d2151:
12’d2152:
12’d2153:
12’d2154:
12’d2155:
12’d2156:
12’d2157:
12’d2158:
12’d2159:
12’d2160:
12’d2161:
12’d2162:
12’d2163:
12’d2164:
12’d2165:
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
173
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
76’d664085591123558202880;
76’d664085591123558202880;
76’d664085591123558202880;
76’d664085591123558202880;
76’d664085591123558202880;
76’d664085591123558202880;
76’d664085591123558202880;
76’d664085591123558202880;
76’d664085591123558202880;
76’d664085591123558202880;
76’d664085591123558202880;
76’d664085591123558202880;
76’d664085591123558202880;
76’d664085591123558202880;
76’d664085591123558202880;
76’d664085591123558202880;
76’d664085591123558202880;
76’d664085450386606718464;
76’d664085168912166878720;
76’d664084887437727038465;
76’d664084605963287198210;
76’d664084465226335713284;
76’d738015275234541500421;
76’d738303364873741727239;
76’d812378290070023369737;
76’d886453356004061803019;
76’d886741445642993594381;
76’d960960626764839447568;
76’d1035035692698609445395;
76’d1109254874095333206037;
76’d1183474055217179059736;
76’d1331624468559427331100;
76’d1405843790418761540127;
76’d1553994204035619282979;
76’d1628213525894685056039;
76’d1776363939236664891947;
76’d1924514352578644727855;
76’d1998877789900664263731;
76’d2147172318430719955512;
76’d2295322731772699791420;
76’d2517404236872471596097;
76’d2665698765402527287878;
76’d2813993294207460886092;
76’d3036074799032354784337;
76’d3184513442750486331479;
76’d3184513442750486331479;
2178
2179
2180
2181
2182
2183
2184
2185
2186
2187
2188
2189
2190
2191
2192
2193
2194
2195
2196
2197
2198
2199
2200
2201
2202
2203
2204
2205
2206
2207
2208
2209
2210
2211
2212
2213
2214
2215
2216
2217
2218
2219
2220
2221
2222
2223
12’d2166:
12’d2167:
12’d2168:
12’d2169:
12’d2170:
12’d2171:
12’d2172:
12’d2173:
12’d2174:
12’d2175:
12’d2176:
12’d2177:
12’d2178:
12’d2179:
12’d2180:
12’d2181:
12’d2182:
12’d2183:
12’d2184:
12’d2185:
12’d2186:
12’d2187:
12’d2188:
12’d2189:
12’d2190:
12’d2191:
12’d2192:
12’d2193:
12’d2194:
12’d2195:
12’d2196:
12’d2197:
12’d2198:
12’d2199:
12’d2200:
12’d2201:
12’d2202:
12’d2203:
12’d2204:
12’d2205:
12’d2206:
12’d2207:
12’d2208:
12’d2209:
12’d2210:
12’d2211:
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
174
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
76’d3184513442750486331479;
76’d3184513442750486331479;
76’d3184513442750486331479;
76’d3184513442750486331479;
76’d3184513442750486331479;
76’d3184513442750486331479;
76’d3184513442750486331479;
76’d3184513442750486331479;
76’d3184513442750486331479;
76’d3184513442750486331479;
76’d885446096420144479747;
76’d885446096420144479747;
76’d885446096420144479747;
76’d885446096420144479747;
76’d885446096420144479747;
76’d885446096420144479747;
76’d885446096420144479747;
76’d885446096420144479747;
76’d885446096420144479747;
76’d885446096420144479747;
76’d885446096420144479747;
76’d885446096420144479747;
76’d885446096420144479747;
76’d885446096420144479747;
76’d885446096420144479747;
76’d885446096420144479747;
76’d885446096420144479747;
76’d885446096420144479747;
76’d885446096420144479747;
76’d885446096420144479747;
76’d885446096420144479747;
76’d885446096420144479747;
76’d885446096420144479747;
76’d885446096420144479747;
76’d885446096420144479747;
76’d885445814945704640003;
76’d885445533471264800260;
76’d885445392734313315845;
76’d885445111534751383046;
76’d959231947092638105096;
76’d959231665618198264841;
76’d1033018501176084986379;
76’d1033306590815285213197;
76’d1107381656749055211023;
76’d1181456722957703115793;
76’d1181888927784979198483;
2224
2225
2226
2227
2228
2229
2230
2231
2232
2233
2234
2235
2236
2237
2238
2239
2240
2241
2242
2243
2244
2245
2246
2247
2248
2249
2250
2251
2252
2253
2254
2255
2256
2257
2258
2259
2260
2261
2262
2263
2264
2265
2266
2267
2268
2269
12’d2212:
12’d2213:
12’d2214:
12’d2215:
12’d2216:
12’d2217:
12’d2218:
12’d2219:
12’d2220:
12’d2221:
12’d2222:
12’d2223:
12’d2224:
12’d2225:
12’d2226:
12’d2227:
12’d2228:
12’d2229:
12’d2230:
12’d2231:
12’d2232:
12’d2233:
12’d2234:
12’d2235:
12’d2236:
12’d2237:
12’d2238:
12’d2239:
12’d2240:
12’d2241:
12’d2242:
12’d2243:
12’d2244:
12’d2245:
12’d2246:
12’d2247:
12’d2248:
12’d2249:
12’d2250:
12’d2251:
12’d2252:
12’d2253:
12’d2254:
12’d2255:
12’d2256:
12’d2257:
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
175
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
76’d1255963993718749196310;
76’d1330183315578083405337;
76’d1478189614007133727772;
76’d1552553051054543792671;
76’d1626772372913878001698;
76’d1700991695048090117670;
76’d1849142108390069953578;
76’d1997292522007196131885;
76’d2071655959054337761330;
76’d2219806372671195503670;
76’d2368100901201251195450;
76’d2516251314818108938303;
76’d2664545843348164630084;
76’d2812840372153098228297;
76’d3034921876977992126542;
76’d3183360520971001581139;
76’d3331655190238545627737;
76’d3331655190238545627737;
76’d3331655190238545627737;
76’d3331655190238545627737;
76’d3331655190238545627737;
76’d3331655190238545627737;
76’d3331655190238545627737;
76’d3331655190238545627737;
76’d3331655190238545627737;
76’d3331655190238545627737;
76’d3331655190238545627737;
76’d3331655190238545627737;
76’d1180593578011568963079;
76’d1180593578011568963079;
76’d1180593578011568963079;
76’d1180593578011568963079;
76’d1180593578011568963079;
76’d1180593578011568963079;
76’d1180593578011568963079;
76’d1180593578011568963079;
76’d1180593578011568963079;
76’d1180593578011568963079;
76’d1180593578011568963079;
76’d1180593578011568963079;
76’d1180593578011568963079;
76’d1180593578011568963079;
76’d1180593578011568963079;
76’d1180593578011568963079;
76’d1180593578011568963079;
76’d1180593578011568963079;
2270
2271
2272
2273
2274
2275
2276
2277
2278
2279
2280
2281
2282
2283
2284
2285
2286
2287
2288
2289
2290
2291
2292
2293
2294
2295
2296
2297
2298
2299
2300
2301
2302
2303
2304
2305
2306
2307
2308
2309
2310
2311
2312
2313
2314
2315
12’d2258:
12’d2259:
12’d2260:
12’d2261:
12’d2262:
12’d2263:
12’d2264:
12’d2265:
12’d2266:
12’d2267:
12’d2268:
12’d2269:
12’d2270:
12’d2271:
12’d2272:
12’d2273:
12’d2274:
12’d2275:
12’d2276:
12’d2277:
12’d2278:
12’d2279:
12’d2280:
12’d2281:
12’d2282:
12’d2283:
12’d2284:
12’d2285:
12’d2286:
12’d2287:
12’d2288:
12’d2289:
12’d2290:
12’d2291:
12’d2292:
12’d2293:
12’d2294:
12’d2295:
12’d2296:
12’d2297:
12’d2298:
12’d2299:
12’d2300:
12’d2301:
12’d2302:
12’d2303:
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
176
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=
76’d1180593578011568963079;
76’d1180593578011568963079;
76’d1180593578011568963079;
76’d1180593578011568963079;
76’d1180593578011568963079;
76’d1180593578011568963079;
76’d1180593578011568963079;
76’d1180593296812007030280;
76’d1180593015337567190537;
76’d1180592874600884141577;
76’d1180592593126444301835;
76’d1180592452389492817420;
76’d1254379288222257446413;
76’d1254379006747817606671;
76’d1328165842305435893265;
76’d1328309816756560264211;
76’d1402385023702964959765;
76’d1476604345562299168791;
76’d1550823667421633377818;
76’d1624898874368038073373;
76’d1699262311415448138272;
76’d1773481633549660254243;
76’d1847700955408994463270;
76’d1995851369026120641577;
76’d2070070690885186415149;
76’d2218221104502312593457;
76’d2292584541549722658357;
76’d2440879070354656257081;
76’d2589029483696904528445;
76’d2737324012501838127170;
76’d2885474426118695869510;
76’d3033768954648751561291;
76’d3182063483453685160016;
76’d3330502127446694614613;
76’d3552583773283954774619;
76’d3552583773283954774619;
76’d3552583773283954774619;
76’d3552583773283954774619;
76’d3552583773283954774619;
76’d3552583773283954774619;
76’d3552583773283954774619;
76’d3552583773283954774619;
76’d3552583773283954774619;
76’d3552583773283954774619;
76’d3552583773283954774619;
76’d3552583773283954774619;
2316
2317
2318
2319
2320
2321
2322
2323
2324
2325
2326
2327
2328
2329
2330
2331
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2333
2334
2335
2336
2337
2338
2339
2340
2341
2342
2343
2344
2345
2346
2347
2348
2349
2350
2351
2352
2353
2354
2355
2356
2357
2358
2359
2360
2361
12’d2304:
12’d2305:
12’d2306:
12’d2307:
12’d2308:
12’d2309:
12’d2310:
12’d2311:
12’d2312:
12’d2313:
12’d2314:
12’d2315:
12’d2316:
12’d2317:
12’d2318:
12’d2319:
12’d2320:
12’d2321:
12’d2322:
12’d2323:
12’d2324:
12’d2325:
12’d2326:
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12’d2328:
12’d2329:
12’d2330:
12’d2331:
12’d2332:
12’d2333:
12’d2334:
12’d2335:
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12’d2337:
12’d2338:
12’d2339:
12’d2340:
12’d2341:
12’d2342:
12’d2343:
12’d2344:
12’d2345:
12’d2346:
12’d2347:
12’d2348:
12’d2349:
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
177
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=
=
=
=
=
=
=
=
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=
=
=
=
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=
=
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=
=
=
=
=
=
=
=
=
=
=
76’d1475741059602993446412;
76’d1475741059602993446412;
76’d1475741059602993446412;
76’d1475741059602993446412;
76’d1475741059602993446412;
76’d1475741059602993446412;
76’d1475741059602993446412;
76’d1475741059602993446412;
76’d1475741059602993446412;
76’d1475741059602993446412;
76’d1475741059602993446412;
76’d1475741059602993446412;
76’d1475741059602993446412;
76’d1475741059602993446412;
76’d1475741059602993446412;
76’d1475741059602993446412;
76’d1475741059602993446412;
76’d1475741059602993446412;
76’d1475741059602993446412;
76’d1475741059602993446412;
76’d1475741059602993446412;
76’d1475741059602993446412;
76’d1475741059602993446412;
76’d1475741059602993446412;
76’d1475741059602993446412;
76’d1475740778403431513613;
76’d1475740637666480029197;
76’d1475740356192308624910;
76’d1475740215455357140495;
76’d1475740074993283563025;
76’d1475739793518843723282;
76’d1549526629076730445332;
76’d1549526629352145223190;
76’d1623313605647520300567;
76’d1697244697130702798362;
76’d1697677042970345143324;
76’d1771752249641603496478;
76’d1845971571776084048417;
76’d1920190893635418257444;
76’d1994410215769630373415;
76’d2142560629111878644778;
76’d2216779951246090760749;
76’d2291143388568378732593;
76’d2439293801910627003956;
76’d2513657239232914975800;
76’d2661807652849772718652;
2362
2363
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2366
2367
2368
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2371
2372
2373
2374
2375
2376
2377
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2379
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2384
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2386
2387
2388
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2391
2392
2393
2394
2395
2396
2397
2398
2399
2400
2401
2402
2403
2404
2405
2406
2407
12’d2350:
12’d2351:
12’d2352:
12’d2353:
12’d2354:
12’d2355:
12’d2356:
12’d2357:
12’d2358:
12’d2359:
12’d2360:
12’d2361:
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12’d2363:
12’d2364:
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12’d2366:
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12’d2368:
12’d2369:
12’d2370:
12’d2371:
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12’d2380:
12’d2381:
12’d2382:
12’d2383:
12’d2384:
12’d2385:
12’d2386:
12’d2387:
12’d2388:
12’d2389:
12’d2390:
12’d2391:
12’d2392:
12’d2393:
12’d2394:
12’d2395:
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
178
=
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=
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=
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=
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=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
76’d2809958066192020990016;
76’d2958252594996954588740;
76’d3106403008614080767049;
76’d3254697537419014365774;
76’d3402992065949070057042;
76’d3551286735491492011095;
76’d3699725520221989821021;
76’d3699725520221989821021;
76’d3699725520221989821021;
76’d3699725520221989821021;
76’d3699725520221989821021;
76’d3699725520221989821021;
76’d3699725520221989821021;
76’d3699725520221989821021;
76’d3699725520221989821021;
76’d3699725520221989821021;
76’d3699725520221989821021;
76’d3699725520221989821021;
76’d1770888681931637849618;
76’d1770888681931637849618;
76’d1770888681931637849618;
76’d1770888681931637849618;
76’d1770888681931637849618;
76’d1770888681931637849618;
76’d1770888681931637849618;
76’d1770888681931637849618;
76’d1770888681931637849618;
76’d1770888681931637849618;
76’d1770888681931637849618;
76’d1770888681931637849618;
76’d1770888681931637849618;
76’d1770888681931637849618;
76’d1770888681931637849618;
76’d1770888681931637849618;
76’d1770888681931637849618;
76’d1770888681931637849618;
76’d1770888681931637849618;
76’d1770888681931637849618;
76’d1770888681931637849618;
76’d1770888681931637849618;
76’d1770888681931637849618;
76’d1770888681931637849618;
76’d1770888681931637849618;
76’d1770888400457466445330;
76’d1770888259720514960915;
76’d1770887978521221463572;
2408
2409
2410
2411
2412
2413
2414
2415
2416
2417
2418
2419
2420
2421
2422
2423
2424
2425
2426
2427
2428
2429
2430
2431
2432
2433
2434
2435
2436
2437
2438
2439
2440
2441
2442
2443
2444
2445
2446
2447
2448
2449
2450
2451
2452
2453
12’d2396:
12’d2397:
12’d2398:
12’d2399:
12’d2400:
12’d2401:
12’d2402:
12’d2403:
12’d2404:
12’d2405:
12’d2406:
12’d2407:
12’d2408:
12’d2409:
12’d2410:
12’d2411:
12’d2412:
12’d2413:
12’d2414:
12’d2415:
12’d2416:
12’d2417:
12’d2418:
12’d2419:
12’d2420:
12’d2421:
12’d2422:
12’d2423:
12’d2424:
12’d2425:
12’d2426:
12’d2427:
12’d2428:
12’d2429:
12’d2430:
12’d2431:
12’d2432:
12’d2433:
12’d2434:
12’d2435:
12’d2436:
12’d2437:
12’d2438:
12’d2439:
12’d2440:
12’d2441:
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
179
=
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=
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=
=
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=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
76’d1770887837784269979157;
76’d1770887697047318494742;
76’d1844674532880083123735;
76’d1844674532880619994649;
76’d1844674533156034772507;
76’d1918461509451409849884;
76’d1992248486021662834206;
76’d1992536716398082981409;
76’d2066611923344487677475;
76’d2140831245203821887013;
76’d2215050567338302438440;
76’d2289269889197636647467;
76’d2363489211331848763438;
76’d2511639624948974941745;
76’d2585858946808309151284;
76’d2660222384130597123128;
76’d2808372797747723301436;
76’d2882736235070011273279;
76’d3030886648686869016131;
76’d3179181177217193143367;
76’d3327331590834050886220;
76’d3475626119639252920400;
76’d3623920648444186518613;
76’d3772215317986608472666;
76’d3920510128266518782047;
76’d3920510128266518782047;
76’d3920510128266518782047;
76’d3920510128266518782047;
76’d3920510128266518782047;
76’d3920510128266518782047;
76’d3920510128266518782047;
76’d3920510128266518782047;
76’d3920510128266518782047;
76’d3920510128266518782047;
76’d3920510128266518782047;
76’d3920510128266518782047;
76’d2139823280280510987800;
76’d2139823280280510987800;
76’d2139823280280510987800;
76’d2139823280280510987800;
76’d2139823280280510987800;
76’d2139823280280510987800;
76’d2139823280280510987800;
76’d2139823280280510987800;
76’d2139823280280510987800;
76’d2139823280280510987800;
2454
2455
2456
2457
2458
2459
2460
2461
2462
2463
2464
2465
2466
2467
2468
2469
2470
2471
2472
2473
2474
2475
2476
2477
2478
2479
2480
2481
2482
2483
2484
2485
2486
2487
2488
2489
2490
2491
2492
2493
2494
2495
2496
2497
2498
2499
12’d2442:
12’d2443:
12’d2444:
12’d2445:
12’d2446:
12’d2447:
12’d2448:
12’d2449:
12’d2450:
12’d2451:
12’d2452:
12’d2453:
12’d2454:
12’d2455:
12’d2456:
12’d2457:
12’d2458:
12’d2459:
12’d2460:
12’d2461:
12’d2462:
12’d2463:
12’d2464:
12’d2465:
12’d2466:
12’d2467:
12’d2468:
12’d2469:
12’d2470:
12’d2471:
12’d2472:
12’d2473:
12’d2474:
12’d2475:
12’d2476:
12’d2477:
12’d2478:
12’d2479:
12’d2480:
12’d2481:
12’d2482:
12’d2483:
12’d2484:
12’d2485:
12’d2486:
12’d2487:
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
180
=
=
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=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
76’d2139823280280510987800;
76’d2139823280280510987800;
76’d2139823280280510987800;
76’d2139823280280510987800;
76’d2139823280280510987800;
76’d2139823280280510987800;
76’d2139823280280510987800;
76’d2139823280280510987800;
76’d2139823280280510987800;
76’d2139823280280510987800;
76’d2139823280280510987800;
76’d2139823280280510987800;
76’d2139823280280510987800;
76’d2139823280280510987800;
76’d2139823280280510987800;
76’d2066036022511232941592;
76’d2066035882049427799577;
76’d2066035600574987959834;
76’d2139822436133143117339;
76’d2139822436408557895196;
76’d2139822436409094766109;
76’d2139822436684509543966;
76’d2213609412979884621344;
76’d2213609413255299399202;
76’d2287396389550674476580;
76’d2361183366120659025446;
76’d2361471596772225515048;
76’d2435690918631559724586;
76’d2509910240766040276525;
76’d2584129562900252393007;
76’d2658348884759855037490;
76’d2732568206894067153461;
76’d2880718620511193332280;
76’d2955082057833481304124;
76’d3029301379692815513151;
76’d3177451793309941691459;
76’d3325746322114875290183;
76’d3400109759437163262027;
76’d3548260173054289440335;
76’d3696554701859223039059;
76’d3844849371401913428567;
76’d3993144040944335382620;
76’d4141438710486757336673;
76’d4141438710486757336673;
76’d4141438710486757336673;
76’d4141438710486757336673;
2500
2501
2502
2503
2504
2505
2506
2507
2508
2509
2510
2511
2512
2513
2514
2515
2516
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2522
2523
2524
2525
2526
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2530
2531
2532
2533
2534
2535
2536
2537
2538
2539
2540
2541
2542
2543
2544
2545
12’d2488:
12’d2489:
12’d2490:
12’d2491:
12’d2492:
12’d2493:
12’d2494:
12’d2495:
12’d2496:
12’d2497:
12’d2498:
12’d2499:
12’d2500:
12’d2501:
12’d2502:
12’d2503:
12’d2504:
12’d2505:
12’d2506:
12’d2507:
12’d2508:
12’d2509:
12’d2510:
12’d2511:
12’d2512:
12’d2513:
12’d2514:
12’d2515:
12’d2516:
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12’d2518:
12’d2519:
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12’d2521:
12’d2522:
12’d2523:
12’d2524:
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12’d2526:
12’d2527:
12’d2528:
12’d2529:
12’d2530:
12’d2531:
12’d2532:
12’d2533:
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
181
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
76’d4141438710486757336673;
76’d4141438710486757336673;
76’d4141438710486757336673;
76’d4141438710486757336673;
76’d4141438710486757336673;
76’d4141438710486757336673;
76’d4141438710486757336673;
76’d4141438710486757336673;
76’d2434970902334277484062;
76’d2434970902334277484062;
76’d2434970902334277484062;
76’d2434970902334277484062;
76’d2434970902334277484062;
76’d2434970902334277484062;
76’d2434970902334277484062;
76’d2434970902334277484062;
76’d2434970902334277484062;
76’d2434970902334277484062;
76’d2434970902334277484062;
76’d2434970902334277484062;
76’d2434970902334277484062;
76’d2434970902334277484062;
76’d2434970902334277484062;
76’d2434970902334277484062;
76’d2434970902334277484062;
76’d2434970902334277484062;
76’d2434970902334277484062;
76’d2434970902334277484062;
76’d2434970902334277484062;
76’d2434970902334277484062;
76’d2434970902334277484062;
76’d2434970902334277484062;
76’d2434970902334277484062;
76’d2434970761597594435102;
76’d2434970480398032502303;
76’d2434970339661349453344;
76’d2434970339936764231201;
76’d2434970339937301102114;
76’d2508757316507822521891;
76’d2508757316508359392804;
76’d2508757316783774170662;
76’d2582544293079149248039;
76’d2656331269649133796905;
76’d2656331269649670667819;
76’d2730262361407999508013;
76’d2804481683542211624495;
2546
2547
2548
2549
2550
2551
2552
2553
2554
2555
2556
2557
2558
2559
2560
2561
2562
2563
2564
2565
2566
2567
2568
2569
2570
2571
2572
2573
2574
2575
2576
2577
2578
2579
2580
2581
2582
2583
2584
2585
2586
2587
2588
2589
2590
2591
12’d2534:
12’d2535:
12’d2536:
12’d2537:
12’d2538:
12’d2539:
12’d2540:
12’d2541:
12’d2542:
12’d2543:
12’d2544:
12’d2545:
12’d2546:
12’d2547:
12’d2548:
12’d2549:
12’d2550:
12’d2551:
12’d2552:
12’d2553:
12’d2554:
12’d2555:
12’d2556:
12’d2557:
12’d2558:
12’d2559:
12’d2560:
12’d2561:
12’d2562:
12’d2563:
12’d2564:
12’d2565:
12’d2566:
12’d2567:
12’d2568:
12’d2569:
12’d2570:
12’d2571:
12’d2572:
12’d2573:
12’d2574:
12’d2575:
12’d2576:
12’d2577:
12’d2578:
12’d2579:
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
182
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
76’d2878556890213738413618;
76’d2878989236053112323636;
76’d2953208558187592875575;
76’d3101214856616643198522;
76’d3175578293938931170365;
76’d3249797616073143286336;
76’d3324161053120553351747;
76’d3472311466737679530055;
76’d3546674904059967501898;
76’d3694825317677093680206;
76’d3769188754999113216594;
76’d3917483283804315250774;
76’d4065633838158661348954;
76’d4213928648713718000734;
76’d4362223318256139954787;
76’d4362223318256139954787;
76’d4362223318256139954787;
76’d4362223318256139954787;
76’d4362223318256139954787;
76’d4362223318256139954787;
76’d4362223318256139954787;
76’d4362223318256139954787;
76’d4362223318256139954787;
76’d4362223318256139954787;
76’d4362223318256139954787;
76’d4362223318256139954787;
76’d2877692617715208748581;
76’d2877692617715208748581;
76’d2877692617715208748581;
76’d2877692617715208748581;
76’d2877692617715208748581;
76’d2877692617715208748581;
76’d2877692617715208748581;
76’d2877692617715208748581;
76’d2877692617715208748581;
76’d2877692617715208748581;
76’d2877692617715208748581;
76’d2877692617715208748581;
76’d2877692617715208748581;
76’d2877692617715208748581;
76’d2877692617715208748581;
76’d2877692617715208748581;
76’d2877692617715208748581;
76’d2877692617715208748581;
76’d2877692617715208748581;
76’d2877692617715208748581;
2592
2593
2594
2595
2596
2597
2598
2599
2600
2601
2602
2603
2604
2605
2606
2607
2608
2609
2610
2611
2612
2613
2614
2615
2616
2617
2618
2619
2620
2621
2622
2623
2624
2625
2626
2627
2628
2629
2630
2631
2632
2633
2634
2635
2636
2637
12’d2580:
12’d2581:
12’d2582:
12’d2583:
12’d2584:
12’d2585:
12’d2586:
12’d2587:
12’d2588:
12’d2589:
12’d2590:
12’d2591:
12’d2592:
12’d2593:
12’d2594:
12’d2595:
12’d2596:
12’d2597:
12’d2598:
12’d2599:
12’d2600:
12’d2601:
12’d2602:
12’d2603:
12’d2604:
12’d2605:
12’d2606:
12’d2607:
12’d2608:
12’d2609:
12’d2610:
12’d2611:
12’d2612:
12’d2613:
12’d2614:
12’d2615:
12’d2616:
12’d2617:
12’d2618:
12’d2619:
12’d2620:
12’d2621:
12’d2622:
12’d2623:
12’d2624:
12’d2625:
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
183
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
76’d2877692617715208748581;
76’d2877692617715208748581;
76’d2877692617715208748581;
76’d2877692617715208748581;
76’d2877692617715208748581;
76’d2803905359946199137829;
76’d2803905219209516088870;
76’d2803905219484930866726;
76’d2803905219485467737639;
76’d2877692196055989157416;
76’d2877692196056526028329;
76’d2877692196331940806187;
76’d2877692196332477677100;
76’d2951479172902730661421;
76’d2951479173178145439279;
76’d3025266149473520516657;
76’d3099053126043505065523;
76’d3099341356695071555125;
76’d3173560678829283671607;
76’d3247780000688886316602;
76’d3321999322823098433084;
76’d3396218644957310549567;
76’d3470437967091791101505;
76’d3544657289226003217988;
76’d3619020726548291189831;
76’d3767027024977341512267;
76’d3841390462299629484110;
76’d3915753899621649021009;
76’d4063904313238775199317;
76’d4138412006486627382361;
76’d4286562560840973480541;
76’d4434713255933076369505;
76’d4583007925475498323557;
76’d4583007925475498323557;
76’d4583007925475498323557;
76’d4583007925475498323557;
76’d4583007925475498323557;
76’d4583007925475498323557;
76’d4583007925475498323557;
76’d4583007925475498323557;
76’d4583007925475498323557;
76’d4583007925475498323557;
76’d4583007925475498323557;
76’d4583007925475498323557;
76’d3246627356526423899692;
76’d3246627356526423899692;
2638
2639
2640
2641
2642
2643
2644
2645
2646
2647
2648
2649
2650
2651
2652
2653
2654
2655
2656
2657
2658
2659
2660
2661
2662
2663
2664
2665
2666
2667
2668
2669
2670
2671
2672
2673
2674
2675
2676
2677
2678
2679
2680
2681
2682
2683
12’d2626:
12’d2627:
12’d2628:
12’d2629:
12’d2630:
12’d2631:
12’d2632:
12’d2633:
12’d2634:
12’d2635:
12’d2636:
12’d2637:
12’d2638:
12’d2639:
12’d2640:
12’d2641:
12’d2642:
12’d2643:
12’d2644:
12’d2645:
12’d2646:
12’d2647:
12’d2648:
12’d2649:
12’d2650:
12’d2651:
12’d2652:
12’d2653:
12’d2654:
12’d2655:
12’d2656:
12’d2657:
12’d2658:
12’d2659:
12’d2660:
12’d2661:
12’d2662:
12’d2663:
12’d2664:
12’d2665:
12’d2666:
12’d2667:
12’d2668:
12’d2669:
12’d2670:
12’d2671:
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
184
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
76’d3246627356526423899692;
76’d3246627356526423899692;
76’d3246627356526423899692;
76’d3246627356526423899692;
76’d3246627356526423899692;
76’d3246627356526423899692;
76’d3246627356526423899692;
76’d3246627356526423899692;
76’d3246627356526423899692;
76’d3246627356526423899692;
76’d3246627356526423899692;
76’d3246627356526423899692;
76’d3246627356526423899692;
76’d3246627356526423899692;
76’d3246627356526423899692;
76’d3246627356526423899692;
76’d3246627356526423899692;
76’d3246627356526423899692;
76’d3246627356526423899692;
76’d3246627356526423899692;
76’d3246627356526423899692;
76’d3246627356526423899692;
76’d3246627356526423899692;
76’d3246627075052252495405;
76’d3246627075327935708717;
76’d3246627075328472579630;
76’d3246627075603887357486;
76’d3246627075604692663855;
76’d3246627075880107441712;
76’d3246627075880644312625;
76’d3320414052450897296947;
76’d3320414052726312074804;
76’d3320414052726848945717;
76’d3394201029297101930039;
76’d3467988005867086478905;
76’d3468276236243775061563;
76’d3542351443190179757629;
76’d3616570765324391874111;
76’d3690645972270528134721;
76’d3691078318110170480196;
76’d3765297640244382596678;
76’d3839516962378594713161;
76’d3987667375995720891980;
76’d4061886698129933007951;
76’d4136250135452220979794;
76’d4210469457586433096277;
2684
2685
2686
2687
2688
2689
2690
2691
2692
2693
2694
2695
2696
2697
2698
2699
2700
2701
2702
2703
2704
2705
2706
2707
2708
2709
2710
2711
2712
2713
2714
2715
2716
2717
2718
2719
2720
2721
2722
2723
2724
2725
2726
2727
2728
2729
12’d2672:
12’d2673:
12’d2674:
12’d2675:
12’d2676:
12’d2677:
12’d2678:
12’d2679:
12’d2680:
12’d2681:
12’d2682:
12’d2683:
12’d2684:
12’d2685:
12’d2686:
12’d2687:
12’d2688:
12’d2689:
12’d2690:
12’d2691:
12’d2692:
12’d2693:
12’d2694:
12’d2695:
12’d2696:
12’d2697:
12’d2698:
12’d2699:
12’d2700:
12’d2701:
12’d2702:
12’d2703:
12’d2704:
12’d2705:
12’d2706:
12’d2707:
12’d2708:
12’d2709:
12’d2710:
12’d2711:
12’d2712:
12’d2713:
12’d2714:
12’d2715:
12’d2716:
12’d2717:
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
185
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
76’d4358620011940779194456;
76’d4432983590000555521628;
76’d4507347168060331848800;
76’d4655641978340242158179;
76’d4803792673706954518631;
76’d4803792673706954518631;
76’d4803792673706954518631;
76’d4803792673706954518631;
76’d4803792673706954518631;
76’d4803792673706954518631;
76’d4803792673706954518631;
76’d4803792673706954518631;
76’d4803792673706954518631;
76’d4803792673706954518631;
76’d4803792673706954518631;
76’d4803792673706954518631;
76’d3689349071357599350324;
76’d3689349071357599350324;
76’d3689349071357599350324;
76’d3689349071357599350324;
76’d3689349071357599350324;
76’d3689349071357599350324;
76’d3689349071357599350324;
76’d3689349071357599350324;
76’d3689349071357599350324;
76’d3689349071357599350324;
76’d3689349071357599350324;
76’d3689349071357599350324;
76’d3689349071357599350324;
76’d3689349071357599350324;
76’d3689349071357599350324;
76’d3689349071357599350324;
76’d3689349071357599350324;
76’d3689349071357599350324;
76’d3689349071357599350324;
76’d3689349071357599350324;
76’d3689349071357599350324;
76’d3689349071357599350324;
76’d3689349071357599350324;
76’d3689349071357599350324;
76’d3689349071357599350324;
76’d3689348930895794208308;
76’d3689348930896331079221;
76’d3689348931172014292533;
76’d3689348931447429070390;
76’d3689348931447965941303;
2730
2731
2732
2733
2734
2735
2736
2737
2738
2739
2740
2741
2742
2743
2744
2745
2746
2747
2748
2749
2750
2751
2752
2753
2754
2755
2756
2757
2758
2759
2760
2761
2762
2763
2764
2765
2766
2767
2768
2769
2770
2771
2772
2773
2774
2775
12’d2718:
12’d2719:
12’d2720:
12’d2721:
12’d2722:
12’d2723:
12’d2724:
12’d2725:
12’d2726:
12’d2727:
12’d2728:
12’d2729:
12’d2730:
12’d2731:
12’d2732:
12’d2733:
12’d2734:
12’d2735:
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12’d2756:
12’d2757:
12’d2758:
12’d2759:
12’d2760:
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12’d2763:
quad_corners
quad_corners
quad_corners
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186
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=
76’d3689348931723649154615;
76’d3689348931724186025528;
76’d3689348931999600803386;
76’d3763135908569853787707;
76’d3763135908570390658620;
76’d3763135908845537001022;
76’d3836922885415789985343;
76’d3837067000879280619073;
76’d3911142207825416879683;
76’d3985361529685019524677;
76’d3985649760336317578823;
76’d4059869082470529695305;
76’d4134088404605010247243;
76’d4208163611551146507854;
76’d4282382933685358624336;
76’d4356746371007646596691;
76’d4430965693141858712662;
76’d4505185015275802393177;
76’d4579548734073067075676;
76’d4727699288427681609311;
76’d4802063007499555763810;
76’d4876426585559332090982;
76’d5024577280651166544489;
76’d5024577280651166544489;
76’d5024577280651166544489;
76’d5024577280651166544489;
76’d5024577280651166544489;
76’d5024577280651166544489;
76’d5024577280651166544489;
76’d5024577280651166544489;
76’d5024577280651166544489;
76’d5024577280651166544489;
76’d5024577280651166544489;
76’d5024577280651166544489;
76’d4132070927201141063228;
76’d4132070927201141063228;
76’d4132070927201141063228;
76’d4132070927201141063228;
76’d4132070927201141063228;
76’d4132070927201141063228;
76’d4132070927201141063228;
76’d4132070927201141063228;
76’d4132070927201141063228;
76’d4132070927201141063228;
76’d4132070927201141063228;
76’d4132070927201141063228;
2776
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2800
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2810
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12’d2764:
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12’d2803:
12’d2804:
12’d2805:
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12’d2809:
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
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quad_corners
quad_corners
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quad_corners
187
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76’d4132070927201141063228;
76’d4132070927201141063228;
76’d4132070927201141063228;
76’d4132070927201141063228;
76’d4132070927201141063228;
76’d4132070927201141063228;
76’d4132070927201141063228;
76’d4132070927201141063228;
76’d4132070927201141063228;
76’d4132070927201141063228;
76’d4132070927201141063228;
76’d4132070927201141063228;
76’d4132070927201141063228;
76’d4132070786464458014268;
76’d4132070786739872792125;
76’d4132070786740409663037;
76’d4132070787016092876350;
76’d4132070787291507654206;
76’d4132070787292044525119;
76’d4132070787567459302976;
76’d4132070787842874080833;
76’d4132070787843410951746;
76’d4205857764413663936067;
76’d4205857764689078713925;
76’d4205857764964493491782;
76’d4279788856447675989575;
76’d4280077087099242479177;
76’d4354152294045378739787;
76’d4428227500991515000397;
76’d4428659846831157345871;
76’d4502735053777293606481;
76’d4576954375911505722963;
76’d4651029582857641983573;
76’d4651461928697015893592;
76’d4725681250831228009562;
76’d4800044828890735901277;
76’d4874264432499924728416;
76’d5022270871666463406178;
76’d5096634590463459653221;
76’d5170854194347526386792;
76’d5245217772407034278508;
76’d5245217772407034278508;
76’d5245217772407034278508;
76’d5245217772407034278508;
76’d5245217772407034278508;
76’d5245217772407034278508;
2822
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12’d2810:
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12’d2848:
12’d2849:
12’d2850:
12’d2851:
12’d2852:
12’d2853:
12’d2854:
12’d2855:
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
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quad_corners
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quad_corners
quad_corners
188
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76’d5245217772407034278508;
76’d5245217772407034278508;
76’d5245217772407034278508;
76’d5245217772407034278508;
76’d5245217772407034278508;
76’d5245217772407034278508;
76’d4574792782769536433733;
76’d4574792782769536433733;
76’d4574792782769536433733;
76’d4574792782769536433733;
76’d4574792782769536433733;
76’d4574792782769536433733;
76’d4574792782769536433733;
76’d4574792782769536433733;
76’d4574792782769536433733;
76’d4574792782769536433733;
76’d4574792782769536433733;
76’d4574792782769536433733;
76’d4574792782769536433733;
76’d4574792782769536433733;
76’d4574792782769536433733;
76’d4574792782769536433733;
76’d4574792782769536433733;
76’d4574792782769536433733;
76’d4574792782769536433733;
76’d4574792782769536433733;
76’d4574792782769536433733;
76’d4574792782769536433733;
76’d4574792782769536433733;
76’d4574792782769536433733;
76’d4574792782769536433733;
76’d4574792642307731291717;
76’d4574792642308268162629;
76’d4574792642583951375942;
76’d4574792642584488246854;
76’d4574792642859903024711;
76’d4574792643135586238023;
76’d4574792643136123108936;
76’d4574792643411537886793;
76’d4574792643686684229194;
76’d4648579619982059306571;
76’d4648579620257474084428;
76’d4648579620532888862285;
76’d4722510712290949267022;
76’d4722798942942515756624;
76’d4723087173318935903825;
2868
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12’d2856:
12’d2857:
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12’d2894:
12’d2895:
12’d2896:
12’d2897:
12’d2898:
12’d2899:
12’d2900:
12’d2901:
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
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quad_corners
quad_corners
quad_corners
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quad_corners
quad_corners
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quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
189
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=
76’d4797162380265072164435;
76’d4797450610916370218581;
76’d4871525817862774914646;
76’d4945601024808911175256;
76’d4946033370648285085274;
76’d5020108577594152910428;
76’d5094328181203341737055;
76’d5168547644075042208353;
76’d5242767106946474244195;
76’d5316986710555663070822;
76’d5391206173701973013608;
76’d5465425777311161840235;
76’d5539789496108158087278;
76’d5539789496108158087278;
76’d5539789496108158087278;
76’d5539789496108158087278;
76’d5539789496108158087278;
76’d5539789496108158087278;
76’d5539789496108158087278;
76’d5539789496108158087278;
76’d5539789496108158087278;
76’d5539789496108158087278;
76’d5539789496108158087278;
76’d5539789496108158087278;
76’d5091301614633037921870;
76’d5091301614633037921870;
76’d5091301614633037921870;
76’d5091301614633037921870;
76’d5091301614633037921870;
76’d5091301614633037921870;
76’d5091301614633037921870;
76’d5091301614633037921870;
76’d5091301614633037921870;
76’d5091301614633037921870;
76’d5091301614633037921870;
76’d5091301614633037921870;
76’d5091301614633037921870;
76’d5091301614633037921870;
76’d5091301614633037921870;
76’d5091301614633037921870;
76’d5091301614633037921870;
76’d5091301614633037921870;
76’d5091301614633037921870;
76’d5091301614633037921870;
76’d5091301614633037921870;
76’d5091301614633037921870;
2914
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12’d2902:
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12’d2937:
12’d2938:
12’d2939:
12’d2940:
12’d2941:
12’d2942:
12’d2943:
12’d2944:
12’d2945:
12’d2946:
12’d2947:
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
190
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=
=
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=
=
=
=
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=
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=
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=
=
=
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=
=
=
=
=
=
76’d5091301614633037921870;
76’d5091301614633037921870;
76’d5091301614633037921870;
76’d5091301473896086961742;
76’d5091301474171770175054;
76’d5091301474172307045966;
76’d5091301474447721823823;
76’d5091301474723405037135;
76’d5091301474723941908048;
76’d5091301474999356685904;
76’d5091301475274771463761;
76’d5091301475275039899218;
76’d5091301475550454677074;
76’d5091301475825869454931;
76’d5091301476101015797332;
76’d5165232567859344637525;
76’d5165520798235764784727;
76’d5165664913698986983000;
76’d5239740120645391679065;
76’d5240028351296689733211;
76’d5240316581947987787356;
76’d5314391788894124047966;
76’d5314680160282910457440;
76’d5388755507966266637409;
76’d5462830855649891252835;
76’d5463263342226753517669;
76’d5537338830647598053479;
76’d5611558293519298524777;
76’d5611990920833380709483;
76’d5686210524442301100654;
76’d5760430128051221491824;
76’d5760430128051221491824;
76’d5760430128051221491824;
76’d5760430128051221491824;
76’d5760430128051221491824;
76’d5760430128051221491824;
76’d5760430128051221491824;
76’d5760430128051221491824;
76’d5760430128051221491824;
76’d5760430128051221491824;
76’d5760430128051221491824;
76’d5760430128051221491824;
76’d5607810446221392019032;
76’d5607810446221392019032;
76’d5607810446221392019032;
76’d5607810446221392019032;
2960
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2990
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2995
2996
2997
2998
2999
3000
3001
3002
3003
3004
3005
12’d2948:
12’d2949:
12’d2950:
12’d2951:
12’d2952:
12’d2953:
12’d2954:
12’d2955:
12’d2956:
12’d2957:
12’d2958:
12’d2959:
12’d2960:
12’d2961:
12’d2962:
12’d2963:
12’d2964:
12’d2965:
12’d2966:
12’d2967:
12’d2968:
12’d2969:
12’d2970:
12’d2971:
12’d2972:
12’d2973:
12’d2974:
12’d2975:
12’d2976:
12’d2977:
12’d2978:
12’d2979:
12’d2980:
12’d2981:
12’d2982:
12’d2983:
12’d2984:
12’d2985:
12’d2986:
12’d2987:
12’d2988:
12’d2989:
12’d2990:
12’d2991:
12’d2992:
12’d2993:
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
191
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
76’d5607810446221392019032;
76’d5607810446221392019032;
76’d5607810446221392019032;
76’d5607810446221392019032;
76’d5607810446221392019032;
76’d5607810446221392019032;
76’d5607810446221392019032;
76’d5607810446221392019032;
76’d5607810446221392019032;
76’d5607810446221392019032;
76’d5607810446221392019032;
76’d5607810446221392019032;
76’d5607810446221392019032;
76’d5607810446221392019032;
76’d5607810446221392019032;
76’d5607810446221392019032;
76’d5607810446221392019032;
76’d5607810446221392019032;
76’d5607810446221392019032;
76’d5607810446221392019032;
76’d5607810446221392019032;
76’d5607810446496807321176;
76’d5607810305760124796504;
76’d5607810306035539574360;
76’d5607810306310954876504;
76’d5534023330016654065240;
76’d5534023330292068843097;
76’d5534023330292605714009;
76’d5534023330568020491865;
76’d5534023330843435269722;
76’d5534023331118850047579;
76’d5534023331119118483035;
76’d5607954422877447323228;
76’d5608098538340669521501;
76’d5608242653803891719774;
76’d5608530884455458209375;
76’d5608674999643802500704;
76’d5682606091401862905441;
76’d5682894322053160959586;
76’d5683182693441678933092;
76’d5757113925937227693157;
76’d5757402438063502457446;
76’d5831477785747127072872;
76’d5831766157135645046378;
76’d5832054669261651375211;
76’d5906130016945275990637;
3006
3007
3008
3009
3010
3011
3012
3013
3014
3015
3016
3017
3018
3019
3020
3021
3022
3023
3024
3025
3026
3027
3028
3029
3030
3031
3032
3033
3034
3035
3036
3037
3038
3039
3040
3041
3042
3043
3044
3045
3046
3047
3048
3049
3050
3051
12’d2994:
12’d2995:
12’d2996:
12’d2997:
12’d2998:
12’d2999:
12’d3000:
12’d3001:
12’d3002:
12’d3003:
12’d3004:
12’d3005:
12’d3006:
12’d3007:
12’d3008:
12’d3009:
12’d3010:
12’d3011:
12’d3012:
12’d3013:
12’d3014:
12’d3015:
12’d3016:
12’d3017:
12’d3018:
12’d3019:
12’d3020:
12’d3021:
12’d3022:
12’d3023:
12’d3024:
12’d3025:
12’d3026:
12’d3027:
12’d3028:
12’d3029:
12’d3030:
12’d3031:
12’d3032:
12’d3033:
12’d3034:
12’d3035:
12’d3036:
12’d3037:
12’d3038:
12’d3039:
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
192
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
76’d5980349620554196381807;
76’d5980638132680202710641;
76’d6054857595551634746483;
76’d6054857595551634746483;
76’d6054857595551634746483;
76’d6054857595551634746483;
76’d6054857595551634746483;
76’d6054857595551634746483;
76’d6054857595551634746483;
76’d6054857595551634746483;
76’d6054857595551634746483;
76’d6054857595551634746483;
76’d6054857595551634746483;
76’d6054857595551634746483;
76’d6198106394842071628898;
76’d6198106394842071628898;
76’d6198106394842071628898;
76’d6198106394842071628898;
76’d6198106394842071628898;
76’d6198106394842071628898;
76’d6198106394842071628898;
76’d6198106394842071628898;
76’d6198106394842071628898;
76’d6198106394842071628898;
76’d6198106394842071628898;
76’d6198106394842071628898;
76’d6198106394842071628898;
76’d6198106394842071628898;
76’d6198106394842071628898;
76’d6198106394842071628898;
76’d6198106394842071628898;
76’d6198106394842071628898;
76’d6198106394842071628898;
76’d6198106394842071628898;
76’d6198106394842071628898;
76’d6198106394842071628898;
76’d6198106394842071628898;
76’d6198106394842071628898;
76’d6198106394842071628898;
76’d6124319418822648724578;
76’d6124319278085966724706;
76’d6124319137623893671522;
76’d6124319137899308973666;
76’d6124319137899846368866;
76’d6124319138175261671010;
76’d6050532162155838766690;
3052
3053
3054
3055
3056
3057
3058
3059
3060
3061
3062
3063
3064
3065
3066
3067
3068
3069
3070
3071
3072
3073
3074
3075
3076
3077
3078
3079
3080
3081
3082
3083
3084
3085
3086
3087
3088
3089
3090
3091
3092
3093
3094
3095
3096
3097
12’d3040:
12’d3041:
12’d3042:
12’d3043:
12’d3044:
12’d3045:
12’d3046:
12’d3047:
12’d3048:
12’d3049:
12’d3050:
12’d3051:
12’d3052:
12’d3053:
12’d3054:
12’d3055:
12’d3056:
12’d3057:
12’d3058:
12’d3059:
12’d3060:
12’d3061:
12’d3062:
12’d3063:
12’d3064:
12’d3065:
12’d3066:
12’d3067:
12’d3068:
12’d3069:
12’d3070:
12’d3071:
12’d3072:
12’d3073:
12’d3074:
12’d3075:
12’d3076:
12’d3077:
12’d3078:
12’d3079:
12’d3080:
12’d3081:
12’d3082:
12’d3083:
12’d3084:
12’d3085:
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
193
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
76’d6050532162156376161890;
76’d6050676277619598360163;
76’d6050676277895013138019;
76’d6050820393083357429348;
76’d6050820393358772207204;
76’d6050964508821994405477;
76’d6051108624285216603749;
76’d6051252739473560895078;
76’d6051396995674271448167;
76’d6125328228169820208232;
76’d6125472343633042405993;
76’d6125616599833752959594;
76’d6125904971222270933099;
76’d6126049368160469841516;
76’d6200124715568948115053;
76’d6200268971769658668142;
76’d6200557483895664996975;
76’d6200845855284182970481;
76’d6274777228516951649906;
76’d6275065740642957978739;
76’d6349141088326314158709;
76’d6349141088326314158709;
76’d6349141088326314158709;
76’d6349141088326314158709;
76’d6349141088326314158709;
76’d6349141088326314158709;
76’d6349141088326314158709;
76’d6349141088326314158709;
76’d6349141088326314158709;
76’d6349141088326314158709;
76’d6349141088326314158709;
76’d6349141088326314158709;
76’d6715336083845781190252;
76’d6715336083845781190252;
76’d6715336083845781190252;
76’d6715336083845781190252;
76’d6715336083845781190252;
76’d6715336083845781190252;
76’d6715336083845781190252;
76’d6715336083845781190252;
76’d6715336083845781190252;
76’d6715336083845781190252;
76’d6715336083845781190252;
76’d6715336083845781190252;
76’d6715336083845781190252;
76’d6715336083845781190252;
3098
3099
3100
3101
3102
3103
3104
3105
3106
3107
3108
3109
3110
3111
3112
3113
3114
3115
3116
3117
3118
3119
3120
3121
3122
3123
3124
3125
3126
3127
3128
3129
3130
3131
3132
3133
3134
3135
3136
3137
3138
3139
3140
3141
3142
3143
12’d3086:
12’d3087:
12’d3088:
12’d3089:
12’d3090:
12’d3091:
12’d3092:
12’d3093:
12’d3094:
12’d3095:
12’d3096:
12’d3097:
12’d3098:
12’d3099:
12’d3100:
12’d3101:
12’d3102:
12’d3103:
12’d3104:
12’d3105:
12’d3106:
12’d3107:
12’d3108:
12’d3109:
12’d3110:
12’d3111:
12’d3112:
12’d3113:
12’d3114:
12’d3115:
12’d3116:
12’d3117:
12’d3118:
12’d3119:
12’d3120:
12’d3121:
12’d3122:
12’d3123:
12’d3124:
12’d3125:
12’d3126:
12’d3127:
12’d3128:
12’d3129:
12’d3130:
12’d3131:
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
194
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
76’d6715336083845781190252;
76’d6715336083845781190252;
76’d6715336083845781190252;
76’d6715336083845781190252;
76’d6715336083845781190252;
76’d6715336083845781190252;
76’d6715336083845781190252;
76’d6715336083845781190252;
76’d6715336083845781190252;
76’d6715336083845781190252;
76’d6715336083845781190252;
76’d6715191828195632281708;
76’d6715191687458681321580;
76’d6715191687734096624236;
76’d6641260455514231601772;
76’d6641260455789646903916;
76’d6641260456065062730860;
76’d6641260315328111770732;
76’d6641260315603527072876;
76’d6567473339583835733100;
76’d6567617454772448984172;
76’d6567617595785084206188;
76’d6567617596060231072877;
76’d6567761711248575364205;
76’d6567761852261478496877;
76’d6567905967724432259694;
76’d6567906108737066956910;
76’d6568050364662899603567;
76’d6568194620863610156655;
76’d6568194621138488063600;
76’d6568339018076686972017;
76’d6568483274277129089649;
76’d6568627530202961736306;
76’d6568771786403403853939;
76’d6569060298529410182772;
76’d6569204554729852300404;
76’d6569348951667782773365;
76’d6569493348605444810358;
76’d6569781719993962783863;
76’d6569781719993962783863;
76’d6569781719993962783863;
76’d6569781719993962783863;
76’d6569781719993962783863;
76’d6569781719993962783863;
76’d6569781719993962783863;
76’d6569781719993962783863;
3144
3145
3146
3147
3148
3149
3150
3151
3152
3153
3154
3155
3156
3157
3158
3159
3160
3161
3162
3163
3164
3165
3166
3167
3168
3169
3170
3171
3172
3173
3174
3175
3176
3177
3178
3179
3180
3181
3182
3183
3184
3185
3186
3187
3188
3189
12’d3132:
12’d3133:
12’d3134:
12’d3135:
12’d3136:
12’d3137:
12’d3138:
12’d3139:
12’d3140:
12’d3141:
12’d3142:
12’d3143:
12’d3144:
12’d3145:
12’d3146:
12’d3147:
12’d3148:
12’d3149:
12’d3150:
12’d3151:
12’d3152:
12’d3153:
12’d3154:
12’d3155:
12’d3156:
12’d3157:
12’d3158:
12’d3159:
12’d3160:
12’d3161:
12’d3162:
12’d3163:
12’d3164:
12’d3165:
12’d3166:
12’d3167:
12’d3168:
12’d3169:
12’d3170:
12’d3171:
12’d3172:
12’d3173:
12’d3174:
12’d3175:
12’d3176:
12’d3177:
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
195
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
76’d6569781719993962783863;
76’d6569781719993962783863;
76’d6569781719993962783863;
76’d6569781719993962783863;
76’d7306352608131693211767;
76’d7306352608131693211767;
76’d7306352608131693211767;
76’d7306352608131693211767;
76’d7306352608131693211767;
76’d7306352608131693211767;
76’d7306352608131693211767;
76’d7306352608131693211767;
76’d7306352608131693211767;
76’d7306352608131693211767;
76’d7306352608131693211767;
76’d7306352608131693211767;
76’d7306352608131693211767;
76’d7306352608131693211767;
76’d7306352608131693211767;
76’d7306352608131693211767;
76’d7306352608131693211767;
76’d7306352608131693211767;
76’d7306352608131693211767;
76’d7306352608131693211767;
76’d7306352608131693211767;
76’d7306352608131693211767;
76’d7306352608131693211767;
76’d7306352608131693211767;
76’d7306352608131693211767;
76’d7306208493219301618295;
76’d7306208352482350658167;
76’d7306064237569690104950;
76’d7232277120812778845302;
76’d7232133005625240909430;
76’d7232133005900387776118;
76’d7158346029606086964854;
76’d7158345889143746000502;
76’d7158201774231085447286;
76’d7158201914968842762357;
76’d7158201915243989629045;
76’d7084414939224567248501;
76’d7084415079962324563574;
76’d7084415080237202994806;
76’d7084415221249838216822;
76’d7010772360143344301174;
76’d7010772501155978998902;
3190
3191
3192
3193
3194
3195
3196
3197
3198
3199
3200
3201
3202
3203
3204
3205
3206
3207
3208
3209
3210
3211
3212
3213
3214
3215
3216
3217
3218
3219
3220
3221
3222
3223
3224
3225
3226
3227
3228
3229
3230
3231
3232
3233
3234
3235
12’d3178:
12’d3179:
12’d3180:
12’d3181:
12’d3182:
12’d3183:
12’d3184:
12’d3185:
12’d3186:
12’d3187:
12’d3188:
12’d3189:
12’d3190:
12’d3191:
12’d3192:
12’d3193:
12’d3194:
12’d3195:
12’d3196:
12’d3197:
12’d3198:
12’d3199:
12’d3200:
12’d3201:
12’d3202:
12’d3203:
12’d3204:
12’d3205:
12’d3206:
12’d3207:
12’d3208:
12’d3209:
12’d3210:
12’d3211:
12’d3212:
12’d3213:
12’d3214:
12’d3215:
12’d3216:
12’d3217:
12’d3218:
12’d3219:
12’d3220:
12’d3221:
12’d3222:
12’d3223:
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
196
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
76’d7010772642168345260662;
76’d7010916898094177907318;
76’d7010917039106544169079;
76’d6937130203824072224375;
76’d6937274460024514342007;
76’d6937418856687566908024;
76’d6937418997699933169784;
76’d6937563394637863642744;
76’d6937707650838305760377;
76’d6937707932313014035065;
76’d6864065352956106301050;
76’d6864065352956106301050;
76’d6864065352956106301050;
76’d6864065352956106301050;
76’d6864065352956106301050;
76’d6864065352956106301050;
76’d6864065352956106301050;
76’d6864065352956106301050;
76’d6864065352956106301050;
76’d6864065352956106301050;
76’d6864065352956106301050;
76’d6864065352956106301050;
76’d7971300364638276086403;
76’d7971300364638276086403;
76’d7971300364638276086403;
76’d7971300364638276086403;
76’d7971300364638276086403;
76’d7971300364638276086403;
76’d7971300364638276086403;
76’d7971300364638276086403;
76’d7971300364638276086403;
76’d7971300364638276086403;
76’d7971300364638276086403;
76’d7971300364638276086403;
76’d7971300364638276086403;
76’d7971300364638276086403;
76’d7971300364638276086403;
76’d7971300364638276086403;
76’d7971300364638276086403;
76’d7971300364638276086403;
76’d7971300364638276086403;
76’d7971300364638276086403;
76’d7971300364638276086403;
76’d7971300364638276086403;
76’d7971300364638276086403;
76’d7971300364638276086403;
3236
3237
3238
3239
3240
3241
3242
3243
3244
3245
3246
3247
3248
3249
3250
3251
3252
3253
3254
3255
3256
3257
3258
3259
3260
3261
3262
3263
3264
3265
3266
3267
3268
3269
3270
3271
3272
3273
3274
3275
3276
3277
3278
3279
3280
3281
12’d3224:
12’d3225:
12’d3226:
12’d3227:
12’d3228:
12’d3229:
12’d3230:
12’d3231:
12’d3232:
12’d3233:
12’d3234:
12’d3235:
12’d3236:
12’d3237:
12’d3238:
12’d3239:
12’d3240:
12’d3241:
12’d3242:
12’d3243:
12’d3244:
12’d3245:
12’d3246:
12’d3247:
12’d3248:
12’d3249:
12’d3250:
12’d3251:
12’d3252:
12’d3253:
12’d3254:
12’d3255:
12’d3256:
12’d3257:
12’d3258:
12’d3259:
12’d3260:
12’d3261:
12’d3262:
12’d3263:
12’d3264:
12’d3265:
12’d3266:
12’d3267:
12’d3268:
12’d3269:
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
197
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
76’d7971300364638276086403;
76’d7897369273430777850498;
76’d7897225017505751035010;
76’d7897225017781166861953;
76’d7897080902868506308225;
76’d7823149670648641286273;
76’d7823149670923788677248;
76’d7749218579441412010112;
76’d7749074464528483545728;
76’d7749074464528752505471;
76’d7675143373320985309823;
76’d7675143373596401136255;
76’d7675143514333890015871;
76’d7601212423126122820222;
76’d7601212563863880659070;
76’d7601212564139027525758;
76’d7527281613668480774270;
76’d7527281754406238088830;
76’d7527281895418604874877;
76’d7453495060136132930685;
76’d7453495200873621285501;
76’d7379708365591149340797;
76’d7379708506328637695613;
76’d7379708647341003957373;
76’d7305921812058532012669;
76’d7305922093533240287356;
76’d7232135258250768342652;
76’d7232135540000354524284;
76’d7232135821475062798460;
76’d7232135821475062798460;
76’d7232135821475062798460;
76’d7232135821475062798460;
76’d7232135821475062798460;
76’d7232135821475062798460;
76’d7232135821475062798460;
76’d7232135821475062798460;
76’d7232135821475062798460;
76’d7232135821475062798460;
76’d7232135821475062798460;
76’d7232135821475062798460;
76’d8562461285587240673934;
76’d8562461285587240673934;
76’d8562461285587240673934;
76’d8562461285587240673934;
76’d8562461285587240673934;
76’d8562461285587240673934;
3282
3283
3284
3285
3286
3287
3288
3289
3290
3291
3292
3293
3294
3295
3296
3297
3298
3299
3300
3301
3302
3303
3304
3305
3306
3307
3308
3309
3310
3311
3312
3313
3314
3315
3316
3317
3318
3319
3320
3321
3322
3323
3324
3325
3326
3327
12’d3270:
12’d3271:
12’d3272:
12’d3273:
12’d3274:
12’d3275:
12’d3276:
12’d3277:
12’d3278:
12’d3279:
12’d3280:
12’d3281:
12’d3282:
12’d3283:
12’d3284:
12’d3285:
12’d3286:
12’d3287:
12’d3288:
12’d3289:
12’d3290:
12’d3291:
12’d3292:
12’d3293:
12’d3294:
12’d3295:
12’d3296:
12’d3297:
12’d3298:
12’d3299:
12’d3300:
12’d3301:
12’d3302:
12’d3303:
12’d3304:
12’d3305:
12’d3306:
12’d3307:
12’d3308:
12’d3309:
12’d3310:
12’d3311:
12’d3312:
12’d3313:
12’d3314:
12’d3315:
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
198
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
76’d8562461285587240673934;
76’d8562461285587240673934;
76’d8562461285587240673934;
76’d8562461285587240673934;
76’d8562461285587240673934;
76’d8562461285587240673934;
76’d8562461285587240673934;
76’d8562461285587240673934;
76’d8562461285587240673934;
76’d8562461285587240673934;
76’d8562461285587240673934;
76’d8562461285587240673934;
76’d8562461285587240673934;
76’d8562461285587240673934;
76’d8562461285587240673934;
76’d8562461285587240673934;
76’d8562461285587240673934;
76’d8562461285587240673934;
76’d8562461285587240673934;
76’d8562317029662214382734;
76’d8562172914749553829517;
76’d8488241682804567238285;
76’d8488097567617028778124;
76’d8487953452704100313228;
76’d8414022361221723646603;
76’d8414022361496871037579;
76’d8340091270014225935498;
76’d8339947155101297470602;
76’d8266016063618652368009;
76’d8265871948705723903113;
76’d8191940997960567155848;
76’d8191940998235714546824;
76’d8118010047765167270535;
76’d8117865932577360374406;
76’d8043934982106813622918;
76’d8043935122844302502021;
76’d7970004031636267394693;
76’d7969860057185680418436;
76’d7896073221903209522308;
76’d7822142271157784339075;
76’d7822142552907638956162;
76’d7748211602161944813186;
76’d7748067627986235219073;
76’d7674280933166105287297;
76’d7600349982695289050752;
76’d7526563287875159118975;
3328
3329
3330
3331
3332
3333
3334
3335
3336
3337
3338
3339
3340
3341
3342
3343
3344
3345
3346
3347
3348
3349
3350
3351
3352
3353
3354
3355
3356
3357
3358
3359
3360
3361
3362
3363
3364
3365
3366
3367
3368
3369
3370
3371
3372
3373
12’d3316:
12’d3317:
12’d3318:
12’d3319:
12’d3320:
12’d3321:
12’d3322:
12’d3323:
12’d3324:
12’d3325:
12’d3326:
12’d3327:
12’d3328:
12’d3329:
12’d3330:
12’d3331:
12’d3332:
12’d3333:
12’d3334:
12’d3335:
12’d3336:
12’d3337:
12’d3338:
12’d3339:
12’d3340:
12’d3341:
12’d3342:
12’d3343:
12’d3344:
12’d3345:
12’d3346:
12’d3347:
12’d3348:
12’d3349:
12’d3350:
12’d3351:
12’d3352:
12’d3353:
12’d3354:
12’d3355:
12’d3356:
12’d3357:
12’d3358:
12’d3359:
12’d3360:
12’d3361:
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
199
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
76’d7526419313699181088895;
76’d7526419313699181088895;
76’d7526419313699181088895;
76’d7526419313699181088895;
76’d7526419313699181088895;
76’d7526419313699181088895;
76’d7526419313699181088895;
76’d7526419313699181088895;
76’d7526419313699181088895;
76’d7526419313699181088895;
76’d7526419313699181088895;
76’d7526419313699181088895;
76’d9227553297744240892571;
76’d9227553297744240892571;
76’d9227553297744240892571;
76’d9227553297744240892571;
76’d9227553297744240892571;
76’d9227553297744240892571;
76’d9227553297744240892571;
76’d9227553297744240892571;
76’d9227553297744240892571;
76’d9227553297744240892571;
76’d9227553297744240892571;
76’d9227553297744240892571;
76’d9227553297744240892571;
76’d9227553297744240892571;
76’d9227553297744240892571;
76’d9227553297744240892571;
76’d9227553297744240892571;
76’d9227553297744240892571;
76’d9227553297744240892571;
76’d9227553297744240892571;
76’d9227553297744240892571;
76’d9227553297744240892571;
76’d9227553297744240892571;
76’d9227553297744240892571;
76’d9227553297744240892571;
76’d9227409042094092508314;
76’d9227264926906554048154;
76’d9153333694961567457433;
76’d9153045464585685229720;
76’d9079114373378186470040;
76’d9078970258190380098199;
76’d9005039166982613427350;
76’d9004750936606730675349;
76’d8930819845398964003988;
3374
3375
3376
3377
3378
3379
3380
3381
3382
3383
3384
3385
3386
3387
3388
3389
3390
3391
3392
3393
3394
3395
3396
3397
3398
3399
3400
3401
3402
3403
3404
3405
3406
3407
3408
3409
3410
3411
3412
3413
3414
3415
3416
3417
3418
3419
12’d3362:
12’d3363:
12’d3364:
12’d3365:
12’d3366:
12’d3367:
12’d3368:
12’d3369:
12’d3370:
12’d3371:
12’d3372:
12’d3373:
12’d3374:
12’d3375:
12’d3376:
12’d3377:
12’d3378:
12’d3379:
12’d3380:
12’d3381:
12’d3382:
12’d3383:
12’d3384:
12’d3385:
12’d3386:
12’d3387:
12’d3388:
12’d3389:
12’d3390:
12’d3391:
12’d3392:
12’d3393:
12’d3394:
12’d3395:
12’d3396:
12’d3397:
12’d3398:
12’d3399:
12’d3400:
12’d3401:
12’d3402:
12’d3403:
12’d3404:
12’d3405:
12’d3406:
12’d3407:
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
200
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
76’d8930675730211157107860;
76’d8856744779740878791827;
76’d8782669573069889922194;
76’d8782525458156960933009;
76’d8708594507411536274576;
76’d8634663416203500643471;
76’d8634519441752914190990;
76’d8560444375819413152397;
76’d8486513425348866400396;
76’d8412582333865952861835;
76’d8412438359690244316298;
76’d8338507408944551221897;
76’d8264432483748538538120;
76’d8190501533277723350663;
76’d8116570582532029731974;
76’d8042783746974411444869;
76’d7968997052429159419524;
76’d7895210216871541132419;
76’d7821423522051142764673;
76’d7821423522051142764673;
76’d7821423522051142764673;
76’d7821423522051142764673;
76’d7821423522051142764673;
76’d7821423522051142764673;
76’d7821423522051142764673;
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3420
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3465
12’d3408:
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12’d3413:
12’d3414:
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76’d9227553297744240892571;
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76’d8412438359690244316298;
76’d8338507408944551221897;
76’d8264432483748538538120;
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3466
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3511
12’d3454:
12’d3455:
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12’d3459:
12’d3460:
12’d3461:
12’d3462:
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12’d3492:
12’d3493:
12’d3494:
12’d3495:
12’d3496:
12’d3497:
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quad_corners
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202
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=
=
=
=
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76’d7821423522051142764673;
76’d7821423522051142764673;
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76’d9227553297744240892571;
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76’d9227553297744240892571;
76’d9227553297744240892571;
76’d9227553297744240892571;
76’d9227553297744240892571;
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76’d8486513425348866400396;
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3512
3513
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3557
12’d3500:
12’d3501:
12’d3502:
12’d3503:
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12’d3506:
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12’d3537:
12’d3538:
12’d3539:
12’d3540:
12’d3541:
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quad_corners
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203
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76’d8412438359690244316298;
76’d8338507408944551221897;
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76’d9227553297744240892571;
76’d9227553297744240892571;
76’d9227553297744240892571;
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3558
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3602
3603
12’d3546:
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12’d3548:
12’d3549:
12’d3550:
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12’d3552:
12’d3553:
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quad_corners
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204
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76’d9227264926906554048154;
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76’d9227553297744240892571;
3604
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12’d3592:
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12’d3597:
12’d3598:
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12’d3600:
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12’d3627:
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12’d3629:
12’d3630:
12’d3631:
12’d3632:
12’d3633:
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quad_corners
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205
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76’d9227553297744240892571;
76’d9227553297744240892571;
76’d9227553297744240892571;
76’d9227553297744240892571;
76’d9227553297744240892571;
76’d9227553297744240892571;
76’d9227553297744240892571;
76’d9227553297744240892571;
76’d9227553297744240892571;
76’d9227553297744240892571;
76’d9227553297744240892571;
76’d9227553297744240892571;
76’d9227553297744240892571;
76’d9227553297744240892571;
76’d9227553297744240892571;
76’d9227553297744240892571;
76’d9227553297744240892571;
76’d9227409042094092508314;
76’d9227264926906554048154;
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76’d8930819845398964003988;
76’d8930675730211157107860;
76’d8856744779740878791827;
76’d8782669573069889922194;
76’d8782525458156960933009;
76’d8708594507411536274576;
76’d8634663416203500643471;
76’d8634519441752914190990;
76’d8560444375819413152397;
76’d8486513425348866400396;
76’d8412582333865952861835;
76’d8412438359690244316298;
76’d8338507408944551221897;
76’d8264432483748538538120;
76’d8190501533277723350663;
76’d8116570582532029731974;
76’d8042783746974411444869;
76’d7968997052429159419524;
76’d7895210216871541132419;
76’d7821423522051142764673;
76’d7821423522051142764673;
3650
3651
3652
3653
3654
3655
3656
3657
3658
3659
3660
3661
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3665
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3690
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3694
3695
12’d3638:
12’d3639:
12’d3640:
12’d3641:
12’d3642:
12’d3643:
12’d3644:
12’d3645:
12’d3646:
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12’d3650:
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12’d3670:
12’d3671:
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12’d3675:
12’d3676:
12’d3677:
12’d3678:
12’d3679:
12’d3680:
12’d3681:
12’d3682:
12’d3683:
quad_corners
quad_corners
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206
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=
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=
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=
=
76’d7821423522051142764673;
76’d7821423522051142764673;
76’d7821423522051142764673;
76’d7821423522051142764673;
76’d7821423522051142764673;
76’d7821423522051142764673;
76’d7821423522051142764673;
76’d7821423522051142764673;
76’d7821423522051142764673;
76’d7821423522051142764673;
76’d9227553297744240892571;
76’d9227553297744240892571;
76’d9227553297744240892571;
76’d9227553297744240892571;
76’d9227553297744240892571;
76’d9227553297744240892571;
76’d9227553297744240892571;
76’d9227553297744240892571;
76’d9227553297744240892571;
76’d9227553297744240892571;
76’d9227553297744240892571;
76’d9227553297744240892571;
76’d9227553297744240892571;
76’d9227553297744240892571;
76’d9227553297744240892571;
76’d9227553297744240892571;
76’d9227553297744240892571;
76’d9227553297744240892571;
76’d9227553297744240892571;
76’d9227553297744240892571;
76’d9227553297744240892571;
76’d9227553297744240892571;
76’d9227553297744240892571;
76’d9227553297744240892571;
76’d9227553297744240892571;
76’d9227409042094092508314;
76’d9227264926906554048154;
76’d9153333694961567457433;
76’d9153045464585685229720;
76’d9079114373378186470040;
76’d9078970258190380098199;
76’d9005039166982613427350;
76’d9004750936606730675349;
76’d8930819845398964003988;
76’d8930675730211157107860;
76’d8856744779740878791827;
3696
3697
3698
3699
3700
3701
3702
3703
3704
3705
3706
3707
3708
3709
3710
3711
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3732
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3734
3735
3736
3737
3738
3739
3740
3741
12’d3684:
12’d3685:
12’d3686:
12’d3687:
12’d3688:
12’d3689:
12’d3690:
12’d3691:
12’d3692:
12’d3693:
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12’d3722:
12’d3723:
12’d3724:
12’d3725:
12’d3726:
12’d3727:
12’d3728:
12’d3729:
quad_corners
quad_corners
quad_corners
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quad_corners
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207
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=
=
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=
=
=
=
=
=
=
=
=
76’d8782669573069889922194;
76’d8782525458156960933009;
76’d8708594507411536274576;
76’d8634663416203500643471;
76’d8634519441752914190990;
76’d8560444375819413152397;
76’d8486513425348866400396;
76’d8412582333865952861835;
76’d8412438359690244316298;
76’d8338507408944551221897;
76’d8264432483748538538120;
76’d8190501533277723350663;
76’d8116570582532029731974;
76’d8042783746974411444869;
76’d7968997052429159419524;
76’d7895210216871541132419;
76’d7821423522051142764673;
76’d7821423522051142764673;
76’d7821423522051142764673;
76’d7821423522051142764673;
76’d7821423522051142764673;
76’d7821423522051142764673;
76’d7821423522051142764673;
76’d7821423522051142764673;
76’d7821423522051142764673;
76’d7821423522051142764673;
76’d7821423522051142764673;
76’d7821423522051142764673;
76’d9227553297744240892571;
76’d9227553297744240892571;
76’d9227553297744240892571;
76’d9227553297744240892571;
76’d9227553297744240892571;
76’d9227553297744240892571;
76’d9227553297744240892571;
76’d9227553297744240892571;
76’d9227553297744240892571;
76’d9227553297744240892571;
76’d9227553297744240892571;
76’d9227553297744240892571;
76’d9227553297744240892571;
76’d9227553297744240892571;
76’d9227553297744240892571;
76’d9227553297744240892571;
76’d9227553297744240892571;
76’d9227553297744240892571;
3742
3743
3744
3745
3746
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3775
3776
3777
3778
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3780
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3782
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3786
3787
12’d3730:
12’d3731:
12’d3732:
12’d3733:
12’d3734:
12’d3735:
12’d3736:
12’d3737:
12’d3738:
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12’d3768:
12’d3769:
12’d3770:
12’d3771:
12’d3772:
12’d3773:
12’d3774:
12’d3775:
quad_corners
quad_corners
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quad_corners
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208
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=
76’d9227553297744240892571;
76’d9227553297744240892571;
76’d9227553297744240892571;
76’d9227553297744240892571;
76’d9227553297744240892571;
76’d9227553297744240892571;
76’d9227553297744240892571;
76’d9227409042094092508314;
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76’d8264432483748538538120;
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76’d7821423522051142764673;
76’d7821423522051142764673;
76’d7821423522051142764673;
76’d7821423522051142764673;
76’d7821423522051142764673;
76’d7821423522051142764673;
76’d7821423522051142764673;
76’d7821423522051142764673;
76’d7821423522051142764673;
76’d7821423522051142764673;
76’d7821423522051142764673;
3788
3789
3790
3791
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3793
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3800
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3802
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3808
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3818
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3820
3821
3822
3823
3824
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3826
3827
3828
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3830
3831
3832
3833
12’d3776:
12’d3777:
12’d3778:
12’d3779:
12’d3780:
12’d3781:
12’d3782:
12’d3783:
12’d3784:
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12’d3814:
12’d3815:
12’d3816:
12’d3817:
12’d3818:
12’d3819:
12’d3820:
12’d3821:
quad_corners
quad_corners
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209
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76’d9227553297744240892571;
76’d9227553297744240892571;
76’d9227553297744240892571;
76’d9227553297744240892571;
76’d9227553297744240892571;
76’d9227553297744240892571;
76’d9227553297744240892571;
76’d9227553297744240892571;
76’d9227553297744240892571;
76’d9227553297744240892571;
76’d9227553297744240892571;
76’d9227553297744240892571;
76’d9227553297744240892571;
76’d9227553297744240892571;
76’d9227553297744240892571;
76’d9227553297744240892571;
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76’d9227553297744240892571;
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76’d8560444375819413152397;
76’d8486513425348866400396;
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76’d8412438359690244316298;
76’d8338507408944551221897;
3834
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3878
3879
12’d3822:
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12’d3824:
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12’d3826:
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12’d3828:
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12’d3859:
12’d3860:
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12’d3862:
12’d3863:
12’d3864:
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12’d3866:
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quad_corners
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quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
210
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
76’d8264432483748538538120;
76’d8190501533277723350663;
76’d8116570582532029731974;
76’d8042783746974411444869;
76’d7968997052429159419524;
76’d7895210216871541132419;
76’d7821423522051142764673;
76’d7821423522051142764673;
76’d7821423522051142764673;
76’d7821423522051142764673;
76’d7821423522051142764673;
76’d7821423522051142764673;
76’d7821423522051142764673;
76’d7821423522051142764673;
76’d7821423522051142764673;
76’d7821423522051142764673;
76’d7821423522051142764673;
76’d7821423522051142764673;
76’d9227553297744240892571;
76’d9227553297744240892571;
76’d9227553297744240892571;
76’d9227553297744240892571;
76’d9227553297744240892571;
76’d9227553297744240892571;
76’d9227553297744240892571;
76’d9227553297744240892571;
76’d9227553297744240892571;
76’d9227553297744240892571;
76’d9227553297744240892571;
76’d9227553297744240892571;
76’d9227553297744240892571;
76’d9227553297744240892571;
76’d9227553297744240892571;
76’d9227553297744240892571;
76’d9227553297744240892571;
76’d9227553297744240892571;
76’d9227553297744240892571;
76’d9227553297744240892571;
76’d9227553297744240892571;
76’d9227553297744240892571;
76’d9227553297744240892571;
76’d9227553297744240892571;
76’d9227553297744240892571;
76’d9227409042094092508314;
76’d9227264926906554048154;
76’d9153333694961567457433;
3880
3881
3882
3883
3884
3885
3886
3887
3888
3889
3890
3891
3892
3893
3894
3895
3896
3897
3898
3899
3900
3901
3902
3903
3904
3905
3906
3907
3908
3909
3910
3911
3912
3913
3914
3915
3916
3917
3918
3919
3920
3921
3922
3923
3924
3925
12’d3868:
12’d3869:
12’d3870:
12’d3871:
12’d3872:
12’d3873:
12’d3874:
12’d3875:
12’d3876:
12’d3877:
12’d3878:
12’d3879:
12’d3880:
12’d3881:
12’d3882:
12’d3883:
12’d3884:
12’d3885:
12’d3886:
12’d3887:
12’d3888:
12’d3889:
12’d3890:
12’d3891:
12’d3892:
12’d3893:
12’d3894:
12’d3895:
12’d3896:
12’d3897:
12’d3898:
12’d3899:
12’d3900:
12’d3901:
12’d3902:
12’d3903:
12’d3904:
12’d3905:
12’d3906:
12’d3907:
12’d3908:
12’d3909:
12’d3910:
12’d3911:
12’d3912:
12’d3913:
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
211
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
76’d9153045464585685229720;
76’d9079114373378186470040;
76’d9078970258190380098199;
76’d9005039166982613427350;
76’d9004750936606730675349;
76’d8930819845398964003988;
76’d8930675730211157107860;
76’d8856744779740878791827;
76’d8782669573069889922194;
76’d8782525458156960933009;
76’d8708594507411536274576;
76’d8634663416203500643471;
76’d8634519441752914190990;
76’d8560444375819413152397;
76’d8486513425348866400396;
76’d8412582333865952861835;
76’d8412438359690244316298;
76’d8338507408944551221897;
76’d8264432483748538538120;
76’d8190501533277723350663;
76’d8116570582532029731974;
76’d8042783746974411444869;
76’d7968997052429159419524;
76’d7895210216871541132419;
76’d7821423522051142764673;
76’d7821423522051142764673;
76’d7821423522051142764673;
76’d7821423522051142764673;
76’d7821423522051142764673;
76’d7821423522051142764673;
76’d7821423522051142764673;
76’d7821423522051142764673;
76’d7821423522051142764673;
76’d7821423522051142764673;
76’d7821423522051142764673;
76’d7821423522051142764673;
76’d9227553297744240892571;
76’d9227553297744240892571;
76’d9227553297744240892571;
76’d9227553297744240892571;
76’d9227553297744240892571;
76’d9227553297744240892571;
76’d9227553297744240892571;
76’d9227553297744240892571;
76’d9227553297744240892571;
76’d9227553297744240892571;
3926
3927
3928
3929
3930
3931
3932
3933
3934
3935
3936
3937
3938
3939
3940
3941
3942
3943
3944
3945
3946
3947
3948
3949
3950
3951
3952
3953
3954
3955
3956
3957
3958
3959
3960
3961
3962
3963
3964
3965
3966
3967
3968
3969
3970
3971
12’d3914:
12’d3915:
12’d3916:
12’d3917:
12’d3918:
12’d3919:
12’d3920:
12’d3921:
12’d3922:
12’d3923:
12’d3924:
12’d3925:
12’d3926:
12’d3927:
12’d3928:
12’d3929:
12’d3930:
12’d3931:
12’d3932:
12’d3933:
12’d3934:
12’d3935:
12’d3936:
12’d3937:
12’d3938:
12’d3939:
12’d3940:
12’d3941:
12’d3942:
12’d3943:
12’d3944:
12’d3945:
12’d3946:
12’d3947:
12’d3948:
12’d3949:
12’d3950:
12’d3951:
12’d3952:
12’d3953:
12’d3954:
12’d3955:
12’d3956:
12’d3957:
12’d3958:
12’d3959:
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
212
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
76’d9227553297744240892571;
76’d9227553297744240892571;
76’d9227553297744240892571;
76’d9227553297744240892571;
76’d9227553297744240892571;
76’d9227553297744240892571;
76’d9227553297744240892571;
76’d9227553297744240892571;
76’d9227553297744240892571;
76’d9227553297744240892571;
76’d9227553297744240892571;
76’d9227553297744240892571;
76’d9227553297744240892571;
76’d9227553297744240892571;
76’d9227553297744240892571;
76’d9227409042094092508314;
76’d9227264926906554048154;
76’d9153333694961567457433;
76’d9153045464585685229720;
76’d9079114373378186470040;
76’d9078970258190380098199;
76’d9005039166982613427350;
76’d9004750936606730675349;
76’d8930819845398964003988;
76’d8930675730211157107860;
76’d8856744779740878791827;
76’d8782669573069889922194;
76’d8782525458156960933009;
76’d8708594507411536274576;
76’d8634663416203500643471;
76’d8634519441752914190990;
76’d8560444375819413152397;
76’d8486513425348866400396;
76’d8412582333865952861835;
76’d8412438359690244316298;
76’d8338507408944551221897;
76’d8264432483748538538120;
76’d8190501533277723350663;
76’d8116570582532029731974;
76’d8042783746974411444869;
76’d7968997052429159419524;
76’d7895210216871541132419;
76’d7821423522051142764673;
76’d7821423522051142764673;
76’d7821423522051142764673;
76’d7821423522051142764673;
3972
3973
3974
3975
3976
3977
3978
3979
3980
3981
3982
3983
3984
3985
3986
3987
3988
3989
3990
3991
3992
3993
3994
3995
3996
3997
3998
3999
4000
4001
4002
4003
4004
4005
4006
4007
4008
4009
4010
4011
4012
4013
4014
4015
4016
4017
12’d3960:
12’d3961:
12’d3962:
12’d3963:
12’d3964:
12’d3965:
12’d3966:
12’d3967:
12’d3968:
12’d3969:
12’d3970:
12’d3971:
12’d3972:
12’d3973:
12’d3974:
12’d3975:
12’d3976:
12’d3977:
12’d3978:
12’d3979:
12’d3980:
12’d3981:
12’d3982:
12’d3983:
12’d3984:
12’d3985:
12’d3986:
12’d3987:
12’d3988:
12’d3989:
12’d3990:
12’d3991:
12’d3992:
12’d3993:
12’d3994:
12’d3995:
12’d3996:
12’d3997:
12’d3998:
12’d3999:
12’d4000:
12’d4001:
12’d4002:
12’d4003:
12’d4004:
12’d4005:
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
213
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
76’d7821423522051142764673;
76’d7821423522051142764673;
76’d7821423522051142764673;
76’d7821423522051142764673;
76’d7821423522051142764673;
76’d7821423522051142764673;
76’d7821423522051142764673;
76’d7821423522051142764673;
76’d9227553297744240892571;
76’d9227553297744240892571;
76’d9227553297744240892571;
76’d9227553297744240892571;
76’d9227553297744240892571;
76’d9227553297744240892571;
76’d9227553297744240892571;
76’d9227553297744240892571;
76’d9227553297744240892571;
76’d9227553297744240892571;
76’d9227553297744240892571;
76’d9227553297744240892571;
76’d9227553297744240892571;
76’d9227553297744240892571;
76’d9227553297744240892571;
76’d9227553297744240892571;
76’d9227553297744240892571;
76’d9227553297744240892571;
76’d9227553297744240892571;
76’d9227553297744240892571;
76’d9227553297744240892571;
76’d9227553297744240892571;
76’d9227553297744240892571;
76’d9227553297744240892571;
76’d9227553297744240892571;
76’d9227409042094092508314;
76’d9227264926906554048154;
76’d9153333694961567457433;
76’d9153045464585685229720;
76’d9079114373378186470040;
76’d9078970258190380098199;
76’d9005039166982613427350;
76’d9004750936606730675349;
76’d8930819845398964003988;
76’d8930675730211157107860;
76’d8856744779740878791827;
76’d8782669573069889922194;
76’d8782525458156960933009;
4018
4019
4020
4021
4022
4023
4024
4025
4026
4027
4028
4029
4030
4031
4032
4033
4034
4035
4036
4037
4038
4039
4040
4041
4042
4043
4044
4045
4046
4047
4048
4049
4050
4051
4052
4053
4054
4055
4056
4057
4058
4059
4060
4061
4062
4063
12’d4006:
12’d4007:
12’d4008:
12’d4009:
12’d4010:
12’d4011:
12’d4012:
12’d4013:
12’d4014:
12’d4015:
12’d4016:
12’d4017:
12’d4018:
12’d4019:
12’d4020:
12’d4021:
12’d4022:
12’d4023:
12’d4024:
12’d4025:
12’d4026:
12’d4027:
12’d4028:
12’d4029:
12’d4030:
12’d4031:
12’d4032:
12’d4033:
12’d4034:
12’d4035:
12’d4036:
12’d4037:
12’d4038:
12’d4039:
12’d4040:
12’d4041:
12’d4042:
12’d4043:
12’d4044:
12’d4045:
12’d4046:
12’d4047:
12’d4048:
12’d4049:
12’d4050:
12’d4051:
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
214
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
76’d8708594507411536274576;
76’d8634663416203500643471;
76’d8634519441752914190990;
76’d8560444375819413152397;
76’d8486513425348866400396;
76’d8412582333865952861835;
76’d8412438359690244316298;
76’d8338507408944551221897;
76’d8264432483748538538120;
76’d8190501533277723350663;
76’d8116570582532029731974;
76’d8042783746974411444869;
76’d7968997052429159419524;
76’d7895210216871541132419;
76’d7821423522051142764673;
76’d7821423522051142764673;
76’d7821423522051142764673;
76’d7821423522051142764673;
76’d7821423522051142764673;
76’d7821423522051142764673;
76’d7821423522051142764673;
76’d7821423522051142764673;
76’d7821423522051142764673;
76’d7821423522051142764673;
76’d7821423522051142764673;
76’d7821423522051142764673;
76’d9227553297744240892571;
76’d9227553297744240892571;
76’d9227553297744240892571;
76’d9227553297744240892571;
76’d9227553297744240892571;
76’d9227553297744240892571;
76’d9227553297744240892571;
76’d9227553297744240892571;
76’d9227553297744240892571;
76’d9227553297744240892571;
76’d9227553297744240892571;
76’d9227553297744240892571;
76’d9227553297744240892571;
76’d9227553297744240892571;
76’d9227553297744240892571;
76’d9227553297744240892571;
76’d9227553297744240892571;
76’d9227553297744240892571;
76’d9227553297744240892571;
76’d9227553297744240892571;
12’d4052:
12’d4053:
12’d4054:
12’d4055:
12’d4056:
12’d4057:
12’d4058:
12’d4059:
12’d4060:
12’d4061:
12’d4062:
12’d4063:
12’d4064:
12’d4065:
12’d4066:
12’d4067:
12’d4068:
12’d4069:
12’d4070:
12’d4071:
12’d4072:
12’d4073:
12’d4074:
12’d4075:
12’d4076:
12’d4077:
12’d4078:
12’d4079:
12’d4080:
12’d4081:
12’d4082:
12’d4083:
12’d4084:
12’d4085:
12’d4086:
12’d4087:
12’d4088:
12’d4089:
12’d4090:
12’d4091:
12’d4092:
12’d4093:
12’d4094:
12’d4095:
4064
4065
4066
4067
4068
4069
4070
4071
4072
4073
4074
4075
4076
4077
4078
4079
4080
4081
4082
4083
4084
4085
4086
4087
4088
4089
4090
4091
4092
4093
4094
4095
4096
4097
4098
4099
4100
4101
4102
4103
4104
4105
4106
4107
endcase
4108
4109
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
quad_corners
end
215
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
76’d9227553297744240892571;
76’d9227553297744240892571;
76’d9227553297744240892571;
76’d9227553297744240892571;
76’d9227553297744240892571;
76’d9227409042094092508314;
76’d9227264926906554048154;
76’d9153333694961567457433;
76’d9153045464585685229720;
76’d9079114373378186470040;
76’d9078970258190380098199;
76’d9005039166982613427350;
76’d9004750936606730675349;
76’d8930819845398964003988;
76’d8930675730211157107860;
76’d8856744779740878791827;
76’d8782669573069889922194;
76’d8782525458156960933009;
76’d8708594507411536274576;
76’d8634663416203500643471;
76’d8634519441752914190990;
76’d8560444375819413152397;
76’d8486513425348866400396;
76’d8412582333865952861835;
76’d8412438359690244316298;
76’d8338507408944551221897;
76’d8264432483748538538120;
76’d8190501533277723350663;
76’d8116570582532029731974;
76’d8042783746974411444869;
76’d7968997052429159419524;
76’d7895210216871541132419;
76’d7821423522051142764673;
76’d7821423522051142764673;
76’d7821423522051142764673;
76’d7821423522051142764673;
76’d7821423522051142764673;
76’d7821423522051142764673;
76’d7821423522051142764673;
76’d7821423522051142764673;
76’d7821423522051142764673;
76’d7821423522051142764673;
76’d7821423522051142764673;
76’d7821423522051142764673;
4110
endmodule
A.3.3
1
2
3
4
5
6
7
8
accel lut.jl
#=
This script generates an accel_lut.v file.
accel_lut.v contains a verilog implementation of a lookup table,
which takes in an accelerometer reading (6 bit x dir, 6 bit y dir),
and looks up a 76 bit value (4 corners of quadrilateral)
This script requires a input file accel_lut.txt containing data points.
It then interpolates the data points using 2D splines,
and creates the desired lookup table.
9
10
11
Format of accel_lut.txt:
x_accel, y_accel, x1, y1, x2, y2, x3, y3, x4, y4
12
13
14
15
i.e it is a csv file, each line denoting a reading
for ease of entry, all values are hex (just read off hex display)
leading zeros don’t have to be specified, but can be if desired
16
17
18
19
20
21
22
23
NOTE: accel_lut.v and accel_lut.txt are suggested names
General installation:
1) Install julia
2) open Julia interpreter, i.e julia at cmd line
3) install gfortran (gcc frontend for fortran), needed to compile interpolation package
4) install Dierckx (for the spline interpolation) by ‘Pkg.add("Dierckx")’ at julia prompt
5) Dierckx details (docs, installation help, etc): https://github.com/kbarbary/Dierckx.jl
24
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26
General usage:
accel_lut(input_path, output_path) at julia prompt
27
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30
31
input_path is path to the csv file, and output_path is path to the desired .v file
NOTE: in order to run the command, you first need to include this file, so type:
include("accel_lut.jl") at the julia prompt prior to running the above
NOTE: THIS CODE WILL OVERWRITE THE FILE AT OUTPUT_PATH!!!
32
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35
Suggested usage:
accel_lut("./accel_lut.txt", "./accel_lut.v")
=#
36
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using Dierckx # interpolation package
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function read_file(path)
return readcsv(path, String)
end
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67
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69
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function parse_data(path)
raw_data = read_file(path)
num_samples = size(raw_data)[1]
x_accel = zeros(Int64, num_samples)
y_accel = zeros(Int64, num_samples)
x1 = zeros(Int64, num_samples)
y1 = zeros(Int64, num_samples)
x2 = zeros(Int64, num_samples)
y2 = zeros(Int64, num_samples)
x3 = zeros(Int64, num_samples)
y3 = zeros(Int64, num_samples)
x4 = zeros(Int64, num_samples)
y4 = zeros(Int64, num_samples)
base = 16
for i = 1:num_samples
x_accel[i] = parseint(raw_data[i,1], base)
y_accel[i] = parseint(raw_data[i,2], base)
x1[i] = parseint(raw_data[i,3], base)
y1[i] = parseint(raw_data[i,4], base)
x2[i] = parseint(raw_data[i,5], base)
y2[i] = parseint(raw_data[i,6], base)
x3[i] = parseint(raw_data[i,7], base)
y3[i] = parseint(raw_data[i,8], base)
x4[i] = parseint(raw_data[i,9], base)
y4[i] = parseint(raw_data[i,10], base)
end
return float(x_accel), float(y_accel), float(x1), float(y1), float(x2), float(y2), float
end
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73
74
75
76
77
78
79
80
81
function saturate!(vec, low, upp)
for i=1:length(vec)
if (vec[i] < low)
vec[i] = low
elseif (vec[i] > upp)
vec[i] = upp
end
end
return vec
end
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85
86
87
88
function write_file(path, x_accel, y_accel, x1, y1, x2, y2, x3, y3, x4, y4)
# compute grid
x = zeros(2^12)
y = zeros(2^12)
quad_corners = zeros(Int128, 2^12)
for i=0:2^12-1
217
x[i+1] = i >> 6
y[i+1] = i & ((1 << 6) - 1)
89
90
91
end
92
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94
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103
104
105
106
107
108
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111
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117
# do the spline interpolation
# we do linear fits for now
# as we add more points, we can do something more sophisticated
x_deg = 2;
y_deg = 2;
# we also use a smoothing factor
# this trades off exact interpolation vs weighted least squares
# for more details, see doc at: https://github.com/kbarbary/Dierckx.jl
smooth_factor = 454.0;
spline_x1 = Spline2D(x_accel, y_accel, x1; kx=x_deg, ky=y_deg, s=smooth_factor)
spline_x2 = Spline2D(x_accel, y_accel, x2; kx=x_deg, ky=y_deg, s=smooth_factor)
spline_x3 = Spline2D(x_accel, y_accel, x3; kx=x_deg, ky=y_deg, s=smooth_factor)
spline_x4 = Spline2D(x_accel, y_accel, x4; kx=x_deg, ky=y_deg, s=smooth_factor)
spline_y1 = Spline2D(x_accel, y_accel, y1; kx=x_deg, ky=y_deg, s=smooth_factor)
spline_y2 = Spline2D(x_accel, y_accel, y2; kx=x_deg, ky=y_deg, s=smooth_factor)
spline_y3 = Spline2D(x_accel, y_accel, y3; kx=x_deg, ky=y_deg, s=smooth_factor)
spline_y4 = Spline2D(x_accel, y_accel, y4; kx=x_deg, ky=y_deg, s=smooth_factor)
x1_interp = int128(evaluate(spline_x1, x, y))
x2_interp = int128(evaluate(spline_x2, x, y))
x3_interp = int128(evaluate(spline_x3, x, y))
x4_interp = int128(evaluate(spline_x4, x, y))
y1_interp = int128(evaluate(spline_y1, x, y))
y2_interp = int128(evaluate(spline_y2, x, y))
y3_interp = int128(evaluate(spline_y3, x, y))
y4_interp = int128(evaluate(spline_y4, x, y))
118
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121
122
123
124
125
126
127
128
129
130
131
132
# threshold x, y coords at appropriate values
# this is to guarantee we are not putting garbage into the lut
low_x = 0
low_y = 0
upp_x = 639
upp_y = 479
saturate!(x1_interp, low_x, upp_x)
saturate!(x2_interp, low_x, upp_x)
saturate!(x3_interp, low_x, upp_x)
saturate!(x4_interp, low_x, upp_x)
saturate!(y1_interp, low_y, upp_y)
saturate!(y2_interp, low_y, upp_y)
saturate!(y3_interp, low_y, upp_y)
saturate!(y4_interp, low_y, upp_y)
133
134
# compute quad_corners
218
for i=1:2^12
quad_corners[i] = y4_interp[i] + (x4_interp[i] << 9) + (y3_interp[i] << 19) + (x3_in
quad_corners[i] += (y2_interp[i] << 38) + (x2_interp[i] << 47) + (y1_interp[i] << 57
end
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# write header
comment_head = "////////////////////////////////////////////////////////////////////////
comment_body1 = "//This file was autogenerated by accel_lut.jl.\n"
comment_body2 = "//DO NOT MANUALLY EDIT THIS FILE!!!\n\n"
comment_body3 = "//This file implements accel_lut rom for lookup of quadrilateral corner
comment_tail = "////////////////////////////////////////////////////////////////////////
code_preamble1 = "module accel_lut(input clk, input[11:0] accel_val, output reg[75:0] qu
code_preamble2 = "always @(posedge clk) begin\n"
code_preamble3 = "\tcase (accel_val)\n";
fs = open(path, "w")
write(fs, string(comment_head, comment_body1, comment_body2, comment_body3, comment_tail
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# write body
for i=0:2^12-1
val = quad_corners[i+1]
line_str = string("\t\t12’d", i, ": quad_corners = 76’d", val, ";\n")
write(fs, line_str)
end
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158
# write footer
code_end = "\tendcase\nend\nendmodule\n"
write(fs, code_end)
close(fs)
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163
end
164
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function accel_lut(in_path, out_path)
x_accel, y_accel, x1, y1, x2, y2, x3, y3, x4, y4 = parse_data(in_path)
write_file(out_path, x_accel, y_accel, x1, y1, x2, y2, x3, y3, x4, y4)
end
A.3.4
1
2
3
4
5
6
7
8
9
20,20,
20,24,
20,28,
20,2c,
20,30,
20,34,
28,20,
30,20,
34,30,
accel lut.txt
0,0,
a,d,
12,1a,
1b,39,
1f,43,
27,4d,
28,0,
5a,0,
6e,0,
0,1df,
0,1df,
0,1df,
0,1df,
0,1df,
0,1df,
0,1b9,
0,176,
16,155,
27f,1df,
27f,1df,
27f,1df,
27f,1df,
27f,1df,
27f,1df,
25c,1df,
22c,1df,
20f,1df,
219
27f,0
275,d
26e,1a
265,39
263,43
25b,4d
27f,1e
27f,72
26a,86
10
11
12
18,20,
10,20,
20,18,
A.3.5
1
2
3
4
5
6
7
8
0,33,
0,07e,
8,0,
3b,1df,
60,1df,
16,1df,
27f,1a5,
27f,158,
26a,1df,
249,0
21b,0
27f,0
pixels kept.v
////////////////////////////////////////////////////////////////////////////////////////////
// pixels_kept: Calculates the percentage of pixels lost, given the
// coordinates of the four points of the quadrilateral.
// The module is a pure combinational logic module
// The area formula is given by a standard determinant expansion, and may be
// derived easily.
// Alternatively, it is easily available on the web
////////////////////////////////////////////////////////////////////////////////////////////
9
10
11
12
13
14
15
16
17
18
module pixels_kept(input[9:0] x1,
input[8:0] y1,
input[9:0] x2,
input[8:0] y2,
input[9:0] x3,
input[8:0] y3,
input[9:0] x4,
input[8:0] y4,
output wire[6:0] percent_kept); // percent_kept ranges from 0 to 100, a 7 bi
19
20
21
22
23
24
25
26
27
28
29
30
31
wire signed[10:0] sx1, sx2, sx3, sx4;
wire signed[9:0] sy1, sy2, sy3, sy4;
wire signed[10:0] d_x1_x3, d_x2_x4;
wire signed[9:0] d_y1_y3, d_y2_y4;
wire signed[20:0] prod0, prod1;
wire signed[20:0] prod;
wire signed[20:0] abs_prod;
wire[20:0] unsigned_prod;
wire[13:0] shift_prod_7;
wire[11:0] shift_prod_9;
wire[9:0] shift_prod_11;
wire[14:0] sum_shift_prod;
32
33
34
35
36
37
38
39
40
// sign extensions
assign sx1 = {1’b0,
assign sx2 = {1’b0,
assign sx3 = {1’b0,
assign sx4 = {1’b0,
assign sy1 = {1’b0,
assign sy2 = {1’b0,
assign sy3 = {1’b0,
x1};
x2};
x3};
x4};
y1};
y2};
y3};
220
41
assign sy4 = {1’b0, y4};
42
43
44
45
46
47
// difference terms
assign d_x1_x3 = sx1
assign d_x2_x4 = sx2
assign d_y1_y3 = sy1
assign d_y2_y4 = sy2
-
sx3;
sx4;
sy3;
sy4;
48
49
50
51
// multipliers
assign prod0 = d_x1_x3 * d_y2_y4;
assign prod1 = d_y1_y3 * d_x2_x4;
52
53
54
// final area calculation
assign prod = prod0 - prod1; // this is twice the area
55
56
57
58
// but first, we need to take its absolute value
assign abs_prod = (prod < 0) ? -prod : prod;
assign unsigned_prod = abs_prod;
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
// to compute the percentage of pixels covered, here is the calculation
// we want (100*A)/(640*480), or A/(64*48)
// what we have is temp=2*A
// thus, we need temp/(128*48) = temp/(6144) = temp/(2^11 * 3) = (temp >> 11) / 3
// to avoid the division by 3, we approximate 3 ~= 21/64 (accurate to
// within 1%)
// thus, we want ((temp >> 11)*21) >> 6
// but mult by 21 is same as mult by (16 + 4 + 1)
// thus, our final calculation is ((temp >> 7) + (temp >> 9) + (temp >> 11))>>6
assign shift_prod_7 = unsigned_prod >> 7;
assign shift_prod_9 = unsigned_prod >> 9;
assign shift_prod_11 = unsigned_prod >> 11;
assign sum_shift_prod = shift_prod_7 + shift_prod_9 + shift_prod_11;
assign percent_kept = sum_shift_prod >> 6;
74
75
endmodule
A.3.6
1
2
3
4
5
6
7
8
bram.v
‘default_nettype none
////////////////////////////////////////////////////////////////////////////////////////////
// A simple true dual-port bram module, with hardcoded sizes
// number of lines: 320*240 = 76800
// data word width: 12 bits (4 bits r, 4 bits g, 4 bits b, one pixel per line)
// use here is to store a (downsampled) 640x480 frame at reduced resolution
// that can fit in bram (approx 1 Mbit usage per instantiation)
// Xilinx ISE infers the correct synthesis, and thus this module avoids
221
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10
11
12
13
14
15
16
17
18
19
// unnecessary Coregen usage
//
// credits: http://danstrother.com/2010/09/11/inferring-rams-in-fpgas/
////////////////////////////////////////////////////////////////////////////////////////////
module bram(input wire a_clk,
input wire a_wr,
input wire[16:0] a_addr,
input wire[11:0] a_din,
input wire b_clk,
input wire[16:0] b_addr,
output reg[11:0] b_dout);
20
21
22
// Shared memory
reg[11:0] mem[76799:0];
23
24
25
26
27
28
29
// Port A
always @(posedge a_clk) begin
if (a_wr) begin
mem[a_addr] <= a_din;
end
end
30
31
32
33
34
// Port B
always @(posedge b_clk) begin
b_dout <= mem[b_addr];
end
35
36
endmodule
A.3.7
1
2
3
4
5
6
7
8
9
10
addr map.v
////////////////////////////////////////////////////////////////////////////////////////////
// a simple module for mapping hcount and vcount to address in bram
// the math:
// bram is 320*240 = 76800 lines, 320 columns, and 240 rows
// each line of bram corresponds to one pixel
// currently, each line is 12 bits (4 pixels r, 4 pixels g, 4 pixels b)
// hcount and vcount are in the 640x480 space
// Thus, the desired address is: 320*(vcount/2) + (hcount/2)
// = (128 + 32)vcount + hcount/2
////////////////////////////////////////////////////////////////////////////////////////////
11
12
13
14
module addr_map(input[9:0] hcount,
input[9:0] vcount,
output[16:0] addr);
15
222
16
17
assign addr = (vcount[9:1] << 8) + (vcount[9:1] << 6) + (hcount >> 1);
endmodule
A.3.8
1
2
3
4
5
6
7
8
9
10
slow clk.v
////////////////////////////////////////////////////////////////////////////////////////////
// this module generates a VERY SLOW clk by a simple counter
// note: this method is NOT robust to timing issues, and for slowing
// down/speeding up a clk by a reasonable multiple (e.g 2, 3), use DCM instead
// to guarantee phase locking, elimination of most skew, etc
// Here, the intent is only to generate a pulse with a time period of order of
// seconds
////////////////////////////////////////////////////////////////////////////////////////////
module slow_clk(input clk, output slow_clk);
parameter TICKS = 27’d49_999_999;
11
12
13
reg [31:0] count = 0;
reg sig_reg = 0;
14
15
16
17
18
19
20
21
22
23
24
25
26
always @(posedge clk) begin
if (count == TICKS) begin
// flip at half period
sig_reg <= ~sig_reg;
count <= 0;
end
else begin
count <= count + 1;
end
end
assign slow_clk = sig_reg;
endmodule
A.3.9
1
2
3
4
5
6
7
8
9
10
11
12
move cursor.v
////////////////////////////////////////////////////////////////////////////////////////////
// move_cursor: This module implements a simple UI for manually adjusting the
// projector correction via pressing the arrow keys, and selecting which
// corner of the quadrilateral the user is manipulating via switch[1:0] positions.
// 00 -> point 1, 01 -> point 2, 10 -> point 3, 11 -> point 4
// All the adjustments can only happen when the override is pressed.
// Inputs are xi_raw, yi_raw (obtained from accelerometer lut)
// Outputs are xi, yi and display_x, display_y (for hex display).
// The intention is to run this on a slow clk, even vsync could be a little
// too fast
////////////////////////////////////////////////////////////////////////////////////////////
module move_cursor(input clk,
223
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14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
input up,
input down,
input left,
input right,
input override,
input[1:0] switch,
input[9:0] x1_raw,
input[8:0] y1_raw,
input[9:0] x2_raw,
input[8:0] y2_raw,
input[9:0] x3_raw,
input[8:0] y3_raw,
input[9:0] x4_raw,
input[8:0] y4_raw,
output reg[9:0] x1,
output reg[8:0] y1,
output reg[9:0] x2,
output reg[8:0] y2,
output reg[9:0] x3,
output reg[8:0] y3,
output reg[9:0] x4,
output reg[8:0] y4,
output reg[9:0] display_x,
output reg[8:0] display_y);
37
38
parameter OVERRIDE = 1’b0;
39
40
41
parameter XSPEED = 1’d1;
parameter YSPEED = 1’d1;
42
43
44
45
// 640 x 480 screen
parameter SCR_WIDTH = 10’d639;
parameter SCR_HEIGHT = 9’d479;
46
47
reg cur_state = ~OVERRIDE;
48
49
50
51
52
53
54
55
56
57
58
always @(posedge clk)
case (switch)
2’b00: begin
display_x
display_y
end
2’b01: begin
display_x
display_y
end
begin
<= x1;
<= y1;
<= x2;
<= y2;
224
2’b10: begin
display_x
display_y
end
2’b11: begin
display_x
display_y
end
endcase
59
60
61
62
63
64
65
66
67
68
<= x3;
<= y3;
<= x4;
<= y4;
end
69
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73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
always @(posedge clk) begin
if (override && !(cur_state == OVERRIDE)) begin
cur_state <= OVERRIDE;
x1 <= x1_raw;
y1 <= y1_raw;
x2 <= x2_raw;
y2 <= y2_raw;
x3 <= x3_raw;
y3 <= y3_raw;
x4 <= x4_raw;
y4 <= y4_raw;
end
else if (override) begin
case (switch)
2’b00: begin
if (down) begin
y1 <= (y1 <= SCR_HEIGHT-YSPEED) ? (y1 + YSPEED) : y1;
end
else if (up) begin
y1 <= (y1 >= YSPEED) ? (y1 - YSPEED) : y1;
end
else if (left) begin
x1 <= (x1 >= XSPEED) ? (x1 - XSPEED) : x1;
end
else if (right) begin
x1 <= (x1 <= SCR_WIDTH-XSPEED) ? (x1 + XSPEED) : x1;
end
end
2’b01: begin
if (down) begin
y2 <= (y2 <= SCR_HEIGHT-YSPEED) ? (y2 + YSPEED) : y2;
end
else if (up) begin
y2 <= (y2 >= YSPEED) ? (y2 - YSPEED) : y2;
end
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else if (left) begin
x2 <= (x2 >= XSPEED) ? (x2 - XSPEED) : x2;
end
else if (right) begin
x2 <= (x2 <= SCR_WIDTH-XSPEED) ? (x2 + XSPEED) : x2;
end
end
2’b10: begin
if (down) begin
y3 <= (y3 <= SCR_HEIGHT-YSPEED) ? (y3 + YSPEED) : y3;
end
else if (up) begin
y3 <= (y3 >= YSPEED) ? (y3 - YSPEED) : y3;
end
else if (left) begin
x3 <= (x3 >= XSPEED) ? (x3 - XSPEED) : x3;
end
else if (right) begin
x3 <= (x3 <= SCR_WIDTH-XSPEED) ? (x3 + XSPEED) : x3;
end
end
2’b11: begin
if (down) begin
y4 <= (y4 <= SCR_HEIGHT-YSPEED) ? (y4 + YSPEED) : y4;
end
else if (up) begin
y4 <= (y4 >= YSPEED) ? (y4 - YSPEED) : y4;
end
else if (left) begin
x4 <= (x4 >= XSPEED) ? (x4 - XSPEED) : x4;
end
else if (right) begin
x4 <= (x4 <= SCR_WIDTH-XSPEED) ? (x4 + XSPEED) : x4;
end
end
endcase
end
else begin
x1 <= x1_raw;
y1 <= y1_raw;
x2 <= x2_raw;
y2 <= y2_raw;
x3 <= x3_raw;
y3 <= y3_raw;
x4 <= x4_raw;
y4 <= y4_raw;
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cur_state <= ~OVERRIDE;
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end
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end
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endmodule
A.3.10
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perspective params.v
////////////////////////////////////////////////////////////////////////////////////////////
// perspective_params: Generate the parameters for the perspective transform from the
// rectangle to the quadrilateral inside it
// Note that this is the forward mapping
// The math is described as follows
// Let (x1, y1), (x2, y2), (x3, y3), (x4, y4) be the four points inside the
// screen
// Let the (forward) perspective map be given by:
// (X, Y) = ((p1*x + p2*y + p3)/(p7*x + p8*y + p9), (p4*x + p5*y + p6)/(p7*x
// + p8*y + p9))
// Then our task is to determine the values of p_i given the values of the x_i
// This is a system of equations in 8 unknowns
// It turns out that a pretty simple closed form solution exists, given by
//
// p7 = 3((x1-x4)(y2-y3) + 3(y1-y4)(x3-x2))
// p8 = 4((x1-x2)(y3-y4) + 4(x4-x3)(y1-y2))
// denom = x4(y2-y3) + x2(y3-y4) + x3(y4-y2)
// p9 = 1920*denom (2^7 * 15 * denom)
// p3 = 1920*x1*denom (2^7 * 15 * x1 * denom)
// p6 = 1920*y1*denom (2^7 * 15 * y1 * denom)
// p1 = x4*p7 + 3(x4-x1)*denom
// p2 = x2*p8 + 4(x2-x1)*denom
// p4 = y4*p7 + 3(y4-y1)*denom
// p5 = y2*p8 + 4(y2-y1)*denom
//
// inverse mapping
// p1_inv = p6*p8 - p5*p9
// p2_inv = p2*p9 - p3*p8
// p3_inv = p3*p5 - p2*p6
// p4_inv = p4*p9 - p6*p7
// p5_inv = p3*p7 - p1*p9
// p6_inv = p1*p6 - p3*p4
// p7_inv = p5*p7 - p4*p8
// p8_inv = p1*p8 - p2*p7
// p9_inv = p2*p4 - p1*p5
// dec_numx_horiz = p1_inv * 639
// dec_numy_horiz = p4_inv * 639
// dec_denom_horiz = p7_inv * 639
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//
// Future improvements:
// 1)
// This module uses over 120 out of 144 available 18x18
// multipliers!!!
// By reducing bitwidths and avoiding needless multiplies, e.g shifting
// whenever multiplying by constant, resource utilization could be improved
// Even with those improvements, I estimate the need of at least 80-100 18x18
// multipliers to avoid precision loss
//
// 2)
// Right now, the intention is to run this module on a slow clock, since we
// don’t want the parameters to change mid-frame anyway.
// Thus, timing is never an issue right now.
// However, module is easily pipelined, if one needs to run at fast clock.
////////////////////////////////////////////////////////////////////////////////////////////
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module perspective_params(input clk,
input[9:0] x1,
input[8:0] y1,
input[9:0] x2,
input[8:0] y2,
input[9:0] x3,
input[8:0] y3,
input[9:0] x4,
input[8:0] y4,
// reason for the hardcoded numbers is FPGA limitations on
// multiplier bitwidths (s18 x s18 yields s35)
// Note: guaranteed, mathematically proven bitwidths are:
// forward: 36, 36, 44, 35, 35, 43, 24, 24, 33
// inverse: 68, 69, 79, 68, 69, 79, 59, 60, 71
output reg signed[67:0] p1_inv,
output reg signed[68:0] p2_inv,
output reg signed[78:0] p3_inv,
output reg signed[67:0] p4_inv,
output reg signed[68:0] p5_inv,
output reg signed[78:0] p6_inv,
output reg signed[58:0] p7_inv,
output reg signed[59:0] p8_inv,
output reg signed[70:0] p9_inv,
output reg signed[78:0] dec_numx_horiz,
output reg signed[78:0] dec_numy_horiz,
output reg signed[70:0] dec_denom_horiz);
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// sign extensions
wire signed[10:0] sx1, sx2, sx3, sx4;
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wire signed[9:0] sy1, sy2, sy3, sy4;
assign sx1 = {1’b0, x1};
assign sx2 = {1’b0, x2};
assign sx3 = {1’b0, x3};
assign sx4 = {1’b0, x4};
assign sy1 = {1’b0, y1};
assign sy2 = {1’b0, y2};
assign sy3 = {1’b0, y3};
assign sy4 = {1’b0, y4};
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// difference values for computation
wire signed[10:0] d_x1_x2,d_x2_x3,d_x3_x4,d_x4_x1;
wire signed[9:0] d_y1_y2, d_y2_y3, d_y3_y4, d_y4_y1, d_y4_y2;
assign d_x1_x2 = sx1 - sx2;
assign d_x2_x3 = sx2 - sx3;
assign d_x3_x4 = sx3 - sx4;
assign d_x4_x1 = sx4 - sx1;
assign d_y1_y2 = sy1 - sy2;
assign d_y2_y3 = sy2 - sy3;
assign d_y3_y4 = sy3 - sy4;
assign d_y4_y1 = sy4 - sy1;
assign d_y4_y2 = sy4 - sy2;
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// computation of p7, p8
wire signed[20:0] num0, num1, num2, num3;
wire signed[21:0] p7_temp, p8_temp;
wire signed[23:0] p7, p8;
assign num0 = -(d_x4_x1 * d_y2_y3);
assign num1 = d_y4_y1 * d_x2_x3;
assign num2 = d_x1_x2 * d_y3_y4;
assign num3 = -(d_x3_x4 * d_y1_y2);
assign p7_temp = num0 + num1;
assign p8_temp = num2 + num3;
assign p7 = (p7_temp <<< 1) + p7_temp;
assign p8 = (p8_temp <<< 2);
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// computation of denom
wire signed[20:0] denom0, denom1, denom2;
wire signed[21:0] denom;
assign denom0 = sx4 * d_y2_y3;
assign denom1 = sx2 * d_y3_y4;
assign denom2 = sx3 * d_y4_y2;
assign denom = denom0 + denom1 + denom2;
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// computation of p3, p6, p9
// observe that 1920 = 2^7 * 15
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wire signed[25:0] denom_15;
wire signed[32:0] p9;
wire signed[32:0] x1_denom;
wire signed[36:0] x1_denom_15;
wire signed[43:0] p3;
wire signed[31:0] y1_denom;
wire signed[35:0] y1_denom_15;
wire signed[42:0] p6;
assign denom_15 = (denom <<< 4) - denom; // denom * 15
assign p9 = denom_15 <<< 7; // denom * 1920
assign x1_denom = sx1 * denom; // x1 * denom
assign x1_denom_15 = (x1_denom <<< 4) - x1_denom; // x1 * denom * 15
assign p3 = x1_denom_15 <<< 7; // x1 * denom * 1920
assign y1_denom = sy1 * denom; // y1 * denom
assign y1_denom_15 = (y1_denom <<< 4) - y1_denom; // y1 * denom * 15
assign p6 = y1_denom_15 <<< 7; // y1 * denom * 1920
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// computation of p1, p2, p4, p5
wire signed[32:0] d_x1_x2_denom;
wire signed[32:0] d_x4_x1_denom;
wire signed[31:0] d_y4_y1_denom;
wire signed[31:0] d_y1_y2_denom;
wire signed[34:0] d_x1_x2_denom_scale;
wire signed[34:0] d_x4_x1_denom_scale;
wire signed[33:0] d_y4_y1_denom_scale;
wire signed[33:0] d_y1_y2_denom_scale;
wire signed[34:0] x4_p7;
wire signed[34:0] x2_p8;
wire signed[33:0] y4_p7;
wire signed[33:0] y2_p8;
wire signed[35:0] p1, p2;
wire signed[34:0] p4, p5;
assign d_x1_x2_denom = d_x1_x2 * denom;
assign d_x4_x1_denom = d_x4_x1 * denom;
assign d_y4_y1_denom = d_y4_y1 * denom;
assign d_y1_y2_denom = d_y1_y2 * denom;
assign d_x4_x1_denom_scale = (d_x4_x1_denom
assign d_x1_x2_denom_scale = (d_x1_x2_denom
assign d_y4_y1_denom_scale = (d_y4_y1_denom
assign d_y1_y2_denom_scale = (d_y1_y2_denom
assign x4_p7 = sx4 * p7;
assign x2_p8 = sx2 * p8;
assign y4_p7 = sy4 * p7;
assign y2_p8 = sy2 * p8;
assign p1 = x4_p7 + d_x4_x1_denom_scale;
assign p2 = x2_p8 - d_x1_x2_denom_scale;
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<<<
<<<
<<<
<<<
1) + d_x4_x1_denom; // d_x4_x1_denom*3
2); // d_x1_x2_denom*4
1) + d_y4_y1_denom; // d_y4_y1_denom*3
2); // d_y1_y2_denom*4
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assign p4 = y4_p7 + d_y4_y1_denom_scale;
assign p5 = y2_p8 - d_y1_y2_denom_scale;
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// 36, 36, 44, 35, 35, 43, 24, 24, 33
// computation of inverse mapping
wire signed[67:0] p1_inv_wire;
wire signed[68:0] p2_inv_wire;
wire signed[78:0] p3_inv_wire;
wire signed[67:0] p4_inv_wire;
wire signed[68:0] p5_inv_wire;
wire signed[78:0] p6_inv_wire;
wire signed[58:0] p7_inv_wire;
wire signed[59:0] p8_inv_wire;
wire signed[70:0] p9_inv_wire;
assign p1_inv_wire = p6*p8 - p5*p9;
assign p2_inv_wire = p2*p9 - p3*p8;
assign p3_inv_wire = p3*p5 - p2*p6;
assign p4_inv_wire = p4*p9 - p6*p7;
assign p5_inv_wire = p3*p7 - p1*p9;
assign p6_inv_wire = p1*p6 - p3*p4;
assign p7_inv_wire = p5*p7 - p4*p8;
assign p8_inv_wire = p1*p8 - p2*p7;
assign p9_inv_wire = p2*p4 - p1*p5;
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// computation of dec_numx_horiz, dec_numy_horiz, dec_denom_horiz
wire signed[78:0] dec_numx_horiz_wire;
wire signed[78:0] dec_numy_horiz_wire;
wire signed[70:0] dec_denom_horiz_wire;
// multiply stuff by 639 = 512 + 128 - 1
assign dec_numx_horiz_wire = (p1_inv_wire <<< 9) + (p1_inv_wire <<< 7) - p1_inv_wire;
assign dec_numy_horiz_wire = (p4_inv_wire <<< 9) + (p4_inv_wire <<< 7) - p4_inv_wire;
assign dec_denom_horiz_wire = (p7_inv_wire <<< 9) + (p7_inv_wire <<< 7) - p7_inv_wire;
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always @(posedge clk) begin
p1_inv <= p1_inv_wire;
p2_inv <= p2_inv_wire;
p3_inv <= p3_inv_wire;
p4_inv <= p4_inv_wire;
p5_inv <= p5_inv_wire;
p6_inv <= p6_inv_wire;
p7_inv <= p7_inv_wire;
p8_inv <= p8_inv_wire;
p9_inv <= p9_inv_wire;
dec_numx_horiz <= dec_numx_horiz_wire;
dec_numy_horiz <= dec_numy_horiz_wire;
dec_denom_horiz <= dec_denom_horiz_wire;
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end
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endmodule
A.3.11
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pixel map.v
‘default_nettype none
////////////////////////////////////////////////////////////////////////////////////////////
// pixel_map: This module performs the core perspective transformation
// It computes (X, Y) = ((p1*x+p2*y+p3)/(p7*x+p8*y+p9),
// (p4*x+p5*y+p6)/(p7*x+p8*y+p9)) given values pi (computed in
// perspective_params.v)
// The module also does the necessary pixel read form ntsc_buf, and writes the
// output to vga_buf
//
// Future work:
// 1) Note the huge bit width of the divider. This results in a ridiculous ~80
// clock cycles per pixel. Pipelining of 80 bit divider can’t be done in
// coregen, and will need to be done manually. It would be a nice feature,
// since this would enable a real time projector display as opposed to current
// ~1-2 frames per second
//
// 2) reduce bit widths: these bit widths are conservative, and mathematically
// guaranteed never to lose precision. Software indicates that I can lose up
// to 20 bits of precision, and still be ok. A careful analysis of this needs
// to be performed
////////////////////////////////////////////////////////////////////////////////////////////
module pixel_map(input clk,
input signed[67:0] p1_inv,
input signed[68:0] p2_inv,
input signed[78:0] p3_inv,
input signed[67:0] p4_inv,
input signed[68:0] p5_inv,
input signed[78:0] p6_inv,
input signed[58:0] p7_inv,
input signed[59:0] p8_inv,
input signed[70:0] p9_inv,
input signed[78:0] dec_numx_horiz,
input signed[78:0] dec_numy_horiz,
input signed[70:0] dec_denom_horiz,
input[11:0] pixel_in,
output reg[11:0] pixel_out,
output[16:0] ntsc_out_addr,
output reg vga_in_wr,
output[16:0] vga_in_addr);
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// internal registers for numerator and denominator computation
// see perspective_params.v for the equations
reg signed[78:0] num_x = 0;
reg signed[78:0] num_y = 0;
reg signed[78:0] denom = 0;
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// internal registers for pixel index
reg[9:0] cur_x = 0;
reg[9:0] cur_y = 0;
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// divider outputs
wire signed[78:0] inv_x;
wire signed[78:0] inv_y;
wire signed[78:0] dummy_remx;
wire signed[78:0] dummy_remy;
reg div_start;
wire div_done_x;
wire div_done_y;
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// instantiate dividers
divider #(.WIDTH(79)) divider_x(.clk(clk),
.sign(1’b1),
.start(div_start),
.dividend(num_x),
.divider(denom),
.quotient(inv_x),
.remainder(dummy_remx),
.ready(div_done_x));
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divider #(.WIDTH(79)) divider_y(.clk(clk),
.sign(1’b1),
.start(div_start),
.dividend(num_y),
.divider(denom),
.quotient(inv_y),
.remainder(dummy_remy),
.ready(div_done_y));
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// instantiate an address mapper (for the vga_in)
addr_map addr_map_vga(.hcount(cur_x),
.vcount(cur_y),
.addr(vga_in_addr));
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// instantiate an address mapper (for the ntsc_out)
addr_map addr_map_ntsc(.hcount(inv_x[9:0]),
.vcount(inv_y[9:0]),
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.addr(ntsc_out_addr));
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parameter NEXT_PIXEL_ST = 2’b00;
parameter WAIT_FOR_DIV_ST = 2’b01;
parameter WAIT_FOR_MEM_ST = 2’b10;
parameter BLACK = 12’d0;
reg[1:0] cur_state = NEXT_PIXEL_ST;
always @(posedge clk) begin
case (cur_state)
NEXT_PIXEL_ST: begin
vga_in_wr <= 0;
div_start <= 1;
cur_state <= WAIT_FOR_DIV_ST;
if ((cur_x == 639) && (cur_y == 479)) begin
cur_x <= 0;
cur_y <= 0;
num_x <= p3_inv;
num_y <= p6_inv;
denom <= p9_inv;
end
else if ((cur_x == 639) && (cur_y != 479)) begin
cur_x <= 0;
cur_y <= cur_y + 1;
num_x <= num_x - dec_numx_horiz + p2_inv;
num_y <= num_y - dec_numy_horiz + p5_inv;
denom <= denom - dec_denom_horiz + p8_inv;
end
else if (cur_x != 639) begin
cur_x <= cur_x + 1;
cur_y <= cur_y;
num_x <= num_x + p1_inv;
num_y <= num_y + p4_inv;
denom <= denom + p7_inv;
end
end
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WAIT_FOR_DIV_ST: begin
vga_in_wr <= 0;
div_start <= 0;
if (div_done_x == 1) begin
cur_state <= WAIT_FOR_MEM_ST;
end
end
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WAIT_FOR_MEM_ST: begin
if ((inv_x < 0) || (inv_x > 639) || (inv_y < 0) || (inv_y > 479)) begin
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pixel_out <= BLACK;
vga_in_wr <= 1;
cur_state <= NEXT_PIXEL_ST;
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end
else begin
pixel_out <= pixel_in;
vga_in_wr <= 1;
cur_state <= NEXT_PIXEL_ST;
end
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end
endcase
end
endmodule
A.3.12
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audioManager.v
‘default_nettype none
// Shawn Jain
// Receives audio samples via FTDI UM245R USB-to-FIFO, stores to
// onboard flash memory. Plays back the percentage of pixels used
// when audioTrigger is pulsed, where the percent is set by
// audioSelector. Internally it queues upto four separate tracks
// to be played. To save memory and for a faster transfer, the
// system constructs all numbers 1-100 out of a subset of the
// digits.
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module audioManager(
input wire clock, // 27mhz system clock
input wire reset, // 1 to reset to initial state
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// User I/O
input wire startSwitch,
input wire [6:0] audioSelector,
input wire writeSwitch, // 1=Write, 0=Read
output wire [63:0] hexdisp,
input wire audioTrigger, // 1=Begin Playback as determined by audioSelector
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// AC97 I/O
input wire ready,
// 1 when AC97 data is available
input wire [7:0] from_ac97_data, // 8-bit PCM data from mic
output reg [7:0] to_ac97_data,
// 8-bit PCM data to headphone
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// Flash I/O
output wire [15:0] flash_data,
output wire [23:0] flash_address,
output wire flash_ce_b,
235
output wire flash_oe_b,
output wire flash_we_b,
output wire flash_reset_b,
output wire flash_byte_b,
input wire flash_sts,
output wire busy,
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// USB I/O
input wire [7:0] data, // the data pins from the USB fifo
input wire rxf,
// the rxf pin from the USB fifo
output wire rd
// the rd pin from the USB fifo (OUTPUT)
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);
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// Playback addresses:
parameter TRACK_LENGTH = 69000; // approx 1 sec
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parameter
parameter
parameter
parameter
parameter
parameter
parameter
parameter
parameter
parameter
parameter
parameter
parameter
parameter
parameter
parameter
parameter
parameter
parameter
parameter
parameter
parameter
parameter
parameter
parameter
parameter
parameter
parameter
parameter
parameter
ONE_INDEX = 23’d0;
TWO_INDEX = 23’d1;
THREE_INDEX = 23’d2;
FOUR_INDEX = 23’d3;
FIVE_INDEX = 23’d4;
SIX_INDEX = 23’d5;
SEVEN_INDEX = 23’d6;
EIGHT_INDEX = 23’d7;
NINE_INDEX = 23’d8;
TEN_INDEX = 23’d9;
ELEVEN_INDEX = 23’d10;
//
TWELVE_INDEX = 23’d11;
//
THIRTEEN_INDEX = 23’d12; //
FOURTEEN_INDEX = 23’d13; //
FIFTEEN_INDEX = 23’d14;
//
TWENTY_INDEX = 23’d15;
//
THIRTY_INDEX = 23’d16;
//
FOURTY_INDEX = 23’d17;
//
FIFTY_INDEX = 23’d18;
//
SIXTY_INDEX = 23’d19;
//
SEVENTY_INDEX = 23’d20;
//
EIGHTY_INDEX = 23’d21;
//
NINETY_INDEX = 23’d22;
//
HUNDRED_INDEX = 23’d23;
//
TEEN_INDEX = 23’d24;
//
PERCENT_INDEX = 23’d25;
//
USED_INDEX = 23’d26;
//
HELP_AUDIO_INDEX = 23’d27;//
SKIP_INDEX = 23’d28;
//
UNUSED_INDEX = 23’d31;
//
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A
B
C
D
E
F
10
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1A
1B
1C
1F
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reg writemode = 0;
reg [15:0] wdata = 0;
reg dowrite = 0;
reg [22:0] raddr = 2;
wire [15:0] frdata;
reg doread = 0;
//
//
//
//
//
//
1=write mode; 0=read mode
writeData
1=new data, write it
readAddress
readData
1=execute read
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flash_manager fm(
.clock(clock),
.reset(reset),
88
// Interface I/O
.writemode(writemode),
.wdata(wdata),
.dowrite(dowrite),
.raddr(raddr),
.frdata(frdata),
.doread(doread),
.busy(busy),
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// Flash I/O
.flash_data(flash_data),
.flash_address(flash_address),
.flash_ce_b(flash_ce_b),
.flash_oe_b(flash_oe_b),
.flash_we_b(flash_we_b),
.flash_reset_b(flash_reset_b),
.flash_sts(flash_sts),
.flash_byte_b(flash_byte_b)
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);
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wire [7:0] out;// data from FIFO (OUTPUT)
wire newout;
// newout=1 out contains new data (OUTPUT)
wire hold;
// hold=1 the module will not accept new data from the FIFO
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assign hold = 1’b0;
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usb_input usbtest(
.clk(clock),
.reset(reset),
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// USB FTDI I/O
.data(data[7:0]),
.rxf(rxf),
.rd(rd),
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// Interface
.out(out[7:0]),
.newout(newout),
.hold(hold)
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);
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wire [3:0] hundreds;
wire [3:0] tens;
wire [3:0] ones;
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BCD inputToBCD(
.number({1’b0, audioSelector}),
.hundreds(hundreds),
.tens(tens),
.ones(ones)
);
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reg lastAudioTrigger;
reg [2:0] third = 0;
reg lastReady;
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// Set of 4 addresses that represent a playback sequence
// First track in bottom 23 bits[22:0]. Last track in top bits [91:68].
reg [91:0] playbackSeq = 2;
reg [22:0] trackEndAddr = 0;
reg playing = 0;
reg lastPlaying = 0;
reg [15:0] bytesRxed = 0;
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assign hexdisp = {playbackSeq[30:23], playbackSeq[7:0], 1’h0 ,trackEndAddr, 1’h0, raddr[22
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reg [7:0] dataFromFifo;
always @ (posedge rd) begin
dataFromFifo <= out; // out & data have same results
end
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always @ (posedge clock) begin
lastAudioTrigger <= audioTrigger;
lastReady <= ready;
lastPlaying <= playing;
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if (startSwitch) begin
// write USB RX data if switch is up
if (writeSwitch) begin
writemode <= 1’b1;
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doread <= 1’b0;
//dowrite <= 1’b0; // only write on new data // WATCH OUT!!
if (newout) begin
bytesRxed <= bytesRxed + 1;
wdata <= {dataFromFifo, 8’b0};//{out, 8’b0};
dowrite <= 1’b1;
end
end
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// if button is DOWN - scroll through addresses via buttons
if (~writeSwitch) begin
dowrite <= 1’b0;
writemode <= 1’b0;
doread <= 1’b1;
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if (playing & ready) begin // REMOVE audioTrigger
if (raddr < trackEndAddr) begin
// Normal 48K Playback
raddr <= raddr + 1;
to_ac97_data <= frdata[15:8]; // PUT BACK
end
else begin
if (playbackSeq[45:23] < UNUSED_INDEX) begin
// change raddr to next track
raddr <= playbackSeq[45:23] * TRACK_LENGTH;
// shift playbackSeq down
playbackSeq <= {UNUSED_INDEX, playbackSeq[91:23]};
// update trackEndAddr
trackEndAddr <= playbackSeq[45:23] * TRACK_LENGTH + TRACK_LENGTH;
end
else if (playbackSeq[45:23] == UNUSED_INDEX) begin
playing <= 0;
raddr <= 0; // reset for safety - lower than UNUSED_ADDR
end
end
end // if (playing & audioTrigger & ready)
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// if entering this state, assign start address
if (audioTrigger & ~lastAudioTrigger) begin
playing <= 1;
case(ones)
0: playbackSeq[91:23] <= {UNUSED_INDEX, USED_INDEX, PERCENT_INDEX};
1: playbackSeq[91:23] <= {USED_INDEX, PERCENT_INDEX, ONE_INDEX};
2: playbackSeq[91:23] <= {USED_INDEX, PERCENT_INDEX, TWO_INDEX};
3: playbackSeq[91:23] <= {USED_INDEX, PERCENT_INDEX, THREE_INDEX};
4: playbackSeq[91:23] <= {USED_INDEX, PERCENT_INDEX, FOUR_INDEX};
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5: playbackSeq[91:23] <= {USED_INDEX, PERCENT_INDEX, FIVE_INDEX};
6: playbackSeq[91:23] <= {USED_INDEX, PERCENT_INDEX, SIX_INDEX};
7: playbackSeq[91:23] <= {USED_INDEX, PERCENT_INDEX, SEVEN_INDEX};
8: playbackSeq[91:23] <= {USED_INDEX, PERCENT_INDEX, EIGHT_INDEX};
9: playbackSeq[91:23] <= {USED_INDEX, PERCENT_INDEX, NINE_INDEX};
default: playbackSeq <= {USED_INDEX, PERCENT_INDEX, UNUSED_INDEX}; // error
endcase
case (tens)
0: playbackSeq[22:0] <= SKIP_INDEX;
1: playbackSeq[22:0] <= TEN_INDEX;
2: playbackSeq[22:0] <= TWENTY_INDEX;
3: playbackSeq[22:0] <= THIRTY_INDEX;
4: playbackSeq[22:0] <= FOURTY_INDEX;
5: playbackSeq[22:0] <= FIFTY_INDEX;
6: playbackSeq[22:0] <= SIXTY_INDEX;
7: playbackSeq[22:0] <= SEVENTY_INDEX;
8: playbackSeq[22:0] <= EIGHTY_INDEX;
9: playbackSeq[22:0] <= NINETY_INDEX;
default: playbackSeq[22:0] <= UNUSED_INDEX;
endcase
case (hundreds)
0: begin end
1: playbackSeq <= {UNUSED_INDEX, USED_INDEX, PERCENT_INDEX, HUNDRED_INDEX}; // e
endcase
case (audioSelector)
11: playbackSeq <= {UNUSED_INDEX, USED_INDEX, PERCENT_INDEX, ELEVEN_INDEX};
12: playbackSeq <= {UNUSED_INDEX, USED_INDEX, PERCENT_INDEX, TWELVE_INDEX};
13: playbackSeq <= {UNUSED_INDEX, USED_INDEX, PERCENT_INDEX, THIRTEEN_INDEX};
14: playbackSeq <= {UNUSED_INDEX, USED_INDEX, PERCENT_INDEX, FOURTEEN_INDEX};
15: playbackSeq <= {UNUSED_INDEX, USED_INDEX, PERCENT_INDEX, FIFTEEN_INDEX};
16: playbackSeq <= {USED_INDEX, PERCENT_INDEX, TEEN_INDEX, SIX_INDEX};
17: playbackSeq <= {USED_INDEX, PERCENT_INDEX, TEEN_INDEX, SEVEN_INDEX};
18: playbackSeq <= {USED_INDEX, PERCENT_INDEX, TEEN_INDEX, EIGHT_INDEX};
19: playbackSeq <= {USED_INDEX, PERCENT_INDEX, TEEN_INDEX, NINE_INDEX};
default: begin end
endcase
end // if (audioTrigger & ~lastAudioTrigger)
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// just started playing - need to set raddr
// Assuming this happens once playbackSeq has been properly set
if (playing & ~lastPlaying) begin
if (playbackSeq[22:0] == SKIP_INDEX) begin
playbackSeq <= {UNUSED_INDEX, playbackSeq[91:23]};
raddr <= playbackSeq[45:23] * TRACK_LENGTH;
trackEndAddr <= playbackSeq[45:23] * TRACK_LENGTH + TRACK_LENGTH;
end
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else begin
raddr <= playbackSeq[22:0] * TRACK_LENGTH;
trackEndAddr <= playbackSeq[22:0] * TRACK_LENGTH + TRACK_LENGTH;
end
end
end // if (~writeSwitch)
end // if (startSwitch)
else begin
// TO ENABLE RESET:
// writemode <= 1
// dowrite <= 0
// doread <= 0 // to be safe
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// Reset First, Write Second, Read Later
writemode <= 1’h1;
doread <= 1’h0;
dowrite <= 1’h0;
end
end // always @
endmodule
A.3.13
1
2
binaryToDecimal.py
# Shawn Jain
# Python script to generate LUT for BCD.v
3
4
5
6
for i in range(100):
print str(i) + ’: begin ’ + ’ones <= ’ + str(i%10) + ’; ’ + ’tens <= ’ + str(i/10) +
print ’default: begin ones <= 0; tens <= 0; end’
A.3.14
1
2
3
BCD.v
// Shawn Jain
// Converts an 8-bit binary number into a decimal representation
// LUT generated from assets/binaryToDecimal.py
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5
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7
8
9
module BCD(
input wire
output reg
output reg
output reg
[7:0]
[3:0]
[3:0]
[3:0]
number,
hundreds,
tens,
ones);
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12
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14
always @ (number) begin
case(number)
0: begin ones <= 0; tens <= 0; end
1: begin ones <= 1; tens <= 0; end
241
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2: begin ones <= 2; tens <= 0; end
3: begin ones <= 3; tens <= 0; end
4: begin ones <= 4; tens <= 0; end
5: begin ones <= 5; tens <= 0; end
6: begin ones <= 6; tens <= 0; end
7: begin ones <= 7; tens <= 0; end
8: begin ones <= 8; tens <= 0; end
9: begin ones <= 9; tens <= 0; end
10: begin ones <= 0; tens <= 1; end
11: begin ones <= 1; tens <= 1; end
12: begin ones <= 2; tens <= 1; end
13: begin ones <= 3; tens <= 1; end
14: begin ones <= 4; tens <= 1; end
15: begin ones <= 5; tens <= 1; end
16: begin ones <= 6; tens <= 1; end
17: begin ones <= 7; tens <= 1; end
18: begin ones <= 8; tens <= 1; end
19: begin ones <= 9; tens <= 1; end
20: begin ones <= 0; tens <= 2; end
21: begin ones <= 1; tens <= 2; end
22: begin ones <= 2; tens <= 2; end
23: begin ones <= 3; tens <= 2; end
24: begin ones <= 4; tens <= 2; end
25: begin ones <= 5; tens <= 2; end
26: begin ones <= 6; tens <= 2; end
27: begin ones <= 7; tens <= 2; end
28: begin ones <= 8; tens <= 2; end
29: begin ones <= 9; tens <= 2; end
30: begin ones <= 0; tens <= 3; end
31: begin ones <= 1; tens <= 3; end
32: begin ones <= 2; tens <= 3; end
33: begin ones <= 3; tens <= 3; end
34: begin ones <= 4; tens <= 3; end
35: begin ones <= 5; tens <= 3; end
36: begin ones <= 6; tens <= 3; end
37: begin ones <= 7; tens <= 3; end
38: begin ones <= 8; tens <= 3; end
39: begin ones <= 9; tens <= 3; end
40: begin ones <= 0; tens <= 4; end
41: begin ones <= 1; tens <= 4; end
42: begin ones <= 2; tens <= 4; end
43: begin ones <= 3; tens <= 4; end
44: begin ones <= 4; tens <= 4; end
45: begin ones <= 5; tens <= 4; end
46: begin ones <= 6; tens <= 4; end
47: begin ones <= 7; tens <= 4; end
242
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
48:
49:
50:
51:
52:
53:
54:
55:
56:
57:
58:
59:
60:
61:
62:
63:
64:
65:
66:
67:
68:
69:
70:
71:
72:
73:
74:
75:
76:
77:
78:
79:
80:
81:
82:
83:
84:
85:
86:
87:
88:
89:
90:
91:
92:
93:
begin
begin
begin
begin
begin
begin
begin
begin
begin
begin
begin
begin
begin
begin
begin
begin
begin
begin
begin
begin
begin
begin
begin
begin
begin
begin
begin
begin
begin
begin
begin
begin
begin
begin
begin
begin
begin
begin
begin
begin
begin
begin
begin
begin
begin
begin
ones
ones
ones
ones
ones
ones
ones
ones
ones
ones
ones
ones
ones
ones
ones
ones
ones
ones
ones
ones
ones
ones
ones
ones
ones
ones
ones
ones
ones
ones
ones
ones
ones
ones
ones
ones
ones
ones
ones
ones
ones
ones
ones
ones
ones
ones
<=
<=
<=
<=
<=
<=
<=
<=
<=
<=
<=
<=
<=
<=
<=
<=
<=
<=
<=
<=
<=
<=
<=
<=
<=
<=
<=
<=
<=
<=
<=
<=
<=
<=
<=
<=
<=
<=
<=
<=
<=
<=
<=
<=
<=
<=
8;
9;
0;
1;
2;
3;
4;
5;
6;
7;
8;
9;
0;
1;
2;
3;
4;
5;
6;
7;
8;
9;
0;
1;
2;
3;
4;
5;
6;
7;
8;
9;
0;
1;
2;
3;
4;
5;
6;
7;
8;
9;
0;
1;
2;
3;
tens
tens
tens
tens
tens
tens
tens
tens
tens
tens
tens
tens
tens
tens
tens
tens
tens
tens
tens
tens
tens
tens
tens
tens
tens
tens
tens
tens
tens
tens
tens
tens
tens
tens
tens
tens
tens
tens
tens
tens
tens
tens
tens
tens
tens
tens
243
<=
<=
<=
<=
<=
<=
<=
<=
<=
<=
<=
<=
<=
<=
<=
<=
<=
<=
<=
<=
<=
<=
<=
<=
<=
<=
<=
<=
<=
<=
<=
<=
<=
<=
<=
<=
<=
<=
<=
<=
<=
<=
<=
<=
<=
<=
4;
4;
5;
5;
5;
5;
5;
5;
5;
5;
5;
5;
6;
6;
6;
6;
6;
6;
6;
6;
6;
6;
7;
7;
7;
7;
7;
7;
7;
7;
7;
7;
8;
8;
8;
8;
8;
8;
8;
8;
8;
8;
9;
9;
9;
9;
end
end
end
end
end
end
end
end
end
end
end
end
end
end
end
end
end
end
end
end
end
end
end
end
end
end
end
end
end
end
end
end
end
end
end
end
end
end
end
end
end
end
end
end
end
end
107
108
109
110
111
112
113
114
115
116
117
94: begin ones
95: begin ones
96: begin ones
97: begin ones
98: begin ones
99: begin ones
default: begin
endcase
hundreds <= 0;
end
endmodule
<= 4; tens
<= 5; tens
<= 6; tens
<= 7; tens
<= 8; tens
<= 9; tens
ones <= 0;
<= 9; end
<= 9; end
<= 9; end
<= 9; end
<= 9; end
<= 9; end
tens <= 0; end
118
119
120
// Note: a computational logic based binary to BCD is found at:
// http://www.deathbylogic.com/2013/12/binary-to-binary-coded-decimal-bcd-converter/
121
122
123
124
125
126
module BCDTest;
reg [7:0] number = 8’d65;
wire [3:0] hundreds;
wire [3:0] tens;
wire [3:0] ones;
127
128
129
130
131
132
133
134
BCD bc(number, hundreds, tens, ones);
initial begin
#100
$display("%d, %d, %d", hundreds, tens, ones);
$stop();
end
endmodule
A.3.15
1
2
3
ClockDivider.v
// Shawn Jain
// From Lab 4
// Sends a pulse on oneHertz_enable every Hz clock cycles
4
5
6
7
8
module ClockDivider #(parameter Hz = 27000000)(
input clock, reset, fastMode,
output reg oneHertz_enable
);
9
10
reg [24:0] counter = 25’b0;
11
12
13
14
15
always @ (posedge clock) begin
if (reset) begin
counter <= 25’b0;
oneHertz_enable <= 1’b0;
244
end
else if (counter == (fastMode ? 3:Hz)) begin
oneHertz_enable <= 1’b1;
counter <= 25’b0;
end
else begin
counter <= counter + 1;
oneHertz_enable <= 1’b0;
end
16
17
18
19
20
21
22
23
24
end
25
26
27
endmodule
A.3.16
1
2
3
Square.v
// Shawn Jain
// From Lab 4
// Generates a square wave that flips every Hz clock cycles
4
5
6
7
module Square #(parameter Hz = 27000000) (
input clock, reset,
output reg square = 0);
8
9
wire oneHertz_enable;
10
11
12
13
14
15
16
ClockDivider #(.Hz(Hz)) Sqr (
.clock(clock),
.reset(reset),
.fastMode(1’b0),
.oneHertz_enable(oneHertz_enable)
);
17
18
19
20
21
always @ (posedge oneHertz_enable) begin
square <= ~square;
end
endmodule
245