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PSoC™ Mixed-Signal Array
Final Data Sheet
CY8C21234, CY8C21334,
CY8C21434, CY8C21534, and CY8C21634
Features
■ Flexible On-Chip Memory
■ Powerful Harvard Architecture Processor
❐ 8K Flash Program Storage 50,000 Erase/Write
Cycles
❐ 512 Bytes SRAM Data Storage
❐ In-System Serial Programming (ISSP™)
❐ Partial Flash Updates
❐ Flexible Protection Modes
❐ EEPROM Emulation in Flash
❐
❐
❐
❐
M8C Processor Speeds to 24 MHz
Low Power at High Speed
2.4V to 5.25V Operating Voltage
Operating Voltages Down to 1.0V Using
On-Chip Switch Mode Pump (SMP)
❐ Industrial Temperature Range: -40°C to +85°C
■ Advanced Peripherals (PSoC Blocks)
❐ 4 Analog Type “E” PSoC Blocks Provide:
■ Complete Development Tools
❐ Free Development Software
(PSoC™ Designer)
❐ Full-Featured, In-Circuit Emulator and
Programmer
❐ Full Speed Emulation
❐ Complex Breakpoint Structure
❐ 128K Trace Memory
- 2 Comparators with DAC Refs
- Single or Dual 8-Bit 28 Channel ADC
❐ 4 Digital PSoC Blocks Provide:
- 8- to 32-Bit Timers, Counters, and PWMs
- CRC and PRS Modules
- Full-Duplex UART, SPI™ Master or Slave
- Connectable to All GPIO Pins
❐ Complex Peripherals by Combining Blocks
Port 3
Port 2
Port 1
■ Precision, Programmable Clocking
❐ Internal ±2.5% 24/48 MHz Oscillator
❐ Internal Oscillator for Watchdog and Sleep
SystemBus
Global Analog Interconnect
SRAM
512 Bytes
SROM
Flash 8K
CPU Core
(M8C)
Interrupt
Controller
Sleep and
Watchdog
Clock Sources
(Includes IMO and ILO)
DIGITAL SYSTEM
ANALOG SYSTEM
Analog
PSoC
Block
Array
Digital
PSoC
Block
Array
❐ 25 mA Drive on All GPIO
❐ Pull Up, Pull Down, High Z, Strong, or Open
Drain Drive Modes on All GPIO
❐ Up to 8 Analog Inputs on GPIO
❐ Configurable Interrupt on All GPIO
■ Versatile Analog Mux
❐ Common Internal Analog Bus
❐ Simultaneous Connection of IO Combinations
❐ Capacitive Sensing Application Capability
■ Additional System Resources
❐ I2C™ Master, Slave and Multi-Master to
400 kHz
❐ Watchdog and Sleep Timers
❐ User-Configurable Low Voltage Detection
❐ Integrated Supervisory Circuit
❐ On-Chip Precision Voltage Reference
PSoC™ Functional Overview
Port 0
PSoC
CORE
Global Digital
Interconnect
■ Programmable Pin Configurations
Analog
Ref.
The PSoC™ family consists of many Mixed-Signal Array with
On-Chip Controller devices. These devices are designed to
replace multiple traditional MCU-based system components
with one, low cost single-chip programmable component. A
PSoC device includes configurable blocks of analog and digital
logic, as well as programmable interconnect. This architecture
allows the user to create customized peripheral configurations,
to match the requirements of each individual application. Additionally, a fast CPU, Flash program memory, SRAM data memory, and configurable IO are included in a range of convenient
pinouts.
The PSoC architecture, as illustrated on the left, is comprised of
four main areas: the Core, the System Resources, the Digital
System, and the Analog System. Configurable global bus
resources allow all the device resources to be combined into a
complete custom system. Each CY8C21x34 PSoC device
includes four digital blocks and four analog blocks. Depending
on the PSoC package, up to 28 general purpose IO (GPIO) are
also included. The GPIO provide access to the global digital
and analog interconnects.
The PSoC Core
Digital
Clocks
POR and LVD
I2C
System Resets
Sw itch
Mode
Pump
SYSTEM RESOURCES
April 20, 2005
Internal
Voltage
Ref.
Analog
Mux
The PSoC Core is a powerful engine that supports a rich
instruction set. It encompasses SRAM for data storage, an
interrupt controller, sleep and watchdog timers, and IMO (internal main oscillator) and ILO (internal low speed oscillator). The
© Cypress Semiconductor Corp. 2004-2005 — Document No. 38-12025 Rev. *G
1
CY8C21x34 Final Data Sheet
PSoC™ Overview
Additional System Resources
System Resources, some of which have been previously listed,
provide additional capability useful to complete systems. Additional resources include a switch mode pump, low voltage
detection, and power on reset. Brief statements describing the
merits of each system resource are presented below.
Array Input
Configuration
ACI0[1:0]
■
Digital clock dividers provide three customizable clock frequencies for use in applications. The clocks can be routed to
both the digital and analog systems. Additional clocks can be
generated using digital PSoC blocks as clock dividers.
■
The I2C module provides 100 and 400 kHz communication
over two wires. Slave, master, and multi-master modes are
all supported.
■
Low Voltage Detection (LVD) interrupts can signal the application of falling voltage levels, while the advanced POR
(Power On Reset) circuit eliminates the need for a system
supervisor.
■
An internal 1.3 voltage reference provides an absolute reference for the analog system, including ADCs and DACs.
■
An integrated switch mode pump (SMP) generates normal
operating voltages from a single 1.2V battery cell, providing a
low cost boost converter.
■
Versatile analog multiplexer system.
ACI1[1:0]
All IO
X
X
X
ACOL1MUX
X
AnalogMuxBus
X
Array
ACE00
ACE01
ASE10
ASE11
Analog System Block Diagram
PSoC Device Characteristics
The Analog Multiplexer System
The Analog Mux Bus can connect to every GPIO pin. Pins can
be connected to the bus individually or in any combination. The
bus also connects to the analog system for analysis with comparators and analog-to-digital converters. An additional 8:1 analog input multiplexer provides a second path to bring Port 0 pins
to the analog array.
Digital
Rows
Digital
Blocks
Analog
Inputs
Analog
Outputs
Analog
Columns
Analog
Blocks
SRAM
Size
Flash
Size
PSoC Device Characteristics
Digital
IO
Switch control logic enables selected pins to precharge continuously under hardware control. This enables capacitive measurement for applications such as touch sensing. Other
multiplexer applications include:
Depending on your PSoC device characteristics, the digital and
analog systems can have 16, 8, or 4 digital blocks and 12, 6, or
4 analog blocks. The following table lists the resources
available for specific PSoC device groups. The PSoC device
covered by this data sheet is highlighted below.
CY8C29x66
up to
64
4
16
12
4
4
12
2K
32K
Chip-wide mux that allows analog input from any IO pin.
CY8C27x43
up to
44
2
8
12
4
4
12
256
Bytes
16K
Crosspoint connection between any IO pin combinations.
CY8C24794
50
1
4
48
2
2
6
1K
16K
CY8C24x23
up to
24
1
4
12
2
2
6
256
Bytes
4K
CY8C24x23A
up to
24
1
4
12
2
2
6
256
Bytes
4K
CY8C21x34
up to
28
1
4
28
0
2
4a
512
Bytes
8K
CY8C21x23
16
1
4
8
0
2
4a
256
Bytes
4K
■
Track pad, finger sensing.
■
■
PSoC Part
Number
a. Limited analog functionality.
April 20, 2005
Document No. 38-12025 Rev. *G
3
CY8C21x34 Final Data Sheet
1.1.4
1. Pin Information
32-Pin Part Pinout
Table 1-4. 32-Pin Part Pinout (MLF*)
IO
M
P2[7]
3
IO
M
P2[5]
4
IO
M
P2[3]
5
IO
M
P2[1]
6
IO
6
7
M
Power
IO
7
M
Power
P3[3]
In CY8C21434 part.
SMP
Switch Mode Pump (SMP) connection to
required external components in
CY8C21634 part.
P3[1]
In CY8C21434 part.
Vss
Ground connection in CY8C21634 part.
8
IO
M
P1[7]
I2C Serial Clock (SCL).
I2C Serial Data (SDA).
9
IO
M
P1[5]
10
IO
M
P1[3]
11
IO
M
P1[1]
12
Power
Ground connection.
I2C Serial Data (SDA), ISSP-SDATA.
IO
M
P1[0]
14
IO
M
P1[2]
15
IO
M
P1[4]
16
IO
M
P1[6]
17
Input
XRES
Active high external reset with internal
pull down.
IO
M
19
IO
M
P3[2]
20
IO
M
P2[0]
21
IO
M
P2[2]
22
IO
M
P2[4]
23
IO
M
P2[6]
24
IO
I, M
P0[0]
Analog column mux input.
25
IO
I, M
P0[2]
Analog column mux input.
26
IO
I, M
P0[4]
Analog column mux input.
27
IO
I, M
P0[6]
Analog column mux input.
Vdd
Supply voltage.
IO
I, M
P0[7]
Analog column mux input.
30
IO
I, M
P0[5]
Analog column mux input.
31
IO
I, M
P0[3]
Analog column mux input, integrating
input.
Vss
Ground connection.
Power
24
23
22
21
20
19
18
17
P0[0], A, I, M
P2[6], M
P2[4], M
P2[2], M
P2[0], M
P3[2], M
P3[0], M
XRES
CY8C21634 32-Pin PSoC Device
A, I, M, P0[1]
M, P2[7]
M, P2[5]
M, P2[3]
M, P2[1]
SMP
Vss
M, I2C SCL, P1[7]
LEGEND A = Analog, I = Input, O = Output, and M = Analog Mux Input.
* The MLF package has a center pad that must be connected to ground
(Vss).
April 20, 2005
MLF
(Top View )
P3[0]
29
32
Power
1
2
3
4
5
6
7
8
Optional External Clock Input (EXTCLK).
18
28
A, I, M, P0[1]
M, P2[7]
M, P2[5]
M, P2[3]
M, P2[1]
M, P3[3]
M, P3[1]
M, I2C SCL, P1[7]
I2C Serial Clock (SCL), ISSP-SCLK.
Vss
13
Vss
P0[3], A, I, M
P0[5], A, I, M
P0[7], A, I, M
Vdd
P0[6], A, I, M
P0[4], A, I, M
P0[2], A, I, M
2
Analog column mux input, integrating
input.
32
31
30
29
28
27
26
25
P0[1]
9
10
11
12
13
14
15
16
I, M
CY8C21434 32-Pin PSoC Device
M, I2C SDA, P1[5]
M, P1[3]
M, I2C SCL, P1[1]
Vss
M, I2C SDA, P1[0]
M, P1[2]
M, EXTCLK, P1[4]
M, P1[6]
IO
Description
Vss
P0[3], A, I, M
P0[5], A, I, M
P0[7], A, I, M
Vdd
P0[6], A, I, M
P0[4], A, I, M
P0[2], A, I, M
1
Name
Document No. 38-12025 Rev. *G
1
2
3
4
5
6
7
8
32
31
30
29
28
27
26
25
Analog
MLF
(Top View )
24
23
22
21
20
19
18
17
9
10
11
12
13
14
15
16
Digital
P0[0], A, I, M
P2[6], M
P2[4], M
P2[2], M
P2[0], M
P3[2], M
P3[0], M
XRES
M, I2C SDA, P1[5]
M, P1[3]
M, I2C SCL, P1[1]
Vss
M, I2C SDA, P1[0]
M, P1[2]
M, EXTCLK, P1[4]
M, P1[6]
Type
Pin
No.
11
4. Packaging Information
This chapter illustrates the packaging specifications for the CY8C21x34 PSoC device, along with the thermal impedances for each
package.
Important Note Emulation tools may require a larger area on the target PCB than the chip’s footprint. For a detailed description of
the emulation tools’ dimensions, refer to the document titled PSoC Emulator Pod Dimensions at
http://www.cypress.com/support/link.cfm?mr=poddim.
4.1
Packaging Dimensions
PIN 1 ID
8
1
MIN.
MAX.
DIMENSIONS IN INCHES[MM]
*
0.291[7.391]
0.299[7.594]
REFERENCE JEDEC MO-119
*
0.394[10.007]
0.419[10.642]
9
16
PART #
S16.3 STANDARD PKG.
SZ16.3 LEAD FREE PKG.
0.026[0.660]
0.032[0.812]
SEATING PLANE
0.397[10.083]
0.413[10.490]
0.092[2.336]
0.105[2.667]
*
0.004[0.101]
0.050[1.270]
TYP.
0.004[0.101]
0.0118[0.299]
*
0.015[0.381]
0.050[1.270]
0.0091[0.231]
0.0125[0.317]
0.013[0.330]
0.019[0.482]
51-85022 *B
Figure 4-1. 16-Lead (150-Mil) SOIC
April 20, 2005
Document No. 38-12025 Rev. *G
30
CY8C21x34 Final Data Sheet
4. Packaging Information
51-85077 *C
Figure 4-2. 20-Lead (210-MIL) SSOP
51-85079 - *C
Figure 4-3. 28-Lead (210-Mil) SSOP
April 20, 2005
Document No. 38-12025 Rev. *G
31
CY8C21x34 Final Data Sheet
4. Packaging Information
51-85188 **
E-PAD X, Y for this product is 3.71 mm, 3.71 mm (+/-0.08 mm)
Figure 4-4. 32-Lead (5x5 mm) MLF
Important Note For information on the preferred dimensions for mounting MLF packages, see the following Application Note at
http://www.amkor.com/products/notes_papers/MLFAppNote.pdf.
4.2
Thermal Impedances
Table 4-1. Thermal Impedances per Package
Package
Typical
θJA *
Typical
θJC
16 SOIC
123 oC/W
55 oC/W
20 SSOP
117 oC/W
41 oC/W
28 SSOP
32 MLF
o
39 oC/W
o
12 oC/W
96 C/W
22 C/W
* TJ = TA + Power x θJA
April 20, 2005
Document No. 38-12025 Rev. *G
32
CY8C21x34 Final Data Sheet
4.3
4. Packaging Information
Solder Reflow Peak Temperature
Following is the minimum solder reflow peak temperature to achieve good solderability.
Table 4-2. Solder Reflow Peak Temperature
Package
Minimum Peak Temperature*
Maximum Peak Temperature
16 SOIC
240oC
260oC
20 SSOP
240oC
260oC
28 SSOP
240oC
260oC
32 MLF
240oC
260oC
*Higher temperatures may be required based on the solder melting point. Typical temperatures for solder are 220+/-5oC
with Sn-Pb or 245+/-5oC with Sn-Ag-Cu paste. Refer to the solder manufacturer specifications.
April 20, 2005
Document No. 38-12025 Rev. *G
33
5. Ordering Information
The following table lists the CY8C21x34 PSoC device’s key package features and ordering codes.
Temperature
Range
Digital
Blocks
Analog
Blocks
Digital IO
Pins
Analog
Outputs
XRES Pin
8K
512
Yes
-40°C to +85°C
4
4
12
12a
0
No
16 Pin (150-Mil) SOIC
(Tape and Reel)
CY8C21234-24SXIT
8K
512
Yes
-40°C to +85°C
4
4
12
12a
0
No
20 Pin (210-Mil) SSOP
CY8C21334-24PVXI
8K
512
No
-40°C to +85°C
4
4
16
16a
0
Yes
20 Pin (210-Mil) SSOP
(Tape and Reel)
CY8C21334-24PVXIT
8K
512
No
-40°C to +85°C
4
4
16
16a
0
Yes
28 Pin (210-Mil) SSOP
CY8C21534-24PVXI
8K
512
No
-40°C to +85°C
4
4
24
24a
0
Yes
28 Pin (210-Mil) SSOP
(Tape and Reel)
CY8C21534-24PVXIT
8K
512
No
-40°C to +85°C
4
4
24
24a
0
Yes
32 Pin (5x5) MLF b
CY8C21434-24LFXI
8K
512
No
-40°C to +85°C
4
4
28
28a
0
Yes
CY8C21434-24LFXIT
8K
512
No
-40°C to +85°C
4
4
28
28a
0
Yes
32 Pin (5x5) MLF b
CY8C21634-24LFXI
8K
512
Yes
-40°C to +85°C
4
4
26
26a
0
Yes
32 Pin (5x5) MLF b
(Tape and Reel)
CY8C21634-24LFXIT
8K
512
Yes
-40°C to +85°C
4
4
26
26a
0
Yes
Package
32 Pin (5x5) MLF
(Tape and Reel)
b
Analog
Switch Mode
Pump
CY8C21234-24SXI
Inputs a
SRAM
(Bytes)
16 Pin (150-Mil) SOIC
Ordering
Code
Flash
(Bytes)
CY8C21x34 PSoC Device Key Features and Ordering Information
a. All Digital IO Pins also connect to the common analog mux.
b. Refer to the “32-Pin Part Pinout” on page 11 for pin differences.
5.1
Ordering Code Definitions
CY 8 C 21 xxx-24xx
Package Type:
PX = PDIP Pb-Free
SX = SOIC Pb-Free
PVX = SSOP Pb-Free
LFX = MLF Pb-Free
AX = TQFP Pb-Free
Thermal Rating:
C = Commercial
I = Industrial
E = Extended
Speed: 24 MHz
Part Number
Family Code
Technology Code: C = CMOS
Marketing Code: 8 = Cypress MicroSystems
Company ID: CY = Cypress
April 20, 2005
Document No. 38-12025 Rev. *G
34
6. Sales and Service Information
To obtain information about Cypress Semiconductor or PSoC sales and technical support, reference the following information.
Cypress Semiconductor
2700 162nd Street SW, Building D
Lynnwood, WA 98037
Web Sites:
6.1
Phone: 800.669.0557
Facsimile: 425.787.4641
Company Information – http://www.cypress.com
Sales – http://www.cypress.com/aboutus/sales_locations.cfm
Technical Support – http://www.cypress.com/support/login.cfm
Revision History
Document Title:
CY8C21234, CY8C21334, CY8C21434, CY8C21534, and CY8C21634 PSoC Mixed-Signal Array Final Data Sheet
Document Number: 38-12025
Origin of
Revision ECN # Issue Date
Description of Change
Change
**
227340
5/19/2004
HMT
New silicon and document (Revision **).
*A
235992
See ECN
SFV
Updated Overview and Electrical Spec. chapters, along with revisions to the 24-pin pinout part.
Revised the register mapping tables. Added a SSOP 28-pin part.
*B
248572
See ECN
SFV
Changed title to include all part #s. Changed 28-pin SSOP from CY8C21434 to CY8C21534.
Changed pin 9 on the 28-pin SSOP from SMP pin to Vss pin. Added SMP block to architecture
diagram. Update Electrical Specifications. Added another 32-pin MLF part: CY8C21634.
277832
See ECN
HMT
Verify data sheet standards from SFV memo. Add Analog Input Mux to applicable pin outs.
Update PSoC Characteristics table. Update diagrams and specs. Final.
*D
285293
See ECN
HMT
Update 2.7V DC GPIO spec. Add Reflow Peak Temp. table.
*E
301739
See ECN
HMT
DC Chip-Level Specification changes. Update links to new CY.com Portal.
329104
See ECN
HMT
Re-add pinout ISSP notation. Fix TMP register names. Clarify ADC feature. Update Electrical
Specifications. Update Reflow Peak Temp. table. Add 32 MLF E-PAD dimensions. Add ThetaJC to
Thermal Impedance table. Fix 20-pin package order number. Add CY logo. Update CY copyright.
352736
See ECN
HMT
Add new color and logo. Add URL to preferred dimensions for mounting MLF packages. Update
Transmitter and Receiver AC Digital Block Electrical Specifications.
*C
*F
*G
Distribution: External/Public
6.2
Posting: None
Copyrights and Code Protection
Copyrights © Cypress Semiconductor Corp. 2004-2005. All rights reserved. PSoC™, PSoC Designer™, and Programmable System-on-Chip™ are PSoC-related trademarks of Cypress Semiconductor Corp. All other trademarks or registered trademarks referenced herein are property of the respective corporations.
The information contained herein is subject to change without notice. Cypress Semiconductor assumes no responsibility for the use of any circuitry other than circuitry
embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies
Cypress Semiconductor against all charges. Cypress Semiconductor products are not warranted nor intended to be used for medical, life-support, life-saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress Semiconductor.
Flash Code Protection Note the following details of the Flash code protection features on Cypress Semiconductor PSoC devices.
Cypress Semiconductor products meet the specifications contained in their particular data sheets. Cypress Semiconductor believes that its PSoC family of products is one
of the most secure families of its kind on the market today, regardless of how they are used. There may be methods, unknown to Cypress Semiconductor, that can breach
the code protection features. Any of these methods, to our knowledge, would be dishonest and possibly illegal. Neither Cypress Semiconductor nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not mean that we are guaranteeing the product as "unbreakable."
Cypress Semiconductor is willing to work with the customer who is concerned about the integrity of their code. Code protection is constantly evolving. We at Cypress
Semiconductor are committed to continuously improving the code protection features of our products.
April 20, 2005
© Cypress Semiconductor Corp. 2004-2005 — Document No. 38-12025 Rev. *G
35