Agilent J-BERT M8020A High-Performance BERT - TRS

Agilent J-BERT M8020A
High-Performance BERT
Master Your Next Designs
Data Sheet Version 1.0
Key features:
• Data rates up to 8.5 and 16
Gb/s expandable to 32 Gb/s
• 1 to 4 BERT channels in a
5-slot AXIe chassis
• Integrated and calibrated
jitter injection: RJ, PJ1, PJ2,
SJ, BUJ, sinusoidal level
interference (common-mode
and differential-mode), SSC
(triangular and arbitrary,
residual) and Clock/2
• 8 tap de-emphasis, positive
and negative
• Interactive link training for
PCI Express
• Built-in clock recovery and
equalization
Description
The high-performance Agilent J-BERT M8020A enables fast and accurate receiver
characterization of single- and multi-lane devices running up to 16 or 32 Gb/s.
With today’s highest level of integration, the M8020A streamlines your test setup. In
addition, automated in situ calibration of signal conditions ensures accurate and repeatable
measurements. And, through interactive link training, it can behave like your DUT’s link partner.
All in all, the J-BERT M8020A will accelerate insight into your design.
M8000 Series of BER Test Solutions
Simplified time-efficient testing is essential when you are developing next-generation computer, consumer, or communication devices.
The Agilent M8000 Series is a highly integrated BER test solution for physical layer characterization, validation, and compliance testing.
With support for a wide range of data rates and standards, the M8000 Series provides accurate, reliable results that accelerate your insight into
the performance margins of high-speed digital devices.
Shift into high gear with the M8000 Series and take the design verification express lane.
Figure 1. The M8000 Series BER Test Solution is highly integrated and scalable to address the test challenges of the next generation of high-speed digital
receiver test.
2
J-BERT M8020A high-performance BERT
Enabling fast, accurate receiver characterization of single- and multi-lane devices running up to
16 or 32 Gb/s.
Highest level of integration for streamlined test setups
With J-BERT M8020A all receiver (RX) test capabilities are built-in: jitter sources, common- and differential-mode level interference, and
de-emphasis to emulate the transmitter (TX) of the device under test (DUT). In addition M8020A provides a built-in reference clock multiplier for
synchronization of the BERT pattern generator with the DUT’s reference clock which can carry spread spectrum clocking (SSC). On the analyzer
side an equalizer to open closed eyes and a clock recovery with adjustable loop bandwidth for the analyzer is built-in.
With this high level of integration a receiver test set-up with M8020A is now much easier to connect and more robust. Set up and debug time is
shortened, calibration is simpler and the frequency of recalibration is lower, resulting in more efficient use of overall test time.
Figure 2: J-BERT M8020A streamlines complex receiver test setups. The example shows a PCIe 3 (8 GT/s) mother board RX test (CEM spec) with J-BERT
M8020A connected via a compliance load board (CLB). J-BERT M8020A provides built-in de-emphasis, jitter sources, common-mode and differential mode
interference (CMI, DMI), reference clock multiplier, clock recovery and continuous time linear equalizer (CTLE) – everything that is needed is built-in and
calibrated.
3
In situ calibration for the most accurate and repeatable results
At data rates above 5 Gb/s, the influence of the channel (PC-board, cable, connectors) between transmitter (TX) and receiver (RX) is no
longer negligible. The reference point for the RX specification moves to the RX input, the test set-up typically has to contain a certain channel
characteristic, often an ISI channel, as well. To accurately inject a defined stress condition to the RX in situ calibration is required: at that same
exact point where the receiver under test has to be connected during test, a reference load is connected instead and the generated signal is
measured. This allows calibration of the test signal at that point where the specification applies by adjusting the instrument generated stress
such as jitter in a way that the target signal with all its ingredients is achieved.
Calibration
SW
Oscilloscope
J-BERT
M8020A
PG
DUT/ASIC
IC
Channel
Instrument calibration
plane
RX
Specification calibration
plane (possible test points)
Figure 3. With increasing bit rates the calibration plane for the receiver stress conditions moves closer to the receiver inputs. J-BERT M8020A supports in situ
calibration to achieve higher accuracy of the signal and stress conditions at the relevant definable test point.
Interactive link training to fasten loopback
The ever increasing data rate of computer buses and datacom interfaces results in shrinking margins and the necessity to use equalization
techniques in transmitters and receivers to compensate for the lossy channels caused by inexpensive PC board material or long cables. For the
latest industry standards, such as PCI Express 3 or 4, SAS 12G, and backplanes such as 100GBASE-KR4, the link partners are required to optimize
the TX de-emphasis and RX equalization combination. The RX takes the active part during this procedure. In order to do so, the BERT must be
capable to understand the low level protocol and to react accordingly, i.e. change its TX de-emphasis as requested. J-BERT M8020A can behave
like a real link partner with its interactive link training capability, initially PCIe is supported.
4
Figure 4. J-BERT M8020A high-performance BERT for accelerated receiver characterization. The configuration shows a 4 channel 16 Gb/s BERT in a 5-slot
AXIe chasssis consisting of one M8041A module with two BERT channels and clock synthesizer and one M8051A extender module with two additional BERT
channels.
Applications
R&D and test engineers who characterize and verify compliance of chips, devices, boards and systems with serial I/O ports up to 16 Gb/s.
The M8020A can be used to test popular serial bus standards, such as PCI Express®, SATA/SAS, DisplayPort, USB Super Speed, MIPI M-PHY,
SD UHS-II, Fibre Channel, QPI, memory buses, backplanes, repeaters, active optical cables, Thunderbolt, 10 GbE/SFP+, 100GbE/CFP2.
Receiver characterization and compliance test
Many multi gigabit serial interfaces use transmitter de-emphasis to compensate for electrical signal degradations caused by printed circuit boards
or cables between the transmitter and the receiver ports. R&D and test engineers who need to characterize receiver ports under realistic and
worst case conditions require a pattern generator that allows to accurately emulate transmitter de-emphasis and the channel with adjustable
8-tap de-emphasis levels.
5
User interface and measurements
Figure 5: The graphical user interface for J-BERT M8020A offers multiple views that can be defined by the user. This example shows the system view on left side
and the pattern generator data output parameters at the right. Preliminary GUI screen as of May 2014.
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Accuracy and performance
Figure 6. Clean 16.0 Gb/s output signal of J-BERT M8020A with M8041A BERT module using its internal
clock source and PRBS 2 15-1 pattern.
Figure 7. The 32 Gb/s output signal shows excellent intrinsic jitter. This shows the output signal of
M8061A when used with M8041A BERT module and its internal clock source and PRBS 2 15-1 pattern.
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Specifications for M8041A and M8051A J-BERT high-performance BERT modules
Figure 8: Front panel view of M8041A module (bottom) and M8051A (top).
8
Specifications pattern generator
Data output (DATA OUT 1, DATA OUT 2)
Table 1. Data output characteristics for M8041A and M8051A.
All timing parameters are measured 0.5 V into ground
M8041A
M8051A
Data rate
256 Mb/s to 8.50 Gb/s (opt. G08 or C08),
256 Mb/s to 16.20 Gb/s (opt. G16 or C16)
x
x
Data format
NRZ
Channels per module
1 or 2 (second channel requires opt. 0G2)
Amplitude
50 mV to 1.2 Vpp single ended,
100 mV to 2.4 Vpp differential,
1 mV resolution;
addresses LVDS, CML, low-voltage CMOS, others.
See table 2 for max. output amplitude in presence of CMI or DMI
Amplitude accuracy
5 % ± 5 mV typical (AC)3
Output voltage window
-1 V to +3.0 V
External termination voltage
-1 V to +3.0 V. For offset > 1.3 V the termination voltage should
be ± 0.5 V of offset
Transition time
15 to 20 ps typical (20%-80%)
Crossing point
Total intrinsic jitter
Adjustable from 30% to 70%
1
8 ps p-p typical
Random intrinsic jitter 2
300 fs rms typical
Data delay range
0 to 10 ns, resolution 100 fs
Data delay accuracy
± 1% ± 20 mUI typical 5 at constant temperature
Deskew accuracy
± 10 ps typical between data out 1 and 2 of the same module
Electrical idle transition time
Output transitions from full swing signal to 0 V amplitude and
vice versa at constant offset within 4 ns typical. Electrical idle can
be controlled from sequencer. Latency is TBD.
Termination
50 Ω into GND or external termination voltage.
Do not operate into open. Unused outputs must be terminated
into termination voltage.
Output protection
Automatic current monitoring and switch off. Operation into open
is possible for these ranges when “DC coupled“ and “balanced“
termination modes are selected:
output amplitude max. 300 mV 4
offset 0 to 270 mV
Termination modes
Balanced/unbalanced
DC/AC coupling
Connectors
3.5 mm, female
1. At 16 Gb/s PRBS 2 15-1, BER 10 -12, with internal clock.
2. At 16 Gb/s and clock pattern.
3. At 256 Mb/s measured with DCA-X 86108B and clock pattern and in the middle of the eye.
4. Per output when differentially terminated into 100 Ω. Results in doubled swing when driving into open.
5. At constant temperature.
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Table 2. Data output amplitude maximum (single ended) in presence of DMI, CMI, offset voltage.
Offset < 1.9 V
Offset > 1.9 V
CMI
DMI
1.2 Vpp
0.9 Vpp
disabled
disabled
0.9 Vpp
0.675 Vpp
disabled
enabled
0.9 Vpp
0.75 Vpp
enabled
disabled
0.675 Vpp
0.562 Vpp
enabled
enabled
0.8 Vpp
0.666 Vpp
enabled
enabled 1
1. For DMI < 12.5 % of amplitude.
De-emphasis (DATA OUT)
M8020A provides built-in de-emphasis with positive and negative cursors based on a finite impulse response (FIR) filter.
Table 3. Specifications for multi-tap de-emphasis (requires option 0G4).
De-emphasis taps
8 (requires opt. 0G4)
can be adjusted for each channel independently
Pre-cursor 2
± 6.0 dB
Pre-cursor 1
± 12.0 dB
Post-cursor 1
± 20.0 dB
Post-cursor 2
± 12.0 dB
Post-cursor 3
± 12.0 dB
Post-cursor 4
± 6.0 dB
Post-cursor 5
± 6.0 dB
De-emphasis tap resolution
± 0.1 dB
De-emphasis tap accuracy
± 1.0 dB 1 typical
M8041A
M8051A
opt. 0G4
opt. 0G4
1. Sum of all cursors may not exceed Vpp max. The tap accuracy applies for PCIe 3 presets for pre-cursor 1 and post-cursor 1 at 8 Gb/s.
Post-cursor 1 = 20log10 Vb/Va
Pe-cursor = 20log10 Vc/Vb
Vpp nominal = 20log10 Vd
Figure 9. Definition of nominal output amplitude and de-emphasis.
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Clock output (CLK OUT)
Table 4. Clock output specifications (M8041A only).
Frequency range
256 MHz to 8.50 GHz (opt. G08 or C08),
256 MHz to 16.20 GHz (opt. G16 or C16)
Frequency resolution
1 Hz
Frequency accuracy
± 15 ppm
Amplitude
0.1 to 1 V, 5 mV steps, single ended
Output voltage window
-1 V to +3 V 1
External termination voltage
-1 V to +3.0 V
Transition times
20 ps typical (20%-80%)
Duty cycle
50%, accuracy ± 15%
Clock divider
1, 2, 4, 8, 10, 16, 20, 24, 30, 32, 40, 50, 64, 66, 80.
For other dividers use TRG output
Clock modes
See table 5
Intrinsic random jitter
300 fs rms typical at 16.2 GHz and clock divider = 1
SSB phase noise
• 85 dBc/ Hz typical at 10 kHz offset and internal clock and 10/100MHz
as external reference clock.
• 80 dBc/Hz with 10 kHz offset for reference clock multiplier bandwidth
0.1/2/5 MHz
2
Termination
50 Ω into GND or external termination voltage. Do not operate into open.
Unused outputs must be terminated into termination voltage.
Connectors
3.5 mm, female
M8041A
M8051A
x
no clk
1. If Vterm is other than 0 V the following applies: high level voltage range = Vterm -1 V to 3 V and low level voltage range = -1 V to Vterm +1 V.
2. For 8.1 to 16.2 GHz clocks.
Table 5. Clock output modes (M8041A only).
Clock mode
Clock generation
Input frequency range
Option G08/ C08
Option G16/ C16
Option
Reference
PLL with bandwidth below 1 kHz
10/100 MHz
10/100 MHz
Direct
No PLL
8.1 GHz to 8.5 GHz
8.1 GHz to 16.2 GHz
Reference clock multiplier
bandwidth 100 kHz
m/n PLL with loop bandwidth 100 kHz
m, n = 1 to 1620
10 MHz to 8.5 GHz
10 MHz to 16.2 GHz
Reference clock multiplying PLL
with loop bandwidth 2 MHz
Integer PLL with loop bandwidth 2 MHz 1
10 to 105 MHz
10 to 105 MHz
0G6
Reference clock multiplying PLL
with loop bandwidth 5 MHz
Integer PLL with loop bandwidth 5 MHz 1
50 to 105 MHz
50 to 105 MHz
0G6
1. Intended use with settings in Table 7 (other settings may be possible, contact factory)
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Reference clock input (REF CLK IN)
This input on the M8041A module allows locking the system clock to an external reference clock of 10 or 100 MHz instead of the internal
oscillator. It also allows to use an external clock, see clock modes.
Table 6. Reference clock input specifications (M8041A only).
Input amplitude
0.2 to 1.4 Vpp
Input frequency
10 MHz to 16.2 GHz, depends on clock mode and max. data rate option
Interface
Single ended. 50 Ω nominal
Connector
SMA, female
M8041A
M8051A
x
no
Table 7. Predefined settings for reference clock multiplier (M8041A with option 0G6 only).
Ref clock input
Standard
Target data rate
Multiplier
PLL loop BW
M8041A
100 MHz
PCIe 4
16 Gb/s
160
2 MHz
0G6
100 MHz
PCIe 3
8 Gb/s
80
5 MHz
100 MHz
PCIe 2
5 Gb/s
50
5 MHz
100 MHz
PCIe 1
2.5 Gb/s
25
5 MHz
26 MHz to 52 MHz
SD UHS-II
390 Mb/s to 780 Mb/s
15
2 MHz
26 MHz to 52 MHz
SD UHS-II
780 MHz to 1.56 Gb/s
30
2 MHz
52 MHz to 104 MHz
SD UHS-II Gen 2
1.56 Gb/s to 3.12 Gb/s
30
2 MHz
52 MHz to 104 MHz
SD UHS-II Gen 2
3.12 Gb/s to 6.24 Gb/s
30
2 MHz
19.2 MHz
MIPI M-PHY
1.248/ 1.4592/ 2.496/
2.9184/ 4.992/ 5.8368 Gb/s
65/ 76/ 130/
152/ 260/ 304
2 MHz
26 MHz
MIPI M-PHY
1.248/ 1.456/ 2.496/ 2.912/ 48/ 56/ 96/
4.992/ 5.824 Gb/s
112/ 192/ 224
2 MHz
38.4 MHz
MIPI M-PHY
1.248/ 1.4592/ 2.496/
2.9184/ 4.992/ 5.8368 Gb/s
2 MHz
52 MHz
MIPI M-PHY
1.248/ 1.456/ 2.496/ 2.912/ 24/ 28/ 48/
4.992/ 5.824 Gb/s
56/ 96/ 112
12
65:2/ 38/ 65/
76/ 130/ 152
2 MHz
Supplementary inputs and outputs of M8041A and M8051A
Trigger output (TRG OUT)
The trigger output can be used in different modes:
1. Divided clock, dividers: 2 to 65535
2. Sequence block trigger with adjustable pulse width and offset
3. PRBS sequence trigger with adjustable pulse width
Table 8. Trigger output specifications (M8041A only).
Amplitude
0.1 to 1 Vpp single ended;
0.2 to 2 Vpp differential
Output voltage window
-1 to 3 V 1
External termination voltage
-1 to 3 V
Interface
Differential, 50 Ω
Connector
3.5 mm, female
M8041A
M8051A
x
no trg
1. If Vterm is other than 0 V the following applies: high level voltage range = Vterm -1 V to 3 V and low level voltage range = -1 V to Vterm +1 V.
Reference clock output (REF CLK OUT)
Outputs a 10 MHz clock, 1 Vpp single ended into 50 Ω. M8041A only.
Connector: SMA, female.
Clock input (CLK IN)
For future use. For M8041A only. See reference clock input for direct clock mode.
Control input A and B (CTRL IN A, CTRL IN B)
Functionality of each input can be selected as: sequence trigger, error add input.
Table 9. Control input specifications (M8041A and M8051A).
Input voltage
-1 V to +3 V
Termination voltage
-1 V to +3 V
Threshold voltage
-1 V to +3 V
Connector
SMA, female
M8041A
M8051A
x
x
M8041A
M8051A
x
x
Control output A (CTRL OUT A)
Outputs a pulse in case of an error.
Table 10. Control output specifications (M8041A and M8051A).
Amplitude
Output voltage
Connector
0.1 to 2 V
1
1
-0.5 to 1.75 V
SMA, female
1. When terminated with 50 Ω into GND. Doubles into open.
13
Synchonization input and output (SYNC IN, SYNC OUT)
The Sync output on M8041A: clock output to synchronize multiple modules to a common clock.
The Sync input is a clock input on M8051A module to synchronize additional modules to a common clock.
A sync cable is delivered with each M8051A module by default.
System input A/B and auxillary input (AUX IN)
Control inputs to synchronize events for the pattern sequencer.
Auxiliary input: for future use. For M8041A only.
Table 11. System input and auxiliary input specifications (M8041A only)
Input voltage
-1 V to +3 V
Termination voltage
-1 V to +3 V
Threshold voltage
-1 V to +3 V
Connector
SMA, female
M8041A
M8051A
x
no
M8041A
M8051A
x
no
System output A/B (SYS OUT A/B)
Control outputs to synchronize events for the pattern sequencer.
Table 12. System output specifications (M8041A only).
Amplitude
1
0.1 to 2 V
Output voltage 1
-0.5 to 1.75 V
Connector
SMA, female
1. When terminated with 50 Ω into GND. Doubles into open.
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Jitter tolerance test specifications
M8020A provides built-in calibrated jitter sources designed to cover receiver test needs for most of the popular multi-gigabit standards such as:
PCIe, USB, MIPI, SATA, DisplayPort, CPU frontside buses, CEI, 10GbE, 100GbE, SFP+, QSFP, CFP2/4, etc.
M8020A provides automated jitter tolerance measurements. A library of pre-defined compliance curves is provided.
Table 13. Specifications for low frequency sinusoidal jitter (requires option 0G3 advanced jitter sources).
Low frequency sinusoidal jitter
(LF SJ )
(generated by IQ modulator)
Amplitude range
0 to 1000 UI. For frequencies
between 10 kHz and 5 MHz see
figure 10 for maximum LF SJ.
For frequencies between
10 kHz and 5 MHz the
max. jitter amplitude =
1.235 ns * 10-3 * data rate
modulation frequency
Frequency
100 Hz to 5 MHz
Jitter amplitude accuracy
± 2 % ± 1 ps typical
Adjustable
For each data channel
independently,
same LF SJ for clock and trigger
M8041A
M8051A
opt. 0G3
opt. 0G3
Low frequency sinusoidal jitter
1.235 ns * Data rate [UI]
Jitter
amplitude
(UI)
100 Hz
247 ps * Data rate [UI]
10 kHz
5 MHz
Modulation
frequency
Data rate
Max UI at modulation
frequency 100 Hz to 10 kHz
Max UI at modulation
frequency 5 MHz
256.0 Mb/s to 506.25 Mb/s
31.2 to 62.5 UI
0.0632 to 0.125 UI
506.25 Mb/s to 1.0125 Gb/s
62.5 to 1.25 UI
0.125 to 0.25 UI
1.0125 Gb/s to 2.025 Gb/s
123 to 250 UI
0.25 to 0.5 UI
2.025 Gb/s to 4.05 Gb/s
250 to 500 UI
0.5 to 1 UI
4.05 Gb/s to 8.1 Gb/s
500 to 1000 UI
1 to 2 UI
8.1 Gb/s to 16.2 Gb/s
1000 to 2000 UI
2 to 4 UI
Figure 10. Low frequency sinusoidal jitter maximum depends on data rate and modulation frequency.
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Table 14. Specifications for high frequency periodic jitter, random jitter, spectrally distributed random jitter, bounded uncorrelated jitter, Clock/2
jitter (requires option 0G3 advanced jitter sources).
M8041A
M8051A
High frequency jitter
(generated by delay line)
Range
1 UI p-p for data rates > 1 Gb/s
note: this is max sum of RJ, HF-PJ1
and HF-PJ, spectral RJ, external delay
modulation and BUJ.
opt. 0G3
opt. 0G3
High frequency periodic jitter
(HF PJ1 and HF PJ2)
Range
See HF jitter above 1
opt. 0G3
opt. 0G3
Frequency
1 kHz to 500 MHz two tone possible.
Sweep.
Jitter amplitude accuracy
± 3 ps ± 10 % typical
Adjustable
For each channel independently
Range
0 to 72 mUI rms (1 UI p-p max.) 1
opt. 0G3
opt. 0G3
Jitter amplitude accuracy
± 300 fs ± 10 % typical
Filters
high-pass: 10 MHz,
low-pass: 100 MHz, 500 MHz
Adjustable
For each channel independently
Range
0 to 72 mUI rms (1 UI p-p), 1
opt. 0G3
opt. 0G3
Frequency
LF: 0.01 to 1.5 MHz, HF: 1.5 to 100 MHz
Jitter amplitude accuracy
± 200 fs ± 10 % typical
Adjustable
For each channel independently
Range
See HF jitter above1
opt. 0G3
opt. 0G3
PRBS polynomials
2n -1, n = 7,8,9,10,11,15,23,31
Filters
50/100/200 MHz low pass 3rd order
Jitter amplitude accuracy
± 5 ps ± 10% typical for settings
shown in table 15
Adjustable
For each channel independently
Range
± 20 ps or ± 0.1 UI typical (whatever
is less). Note: this means that first eye
can be up to 20 ps longer or shorter
than subsequent eye.
opt. 0G3
opt. 0G3
Jitter amplitude accuracy
± 3 ps typical
Adjustable
For each channel independently
Random jitter (RJ)
Spectrally distributed RJ according
to PCIe 2 (sRJ) 2
Bounded uncorrelated jitter (BUJ)
Clock/2 jitter
1. 1 UI is the maximum sum of RJ, HF-PJ1 and HF-PJ2, spectral RJ, external delay modulation and BUJ.
2. Spectrally distributed jitter is mutually exclusive with RJ and BUJ.
Table 15. BUJ accuracy applies for these BUJ settings.
BUJ calibration settings 1
Rate for PRBS generator
PRBS polynomial
Low pass filter
CEI 6G
1.25 Gb/s
PRBS 29-1
100 MHz
CEI 11G
2.5 Gb/s
PRBS 2 -1
200 MHz
Gaussian
2.5 Gb/s
PRBS 231-1
100 MHz
11
1. Other settings are not calibrated and do not necessarily generate the desired jitter historgrams for all data rates of the PRBS generator.
16
Table 16. Specifications for Spread Spectrum Clocking (SSC) (requires opt. 0G3: advanced jitter sources).
SSC (Spread Spectrum Clock)
Residual SSC (@ PCIe2)
Range
± 5000 ppm (± 0.5 %)
Frequency
30 kHz to 100 kHz
Modulation
Triangular and arbitrary modulation
SSC amplitude accuracy
± 0.025 % typical
Outputs
Can be turned on/off together for
CLK OUT, DATA OUT 1, DATA OUT 2,
TRG OUT
Range
0 to 100 ps
Frequency
30 to 33 kHz
Outputs
Can be turned on/off independently for
DATA OUT 1, DATA OUT 2
M8041A
M8051A
opt. 0G3
na
opt. 0G3
opt. 0G3
Table 17. Specifications for external jitter modulation (DATA MOD IN 1 and 2, CLK MOD IN).
M8041A allows individual jitter injection for data 1, data 2 and clock. M8051A for data 1 and data 2. The option 0G3 is not needed.
External jitter - data modulation
input 1 and 2
External jitter - clock modulation
input
Connectors
Description
Input for delay modulation for each
DATA OUT individually.
Range
Up to 1 UI 1, 0.8 Vpp max
Frequency
Up to 1 GHz
Description
Input for delay modulation for the
TRG OUT and CLK OUT. Affects both.
Range
Up to 1 UI , 0.8 Vpp max
Frequency
Up to 1 GHz
SMA, female
1. 1UI is the maximum sum of RJ, HF-PJ1 and HF-PJ2, spectral RJ, external delay modulation and BUJ.
17
M8041A
M8051A
x
x
x
na
Figure 11. J-BERT M8020A system view for 1 channel.
18
ISI channels
External ISI channels are available to emulate channel loss. Agilent offers dedicated compliant
ISI channels for DisplayPort, PCIe3 (base spec) and SATA. M8048A is offererd in addition.
For detailed specifications see M8048A data sheet.
M8041A-001 ISI Channels provides four short traces:
7.7”(196 mm), 9.4” (240 mm), 11.12 “(282 mm), 12.8”(324 mm)
M8041A.002 ISI Channels provides four long traces:
14.8” (366 mm), 16.1” (408 mm), 24.4” (620 mm), 34.4”(874 mm)
Level interference injection
Common mode and differential mode level interference can be generated internally to test common mode rejection of a receiver and vertical eye
closure tolerance. Simultaneous injection of CMI and DMI is possible.
Table 18. Specifications for sinusoidal level interference (CMI, DMI) (requires option 0G7).
Differential mode interference (DMI)
Amplitude
Common mode interference (CMI)
Max. 30% of output amplitude
2
1
Amplitude accuracy
±10 mV ±10% typ
Amplitude 2, 3
Up to 320 mV 1
Amplitude accuracy
±10 mV ±10% typ
Frequency ranges
LF: 10 MHz to 1 GHz, sinusoidal only
HF: 1 GHz to 6 GHz, sinusoidal only
Simultaneous injection of
CMI and DMI
Yes
M8041A
M8051A
opt 0G7
opt 0G7
opt 0G7
opt 0G7
1. The maximum output amplitude decreases when CMI or DMI is enabled. See table 2.
2. For each channel independently.
3. Up to 5 GHz.
Pattern, sequencer and interactive link training
Table 19. Specifications for pattern, sequencer and link training.
PRBS 1
2n-1, n= 7, 10, 11, 15, 23, 23p 3, 31
PRBS
2 , n = 7, 10, 11, 13, 15, 23
Mark density
Mark density: PRBS 1/8 to 7/8
Zero substitution
Yes
Export/Import
Patterns from N4900 series can be imported
Pattern library
Yes
User definable memory
4 Gbit/channel 2
2 Mbit/channel
Interactive link training
Link training state machine (LTSSM) for PCIe 2/3
Includes speed and de-emphasis negotiation.
Coding
8B/10B, 128B/130B, 128B/132B, binary, hex
Scrambler
PCIe, USB, SATA
Vector/sequence granularity
64/80/130/132 bit
Pattern capture
Yes 2
Pattern sequencer
3 counted loop levels, 1 infinite loop, # of blocks: 500
M8041A
M8051A
x
x
opt. 0S1
na
x
x
n
2
1. Note: polarity is inverted compared to ParBERT and J-BERT N4903A/B and N49xx models.
2. For availability: contact factory. Free software update (interactive link training requires opt. 0S1).
3. Modified compliance pattern for PCIe3.
19
Analyzer (error detector)
Each analyzer channel includes a clock recovery.
For the following functions a separate module option is required:
• Equalizer CTLE option (option 0A3 for M8041A and M8051A)
• SER/FER analysis (option 0S2 is offered for M8041A only, but applies for all analyzers channels in the same clock group): this option
provides handling of 8B/10B coded, 128B/130B coded and 128B/132B 2 coded patterns. 8B/10B coded patterns support automatic handling
of running disparity changes, scrambling/descrambling and up to 4 filler primitives consisting of up to 4 symbols each. No dead time while
filtering filler symbols. Supports changes of length of 128B/130B and 128B/132B 2 coded Skip Ordered Sets for PCIe und USB 3.1 2
Table 20. Specifications for analyzer / error detector (Option C08 or C16).
Data rate
256 Mb/s to 8.50 Gb/s (opt. C08),
256 Mb/s to 16.20 Gb/s (opt. C16)
Channels per module
1 or 2 (opt. 0A2)
Data format
NRZ, single ended and differential
Input sensitivity 1
50 mV typical @ normal sensitivity mode4
40 mV typical @ high sensitivity mode4
M8041A
M8051A
x
x
Input voltage window
-1.0 V to + 3.3 V
Maximum voltage window
1.0 Vpp single ended @ normal sensitivity mode
0.50 Vpp single ended @ high-sensitivity mode
Termination voltage
-1.0 V to + 3.3 V 3
Timing resolution
1 mUI
Input bandwidth
17.5 GHz typical
CTLE
Yes. Four presets are available:
PCIe 3.0 @ 8 Gb/s: -6.0 dB, - 9 dB, - 12 dB
USB 3.0 @ 5 Gb/s
opt. 0A3
opt. 0A3
Clock data recovery
Yes for each input channel.
See table 21 for more details.
x
x
Sampling point
Manual and automatic. Finds optimum voltage
threshold and delay of the sampling point.
Decision threshold range
-1.0 V to + 3.3 V in 1 mV steps. Must be within
± 0.5 V range from common mode voltage
Phase margin
TBD
BER
Accumulated
Symbol/frame error rate
8B/10B, 128B/130B, 128B/132B 2 coded
and retimed patterns
opt. 0S2
na
Filtering of filler symbols
Automatic removal of filler symbols.
See also description above.
opt. 0S2
na
Interface
Differential: 100 Ω, single ended: 50 Ω, DC coupled
x
x
Data input connectors
3.5 mm, female
1. Measured with PRBS 2 31-1 at 16 Gb/s, AC coupling mode, BER =0 for 10 3 bits, CTLE disabled.
2. For availability please contact factory.
3. Termination voltage must be within a window of DC common mode voltage ± 1.7 V.
4. Eye height measured at input of reference cable M8041A-801 with DCA-X module 86117A. Applies for single ended and differential input signals.
20
Table 21. Specifications for clock recovery.
Condition
CDR data rate range
1.0125 to 16.2 Gb/s
Selectable loop type
1st and 2nd order PLL
Tunable loop bandwidth
Adjustable from data rate / 10000 to data rate / TBD
(maximum is 20 MHz)
Loop bandwidth accuracy
TBD
Tunable peaking range
TBD
Transition density compensation
The user can set the expected transition density and the loop
compensates the loop bandwidth accordingly
Tracking range
TBD
M8041A
M8051A
x
x
Table 22. Measurement capabilities (Option C08 or C16).
BER
Accumulation and instant
BERT Scan with RJ, DJ separation
Yes, up to 16.2 Gb/s and PRBS 2 -1
Accumulated and instant BER
Yes
Jitter tolerance
Yes
Eye contour
Yes 1
Quick eye diagram
Yes 1
Output level and Q factor
Yes 1
Bit recovery mode
Yes 1
Counters
8B/10B: compared symbols, errored symbols, illegal symbols,
filler symbols, wrong disparity, frames, errored frames
128B/130B: blocks, errored blocks, illegal sync headers,
filler symbols, modified filler symbols
128B/132B 1: blocks, errored blocks, illegal sync headers,
filler symbols, modified filler symbols, corrected sync headers
M8041A
M8051A
x
x
opt. OS2
na
31
1. For availability: contact factory. Free software update.
21
User interface and remote control
The M8070A system software for the M8000 Series of BER Test Solutions is required to control M8041A, M8051A and M8061A.
Table 23. User interface and remote control interface.
System software
M8070A
Software licensing
Offline version does not require a license. For controlling the hardware you can choose
between a transportable, perpetual license (M8070A-0TP) and a network, perpetual license
(M8070A-0NP) . The network license is only recommended when using multiple M8020A
setups within one company. When ordering M8020A-BU1 the M8070A-0TP license will be
pre-installed on the embedded controller.
Controller requirements
Embedded PC: Choose M8020A-BU1 for a pre-installed embedded controller M9536A
including pre-installation of M8070A software and module licenses. Otherwise: M9536A
1-slot AXIe embedded controller, choose options for Windows 7 or 8, 16 GB RAM, USB
External PC: USB connection recommended between external PC and AXIe chassis.
Minimum of 8 GB RAM recommended. For PCIe connectivity please refer to list of tested
PCs for AXIe Technical Note, pub no. 5990-7632EN
Operating system
Microsoft Windows 7 (64 bit) SP1, Windows 8 (64 bit)
Controller connectivity with AXIe chassis
USB 2.0 (Mini-B) recommended,
PCIe 2.0/8x (only for highest data throughput and desktop PC)
Programming language
SCPI. Not compatible with N4900 series and ParBERT 81250A
Remote control interface
Desktop or Laptop PC: LAN
M9536A: LAN
Save/Recall
Yes
Export of measurement results
Jitter tolerance results as *.csv file
Software pre-requisites
Microsoft Win 7 SP1 or 8, Agilent IO library rev. 16.3
Software download
See www.agilent.com/find/m8020a for latest version
22
General characteristics and physical dimensions
Table 24. General characteristics for M8041A and M8051A modules.
M8041A
M8051A
Operating temperature
5 °C to 40 °C (-23 °F to + 104 °F)
Storage temperature
-40 ºC to +70 ºC (modules) (-65 °F to + 158 °F)
Operating humidity
15% to 95% relative humidity at 40ºC (non-condensing)
Storage humidity
24% to 90% relative humidity at 65ºC (non-condensing)
Power requirements
350 W
250 W
Physical dimensions
for modules
(W x H x D)
3- slot AXIe module:
351 x 92 x 315 mm
(13.8 x 3.6 x 12.4 inch)
2-slot AXIe module:
351 x 61 x 315 mm
(13.8 x 2.4 x 12.4 inch)
Physical dimensions
for M8020A-BU1/-BU2
(W x H x D)
Installed in 5-slot AXIe chassis:
463 x 194 x 446 mm
(18.2 x 7.6 x 17.6 inch)
Weight net
M8041A module: 6.6 kg (14.6 lb)
With M8020A-BU1: 24 kg (53 lb)
With M8020A-BU2: 19.9 kg (43.9 lb)
M8051A module: 5.0 kg (11.0 lb)
In bundle with M8041A and in a 5-slot
chassis: 24.9 kg (54.9 lb)
Weight shipping
With M8020A-BU1: 37 kg (82 lb)
With M8020A-BU2: 32.5 kg (71.7 lb)
N/A
Recommended recalibration period
1 year
Warranty period
3 years return to Agilent
Warm-up time
Cooling requirements
30 minutes
Slot airflow direction is from right to left. When operating the M8041A/51A choose a
location that provides at least 80 mm of clearance at rear, and at least 30 mm of clearance
at each side. See also start-up guide for M9502A chassis.
EMC
IEC 61326-1
Safety
IEC 61010-1
Quality management
ISO 9001, 14001
23
Supplementary specifications for M8061A multiplexer 2:1 when used
with M8041A for operation up to 32 Gb/s
Figure 12: For a 32 Gb/s BERT setup the M8061A multiplexer with de-emphasis option can be used with a two-channel M8041A BERT and the
N4877A clock data recovery with de-multiplexer.
The table below lists the supplementary specifications that apply when M8061A is used with M8041A. For all other specifications and features of
M8061A please refer to the M8061A data sheet.
Table 25. Supplementary specifications for M8061A multiplexer when used with M8041A.
Data rate
Specified range: 2.025 Gb/s to 28.4 Gb/s
Over programming up to 32.4 Gb/s
Channels
1 to 2
Intrinsic random jitter
180 fs rms typical @ 25.78 to 28.0 Gb/s with bandpass filter M8061A-802 at aux clock
input of M8061A;
200 fs rms typical @ 25.0 to 32.0 Gb/s with bandpass filter M8061A-803 at aux clock
input of M8061A;
350 fs rms typical (@ 28.4 Gb/s, clock pattern using M8041A as clock source,
without bandpass filter)
DMI, CMI
External DMI and CMI sources are needed, the combiners are built-in
De-emphasis
4 taps (M8061A opt 004) and extension to 8 taps (M8061A opt 008)
Electrical idle
Use M8061A input
Clock output
Data rate / 2
Error counting
Full-rate sampling. Needs N4877A for 1:2 de-multiplexing and clock recovery. Second
analyzer channel of M8041A required. No CTLE.
Measurements
For bit rates > 16.2 Gb/s measurements: jitter tolerance, accumulated BER (no BERT
Scan with RJ/DJ separation). Requires N4877A CDR and de-multiplexer 1:2 for 100% bit
sampling. Recovered clock is not required.
Software
Requires M8070A system software for M8000 series
Chassis/connectivity
For one 32G channel: M8061A module has to be in same chassis as M8041A module.
For two 32G channels: Two 5-slot chassis are required. The M8041A and M8051A in one
5-slot chassis, the two M8061As in a second 5–slot chassis.
(An external PC is required with just one USB connection to AXIe chassis.)
24
Specification assumptions
The specifications in this document describe the instruments warranted performance. Preliminary values are written in italic. Non-warranted
values are described as typical. All specifications are valid in the specified operating temperature range after the warm-up time and after autoadjustment. If not otherwise stated all outputs need to be terminated with 50 Ω to GND. All M8041A and M8051A specifications if not otherwise
stated are valid using the recommended cable pair M8041A-801 (2.92 mm, 0.85 m, matched pair).
Ordering instructions
Please refer to M8020A configuration guide for ordering details.
M8020A-BU2
16 Gb/s High-performance BERT, 1-2 channel
with external PC
M8020A-BU1
with embedded PC
16 Gb/s High-performance BERT, 3-4 channel
(external PC not shown)
32 Gb/s High-performance BERT, 1 channel
(external PC not shown) with N4877A CDR / Demux
Figure 13. Overview of possible J-BERT M8020A configurations.
25
Default accessories included with shipment:
M8041A module: eight 50 Ω terminations, commercial calibration report (“UK6”), certificate of calibration, ESD protection kit.
M8051A module: four 50 Ω terminations, clock synchronization cable (M8051A-801), commercial calibration report (“UK6”),
certificate of calibration
M8020A-BU1: M9505A AXIe chassis with embedded controller, USB cable, getting started guide, AXIe filler panel, power cord
M8020A-BU2: M9505A AXIe chassis, USB cable, getting started guide, AXIe filler panel, power cord
M8070A: CD-ROM with M8070A system software
Recommended accessories:
Matched cable pair, 2.92 mm (m) to 2.92 mm (m), 0.85 m M8041A-801
(recommended for each data output of M8041A/51A.
This 2.92 mm cable is compatible with 3.5 mm front panel
connectors of M8041A/51A.)
Bandpass filter 11.4 to 15.6 GHz, SMA M8061A-802
(for use with M8061A in clock path to minimize intrinsic RJ of M8061A
for data rates from 25.5 to 28.2 Gb/s)
Bandpass filter 11.1 to 17.5 GHz, SMA M8061A-803 (for use with M8061A in clock path to minimize intrinsic RJ of M8061A
for data rates from 25.0 to 32.0 Gb/s)
Cable kit for connecting M8061A with M8020A, 3x 3.5 mm, 0.6 m
M8061A-804
DC block, 26 GHz, 3.5 mmN9398C
ISI channels, four short tracesM8048A-001
ISI channels, four long tracesM8048A-002
Short matched cable pair, SMA (m) to SMA (m)
for cascading M8048A ISI channelsM8048A-801
Four SMA cables, unmatched15442A
Rack-mount kit for AXIe 5-slot chassis M9505A Y1226A
Test automation software with support of M8020A
Test automation software for PCIe receiver test N5990A-101
Test automation software for USB receiver test N5990A-102
Test automation software for SATA receiver test N5990A-103
PCIe link training suiteN5990A-301
Test automation software, Core
N5990A-010
Warranty, calibration and productivity services:
Extended 5 year warranty Return-to-Agilent R1280 (R-51B-001-5Z)
Calibration services (3 and 5 years)
R1282
Productivity assistanceR1380-M8000
Related Agilent literature
Data sheets and configuration guides:
M8048A ISI Channels Data Sheet5991-3548EN
M8061A Multiplexer with de-emphasis Data Sheet
5991-2506EN
J-BERT N4903B high-performance BERT Data Sheet
5990-3217EN
N4877A and N1075A CDR/Demux Data Sheet
5990-9949EN
M9505A AXIe Chassis 5-slot Data Sheet
5990-6584EN
M8020A Configuration Guide5991-4032EN
Application notes:
Master your MIPI M-PHY receiver test using J-BERT M8020A Application Brief
How to pass receiver test according PCI Express CEM specification Application Note
Accurate calibration of PCIe 3.0 receiver stress signals Application Note
How to test a MIPI M-PHY high-speed receiver Application Note
Master your next PCIe receiver test using J-BERT M8020A Application Note
Master your next USB 3.x designs with J-BERT M8020A Application Brief
26
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© Agilent Technologies, Inc. 2014
Published in USA, July 8, 2014
5991-3647EN