CY7C1355,7C

CY7C1355C
CY7C1357C
9-Mbit (256K x 36/512K x 18)
Flow-Through SRAM with NoBL™ Architecture
Functional Description[1]
Features
• No Bus Latency™ (NoBL™) architecture eliminates
dead cycles between write and read cycles
• Can support up to 133-MHz bus operations with zero
wait states
— Data is transferred on every clock
• Pin compatible and functionally equivalent to ZBT™
devices
• Internally self-timed output buffer control to eliminate
the need to use OE
• Registered inputs for flow-through operation
• Byte Write capability
• 3.3V/2.5V I/O power supply (VDDQ)
• Fast clock-to-output times
— 6.5 ns (for 133-MHz device)
• Clock Enable (CEN) pin to enable clock and suspend
operation
• Synchronous self-timed writes
• Asynchronous Output Enable
• Available in JEDEC-standard and lead-free 100-Pin
TQFP, lead-free and non lead-free 119-Ball BGA
package and 165-Ball FBGA package
The CY7C1355C/CY7C1357C is a 3.3V, 256K x 36/512K x 18
Synchronous Flow-through Burst SRAM designed specifically
to support unlimited true back-to-back Read/Write operations
without
the
insertion
of
wait
states.
The
CY7C1355C/CY7C1357C is equipped with the advanced No
Bus Latency (NoBL) logic required to enable consecutive
Read/Write operations with data being transferred on every
clock cycle. This feature dramatically improves the throughput
of data through the SRAM, especially in systems that require
frequent Write-Read transitions.
All synchronous inputs pass through input registers controlled
by the rising edge of the clock. The clock input is qualified by
the Clock Enable (CEN) signal, which when deasserted
suspends operation and extends the previous clock cycle.
Maximum access delay from the clock rise is 6.5 ns (133-MHz
device).
Write operations are controlled by the two or four Byte Write
Select (BWX) and a Write Enable (WE) input. All writes are
conducted with on-chip synchronous self-timed write circuitry.
Three synchronous Chip Enables (CE1, CE2, CE3) and an
asynchronous Output Enable (OE) provide for easy bank
selection and output tri-state control. In order to avoid bus
contention, the output drivers are synchronously tri-stated
during the data portion of a write sequence.
• Three chip enables for simple depth expansion.
• Automatic Power-down feature available using ZZ
mode or CE deselect
• IEEE 1149.1 JTAG-Compatible Boundary Scan
• Burst Capability—linear or interleaved burst order
• Low standby power
Selection Guide
133 MHz
100 MHz
Unit
Maximum Access Time
6.5
7.5
ns
Maximum Operating Current
250
180
mA
Maximum CMOS Standby Current
40
40
mA
Note:
1. For best-practices recommendations, please refer to the Cypress application note System Design Guidelines on www.cypress.com.
Cypress Semiconductor Corporation
Document #: 38-05539 Rev. *E
•
198 Champion Court
•
San Jose, CA 95134-1709
•
408-943-2600
Revised September 14, 2006
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CY7C1355C
CY7C1357C
1
Logic Block Diagram – CY7C1355C (256K x 36)
ADDRESS
REGISTER
A0, A1, A
A1
D1
A0
D0
MODE
CLK
CEN
C
CE
ADV/LD
C
BURST
LOGIC
Q1 A1'
A0'
Q0
WRITE ADDRESS
REGISTER
ADV/LD
BWA
WRITE
DRIVERS
WRITE REGISTRY
AND DATA COHERENCY
CONTROL LOGIC
BWB
BWC
MEMORY
ARRAY
S
E
N
S
E
A
M
P
S
BWD
WE
D
A
T
A
S
T
E
E
R
I
N
G
O
U
T
P
U
T
B
U
F
F
E
R
S
DQs
DQPA
DQPB
DQPC
DQPD
E
INPUT
E
REGISTER
OE
CE1
CE2
CE3
READ LOGIC
SLEEP
CONTROL
ZZ
2
Logic Block Diagram – CY7C1357C (512K x 18)
ADDRESS
REGISTER
A0, A1, A
A1
D1
A0
D0
MODE
CLK
CEN
C
CE
ADV/LD
C
BURST
LOGIC
Q1 A1'
A0'
Q0
WRITE ADDRESS
REGISTER
ADV/LD
BWA
BWB
WRITE REGISTRY
AND DATA COHERENCY
CONTROL LOGIC
WRITE
DRIVERS
MEMORY
ARRAY
S
E
N
S
E
A
M
P
S
WE
OE
CE1
CE2
CE3
ZZ
Document #: 38-05539 Rev. *E
D
A
T
A
S
T
E
E
R
I
N
G
O
U
T
P
U
T
B
U
F
F
E
R
S
DQs
DQPA
DQPB
E
INPUT E
REGISTER
READ LOGIC
SLEEP
CONTROL
Page 2 of 28
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CY7C1355C
CY7C1357C
Pin Configurations
Document #: 38-05539 Rev. *E
A
43
44
45
46
47
48
49
50
NC/72M
NC/36M
A
A
A
A
A
A
A
41
VDD
42
40
37
A0
VSS
36
A1
39
35
A
NC/144M
34
A
38
33
A
NC/288M
32
A
81
A
82
A
83
84
NC/18M
ADV/LD
85
OE
86
CEN
VSS
90
WE
VDD
91
88
CE3
92
CLK
BWA
93
89
BWC
BWB
BWD
96
94
CE2
97
95
CE1
A
98
87
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
CY7C1355C
31
BYTE D
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
MODE
BYTE C
DQPC
DQC
DQC
VDDQ
VSS
DQC
DQC
DQC
DQC
VSS
VDDQ
DQC
DQC
Vss/DNU
VDD
NC
VSS
DQD
DQD
VDDQ
VSS
DQD
DQD
DQD
DQD
VSS
VDDQ
DQD
DQD
DQPD
99
100
A
100-Pin TQFP Pinout
DQPB
DQB
DQB
VDDQ
VSS
DQB
DQB
DQB
DQB
VSS
VDDQ
DQB
DQB
VSS
NC
VDD
ZZ
DQA
DQA
VDDQ
VSS
DQA
DQA
DQA
DQA
VSS
VDDQ
DQA
DQA
DQPA
BYTE B
BYTE A
Page 3 of 28
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CY7C1355C
CY7C1357C
Pin Configurations (continued)
Document #: 38-05539 Rev. *E
A
42
43
44
45
46
47
48
49
50
NC/72M
NC/36M
A
A
A
A
A
A
A
41
VDD
A0
40
37
A1
VSS
36
A
39
35
A
NC/144M
34
38
33
A
NC/288M
32
A
81
A
82
A
83
NC/18M
84
ADV/LD
85
OE
86
CEN
90
WE
VSS
91
88
VDD
92
CLK
CE3
93
89
BWB
BWA
94
NC
95
NC
97
96
CE1
CE2
A
98
87
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
CY7C1357C
31
BYTE B
VDDQ
VSS
NC
NC
DQB
DQB
VSS
VDDQ
DQB
DQB
Vss/DNU
VDD
NC
VSS
DQB
DQB
VDDQ
VSS
DQB
DQB
DQPB
NC
VSS
VDDQ
NC
NC
NC
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
MODE
NC
NC
NC
99
100
A
100-Pin TQFP Pinout
A
NC
NC
VDDQ
VSS
NC
DQPA
DQA
DQA
VSS
VDDQ
DQA
DQA
VSS
NC
VDD
ZZ
BYTE A
DQA
DQA
VDDQ
VSS
DQA
DQA
NC
NC
VSS
VDDQ
NC
NC
NC
Page 4 of 28
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CY7C1355C
CY7C1357C
Pin Configurations (continued)
119-Ball BGA Pinout (3 Chip Enables with JTAG)
CY7C1355C (256K x 36)
1
A
VDDQ
2
A
3
A
4
NC/18M
5
A
6
A
7
VDDQ
B
C
NC/576M
NC/1G
CE2
A
A
A
ADV/LD
VDD
A
A
CE3
A
NC
NC
D
E
DQC
DQC
DQPC
DQC
VSS
VSS
NC
VSS
VSS
DQPB
DQB
DQB
DQB
F
VDDQ
DQC
VSS
VSS
DQB
VDDQ
G
H
J
K
DQC
DQC
VDDQ
DQD
DQC
DQC
VDD
DQD
BWC
VSS
NC
VSS
BWB
VSS
NC
VSS
DQB
DQB
VDD
DQA
DQB
DQB
VDDQ
DQA
L
DQD
DQD
DQA
VDDQ
DQD
BWA
VSS
DQA
M
BWD
VSS
DQA
VDDQ
N
DQD
DQD
VSS
VSS
DQA
DQA
CE1
OE
A
WE
VDD
CLK
NC
CEN
A1
P
DQD
DQPD
VSS
A0
VSS
DQPA
DQA
R
NC/144M
A
MODE
VDD
NC
A
NC/288M
T
U
NC
VDDQ
NC/72M
TMS
A
TDI
A
TCK
A
TDO
NC/36M
NC
ZZ
VDDQ
6
7
CY7C1357C (512K x 18)
1
2
3
4
5
A
VDDQ
A
A
NC/18M
A
A
VDDQ
B
NC/576M
CE2
A
A
NC/1G
A
A
A
CE3
A
NC
C
ADV/LD
VDD
D
DQB
NC
VSS
NC
VSS
DQPA
NC
E
NC
DQB
VSS
CE1
VSS
NC
DQA
F
VDDQ
NC
VSS
VSS
DQA
VDDQ
G
H
J
NC
DQB
VDDQ
DQB
NC
VDD
BWB
VSS
NC
OE
A
WE
VDD
VSS
VSS
NC
NC
DQA
VDD
DQA
NC
VDDQ
K
NC
DQB
VSS
CLK
VSS
NC
DQA
L
M
DQB
VDDQ
NC
DQB
VSS
VSS
NC
DQA
NC
NC
VDDQ
N
DQB
NC
VSS
CEN
A1
BWA
VSS
VSS
DQA
NC
P
NC
DQPB
VSS
A0
VSS
NC
DQA
R
T
U
NC/144M
NC/72M
VDDQ
A
A
TMS
MODE
A
TDI
VDD
NC/36M
TCK
NC
A
TDO
A
A
NC
NC/288M
ZZ
VDDQ
Document #: 38-05539 Rev. *E
NC
Page 5 of 28
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CY7C1355C
CY7C1357C
Pin Configurations (continued)
165-Ball FBGA Pinout (3 Chip enable with JTAG)
CY7C1355C (256K x 36)
2
3
4
5
6
7
8
9
10
11
A
B
C
D
E
F
G
H
J
K
L
M
N
P
NC/576M
1
A
CE1
BWC
BWB
CE3
CEN
ADV/LD
A
A
NC
NC/1G
A
CE2
BWD
BWA
CLK
WE
OE
NC/18M
A
NC
DQPC
DQC
NC
DQC
VDDQ
VSS
VDD
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VDD
VDDQ
VDDQ
VDDQ
NC
DQB
DQPB
DQB
DQC
DQC
VDDQ
VDD
VSS
VSS
VSS
VDD
VDDQ
DQB
DQB
DQC
DQC
NC
DQD
DQC
VDDQ
VDD
VSS
VSS
VSS
VDD
DQB
VDDQ
NC
VDDQ
VDD
VDD
VDD
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VDD
VDD
VDD
VDDQ
VDDQ
NC
VDDQ
DQB
DQC
NC
DQD
DQB
NC
DQA
DQB
ZZ
DQA
DQD
DQD
VDDQ
VDD
VSS
VSS
VSS
VDD
VDDQ
DQA
DQA
DQD
DQD
VDDQ
VDD
VSS
VSS
VSS
VDD
VDDQ
DQA
DQA
DQD
DQPD
DQD
NC
VDDQ
VDDQ
VDD
VSS
VSS
NC
VSS
A
A
R
MODE
NC/36M
A
A
1
2
3
4
5
A
B
C
D
E
F
G
H
J
K
L
M
N
P
NC/576M
A
CE1
BWB
R
MODE
NC/144M NC/72M
VSS
NC
VDD
VSS
VDDQ
VDDQ
DQA
NC
DQA
DQPA
TDI
NC
A1
TDO
A
A
A
NC/288M
TMS
A0
TCK
A
A
A
A
6
7
8
9
10
11
NC
CE3
CEN
ADV/LD
A
A
A
CY7C1357C (512K x 18)
NC/1G
A
CE2
NC
BWA
CLK
WE
OE
NC/18M
A
NC
NC
NC
NC
DQB
VDDQ
VDDQ
VSS
VDD
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VDD
VDDQ
VDDQ
NC
NC
DQPA
DQA
NC
DQB
VDDQ
VDD
VSS
VSS
VSS
VDD
VDDQ
NC
DQA
NC
DQB
VDDQ
VDD
VSS
VSS
VSS
VDD
VDDQ
NC
DQA
NC
NC
DQB
DQB
NC
NC
VDDQ
NC
VDDQ
VDD
VDD
VDD
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VDD
VDD
VDD
VDDQ
NC
VDDQ
NC
NC
DQA
DQA
ZZ
NC
DQB
NC
VDDQ
VDD
VSS
VSS
VSS
VDD
VDDQ
DQA
NC
DQB
NC
VDDQ
VDD
VSS
VSS
VSS
VDD
VDDQ
DQA
NC
DQB
DQPB
NC
NC
VDDQ
VDDQ
VDD
VSS
VSS
NC
VSS
VDD
VSS
VDDQ
VDDQ
DQA
NC
NC
NC
A
A
TDI
NC
A1
VSS
NC
TDO
A
A
A
NC/288M
A
A
TMS
A0
TCK
A
A
A
A
NC/144M NC/72M
NC/36M
Document #: 38-05539 Rev. *E
Page 6 of 28
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CY7C1355C
CY7C1357C
Pin Definitions
Name
I/O
Description
A0, A1, A
InputSynchronous
Address Inputs used to select one of the address locations. Sampled at the rising edge
of the CLK. A[1:0] are fed to the two-bit burst counter.
BWA, BWB
BWC, BWD
InputSynchronous
Byte Write Inputs, active LOW. Qualified with WE to conduct Writes to the SRAM. Sampled
on the rising edge of CLK.
WE
InputSynchronous
Write Enable Input, active LOW. Sampled on the rising edge of CLK if CEN is active LOW.
This signal must be asserted LOW to initiate a write sequence.
ADV/LD
InputSynchronous
Advance/Load Input. Used to advance the on-chip address counter or load a new address.
When HIGH (and CEN is asserted LOW) the internal burst counter is advanced. When LOW,
a new address can be loaded into the device for an access. After being deselected, ADV/LD
should be driven LOW in order to load a new address.
CLK
InputClock
Clock Input. Used to capture all synchronous inputs to the device. CLK is qualified with
CEN. CLK is only recognized if CEN is active LOW.
CE1
InputSynchronous
Chip Enable 1 Input, active LOW. Sampled on the rising edge of CLK. Used in conjunction
with CE2, and CE3 to select/deselect the device.
CE2
InputSynchronous
Chip Enable 2 Input, active HIGH. Sampled on the rising edge of CLK. Used in conjunction
with CE1 and CE3 to select/deselect the device.
CE3
InputSynchronous
Chip Enable 3 Input, active LOW. Sampled on the rising edge of CLK. Used in conjunction
with CE1 and CE2 to select/deselect the device.
OE
InputOutput Enable, asynchronous input, active LOW. Combined with the synchronous logic
Asynchronous block inside the device to control the direction of the I/O pins. When LOW, the I/O pins are
allowed to behave as outputs. When deasserted HIGH, I/O pins are tri-stated, and act as
input data pins. OE is masked during the data portion of a write sequence, during the first
clock when emerging from a deselected state, when the device has been deselected.
CEN
InputSynchronous
ZZ
InputZZ “Sleep” Input. This active HIGH input places the device in a non-time critical “sleep”
Asynchronous condition with data integrity preserved. For normal operation, this pin has to be LOW or left
floating. ZZ pin has an internal pull-down.
DQs
I/OSynchronous
Bidirectional Data I/O lines. As inputs, they feed into an on-chip data register that is
triggered by the rising edge of CLK. As outputs, they deliver the data contained in the
memory location specified by the addresses presented during the previous clock rise of the
Read cycle. The direction of the pins is controlled by OE. When OE is asserted LOW, the
pins behave as outputs. When HIGH, DQs and DQPX are placed in a tri-state condition.The
outputs are automatically tri-stated during the data portion of a Write sequence, during the
first clock when emerging from a deselected state, and when the device is deselected,
regardless of the state of OE.
DQPX
I/OSynchronous
Bidirectional Data Parity I/O Lines. Functionally, these signals are identical to DQs. During
Write sequences, DQPX is controlled by BWX correspondingly.
Clock Enable Input, active LOW. When asserted LOW the Clock signal is recognized by
the SRAM. When deasserted HIGH the Clock signal is masked. Since deasserting CEN
does not deselect the device, CEN can be used to extend the previous cycle when required.
MODE
Input Strap Pin Mode Input. Selects the burst order of the device. When tied to Gnd selects linear burst
sequence. When tied to VDD or left floating selects interleaved burst sequence.
VDD
Power Supply
VDDQ
VSS
I/O Power
Supply
Ground
Power supply inputs to the core of the device.
Power supply for the I/O circuitry.
Ground for the device.
TDO
JTAG serial output Serial data-out to the JTAG circuit. Delivers data on the negative edge of TCK. If the JTAG
Synchronous feature is not being utilized, this pin should be left unconnected. This pin is not available on
TQFP packages.
TDI
JTAG serial input Serial data-In to the JTAG circuit. Sampled on the rising edge of TCK. If the JTAG feature
Synchronous is not being utilized, this pin can be left floating or connected to VDD through a pull up resistor.
This pin is not available on TQFP packages.
Document #: 38-05539 Rev. *E
Page 7 of 28
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CY7C1355C
CY7C1357C
Pin Definitions (continued)
Name
TMS
I/O
Description
JTAG serial input Serial data-In to the JTAG circuit. Sampled on the rising edge of TCK. If the JTAG feature
Synchronous is not being utilized, this pin can be disconnected or connected to VDD. This pin is not
available on TQFP packages.
TCK
JTAG
Clock
Clock input to the JTAG circuitry. If the JTAG feature is not being utilized, this pin must
be connected to VSS. This pin is not available on TQFP packages.
NC
–
No Connects. Not internally connected to the die. 18 Mbit, 36 Mbit, 72 Mbit, 144 Mbit, 288
Mbit, 576 Mbit and 1G are address expansion pins and are not internally connected to the
die.
VSS/DNU
Ground/DNU
This pin can be connected to Ground or should be left floating.
Burst Read Accesses
Functional Overview
The CY7C1355C/CY7C1357C is a synchronous flow-through
burst SRAM designed specifically to eliminate wait states
during Write-Read transitions. All synchronous inputs pass
through input registers controlled by the rising edge of the
clock. The clock signal is qualified with the Clock Enable input
signal (CEN). If CEN is HIGH, the clock signal is not recognized and all internal states are maintained. All synchronous
operations are qualified with CEN. Maximum access delay
from the clock rise (tCDV) is 6.5 ns (133-MHz device).
Accesses can be initiated by asserting all three Chip Enables
(CE1, CE2, CE3) active at the rising edge of the clock. If Clock
Enable (CEN) is active LOW and ADV/LD is asserted LOW,
the address presented to the device will be latched. The
access can either be a Read or Write operation, depending on
the status of the Write Enable (WE). BWX can be used to
conduct Byte Write operations.
Write operations are qualified by the Write Enable (WE). All
writes are simplified with on-chip synchronous self-timed Write
circuitry.
Three synchronous Chip Enables (CE1, CE2, CE3) and an
asynchronous Output Enable (OE) simplify depth expansion.
All operations (Reads, Writes, and Deselects) are pipelined.
ADV/LD should be driven LOW once the device has been
deselected in order to load a new address for the next
operation.
Single Read Accesses
A read access is initiated when the following conditions are
satisfied at clock rise: (1) CEN is asserted LOW, (2) CE1, CE2,
and CE3 are ALL asserted active, (3) the Write Enable input
signal WE is deasserted HIGH, and 4) ADV/LD is asserted
LOW. The address presented to the address inputs is latched
into the address register and presented to the memory array
and control logic. The control logic determines that a read
access is in progress and allows the requested data to
propagate to the output buffers. The data is available within 7.5
ns (133-MHz device) provided OE is active LOW. After the first
clock of the read access, the output buffers are controlled by
OE and the internal control logic. OE must be driven LOW in
order for the device to drive out the requested data. On the
subsequent clock, another operation (Read/Write/Deselect)
can be initiated. When the SRAM is deselected at clock rise
by one of the chip enable signals, its output will be tri-stated
immediately.
Document #: 38-05539 Rev. *E
The CY7C1355C/CY7C1357C has an on-chip burst counter
that allows the user the ability to supply a single address and
conduct up to four Reads without reasserting the address
inputs. ADV/LD must be driven LOW in order to load a new
address into the SRAM, as described in the Single Read
Access section above. The sequence of the burst counter is
determined by the MODE input signal. A LOW input on MODE
selects a linear burst mode, a HIGH selects an interleaved
burst sequence. Both burst counters use A0 and A1 in the
burst sequence, and will wrap around when incremented sufficiently. A HIGH input on ADV/LD will increment the internal
burst counter regardless of the state of chip enable inputs or
WE. WE is latched at the beginning of a burst cycle. Therefore,
the type of access (Read or Write) is maintained throughout
the burst sequence.
Single Write Accesses
Write access are initiated when the following conditions are
satisfied at clock rise: (1) CEN is asserted LOW, (2) CE1, CE2,
and CE3 are ALL asserted active, and (3) the Write signal WE
is asserted LOW. The address presented to the address bus
is loaded into the address register. The write signals are
latched into the Control Logic block. The data lines are
automatically tri-stated regardless of the state of the OE input
signal. This allows the external logic to present the data on
DQs and DQPX.
On the next clock rise the data presented to DQs and DQPX
(or a subset for byte write operations, see Truth Table for
details) inputs is latched into the device and the write is
complete. Additional accesses (Read/Write/Deselect) can be
initiated on this cycle.
The data written during the Write operation is controlled by
BWX signals. The CY7C1355C/CY7C1357C provides byte
write capability that is described in the Truth Table. Asserting
the Write Enable input (WE) with the selected Byte Write
Select input will selectively write to only the desired bytes.
Bytes not selected during a byte write operation will remain
unaltered. A synchronous self-timed Write mechanism has
been provided to simplify the Write operations. Byte Write
capability has been included in order to greatly simplify
Read/Modify/Write sequences, which can be reduced to
simple Byte Write operations.
Because the CY7C1355C/CY7C1357C is a common I/O
device, data should not be driven into the device while the
outputs are active. The Output Enable (OE) can be deasserted
HIGH before presenting data to the DQs and DQPX inputs.
Doing so will tri-state the output drivers. As a safety
Page 8 of 28
[+] Feedback
CY7C1355C
CY7C1357C
Interleaved Burst Address Table
(MODE = Floating or VDD)
precaution, DQs and DQPX are automatically tri-stated during
the data portion of a write cycle, regardless of the state of OE.
Burst Write Accesses
The CY7C1355C/CY7C1357C has an on-chip burst counter
that allows the user the ability to supply a single address and
conduct up to four Write operations without reasserting the
address inputs. ADV/LD must be driven LOW in order to load
the initial address, as described in the Single Write Access
section above. When ADV/LD is driven HIGH on the subsequent clock rise, the Chip Enables (CE1, CE2, and CE3) and
WE inputs are ignored and the burst counter is incremented.
The correct BWX inputs must be driven in each cycle of the
burst write, in order to write the correct bytes of data.
First
Address
A1: A0
Second
Address
A1: A0
Third
Address
A1: A0
Fourth
Address
A1: A0
00
01
10
11
01
00
11
10
10
11
00
01
11
10
01
00
Linear Burst Address Table (MODE = GND)
Sleep Mode
First
Address
A1: A0
Second
Address
A1: A0
Third
Address
A1: A0
00
01
10
11
01
10
11
00
10
11
00
01
11
00
01
10
The ZZ input pin is an asynchronous input. Asserting ZZ
places the SRAM in a power conservation “sleep” mode. Two
clock cycles are required to enter into or exit from this “sleep”
mode. While in this mode, data integrity is guaranteed.
Accesses pending when entering the “sleep” mode are not
considered valid nor is the completion of the operation
guaranteed. The device must be deselected prior to entering
the “sleep” mode. CE1, CE2, and CE3, must remain inactive
for the duration of tZZREC after the ZZ input returns LOW.
Fourth
Address
A1: A0
. .
ZZ Mode Electrical Characteristics
Parameter
Description
IDDZZ
Sleep mode standby current
Test Conditions
Min.
ZZ > VDD – 0.2V
tZZS
Device operation to ZZ
ZZ > VDD – 0.2V
tZZREC
ZZ recovery time
ZZ < 0.2V
tZZI
ZZ active to sleep current
This parameter is sampled
tRZZI
ZZ Inactive to exit sleep current
This parameter is sampled
Max.
Unit
50
mA
2tCYC
ns
2tCYC
ns
2tCYC
0
ns
ns
Truth Table[2, 3, 4, 5, 6, 7, 8]
Operation
Deselect Cycle
Deselect Cycle
Address
Used CE1 CE2 CE3 ZZ
None
H
X
X
L
None
X
X
H
L
ADV/LD WE BWX OE CEN CLK
DQ
L
X
X
X
L
L->H
Tri-State
L
X
X
X
L
L->H
Tri-State
Deselect Cycle
None
X
L
X
L
L
X
X
X
L
L->H
Tri-State
Continue Deselect Cycle
None
X
X
X
L
H
X
X
X
L
L->H
Tri-State
External
L
H
L
L
L
H
X
L
L
L->H Data Out (Q)
Next
X
X
X
L
H
X
X
L
L
L->H Data Out (Q)
External
L
H
L
L
L
H
X
H
L
L->H
Tri-State
Next
X
X
X
L
H
X
X
H
L
L->H
Tri-State
External
L
H
L
L
L
L
L
X
L
L->H
Data In (D)
Next
X
X
X
L
H
X
L
X
L
L->H
Data In (D)
READ Cycle (Begin Burst)
READ Cycle (Continue Burst)
NOP/DUMMY READ (Begin Burst)
DUMMY READ (Continue Burst)
WRITE Cycle (Begin Burst)
WRITE Cycle (Continue Burst)
Notes:
2. X = “Don't Care.” H = Logic HIGH, L = Logic LOW. BWx = L signifies at least one Byte Write Select is active, BWx = Valid signifies that the desired Byte Write
Selects are asserted, see Truth Table for details.
3. Write is defined by BWX, and WE. See Truth Table for Read/Write.
4. When a Write cycle is detected, all I/Os are tri-stated, even during Byte Writes.
5. The DQs and DQPX pins are controlled by the current cycle and the OE signal. OE is asynchronous and is not sampled with the clock.
6. CEN = H, inserts wait states.
7. Device will power-up deselected and the I/Os in a tri-state condition, regardless of OE.
8. OE is asynchronous and is not sampled with the clock rise. It is masked internally during Write cycles. During a Read cycle DQs and DQPX = Tri-state when OE
is inactive or when the device is deselected, and DQs and DQPX = data when OE is active.
Document #: 38-05539 Rev. *E
Page 9 of 28
[+] Feedback
CY7C1355C
CY7C1357C
Truth Table[2, 3, 4, 5, 6, 7, 8]
Operation
Address
Used CE1 CE2 CE3 ZZ
ADV/LD WE BWX OE CEN CLK
DQ
NOP/WRITE ABORT (Begin Burst)
None
L
H
L
L
L
L
H
X
L
L->H
Tri-State
WRITE ABORT (Continue Burst)
Next
X
X
X
L
H
X
H
X
L
L->H
Tri-State
Current
X
X
X
L
X
X
X
X
H
L->H
–
None
X
X
X
H
X
X
X
X
X
X
Tri-State
IGNORE CLOCK EDGE (Stall)
SLEEP MODE
Partial Truth Table for Read/Write[2, 3, 9]
Function (CY7C1355C)
WE
H
BWA
X
BWB
X
BWC
X
BWD
X
Write No bytes written
L
H
H
H
H
Write Byte A – (DQA and DQPA)
Write Byte B – (DQB and DQPB)
L
L
H
H
H
L
H
L
H
H
Write Byte C – (DQC and DQPC)
L
H
H
L
H
Write Byte D – (DQD and DQPD)
L
H
H
H
L
Write All Bytes
L
L
L
L
L
Read
Truth Table for Read/Write[2, 3,9]
Function (CY7C1357C)
WE
H
BWA
X
BWB
X
Write - No bytes written
L
H
H
Write Byte A – (DQA and DQPA)
Write Byte B – (DQB and DQPB)
L
H
H
L
H
H
Write All Bytes
L
L
L
Read
Note:
9. Table only lists a partial listing of the byte write combinations. Any combination of BWX is valid. Appropriate write will be done based on which byte write is active.
Document #: 38-05539 Rev. *E
Page 10 of 28
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CY7C1355C
CY7C1357C
IEEE 1149.1 Serial Boundary Scan (JTAG)
Test MODE SELECT (TMS)
The CY7C1355C/CY7C1357C incorporates a serial boundary
scan test access port (TAP) in the BGA package only. The
TQFP package does not offer this functionality. This part
operates in accordance with IEEE Standard 1149.1-1900, but
doesn’t have the set of functions required for full 1149.1
compliance. These functions from the IEEE specification are
excluded because their inclusion places an added delay in the
critical speed path of the SRAM. Note the TAP controller
functions in a manner that does not conflict with the operation
of other devices using 1149.1 fully compliant TAPs. The TAP
operates using JEDEC-standard 3.3V or 2.5V I/O logic levels.
The CY7C1355C/CY7C1357C contains a TAP controller,
instruction register, boundary scan register, bypass register,
and ID register.
The TMS input is used to give commands to the TAP controller
and is sampled on the rising edge of TCK. It is allowable to
leave this ball unconnected if the TAP is not used. The ball is
pulled up internally, resulting in a logic HIGH level.
Test Data-In (TDI)
The TDI ball is used to serially input information into the
registers and can be connected to the input of any of the
registers. The register between TDI and TDO is chosen by the
instruction that is loaded into the TAP instruction register. TDI
is internally pulled up and can be unconnected if the TAP is
unused in an application. TDI is connected to the most significant bit (MSB) of any register. (See Tap Controller Block
Diagram.)
Test Data-Out (TDO)
Disabling the JTAG Feature
It is possible to operate the SRAM without using the JTAG
feature. To disable the TAP controller, TCK must be tied
LOW(VSS) to prevent clocking of the device. TDI and TMS are
internally pulled up and may be unconnected. They may alternately be connected to VDD through a pull-up resistor. TDO
should be left unconnected. Upon power-up, the device will
come up in a reset state which will not interfere with the
operation of the device.
The TDO output ball is used to serially clock data-out from the
registers. The output is active depending upon the current
state of the TAP state machine. The output changes on the
falling edge of TCK. TDO is connected to the least significant
bit (LSB) of any register. (See Tap Controller State Diagram.)
TAP Controller Block Diagram
0
Bypass Register
TAP Controller State Diagram
2 1 0
1
TEST-LOGIC
RESET
TDI
0
0
RUN-TEST/
IDLE
1
SELECT
DR-SCAN
1
SELECT
IR-SCAN
0
1
1
CAPTURE-DR
0
Selection
Circuitry
TDO
Identification Register
x . . . . . 2 1 0
CAPTURE-IR
Boundary Scan Register
SHIFT-IR
1
0
1
EXIT1-DR
1
EXIT1-IR
0
1
TCK
TMS
TAP CONTROLLER
0
PAUSE-DR
0
PAUSE-IR
1
0
Performing a TAP Reset
1
EXIT2-DR
0
EXIT2-IR
1
1
UPDATE-DR
1
1
0
SHIFT-DR
Instruction Register
31 30 29 . . . 2 1 0
0
0
0
Selection
Circuitry
0
UPDATE-IR
1
0
A RESET is performed by forcing TMS HIGH (VDD) for five
rising edges of TCK. This RESET does not affect the operation
of the SRAM and may be performed while the SRAM is
operating.
At power-up, the TAP is reset internally to ensure that TDO
comes up in a High-Z state.
TAP Registers
The 0/1 next to each state represents the value of TMS at the
rising edge of the TCK.
Test Access Port (TAP)
Test Clock (TCK)
The test clock is used only with the TAP controller. All inputs
are captured on the rising edge of TCK. All outputs are driven
from the falling edge of TCK.
Document #: 38-05539 Rev. *E
Registers are connected between the TDI and TDO balls and
allow data to be scanned into and out of the SRAM test
circuitry. Only one register can be selected at a time through
the instruction register. Data is serially loaded into the TDI ball
on the rising edge of TCK. Data is output on the TDO ball on
the falling edge of TCK.
Instruction Register
Three-bit instructions can be serially loaded into the instruction
register. This register is loaded when it is placed between the
TDI and TDO balls as shown in the Tap Controller Block
Page 11 of 28
[+] Feedback
CY7C1355C
CY7C1357C
Diagram. Upon power-up, the instruction register is loaded
with the IDCODE instruction. It is also loaded with the IDCODE
instruction if the controller is placed in a reset state as
described in the previous section.
When the TAP controller is in the Capture-IR state, the two
least significant bits are loaded with a binary “01” pattern to
allow for fault isolation of the board-level serial test data path.
Bypass Register
To save time when serially shifting data through registers, it is
sometimes advantageous to skip certain chips. The bypass
register is a single-bit register that can be placed between the
TDI and TDO balls. This allows data to be shifted through the
SRAM with minimal delay. The bypass register is set LOW
(VSS) when the BYPASS instruction is executed.
Boundary Scan Register
The boundary scan register is connected to all the input and
bidirectional balls on the SRAM.
The boundary scan register is loaded with the contents of the
RAM I/O ring when the TAP controller is in the Capture-DR
state and is then placed between the TDI and TDO balls when
the controller is moved to the Shift-DR state. The EXTEST,
SAMPLE/PRELOAD and SAMPLE Z instructions can be used
to capture the contents of the I/O ring.
The Boundary Scan Order tables show the order in which the
bits are connected. Each bit corresponds to one of the bumps
on the SRAM package. The MSB of the register is connected
to TDI, and the LSB is connected to TDO.
Identification (ID) Register
The ID register is loaded with a vendor-specific, 32-bit code
during the Capture-DR state when the IDCODE command is
loaded in the instruction register. The IDCODE is hardwired
into the SRAM and can be shifted out when the TAP controller
is in the Shift-DR state. The ID register has a vendor code and
other information described in the Identification Register
Definitions table.
TAP Instruction Set
Overview
Eight different instructions are possible with the three bit
instruction register. All combinations are listed in the
Instruction Codes table. Three of these instructions are listed
as RESERVED and should not be used. The other five instructions are described in detail below.
Instructions are loaded into the TAP controller during the
Shift-IR state when the instruction register is placed between
TDI and TDO. During this state, instructions are shifted
through the instruction register through the TDI and TDO balls.
To execute the instruction once it is shifted in, the TAP
controller needs to be moved into the Update-IR state.
IDCODE
The IDCODE instruction causes a vendor-specific, 32-bit code
to be loaded into the instruction register. It also places the
instruction register between the TDI and TDO balls and allows
the IDCODE to be shifted out of the device when the TAP
controller enters the Shift-DR state.The IDCODE instruction is
loaded into the instruction register upon power-up or
whenever the TAP controller is given a test logic reset state.
Document #: 38-05539 Rev. *E
SAMPLE Z
The SAMPLE Z instruction causes the boundary scan register
to be connected between the TDI and TDO pins when the TAP
controller is in a Shift-DR state. The SAMPLE Z command puts
the output bus into a High-Z state until the next command is
given during the “Update IR” state.
SAMPLE/PRELOAD
SAMPLE/PRELOAD is a 1149.1 mandatory instruction. When
the SAMPLE/PRELOAD instructions are loaded into the instruction register and the TAP controller is in the Capture-DR
state, a snapshot of data on the inputs and output pins is captured in the boundary scan register.
The user must be aware that the TAP controller clock can only
operate at a frequency up to 20 MHz, while the SRAM clock
operates more than an order of magnitude faster. Because
there is a large difference in the clock frequencies, it is possible that during the Capture-DR state, an input or output will
undergo a transition. The TAP may then try to capture a signal
while in transition (metastable state). This will not harm the
device, but there is no guarantee as to the value that will be
captured. Repeatable results may not be possible.
To guarantee that the boundary scan register will capture the
correct value of a signal, the SRAM signal must be stabilized
long enough to meet the TAP controller's capture set-up plus
hold times (tCS and tCH). The SRAM clock input might not be
captured correctly if there is no way in a design to stop (or
slow) the clock during a SAMPLE/PRELOAD instruction. If this
is an issue, it is still possible to capture all other signals and
simply ignore the value of the CK and CK# captured in the
boundary scan register.
Once the data is captured, it is possible to shift out the data by
putting the TAP into the Shift-DR state. This places the boundary scan register between the TDI and TDO pins.
PRELOAD allows an initial data pattern to be placed at the
latched parallel outputs of the boundary scan register cells prior to the selection of another boundary scan test operation.
The shifting of data for the SAMPLE and PRELOAD phases
can occur concurrently when required—that is, while data
captured is shifted out, the preloaded data can be shifted in.
BYPASS
When the BYPASS instruction is loaded in the instruction
register and the TAP is placed in a Shift-DR state, the bypass
register is placed between the TDI and TDO pins. The
advantage of the BYPASS instruction is that it shortens the
boundary scan path when multiple devices are connected
together on a board.
EXTEST
The EXTEST instruction enables the preloaded data to be
driven out through the system output pins. This instruction also
selects the boundary scan register to be connected for serial
access between the TDI and TDO in the shift-DR controller
state.
Reserved
These instructions are not implemented but are reserved for
future use. Do not use these instructions.
Page 12 of 28
[+] Feedback
CY7C1355C
CY7C1357C
TAP Timing
1
2
Test Clock
(TCK)
3
t TH
t TMSS
t TMSH
t TDIS
t TDIH
t
TL
4
5
6
t CYC
Test Mode Select
(TMS)
Test Data-In
(TDI)
t TDOV
t TDOX
Test Data-Out
(TDO)
DON’T CARE
UNDEFINED
TAP AC Switching Characteristics Over the Operating Range[10, 11]
Parameter
Description
Min.
Max.
Unit
Clock
tTCYC
TCK Clock Cycle Time
tTF
TCK Clock Frequency
tTH
TCK Clock HIGH Time
20
ns
tTL
TCK Clock LOW Time
20
ns
50
ns
20
MHz
Output Times
tTDOV
TCK Clock LOW to TDO Valid
tTDOX
TCK Clock LOW to TDO Invalid
10
ns
0
ns
Set-up Times
tTMSS
TMS Set-Up to TCK Clock Rise
5
ns
tTDIS
TDI Set-Up to TCK Clock Rise
5
ns
tCS
Capture Set-Up to TCK Rise
5
ns
tTMSH
TMS Hold after TCK Clock Rise
5
ns
tTDIH
TDI Hold after Clock Rise
5
ns
tCH
Capture Hold after Clock Rise
5
ns
Hold Times
Notes:
10. tCS and tCH refer to the set-up and hold time requirements of latching data from the boundary scan register.
11. Test conditions are specified using the load in TAP AC Test Conditions. tR/tF = 1 ns.
Document #: 38-05539 Rev. *E
Page 13 of 28
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CY7C1355C
CY7C1357C
3.3V TAP AC Test Conditions
2.5V TAP AC Test Conditions
Input pulse levels ................................................ VSS to 3.3V
Input pulse levels................................................. VSS to 2.5V
Input rise and fall times ................................................... 1 ns
Input rise and fall time .....................................................1 ns
Input timing reference levels ...........................................1.5V
Input timing reference levels......................................... 1.25V
Output reference levels...................................................1.5V
Output reference levels ................................................ 1.25V
Test load termination supply voltage...............................1.5V
Test load termination supply voltage ............................ 1.25V
3.3V TAP AC Output Load Equivalent
2.5V TAP AC Output Load Equivalent
1.5V
1.25V
50Ω
50Ω
TDO
TDO
Z O= 50Ω
Z O= 50Ω
20pF
20pF
TAP DC Electrical Characteristics And Operating Conditions (0°C < TA < +70°C; VDD = 3.3V ± 0.165V unless
otherwise noted)[12]
Parameter
Description
Conditions
Min.
Max.
Unit
VOH1
Output HIGH Voltage
IOH = –4.0 mA, VDDQ = 3.3V
IOH = –1.0 mA, VDDQ = 2.5V
2.4
2.0
V
VOH2
Output HIGH Voltage
IOH = –100 µA
VDDQ = 3.3V
2.9
V
VDDQ = 2.5V
2.1
VOL1
Output LOW Voltage
IOL = 8.0 mA
VDDQ = 3.3V
0.4
V
IOL = 8.0 mA
VDDQ = 2.5V
0.4
V
VOL2
Output LOW Voltage
IOL = 100 µA
VDDQ = 3.3V
0.2
V
VIH
Input HIGH Voltage
VIL
Input LOW Voltage
IX
Input Load Current
VDDQ = 2.5V
V
V
0.2
V
2.0
VDD + 0.3
V
VDDQ = 2.5V
1.7
VDD + 0.3
V
VDDQ = 3.3V
–0.5
0.7
V
VDDQ = 2.5V
–0.3
0.7
V
–5
5
µA
VDDQ = 3.3V
GND < VIN < VDDQ
Identification Register Definitions
Instruction Field
Revision Number (31:29)
CY7C1355C
(256Kx36)
CY7C1357C
(512Kx18)
010
010
Description
Describes the version number
Device Depth (28:24)
01010
01010
Reserved for Internal Use
Device Width (23:18)
001001
001001
Defines memory type and architecture
Defines width and density
Cypress Device ID (17:12)
Cypress JEDEC ID Code (11:1)
ID Register Presence Indicator (0)
100110
010110
00000110100
00000110100
1
1
Allows unique identification of SRAM vendor
Indicates the presence of an ID register
Note:
12. All voltages referenced to VSS (GND).
Document #: 38-05539 Rev. *E
Page 14 of 28
[+] Feedback
CY7C1355C
CY7C1357C
Scan Register Sizes
Register Name
Instruction
Bit Size (x36)
Bit Size (x18)
3
3
Bypass
1
1
ID
32
32
Boundary Scan Order (119-ball BGA package)
69
69
Boundary Scan Order (165-ball FBGA package)
69
69
Identification Codes
Instruction
Code
Description
EXTEST
000
Captures I/O ring contents. Places the boundary scan register between TDI and TDO.
Forces all SRAM outputs to High-Z state. This instruction is not 1149.1 compliant.
IDCODE
001
Loads the ID register with the vendor ID code and places the register between TDI and
TDO. This operation does not affect SRAM operations.
SAMPLE Z
010
Captures I/O ring contents. Places the boundary scan register between TDI and TDO.
Forces all SRAM output drivers to a High-Z state.
RESERVED
011
Do Not Use: This instruction is reserved for future use.
SAMPLE/PRELOAD
100
Captures I/O ring contents. Places the boundary scan register between TDI and TDO.
Does not affect SRAM operation. This instruction does not implement 1149.1 preload
function and is therefore not 1149.1 compliant.
RESERVED
101
Do Not Use: This instruction is reserved for future use.
RESERVED
110
Do Not Use: This instruction is reserved for future use.
BYPASS
111
Places the bypass register between TDI and TDO. This operation does not affect SRAM
operations.
Document #: 38-05539 Rev. *E
Page 15 of 28
[+] Feedback
CY7C1355C
CY7C1357C
119-ball BGA Boundary Scan Order
CY7C1355C (256K x 36)
CY7C1357C (512K x 18)
Bit#
ball ID
Signal
Name
Bit#
ball ID
Signal
Name
Bit#
ball Id
Signal
Name
Bit#
ball Id
Signal
Name
1
K4
CLK
37
R6
A
1
K4
CLK
37
R6
A
2
H4
WE
38
T5
A
2
H4
WE
38
T5
A
3
M4
CEN
39
T3
A
3
M4
CEN
39
T3
A
4
F4
OE
40
R2
A
4
F4
OE
40
R2
A
5
B4
ADV/LD
41
R3
MODE
5
B4
ADV/LD
41
R3
MODE
6
G4
A
42
P2
DQPD
6
G4
A
42
Internal
Internal
7
C3
A
43
P1
DQD
7
C3
A
43
Internal
Internal
8
B3
A
44
L2
DQD
8
B3
A
44
Internal
Internal
9
D6
DQPB
45
K1
DQD
9
T2
A
45
Internal
Internal
10
H7
DQB
46
N2
DQD
10
Internal
Internal
46
P2
DQPB
11
G6
DQB
47
N1
DQD
11
Internal
Internal
47
N1
DQB
12
E6
DQB
48
M2
DQD
12
Internal
Internal
48
M2
DQB
13
D7
DQB
49
L1
DQD
13
D6
DQPA
49
L1
DQB
14
E7
DQB
50
K2
DQD
14
E7
DQA
50
K2
DQB
15
F6
DQB
51
Internal
Internal
15
F6
DQA
51
Internal
Internal
16
G7
DQB
52
H1
DQC
16
G7
DQA
52
H1
DQB
17
H6
DQB
53
G2
DQC
17
H6
DQA
53
G2
DQB
18
T7
ZZ
54
E2
DQC
18
T7
ZZ
54
E2
DQB
19
K7
DQA
55
D1
DQC
19
K7
DQA
55
D1
DQB
20
L6
DQA
56
H2
DQC
20
L6
DQA
56
Internal
Internal
21
N6
DQA
57
G1
DQC
21
N6
DQA
57
Internal
Internal
22
P7
DQA
58
F2
DQC
22
P7
DQA
58
Internal
Internal
23
N7
DQA
59
E1
DQC
23
Internal
Internal
59
Internal
Internal
24
M6
DQA
60
D2
DQPC
24
Internal
Internal
60
Internal
Internal
25
L7
DQA
61
C2
A
25
Internal
Internal
61
C2
A
26
K6
DQA
62
A2
A
26
Internal
Internal
62
A2
A
27
P6
DQPA
63
E4
CE1
27
Internal
Internal
63
E4
CE1
28
T4
A
64
B2
CE2
28
T6
A
64
B2
CE2
29
A3
A
65
L3
BWD
29
A3
A
65
Internal
Internal
30
C5
A
66
G3
BWC
30
C5
A
66
G3
BWB
31
B5
A
67
G5
BWB
31
B5
A
67
Internal
Internal
32
A5
A
68
L5
BWA
32
A5
A
68
L5
BWA
33
C6
A
69
B6
CE3
33
C6
A
69
B6
CE3
34
A6
A
34
A6
A
35
P4
A0
35
P4
A0
36
N4
A1
36
N4
A1
Document #: 38-05539 Rev. *E
Page 16 of 28
[+] Feedback
CY7C1355C
CY7C1357C
165-ball FBGA Boundary Scan Order
CY7C1355C (256K x 36)
CY7C1357C (512K x 18)
Bit#
ball ID
Signal
Name
Bit#
ball ID
Signal
Name
Bit#
ball ID
Signal
Name
Bit#
ball ID
Signal
Name
1
B6
CLK
37
R4
A
1
B6
CLK
37
R4
A
2
B7
WE
38
P4
A
2
B7
WE
38
P4
A
3
A7
CEN
39
R3
A
3
A7
CEN
39
R3
A
4
B8
OE
40
P3
A
4
B8
OE
40
P3
A
5
A8
ADV/LD
41
R1
MODE
5
A8
ADV/LD
41
R1
MODE
6
A9
A
42
N1
DQPD
6
A9
A
42
Internal
Internal
7
B10
A
43
L2
DQD
7
B10
A
43
Internal
Internal
8
A10
A
44
K2
DQD
8
A10
A
44
Internal
Internal
9
C11
DQPB
45
J2
DQD
9
A11
A
45
Internal
Internal
10
E10
DQB
46
M2
DQD
10
Internal
Internal
46
N1
DQPB
11
F10
DQB
47
M1
DQD
11
Internal
Internal
47
M1
DQB
12
G10
DQB
48
L1
DQD
12
Internal
Internal
48
L1
DQB
13
D10
DQB
49
K1
DQD
13
C11
DQPA
49
K1
DQB
14
D11
DQB
50
J1
DQD
14
D11
DQA
50
J1
DQB
15
E11
DQB
51
Internal
Internal
15
E11
DQA
51
Internal
Internal
16
F11
DQB
52
G2
DQC
16
F11
DQA
52
G2
DQB
17
G11
DQB
53
F2
DQC
17
G11
DQA
53
F2
DQB
18
H11
ZZ
54
E2
DQC
18
H11
ZZ
54
E2
DQB
19
J10
DQA
55
D2
DQC
19
J10
DQA
55
D2
DQB
20
K10
DQA
56
G1
DQC
20
K10
DQA
56
Internal
Internal
21
L10
DQA
57
F1
DQC
21
L10
DQA
57
Internal
Internal
22
M10
DQA
58
E1
DQC
22
M10
DQA
58
Internal
Internal
23
J11
DQA
59
D1
DQC
23
Internal
Internal
59
Internal
Internal
24
K11
DQA
60
C1
DQPC
24
Internal
Internal
60
Internal
Internal
25
L11
DQA
61
B2
A
25
Internal
Internal
61
B2
A
26
M11
DQA
62
A2
A
26
Internal
Internal
62
A2
A
27
N11
DQPA
63
A3
CE1
27
Internal
Internal
63
A3
CE1
28
R11
A
64
B3
CE2
28
R11
A
64
B3
CE2
29
R10
A
65
B4
BWD
29
R10
A
65
Internal
Internal
30
P10
A
66
A4
BWC
30
P10
A
66
Internal
Internal
31
R9
A
67
A5
BWB
31
R9
A
67
A4
BWB
32
P9
A
68
B5
BWA
32
P9
A
68
B5
BWA
33
R8
A
69
A6
CE3
33
R8
A
69
A6
CE3
34
P8
A
34
P8
A
35
R6
A0
35
R6
A0
36
P6
A1
36
P6
A1
Document #: 38-05539 Rev. *E
Page 17 of 28
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CY7C1355C
CY7C1357C
Maximum Ratings
DC Input Voltage ................................... –0.5V to VDD + 0.5V
(Above which the useful life may be impaired. For user guidelines, not tested.)
Storage Temperature ................................. –65°C to +150°C
Ambient Temperature with
Power Applied............................................. –55°C to +125°C
Current into Outputs (LOW)......................................... 20 mA
Static Discharge Voltage........................................... > 2001V
(per MIL-STD-883, Method 3015)
Latch-up Current.................................................... > 200 mA.
Operating Range
Supply Voltage on VDD Relative to GND........ –0.5V to +4.6V
Supply Voltage on VDDQ Relative to GND ...... –0.5V to +VDD
Range
DC Voltage Applied to Outputs
in Tri-State........................................... –0.5V to VDDQ + 0.5V
Commercial
Industrial
Ambient
Temperature
0°C to +70°C
–40°C to +85°C
VDD
VDDQ
3.3V – 5%/+10% 2.5V – 5%
to VDD
Electrical Characteristics Over the Operating Range[13, 14]
Parameter
Description
VDD
Power Supply Voltage
VDDQ
I/O Supply Voltage
VOH
VOL
VIH
VIL
IX
Output HIGH Voltage
Output LOW Voltage
Input HIGH
Input LOW
Voltage[13]
Voltage[13]
Input Leakage Current
except ZZ and MODE
Test Conditions
Min.
Max.
Unit
3.135
3.6
V
V
for 3.3V I/O
3.135
VDD
for 2.5V I/O
2.375
2.625
for 3.3V I/O, IOH = −4.0 mA
2.4
V
for 2.5V I/O, IOH = −1.0 mA
2.0
V
for 3.3V I/O, IOL= 8.0 mA
0.4
V
for 2.5V I/O, IOL= 1.0 mA
0.4
V
for 3.3V I/O
2.0
VDD + 0.3V
V
for 2.5V I/O
1.7
VDD + 0.3V
V
for 3.3V I/O
–0.3
0.8
V
for 2.5V I/O
–0.3
0.7
V
–5
5
µA
GND ≤ VI ≤ VDDQ
Input = VDD
Input Current of ZZ
µA
–30
Input Current of MODE Input = VSS
5
Input = VSS
µA
–5
Input = VDD
µA
30
µA
IOZ
Output Leakage Current GND ≤ VI ≤ VDDQ, Output Disabled
5
µA
IDD
VDD Operating Supply
Current
VDD = Max., IOUT = 0 mA,
f = fMAX = 1/tCYC
7.5-ns cycle, 133 MHz
250
mA
10-ns cycle, 100 MHz
180
mA
ISB1
Automatic CE
Power-down
Current—TTL Inputs
VDD = Max, Device Deselected,
VIN ≥ VIH or VIN ≤ VIL
f = fMAX, inputs switching
All speeds
110
mA
ISB2
VDD = Max, Device Deselected,
Automatic CE
Power-down
VIN ≤ 0.3V or VIN > VDD – 0.3V,
Current—CMOS Inputs f = 0, inputs static
All speeds
40
mA
ISB3
Automatic CE
VDD = Max, Device Deselected, or All speeds
Power-down
VIN ≤ 0.3V or VIN > VDDQ – 0.3V
Current—CMOS Inputs f = fMAX, inputs switching
Automatic CE
VDD = Max, Device Deselected, All Speeds
Power-down
VIN ≥ VIH or VIN ≤ VIL, f = 0, inputs
Current—TTL Inputs
static
100
mA
40
mA
ISB4
–5
Notes:
13. Overshoot: VIH(AC) < VDD +1.5V (Pulse width less than tCYC/2), undershoot: VIL(AC) > –2V (Pulse width less than tCYC/2).
14. TPower-up: Assumes a linear ramp from 0V to VDD(min.) within 200 ms. During this time VIH < VDD and VDDQ < VDD.
Document #: 38-05539 Rev. *E
Page 18 of 28
[+] Feedback
CY7C1355C
CY7C1357C
Capacitance[15]
Parameter
Description
CIN
Input Capacitance
CCLK
Clock Input Capacitance
CI/O
Input/Output Capacitance
Test Conditions
100 TQFP
Max.
119 BGA
Max.
165 FBGA
Max.
TA = 25°C, f = 1 MHz,
VDD = 3.3V.
VDDQ = 2.5V
5
5
5
pF
5
5
5
pF
5
7
7
pF
100 TQFP
Package
119 BGA
Package
165 FBGA
Package
Unit
29.41
34.1
16.8
°C/W
6.31
14.0
3.0
°C/W
Unit
Thermal Resistance[15]
Parameter
Description
ΘJA
Thermal Resistance
(Junction to Ambient)
ΘJC
Thermal Resistance
(Junction to Case)
Test Conditions
Test conditions follow standard
test methods and procedures
for measuring thermal
impedance, per EIA/JESD51.
AC Test Loads and Waveforms
3.3V I/O Test Load
R = 317Ω
3.3V
OUTPUT
ALL INPUT PULSES
VDDQ
OUTPUT
RL = 50Ω
Z0 = 50Ω
10%
90%
10%
90%
GND
5 pF
R = 351Ω
≤ 1 ns
≤ 1 ns
VT = 1.5V
INCLUDING
JIG AND
SCOPE
(a)
(c)
(b)
2.5V I/O Test Load
R = 1667Ω
2.5V
OUTPUT
Z0 = 50Ω
10%
R = 1538Ω
(a)
INCLUDING
JIG AND
SCOPE
90%
10%
90%
GND
5 pF
VT = 1.25V
ALL INPUT PULSES
VDDQ
OUTPUT
RL = 50Ω
(b)
≤ 1 ns
≤ 1 ns
(c)
Note:
15. Tested initially and after any design or process change that may affect these parameters
Document #: 38-05539 Rev. *E
Page 19 of 28
[+] Feedback
CY7C1355C
CY7C1357C
Switching Characteristics Over the Operating Range [16, 17]
–133
Parameter
tPOWER
Description
Min.
[18]
VDD(Typical) to the First Access
–100
Max.
Min.
Max.
Unit
1
1
ms
Clock
tCYC
Clock Cycle Time
7.5
10
ns
tCH
Clock HIGH
3.0
4.0
ns
tCL
Clock LOW
3.0
4.0
ns
Output Times
tCDV
Data Output Valid after CLK Rise
tDOH
Data Output Hold after CLK Rise
[19, 20, 21]
6.5
2.0
7.5
2.0
ns
tCLZ
Clock to Low-Z
tCHZ
Clock to High-Z[19, 20, 21]
3.5
3.5
ns
tOEV
OE LOW to Output Valid
3.5
3.5
ns
tOELZ
tOEHZ
OE LOW to Output
Low-Z[19, 20, 21]
OE HIGH to Output
High-Z[19, 20, 21]
0
ns
0
0
ns
0
3.5
ns
3.5
ns
Set-up Times
tAS
Address Set-up before CLK Rise
1.5
1.5
ns
tALS
ADV/LD Set-up before CLK Rise
1.5
1.5
ns
tWES
WE, BWX Set-up before CLK Rise
1.5
1.5
ns
tCENS
CEN Set-up before CLK Rise
1.5
1.5
ns
tDS
Data Input Set-up before CLK Rise
1.5
1.5
ns
tCES
Chip Enable Set-Up before CLK Rise
1.5
1.5
ns
tAH
Address Hold after CLK Rise
0.5
0.5
ns
tALH
ADV/LD Hold after CLK Rise
0.5
0.5
ns
tWEH
WE, BWX Hold after CLK Rise
0.5
0.5
ns
Hold Times
tCENH
CEN Hold after CLK Rise
0.5
0.5
ns
tDH
Data Input Hold after CLK Rise
0.5
0.5
ns
tCEH
Chip Enable Hold after CLK Rise
0.5
0.5
ns
Notes:
16. Timing reference level is 1.5V when VDDQ = 3.3V and is 1.25V when VDDQ = 2.5V.
17. Test conditions shown in (a) of AC Test Loads unless otherwise noted.
18. This part has a voltage regulator internally; tPOWER is the time that the power needs to be supplied above VDD(minimum) initially, before a Read or Write operation
can be initiated.
19. tCHZ, tCLZ,tOELZ, and tOEHZ are specified with AC test conditions shown in part (b) of AC Test Loads. Transition is measured ± 200 mV from steady-state voltage.
20. At any given voltage and temperature, tOEHZ is less than tOELZ and tCHZ is less than tCLZ to eliminate bus contention between SRAMs when sharing the same
data bus. These specifications do not imply a bus contention condition, but reflect parameters guaranteed over worst case user conditions. Device is designed
to achieve High-Z prior to Low-Z under the same system conditions.
21. This parameter is sampled and not 100% tested.
Document #: 38-05539 Rev. *E
Page 20 of 28
[+] Feedback
CY7C1355C
CY7C1357C
Switching Waveforms
Read/Write Waveforms[22, 23, 24]
1
2
3
tCYC
4
5
6
7
8
9
A5
A6
A7
10
CLK
tCENS
tCENH
tCES
tCEH
tCH
tCL
CEN
CE
ADV/LD
WE
BWX
A1
ADDRESS
tAS
A2
A4
A3
tCDV
tAH
tDOH
tCLZ
DQ
D(A1)
tDS
D(A2)
Q(A3)
D(A2+1)
tOEV
Q(A4+1)
Q(A4)
tOELZ
WRITE
D(A1)
WRITE
D(A2)
D(A5)
Q(A6)
D(A7)
WRITE
D(A7)
DESELECT
tOEHZ
tDH
OE
COMMAND
tCHZ
BURST
WRITE
D(A2+1)
READ
Q(A3)
READ
Q(A4)
DON’T CARE
BURST
READ
Q(A4+1)
tDOH
WRITE
D(A5)
READ
Q(A6)
UNDEFINED
Notes:
22. For this waveform ZZ is tied LOW.
23. When CE is LOW, CE1 is LOW, CE2 is HIGH and CE3 is LOW. When CE is HIGH, CE1 is HIGH or CE2 is LOW or CE3 is HIGH.
24. Order of the Burst sequence is determined by the status of the MODE (0 = Linear, 1 = Interleaved). Burst operations are optional.
Document #: 38-05539 Rev. *E
Page 21 of 28
[+] Feedback
CY7C1355C
CY7C1357C
Switching Waveforms (continued)
NOP, STALL and DESELECT Cycles[22, 23, 25]
1
2
3
tCYC
4
5
6
7
8
9
A5
A6
A7
10
CLK
tCENS tCENH
tCH
tCL
CEN
tCES
tCEH
CE
ADV/LD
WE
BWX
A1
ADDRESS
tAS
A2
A4
A3
tCDV
tAH
tDOH
tCLZ
DQ
D(A1)
tDS
D(A2)
Q(A3)
D(A2+1)
tOEV
Q(A4+1)
Q(A4)
tOELZ
WRITE
D(A1)
WRITE
D(A2)
D(A5)
Q(A6)
D(A7)
WRITE
D(A7)
DESELECT
tOEHZ
tDH
OE
COMMAND
tCHZ
BURST
WRITE
D(A2+1)
READ
Q(A3)
READ
Q(A4)
DON’T CARE
BURST
READ
Q(A4+1)
tDOH
WRITE
D(A5)
READ
Q(A6)
UNDEFINED
Note:
25. The IGNORE CLOCK EDGE or STALL cycle (Clock 3) illustrates CEN being used to create a pause. A write is not performed during this cycle.
Document #: 38-05539 Rev. *E
Page 22 of 28
[+] Feedback
CY7C1355C
CY7C1357C
Switching Waveforms (continued)
ZZ Mode Timing[26, 27]
CLK
t ZZ
ZZ
I
t ZZREC
t ZZI
SUPPLY
I DDZZ
t RZZI
ALL INPUTS
(except ZZ)
Outputs (Q)
DESELECT or READ Only
High-Z
DON’T CARE
Notes:
26. Device must be deselected when entering ZZ mode. See truth table for all possible signal conditions to deselect the device.
27. DQs are in high-Z when exiting ZZ sleep mode.
Document #: 38-05539 Rev. *E
Page 23 of 28
[+] Feedback
CY7C1355C
CY7C1357C
Ordering Information
Not all of the speed, package and temperature ranges are available. Please contact your local sales representative or
visit www.cypress.com for actual products offered.
Speed
(MHz)
133
Ordering Code
CY7C1355C-133AXC
Package
Diagram
Part and Package Type
51-85050 100-Pin Thin Quad Flat Pack (14 x 20 x 1.4 mm) Lead-Free
Operating
Range
Commercial
CY7C1357C-133AXC
CY7C1355C-133BGC
51-85115 119-ball Ball Grid Array (14 x 22 x 2.4 mm)
CY7C1357C-133BGC
CY7C1355C-133BGXC
51-85115 119-ball Ball Grid Array (14 x 22 x 2.4 mm) Lead-Free
CY7C1357C-133BGXC
CY7C1355C-133BZC
51-85180 165-ball Fine-Pitch Ball Grid Array (13 x 15 x 1.4 mm)
CY7C1357C-133BZC
CY7C1355C-133BZXC
51-85180 165-ball Fine-Pitch Ball Grid Array (13 x 15 x 1.4 mm) Lead-Free
CY7C1357C-133BZXC
CY7C1355C-133AXI
51-85050 100-Pin Thin Quad Flat Pack (14 x 20 x 1.4 mm) Lead-Free
lndustrial
CY7C1357C-133AXI
CY7C1355C-133BGI
51-85115 119-ball Ball Grid Array (14 x 22 x 2.4 mm)
CY7C1357C-133BGI
CY7C1355C-133BGXI
51-85115 119-ball Ball Grid Array (14 x 22 x 2.4 mm) Lead-Free
CY7C1357C-133BGXI
CY7C1355C-133BZI
51-85180 165-ball Fine-Pitch Ball Grid Array (13 x 15 x 1.4 mm)
CY7C1357C-133BZI
CY7C1355C-133BZXI
51-85180 165-ball Fine-Pitch Ball Grid Array (13 x 15 x 1.4 mm) Lead-Free
CY7C1357C-133BZXI
100
CY7C1355C-100AXC
51-85050 100-Pin Thin Quad Flat Pack (14 x 20 x 1.4 mm) Lead-Free
Commercial
CY7C1357C-100AXC
CY7C1355C-100BGC
51-85115 119-ball Ball Grid Array (14 x 22 x 2.4 mm)
CY7C1357C-100BGC
CY7C1355C-100BGXC
51-85115 119-ball Ball Grid Array (14 x 22 x 2.4 mm) Lead-Free
CY7C1357C-100BGXC
CY7C1355C-100BZC
51-85180 165-ball Fine-Pitch Ball Grid Array (13 x 15 x 1.4 mm)
CY7C1357C-100BZC
CY7C1355C-100BZXC
51-85180 165-ball Fine-Pitch Ball Grid Array (13 x 15 x 1.4 mm) Lead-Free
CY7C1357C-100BZXC
CY7C1355C-100AXI
51-85050 100-Pin Thin Quad Flat Pack (14 x 20 x 1.4 mm) Lead-Free
lndustrial
CY7C1357C-100AXI
CY7C1355C-100BGI
51-85115 119-ball Ball Grid Array (14 x 22 x 2.4 mm)
CY7C1357C-100BGI
CY7C1355C-100BGXI
51-85115 119-ball Ball Grid Array (14 x 22 x 2.4 mm) Lead-Free
CY7C1357C-100BGXI
CY7C1355C -100BZI
51-85180 165-ball Fine-Pitch Ball Grid Array (13 x 15 x 1.4 mm)
CY7C1357C-100BZI
CY7C1355C-100BZXI
51-85180 165-ball Fine-Pitch Ball Grid Array (13 x 15 x 1.4 mm) Lead-Free
CY7C1357C-100BZXI
Document #: 38-05539 Rev. *E
Page 24 of 28
[+] Feedback
CY7C1355C
CY7C1357C
Package Diagrams
100-Pin Thin Plastic Quad Flatpack (14 x 20 x 1.4 mm) (51-85050)
16.00±0.20
1.40±0.05
14.00±0.10
81
100
80
1
20.00±0.10
22.00±0.20
0.30±0.08
0.65
TYP.
30
12°±1°
(8X)
SEE DETAIL
A
51
31
50
0.20 MAX.
R 0.08 MIN.
0.20 MAX.
0.10
1.60 MAX.
0° MIN.
SEATING PLANE
STAND-OFF
0.05 MIN.
0.15 MAX.
0.25
NOTE:
1. JEDEC STD REF MS-026
GAUGE PLANE
0°-7°
R 0.08 MIN.
0.20 MAX.
2. BODY LENGTH DIMENSION DOES NOT INCLUDE MOLD PROTRUSION/END FLASH
MOLD PROTRUSION/END FLASH SHALL NOT EXCEED 0.0098 in (0.25 mm) PER SIDE
BODY LENGTH DIMENSIONS ARE MAX PLASTIC BODY SIZE INCLUDING MOLD MISMATCH
3. DIMENSIONS IN MILLIMETERS
0.60±0.15
0.20 MIN.
51-85050-*B
1.00 REF.
DETAIL
Document #: 38-05539 Rev. *E
A
Page 25 of 28
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CY7C1355C
CY7C1357C
Package Diagrams (continued)
119-Ball BGA (14 x 22 x 2.4 mm) (51-85115)
Ø0.05 M C
Ø0.25 M C A B
A1 CORNER
Ø0.75±0.15(119X)
Ø1.00(3X) REF.
1
2
3 4
5
6
7
7
6
5
4 3 2 1
A
A
B
B
C
D
1.27
C
D
E
E
F
F
H
19.50
J
K
L
20.32
G
H
22.00±0.20
G
J
K
L
M
10.16
M
N
P
N
P
R
R
T
T
U
U
1.27
0.70 REF.
A
3.81
7.62
30° TYP.
14.00±0.20
0.15(4X)
0.15 C
2.40 MAX.
B
0.90±0.05
0.25 C
12.00
51-85115-*B
C
Document #: 38-05539 Rev. *E
0.60±0.10
0.56
SEATING PLANE
Page 26 of 28
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CY7C1355C
CY7C1357C
Package Diagrams (continued)
165 FBGA 13 x 15 x 1.40 MM BB165D/BW165D
165-Ball FBGA (13 x 15 x 1.4 mm) (51-85180)
BOTTOM VIEW
PIN 1 CORNER
BOTTOM VIEW
TOP VIEW
PIN 1 CORNER
TOP VIEW
Ø0.05 M C
Ø0.25 MØ0.05
CAB MC
PIN 1 CORNER
Ø0.25 M C A B
Ø0.50 -0.06
(165X)
PIN 1 CORNER
1
2
+0.14
4
2
5
3
6
4
7
5
8
6
9
7
10
11
8
9
11
10
11
10
9
11
8
10
7
9
6
8
5
7
Ø0.50 -0.06 (165X)
4
6
1
3 +0.14
2
5
4
3
2
1A
B
A
C
B
C
B
D
C
D
C
E
D
F
1.00
A
1.00
B
F
E
G
F
G
F
H
G
H
G
J
H
K
J
L
K
M
L
N
M
P
N
P
N
R
P
R
P
7.00
7.00
14.00
D
E
14.00
15.00±0.10
E
15.00±0.10
15.00±0.10
A
15.00±0.10
3
1
J
H
K
J
L
K
M
L
N
M
R
R
A
A
A
1.00
5.00
A
1.00
5.00
10.00
10.00
B
B
13.00±0.10
B
13.00±0.10
B
13.00±0.10
13.00±0.10
SEATING PLANE
NOTES :
NOTES
:
SOLDER
PAD TYPE
: NON-SOLDER MASK DEFINED (NSMD)
PACKAGE
WEIGHT
SOLDER
PAD: 0.475g
TYPE : NON-SOLDER MASK DEFINED (NSMD)
JEDEC REFERENCE
: MO-216
/ DESIGN 4.6C
PACKAGE WEIGHT
: 0.475g
PACKAGE
CODE
: BB0AC : MO-216 / DESIGN 4.6C
JEDEC
REFERENCE
PACKAGE CODE : BB0AC
51-85180-*A
0.35±0.06
C
0.35±0.06
0.36
0.36
SEATING PLANE
C
0.15 C
1.40 MAX.
1.40 MAX.
0.15(4X)
0.15 C
0.53±0.05
0.53±0.05
0.25
C
0.25 C
0.15(4X)
51-85180-*A
NoBL and No Bus Latency are trademarks of Cypress Semiconductor Corporation. ZBT is a trademark of Integrated Device
Technology, Inc. All product and company names mentioned in this document are the trademarks of their respective holders
Document #: 38-05539 Rev. *E
Page 27 of 28
© Cypress Semiconductor Corporation, 2006. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use
of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be
used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its
products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress
products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.
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CY7C1355C
CY7C1357C
Document History Page
Document Title: CY7C1355C/CY7C1357C 9-Mbit (256K x 36/512K x 18) Flow-Through SRAM with NoBL™ Architecture
Document Number: 38-05539
REV.
ECN NO.
Issue Date
Orig. of
Change
Description of Change
**
242032
See ECN
RKF
New data sheet
*A
332059
See ECN
PCI
Changed Boundary Scan Order to match the B rev of these devices
Removed description on Extest Output Bus Tri-state
Removed 117 MHz Speed Bin
Changed IDDZZ from 35 mA to 50 mA on Pg # 9
Changed ISB1 and ISB3 from 40 mA to 110 and 100 mA respectively
Address expansion pins/balls in the pinouts for all packages are modified as
per JEDEC standard
Modified VOL, VOH test conditions
Corrected ISB4 Test Condition from (VIN ≥ VDD – 0.3V or VIN ≤ 0.3V) to (VIN ≥ VIH
or VIN ≤ VIL) in the Electrical Characteristic Table on Pg #18
Changed ΘJA and ΘJc for TQFP Package from 25 and 9 °C/W to 29.41 and
6.13 °C/W
respectively
Changed ΘJA and ΘJc for BGA Package from 25 and 6 °C/W to 34.1 and 14.0
°C/W
respectively
Changed ΘJA and ΘJc for FBGA Package from 27 and 6 °C/W to 16.8 and 3.0
°C/W respectively
Added lead-free information for 100-pin TQFP, 119 BGA and 165 FBGA
Packages
Updated Ordering Information Table
Changed from Preliminary to Final
*B
351895
See ECN
PCI
Changed ISB2 from 30 to 40 mA
Updated Ordering Information Table
*C
377095
See ECN
PCI
Modified test condition in note# 14 from VIH < VDD to VIH < VDD
*D
408298
See ECN
RXU
Changed address of Cypress Semiconductor Corporation on Page# 1 from
“3901 North First Street” to “198 Champion Court”
Modified “Input Load” to “Input Leakage Current except ZZ and MODE” in the
Electrical Characteristics Table
Changed three-state to tri-state
Replaced Package Name column with Package Diagram in the Ordering
Information table
Updated Ordering Information Table
*E
501793
See ECN
VKN
Added the Maximum Rating for Supply Voltage on VDDQ Relative to GND
Changed tTH, tTL from 25 ns to 20 ns and tTDOV from 5 ns to 10 ns in TAP AC
Switching Characteristics table.
Updated the Ordering Information table.
Document #: 38-05539 Rev. *E
Page 28 of 28
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