VX-1700 Series - The Repeater Builder`s Technical Information Page

VERTEX STANDARD CO., LTD.
4-8-8 Nakameguro, Meguro-Ku, Tokyo 153-8644, Japan
VERTEX STANDARD
VX-1700 Series
US Headquarters
10900 Walker Street, Cypress, CA 90630, U.S.A.
YAESU EUROPE B.V.
HF Multi Mode Mobile Radio
Service Manual
YAESU UK LTD.
Unit 12, Sun Valley Business Park, Winnall Close
Winchester, Hampshire, SO23 0LB, U.K.
VERTEX STANDARD HK LTD.
For USA Version
©2005 VERTEX STANDARD CO., LTD.
P.O. Box 75525, 1118 ZN Schiphol, The Netherlands
EC051H95A
Unit 5, 20/F., Seaview Centre, 139-141 Hoi Bun Road,
Kwun Tong, Kowloon, Hong Kong
Introduction
This manual provides the technical information necessary for servicing the VX-1700 HF Transceiver.
Servicing this equipment requires expertise in handing surface-mount chip components. Attempts by nonqualified persons to service this equipment may result in permanent damage not covered by the warranty,
and may be illegal in some countries.
Two PCB layout diagrams are provided for each double-sided board in this transceiver. Each side of the board
is referred to by the type of the majority of components installed on that side (“Side A” or “Side B”). In most
cases one side has only chip components (surface-mount devices), and the other has either a mixture of both
chip and leaded components (trimmers, coils, electrolytic capacitors, ICs, etc.), or leaded components only.
As described in the pages to follow, the advanced microprocessor design of the VX-1700 Transceiver allows a
complete alignment of this transceiver to be performed without opening the case of the radio; all adjustments
can be performed from the front panel, using the “Alignment Mode” menu.
While we believe the information in this manual to be correct, VERTEX STANDARD assumes no liability for
damage that may occur as a result of typographical or other errors that may be present. Your cooperation in
pointing out any inconsistencies in the technical information would be appreciated.
Contents
Specifications ...................................................................................................................................................... 2
Exploded View & Miscellaneous Parts .......................................................................................................... 3
Block Diagram .................................................................................................................................................... 5
Connection Diagram .......................................................................................................................................... 6
Circuit Description ............................................................................................................................................. 7
Connector Pinout Diagrams ........................................................................................................................... 10
Alignment .......................................................................................................................................................... 11
ALE-1 Automatic Link Establishment Unit Installation .......................................................................... 19
CE77 PC Programming Software ................................................................................................................... 21
Board Units (Schematics, Layouts & Parts)
MAIN Unit .................................................................................................................................................. 49
PA Unit ........................................................................................................................................................ 71
PANEL Unit ................................................................................................................................................ 81
GPS-INTERFACE Unit .............................................................................................................................. 87
MIC Unit ...................................................................................................................................................... 91
ENC Unit ..................................................................................................................................................... 92
ALE Unit (Option) ..................................................................................................................................... 93
1
Specifications
General
Receiver Frequency Range:
Transmitter Frequency:
Emission Modes:
Frequency Synthesizer Step:
Frequency Stability:
Operating Temperature Range:
Antenna Impedance:
Supply Voltage:
Power Consumption:
Dimensions (WxHxD):
Weight (approx.):
30 kHz ~ 30.0000 MHz
1.600 ~ 30.0000 MHz
A1A (CW), J3E (LSB/USB), A3E (AM), J2B (USB/LSB),
10 Hz, 100 Hz, 1 kHz
±1 ppm (Typical)
14° F ~ 131° F (–10° ~ +55° C) @Duty Cycle TX:RX = 1 min.: 4 min.
50 Ohms
13.8 Volts DC ±15%, negative ground
25 mA (Standby)
1.0 A (Receive, no signal)
1.5 A (Receive)
22 A (Transmit, 125 Watts output)
9.5” x 3.9” x 11.2” (241 x 99 x 285 mm)
9.5 lbs (4.3 kg)
Transmitter
Power Output:
Modulation Types:
Spurious Radiation:
J3E Carrier Suppression:
Undesired Sideband Suppression:
J3E Audio Response:
Occupied Bandwidth:
Microphone Impedance:
125 Watts (A1A, J2B, J3E @1.6000 ~ 3.9999 MHz)
100 Watts (A1A, J2B, J3E @4.0000 ~ 30.0000 MHz)
31 Watts AM Carrier (A3E @1.6000 ~ 3.9999 MHz)
25 Watts AM Carrier (A3E @4.0000 ~ 30.0000 MHz)
J3E: PSN type modulator,
A3E: Low-level (early stage)
Better than –56 dB
Better than 50 dB below peak output
Better than 60 dB below peak output
Not more than –6 dB from 400 Hz ~ 2500 Hz
A1A: less than 0.5 kHz
J3E: less than 3.0 kHz
A3E: less than 6.0 kHz
200 ~ 10 k Ohms (600 Ohms Nominal)
Receiver
Circuit Type:
Intermediate Frequencies:
Sensitivity:
Squelch Sensitivity (A1A/J2B/J3E):
IF Rejection:
Image Rejection:
Selectivity:
Audio Output:
Audio Output Impedance:
Conducted Radiation:
Double-conversion Superheterodyne
1st: 45.274 MHz, 2nd: 24 kHz
A1A/J2B/J3E
A3E
0.1 ~ 0.5 MHz
—
—
0.5 ~ 1.6 MHz: 1.41 µV
8 µV
1.6 ~ 30 MHz:
0.16 µV
1 µV
(A1A/J2B/J3E/A3E: S/N 10 dB)
0.1 ~ 0.5 MHz
—
0.5 ~ 1.6 MHz: 2.5 µV
1.6 ~ 30 MHz:
2 µV
Better than 80 dB
Better than 80 dB
–6 dB
–60 dB
A1A(W), J2B(W), J3E > 2.2 kHz < 4.5 kHz
A1A(N), J2B(N)
> 500 Hz < 2.0 kHz
A3E
> 6 kHz
< 20 kHz
At least 2.2 Watts into 8 Ohms @ 10% THD
4 ~ 16 Ohms (8 Ohms Nominal)
Less than 4000 µµW
Specifications are subject to change without notice or obligation.
2
Exploded View & Miscellaneous Parts
14
14
14
14
14
RA0695200
COVER (TOP)
14
14
13
14
1
13
PA UNIT
2
13
13
P1090352
CONNECTOR (FM-MDR-MI)
6
6
13
6
6
3
15
5
RA0635400
CHASSIS
RA0695600
HOLDER PLATE (CW)
5
T9207202A
WIRE ASSY
PANEL UNIT
RA0695700
HOLDER PLATE (D-SUB)
12
RA0696100
REFLECTOR SHEET
RA0727200
DIFFUSER SHEET (BLIND) (2pcs)
9
4
RA0695800
INTER CONNECTOR (2pcs)
9
G6090162
LCD
MAIN UNIT
4
10
RA0695000
FRONT PLATE (A)
RA0727100
DIFFUSER SHEET (LCD)
12
RA0694600
PACKING PAD (SP)
RA069450A
RUBBER KNOB (PW)
RA0695900
LIGHT GUIDE (LCD)
12
M4090146
SPEAKER
12
11
MIC UNIT
11
RA0695500
PACKING PAD (CHASSIS)
GPS INTERFACE UNIT
RA0696000
LCD HOLDER
RA0696200
SPONGE RUBBER (LCD)
2
VXSTD P/N
A06870001
T9023725
Q0000074
2
REF.
P0001
P0002
P0004
P0005
P0006
P0007
P0008
8
M2090040
FAN
RA0695300
COVER (BOTTOM)
9
9
14
4
RA0695000
FRONT PLATE (B)
14
RA069420A
RUBBER KNOB (12KEY)
4
RA069430A
RUBBER KNOB (4KEY)
RA069440A
RUBBER KNOB (UP/DOWN)
RA0694800
KNOB (L)
RA0694900
KNOB (S)
14
S4000043
CASE LEG (FF-003)
R3100700A
FOOT
14
7
QTY.
1
1
1
13
13
ENC UNIT
RA0725400
FRONT PANEL ASSY
SUPPLIED ACCESSORIES
DESCRIPTION
MH-31A8J Hand Microphone
DC Power Cord
Spare Fuse (25 A Blade Type)
R3100700A
FOOT
7
R0145630
STAND
S4000043
CASE LEG (FF-003)
REF.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
VXSTD P/N
U02308002
U03308002
U04410002
U10306001
U20205002
U20306002
U20406007
U20430002
U24106002
U24108002
U24206001
U24208002
U24308002
U31306007
U70004012
CONNECTION CABLES
VXSTD P/N
DESCRIPTION
T9315504
Coaxial Cable (J1001J2006)
T9315905
Coaxial Cable (J1002J2001)
T9207203
30-pin Flat Cable ( J1003J2002)
T9207210
13-pin Molex (J1008J4001)
T9207211
8-pin Molex (J1005J6002)
T9207209
8-pin Molex (J3004J6101)
T9207117A 30-pin Flat Cable (J1004J3001)
DESCRIPTION
SEMS SCREW
SEMS SCREW
SEMS SCREW
TRUSS HEAD SCREW
BINDING HEAD SCREW
BINDING HEAD SCREW
BINDING HEAD SCREW
BINDING HEAD SCREW
TAPTITE SCREW
TAPTITE SCREW
TAPTITE SCREW
TAPTITE SCREW
TAPTITE SCREW
OVAL HEAD SCREW
PLAIN WASHER
SM3X8NI
ASM3X8NI
HSM4X10NI
M3X6
M2.6X5NI
M3X6NI
M4X6B
M4X30(Ni)
M2X6NI
M2X8NI
M2.6X6
M2.6X8NI
M3X8NI
M3X6B
FW4BSNI
QTY.
4
7
1
4
2
4
2
4
6
3
2
4
14
12
1
Non-designated parts are available only as part of a designated assembly.
3
Exploded View & Miscellaneous Parts
Note
4
Block Diagram
5
Connection Diagram
6
Circuit Description
Receive Signal Path
Incoming RF signal from the ANT jack is delivered
to the PA Unit, and passes through the TX/RX relay
RL2009 to J2006.
The RF signal is then applied to J1001 on the MAIN
Unit, and passed through the limiter circuit consisting of D1006, D1007, D1008, and D1009 (all RLS245)
to prevent distortion from high RF signal input, and
is fed to one of eight band-pass filters which strip
away unwanted signals prior to delivery of the incoming signal to the RF amplifiers, Q1022 and Q1024
(both 2SK520-K41).
The amplified RF signal passes through a low-pass
filter to the doubly-balanced mixer D1032
(HSB88WS), where the RF signal is mixed with the
1st local signal delivered from buffer amplifier
Q1029 (2SC2954), resulting in a 45.274 MHz 1st IF
signal.
The 45.274 MHz 1st IF signal is fed through monolithic crystal filter XF1001, which strips away unwanted mixer products, and is amplified by 1st IF
amplifier Q1050 (3SK151GR); the 1st IF signal is
then applied to the 2nd mixer Q1052 (RF2713),
where it is mixed with the 45.25 MHz 2nd local signal which is divided from 90.5 MHz reference signal delivered from buffer amplifier Q1075
(2SC2714Y), resulting in a 24 kHz 2nd IF signal.
The 24 kHz 2nd IF signal is fed through buffer amplifiers Q1030 and Q1041 (both UPC4572G2) to the
A/D converter Q1071 (AK4528A), then delivered to
the DSP IC Q1035 (UPD77115), where the 24 kHz
2nd IF signal is demodulated in accordance with the
mode selection data from the main CPU Q1018
(HD64F2134). The demodulated signal is delivered
to the D/A converter Q1081 (AK4550VT) which converts the demodulated signal to audio.
The audio signal from the D/A converter Q1081
(AK4550VT) is fed through a low-pass filter at Q1036
(UPC4572G), which eliminates high-pitched noise
on the audio signal, and is fed to the AF mute gate
Q1092 (2SJ125D), then applied to the audio amplifier Q1055 (TDA2003H). The amplified audio signal
is delivered to J3001 on the PANEL Unit, then passes through the speaker switch RL3001/Q3006
(DTC143ZE) to the internal or external speaker.
The DSP IC Q1035 (UPD77115) outputs AGC data
which is proportionate to the received signal
strength to the main CPU Q1018 (HD64F2134). The
main CPU Q1018 (HD64F2134), in turn, outputs a
DC voltage in accordance with the received signal
strength. This DC voltage is fed through buffer amplifier Q1039 (LM2904PW) to RF amplifiers Q1022
& Q1024 (both 2SK520) and gate 2 of IF amplifier
Q1050 (3SK151GR), to reduce their gains when
strong signals are present in the receiver passband.
Transmit Signal Path
The speech audio from the microphone is delivered
to J6001 on the MIC Unit, then applied to J1005 on
the MAIN Unit.
The speech audio is amplified by Q1032-1
(UPC4572G2), then passed though the clipper,
D1044 (MC2850), and further amplified by Q1032-2
(UPC4572G2).
The amplified speech audio is fed through the A/D
converter Q1081 (AK4550VT), then delivered to the
DSP IC Q1035 (UPD77115), where the speech audio is modulated in the 24 kHz TX 1st IF signal in
accordance with the mode selection data from the
main CPU, Q1018 (HD64F2134).
The modulated signal is fed through the D/A converter Q1071 (AK4528A) and buffer amplifier Q1034
(UPC4572G2) to the mixer Q1054 (RF2713) where
the 24 kHz TX 1st IF signal is mixed with 1st local
signal delivered from buffer amplifier Q1075
(2SC2714Y), resulting in a 45.274 MHz IF signal.
The resulting 45.274 MHz IF signal is buffered by
Q1049 (3SK151GR), then delivered to the monolithic crystal filter XF1001, which strips away unwanted mixer products, and then is amplified by Q1043
(3SK151GR). The amplified IF signal is delivered
to doubly-balanced mixer D1032 (HSB88WS),
where it is mixed with the PLL local signal from the
buffer amplifier, Q1029 (2SC2954).
The resulting the RF signal at the transmit frequency is fed through a low-pass filter circuit, and then
is amplified by Q1026 (2SC2714Y) and buffer amplifier Q1025 (2SC3357), and then filtered by one
of eight band-pass filters to suppress out-of-band
responses. The RF signal is then amplified by Q1001
(2SC2954) and delivered to the PA Unit.
7
Circuit Description
On the PA Unit, the low-level RF signal from the
MAIN Unit is amplified by pre-driver Q2001
(RD06HHF1), push-pull driver Q2008/Q2009 (both
RD16HHF1), and push-pull final amplifier Q2012/
Q2013 (both SD1405), which provides up to 120
watts of RF output power.
The RF output from the final amplifier is fed through
the one of seven low-pass filters, sampling directional coupler T2005, and TX/RX relay RL2009 before delivery to the antenna jack.
The sampling directional coupler senses forward
and reverse power output, which is rectified by
D2017 and D2018 (both MA729), respectively, and
the DC voltage is then amplified by Q2015
(LM2904PW) on the PA Unit.
The DC voltages derived from forward and reverse
power are applied to J1003 on the MAIN Unit, and
then amplified by Q1040 (LM2904PW) and Q1044
(2SC2812). The amplified DC voltage is fed back to
the 2nd gate of the 45.275 MHz IF amplifier Q1043
(3SK151GR), so that the transmitter’s IF gain can
be regulated by this sensing of the power output,
preventing overdrive or damage caused by transmission into an excessive impedance mismatch at
the antenna.
PLL Circuit
The PLL local signal for the receiver 1st local and
the transmitter final local is generated by one of two
VCOs: Q1072 or Q1073 (both 2SK210GR) in conjunction with varactor diodes D1047, D1048, D1049,
D1050, D1051, D1052, D1053, and D1054 (all
HVU359) on the MAIN Unit. The oscillating frequency is determined primarily by the level of DC voltage applied to the varactor diodes. The VCO output
is buffered by Q1066 (2SK302Y), amplified by Q1074
(2SC2714Y), and band-pass filtered by capacitors
C1389, C1391, C1397, C1400, C1409, and C1420 and
coils L1070, L1071, L1074, and L1076. The filtered
PLL local signal is fed through buffer amplifiers
Q1027 (2SC2714Y), Q1028 (2SC3356), and Q1029
(2SC2954) to the TX final mixer or RX 1st mixer
D1032 (HSB88WS).
A portion of the output of buffer amplifier Q1066
(2 S K 3 0 2 Y) is further amplified by Q1064
(2SC2714Y), then delivered to the PLL subsystem
8
IC Q1056 (ADF4001BRU), which contains a reference divider, serial-to-parallel data latch, programmable divider, phase comparator and a swallow
counter. The sample VCO signal is divided by the
programmable divider section of the Q1056
(ADF4001BRU). Meanwhile, the output from the
22.625 MHz TCXO reference oscillator, X1003, is
amplified by Q1062 (TC7S04FU) and divided by the
DDS IC Q1060 (AD9833BRM) in accordance with
the PLL dividing data from the main CPU, Q1018
(HD64F2134), then fed through the buffer amplifiers Q1063 (2SC2714Y) to ceramic filter CF1001. The
divided and filtered reference signal is applied to
the reference divider section of the PLL subsystem
IC Q1056 (ADF4001BRU), where it is divided by 25/
26 to produce the loop reference.
The divided signal from the programmable divider
(derived from the VCO), and that derived from the
reference oscillator, are applied to the phase detector section of the PLL subsystem IC Q1056
(ADF4001BRU), which produces a pulsed output
with pulse duration depending on the phase difference between the input signals. This pulse train is
fed through the loop filter, consisting of resistors
R1222, R1233, & R1247 and capacitors C1278, C1284,
C1298, C1308, & C1418, then fed back to the VCO
varactor diodes D1047, D1048, D1049, D1050,
D1051, D1052, D1053, and D1054 (all HVU359).
Changes in the DC voltage applied to these varactor diodes affect the reactance in the tank circuit of
VCOs Q1072 and Q1073 (both 2SK210GR), changing the oscillating frequency according to the phase
difference between the signals derived from the
VCO and the TCXO reference oscillator. The VCO
is thus phase-locked to the reference frequency standard.
A portion of the output of reference signal from
TCXO X1003 is multiplied by four at Q1070
(2SC2714Y). The resulting 90.5 MHz signal is buffered by Q1075 (2SC2714Y), then applied to a lowpass filter, consisting of capacitors C1401, C1405,
C1410, C1411, and C1421 and coils L1075 and L1077.
The filtered reference signal is applied to the TX 1st
mixer Q1054 and RX 2nd mixer Q1052 (both
RF2713).
Circuit Description
Control Circuit
TX/RX Control
Major frequency control functions such as channel
selection, display, and PLL divider control are performed by main CPU Q1018 (HD64F2134) on the
MAIN Unit, at the command of the user via the tuning knob and function switches on the front panel.
When the PTT switch is pressed, pin 21 of the main
CPU Q1018 (HD64F2134) goes low, which causes
pin 60 of the main CPU Q1018 (HD64F2134) to go
low. This signal disables the receiver 12 V bus at
Q1046 (2SA1602A). At the same time, pin 59 of the
main CPU Q1018 (HD64F2134) goes low to activate
the transmit 12 V bus at Q1048 (2SA1365).
The programmable divider data for the PLL from
the main CPU is applied directly to DDS IC Q1016
(AD9833BRM) and PLL subsystem IC Q1056
(ADF4001BRU).
The Mode selection data from the main CPU is also
delivered to DSP IC Q1035 (UPD77115) to control
the various circuits required for the selected mode.
The Band selection binary data from the main CPU
is decoded (BCD to Decimal) by Q1011 (TC4028BF).
The resulting decimal outputs are level-shifted by
Q1003 (TD62783AF) to select the active band-pass
filter on the MAIN Unit required for the operating
frequency. Also, the decimal outputs from Q1003
(TD62783AF) are delivered to PA Unit, where they
are used to select the active low-pass filter required
for the operating frequency.
Power Supply & Regulation
The +5 V bus for the main CPU Q1018 (HD64F2134)
is derived from the 13.5 V bus via regulator Q1012
(BA05FP) on the MAIN Unit. The +8 V bus is derived from the 13.5 V bus via regulator Q1007
(KIA7808API) on the MAIN Unit.
A portion of the +8 V bus is regulated by Q1008
(L78M05T) for the +5 V bus, and is regulated by
Q1006 (UPC2926) for the +2.6 V bus required by the
DSP IC Q1035 (UPD77115GK).
9
Connector Pinout Diagrams
MIC Jack
GPS Jack
(As Viewed From Front Panel)
(As Viewed From Rear Panel)
P ENB
CNTL GND
PTT
MIC
MIC GND
+ 5V
UP
DOWN
Connected with ,
GPS Data Input (+)
N/C
Connected with ,
GPS Data Input (--)
Connected with ,
Connected with ,
Connected with ,
NC
,
, and
.
,
, and
.
,
,
,
, and
, and
, and
.
.
.
Pin 3 PTT Open Circuit Voltage: 5 V, Closed Circuit Current: 1 mA
ACC Jack
TUNE Jack
DATA Jack
(As Viewed From Rear Panel)
(As Viewed From Rear Panel)
(As Viewed From Rear Panel)
+13.8 V OUT
TX GND
GND
BAND DATA A
BAND DATA B
BAND DATA C
BAND DATA D
TX-INH
EXT ALC Input
TX REQ
Pin 1 +13.8 V
Max. 1 A
This terminal is connected
in parallel with the pin 1 of
TUNE Jack.
Pin 2 TX GND Open Collector
(Max. 60 V, 1A)
This terminal is connected
in parallel with the pin 2 of
TUNE Jack.
+13.8 V OUT
TX GND
GND
RX D
TX D
TUNER SENSE
RESET
TX-INH
Pin 1 +13.8 V
Max. 1 A
This terminal is connected
in parallel with the pin 1 of
ACC Jack.
Pin 2 TX GND Open Collector
(Max. 60 V, 1A)
This terminal is connected
in parallel with the pin 2 of
ACC Jack.
DATA IN
GND
DATA PTT
DCD
DATA OUT
SQL OUT
Pin 1 DATA IN
60 mVp-p @1 kΩ.
Pin 5 DATA OUT 500 mVp-p @1 kΩ
Pin 6 SQL OUT
SQL OPEN: 5 V
SQL CLOSE: 0 V
Accessory Port (Located on the MAIN Unit)
ENCR_TXIN
ENCR_RXIN
INDICATOR
CODE (8)
CODE (4)
CODE (2)
CODE (1)
ENCR_RXOUT
CLEAR/SCRAMBLE
PTT
VCC
GND
ENCR_TXOUT
10