S3FM02G
32-Bit CMOS MICROCONTROLLERS
Revision 1.00
January 2011
 2010
Samsung Electronics Co., Ltd. All rights reserved.
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or incidental damages.
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Samsung Electronics Co., Ltd.
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Revision History
Revision No.
Date
1.00
Jan. 10, 2011
Description

Author(s)
Juil. Kim
Table of Contents
1 OVERVIEW ..................................................................................................1-1
1.1 Purpose This Document .......................................................................................................................... 1-1
1.2 Instruction to S3FM02G ........................................................................................................................... 1-1
1.3 Features ................................................................................................................................................... 1-2
1.4 Block Diagram .......................................................................................................................................... 1-6
2 PIN CONFIGURATION ................................................................................2-1
2.1 Pin Configuration...................................................................................................................................... 2-1
2.2 Pin Assignments ...................................................................................................................................... 2-2
2.3 Pin Description ......................................................................................................................................... 2-6
2.3.1 Miscellaneous ................................................................................................................................... 2-6
2.3.2 Clock Manager .................................................................................................................................. 2-6
2.3.3 External Interrupt .............................................................................................................................. 2-6
2.3.4 DEBUG Interface .............................................................................................................................. 2-6
2.3.5 USART Interface............................................................................................................................... 2-7
2.3.6 Encoder Interface ............................................................................................................................. 2-7
2.3.7 IMC Interface .................................................................................................................................... 2-7
2.3.8 TIMER Interface................................................................................................................................ 2-7
2.3.9 PWM Interface .................................................................................................................................. 2-7
2.3.10 I2C Interface ................................................................................................................................... 2-7
2.3.11 CAN Interface ................................................................................................................................. 2-8
2.3.12 SSP Interface.................................................................................................................................. 2-8
2.3.13 LCD Controller Interface ................................................................................................................. 2-8
2.3.14 ADC Interface ................................................................................................................................. 2-8
2.3.15 OP-AMP Interface........................................................................................................................... 2-8
2.3.16 GPIOs ............................................................................................................................................. 2-9
2.3.17 FLASH ............................................................................................................................................ 2-9
2.3.18 Power .............................................................................................................................................. 2-9
3 SYSTEM MEMORY MANAGEMENT ...........................................................3-1
3.1 Default Memory Map ................................................................................................................................ 3-1
3.2 Special Function Register Map ................................................................................................................ 3-2
3.2.1 Core Special Function Register Map ................................................................................................ 3-2
3.2.2 Peripheral Special Function Register Map ....................................................................................... 3-2
4 ELECTRICAL DATA ....................................................................................4-1
4.1 Absolute Maximum Ratings ..................................................................................................................... 4-1
4.2 Recommended Operation Conditions ...................................................................................................... 4-2
4.3 I/O D.C. Characteristics ........................................................................................................................... 4-3
4.4 I/O Capacitance ....................................................................................................................................... 4-4
4.5 RESET Input Characteristics ................................................................................................................... 4-4
4.6 External Interrupt Input Characteristics ................................................................................................... 4-5
4.7 Oscillator Characteristics ......................................................................................................................... 4-6
4.7.1 External Main Clock Oscillator Characteristics ................................................................................. 4-6
4.7.2 External Sub Clock Oscillator Characteristics .................................................................................. 4-6
4.7.3 Internal Main Clock Oscillator Characteristics .................................................................................. 4-7
4.7.4 Internal Sub Clock Oscillator Characteristics ................................................................................... 4-7
4.7.5 PLL Characteristics........................................................................................................................... 4-7
4.8 Current Consumption ............................................................................................................................... 4-8
4.9 LVD Characteristics ............................................................................................................................... 4-14
4.10 12-Bit ADC0 Characteristics ................................................................................................................ 4-15
4.10.1 OP-AMP Characteristics ............................................................................................................... 4-16
4.11 10-Bit ADC1 Characteristics ................................................................................................................ 4-17
4.12 LCD Characteristics ............................................................................................................................. 4-18
4.13 Memory Characteristics ....................................................................................................................... 4-19
4.13.1 Program Flash Memory Characteristics ....................................................................................... 4-19
4.13.2 Data FLASH Memory Characteristics........................................................................................... 4-19
4.14 ESD Characteristics ............................................................................................................................. 4-20
5 PACKAGE SPECIFICATION .......................................................................5-1
5.1 Overview .................................................................................................................................................. 5-1
5.2 Package Dimension ................................................................................................................................. 5-2
List of Figures
Figure
Number
Title
Page
Number
Figure 1-1
S3FM02G Block Diagram ................................................................................................................. 1-6
Figure 2-1
Pin Configuration .............................................................................................................................. 2-1
Figure 4-1
Figure 4-2
Input Timing for nRESET .................................................................................................................. 4-4
Input Timing for External Interrupt .................................................................................................... 4-5
Figure 5-1
128ETQFP-1414 Package Dimension ............................................................................................. 5-2
List of Tables
Table
Number
Title
Page
Number
Table 2-1
Pin Assignments – Pin Number Order ............................................................................................... 2-2
Table 3-1
Table 3-2
Table 3-3
Memory Map ...................................................................................................................................... 3-1
Core Special Function Register Map ................................................................................................. 3-2
Peripheral Memory Map ..................................................................................................................... 3-2
Table 4-1
Table 4-2
Absolute Maximum Ratings ............................................................................................................... 4-1
Recommended Operating Conditions ................................................................................................ 4-2
Table 5-1
Absolute Maximum Ratings ............................................................................................................... 5-1
List of Conventions
Register RW Access Type Conventions
Type
Definition
Description
R
Read Only
The application has permission to read the Register field. Writes to read-only fields
have no effect.
W
Write Only
The application has permission to write in the Register field.
RW
Read & Write
The application has permission to read and writes in the Register field. The
application sets this field by writing 1’b1 and clears it by writing 1’b0.
Register Value Conventions
Expression
Description
x
Undefined bit
X
Undefined multiple bits
?
Undefined, but depends on the device or pin status
Device dependent
Pin value
The value depends on the device
The value depends on the pin status
Reset Value Conventions
Expression
Description
0
1
x
Warning:
Some bits of control registers are driven by hardware or write only. As a result the indicated reset
value and the read value after reset might be different.
S3FM02G_DS_REV 1.00
1
1 OVERVIEW
OVERVIEW
1.1 Purpose This Document
The purpose of this document is to provide a complete reference specification of S3FM02G.
1.2 Instruction to S3FM02G
TM
S3FM02G is a family of cost-effective and high-performance microcontrollers with Cortex -M3 designed by
Advanced RISC Machines (ARM). This Microcontroller unit (MCU) applies to inverter motor control within the
home appliance applications.

ARM Cortex -M3 Core

Built-in up to 384 Kbytes Program Flash Memory

Built-in up to 16 Kbytes Data Flash Memory

Internal up to 24 Kbytes SRAM for stack, data memory, or code memory

Operating temperature: -40 ~ 85 C

Operating voltage range: 2.7 ~ 5.5 V

Interrupt controller: Dynamically reconfigurable Nested Vectored Interrupt Controller (NVIC)

Clock and Power Controller (CM)

10ch x DMA Controller (DMAC)

Watch-Dog Timer (WDT)

8ch x 16-bit Timer/Counters (TC)

32-bit Free-Running Timer (FRT)

8ch x 16-bit PWM

2ch x 16bit Encoder Counter (ENC)

2ch x 6-Phase Inverter Motor Controller (IMC)

2ch x I2C, 2ch x SSP, 2ch x CAN and 4ch x USART

12-bit ADC(4 channels with OP-AMP)

10-bit ADC

5ch OP-AMP

4com x 40seg LCD Controller (LCDC)

Support Normal, High-speed, IDLE, and STOP mode
TM
1-1
S3FM02G_DS_REV 1.00
1 OVERVIEW
1.3 Features






CPU

32-bit RISC ARM Cortex -M3 Core

ETM function embedded with ARM Cortex -M3

SWD(Serial Wire Debug) and JTAG Debugging Solution
TM
TM
Memory

Up to 384 Kbytes Internal Program Full Flash

Up to 16 Kbytes Internal Data Flash

Up to 24 Kbytes Internal SRAM

Only little-endian support
Interrupt Controller

Supports Nested Vectored Interrupt Controller of Cortex -M3

Dynamically reconfigurable Interrupt Priority (16 priority levels)
TM
Clock Manager (CM)

External Oscillator 4 ~ 8MHz (EMCLK: External Main Clock) and 32.768KHz (ESCLK: External SubClock)

Internal Oscillator 8/16/20MHz (IMCLK: Internal Main Clock) and 32.768KHz (ISCLK: Internal Sub-Clock)

Up to 75MHz by Phase-Locked Loop Control (PLL)

Clock Monitor to detect an external main and sub-oscillator failure

Support Low Power Mode (IDLE / STOP) by Clock Gating Control

Programmable Clock Dividers (SDIV, PDIV)

Reset Management

Include basic timer for reset generation and STOP wake-up
DMAC: Direct Memory Access Controller

Up to 10 channels

Transfer from Memory to Memory

Transfer between Peripheral and Memory

Transfer between Peripheral and Peripheral
WDT: Watchdog Timer

Configurable micro-controller reset event

Programmable 16-bit down counter
1-2
S3FM02G_DS_REV 1.00






1 OVERVIEW
TC: 16-bit Timer/Counter

Up to 8 channels (TC0 ~ TC7)

Operation in an interval, capture, match & overflow, or PWM mode

Match and overflow interrupt

Selectable an internal or external timer clock
FRT: Free Running Timer

32-bit Timer

Can operate in stop mode with ISCLK, as an independent timer
PWM: Pulse Width Modulation

Up to 8 channels

16-bit PWM signal generation

Interval Mode

Programmable Idle Level

Support extension PWM function
ENC: Encoder Counter

Up to 2 channels

3 input signals: PHASEA, PHASEB, and PHASEZ

Support position counter and speed counter

Up/Down counter

Support capture mode
IMC: Inverter Motor Controller

UP to 2 channels

Support 3-Phase 16-bit PWM generation

Programmable dead time insertion

ADC conversion start signal generation
CAN: Controller Area Network

CAN0/1 With 32 Buffers

Support CAN 2.0A and 2.0B Full Speed

Stampable Message
1-3
S3FM02G_DS_REV 1.00





1 OVERVIEW
USART: Universal Sync/Async Receiver Transmitter

Up to 4 channels

Support 5, 6, 7, and 8bit Data length

Programmable baud rate generator

Parity, framing and overrun error detection

Support loop-back mode

Support full duplex

Idle flag for J1587 protocol

Support LIN protocol: LIN1.2 or LIN 2.0 configurable release

Smart-card protocol: Error signaling and re-transmission

Dedicated DMA channel
SSP: Serial Synchronous Peripheral Interface

Up to 2 channels

Programmable data frame from 4 to 16-bit

Support Master and Slave Mode

Programmable Clock Pre-scale

Separate 16 x 32-bit width Transmit/Receive FIFO

Dedicated DMA channel
IIC: Inter-Integrated Circuit

Up to 2 channels

Multi-Master IIC-Bus

Serial, 8-bit Oriented and Bi-directional Data Transfers

100Kbit/s in Standard Mode and up to 400Kbit/s in Fast mode

Dedicated DMA channel
ADC: A/D Converters

Up to 16 channel’s Analog Inputs

12-bit ADC0 x 2 and 10-bit ADC1

4 x Op-amp for 12-bit ADC input level amplification

supports simultaneous sampling and conversion up to 2-input channels

Dedicated DMA channel
OP amp

5 ch OP amp

Can be operated with ADC

Edge detection function which is related with IMC
1-4
S3FM02G_DS_REV 1.00



LCDC: LCD Controller

4 com x 40 segment

Static, 1/2 and 1/3 bias mode

External and internal resistor bias
General Purpose IO (GPIO)

Disabling IO port enables the function of peripherals on pins

Output Open-drain / Push-pull configuration

Input Pull-up Resistor enable/disable configuration

GPIO Interrupt
Two Low Power Modes

IDLE: Only CPU clock stops

STOP: Selected system clock and CPU clock stop

Fast wake-up with internal 8/16/20MHz oscillator (from STOP mode to normal mode)

Programmable external event/interrupt sources for Wake-up

POR: Power-On Reset

LVD: Low Voltage Detection



LVD for reset with configurable voltage levels

LVD for interrupt with configurable voltage levels
PLL: Phase-Locked Loop

Input Frequency: 4 ~ 8 MHz

Output Frequency: 8 ~ 75MHz
Operating Voltage Range



2.7V ~ 5.5V
Operating Frequency Range

4 ~ 8 MHz by external main oscillator clock

8/16/20MHz by internal main oscillator clock

32.768KHz external/internal sub-oscillator clock

8 ~ 75 MHz by PLL clock
Operating Temperature Range


1 OVERVIEW
-40 ~ 85 C
Available in 128 ETQFP Package
1-5
S3FM02G_DS_REV 1.00
1 OVERVIEW
1.4 Block Diagram
Interrupts
NMI
INTNMI
sleep
CM3
Core
debug
E
T
M
Inst
Systick
DWP
ITM
T
P
I
U
Cortex-M3
APB
S-BUS
AHB-AP
D-Code
S
W
J
D
P
JTAG/SWDBG
Data
From CM
I-Code
I/O conf
INTISR
GPIO
Cortex-M3
N
V
I
V
APB
AHB Bus Matrix
Program Flash
384KB
Data Flash
16KB
PF Controller
DF Controller
PLL
CM
IVC Controller
IMOSC16
PLLCLK (8 ~ 75MHz)
EMCLK (4 ~ 8MHz)
12-BIT
ADC0
12-BIT
ADC0
10-BIT
ADC0
5ch
OP-AMP
IMCLK (8/16/20MHz)
ESCLK (32.768KHz)
ISOSC
DMA
Con.
SRAM Controller
IMOSC20
IVC
SRAM
24KB
AHB2APB
ADC 0/1
Controller
ISCLK (32.768KHz)
OP-AMP
Controller
WDT
2ch SSP
2ch IMC
8ch PWM
2ch ENC
4ch USART
2ch CAN
4 com x 40 seg
LCD Controller
Figure 1-1
STT
S3FM02G Block Diagram
1-6
GPIO
I/O conf
GPIO
2ch I2C
8-ch
Timer/Counter
I/O conf
FRT
S3FM02G_DS_REV 1.00
2
2 PIN CONFIGURATION
PIN CONFIGURATION
P3.4/TRACEDCLK
P3.3/TRACED0
P3.2/TRACED1
P3.1/TRACED2
P3.0/TRACED3
P2.27/SDA1/EXI13
P2.26/SCL1/EXI12
P2.25/PHASEZ0
P2.24/PHASEB0
P2.23/PHASEA0
P2.22/PWM0D2
P2.21/PWM0U2
P2.20/PWM0D1
P2.19/PWM0U1
P2.18/PWM0D0
P2.17/PWM0U0
P2.16/PWM0OFF
VSS4
VDDIO4
P2.15/AIN08/OP4_P/EXI11
P2.14/AIN07/OP4_N/EXI10
P2.13/AIN06/OP4_O/EXI9
P2.12/AIN05
P2.11/AIN04
P2.10/AIN03
P2.9/AIN02
P2.8/AIN01
AVREF0
AVDD0
AVSS0
AVDD1
AVSS1
128
127
126
125
124
123
122
121
120
119
118
117
116
115
114
113
112
111
110
109
108
107
106
105
104
103
102
101
100
99
98
97
2.1 Pin Configuration
nTRST/P3.5
1
96
AVREF1
TDO_TRACESWO/P3.6
2
95
P2.7/AIN17
TDI/P3.7
3
94
P2.6/AIN16
TMS_SWDIO/P3.8
4
93
P2.5/AIN15
TCK_SWCLK/P3.9
5
92
P2.4/AIN14
IVCOUT2
6
91
P2.3/AIN13
(for PLL IVC) VDDCORE2
7
90
P2.2/AIN12/OP3_P
VSS1
8
89
P2.1/AIN11/OP3_N/EXI8
nRESET
9
88
P2.0/AIN10/OP3_O/EXI7
XOUT
10
87
P1.31/OP2_P/USARTTXD0
XIN
11
86
P1.30/OP2_N/USARTRXD0
MODE0
12
85
P1.29/OP2_O/USARTCLK0/ADTRG1
XTIN
13
84
P1.28/OP1_P/CANTX0/SSPFSS1
XTOUT
14
83
P1.27/OP1_N/CANRX0/SSPCLK1
MODE1
15
82
P1.26/OP1_O/SCL0/SSPMISO1
MODE2
16
F_SDAT 81
P1.25/OP0_P/SDA0/SSPMOSI1
(for main IVC) VDDCORE1
17
F_SCLK 80
P1.24/OP0_N/USARTTXD1
IVCOUT1
18
79
P1.23/OP0_O/USARTRXD1
VDDIO1
19
78
VSS3
USARTRXD0/CLKOUT/VLCD1/P0.0
20
77
VDDIO3
USARTTXD0/VLCD2/P0.1
21
76
P1.22/ADTRG0/EXI6
USARTCLK0/TCAP7/VLCD3/P0.2
22
75
P1.21/PWM1OFF
EXI14/TPWM7/COM0/P0.3
23
74
P1.20/PWM1U0
EXI15/TCAP6/COM1/P0.4
24
73
P1.19/PWM1D0
TPWM6/COM2/P0.5
25
72
P1.18/PWM1U1
TCAP5/COM3/P0.6
26
71
P1.17/PWM1D1
ADTRG1/TPWM5/SEG0/P0.7
27
70
P1.16/PWM1U2
SSPFSS0/TCAP4/SEG1/P0.8
28
69
P1.15/PWM1D2
SSPCLK0/TPWM4/SEG2/P0.9
29
68
P1.14/SEG39/USARTCLK1/NMI
SSPMISO0/TCLK7/SEG3/P0.10
30
67
P1.13/SEG38/TPWM0/PWM7
SSPMOSI0/TCLK6/SEG4/P0.11
31
66
P1.12/SEG37/TCAP0/PWM6
EXI0/TCLK5/SEG5/P0.12
32
65
P1.11/SEG36/TCLK0/PWM5
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
USARTTXD3/SEG21/P0.28
PHASEA1/SEG22/P0.29
PHASEB1/SEG23/P0.30
PHASEZ1/SEG24/P0.31
SSPMOSI1/SEG25/P1.0
SSPMISO1/SEG26/P1.1
SSPCLK1/SEG27/P1.2
SSPFSS1/SEG28/P1.3
SSPMOSI0/SCL1/SEG29/P1.4
SSPMISO0/SDA1/SEG30/P1.5
SSPCLK0/CANRX1/SEG31//P1.6
SSPFSS0/CANTX1/SEG32/P1.7
EXI5/USARTCLK2/SEG33/P1.8
PWM3/USARTRXD2/SEG34/P1.9
PWM4/USARTTXD2/SEG35/P1.10
48
EXI4/USARTCLK3/SEG19/P0.26
49
47
VSS2
Figure 2-1
USARTRXD3/SEG20/P0.27
46
VDDIO2
41
USARTRXD1/TCAP1/SEG14/P0.21
45
40
USARTCLK1/TCLK1/SEG13/P0.20
PWM2/SEG18/P0.25
39
CANRX0/TPWM2/SEG12/P0.19
44
38
CANTX0/TCAP2/SEG11/P0.18
PWM1/SEG17/P0.24
37
EXI3/TCLK2/SEG10/P0.17
43
36
EXI2/TCLK3/SEG9/P0.16
PWM0/SEG16/P0.23
35
SDA0/TPWM3/SEG8/P0.15
42
34
USARTTXD1/TPWM1/SEG15/P0.22
33
EXI1/TCLK4/SEG6/P0.13
SCL0/TCAP3/SEG7/P0.14
S3FM02G
(128-ETQFP-1414)
Pin Configuration
2-1
S3FM02G_DS_REV 1.00
2 PIN CONFIGURATION
2.2 Pin Assignments

D: Digital, A: Analog

IO: Input and Output (Bi-direction), O: Output, I: Input, P: Power, G: Ground
Table 2-1
Pin Assignments – Pin Number Order
PIN Name
PULL
up/dn
@RESET
I/O state
@RESET
PULL-UP
I
–
O
1st
2nd
3rd
4th
Default
@RESET
1
P3.5
nTRST
–
–
nTRST
2
P3.6
TDO/TRACESWO
–
–
3
P3.7
TDI
–
–
TDI
PULL-UP
I
4
P3.8
TMS/SWDIO
–
–
TMS/SWDIO
PULL-UP
I
5
P3.9
TCK/SWCLK
–
–
TCK/SWCLK
PULL-UP
I
6
IVCOUT2
IVCOUT2
IVCOUT2
IVCOUT2
IVCOUT2
–
O
7
VDDCORE2
VDDCORE2
VDDCORE2
VDDCORE2
VDDCORE2
–
P
8
VSS1
VSS1
VSS1
VSS1
VSS1
–
G
9
nRESET
nRESET
nRESET
nRESET
nRESET
PULL-UP
I
10
XOUT
XOUT
XOUT
XOUT
XOUT
–
O
11
XIN
XIN
XIN
XIN
XIN
–
I
12
MODE0
MODE0
MODE0
MODE0
MODE0
PULL-DN
I
13
XTIN
XTIN
XTIN
XTIN
XTIN
–
I
14
XTOUT
XTOUT
XTOUT
XTOUT
XTOUT
–
O
15
MODE1
MODE1
MODE1
MODE1
MODE1
PULL-DN
I
16
MODE2
MODE2
MODE2
MODE2
MODE2
PULL-DN
I
17
VDDCORE1
VDDCORE1
VDDCORE1
VDDCORE1
VDDCORE1
–
P
18
IVCOUT1
IVCOUT1
IVCOUT1
IVCOUT1
IVCOUT1
–
O
19
VDDIO1
VDDIO1
VDDIO1
VDDIO1
VDDIO1
–
P
20
P0.0
VLCD1
CLKOUT
USARTRXD0
P0.0
–
I
21
P0.1
VLCD2
–
USARTTXD0
P0.1
–
I
22
P0.2
VLCD3
TCAP7
USARTCLK0
P0.2
–
I
23
P0.3
COM0
TPWM7
EXI14
P0.3
–
I
24
P0.4
COM1
TCAP6
EXI15
P0.4
–
I
25
P0.5
COM2
TPWM6
–
P0.5
–
I
26
P0.6
COM3
TCAP5
–
P0.6
–
I
27
P0.7
SEG0
TPWM5
ADTRG1
P0.7
–
I
28
P0.8
SEG1
TCAP4
SSPFSS0
P0.8
–
I
29
P0.9
SEG2
TPWM4
SSPCLK0
P0.9
–
I
Num
2-2
TDO/
TRACESWO
S3FM02G_DS_REV 1.00
2 PIN CONFIGURATION
PIN Name
PULL
up/dn
@RESET
I/O state
@RESET
1st
2nd
3rd
4th
Default
@RESET
30
P0.10
SEG3
TCLK7
SSPMISO0
P0.10
–
I
31
P0.11
SEG4
TCLK6
SSPMOSI0
P0.11
–
I
32
P0.12
SEG5
TCLK5
EXI0
P0.12
–
I
33
P0.13
SEG6
TCLK4
EXI1
P0.13
–
I
34
P0.14
SEG7
TCAP3
SCL0
P0.14
–
I
35
P0.15
SEG8
TPWM3
SDA0
P0.15
–
I
36
P0.16
SEG9
TCLK3
EXI2
P0.16
–
I
37
P0.17
SEG10
TCLK2
EXI3
P0.17
–
I
38
P0.18
SEG11
TCAP2
CANTX0
P0.18
–
I
39
P0.19
SEG12
TPWM2
CANRX0
P0.19
–
I
40
P0.20
SEG13
TCLK1
USARTCLK1
P0.20
–
I
41
P0.21
SEG14
TCAP1
USARTRXD1
P0.21
–
I
42
P0.22
SEG15
TPWM1
USARTTXD1
P0.22
–
I
43
P0.23
SEG16
PWM0
–
P0.23
–
I
44
P0.24
SEG17
PWM1
–
P0.24
–
I
45
P0.25
SEG18
PWM2
–
P0.25
–
I
46
VDDIO2
VDDIO2
VDDIO2
VDDIO2
VDDIO2
–
P
47
VSS2
VSS2
VSS2
VSS2
VSS2
–
G
48
P0.26
SEG19
USARTCLK3
EXI4
P0.26
–
I
49
P0.27
SEG20
USARTRXD3
–
P0.27
–
I
50
P0.28
SEG21
USARTTXD3
–
P0.28
–
I
51
P0.29
SEG22
PHASEA1
–
P0.29
–
I
52
P0.30
SEG23
PHASEB1
–
P0.30
–
I
53
P0.31
SEG24
PHASEZ1
–
P0.31
–
I
54
P1.0
SEG25
SSPMOSI1
–
P1.0
–
I
55
P1.1
SEG26
SSPMISO1
–
P1.1
–
I
56
P1.2
SEG27
SSPCLK1
–
P1.2
–
I
57
P1.3
SEG28
SSPFSS1
–
P1.3
–
I
58
P1.4
SEG29
SCL1
SSPMOSI0
P1.4
–
I
59
P1.5
SEG30
SDA1
SSPMISO0
P1.5
–
I
60
P1.6
SEG31
CANRX1
SSPCLK0
P1.6
–
I
61
P1.7
SEG32
CANTX1
SSPFSS0
P1.7
–
I
62
P1.8
SEG33
USARTCLK2
EXI5
P1.8
–
I
63
P1.9
SEG34
USARTRXD2
PWM3
P1.9
–
I
64
P1.10
SEG35
USARTTXD2
PWM4
P1.10
–
I
Num
2-3
S3FM02G_DS_REV 1.00
2 PIN CONFIGURATION
PIN Name
PULL
up/dn
@RESET
I/O state
@RESET
1st
2nd
3rd
4th
Default
@RESET
65
P1.11
SEG36
TCLK0
PWM5
P1.11
–
I
66
P1.12
SEG37
TCAP0
PWM6
P1.12
–
I
67
P1.13
SEG38
TPWM0
PWM7
P1.13
–
I
68
P1.14
SEG39
USARTCLK1
NMI
P1.14
–
I
69
P1.15
PWM1D2
–
–
P1.15
–
I
70
P1.16
PWM1U2
–
–
P1.16
–
I
71
P1.17
PWM1D1
–
–
P1.17
–
I
72
P1.18
PWM1U1
–
–
P1.18
–
I
73
P1.19
PWM1D0
–
–
P1.19
–
I
74
P1.20
PWM1U0
–
–
P1.20
–
I
75
P1.21
PWM1OFF
–
–
P1.21
–
I
76
P1.22
ADTRG0
EXI6
–
P1.22
–
I
77
VDDIO3
VDDIO3
VDDIO3
VDDIO3
VDDIO3
–
P
78
VSS3
VSS3
VSS3
VSS3
VSS3
–
G
79
P1.23
OP0_O
USARTRXD1
–
P1.23
–
I
80
P1.24
OP0_N
USARTTXD1
–
P1.24
–
I
81
P1.25
OP0_P
SDA0
SSPMOSI1
P1.25
–
I
82
P1.26
OP1_O
SCL0
SSPMISO1
P1.26
–
I
83
P1.27
OP1_N
CANRX0
SSPCLK1
P1.27
–
I
84
P1.28
OP1_P
CANTX0
SSPFSS1
P1.28
–
I
85
P1.29
OP2_O
USARTCLK0
ADTRG1
P1.29
–
I
86
P1.30
OP2_N
USARTRXD0
–
P1.30
–
I
87
P1.31
OP2_P
USARTXD0
–
P1.31
–
I
88
P2.0
AIN10
OP3_O
EXI7
P2.0
–
I
89
P2.1
AIN11
OP3_N
EXI8
P2.1
–
I
90
P2.2
AIN12
OP3_P
–
P2.2
–
I
91
P2.3
AIN13
–
–
P2.3
–
I
92
P2.4
AIN14
–
–
P2.4
–
I
93
P2.5
AIN15
–
–
P2.5
–
I
94
P2.6
AIN16
–
–
P2.6
–
I
95
P2.7
AIN17
–
–
P2.7
–
I
96
AVREF1
AVREF1
AVREF1
AVREF1
AVREF1
–
I
97
AVSS1
AVSS1
AVSS1
AVSS1
AVSS1
–
G
98
AVDD1
AVDD1
AVDD1
AVDD1
AVDD1
–
P
99
AVSS0
AVSS0
AVSS0
AVSS0
AVSS0
–
G
Num
2-4
S3FM02G_DS_REV 1.00
2 PIN CONFIGURATION
PIN Name
PULL
up/dn
@RESET
I/O state
@RESET
1st
2nd
3rd
4th
Default
@RESET
100
AVDD0
AVDD0
AVDD0
AVDD0
AVDD0
–
P
101
AVREF0
AVREF0
AVREF0
AVREF0
AVREF0
–
I
102
P2.8
AIN01
–
–
P2.8
–
I
103
P2.9
AIN02
–
–
P2.9
–
I
104
P2.10
AIN03
–
–
P2.10
–
I
105
P2.11
AIN04
–
–
P2.11
–
I
106
P2.12
AIN05
–
–
P2.12
–
I
107
P2.13
AIN06
OP4_O
EXI9
P2.13
–
I
108
P2.14
AIN07
OP4_N
EXI10
P2.14
–
I
109
P2.15
AIN08
OP4_P
EXI11
P2.15
–
I
110
VDDIO4
VDDIO4
VDDIO4
VDDIO4
VDDIO4
–
P
111
VSS4
VSS4
VSS4
VSS4
VSS4
–
G
112
P2.16
PWM0OFF
–
–
P2.16
–
I
113
P2.17
PWM0U0
–
–
P2.17
–
I
114
P2.18
PWM0D0
–
–
P2.18
–
I
115
P2.19
PWM0U1
–
–
P2.19
–
I
116
P2.20
PWM0D1
–
–
P2.20
–
I
117
P2.21
PWM0U2
–
–
P2.21
–
I
118
P2.22
PWM0D2
–
–
P2.22
–
I
119
P2.23
PHASEA0
–
–
P2.23
–
I
120
P2.24
PHASEB0
–
–
P2.24
–
I
121
P2.25
PHASEZ0
–
–
P2.25
–
I
122
P2.26
SCL1
EXI12
–
P2.26
–
I
123
P2.27
SDA1
EXI13
–
P2.27
–
I
124
P3.0
TRACED3
–
–
P3.0
–
I
125
P3.1
TRACED2
–
–
P3.1
–
I
126
P3.2
TRACED1
–
–
P3.2
–
I
127
P3.3
TRACED0
–
–
P3.3
–
I
128
P3.4
TRACECLK
–
–
P3.4
–
I
Num
2-5
S3FM02G_DS_REV 1.00
2 PIN CONFIGURATION
2.3 Pin Description

D: Digital, A: Analog

IO: Input and Output (Bi-direction), O: Output, I: Input, P: Power, G: Ground
2.3.1 Miscellaneous
Name
I/O
Description
D/A
nRESET
I
Chip Reset Signal (active “Low”)
This nRESET pin contains an internal pull up resistor 250. Setting this pin to
low level initialize the internal state of the device. Thereafter, setting the
input to high release the reset status. The S3FM02G waits for the system
clock to be stable, and the PC to the reset interrupt vector. Internal Reset is
generated after clock stabilization.
D
MODE[2:0]
I
Factory test input pins. This pins should be connected to Ground
D
2.3.2 Clock Manager
Name
I/O
Description
D/A
XIN
I
External Main Oscillator Input (4MHz ~ 8MHz)
A
XOUT
O
External Main Oscillator Output
A
XTIN
I
External Sub-Oscillator Input (32.768KHz)
A
XTOUT
O
External Sub-Oscillator Output.
A
CLKOUT
O
Internal Clock Output signals.
D
2.3.3 External Interrupt
Name
EXI0 ~ EXI15
I/O
I
Description
External interrupt/wakeup input pins
D/A
D
2.3.4 DEBUG Interface
Name
I/O
Description
D/A
TCK/SWCLK
I
JTAG Test Clock/ Serial Wire Clock, Pull-up
D
TMS/SWDIO
I
JTAG Test Mode Select/ Serial Wire Data Input Output, Pull-up
D
TDI
I
JTAG Test Data Input, Pull-up
D
TDO/TRACESWO
O
JTAG Test Data Out / Trace Serial Wire Viewer Data
D
nTRST
I
JTAG Test nRESET, Pull-up
D
TRACECLK
O
Trace Clock
D
TRACED[3:0]
O
Trace Data
D
2-6
S3FM02G_DS_REV 1.00
2 PIN CONFIGURATION
2.3.5 USART Interface
Name
I/O
USARTCLK[3:0]
IO
USARTRXD[3:0]
USARTTXD[3:0]
Description
D/A
External Clock Signal Input / Internal Clock Signal Output
D
I
Receive Data Input
D
O
Transmit Data Output
D
2.3.6 Encoder Interface
Name
I/O
Description
D/A
PHASEA[1:0]
I
Phase A input pin
D
PHASEB[1:0]
I
Phase B input pin
D
PHASEZ[1:0]
I
Phase Z input pin
D
2.3.7 IMC Interface
Name
I/O
Description
D/A
PWM[1:0]U[2:0]
O
PWM output for inverter motor
D
PWM[1:0]D[2:0]
O
PWM output for inverter motor
D
PWM[1:0]OFF
I
Input pin for PWM output off
D
2.3.8 TIMER Interface
Name
I/O
Description
D/A
TCLK[7:0]
I
External Clock Input
D
TCAP[7:0]
I
External Capture Input
D
TPWM[7:0]
O
PWM Output
D
2.3.9 PWM Interface
Name
PWM[7:0]
I/O
O
Description
Pulse width modulation output
D/A
D
2.3.10 I2C Interface
Name
I/O
Description
D/A
SCL[1:0]
IO
Serial Clock
D
SDA[1:0]
IO
Serial Data
D
2-7
S3FM02G_DS_REV 1.00
2 PIN CONFIGURATION
2.3.11 CAN Interface
Name
I/O
Description
D/A
CANTX[1:0]
O
Transmit Data Output
D
CANRX[1:0]
I
Receive Data Input
D
2.3.12 SSP Interface
Name
I/O
Description
D/A
SSPCLK[1:0]
IO
SSP Master Clock Output / Slave Clock Input
D
SSPMISO[1:0]
IO
SSP Master Input / Slave Output
D
SSPMOSI[1:0]
IO
SSP Master Output / Slave Input
D
SSPFSS[1:0]
IO
SSP Master Chip Select Output / Slave Chip Select Input
D
2.3.13 LCD Controller Interface
Name
I/O
Description
D/A
VLCD[3:1]
P
LCD Power Supply
D
COM[3:0]
O
COM drive signal
D
SEG[39:0]
O
SEG drive signal
D
2.3.14 ADC Interface
Name
I/O
Description
D/A
AIN0[8:1]
I
Analog Input pins for 8-channels
A
AIN1[7:0]
I
Analog Input pins for 8-channels
A
ADTRG[1:0]
I
ADC External Trigger Input pin
D
AVREF[1:0]
I
ADC Reference Top Voltage.
A
2.3.15 OP-AMP Interface
Name
I/O
Description
D/A
OP[4:0]_O
O
OP-AMP Output
A
OP[4:0]_N
I
OP-AMP N Input
A
OP[4:0]_P
I
OP-AMP P Input
A
2-8
S3FM02G_DS_REV 1.00
2 PIN CONFIGURATION
2.3.16 GPIOs
Name
I/O
Description
D/A
P0[31:0]
IO
General Purpose I/O port 0
D
P1[31:0]
IO
General Purpose I/O port 1
D
P2[27:0]
IO
General Purpose I/O port 2
D
P3[9:0]
IO
General Purpose I/O port 3
D
2.3.17 FLASH
Name
I/O
F_SDAT
IO
F_SCLK
I
Description
D/A
Serial Data pin (Output when reading, Input when writing)
D
Serial Clock
D
2.3.18 Power
Name
I/O
Description
VDDCORE[2:1]
P
Digital Power for interval IVC (2.7V ~ 5.5V)
VDDIO[4:1]
P
Digital IO Power 2.7 V ~ 5.5V
VSS[4:1]
G
Digital Ground
IVCOUT[2:1]
P
Cap Output port from internal Regulators (connect to GND through a 1uF capacitor)
AVDD[1:0]
P
Analog Power
AVSS[1:0]
G
Analog Ground
MODE2
MODE1
MODE0
Mode Description
0
0
0
User Normal/Debug Mode
0
0
1
User Flash Writing Tool Mode
0
1
0
User UART SPGM Tool Mode
1
0
1
SCAN Mode (Only for Test)
2-9
S3FM02G_DS_REV 1.00
3
3 SYSTEM MEMORY MANAGEMENT
SYSTEM MEMORY MANAGEMENT
3.1 Default Memory Map
The S3FM02G has memory space allocation as below.
Table 3-1
Memory Map
Address
Memory
Reserved
Reserved
0xE00F_FFFF
~
0xE000_0000
Cortex -M3 Internal Peripheral Registers
Reserved
Reserved
0x8000_3FFF
~
0x8000_0000
16 Kbytes Internal Data Flash Memory
Reserved
Reserved
0x400F_FFFF
~
0x4000_0000
Special Function Registers
Reserved
Reserved
0x2000_5FFF
~
0x2000_0000
24 Kbytes Internal SRAM Memory
Reserved
Reserved
0x0005_FFFF
~
0x0000_0000
384 Kbytes Internal Program Flash Memory
TM
3-1
S3FM02G_DS_REV 1.00
3 SYSTEM MEMORY MANAGEMENT
3.2 Special Function Register Map
3.2.1 Core Special Function Register Map
Table 3-2
Core Special Function Register Map
Base Address
Peripheral
Description
0xE00F_F000
ROM Table
0xE004_2000
External PPB
0xE004_1000
ETM
Embedded Trace Macro Register
0xE004_0000
TPIU
Trace Port Interface
0xE000_F000
Reserved
0xE000_E000
SCS
0xE000_3000
Reserved
0xE000_2000
FPB
Flash Patch & Break Pint
0xE000_1000
DWT
Data Watch Point & Trace
0xE000_0000
ITM
Instrumentation Trace Macro-cell
ROM memory table
Private Peripheral Bus
–
System Control Space
–
3.2.2 Peripheral Special Function Register Map
Table 3-3
Peripheral Memory Map
Peripheral Group
Base Address
Peripheral
DMAC
0x400F_0000
DMAC
Direct Memory Access Controller
0x400E_1000
CAN1
Controller Area Network 1
0x400E_0000
CAN0
Controller Area Network 0
0x400D_0000
LCDC
LCD Controller
0x400C_1000
ENC1
Encoder Counter 1
0x400C_0000
ENC0
Encoder Counter 0
0x400B_1000
IMC1
Inverter Motor Controller1
0x400B_0000
IMC0
Inverter Motor Controller0
0x400A_1000
I2C1
Inter-Integrated Circuit 1
0x400A_0000
I2C0
Inter-Integrated Circuit 0
0x4009_1000
SSP1
Synchronous Serial Port 1
0x4009_0000
SSP0
Synchronous Serial Port 0
0x4008_3000
USART3
Universal Sync/Async Receiver/Transmitter 3
0x4008_2000
USART2
Universal Sync/Async Receiver/Transmitter 2
0x4008_1000
USART1
Universal Sync/Async Receiver/Transmitter 1
0x4008_0000
USART0
Universal Sync/Async Receiver/Transmitter 0
STT
0x4007_8000
STT
PWM
0x4007_7000
PWM7
CAN
LCDC
ENC
IMC
I2C
SSP
USART
Description
Stamp Timer
Pulse Width Modulation 7 (16bit)
3-2
S3FM02G_DS_REV 1.00
Peripheral Group
3 SYSTEM MEMORY MANAGEMENT
Base Address
Peripheral
0x4007_6000
PWM6
Pulse Width Modulation 6 (16bit)
0x4007_5000
PWM5
Pulse Width Modulation 5 (16bit)
0x4007_4000
PWM4
Pulse Width Modulation 4 (16bit)
0x4007_3000
PWM3
Pulse Width Modulation 3 (16bit)
0x4007_2000
PWM2
Pulse Width Modulation 2 (16bit)
0x4007_1000
PWM1
Pulse Width Modulation 1 (16bit)
0x4007_0000
PWM0
Pulse Width Modulation 0 (16bit)
0x4006_7000
TC7
Timer/Counter 7 (16bit)
0x4006_6000
TC6
Timer/Counter 6 (16bit)
0x4006_5000
TC5
Timer/Counter 5 (16bit)
0x4006_4000
TC4
Timer/Counter 4 (16bit)
0x4006_3000
TC3
Timer/Counter 3 (16bit)
0x4006_2000
TC2
Timer/Counter 2 (16bit)
0x4006_1000
TC1
Timer/Counter 1 (16bit)
0x4006_0000
TC0
Timer/Counter 0 (16bit)
0x4005_8000
IOCONF
0x4005_3000
GPIO3
General Purpose IO Group 3
0x4005_2000
GPIO2
General Purpose IO Group 2
0x4005_1000
GPIO1
General Purpose IO Group 1
0x4005_0000
GPIO0
General Purpose IO Group 0
0x4004_2000
OPAMP
OP-AMP
0x4004_1000
ADC1
Analog to Digital Converter 1 (10bit)
0x4004_0000
ADC0
Analog to Digital Converter 0 (12bit)
FRT
0x4003_1000
FRT
Free Running Timer (32bit)
WDT
0x4003_0000
WDT
Watchdog Timer
SYSTEM
0x4002_0000
CM
System(Clock, Reset and Power) Manager
0x4001_1000
DFC
Data Flash Controller
0x4001_0000
PFC
Program Flash Controller
0x4000_0000
–
TIMER/ Counter
GPIO
OPAMP
ADC
MEMORY
SFM
Description
IO Configuration
Device information including Chip ID
3-3
S3FM02G_DS_REV 1.00
4
4 ELECTRICAL DATA
ELECTRICAL DATA
4.1 Absolute Maximum Ratings
Stresses above those listed in "Absolute Maximum Ratings" may cause permanent damage to the device. The
functional operation of the device at these conditions is not implied. Exposure to maximum rating conditions for
extended periods may affect device reliability.
Table 4-1
Parameter
Absolute Maximum Ratings
Symbol
Conditions
Rating
Unit
VDDCORE
–
–0.3 to 6.0
V
DC Supply Voltage for VDDIO
VDDIO
–
–0.3 to 6.0
V
DC Supply Voltage for AVDD
AVDD
–
–0.3 to 6.0
V
DC Supply Voltage for AVREF
AVREF
–
–0.3 to 6.0
V
Digital I/O Input Voltage
VIN
–
–0.3 to VDDIO+0.3
V
Analog I/O Input Voltage
AVIN
–
–0.3 to AVDD+0.3
V
IIN_D
All Input Pins
–
mA
–
Per Pin
–
mA
IIN_A
All Input Pins
–
mA
Per Pin
–
mA
IO_LOW
All Output Pins
–
mA
–
Per Pin
–
mA
IO_HIGH
All Output Pins
–
mA
–
Per Pin
–
mA
Output Voltage
VO
All Output Pins
–0.3 to VDDIO+0.3
V
Operating Temperature
TA
–
–40 to 85
C
TSTG
–
–65 to 155
C
DC Supply Voltage for VDDCORE
DC Digital Input Current
DC Analog Input Current
Output Current Low
Output Current High
Storage Temperature
NOTE: The device is not guaranteed to operate properly above those listed in 'Absolute Maximum Ratings'.
4-1
S3FM02G_DS_REV 1.00
4 ELECTRICAL DATA
4.2 Recommended Operation Conditions
The recommended operating conditions are required in order to ensure the normal operation of the semiconductor
device. All of the device’s electrical characteristics are warranted when the device is operated within these ranges.
Always use semiconductor devices within their recommended operating condition ranges. Operation outside these
ranges may adversely affect reliability and could result in device failure.
Table 4-2
Parameter
Recommended Operating Conditions
Symbol
Conditions
Rating
Unit
VDDCORE
–
2.7 to 5.5
V
DC Supply Voltage for I/O
VDDIO
–
2.7 to 5.5
V
DC Supply Voltage for AVDD
AVDD
–
2.7 to 5.5
V
DC Supply Voltage for AVREF
AVREF
–
0.0 to 5.5
V
TA
–
–40 to 85
C
DC Supply Voltage for VDD Core
Operating Temperature
4-2
S3FM02G_DS_REV 1.00
4 ELECTRICAL DATA
4.3 I/O D.C. Characteristics
(TA = –40 to 85 C, VDD = VDDCORE = VDDIO = AVDD = 2.7V to 5.5V)
Parameter
Symbol
Conditions
Min
Typ
Max
Unit
2.7
–
5.5
V
0.8VDD
–
VDD
VDD –0.3
–
VDD
VDD
XIN = 4MHz ~ 8MHz,
PLLCLK = 75MHz
VIH1
All input pins except VIH2
VIH2
XIN, XTIN, MODE[2:0], nRESET
VIL1
All input pins except VIL2
–
–
0.2 VDD
VIL2
XIN, XTIN, MODE[2:0], nRESET
–
–
0.3
VOH1
IOH = –1.6mA, VDD=5.0V
VDD –0.4
–
–
V
VOH2
IOH=-20mA, 12 IMC pads, VDD=5.0V
(PWM[1:0]U[2:0], PWM[1:0]D[2:0])
VDD –1.0
–
–
V
VOL1
IOL = 1.6mA , VDD=5.0V
–
–
0.4
V
VOL2
IOL=20mA, 12 IMC pads, VDD=5.0V
(PWM[1:0]U[2:0], PWM[1:0]D[2:0])
–
–
1.0
V
Input High Leakage
Current
ILIH1
VIN=VDD, All input pins except
MODE[2:0] and ILIH2
–
–
1
ILIH2
VIN=VDD, XIN, XTIN
–
–
20
Input Low Leakage
Current
ILIL1
VIN=0V, All input pins except
nRESET and ILIL2
–
–
–1
ILIL2
VIN=0V, XIN, XTIN
–
–
–20
Output High
Leakage Current
ILOH
VOUT=VDD, All output pins
–
–
3
A
Output Low
Leakage Current
ILOL
VOUT=0V, All output pins
–
–
–3
A
Pull-up Resistor
RL
VIN=0V, VDD=5.0V
All ports
16
30
60
k
Operating Voltage
Input High Voltage
Input Low Voltage
Output High
Voltage
Output Low Voltage
NOTE: All pins are schmitt trigger type
4-3
V
V
A
A
S3FM02G_DS_REV 1.00
4 ELECTRICAL DATA
4.4 I/O Capacitance
(TA = –40 to 85 C, VDD = VDDCORE = VDDIO = AVDD = 2.7V to 5.5V)
Parameter
I/O Capacitance
Input Capacitance
Output Capacitance
Symbol
Conditions
CIO
CIN
F = 1MHz, unmeasured pins are
connected to VSS
COUT
Min
Typ
Max
–
–
10
–
–
10
–
–
10
Unit
pF
4.5 RESET Input Characteristics
(TA = –40 to 85 C, VDD = VDDCORE = VDDIO = AVDD = 2.7V to 5.5V)
Parameter
Symbol
Pull-up Resistor
RNRST
Input Low Width
tRSL
Conditions
Min
Typ
Max
Unit
VIN=0V, VDD=5.0V
16
30
60
k
–
0.8
1.2
2
s
NOTE: If the width of reset pulse is greater than minimum value, the pulse is always recognized as a valid pulse.
tRSL
PnRESET
0.2 VDD
Figure 4-1
Input Timing for nRESET
4-4
S3FM02G_DS_REV 1.00
4 ELECTRICAL DATA
4.6 External Interrupt Input Characteristics
(TA = –40 to 85 C, VDD = VDDCORE = VDDIO = AVDD = 2.7V to 5.5V)
Parameter
Symbol
Conditions
Min
Typ
Max
Unit
Interrupt Input High Width
tINTH
VDD=5.0V
100
200
300
ns
Interrupt Input Low Width
tINTL
VDD=5.0V
100
200
300
ns
NOTE: If the width of interrupt pulse is greater than minimum value, the pulse is always recognized as a valid pulse.
tINTL
tINTH
0.8 VDD
External
Interrupt
0.2 VDD
Figure 4-2
Input Timing for External Interrupt
4-5
S3FM02G_DS_REV 1.00
4 ELECTRICAL DATA
4.7 Oscillator Characteristics
4.7.1 External Main Clock Oscillator Characteristics
(TA = –40 to 85 C, VDD = VDDCORE = VDDIO = AVDD = 2.7V to 5.5V)
Oscillator
Symbol
Conditions
Min
Typ
Max
Unit
Oscillator frequency
EMCLK
–
4
–
8
MHz
TSTA
–
–
–
10
ms
4
–
8
MHz
4
–
8
MHz
Stabilization Time
C1
XIN
Crystal/Resonator/
Ceramic
EMCLK
XOUT
C2
External
Clock
External Clock
XIN
EMCLK
Open Pin
XOUT
4.7.2 External Sub Clock Oscillator Characteristics
(TA = –40 to 85 C, VDD = VDDCORE = VDDIO = AVDD = 2.7V to 5.5V)
Oscillator
Symbol
Conditions
Min
Typ
Max
Unit
Oscillator frequency
ESCLK
–
–
32.768
–
KHz
TSTA
–
–
–
10
s
–
32.768
–
KHz
Stabilization Time
C1
XTIN
Crystal/Resonator/
Ceramic
ESCLK
XTOUT
C2
4-6
S3FM02G_DS_REV 1.00
4 ELECTRICAL DATA
4.7.3 Internal Main Clock Oscillator Characteristics
(TA = –40 to 85 C, VDD = VDDCORE = VDDIO = AVDD = 2.7V to 5.5V)
Oscillator
Oscillator frequency
Output clock duty ratio
Accuracy
Stabilization Time
Symbol
IMCLK16
IMCLK20
Conditions
VDD=5.0V
Min
Typ
Max
Unit
–
8/16
–
MHz
–
20
–
MHz
–
VDD=5.0V
40
–
60
%
–
VDD=5.0V, TA = 25'C
–
–
±1
%
–
VDD=2.7~5.5V, TA = 0~70'C
–
–
±2
%
–
VDD=5.0V, TA = –40~85'C
–
–
±3
%
–
VDD=2.7~5.5V, TA = –40~85'C
–
–
±5
%
–
–
2
ms
Min
Typ
Max
Unit
–
TSTA
4.7.4 Internal Sub Clock Oscillator Characteristics
(TA = –40 to 85 C, VDD = VDDCORE = VDDIO = AVDD = 2.7V to 5.5V)
Oscillator
Symbol
Conditions
ISCLK
VDD=5.0V
–
32.768
–
KHz
Output clock duty ratio
–
VDD=5.0V
40
–
60
%
Accuracy
–
TA = –40 to 85 C
–
–
±50
%
–
–
–
500
s
Min
Typ
Max
Unit
4
–
8
MHz
8
–
75
MHz
40
50
60
%
–
–
200
s
Oscillator frequency
Stabilization Time
TSTA
4.7.5 PLL Characteristics
(TA = –40 to 85 C, VDD = VDDCORE = VDDIO = AVDD = 2.7V to 5.5V)
Parameter
Input frequency
Symbol
Conditions
FIN
Output frequency
FOUT
Clock Duty Ratio
TOD
Locking Time
TLT
–
4-7
S3FM02G_DS_REV 1.00
4 ELECTRICAL DATA
4.8 Current Consumption
(TA = –40 to 85 C, VDD = VDDCORE = VDDIO = AVDD = 5.5V)
Parameter
Symbol
Mode
Min.
Typ.
Max.
Unit
IDD111
Enable EMCLK, IMCLK,
ESCLK, and ISCLK
Enable all peripherals
Run CPU by EMCLK =
8MHz
Normal operating 11
–
13
26
mA
IDD112 (3)
Enable EMCLK, IMCLK,
ESCLK, and ISCLK
Enable all peripherals
Run CPU by EMCLK =
4MHz
Normal operating 11
–
10
20
mA
IDD121 (3)
Disable EMCLK
Enable IMCLK, ESCLK,
and ISCLK
Enable all peripherals
Run CPU by IMCLK =
20MHz
Normal operating 12
–
20
40
mA
IDD122 (3)
Disable EMCLK
Enable IMCLK, ESCLK,
and ISCLK
Enable all peripherals
Run CPU by IMCLK =
8MHz
Normal operating 12
–
10
20
mA
IDD2
Enable PLL
Enable EMCLK, IMCLK,
ESCLK, and ISCLK
Run CPU by PLLCLK
High-speed operating
–
50
90
mA
IDD31
CPU stops in IDD11
Condition.
Normal idle 1
–
6
12
mA
IDD32 (3)
CPU stops in IDD12
Condition.
Normal idle 2
–
6
12
mA
IDD4
CPU stops in IDD2
Condition.
High-speed idle
–
10
20
mA
IDD51 (3)
Disable EMCLK, and
IMCLK
Enable ESCLK, and ISCLK
Enable all peripherals
Run CPU by ESCLK
Sub-operating 1
–
5
10
mA
IDD52 (3)
Disable EMCLK, IMCLK,
and ESCLK
Enable ISCLK
Enable all peripherals
Sub-operating 2
–
5
10
mA
Supply
Current
Condition
4-8
S3FM02G_DS_REV 1.00
Parameter
Symbol
IDD61 (3)
4 ELECTRICAL DATA
Condition
Run CPU by ISCLK
CPU stops in IDD51
Condition.
Mode
Min.
Typ.
Max.
Unit
Sub-idle 1
–
4
8
mA
Sub-idle 2
–
4
8
mA
Stop 1
–
0.5
1
mA
Stop 2
–
0.6
1
mA
LVD OFF, LCD OFF
IDD62 (3)
CPU stops in IDD52
Condition.
LVD OFF, LCD OFF
IDD71
Disable EMCLK, IMCLK,
ESCLK, and ISCLK
All peripherals stop.
LVD OFF, LCD OFF
IDD72 (3)
Disable EMCLK, IMCLK,
and ESCLK
Enable ISCLK, FRT
LVD OFF, LCD OFF
NOTE:
1.
Supply Current does not include current drawn through internal pull-up resistor, LCD voltage dividing resistors, and
external output current loads.
2.
Above tables, the current is based on LVD-OFF condition.
3.
These values are only characterization data, and not tested in the mass production.
4-9
S3FM02G_DS_REV 1.00
4 ELECTRICAL DATA
(TA = –40 to 85 C, VDD = VDDCORE = VDDIO = AVDD = 3.3V) (3)
Parameter
Supply
Current
Symbol
Condition
Mode
Min.
Typ.
Max.
Unit
IDD111
Enable EMCLK, IMCLK,
ESCLK, and ISCLK
Enable all peripherals
Run CPU by EMCLK = 8MHz
Normal operating 11
–
10
20
mA
IDD112
Enable EMCLK, IMCLK,
ESCLK, and ISCLK
Enable all peripherals
Run CPU by EMCLK = 4MHz
Normal operating 11
–
7
14
mA
IDD121
Disable EMCLK
Enable IMCLK, ESCLK, and
ISCLK
Enable all peripherals
Run CPU by IMCLK = 20MHz
Normal operating 12
–
17
34
mA
IDD122
Disable EMCLK
Enable IMCLK, ESCLK, and
ISCLK
Enable all peripherals
Run CPU by IMCLK = 8MHz
Normal operating 12
–
8
16
mA
IDD2
Enable PLL
Enable EMCLK, IMCLK,
ESCLK, and ISCLK
Run CPU by PLLCLK
High-speed
operating
–
45
85
mA
IDD31
CPU stops in IDD11 Condition.
Normal idle 1
–
3
6
mA
IDD32
CPU stops in IDD12 Condition.
Normal idle 2
–
3
6
mA
IDD4
CPU stops in IDD2 Condition.
High-speed idle
–
7
14
mA
IDD51
Disable EMCLK, and IMCLK
Enable ESCLK, and ISCLK
Enable all peripherals
Run CPU by ESCLK
Sub-operating 1
–
3
6
mA
IDD52
Disable EMCLK, IMCLK, and
ESCLK
Enable ISCLK
Enable all peripherals
Run CPU by ISCLK
Sub-operating 2
–
3
6
mA
Sub-idle 1
–
2
4
mA
Sub-idle 2
–
2
4
mA
Stop 1
–
0.5
1
mA
IDD61
CPU stops in IDD51 Condition.
LVD OFF, LCD OFF
IDD62
CPU stops in IDD52 Condition.
LVD OFF, LCD OFF
IDD71
Disable EMCLK, IMCLK,
ESCLK, and ISCLK
All peripherals stop.
4-10
S3FM02G_DS_REV 1.00
Parameter
Symbol
4 ELECTRICAL DATA
Condition
Mode
Min.
Typ.
Max.
Unit
–
0.5
1
mA
LVD OFF, LCD OFF
IDD72
Disable EMCLK, IMCLK, and
ESCLK
Enable ISCLK, FRT
Stop 2
LVD OFF, LCD OFF
NOTE:
1.
Supply Current does not include current drawn through internal pull-up resistor, LCD voltage dividing resistors, and
external output current loads.
2.
Above tables, the current is based on LVD-OFF condition.
3.
3.3V data is only characteristic data. These values are not tested in the mass production
4-11
S3FM02G_DS_REV 1.00
4 ELECTRICAL DATA
(TA = –40 to 85 C, VDD = VDDCORE = VDDIO = AVDD = 2.7V) (3)
Parameter
Symbol
Condition
Mode
Min.
Typ.
Max.
Unit
IDD111
Enable EMCLK, IMCLK,
ESCLK, and ISCLK
Enable all peripherals
Run CPU by EMCLK =
8MHz
Normal operating 11
–
9
18
mA
IDD112
Enable EMCLK, IMCLK,
ESCLK, and ISCLK
Enable all peripherals
Run CPU by EMCLK =
4MHz
Normal operating 11
–
6
12
mA
IDD121
Disable EMCLK
Enable IMCLK, ESCLK, and
ISCLK
Enable all peripherals
Run CPU by IMCLK =
20MHz
Normal operating 12
–
17
34
mA
IDD122
Disable EMCLK
Enable IMCLK, ESCLK, and
ISCLK
Enable all peripherals
Run CPU by IMCLK =
8MHz
Normal operating 12
–
8
16
mA
IDD2
Enable PLL
Enable EMCLK, IMCLK,
ESCLK, and ISCLK
Run CPU by PLLCLK
High-speed operating
–
44
85
mA
IDD31
CPU stops in IDD11
Condition.
Normal idle 1
–
2
5
mA
IDD32
CPU stops in IDD12
Condition.
Normal idle 2
–
2
5
mA
IDD4
CPU stops in IDD2 Condition.
High-speed idle
–
7
14
mA
IDD51
Disable EMCLK, and
IMCLK
Enable ESCLK, and ISCLK
Enable all peripherals
Run CPU by ESCLK
Sub-operating 1
–
2
5
mA
IDD52
Disable EMCLK, IMCLK,
and ESCLK
Enable ISCLK
Enable all peripherals
Run CPU by ISCLK
Sub-operating 2
–
2
5
mA
IDD61
CPU stops in IDD51
Sub-idle 1
–
1
3
mA
Supply
Current
4-12
S3FM02G_DS_REV 1.00
Parameter
Symbol
4 ELECTRICAL DATA
Condition
Condition.
Mode
Min.
Typ.
Max.
Unit
Sub-idle 2
–
1
3
mA
Stop 1
–
0.5
1
mA
Stop 2
–
0.5
1
mA
LVD OFF, LCD OFF
IDD62
CPU stops in IDD52
Condition.
LVD OFF, LCD OFF
IDD71
Disable EMCLK, IMCLK,
ESCLK, and ISCLK
All peripherals stop.
LVD OFF, LCD OFF
IDD72
Disable EMCLK, IMCLK,
and ESCLK
Enable ISCLK, FRT
LVD OFF, LCD OFF
NOTE:
1.
Supply Current does not include current drawn through internal pull-up resistor, LCD voltage dividing resistors, and
external output current loads.
2.
Above tables, the current is based on LVD-OFF condition.
3.
2.7V data is only characteristic data. These values are not tested in the mass production
4-13
S3FM02G_DS_REV 1.00
4 ELECTRICAL DATA
4.9 LVD Characteristics
(TA = –40 to 85 C, VDD = VDDCORE = VDDIO = AVDD = 2.7V to 5.5V)
Oscillator
Symbol
Conditions
VLVD0
LVD Detect Voltage
VLVD1
VLVD2
Reset Default
VLVD3
Hysteresis of VLVD
(Slew Rate of LVD)
∆V
–
Min
Typ
Max
2.5
2.6
2.7
2.6
2.8
3.0
3.5
3.75
4.0
4.0
4.25
4.5
–
100
200
NOTE: User can select the level for reset and interrupt voltage by LVDRL[2:0] and LVDIL[2:0] in CM_MR0 register
4-14
Unit
V
mV
S3FM02G_DS_REV 1.00
4 ELECTRICAL DATA
4.10 12-Bit ADC0 Characteristics
(TA = –40 to 85 C, VDD = VDDCORE = VDDIO = AVDD = 2.7V to 5.5V)
Parameter
Symbol
Conditions
Min
Typ
Max
Unit
–
–
–
12
–
Bit
Supply Voltage
AVDD0
–
2.7
5
5.5
V
Reference Voltage
AVREF
–
2.7
–
AVDD0
V
Input Voltage Range
VAIN0
–
0
–
AVREF
V
Clock Frequency
FADC0
50% duty cycle
–
–
5
MHz
Maximum Conversion
Time
tADC0
Max. FADC0
AVDD0 = AVREF
–
–
1
MSPS
Differential nonlinearity
DNL
AVDD0 = AVREF
AVSS0 = 0.0V
–
–
1.5
LSB
Integral nonlinearity
INL
AVDD0 = AVREF
AVSS0 = 0.0V
–
–
3.5
LSB
AVREF = 5.5V
–
–
AVREF - 43
mV
AVREF = 2.7V
–
–
AVREF - 22
mV
AVREF = 5.5V
–
–
43
mV
AVREF = 2.7V
–
–
22
mV
Resolution
TOPOFF
Offset Error
(1)
(unadjusted)
BOTOFF
Operation Current
IOP
AVDD0 = AVREF = 5.0V
AVSS0 = 0.0V
–
7.5
10
mA
Power down Current
IPD
AVDD0 = AVREF = 5.0V
AVSS0 = 0.0V
–
20
30
A
NOTE: When Internal Calibration mode is set, the 1/4 and 3/4 values of VREF are stored in ADC_OCR registers but these
values can't be used for getting accurate compensation (calibration) because of the offset difference in the customer
board environment. Therefore external calibration is better to be used for more accurate calibration. More detail
information is shown in ADC0 section.
4-15
S3FM02G_DS_REV 1.00
4 ELECTRICAL DATA
4.10.1 OP-AMP Characteristics
(TA = –40 to 85 C, VDD = VDDCORE = VDDIO = AVDD = 2.7V to 5.5V)
Parameter
Input Offset
Voltage
Input Voltage
Range
Slew Rate
Gain Error
Symbol
Conditions
Min
Typ
Max
Unit
|VIO|
–
–
–
±9
mV
Gain = 2.32 to 4.09
0.04AVDD0
–
0.36AVDD0
V
Gain = 4.53 to 5.92
0.02AVDD0
–
0.18AVDD0
V
Gain = 7.09, 8.86
0.01AVDD0
–
0.085AVDD0
V
@CL = 10pF
10
15
-
V/s
@CL = 50pF
–
10
-
V/s
Gain = 2.32 to 4.53, TA = 25C
–
±1.0
±2.0
%
Gain = 5.04 to 8.86, TA = 25C
–
±1.5
±3.0
%
Gain = 2.32 to 4.53,
TA = –40 to 85 C
–
±2.0
±4.0
%
Gain = 5.04 to 8.86,
TA = –40 to 85 C
–
±3.0
±6.0
%
VI
SR
GE
4-16
S3FM02G_DS_REV 1.00
4 ELECTRICAL DATA
4.11 10-Bit ADC1 Characteristics
(TA = –40 to 85 C, VDD = VDDCORE = VDDIO = AVDD = 2.7V to 5.5V)
Parameter
Symbol
Conditions
Min
Typ
Max
Unit
–
–
–
10
–
Bit
Supply Voltage
AVDD1
–
2.7
5
5.5
V
Reference Voltage
AVREF
–
2.7
–
AVDD1
V
Input Voltage Range
VAIN1
–
0
–
AVREF
V
Clock Frequency
FADC1
50% duty cycle
–
–
700
㎑
Maximum Conversion
Time
tADC1
Max. FADC1
AVDD1 = AVREF
–
–
50
KSPS
Differential nonlinearity
DNL
AVDD1 = AVREF
AVSS1 = 0.0V
–
–
±1
LSB
Integral nonlinearity
INL
AVDD1 = AVREF
AVSS1 = 0.0V
–
–
±1.5
LSB
AVREF = 5.5V
–
–
AVREF - 172
mV
AVREF = 2.7V
–
–
AVREF - 85
mV
AVREF = 5.5V
–
–
172
mV
AVREF = 2.7V
–
–
85
mV
Resolution
TOPOFF
Offset Error (unadjusted)
BOTOFF
Operation Current
IOP
AVDD1 = AVREF = 5.0V
AVSS1 = 0.0V
–
0.2
1
mA
Power down Current
IPD
AVDD1 = AVREF = 5.0V
AVSS1 = 0.0V
–
1
2
A
4-17
S3FM02G_DS_REV 1.00
4 ELECTRICAL DATA
4.12 LCD Characteristics
(TA = –40 to 85 C, VDD = VDDCORE = VDDIO = AVDD = 2.7V to 5.5V)
Parameter
LCD voltage
dividing resistor
Symbol
RLCD1
RLCD2
Conditions
–
Min
Typ
Max
Unit
LCDC_CR.17=0
40
60
80
k
LCDC_CR.17=1
20
30
40
k
|VLCD - COMi|
voltage drop
(i=0 ~ 3)
VDC
–15A per common pin
–
–
120
mV
|VLCD - SEGi|
voltage drop
(i=0 ~ 39)
VDS
–15A per common pin
–
–
120
mV
0.67VDD-0.2
–
0.67VDD+0.2
V
0.33VDD-0.2
–
0.33VDD+0.2
V
Middle Output
Voltage
VLCD1
VLCD2
–
4-18
S3FM02G_DS_REV 1.00
4 ELECTRICAL DATA
4.13 Memory Characteristics
4.13.1 Program Flash Memory Characteristics
(TA = –40 to 85 C, VDD = VDDCORE = VDDIO = AVDD = 2.7V to 5.5V)
Parameter
Symbol
Conditions
Min
Typ
Max
Unit
FSIZE
–
–
384
–
KB
Program Size
FWSIZE
–
–
4
–
B
Page Size
FPSIZE
–
–
1024
–
B
Sector Size
FSSIZE
–
–
32
–
KB
FTW
–
20
25
30
s
Page Erase Time
FTPERA
–
4
8
12
ms
Sector Erase Time
FTSERA
–
12
20
28
ms
Chip Erase Time
FTCERA
–
32
50
70
ms
FRA
–
–
–
50
ns
Endurance Number of writing/erasing
FNWE
–
10,000
–
–
Times
Data Retention
FTDR
–
10
–
–
Years
Total Size
Programming Time for 1 Word
Read Command to valid data
NOTE: Flash hardware operating times: Total flash operating (program/erase) time may depend upon the software
4.13.2 Data FLASH Memory Characteristics
(TA = –40 to 85 C, VDD = VDDCORE = VDDIO = AVDD = 2.7V to 5.5V)
Parameter
Symbol
Conditions
Min
Typ
Max
Unit
FSIZE
–
–
16
–
KB
Program Size
FWSIZE
–
1
2
4
B
Page Size
FPSIZE
–
–
256
–
B
Sector Size
FSSIZE
–
–
1
–
KB
FTW
–
20
25
30
s
Page Erase Time
FTPERA
–
4
8
12
ms
Sector Erase Time
FTSERA
–
12
20
28
ms
Chip Erase Time
FTCERA
–
32
50
70
ms
FRA
–
–
–
100
ns
Endurance Number of writing/erasing
FNWE
–
100,000
–
–
Times
Data Retention
FTDR
–
10
–
–
Years
Total Size
Programming Time for 1 Word
Read Command to valid data
NOTE: Flash hardware operating times: Total flash operating (program/erase) time may depend upon the software
4-19
S3FM02G_DS_REV 1.00
4 ELECTRICAL DATA
4.14 ESD Characteristics
Parameter
Electrostatic discharge
Symbol
Conditions
Min
Typ
Max
Unit
HBM
2000
–
–
V
MM
200
–
–
V
CDM
500
–
–
V
VESD
4-20
S3FM02G_DS_REV 1.00
5
5 PACKAGE SPECIFICATION
PACKAGE SPECIFICATION
5.1 Overview
This chapter describes the package information of S3FM02G. It is available in a 128-ETQFP-1414 package type.
Table 5-1
Absolute Maximum Ratings
Package Number
128-ETQFP-1414
Package Width / Package Length
14.0 / 14.0 mm
Mounting Height
1.20 mm MAX
Lead Pitch
0.40 mm
5-1
S3FM02G_DS_REV 1.00
5 PACKAGE SPECIFICATION
5.2 Package Dimension
Figure 5-1
128ETQFP-1414 Package Dimension
5-2