EZ-Host™ Programmable Embedded USB Host/Peripheral

CY7C67300
PRELIMINARY
EZ-Host™ Programmable Embedded
USB Host/Peripheral Controller
Cypress Semiconductor Corporation
Document #: 38-08015 Rev. *D
•
3901 North First Street
•
San Jose, CA 95134
•
408-943-2600
Revised May 28, 2003
PRELIMINARY
CY7C67300
TABLE OF CONTENTS
1.0 INTRODUCTION ............................................................................................................................ 10
1.1 EZ-Host Features ...................................................................................................................... 10
2.0 TYPICAL APPLICATIONS ............................................................................................................. 11
3.0 FUNCTIONAL OVERVIEW ............................................................................................................ 11
3.1 Processor Core ......................................................................................................................... 11
3.1.1 Processor ........................................................................................................................................ 11
3.1.2 Clocking ..........................................................................................................................................11
3.1.3 Memory ........................................................................................................................................... 11
3.1.4 Interrupts ......................................................................................................................................... 11
3.1.5 General Timers and Watchdog Timer ............................................................................................. 11
3.1.6 Power Management ........................................................................................................................11
4.0 INTERFACE DESCRIPTIONS ....................................................................................................... 11
4.1 USB Interface ............................................................................................................................ 13
4.1.1 USB Features .................................................................................................................................. 13
4.1.2 USB Pins. ........................................................................................................................................ 14
4.2 OTG Interface ........................................................................................................................... 14
4.2.1 OTG Features ................................................................................................................................. 14
4.2.2 OTG Pins. ....................................................................................................................................... 14
4.3 External Memory Interface ........................................................................................................ 14
4.3.1 External Memory Interface Features ............................................................................................... 14
4.3.2 External Memory Access Description ............................................................................................. 14
4.3.3 Program Memory Hole Description ................................................................................................. 15
4.3.4 External Memory Interface Pins. ..................................................................................................... 15
4.3.5 External Memory Interface Block Diagrams[3] ................................................................................ 16
4.4 General Purpose I/O Interface (GPIO) ...................................................................................... 17
4.4.1 GPIO Description ............................................................................................................................ 17
4.4.2 Unused Pin Descriptions .................................................................................................................17
4.5 UART Interface ......................................................................................................................... 17
4.5.1 UART Features ............................................................................................................................... 17
4.5.2 UART Pins. ..................................................................................................................................... 17
4.6 I2C EEPROM Interface ............................................................................................................. 17
4.6.1 I2C EEPROM Features ................................................................................................................... 17
4.6.2 I2C EEPROM Pins. ......................................................................................................................... 18
4.7 Serial Peripheral Interface ........................................................................................................ 18
4.7.1 SPI Features ...................................................................................................................................18
4.7.2 SPI Pins ..........................................................................................................................................18
4.8 High-speed Serial Interface ...................................................................................................... 18
4.8.1 HSS Features .................................................................................................................................. 19
4.8.2 HSS Pins ......................................................................................................................................... 19
4.9 Programmable Pulse/PWM Interface ........................................................................................ 19
4.9.1 Programmable Pulse/PWM Features ..............................................................................................19
4.9.2 Programmable Pulse/PWM Pins. ....................................................................................................19
4.10 Host Port Interface .................................................................................................................. 19
4.10.1 HPI Features ................................................................................................................................. 20
4.10.2 HPI Pins. ....................................................................................................................................... 20
4.11 IDE Interface ........................................................................................................................... 21
4.11.1 IDE Features ................................................................................................................................. 21
4.11.2 IDE Pins ....................................................................................................................................... 22
4.11.3 Charge Pump Interface .................................................................................................................22
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PRELIMINARY
CY7C67300
TABLE OF CONTENTS (continued)
4.11.4 Charge Pump Features .................................................................................................................23
4.11.5 Charge Pump Pins. ....................................................................................................................... 23
4.11.6 Booster Interface ........................................................................................................................... 23
4.11.7 Booster Pins. ................................................................................................................................. 25
4.11.8 Crystal Interface ............................................................................................................................ 25
4.11.9 Crystal Pins. .................................................................................................................................. 25
4.11.10 Boot Configuration Interface ....................................................................................................... 25
4.12 Operational Modes .................................................................................................................. 26
4.12.1 Coprocessor Mode ........................................................................................................................26
4.12.2 Stand-alone Mode ......................................................................................................................... 26
5.0 POWER SAVINGS AND RESET DESCRIPTION .......................................................................... 27
5.1 Power Savings Mode Description ............................................................................................. 27
5.2 Sleep ......................................................................................................................................... 27
5.3 External (Remote) Wake-up Source ......................................................................................... 27
5.4 Power-On-Reset Description .................................................................................................... 27
5.5 Reset Pin .................................................................................................................................. 27
5.6 USB Reset ................................................................................................................................ 27
6.0 MEMORY MAP ............................................................................................................................... 28
6.1 Mapping .................................................................................................................................... 28
6.1.1 Internal Memory ..............................................................................................................................28
6.1.2 External Memory ............................................................................................................................. 28
7.0 REGISTERS ................................................................................................................................... 30
7.1 Processor Control Registers ..................................................................................................... 30
7.1.1 CPU Flags Register [0xC000] [R] ................................................................................................. 30
7.1.2 Bank Register [0xC002] [R/W] ...................................................................................................... 31
7.1.3 Hardware Revision Register [0xC004] [R] .................................................................................... 32
7.1.4 CPU Speed Register [0xC008] [R/W] ........................................................................................... 32
7.1.5 Power Control Register [0xC00A] [R/W] .......................................................................................33
7.1.6 Interrupt Enable Register [0xC00E] [R/W] .................................................................................... 35
7.1.7 Breakpoint Register [0xC014] [R/W] ............................................................................................. 36
7.1.8 USB Diagnostic Register [0xC03C] [R/W] ..................................................................................... 37
7.1.9 Memory Diagnostic Register [0xC03E] [W] ................................................................................... 38
7.2 External Memory Registers ....................................................................................................... 39
7.2.1 Extended Page n Map Register [R/W] ............................................................................................ 39
7.2.2 External Memory Control Register [0xC03A] [R/W] ...................................................................... 40
7.3 Timer Registers ......................................................................................................................... 41
7.3.1 Watchdog Timer Register [0xC00C] [R/W] ................................................................................... 41
7.3.2 Timer n Register [R/W] .................................................................................................................... 42
7.4 General USB Registers ............................................................................................................. 42
7.4.1 USB n Control Register [R/W] ......................................................................................................... 42
7.5 USB Host Only Registers .......................................................................................................... 45
7.5.1 Host n Control Register [R/W] ......................................................................................................... 45
7.5.2 Host n Address Register [R/W] ....................................................................................................... 46
7.5.3 Host n Count Register [R/W] ...........................................................................................................46
7.5.4 Host n Endpoint Status Register [R] ............................................................................................... 47
7.5.5 Host n PID Register [W] .................................................................................................................. 48
7.5.6 Host n Count Result Register [R] ....................................................................................................49
7.5.7 Host n Device Address Register [W] ............................................................................................... 50
7.5.8 Host n Interrupt Enable Register [R/W] ........................................................................................... 50
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PRELIMINARY
CY7C67300
TABLE OF CONTENTS (continued)
7.5.9 Host n Status Register [R/W] .......................................................................................................... 52
7.5.10 Host n SOF/EOP Count Register [R/W] ........................................................................................ 53
7.5.11 Host n SOF/EOP Counter Register [R] ......................................................................................... 54
7.5.12 Host n Frame Register [R] ............................................................................................................ 54
7.6 USB Device Only Registers ...................................................................................................... 54
7.6.1 Device n Endpoint n Control Register [R/W] ................................................................................... 55
7.6.2 Device n Endpoint n Address Register [R/W] .................................................................................56
7.6.3 Device n Endpoint n Count Register [R/W] ..................................................................................... 57
7.6.4 Device n Endpoint n Status Register [R/W] .................................................................................... 57
7.6.5 Device n Endpoint n Count Result Register [R/W] ..........................................................................59
7.6.6 Device n Port Select Register [R/W] ............................................................................................... 60
7.6.7 Device n Interrupt Enable Register [R/W] .......................................................................................60
7.6.8 Device n Address Register [W] ....................................................................................................... 63
7.6.9 Device n Status Register [R/W] ....................................................................................................... 63
7.6.10 Device n Frame Number Register [R] ........................................................................................... 65
7.6.11 Device n SOF/EOP Count Register [W] ........................................................................................ 66
7.7 OTG Control Registers ............................................................................................................. 66
7.7.1 OTG Control Register [0xC098] [R/W] .......................................................................................... 66
7.8 GPIO Registers ......................................................................................................................... 68
7.8.1 GPIO Control Register [0xC006] [R/W] ......................................................................................... 68
7.8.2 GPIO n Output Data Register [R/W] ............................................................................................... 70
7.8.3 GPIO n Input Data Register [R] ....................................................................................................... 70
7.8.4 GPIO n Direction Register [R/W] ..................................................................................................... 71
7.9 IDE Registers ............................................................................................................................ 71
7.9.1 IDE Mode Register [0xC048] [R/W] ..............................................................................................71
7.9.2 IDE Start Address Register [0xC04A] [R/W] .................................................................................72
7.9.3 IDE Stop Address Register [0xC04C] [R/W] .................................................................................73
7.9.4 IDE Control Register [0xC04E] [R/W] ........................................................................................... 73
7.9.5 IDE PIO Port Registers [0xC050 - 0xC06F] [R/W] .......................................................................... 74
7.10 HSS Registers ........................................................................................................................ 74
7.10.1 HSS Control Register [0xC070] [R/W] ........................................................................................ 75
7.10.2 HSS Baud Rate Register [0xC072] [R/W] ................................................................................... 77
7.10.3 HSS Transmit Gap Register [0xC074] [R/W] .............................................................................. 77
7.10.4 HSS Data Register [0xC076] [R/W] ............................................................................................ 78
7.10.5 HSS Receive Address Register [0xC078] [R/W] ......................................................................... 78
7.10.6 HSS Receive Counter Register [0xC07A] [R/W] ......................................................................... 79
7.10.7 HSS Transmit Address Register [0xC07C] [R/W] ....................................................................... 79
7.10.8 HSS Transmit Counter Register [0xC07E] [R/W] ........................................................................ 80
7.11 HPI Registers .......................................................................................................................... 80
7.11.1 HPI Breakpoint Register [0x0140] [R] ......................................................................................... 80
7.11.2 Interrupt Routing Register [0x0142] [R] .......................................................................................81
7.11.3 SIEXmsg Register [W] .................................................................................................................. 83
7.11.4 HPI Mailbox Register [0xC0C6] [R/W] ........................................................................................ 83
7.11.5 HPI Status Port [] [HPI: R] ...........................................................................................................84
7.12 SPI Registers .......................................................................................................................... 85
7.12.1 SPI Configuration Register [0xC0C8] [R/W] ................................................................................ 86
7.12.2 SPI Control Register [0xC0CA] [R/W] ......................................................................................... 87
7.12.3 SPI Interrupt Enable Register [0xC0CC] [R/W] ........................................................................... 89
7.12.4 SPI Status Register [0xC0CE] [R] ............................................................................................... 90
7.12.5 SPI Interrupt Clear Register [0xC0D0] [W] ................................................................................... 90
7.12.6 SPI CRC Control Register [0xC0D2] [R/W] .................................................................................91
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PRELIMINARY
CY7C67300
TABLE OF CONTENTS (continued)
7.12.7 SPI CRC Value Register [0xC0D4] [R/W] ................................................................................... 92
7.12.8 SPI Data Register [0xC0D6] [R/W] ..............................................................................................92
7.12.9 SPI Transmit Address Register [0xC0D8] [R/W] .......................................................................... 93
7.12.10 SPI Transmit Count Register [0xC0DA] [R/W] ........................................................................... 93
7.12.11 SPI Receive Address Register [0xC0DC [R/W] ......................................................................... 93
7.12.12 SPI Receive Count Register [0xC0DE] [R/W] ............................................................................94
7.13 UART Registers ...................................................................................................................... 94
7.13.1 UART Control Register [0xC0E0] [R/W] .......................................................................................94
7.13.2 UART Status Register [0xC0E2] [R] ........................................................................................... 95
7.13.3 UART Data Register [0xC0E4] [R/W] ........................................................................................... 96
7.14 PWM Registers ....................................................................................................................... 96
7.14.1 PWM Control Register [0xC0E6] [R/W] ........................................................................................ 97
7.14.2 PWM Maximum Count Register [0xC0E8] [R/W] ......................................................................... 98
7.14.3 PWM n Start Register [R/W] ......................................................................................................... 98
7.14.4 PWM n Stop Register [R/W] .......................................................................................................... 99
7.14.5 PWM Cycle Count Register [0xC0FA] [R/W] ............................................................................. 100
8.0 PIN DIAGRAM .............................................................................................................................101
9.0 PIN DESCRIPTIONS ....................................................................................................................101
10.0 ABSOLUTE MAXIMUM RATINGS ............................................................................................ 105
11.0 OPERATING CONDITIONS ....................................................................................................... 105
12.0 CRYSTAL REQUIREMENTS (XTALIN, XTALOUT) ................................................................. 105
13.0 DC CHARACTERISTICS
.........................................................................................................106
13.1 USB Transceiver ................................................................................................................... 107
14.0 AC TIMING CHARACTERISTICS ..............................................................................................107
14.1 Reset Timing ........................................................................................................................ 107
14.2 Clock Timing ........................................................................................................................ 108
14.3 SRAM Read Cycle ............................................................................................................... 109
14.4 SRAM Write Cycle ............................................................................................................... 110
14.5 I2C EEPROM Timing ........................................................................................................... 111
14.6 HPI (Host Port Interface) Write Cycle Timing ...................................................................... 112
14.7 HPI (Host Port Interface) Read Cycle Timing ...................................................................... 113
14.8 IDE Timing ............................................................................................................................ 114
14.9 HSS BYTE Mode Transmit ................................................................................................... 114
14.10 HSS Block Mode Transmit .................................................................................................. 114
14.11 HSS BYTE and BLOCK Mode Receive .............................................................................. 114
14.12 Hardware CTS/RTS Handshake ......................................................................................... 115
15.0 REGISTERS SUMMARY ........................................................................................................... 115
16.0 ORDERING INFORMATION ...................................................................................................... 119
17.0 PACKAGE DIAGRAMS ............................................................................................................. 119
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PRELIMINARY
CY7C67300
LIST OF FIGURES
Figure 1-1. Block Diagram ..................................................................................................................... 10
Figure 4-1. Up to 256k x 16 External SRAM Data ................................................................................. 16
Figure 4-2. Up to 512k x 8 External SRAM Data ................................................................................... 16
Figure 4-3. Up to 256k x 16 External ROM Code .................................................................................. 16
Figure 4-4. Up to 512K x 8 External ROM Code ................................................................................... 17
Figure 4-5. Charge Pump ...................................................................................................................... 23
Figure 4-6. Power Supply Connection With Booster ............................................................................. 24
Figure 4-7. Power Supply Connection Without Booster ........................................................................ 24
Figure 4-8. Crystal Interface .................................................................................................................. 25
Figure 4-9. Minimum Stand-alone Hardware Configuration – Peripheral Only...................................... 26
Figure 6-1. Memory Map ....................................................................................................................... 29
Figure 7-1. Processor Control Registers ............................................................................................... 30
Figure 7-2. CPU Flags Register............................................................................................................. 30
Figure 7-3. Bank Register ...................................................................................................................... 31
Figure 7-4. Revision Register ................................................................................................................ 32
Figure 7-5. CPU Speed Register ........................................................................................................... 32
Figure 7-6. Power Control Register ....................................................................................................... 33
Figure 7-7. Interrupt Enable Register .................................................................................................... 35
Figure 7-8. Breakpoint Register ............................................................................................................. 36
Figure 7-9. USB Diagnostic Register..................................................................................................... 37
Figure 7-10. Memory Diagnostic Register ............................................................................................. 38
Figure 7-11. External Memory Control Registers .................................................................................. 39
Figure 7-12. Extended Page n Map Register ........................................................................................ 39
Figure 7-13. External Memory Control Register .................................................................................... 40
Figure 7-14. Timer Registers ................................................................................................................. 41
Figure 7-15. Watchdog Timer Register.................................................................................................. 41
Figure 7-16. Timer n Register................................................................................................................ 42
Figure 7-17. General USB Registers ..................................................................................................... 42
Figure 7-18. USB n Control Register ..................................................................................................... 42
Figure 7-19. USB Host Only Register .................................................................................................... 45
Figure 7-20. Host n Control Register ..................................................................................................... 45
Figure 7-21. Host n Address Register ................................................................................................... 46
Figure 7-22. Host n Count Register ....................................................................................................... 46
Figure 7-23. Host n Endpoint Status Register ....................................................................................... 47
Figure 7-24. Host n PID Register........................................................................................................... 48
Figure 7-25. Host n Count Result Register............................................................................................ 49
Figure 7-26. Host n Device Address Register ....................................................................................... 50
Figure 7-27. Host n Interrupt Enable Register ....................................................................................... 50
Figure 7-28. Host n Status Register ...................................................................................................... 52
Figure 7-29. Host n SOF/EOP Count Register ...................................................................................... 53
Figure 7-30. Host n SOF/EOP Counter Register................................................................................... 54
Figure 7-31. Host n Frame Register ...................................................................................................... 54
Figure 7-32. USB Device Only Registers .............................................................................................. 55
Figure 7-33. Device n Endpoint n Register............................................................................................ 55
Figure 7-34. Device n Endpoint n Address Register.............................................................................. 57
Figure 7-35. Device n Endpoint n Count Register ................................................................................. 57
Figure 7-36. Device n Endpoint n Status Register................................................................................. 58
Figure 7-37. Device n Endpoint n Count Result Register ...................................................................... 60
Figure 7-38. Device n Port Select Register ........................................................................................... 60
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PRELIMINARY
CY7C67300
LIST OF FIGURES (continued)
Figure 7-39. Device n Interrupt Enable Register ................................................................................... 61
Figure 7-40. Device n Address Register ................................................................................................ 63
Figure 7-41. Device n Status Register................................................................................................... 63
Figure 7-42. Device n Frame Number Register ..................................................................................... 65
Figure 7-43. Device n SOF/EOP Count Register .................................................................................. 66
Figure 7-44. OTG Registers .................................................................................................................. 66
Figure 7-45. OTG Control Register........................................................................................................ 66
Figure 7-46. GPIO Registers ................................................................................................................. 68
Figure 7-47. GPIO Control Register ...................................................................................................... 68
Figure 7-48. GPIO n Output Data Register............................................................................................ 70
Figure 7-49. GPIO n Input Data Register .............................................................................................. 70
Figure 7-50. GPIO n Direction Register................................................................................................. 71
Figure 7-51. IDE Registers .................................................................................................................... 71
Figure 7-52. IDE Mode Register ............................................................................................................ 71
Figure 7-53. IDE Start Address Register ............................................................................................... 72
Figure 7-54. IDE Stop Address Register ............................................................................................... 73
Figure 7-55. IDE Control Register ......................................................................................................... 73
Figure 7-56. HSS Registers ................................................................................................................... 75
Figure 7-57. HSS Control Register ........................................................................................................ 75
Figure 7-58. HSS Baud Rate Register................................................................................................... 77
Figure 7-59. HSS Transmit Gap Register.............................................................................................. 77
Figure 7-60. HSS Data Register ............................................................................................................ 78
Figure 7-61. HSS Receive Address Register ........................................................................................ 78
Figure 7-62. HSS Receive Counter Register ......................................................................................... 79
Figure 7-63. HSS Transmit Address Register ....................................................................................... 79
Figure 7-64. HSS Transmit Counter Register........................................................................................ 80
Figure 7-65. HPI Registers .................................................................................................................... 80
Figure 7-66. HPI Breakpoint Register .................................................................................................... 80
Figure 7-67. Interrupt Routing Register ................................................................................................. 81
Figure 7-68. SIEXmsg Register ............................................................................................................. 83
Figure 7-69. HPI Mailbox Register......................................................................................................... 83
Figure 7-70. HPI Status Port.................................................................................................................. 84
Figure 7-71. SPI Registers .................................................................................................................... 85
Figure 7-72. SPI Configuration Register ................................................................................................ 86
Figure 7-73. SPI Control Register.......................................................................................................... 87
Figure 7-74. SPI Interrupt Enable Register............................................................................................ 89
Figure 7-75. SPI Status Register ........................................................................................................... 90
Figure 7-76. SPI Interrupt Clear Register .............................................................................................. 90
Figure 7-77. SPI CRC Control Register................................................................................................. 91
Figure 7-78. SPI CRC Value Register ................................................................................................... 92
Figure 7-79. SPI Data Register.............................................................................................................. 92
Figure 7-80. SPI Transmit Address Register ......................................................................................... 93
Figure 7-81. SPI Transmit Count Register............................................................................................. 93
Figure 7-82. SPI Receive Address Register .......................................................................................... 93
Figure 7-83. SPI Receive Count Register.............................................................................................. 94
Figure 7-84. UART Registers ................................................................................................................ 94
Figure 7-85. UART Control Register...................................................................................................... 94
Figure 7-86. UART Status Register ....................................................................................................... 95
Figure 7-87. UART Data Register.......................................................................................................... 96
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PRELIMINARY
CY7C67300
LIST OF FIGURES (continued)
Figure 7-88. PWM Registers ................................................................................................................. 96
Figure 7-89. PWM Control Register....................................................................................................... 97
Figure 7-90. PWM Maximum Count Register ........................................................................................ 98
Figure 7-91. PWM n Start Register........................................................................................................ 99
Figure 7-92. PWM n Stop Register........................................................................................................ 99
Figure 7-93. PWM Cycle Count Register............................................................................................. 100
Figure 8-1. EZ-Host Pin Diagram ........................................................................................................ 101
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PRELIMINARY
CY7C67300
LIST OF TABLES
Table 4-1. Interface Options for GPIO Pins .......................................................................................... 12
Table 4-2. Interface Options for External Memory Bus Pins ................................................................. 12
Table 4-3. USB Port Configuration Options .......................................................................................... 13
Table 4-4. USB Interface Pins .............................................................................................................. 14
Table 4-5. OTG Interface Pins .............................................................................................................. 14
Table 4-6. External Memory Interface Pins .......................................................................................... 15
Table 4-7. UART Interface Pins ............................................................................................................ 17
Table 4-8. I2C EEPROM Interface Pins ............................................................................................... 18
Table 4-9. SPI Interface Pins ................................................................................................................ 18
Table 4-10. HSS Interface Pins ............................................................................................................ 19
Table 4-11. PWM Interface Pins ........................................................................................................... 19
Table 4-12. HPI Interface Pins[4, 5] ...................................................................................................................................................................20
Table 4-13. HPI Addressing .................................................................................................................. 21
Table 4-14. IDE Throughput ................................................................................................................. 21
Table 4-15. IDE Interface Pins .............................................................................................................. 22
Table 4-16. Charge Pump Interface Pins ............................................................................................. 23
Table 4-17. Charge Pump Interface Pins ............................................................................................. 25
Table 4-18. Crystal Pins ....................................................................................................................... 25
Table 4-19. Boot Configuration Interface .............................................................................................. 25
Table 5-1. Wake-up Sources ................................................................................................................ 27
Table 7-1. Bank Register Example ....................................................................................................... 31
Table 7-2. CPU Speed Definition .......................................................................................................... 32
Table 7-3. Force Select Definition ........................................................................................................ 38
Table 7-4. Memory Arbitration Select ................................................................................................... 38
Table 7-5. Period Select Definition ....................................................................................................... 41
Table 7-6. USB Data Line Pull-up and Pull-down Resistors ................................................................. 44
Table 7-7. Port A/B Force D± State ...................................................................................................... 44
Table 7-8. Port Select Definition ........................................................................................................... 47
Table 7-9. PID Select Definition ............................................................................................................ 49
Table 7-10. Mode Select Definition ....................................................................................................... 69
Table 7-11. Mode Select Definition ....................................................................................................... 72
Table 7-12. IDE PIO Port Registers ...................................................................................................... 74
Table 7-13. Scale Select Field Definition for SCK Frequency .............................................................. 86
Table 7-14. CRC Mode Definition ......................................................................................................... 91
Table 7-15. UART Baud Select Definition ............................................................................................ 95
Table 7-16. Prescaler Select Definition ................................................................................................ 97
Table 9-1. Pin Descriptions ................................................................................................................. 101
Table 12-1. Crystal Requirements ...................................................................................................... 105
Table 13-1. DC Characteristics ........................................................................................................... 106
Table 13-2. DC Characteristics: Charge Pump .................................................................................. 106
Table 15-1. Register Summary .......................................................................................................... 115
Table 16-1. Ordering Information ........................................................................................................ 119
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PRELIMINARY
1.0
CY7C67300
INTRODUCTION
EZ-Host™ (CY7C67300) is Cypress Semiconductor’s first full-speed, low-cost multi-port host/peripheral controller. EZ-Host is
designed to easily interface to most high-performance CPUs to add USB host functionality. EZ-Host has its own 16-bit RISC
processor to act as a coprocessor or operate in standalone mode. EZ-Host also has a programmable I/O interface block allowing
a wide range of interface options.
CY7C67300
Timer 0
Control
Timer 1
UART I/F
I2C
EEPROM I/F
Watchdog
CY16
16-bit RISC CORE
HSS I/F
Vbus, ID
OTG
PWM
USB-A
D+,D-
SIE1
Host/
Peripheral
USB Ports
D+,D-
USB-B
D+,D-
USB-A
SPI I/F
IDE I/F
SIE2
4Kx16
ROM BIOS
8Kx16
RAM
SHARED INPUT/OUTPUT PINS
nRESET
GPIO [31:0]
HPI I/F
USB-B
D+,D-
GPIO
X1
X2
PLL
Mobile
Power
Booster
External MEM I/F
(SRAM/ROM)
SHARED INPUT/OUTPUT PINS
A[15:0] D[15:0]
CTRL[9:0]
Figure 1-1. Block Diagram
1.1
EZ-Host Features
• Single-chip programmable USB dual role (Host/Peripheral) controller with two configurable Serial Interface Engines
(SIEs) and four USB ports
• Support for USB On-The-Go (OTG) protocol
• On-chip 48-MHz 16-bit processor with dynamically switchable clock speed
• Up to 16 bits of programmable bidirectional Data I/O
• Configurable I/O block supporting a variety of I/O options or up to 32 bits of General Purpose I/O (GPIO)
• 4K x 16 internal masked ROM containing built-in BIOS that supports a communication ready state with access to I2C
EEPROM Interface, external ROM, UART, or USB
• 8K x 16 internal RAM for code and data buffering
• Extended memory interface port for external SRAM and ROM
• 16-bit parallel Host Port Interface (HPI) with a DMA/Mailbox data path for an external processor to directly access all
of the on-chip memory and control on-chip SIEs
• Extended memory interface port for external SRAM and ROM
• Fast serial port supports from 9600 baud to 2.0 Mbaud
• SPI support in both master and slave
• On-chip 16-bit DMA/Mailbox data path interface
• Supports 12-MHz external crystal or clock
• 3.3V operation
• Package option — 100-pin TQFP
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PRELIMINARY
2.0
CY7C67300
Typical Applications
EZ-Host is a very powerful and flexible dual role USB controller that supports a wide variety of applications. It is primarily intended
to enable host capability in applications such as:
• Set-top boxes
• Printers
• KVM switches
• Kiosks
• Automotive applications
• Wireless access points.
3.0
Functional Overview
3.1
Processor Core
3.1.1
Processor
EZ-Host has a general-purpose 16-bit embedded RISC processor that runs at 48 MHz.
3.1.2
Clocking
EZ-Host requires a 12-MHz source for clocking. Either an external crystal or TTL level oscillator may be used. EZ-Host has an
internal PLL that produces a 48-MHz internal clock from the 12-MHz source.
3.1.3
Memory
EZ-Host has a built in 4Kx16 masked ROM and a 8Kx16 internal RAM. The masked ROM contains the EZ-Host BIOS. The internal
RAM can be used for program code or data.
3.1.4
Interrupts
EZ-Host provides 128 interrupt vectors. The first 48 vectors are hardware interrupts and the following 80 vectors are software
interrupts.
3.1.5
General Timers and Watchdog Timer
EZ-Host has two built in programmable timers and a Watchdog timer. All three timers can generate an interrupt to the EZ-Host.
3.1.6
Power Management
EZ-Host has one main power saving mode, Sleep. Sleep mode pauses all operations and provides the lowest power state.
4.0
Interface Descriptions
EZ-Host has a wide variety of interface options for connectivity. With several interface options available, EZ-Host can act as a
seamless data transport between many different types of devices.
Please see Table 4-1 and Table 4-2 to understand how the interfaces share pins and which can coexist. It should be noted that
some interfaces have more then one possible port location selectable through the GPIO Control Register [0xC006]. Below are
some general guidelines:
• HPI and IDE interfaces are mutually exclusive.
• If 16-bit external memory is required, then HSS and SPI default locations must be used.
• I2C EEPROM and OTG do not conflict with any interfaces.
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Table 4-1. Interface Options for GPIO Pins
GPIO Pins
GPIO31
GPIO30
GPIO29
GPIO28
GPIO27
GPIO26
GPIO25
GPIO24
GPIO23
GPIO22
GPIO21
GPIO20
GPIO19
GPIO18
GPIO17
GPIO16
GPIO15
GPIO14
GPIO13
GPIO12
GPIO11
GPIO10
GPIO9
GPIO8
GPIO7
GPIO6
GPIO5
GPIO4
GPIO3
GPIO2
GPIO1
GPIO0
HPI
IDE
PWM
HSS
SPI
UART
I2C
SCL/SDA
SCL/SDA
OTG
OTGID
TX[1]
RX[1]
INT
nRD
nWR
nCS
A1
A0
PWM3
CTS[1]
PWM2
PWM1
PWM0
RTS[1]
RXD[1]
TXD[1]
IOREADY
IOR
IOW
D15
D14
D13
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
CS1
CS0
A2
A1
A0
D15
D14
D13
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
MOSI[1]
SCK[1]
nSSI[1]
MISO[1]
TX[2]
RX[2]
Table 4-2. Interface Options for External Memory Bus Pins
MEM Pins
D15
D14
D13
D12
D11
D10
D9
D8
D[7:0]
A[18:0]
CONTROL
HPI
IDE
PWM
HSS
CTS2
RTS2
RXD2
TXD2
SPI
UART
I2C
OTG
MOSI[2]
SCK[2]
nSSI[2]
MISO[2]
Notes:
1. Default interface location.
2. Alternate interface location.
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4.1
CY7C67300
USB Interface
EZ-Host has two built-in Host/Peripheral SIEs and four USB transceivers that meet the USB 2.0 specification requirements for
full and low speed (high speed is not supported). In Host mode, EZ-Host supports four downstream ports, each support control,
interrupt, bulk, and isochronous transfers. In Peripheral mode, EZ-Host supports one peripheral port with eight endpoints for each
of the two SIEs. Endpoint 0 is dedicated as the control endpoint and only supports control transfers. Endpoints 1 though 7 support
Interrupt, Bulk (up to 64 Bytes/packet), or Isochronous transfers (up to 1023 Bytes/packet size). EZ-Host also supports a combination of Host and Peripheral ports simultaneously as shown in Table 4-3.
Table 4-3. USB Port Configuration Options
Port Configurations
Port 1A
Port 1B
Port 2A
Port 2B
OTG
OTG
–
–
–
OTG + 2 Hosts
OTG
–
Host
Host
OTG + 1 Host
OTG
–
Host
–
OTG + 1 Host
OTG
–
–
Host
OTG + 1 Peripheral
OTG
–
Peripheral
–
OTG + 1 Peripheral
OTG
–
–
Peripheral
4 Hosts
Host
Host
Host
Host
3 Hosts
Any Combination of Ports
2 Hosts
Any Combination of Ports
1 Host
Any Port
2 Hosts + 1 Peripheral
Host
Host
Peripheral
–
2 Hosts + 1 Peripheral
Host
Host
–
Peripheral
2 Hosts + 1 Peripheral
Peripheral
–
Host
Host
2 Hosts + 1 Peripheral
–
Peripheral
Host
Host
1 Host + 1 Peripheral
Host
–
Peripheral
–
1 Host + 1 Peripheral
Host
–
–
Peripheral
1 Host + 1 Peripheral
–
Host
–
Peripheral
1 Host + 1 Peripheral
–
Host
Peripheral
–
1 Host + 1 Peripheral
Peripheral
–
Host
–
1 Host + 1 Peripheral
Peripheral
–
–
Host
1 Host + 1 Peripheral
–
Peripheral
–
Host
1 Host + 1 Peripheral
–
Peripheral
Host
–
2 Peripherals
Peripheral
–
Peripheral
–
2 Peripherals
Peripheral
–
–
Peripheral
2 Peripherals
–
Peripheral
–
Peripheral
2 Peripherals
–
Peripheral
Peripheral
–
1 Peripheral
Any Port
4.1.1
USB Features
• USB 2.0-compliant for full and low speed
• Up to four downstream USB host ports
• Up to two upstream USB peripheral ports
• Configurable endpoint buffers (pointer and length), must reside in internal RAM
• Up to eight available peripheral endpoints (one control endpoint)
• Supports Control, Interrupt, Bulk, and Isochronous transfers
• Internal DMA channels for each endpoint
• Internal pull-up and pull-down resistors
• Internal Series termination resistors on USB data lines
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4.1.2
CY7C67300
USB Pins.
Table 4-4. USB Interface Pins
4.2
Pin Name
Pin Number
DM1A
22
DP1A
23
DM1B
18
DP1B
19
DM2A
9
DP2A
10
DM2B
4
DP2B
5
OTG Interface
EZ-Host has one USB port that is compatible with the USB On-The-Go supplement to the USB 2.0 specification. The USB OTG
port has a various hardware features to support Session Request Protocol (SRP) and Host Negotiation Protocol (HNP). OTG is
only supported on USB PORT 1A.
4.2.1
OTG Features
• Internal Charge Pump to supply and control VBUS
• VBUS Valid Status (above 4.4V)
• VBUS Status for 2.4V< VBUS <0.8V
• ID Pin Status
• Switchable 2KΩ internal discharge resistor on VBUS
• Switchable 500Ω internal Pull-up resistor on VBUS
• Individually switchable internal Pull-up and Pull-down resistors on the USB Data Lines
4.2.2
OTG Pins.
Table 4-5. OTG Interface Pins
4.3
Pin Name
Pin Number
DM1A
22
DP1A
23
OTGVBUS
11
OTGID
41
CSwitchA
13
CSwitchB
12
External Memory Interface
EZ-Host provides a port capable of interfacing to either external SRAM or ROM. This port consists of a separate address bus
and 8-/16-bit data bus.
4.3.1
External Memory Interface Features
• Supports 8-bit or 16-bit SRAM or ROM
• SRAM or ROM can be used for code or data space
• Direct addressing of SRAM or ROM
• Two external memory mapped page registers
4.3.2
External Memory Access Description
Access to external memory is sampled asynchronously on the rising edge of negative logic strobes with a minimum of 1 wait state
cycle. Up to 7 wait state cycles may be inserted for external memory access. Each additional wait state cycle stretches the external
memory access time by 20nsec. An external memory device with 15nsec access time is necessary to support 48MHz code
execution.
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4.3.3
CY7C67300
Program Memory Hole Description
Code residing in the 0xC000-0xC0FF address space is not accessible by the cpu.
4.3.4
External Memory Interface Pins.
Table 4-6. External Memory Interface Pins
Pin Name
nWR
Pin Number
64
nRD
nXMEMSEL (optional nCS)
62
34
nXROMSEL (ROM nCS)
nXRAMSEL (RAM nCS)
35
36
A18
A17
96
95
A16
A15
97
38
A14
A13
33
32
A12
A11
31
30
A10
A9
27
25
A8
A7
24
20
A6
17
A5
A4
8
7
A3
A2
3
2
A1
nBEL/A0
1
99
nBEH
D15
98
67
D14
D13
68
69
D12
D11
70
71
D10
D9
72
73
D8
D7
74
76
D6
D5
77
78
D4
D3
79
80
D2
D1
81
82
D0
83
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4.3.5
CY7C67300
External Memory Interface Block Diagrams[3]
Up to 256k x 16 External SRAM Data
EZ-Host
CY7C67300
A[18:1]
D[15:0]
nXRAMSEL
nBEL
A0/nBEH
nWR
nRD
External SRAM
Up to 256k x 16 Data
A[17:0]
D[15:0]
CE
BLE
BHE
WE
OE
Figure 4-1. Up to 256k x 16 External SRAM Data
Up to 512k x 8 External SRAM Data
EZ-Host
CY7C67300
A[18:0]
D[7:0]
nXRAMSEL
nWR
nRD
External SRAM
Up to 512k x8 Data
A[18:0]
D[7:0]
CE
WE
OE
Figure 4-2. Up to 512k x 8 External SRAM Data
Up to 256k x 16 External ROM Code
EZ-Host
CY7C67300
A[18:1]
D[15:0]
nXROMSEL
nBEL
A0/nBEH
nRD
External ROM
Up to 256k x 16 Code
A[17:0]
D[15:0]
CE
BLE
BHE
OE
Figure 4-3. Up to 256k x 16 External ROM Code
Note:
3. Address lines do not map directly.
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Up to 512k x 8 External ROM Code
EZ-Host
CY7C67300
External ROM
Up to 512k x8 Code
A[18:0]
D[7:0]
nXR0MSEL
nRD
A[18:0]
D[7:0]
CE
OE
Figure 4-4. Up to 512K x 8 External ROM Code
4.4
General Purpose I/O Interface (GPIO)
EZ-Host has up to 32 GPIO signals available. Several other optional interfaces use GPIO pins as well and may reduce the overall
number of available GPIOs.
4.4.1
GPIO Description
All Inputs are sampled asynchronously with state changes occurring at a rate of up to two 48-MHZ clock cycles. GPIO pins are
latched directly into registers, a single flip-flop.
4.4.2
Unused Pin Descriptions
Unused USB pins should be three-stated with the D+ line pulled high through the internal pull-up resistor and the D- line pulled
low through the internal pull-down resistor.
Unused GPIO pins should be configured as outputs and driven low.
4.5
UART Interface
EZ-Host has a built-in UART interface. The UART interface supports data rates from 900 to 115.2K baud. It can be used as a
development port or for other interface requirements. The UART interface is exposed through GPIO pins.
4.5.1
UART Features
• Supports baud rates of 900 to 115.2K
• 8-N-1
4.5.2
UART Pins.
Table 4-7. UART Interface Pins
4.6
Pin Name
Pin Number
TX
42
RX
43
I2C EEPROM Interface
EZ-Host provides a master only I2C interface for external serial EEPROMs. The serial EEPROM can be used to store application
specific code and data. This I2C interface is only to be used for loading code out of EEPROM, it is not a general I2C interface.
The I2C EEPROM interface is a BIOS implementation and is exposed through GPIO pins. Please refer to the BIOS documentation
for additional details on this interface.
4.6.1
I2C EEPROM Features
• Supports EEPROMs up to 64KB (512K bit)
• Auto-Detection of EEPROM size
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4.6.2
CY7C67300
I2C EEPROM Pins.
Table 4-8. I2C EEPROM Interface Pins
Pin Name
Pin Number
SMALL EEPROM
SCK
39
SDA
40
LARGE EEPROM
4.7
SCK
40
SDA
39
Serial Peripheral Interface
EZ-Host provides a SPI interface for added connectivity. EZ-Host may be configured as either an SPI master or SPI slave. The
SPI interface can be exposed through GPIO pins or the External Memory port.
4.7.1
SPI Features
• Master or slave mode operation
• DMA block transfer and PIO byte transfer modes
• Full duplex or half duplex data communication
• 8 byte receive FIFO and 8 byte transmit FIFO
• Selectable master SPI clock rates from 250 KHz to 12 MHz.
• Selectable master SPI clock phase and polarity
• Slave SPI signaling synchronization and filtering
• Slave SPI clock rates up to 2 MHz.
• Maskable interrupts for block and byte transfer modes
• Individual bit transfer for non-byte aligned serial communication in PIO mode
• Programmable delay timing for the active/in-active master SPI clock
• Auto or manual control for master mode slave select signal
• Complete access to internal memory
4.7.2
SPI Pins
The SPI port has a few different pin location options as shown in Table 4-9. The port location is selectable via the GPIO Control
Register [0xC006].
Table 4-9. SPI Interface Pins
Pin Name
Pin Number
Default Location
nSSI
56 or 65
SCK
61
MOSI
60
MISO
66
Alternate Location
4.8
nSSI
73
SCK
72
MOSI
71
MISO
74
High-speed Serial Interface
EZ-Host provides an HSS interface. The HSS interface is a programmable serial connection with baud rate from 9600 baud to
2.0 Mbaud. The HSS interface supports both byte and block mode operations as well as hardware and software handshaking.
Complete control of EZ-Host can be accomplished through this interface via an extensible API and communication protocol. The
HSS interface can be exposed through GPIO pins or the External Memory port.
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4.8.1
HSS Features
• 8 bits, no parity code
• Programmable baud rate from 9600 baud to 2 Mega baud
• Selectable 1 or 2 stop bit on transmit
• Programmable inter-character gap timing for Block Transmit
• 8 bytes receive FIFO
• Glitch filter on receive
• Block mode transfer directly to/from EZ-Host internal memory (DMA transfer)
• Selectable CTS/RTS hardware signal handshake protocol
• Selectable XON/XOFF software handshake protocol
• Programmable Receive interrupt, Block Transfer Done interrupts
• Complete access to internal memory
4.8.2
HSS Pins
The HSS port has a few different pin location options as shown in Table 4-10. The port location is selectable via the GPIO Control
Register [0xC006].
Table 4-10. HSS Interface Pins
Pin Name
Pin Number
Default Location
CTS
67
RTS
68
RX
69
TX
70
Alternate Location
4.9
CTS
44
RTS
53
RX
54
TX
55
Programmable Pulse/PWM Interface
EZ-Host has four built-in PWM output channels. Each channel provides a programmable timing generator sequence that can be
used to interface to various image sensors or other applications. The PWM interface is exposed through GPIO pins.
4.9.1
Programmable Pulse/PWM Features
• Four independent programmable waveform generators
• Programmable predefined frequencies ranging from 5.90KHz to 48MHz
• Configurable Polarity
• Continuous and One-Shot mode available
4.9.2
Programmable Pulse/PWM Pins.
Table 4-11. PWM Interface Pins
4.10
Pin Name
Pin Number
PWM3
44
PWM2
53
PWM1
54
PWM0
55
Host Port Interface
EZ-Host has an HPI interface. The HPI interface provides DMA access to the EZ-Host internal memory by an external host, plus
a bidirectional mailbox register for supporting high-level communication protocols. This port is designed to be the primary highDocument #: 38-08015 Rev. *D
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speed connection to a host processor. Complete control of EZ-Host can be accomplished through this interface via an extensible
API and communication protocol. Other than the HW communication protocols, a host processor has identical control over
EZ-Host whether connecting to the HPI or HSS port. The HPI interface is exposed through GPIO pins.
4.10.1 HPI Features
• 16-bit data bus interface
• 16 MB/s throughput
• Auto-Increment of address pointer for fast block mode transfers
• Direct memory access (DMA) to internal memory
• Bidirectional Mailbox register
• Byte Swapping
• Complete access to internal memory
• Complete control of SIEs through HPI
• Dedicated HPI Status Register
4.10.2
HPI Pins.
Table 4-12. HPI Interface Pins[4, 5]
Pin Name
Pin Number
INT
46
nRD
47
nWR
48
nCS
49
A1
50
A0
52
D15
56
D14
57
D13
58
D12
59
D11
60
D10
61
D9
65
D8
66
D7
86
D6
87
D5
89
D4
90
D3
91
D2
92
D1
93
D0
94
Notes:
4. HPI_INT is for the Outgoing Mailbox Interrupt.
5. HPI strobes are negative logic sampled on rising edge.
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The two HPI address pins are used to address one of four possible HPI port registers as shown in Table 4-13 below.
Table 4-13. HPI Addressing
4.11
HPI A[1:0]
A1
A0
HPI Data
0
0
HPI Mailbox
0
1
HPI Address
1
0
HPI Status
1
1
IDE Interface
EZ-Host has an IDE interface. The IDE interface supports PIO mode 0-4 as specified in the Information Technology-AT Attachment–4 with Packet Interface Extension (ATA/ATAPI-4) Specification, T13/1153D Rev 18. There is no need for firmware to use
programmable wait states. The CPU read/write cycle is automatically extended as needed for direct CPU to IDE read/write
accesses.
The EZ-Host IDE interface also has a BLOCK transfer mode that allows EZ-Host to read/write large blocks of data to/from the
IDE Data Register and move it to/from the EZ-Host onchip memory directly without intervention of the CPU. The IDE interface is
exposed through GPIO pins. Table 4-14 lists the achieved throughput for maximum block mode data transfer rate (with
IDE_IORDY true) for the various IDE PIO modes.
Table 4-14. IDE Throughput
Mode
ATA/ATAPI-4
Min Cycle Time
Actual
Min Cycle Time
ATA/ATPI-4
Max Transfer Rate
Actual
Max Transfer Rate
PIO Mode 0
600 ns
30T = 625 ns
3.33 MB/s
3.2 MB/s
PIO Mode 1
383 ns
20T = 416.7 ns
5.22 MB/s
4.8 MB/s
PIO Mode 2
240
13T = 270.8 ns
8.33 MB/s
7.38 MB/s
PIO Mode 3
180 ns
10T = 208.3 ns
11.11 MB/s
9.6 MB/s
PIO Mode 4
120 ns
8T = 166.7 ns
16.67 MB/s
12.0 MB/s
T = System clock period = 1/48MHz
4.11.1 IDE Features
• Programmable I/O mode 0-4
• Block mode transfers
• Direct memory access to/from internal memory through the IDE Data Register
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4.11.2
CY7C67300
IDE Pins
Table 4-15. IDE Interface Pins
4.11.3
Pin Name
Pin Number
IORDY
46
IOR
47
IOW
48
CS1
50
CS0
52
A2
53
A1
54
A0
55
D15
56
D14
57
D13
58
D12
59
D11
60
D10
61
D9
65
D8
66
D7
86
D6
87
D5
89
D4
90
D3
91
D2
92
D1
93
D0
94
Charge Pump Interface
VBUS for the USB OTG port can be produced by EZ-Host using its built-in charge pump and some external components. The
circuit connections should look similar to the diagram below.
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PRELIMINARY
D1
CY7C67300
D2
CSWITCHA
CY7C67300
CSWITCHB
C1
VBUS
OTGVBUS
C2
Figure 4-5. Charge Pump
Component details:
• D1 and D2: Schottky diodes with a current rating greater than 60 mA
• C1: Ceramic capacitor with a capacitance of 0.1 uF
• C2: Capacitor value should be no more that 6.5 uF since that is the maximum capacitance allowed by the USB OTG spec for
a dual-role device. The minimum value of C2 is 1 uF. There are no restrictions on the type of capacitor for C2.
If the VBUS charge pump circuit is not to be used, CSWITCHA, CSWITCHB, and OTGVBUS can be left unconnected.
4.11.4 Charge Pump Features
• Meets OTG Supplement Requirements, see the DC Characteristics: Charge Pump Table 13-2 for details.
4.11.5
Charge Pump Pins.
Table 4-16. Charge Pump Interface Pins
Pin Name
4.11.6
Pin Number
OTGVBUS
11
CSwitchA
13
CSwitchB
12
Booster Interface
EZ-Host has an on-chip power booster circuit for use with power supplies that range between 2.7V and 3.6V. The booster circuit
boosts the power to 3.3V nominal to supply power for the entire chip. The booster circuit requires an external inductor, diode, and
capacitor. During power down mode, the circuit is disabled to save power. The figure below shows how to connect the booster
circuit.
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CY7C67300
BOOSTVcc
L1
2.7V to 3.6V
power supply
VSWITCH
D1
3.3V
VCC
AVCC
C1
Figure 4-6. Power Supply Connection With Booster
Component details:
• L1: Inductor with inductance of 10 uH and a current rating of at least 250 mA
• D1: Schottky diode with a current rating of at least 250 mA
• C1: Tantalum or ceramic capacitor with a capacitance of at least 2.2 uF.
Figure 4-7 shows how to connect the power supply when the booster circuit is not being used.
BOOSTVcc
3.0V to 3.6V
power supply
VSWITCH
VCC
AVCC
Figure 4-7. Power Supply Connection Without Booster
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PRELIMINARY
4.11.7
CY7C67300
Booster Pins.
Table 4-17. Charge Pump Interface Pins
4.11.8
Pin Name
Pin Number
BOOSTVcc
16
VSWITCH
14
Crystal Interface
The recommended crystal circuit to be used with EZ-Host is shown in Figure 4-8 If an oscillator is used instead of a crystal circuit,
connect it to XTALIN and leave XTALOUT unconnected. For further information on the crystal requirements, see Crystal Requirements Table 12-1.
XTALIN
CY7C67300
Y1
XTALOUT
C1 = 22 pF
12MHz
Parallel Resonant
Fundamental Mode
500uW
20-33pf ±5%
C2 = 22 pF
Figure 4-8. Crystal Interface
4.11.9
Crystal Pins.
Table 4-18. Crystal Pins
Pin Name
Pin Number
XTALIN
29
XTALOUT
28
4.11.10 Boot Configuration Interface
EZ-Host can boot into any one of four modes. The mode it boots into is determined by the TTL voltage level of GPIO[31:30] at
the time nRESET is de-asserted. The table below shows the different boot pin combinations possible. After a reset pin event
occurs, the BIOS bootup procedure executes for up to 3ms. GPIO[31:30] are sampled by the BIOS during bootup only. After
bootup these pins are available to the application as GPIOs.
Table 4-19. Boot Configuration Interface
GPIO31 (Pin 39)
GPIO30 (Pin 40)
Boot Mode
0
0
Host Port Interface (HPI)
0
1
High Speed Serial (HSS)
1
0
Serial Peripheral Interface (SPI, slave mode)
1
1
I2C EEPROM (Standalone Mode)
GPIO[31:30] should be pulled high or low as needed using resistors tied to VCC or GND with resistor values between 5KΩ and
15KΩ. GPIO[31:30] should not be tied directly to VCC or GND. Note that in Standalone mode, the pull-ups on those two pins are
used for the serial I2C EEPROM (if implemented). The resistors used for these pull-ups should conform to the serial EEPROM
manufacturer’s requirements.
If any mode other then standalone is chosen, EZ-Host will be in coprocessor mode. The device will power up with the appropriate
communication interface enabled according to its boot pins and wait idle until a coprocessor communicates with it. See the BIOS
documentation for greater detail of the boot process.
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4.12
Operational Modes
4.12.1
Coprocessor Mode
CY7C67300
EZ-Host can act as a coprocessor to an external host processor. In this mode, an external host processor drives EZ-Host and is
the main processor rather then EZ-Host’s own 16-bit internal CPU. An external host processor may interface to EZ-Host through
one of the following three interfaces in coprocessor mode:
• HPI mode, a 16-bit parallel interface with up to 16 MBytes transfer rate
• HSS mode, a serial interface with up to 2 MBaud transfer rate
• SPI mode, a serial interface with up to 2 Mbits/s transfer rate.
At bootup GPIO[31:30] determine which of these three interfaces are used for coprocessor mode. Please see Table 4-19 for
details. Bootloading begins from the selected interface after POR + 3 ms of BIOS boot-up.
4.12.2
Stand-alone Mode
In stand-alone mode, there is no external processor connected to EZ-Host. Instead, EZ-Host’s own internal 16-bit CPU is the
main processor and firmware is typically downloaded from an EEPROM. Optionally, firmware may also be downloaded via USB.
Please see Table 4-19 for booting into stand-alone mode.
After booting into stand-alone mode (GPIO[31:30] = ‘11’), the following pins are effected:
• GPIO[31:20] are configured as output pins to examine the EEPROM contents
• GPIO[28:27] are enabled for debug UART mode
• GPIO[29] is configured for as OTGID for OTG applications on PORT1A
— If OTGID is logic 1 then PORT1A (OTG) is configured as a USB peripheral
— If OTGID is logic 0 then PORT1A (OTG) is configured as a USB host
• Ports 1B, 2A, and 2B default as USB peripheral ports
• All other pins remain INPUT pins.
4.12.2.1 Minimum Hardware Requirements for Stand-alone Mode – Peripheral Only
Minimum Standalone Hardware Configuration - Peripheral Only
EZ-Host
CY7C67300
VCC
VReg
Standard-B
or Mini-B
VBus
D+
Reset
Logic
nRESET
DPlus
DMinus
DGND
SHIELD
Bootstrap Options
Vcc Vcc
10k 10k
GPIO[30]
GPIO[31]
SCL*
SDA*
Int. 16k x8
Code / Data
VCC
A0
A1
A2
Up to 64k x8
EEPROM
GND
Bootloading Firmware
VCC
WP
SCL
SDA
22pf
XIN
12MHz
XOUT
22pf
*Bootloading begins after POR + 3ms BIOS bootup
*GPIO[31:30]
Up to 2k x8
2k x8 to 64k x8
31
30
SCL SDA
SDA SCL
* Parallel Resonant
Fundamental Mode
500uW
20-33pf ±5%
Figure 4-9. Minimum Stand-alone Hardware Configuration – Peripheral Only
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5.0
5.1
CY7C67300
Power Savings and Reset Description
Power Savings Mode Description
EZ-Host has one main power savings mode, Sleep. For detailed information on Sleep mode, please see section 5.2.
Sleep mode is used for USB applications to support USB suspend and non USB applications as the main chip power down mode.
5.2
Sleep
Sleep mode is the main chip power down mode and is also used for USB suspend. Sleep mode is entered by setting the Sleep
Enable (bit 1) of the Power Control Register [0xC00A]. During Sleep mode (USB Suspend) the following events and states are
true:
• GPIO pins maintain their configuration during sleep (in suspend)
• External Memory Address pins are driven low
• XTALOUT will be turned off
• Internal PLL will be turned off
• Firmware should disable the charge pump (OTG Control Register [0xC098]) causing OTGVBUS to drop below 0.2V. Otherwise
OTGVBUS will only drop to VCC – (2 schottky diode drops).
• Booster circuit will be turned off
• USB transceivers will be turned off
• CPU will suspend until a programmable wake-up event.
5.3
External (Remote) Wake-up Source
There are several possible events available to wake EZ-Host from Sleep mode as shown in Table 5-1. These may also be used
as remote wakeup options for USB applications. Please see the Power-down Control Register [0xC00A] for details.
Upon wake-up, code will begin executing within 200 µs, the time it takes the PLL to stabilize.
Table 5-1. Wake-up Sources
5.4
Wake-up Source
(if enabled)
Event
USB Resume
D+/D- Signaling
OTGVBUS
Level
OTGID
Any Edge
HPI
Read
HSS
Read
SPI
Read
IRQ1 (GPIO 25)
Any Edge
IRQ0 (GPIO 24)
Any Edge
Power-On-Reset Description
The length of the power-on-reset (POR) event is defined by (VCC ramp to valid) + (Crystal start up) + (PLL Stabilization). A typical
application might utilize a 10-ms power-on-reset event = ~5 ms + ~3 ms + 200 µs, respectively.
5.5
Reset Pin
The Reset pin is active low and requires a minimum pulse duration of 16 12-MHz clock cycles (1.3 µs). A reset event will restore
all registers to their default POR settings. Code execution will then begin 200 µs later at 0xFF00 with an immediate jump to
0xE000, the start of BIOS. Please refer to BIOS documentation for addition details.
5.6
USB Reset
A USB Reset will affect registers 0xC090 and 0xC0B0, all other registers remain unchanged.
Notes:
6. Read data will be discarded (dummy data)
7. HPI_INT will assert on a USB Resume
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6.0
6.1
CY7C67300
Memory Map
Mapping
The EZ-Host has 64K bytes of total addressable memory containing both program and data space. This memory space is byte
addressable. Figure 6-1 shows the various memory region address locations.
6.1.1
Internal Memory
Of the internal memory, 15K bytes is allocated for user’s program and data code. The lower memory space from 0x0000 to 0x0600
is reserved for interrupt vectors, general purpose registers, USB control registers, the stack, and other BIOS variables. The upper
internal memory space contains EZ-Host control registers from 0xC000 to 0xC0FF and the BIOS ROM itself from 0xE000 to
0xFFFF. For more information on the reserved lower memory or the BIOS ROM, please refer to the Programmers documentation
and the BIOS documentation.
During development with the EZ-Host toolset, the lower 1K byte of User’s space (0x0600 to 0x0A00) should be left available to
load the GDB stub. The GDB stub is required to allow the toolset debug access into EZ-Host.
6.1.2
External Memory
An external memory interface allows for additional program and data space to be added. 8K bytes of this space is reserved as
directly addressable external RAM for data. 16K bytes of the external memory space is addressable through two Extended Page
Map registers [0xC018, 0xC01A]. This 16K byte region of external memory can be configured to interface with either SRAM or
ROM through the External Memory Control Register [0xC03A]. This 16K region can be broken into two 8K regions, each of which
can be configured as SRAM or ROM.
The upper external memory space at 0xC100 is reserved for directly addressable external ROM. This allows for program code
to be stored and booted from an external ROM. Please refer to BIOS documentation for additional information on booting.
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PRELIMINARY
CY7C67300
Internal Mem ory
0x0000
HW INT’s
SW INT’s
0x0100
0x0144
Primary Registers
Swap Registers
Reserv ed
0x0200
USB Registers
0x0300
Reserved
0x0600
USER CODE
~15KB
External Mem ory
0x4000
8KB External RAM
0x8000
8KB Extended
Memory Page 1
SRAM/ROM
0xA000
8KB Extended
Memory Page 2
SRAM/ROM
0xC000
Control Registers
0xC100
0xE000
External ROM
Reserved
(8KB BIOS)
Figure 6-1. Memory Map
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PRELIMINARY
7.0
CY7C67300
Registers
7.1
Processor Control Registers
There are nine registers dedicated to general processor control. Each of these registers are covered in this section and are
summarized in Figure 7-1.
Register Name
CPU Flags Register
Register Bank Register
Hardware Revision Register
CPU Speed Register
Power Control Register
Interrupt Enable Register
Breakpoint Register
USB Diagnostic Register
Memory Diagnostic Register
Address
0xC000
0xC002
0xC004
0xC008
0xC00A
0xC00E
0xC014
0xC03C
0xC03E
R/W
R
R/W
R
R/W
R/W
R/W
R/W
W
W
Figure 7-1. Processor Control Registers
7.1.1
CPU Flags Register [0xC000] [R]
Bit #
15
14
13
12
Field
11
10
9
8
Reserved...
Read/Write
-
-
-
-
-
-
-
-
Default
0
0
0
0
0
0
0
0
Bit #
7
6
5
Field
...Reserved
4
3
2
1
0
Global
Interrupt
Enable
Negative
Flag
Overflow
Flag
Carry
Flag
Zero
Flag
Read/Write
-
-
-
R
R
R
R
R
Default
0
0
0
X
X
X
X
X
Figure 7-2. CPU Flags Register
Register Description
The CPU Flags Register is a read-only register that gives processor flags status.
Global Interrupt Enable (Bit 4)
The Global Interrupt Enable bit indicates if the Global Interrupts are enabled.
1: Enabled
0: Disabled
Negative Flag (Bit 3)
The Negative Flag bit indicates if an arithmetic operation results in a negative answer.
1: MS result bit is ‘1’
0: MS result bit is not ‘1’
Overflow Flag (Bit 2)
The Overflow Flag bit indicates if an overflow condition occurred. An overflow condition can occur if an arithmetic result was either
larger than the destination operand size (for addition) or smaller than the destination operand should allow for subtraction.
1: Overflow occurred
0: Overflow did not occur
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CY7C67300
Carry Flag (Bit 1)
The Carry Flag bit indicates if an arithmetic operation resulted in a Carry for addition, or borrow for subtraction.
1: Carry/Borrow occurred
0: Carry/Borrow did not occur
Zero Flag (Bit 0)
The Zero Flag bit indicates if an instruction execution resulted in a ‘0’.
1: Zero occurred
0: Zero did not occur
7.1.2
Bank Register [0xC002] [R/W]
Bit #
15
14
13
12
11
10
9
8
Read/Write
R/W
R/W
R/W
R/W
Default
0
0
R/W
R/W
R/W
R/W
0
0
0
0
0
1
Bit #
7
6
5
4
3
2
1
0
Field
Address...
Field
...Address
Reserved
Read/Write
R/W
R/W
R/W
-
-
-
-
-
Default
0
0
0
X
X
X
X
X
Figure 7-3. Bank Register
Register Description
The Bank Register maps registers R0-R15 into RAM. The eleven MSBs of this register are used as a base address for registers
R0-R15. A register address is automatically generated by:
1. Shifting the four LSBs of the register address left by 1.
2. ORing the four shifted bits of the register address with the twelve MSBs of the Bank Register.
3. Forcing the LSB to zero.
For example, if the Bank Register is left at its default value of 0x0100, and R2 is read, then the physical address 0x0102 will be
read. Please refer to Table 7-1 for details.
Table 7-1. Bank Register Example
Register
Hex Value
Binary Value
Bank
0x0100
0000 0001 0000 0000
R14
0x000E << 1 = 0x001C
0000 0000 0001 1100
RAM Location
0x011C
0000 0001 0001 1100
Address (Bits [15:4])
The Address field is used as a base address for all register addresses to start from.
Reserved
All reserved bits should be written as ‘0’.
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PRELIMINARY
7.1.3
CY7C67300
Hardware Revision Register [0xC004] [R]
Bit #
15
14
13
12
11
10
9
8
Read/Write
R
R
R
R
Default
X
X
R
R
R
R
X
X
X
X
X
X
Bit #
7
6
5
4
3
2
1
0
Read/Write
R
R
R
R
Default
R
R
R
R
X
X
X
X
X
X
X
X
Field
Revision...
Field
...Revision
Figure 7-4. Revision Register
Register Description
The Hardware Revision Register is a read-only register that indicates the silicon revision number. The first silicon revision is
represented by 0x0101. This number will be increased by one for each new silicon revision.
Revision (Bits [15:0])
The Revision field contains the silicon revision number.
7.1.4
CPU Speed Register [0xC008] [R/W]
Bit #
15
14
13
12
Field
11
10
9
8
Reserved...
Read/Write
-
-
-
-
-
-
-
-
Default
0
0
0
0
0
0
0
0
Bit #
7
6
5
4
3
2
1
0
Field
...Reserved
CPU Speed
Read/Write
-
-
-
-
R/W
R/W
R/W
R/W
Default
0
0
0
0
1
1
1
1
Figure 7-5. CPU Speed Register
Register Description
The CPU Speed Register allows the processor to operate at a user-selected speed. This register will only affect the CPU, all
other peripheral timing is still based on the 48-MHz system clock (unless otherwise noted).
CPU Speed (Bits[3:0])
The CPU Speed field is a divisor that selects the operating speed of the processor as defined in Table 7-2.
Table 7-2. CPU Speed Definition
CPU Speed [3:0]
Processor Speed
0000
48 MHz/1
0001
48 MHz/2
0010
48 MHz/3
0011
48 MHz/4
0100
48 MHz/5
0101
48 MHz/6
0110
48 MHz/7
0111
48 MHz/8
1000
48 MHz/9
1001
48 MHz/10
1010
48 MHz/11
1011
48 MHz/12
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PRELIMINARY
CY7C67300
Table 7-2. CPU Speed Definition (continued)
1100
48 MHz/13
1101
48 MHz/14
1110
48 MHz/15
1111
48 MHz/16
Reserved
All reserved bits should be written as ‘0’.
7.1.5
Power Control Register [0xC00A] [R/W]
Bit #
15
14
13
12
11
10
9
8
Field
Host/Device 2B
Wake
Enable
Host/Device 2A
Wake
Enable
Host/Device 1B
Wake
Enable
Host/Device 1A
Wake
Enable
OTG
Wake
Enable
Reserved
HSS
Wake
Enable
SPI
Wake
Enable
Read/Write
R/W
R/W
R/W
R/W
R/W
-
R/W
R/W
Default
0
0
0
0
0
0
0
0
6
Bit #
7
Field
HPI
Wake
Enable
5
Read/Write
R/W
-
-
Default
0
0
0
Reserved
4
3
2
1
0
GPI
Wake
Enable
Reserved
Boost 3V
OK
Sleep
Enable
Halt
Enable
R/W
-
R
R/W
R/W
0
0
0
0
0
Figure 7-6. Power Control Register
Register Description
The Power Control Register controls the power-down and wake-up options. Either the sleep mode or the halt mode options can
be selected. All other writable bits in this register can be used as a wake-up source while in sleep mode.
Host/Device 2B Wake Enable (Bit 15)
The Host/Device 2B Wake Enable bit enables or disables a wakeup condition to occur on a Host/Device 2B transition. This wake
up from the SIE port does not cause an interrupt to the on-chip CPU.
1: Enable wake-up on Host/Device 2B transition.
0: Disable wake-up on Host/Device 2B transition.
Host/Device 2A Wake Enable (Bit 14)
The Host/Device 2A Wake Enable bit enables or disables a wakeup condition to occur on an Host/Device 2A transition. This wake
up from the SIE port does not cause an interrupt to the on-chip CPU.
1: Enable wake-up on Host/Device 2A transition.
0: Disable wake-up on Host/Device 2A transition.
Host/Device 1B Wake Enable (Bit 13)
The Host/Device 1B Wake Enable bit enables or disables a wakeup condition to occur on an Host/Device 1B transition. This wake
up from the SIE port does not cause an interrupt to the on-chip CPU.
1: Enable wake-up on Host/Device 1B transition.
0: Disable wake-up on Host/Device 1B transition.
Host/Device 1A Wake Enable (Bit 12)
The Host/Device 1A Wake Enable bit enables or disables a wakeup condition to occur on an Host/Device 1A transition. This wake
up from the SIE port does not cause an interrupt to the on-chip CPU.
1: Enable wake-up on Host/Device 1A transition.
0: Disable wake-up on Host/Device 1A transition.
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CY7C67300
OTG Wake Enable (Bit 11)
The OTG Wake Enable bit enables or disables a wake-up condition to occur on either an OTG VBUS_Valid or OTG ID transition
(IRQ20).
1: Enable wake-up on OTG VBUS valid or OTG ID transition.
0: Disable wake-up on OTG VBUS valid or OTG ID transition.
HSS Wake Enable (Bit 9)
The HSS Wake Enable bit enables or disables a wake-up condition to occur on an HSS Rx serial input transition. The processor
may take several hundreds of microseconds before being operational after wake-up. Therefore, the incoming data byte that
causes the wake-up will be discarded.
1: Enable wake-up on HSS Rx serial input transition.
0: Disable wake-up on HSS Rx serial input transition.
SPI Wake Enable (Bit 8)
The SPI Wake Enable bit enables or disables a wake-up condition to occur on a falling SPI_nSS input transition. The processor
may take several hundreds of microseconds before being operational after wake-up. Therefore, the incoming data byte that
causes the wake-up will be discarded.
1: Enable wake-up on falling SPI nSS input transition.
0: Disable SPI_nSS interrupt.
HPI Wake Enable (Bit 7)
The HPI Wake Enable bit enables or disables a wake-up condition to occur on an HPI interface read.
1: Enable wake-up on HPI interface read.
0: Disable wake-up on HPI interface read.
GPI Wake Enable (Bit 4)
The GPI Wake Enable bit enables or disables a wake-up condition to occur on a GPIO(25:24) transition.
1: Enable wake-up on GPIO(25:24) transition.
0: Disable wake-up on GPIO(25:24) transition.
Boost 3V OK (Bit 2)
The Boost 3V OK bit is a read only bit that returns the status of the OTG Boost circuit.
1: Boost circuit not ok and internal voltage rails are below 3.0V.
0: Boost circuit ok and internal voltage rails are at or above 3.0V
Sleep Enable (Bit 1)
Setting this bit to ‘1’ will immediately initiate SLEEP mode. While in SLEEP mode, the entire chip is paused, achieving the lowest
standby power state. All operations are paused, the internal clock is stopped, the booster circuit and OTG VBUS charge pump
are all powered down, and the USB transceivers are powered down. All counters and timers are paused but will retain their values;
enabled PWM outputs freeze in their current states. SLEEP mode exits by any activity selected in this register. When SLEEP
mode ends, instruction execution will resume within 0.5 ms.
1: Enable Sleep mode.
0: No function.
Halt Enable (Bit 0)
Setting this bit to ‘1’ will immediately initiate HALT mode. While in HALT mode, only the CPU is stopped. The internal clock still
runs and all peripherals still operate, including the USB engines. The power saving using HALT in most cases will be minimal,
but in applications that are very CPU intensive the incremental savings may provide some benefit.
The HALT state is exited when any enabled interrupt is triggered. Upon exiting the HALT state, one or two instructions immediately
following the HALT instruction may be executed before the waking interrupt is serviced (you may want to follow the HALT
instruction with two NOPs).
1: Enable Halt mode.
0: No function.
Reserved
All reserved bits should be written as ‘0’.
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PRELIMINARY
7.1.6
CY7C67300
Interrupt Enable Register [0xC00E] [R/W]
Bit #
15
Field
14
13
Reserved
12
11
10
OTG
Interrupt
Enable
SPI
Interrupt
Enable
Reserved
9
8
Host/Device 2 Host/Device 1
Interrupt
Interrupt
Enable
Enable
Read/Write
-
-
-
R/W
R/W
-
R/W
R/W
Default
0
0
0
0
0
0
0
0
Bit #
7
6
5
4
3
2
1
0
Field
HSS
Interrupt
Enable
In Mailbox
Interrupt
Enable
Out Mailbox
Interrupt
Enable
Reserved
UART
Interrupt
Enable
GPIO
Interrupt
Enable
Timer 1
Interrupt
Enable
Timer 0
Interrupt
Enable
Read/Write
R/W
R/W
R/W
-
R/W
R/W
R/W
R/W
Default
0
0
0
1
0
0
0
0
Figure 7-7. Interrupt Enable Register
Register Description
The Interrupt Enable Register allows control of the hardware interrupt vectors.
OTG Interrupt Enable (Bit 12)
The OTG Interrupt Enable bit enables or disables the OTG ID/OTG4.4V Valid hardware interrupt.
1: Enable OTG interrupt.
0: Disable OTG interrupt.
SPI Interrupt Enable (Bit 11)
The SPI Interrupt Enable bit enables or disables the following three SPI hardware interrupts: SPI TX, SPI RX, and SPI DMA Block
Done.
1: Enable SPI interrupt.
0: Disable SPI interrupt.
Host/Device 2 Interrupt Enable (Bit 9)
The Host/Device 2 Interrupt Enable bit enables or disables all of the following Host/Device 2 hardware interrupts: Host 2 USB
Done, Host 2 USB SOF/EOP, Host 2 WakeUp/Insert/Remove, Device 2 Reset, Device 2 SOF/EOP or WakeUp from USB, Device
2 Endpoint n.
1: Enable Host 2 and Device 2 interrupt.
0: Disable Host 2 and Device 2 interrupt.
Host/Device 1 Interrupt Enable (Bit 8)
The Host/Device 1 Interrupt Enable bit enables or disables all of the following Host/Device 1 hardware interrupts: Host 1 USB
Done, Host 1 USB SOF/EOP, Host 1 WakeUp/Insert/Remove, Device 1 Reset, Device 1 SOF/EOP or WakeUp from USB, Device
1Endpoint n.
1: Enable Host 1 and Device 1 interrupt.
0: Disable Host 1 and Device 1 interrupt.
HSS Interrupt Enable (Bit 7)
The HSS Interrupt Enable bit enables or disables the following High-speed Serial Interface hardware interrupts: HSS Block Done,
and HSS RX Full.
1: Enable HSS interrupt.
0: Disable HSS interrupt.
In Mailbox Interrupt Enable (Bit 6)
The In Mailbox Interrupt Enable bit enables or disables the HPI: Incoming Mailbox hardware interrupt.
1: Enable MBXI interrupt.
0: Disable MBXI interrupt.
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PRELIMINARY
CY7C67300
Out Mailbox Interrupt Enable (Bit 5)
The Out Mailbox Interrupt Enable bit enables or disables the HPI: Outgoing Mailbox hardware interrupt.
1: Enable MBXO interrupt.
0: Disable MBXO interrupt.
UART Interrupt Enable (Bit 3)
The UART Interrupt Enable bit enables or disables the following UART hardware interrupts: UART TX, and UART RX.
1: Enable UART interrupt.
0: Disable UART interrupt.
GPIO Interrupt Enable (Bit 2)
The GPIO Interrupt Enable bit enables or disables the General Purpose I/O Pins Interrupt (See the GPIO Control Register). When
GPIO bit is reset, all pending GPIO interrupts are also cleared
1: Enable GPIO interrupt.
0: Disable GPIO interrupt.
Timer 1 Interrupt Enable (Bit 1)
The Timer 1 Interrupt Enable bit enables or disables the TImer1 Interrupt Enable. When this bit is reset, all pending Timer 1
interrupts are cleared.
1: Enable TM1 interrupt.
0: Disable TM1 interrupt.
Timer 0 Interrupt Enable (Bit 0)
The Timer 0 Interrupt Enable bit enables or disables the TImer0 Interrupt Enable. When this bit is reset, all pending Timer 0
interrupts are cleared.
1: Enable TM0 interrupt.
0: Disable TM0 interrupt.
Reserved
All reserved bits should be written as ‘0’.
7.1.7
Breakpoint Register [0xC014] [R/W]
Bit #
15
14
13
12
Field
11
10
9
8
Address...
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Default
0
0
0
0
0
0
0
0
Bit #
7
6
5
4
3
2
1
0
Field
...Address
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Default
0
0
0
0
0
0
0
0
Figure 7-8. Breakpoint Register
Register Description
The Breakpoint Register holds the breakpoint address. When the program counter match this address, the INT127 interrupt
occurs. To clear this interrupt, a zero value should be written to this register.
Address (Bits [15:0])
The Address field is a 16-bit field containing the breakpoint address.
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PRELIMINARY
7.1.8
CY7C67300
USB Diagnostic Register [0xC03C] [R/W]
Bit #
15
14
13
12
11
10
9
8
Field
Port 2B
Diagnostic
Enable
Port 2A
Diagnostic
Enable
Port 1B
Diagnostic
Enable
Port 1A
Diagnostic
Enable
Read/Write
R/W
R/W
R/W
R/W
-
-
-
-
Default
0
0
0
0
0
0
0
0
Bit #
7
6
5
4
3
2
1
0
Field
...Reserved
Pull-down
Enable
LS Pull-up
Enable
FS Pull-up
Enable
Reserved
Read/Write
-
R/W
R/W
R/W
-
R/W
R/W
R/W
Default
0
0
0
0
0
0
0
0
Reserved...
Force Select
Figure 7-9. USB Diagnostic Register
Register Description
The USB Diagnostic Register provides control of diagnostic modes. It is intended for use by device characterization tests, not for
normal operations. This register is Read/Write by the on-chip CPU but is write only via the HPI port.
Port 2B Diagnostic Enable (Bit 15)
The Port 2B Diagnostic Enable bit enables or disables Port 2B for the test conditions selected in this register.
1: Apply any of the following enabled test conditions: J/K, DCK, SE0, RSF, RSL, PRD.
0: Do not apply test conditions.
Port 2A Diagnostic Enable (Bit 14)
The Port 2A Diagnostic Enable bit enables or disables Port 2A for the test conditions selected in this register.
1: Apply any of the following enabled test conditions: J/K, DCK, SE0, RSF, RSL, PRD.
0: Do not apply test conditions.
Port 1B Diagnostic Enable (Bit 13)
The Port 1B Diagnostic Enable bit enables or disables Port 1B for the test conditions selected in this register.
1: Apply any of the following enabled test conditions: J/K, DCK, SE0, RSF, RSL, PRD.
0: Do not apply test conditions.
Port 1A Diagnostic Enable (Bit 12)
The Port 1A Diagnostic Enable bit enables or disables Port 1A for the test conditions selected in this register.
1: Apply any of the following enabled test conditions: J/K, DCK, SE0, RSF, RSL, PRD.
0: Do not apply test conditions.
Pull-down Enable (Bit 6)
The Pull-down Enable bit enables or disables full-speed pull-down resistors (pull-down on both D+ and D–) for testing.
1: Enable pull-down resistors on both D+ and D–.
0: Disable pull-down resistors on both D+ and D–.
LS Pull-up Enable (Bit 5)
The LS Pull-up Enable bit enables or disables a low-speed pull-up resistor (pull-up on D–) for testing.
1: Enable low-speed pull-up resistor on D–.
0: Pull-up resistor is not connected on D–.
FS Pull-up Enable (Bit 4)
The FS Pull-up Enable bit enables or disables a full-speed pull-up resistor (pull up on D+) for testing.
1: Enable full-speed pull-up resistor on D+.
0: Pull-up resistor is not connected on D+.
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CY7C67300
Force Select (Bits [2:0])
The Force Select field bit selects several different test condition states on the data lines (D+/D–). Please refer to Table 7-3 for
details.
Table 7-3. Force Select Definition
Force Select [2:0]
Data Line State
1xx
Assert SE0
01x
Toggle JK
001
Assert J
000
Assert K
Reserved
All reserved bits should be written as ‘0’.
7.1.9
Memory Diagnostic Register [0xC03E] [W]
Bit #
15
14
Field
13
12
11
10
Reserved
9
8
Memory
Arbitration
Select
Read/Write
-
-
-
-
-
W
W
W
Default
0
0
0
0
0
0
0
0
Bit #
7
6
5
4
3
2
1
Field
Reserved
0
Monitor
Enable
Read/Write
-
-
-
-
-
-
-
W
Default
0
0
0
0
0
0
0
0
Figure 7-10. Memory Diagnostic Register
Register Description
The Memory Diagnostic Register provides control of diagnostic modes.
Memory Arbitration Select (Bits[10:8])
The Memory Arbitration Select field is defined in Table 7-4.
Table 7-4. Memory Arbitration Select
Memory Arbitration
Select [3:0]
Memory Arbitration Timing
111
1/8, 7 of every 8 cycles dead
110
2/8, 6 of every 8 cycles dead
101
3/8, 5 of every 8 cycles dead
100
4/8, 4 of every 8 cycles dead
011
5/8, 3 of every 8 cycles dead
010
6/8, 2 of every 8 cycles dead
001
7/8, 1 of every 8 cycles dead
000
8/8, all cycles available
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Monitor Enable (Bit 0)
The Monitor Enable bit enables or disables monitor mode. In monitor mode the internal address bus is echoed to the external
address pins.
1: Enable monitor mode.
0: Disable monitor mode.
Reserved
All reserved bits should be written as ‘0’.
7.2
External Memory Registers
There are four registers dedicated to controlling the external memory interface. Each of these registers are covered in this section
and are summarized in Figure 7-11
Register Name
Extended Page 1 Map Register
Extended Page 2 Map Register
External Memory Control Register
Address
0xC018
0xC01A
0xC03A
R/W
R/W
R/W
R/W
Figure 7-11. External Memory Control Registers
7.2.1
Extended Page n Map Register [R/W]
• Extended Page 1 Map Register 0xC018
• Extended Page 2 Map Register 0xC01A
Bit #
15
14
13
12
Field
11
10
9
8
Address...
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Default
0
0
0
0
0
0
0
0
Bit #
7
6
5
4
3
2
1
0
Field
...Address
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Default
0
0
0
0
0
0
0
0
Figure 7-12. Extended Page n Map Register
Register Description
The Extended Page n Map Register contains the Page n high-order address bits. These bits are always appended to accesses
to the Page n Memory mapped space.
Address (Bits [15:0])
The Address field contains the high-order bits 28 to 13 of the Page n address. The address pins [8:0] (Page n address [21:13])
will reflect the content of this register when the CPU accesses the address 0x8000-0x9FFF. For the SRAM mode, the address
pin on [4:0] (Page n address [17:13]) will be used.
Bit [8] (Page n address [21]) should be set to ‘0’, so that Page n reads/writes will access external areas (SRAM, ROM or
peripherals). nXMEMSEL will be the external Chip Select for this space
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PRELIMINARY
7.2.2
CY7C67300
External Memory Control Register [0xC03A] [R/W]
Bit #
15
Field
14
13
Reserved
12
XRAM Merge XROM Merge
Enable
Enable
11
10
XMEM Width
Select
9
8
XMEM Wait
Select
Read/Write
-
-
R/W
R/W
R/W
R/W
R/W
R/W
Default
X
X
X
X
X
X
X
X
Bit #
7
6
5
4
3
2
1
0
Field
XROM Width
Select
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Default
X
X
X
X
X
X
X
X
XROM Wait
Select
XRAM Width
Select
XRAM Wait
Select
Figure 7-13. External Memory Control Register
Register Description
The External Memory Control Register provides control of Wait States for the external SRAM or ROM. All wait states are based
off of 48 MHz.
XRAM Merge Enable (Bit 13)
The XRAM Merge Enable bit will enable or disable the RAM merge feature. When the RAM merge feature is enabled, the
nXRAMSEL will be active when ever the nXMEMSEL is active.
1: Enable RAM merge.
0: Disable RAM merge.
XROM Merge Enable (Bit 12)
The XROM Merge Enable bit will enable or disable the ROM merge feature. When the ROM merge feature is enabled, the
nXROMSEL will be active when ever the nXMEMSEL is active.
1: Enable ROM merge.
0: Disable ROM merge.
XMEM Width Select (Bit 11)
The XMEM Width Select bit selects the extended memory width.
1: Extended memory = 8.
0: Extended memory = 16.
XMEM Wait Select (Bits [10:8])
The XMEM Wait Select field selects the extended memory wait state from 0 to 7.
XROM Width Select (Bit 7)
The XROM Width Select bit selects the external ROM width.
1: External memory = 8.
0: External memory = 16.
XROM Wait Select (Bits[6:4])
The XROM Wait Select field selects the external ROM wait state from 0 to 7.
XRAM Width Select (Bit 3)
The XRAM Width Select bit selects the external RAM width.
1: External memory = 8.
0: External memory = 16.
XRAM Wait Select (Bits[2:0])
The XRAM Wait Select field selects the external RAM wait state from 0 to 7.
Reserved
All reserved bits should be written as ‘0’.
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7.3
CY7C67300
Timer Registers
There are three registers dedicated to timer operations. Each of these registers are discussed in this section and are summarized
in Figure 7-14.
Register Name
Watchdog Timer Register
Timer 0 Register
Timer 1 Register
Address
0xC00C
0xC010
0xC012
R/W
R/W
R/W
R/W
Figure 7-14. Timer Registers
7.3.1
Watchdog Timer Register [0xC00C] [R/W]
Bit #
15
14
13
12
Field
11
10
9
8
Reserved...
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Default
0
0
0
0
0
0
0
0
Bit #
7
5
4
Field
6
...Reserved
Time-out
Flag
3
Period
Select
2
1
0
Lock
Enable
WDT
Enable
Reset
Strobe
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
W
Default
0
0
0
0
0
0
0
0
Figure 7-15. Watchdog Timer Register
Register Description
The Watchdog Timer Register provide status and control over the Watchdog timer. The Watchdog timer can also interrupt the
processor.
Time-out Flag (Bit 5)
The Time-out Flag bit indicates if the Watchdog timer has expired. The processor can read this bit after exiting a reset to determine
if a Watchdog time-out occurred. This bit will be cleared on the next external hardware reset.
1: Watchdog timer expired.
0: Watchdog timer did not expire.
Period Select (Bits [4:3])
The Period Select field is defined in Table 7-5. If this time expires before the Reset Strobe bit is set, the internal processor will
get reset.
Table 7-5. Period Select Definition
Period Select[4:3]
WDT Period Value
00
1.4 ms
01
5.5 ms
10
22.0 ms
11
66.0 ms
Lock Enable (Bit 2)
The Lock Enable bit will not allow any writes to this register until a reset. In doing so the Watchdog timer can be set up and enabled
permanently so that it can only be cleared on reset (the WDT Enable bit is ignored).
1: Watchdog timer permanently set.
0: Watchdog timer not permanently set.
WDT Enable (Bit 1)
The WDT Enable bit enables or disables the Watchdog timer.
1: Enable Watchdog timer operation.
0: Disable Watchdog timer operation.
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Reset Strobe (Bit 0)
The Reset Strobe is a write-only bit that resets the Watchdog timer count. It must be set to ‘1’ before the count expires to avoid
a Watchdog trigger
1: Reset Count
Reserved
All reserved bits should be written as ‘0’.
7.3.2
Timer n Register [R/W]
• Timer 0 Register 0xC010.
• Timer 1 Register 0xC012.
Bit #
15
14
13
12
Field
11
10
9
8
Count...
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Default
1
1
1
1
1
1
1
1
Bit #
7
6
5
4
3
2
1
0
Field
...Count
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Default
1
1
1
1
1
1
1
1
Figure 7-16. Timer n Register
Register Description
The Timer n Register sets the Timer n count. Both Timer 0 and Timer 1 decrement by one every 1-µs clock tick. Each can provide
an interrupt to the CPU when the timer reaches zero.
Count (Bits [15:0])
The Count field sets the Timer count.
7.4
General USB Registers
There is one set of register dedicated to general USB control. This set consists of two identical registers, one for Host/Device
Port 1 and one for Host/Device Port 2. This register set has functions for both USB host and USB peripheral options and is covered
in this section and summarized in Figure 7-8. USB Host only registers are covered in section 4.5, and USB device-only registers
are covered in section 7.2.
Register Name
USB n Control Register
Address (SIE1 / SIE2)
0xC08A / 0xC0AA
R/W
R/W
Figure 7-17. General USB Registers
7.4.1
USB n Control Register [R/W]
• USB 1 Control Register 0xC08A.
• USB 2 Control Register 0xC0AA.
Bit #
15
14
13
12
11
10
9
8
Field
Port B
D+
Status
Port B
D–
Status
Port A
D+
Status
Port A
D–
Status
LOB
LOA
Mode
Select
Port B
Resistors
Enable
Read/Write
R
R
R
R
R/W
R/W
R/W
R/W
Default
X
X
X
X
0
0
0
0
6
5
4
Bit #
7
Field
Port A
Resistors
Enable
Read/Write
R/W
R/W
R/W
R/W
Default
0
0
0
0
Port B
Force D±
State
3
2
1
0
Suspend
Enable
Port B
SOF/EOP
Enable
Port A
SOF/EOP
Enable
R/W
R/W
R/W
R/W
0
0
0
0
Port A
Force D±
State
Figure 7-18. USB n Control Register
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Register Description
The USB n Control Register is used in both host and device mode. It monitors and controls the SIE and the data lines of the USB
ports. This register can be accessed by the HPI interface.
Port B D+ Status (Bit 15)
The Port B D+ Status bit is a read-only bit that indicates the value of DATA+ on Port B.
1: D+ is HIGH.
0: D+ is LOW.
Port B D– Status (Bit 14)
The Port B D– Status bit is a read-only bit that indicates the value of DATA– on Port B.
1: D– is HIGH.
0: D– is LOW.
Port A D+ Status (Bit 13)
The Port A D+ Status bit is a read-only bit that indicates the value of DATA+ on Port A.
1: D+ is HIGH.
0: D+ is LOW.
Port A D– Status (Bit 12)
The Port A D– Status bit is a read-only bit that indicates the value of DATA– on Port A.
1: D– is HIGH.
0: D– is LOW.
LOB (Bit 11)
The LOB bit selects the speed of Port B.
1: Port B is set to low-speed mode.
0: Port B is set to full-speed mode.
LOA (Bit 10)
The LOA bit selects the speed of Port A.
1: Port A is set to low-speed mode.
0: Port A is set to full-speed mode.
Mode Select (Bit 9)
The Mode Select bit sets the SIE for host or device operation. When set for device operation only one USB port is supported.
The active port is selected by the Port Select bit in the Host n Count Register.
1: Host mode.
0: Device mode.
Port B Resistors Enable (Bit 8)
The Port B Resistors Enable bit enables or disables the pull-up/pull-down resistors on Port B. When enabled, the Mode Select
bit and LOB bit of this Register will set the pull-up/pull-down resistors appropriately. When the Mode Select is set for Host mode,
the pull-down resistors on the data lines (D+ and D–) are enabled. When the Mode Select is set for Device mode, a single pullup resistor on either D+ or D–, determined by the LOB bit, will be enabled. Please see Table 7-6 for details.
1: Enable pull-up/pull-down resistors.
0: Disable pull-up/pull-down resistors.
Port A Resistors Enable (Bit 7)
The Port A Resistors Enable bit enables or disables the pull-up/pull-down resistors on Port A. When enabled, the Mode Select
bit and LOA bit of this Register will set the pull-up/pull-down resistors appropriately. When the Mode Select is set for Host mode,
the pull-down resistors on the data lines (D+ and D–) are enabled. When the Mode Select is set for Device mode, a single pullup resistor on either D+ or D–, determined by the LOA bit, will be enabled. Please see Table 7-6 for details.
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1: Enable pull-up/pull-down resistors.
0: Disable pull-up/pull-down resistors
Table 7-6. USB Data Line Pull-up and Pull-down Resistors
L0A/L0B
Mode Select
Port n Resistors
Enable
X
X
0
Pull-up/Pull-down on D+ and D– Disabled
X
1
1
Pull-down on D+ and D– Enabled
1
0
1
Pull-up on USB D– Enabled
0
0
1
Pull-up on USB D+ Enabled
Function
Port B Force D± State (Bits [6:5])
The Port B Force D± State field controls the forcing state of the D+ D– data lines for Port B. This field will force the state of the
Port B data lines independent of the Port Select bit setting. See Table 7-7 for details.
Port A Force D± State (Bits [4:3])
The Port A Force D± State field controls the forcing state of the D+ D– data lines for Port A. This field will force the state of the
Port A data lines independent of the Port Select bit setting. See Table 7-7 for details.
Table 7-7. Port A/B Force D± State
Port A/B Force D± State
Function
0
0
Normal Operation
0
1
Force USB Reset, SE0 State
1
0
Force J-State
1
1
Force K-State
Suspend Enable (Bit 2)
The Suspend Enable bit enables or disables the suspend feature on both ports. When suspend is enabled the USB transceivers
are powered down and can not transmit or received USB packets but can still monitor for a wakeup condition.
1: Enable suspend.
0: Disable suspend.
Port B SOF/EOP Enable (Bit 1)
The Port B SOF/EOP Enable bit is only applicable in host mode. In device mode this bit should be written as ‘0’. In host mode
this bit enables or disables SOFs or EOPs for Port B. Either SOFs or EOPs will be generated depending on the LOB bit in the
USB n Control Register when Port B is active.
1: Enable SOFs or EOPs.
0: Disable SOFs or EOPs.
Port A SOF/EOP Enable (Bit 0)
The Port A SOF/EOP Enable bit is only applicable in host mode. In device mode this bit should be written as ‘0’. In host mode
this bit enables or disables SOFs or EOPs for Port A. Either SOFs or EOPs will be generated depending on the LOA bit in the
USB n Control Register when Port A is active.
1: Enable SOFs or EOPs.
0: Disable SOFs or EOPs.
Reserved
All reserved bits should be written as ‘0’.
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PRELIMINARY
7.5
CY7C67300
USB Host Only Registers
There are twelve sets of dedicated registers for USB host only operation. Each set consists of two identical registers (unless
otherwise noted), one for Host Port 1 and one for Host Port 2. These register sets are covered in this section and summarized
in Figure 7-19.
Register Name
Host n Control Register
Host n Address Register
Host n Count Register
Host n Endpoint Status Register
Host n PID Register
Host n Count Result Register
Host n Device Address Register
Host n Interrupt Enable Register
Host n Status Register
Host n SOF/EOP Count Register
Host n SOF/EOP Counter Register
Host n Frame Register
Address (Host 1 / Host 2)
0xC080 / 0xC0A0
0xC082 / 0xC0A2
0xC084 / 0xC0A4
0xC086 / 0xC0A6
0xC086 / 0xC0A6
0xC088 / 0xC0A8
0xC088 / 0xC0A8
0xC08C / 0xC0AC
0xC090 / 0xC0B0
0xC092 / 0xC0B2
0xC094 / 0xC0B4
0xC096 / 0xC0B6
R/W
R/W
R/W
R/W
R
W
R
W
R/W
R/W
R/W
R
R
Figure 7-19. USB Host Only Register
7.5.1
Host n Control Register [R/W]
• Host 1 Control Register 0xC080.
• Host 2 Control Register 0xC0A0.
Bit #
15
14
13
12
Field
11
10
9
8
Reserved
Read/Write
-
-
-
-
-
-
-
-
Default
0
0
0
0
0
0
0
0
3
2
1
Bit #
7
6
5
4
Field
Preamble
Enable
Sequence
Select
Sync
Enable
ISO
Enable
Read/Write
R/W
R/W
R/W
R/W
-
-
-
R/W
Default
0
0
0
0
0
0
0
0
Reserved
0
Arm
Enable
Figure 7-20. Host n Control Register
Register Description
The Host n Control Register allows high-level USB transaction control.
Preamble Enable (Bit 7)
The Preamble Enable bit enables or disables the transmission of a preamble packet before all low speed packets. This bit should
only be set when communicating with a low-speed device.
1: Enable Preamble packet.
0: Disable Preamble packet.
Sequence Select (Bit 6)
The Sequence Select bit sets the data toggle for the next packet. This bit has no effect on receiving data packets, sequence
checking must be handled in firmware.
1: Send DATA1.
0: Send DATA0.
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Sync Enable (Bit 5)
The Sync Enable bit will synchronize the transfer with the SOF packet in full speed mode and the EOP packet in low-speed mode.
1: The next enabled packet will be transferred after the SOF or EOP packet is transmitted.
0: The next enabled packet will be transferred as soon as the SIE is free.
ISO Enable (Bit 4)
The ISO Enable bit enables or disables an Isochronous transaction.
1: Enable Isochronous transaction.
0: Disable Isochronous transaction.
Arm Enable (Bit 0)
The Arm Enable bit arms an endpoint and starts a transaction. This bit is automatically cleared to ‘0’ when a transaction is
complete.
1: Arm endpoint and begin transaction.
0: Endpoint disarmed.
Reserved
All reserved bits should be written as ‘0’.
7.5.2
Host n Address Register [R/W]
• Host 1 Address Register 0xC082.
• Host 2 Address Register 0xC0A2.
Bit #
15
14
13
12
Field
11
10
9
8
Address...
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Default
0
0
0
0
0
0
0
0
Bit #
7
6
5
4
3
2
1
0
Field
...Address
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Default
0
0
0
0
0
0
0
0
Figure 7-21. Host n Address Register
Register Description
The Host n Address Register is used as the base pointer into memory space for the current host transactions.
Address (Bits [15:0])
The Address field sets the address pointer into internal RAM or ROM.
7.5.3
Host n Count Register [R/W]
• Host 1 Count Register 0xC084.
• Host 2 Count Register 0xC0A4.
Bit #
15
14
Field
Reserved
Port
Select
13
12
11
10
9
Read/Write
-
R/W
-
-
-
-
R/W
R/W
Default
0
0
0
0
0
0
0
0
Bit #
7
6
5
4
3
2
1
0
Reserved
Field
8
Count...
...Count
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Default
0
0
0
0
0
0
0
0
Figure 7-22. Host n Count Register
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Register Description
The Host n Count Register is used to hold the number of bytes (packet length) for the current transaction. The maximum packet
length is 1023 bytes in ISO mode. The Host Count value is used to determine how many bytes to transmit, or the maximum
number of bytes to receive. If the number of received bytes is greater then the Host Count value then an overflow condition will
be flagged by the Overflow bit in the Host n Endpoint Status Register.
Port Select (Bit 14)
The Port Select bit selects which of the two active ports is selected and is summarized in Table 7-8.
1: Port 1B or Port 2B is enabled.
0: Port 1A or Port 2A is enabled.
Table 7-8. Port Select Definition
Port Select
Host/Device 1
Active Port
Host/Device 2
Active Port
0
A
A
1
B
B
Count (Bits [9:0])
The Count field sets the value for the current transaction data packet length. This value is retained when switching between host
and device mode, and back again.
Reserved
All reserved bits should be written as ‘0’.
7.5.4
Host n Endpoint Status Register [R]
• Host 1 Endpoint Status Register 0xC086.
• Host 2 Endpoint Status Register 0xC0A6.
Bit #
15
14
Field
13
12
Reserved
11
10
Overflow
Flag
Underflow
Flag
9
8
Reserved
Read/Write
-
-
-
-
R
R
-
-
Default
0
0
0
0
0
0
0
0
Bit #
7
6
5
4
3
2
1
0
Field
Stall
Flag
NAK
Flag
Length
Exception
Flag
Reserved
Sequence
Status
Time-out
Flag
Error
Flag
ACK
Flag
Read/Write
R
R
R
-
R
R
R
R
Default
0
0
0
0
0
0
0
0
Figure 7-23. Host n Endpoint Status Register
Register Description
The Host n Endpoint Status Register is a read-only register that provides status for the last USB transaction.
Overflow Flag (Bit 11)
The Overflow Flag bit indicates that the received data in the last data transaction exceeded the maximum length specified in the
Host n Count Register. The Overflow Flag should be checked in response to a Length Exception signified by the Length Exception
Flag set to ‘1’.
1: Overflow condition occurred.
0: Overflow condition did not occur.
Underflow Flag (Bit 10)
The Underflow Flag bit indicates that the received data in the last data transaction was less then the maximum length specified
in the Host n Count Register. The Underflow Flag should be checked in response to a Length Exception signified by the Length
Exception Flag set to ‘1’.
1: Underflow condition occurred.
0: Underflow condition did not occur.
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Stall Flag (Bit 7)
The Stall Flag bit indicates that the peripheral device replied with a Stall in the last transaction.
1: Device returned Stall.
0: Device did not return Stall.
NAK Flag (Bit 6)
The NAK Flag bit indicates that the peripheral device replied with a NAK in the last transaction.
1: Device returned NAK.
0: Device did not return NAK.
Length Exception Flag (Bit 5)
The Length Exception Flag bit indicates the received data in the data stage of the last transaction does not equal the maximum
Host Count specified in the Host n Count Register. A Length Exception can either mean an overflow or underflow and the Overflow
and Underflow flags (bits 11 and 10 respectively) should be checked to determine which event occurred.
1: An overflow or underflow condition occurred.
0: An overflow or underflow condition did not occur.
Sequence Status (Bit 3)
The Sequence Status bit indicates the state of the last received data toggle from the device. Firmware is responsible for monitoring
and handling the sequence status. The Sequence bit is only valid if the ACK bit is set to ‘1’. The Sequence bit is set to ‘0’ when
an error is detected in the transaction and the Error bit will be set.
1: DATA1.
0: DATA0.
Time-out Flag (Bit 2)
The Time-out Flag bit indicates if a timeout condition occurred for the last transaction. A time-out condition can occur when a
device either takes too long to respond to a USB host request or takes too long to respond with a handshake.
1: Time-out occurred.
0: Time-out did not occur.
Error Flag (Bit 1)
The Error Flag bit indicates a transaction failed for any reason other than the following: Time-out, receiving a NAK, or receiving
a STALL. Overflow and Underflow are not considered errors and do not affect this bit. CRC5 and CRC16 errors will result in an
Error flag along with receiving incorrect packet types.
1: Error detected.
0: No error detected.
ACK Flag (Bit 0)
The ACK Flag bit indicates two different conditions depending on the transfer type. For non-Isochronous transfers, this bit
represents a transaction ending by receiving or sending an ACK packet. For Isochronous transfers, this bit represents a successful transaction which will not be represented by an ACK packet.
1: For non-Isochronous transfers, the transaction was ACKed. For Isochronous transfers, the transaction was completed successfully.
0: For non-Isochronous transfers, the transaction was not ACKed. For Isochronous transfers, the transaction did not completed
successfully.
7.5.5
Host n PID Register [W]
• Host 1 PID Register 0xC086.
• Host 2 PID Register 0xC0A6.
Bit #
15
14
13
12
Field
11
10
9
8
Reserved
Read/Write
-
-
-
-
-
-
-
-
Default
0
0
0
0
0
0
0
0
Bit #
7
6
5
4
3
2
1
0
Field
PID Select
Endpoint Select
Read/Write
W
W
W
W
W
W
W
W
Default
0
0
0
0
0
0
0
0
Figure 7-24. Host n PID Register
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Register Description
The Host n PID Register is a write-only register that provides the PID and Endpoint information to the USB SIE to be used in the
next transaction.
PID Select (Bits [7:4])
The PID Select field defined as in Table 7-9. ACK and NAK tokens are automatically sent based on settings in the Host n Control
Register and do not need to be written in this register.
Table 7-9. PID Select Definition
PID TYPE
PID Select [7:4]
SETUP
1101 (D Hex)
IN
1001 (9 Hex)
OUT
0001 (1 Hex)
SOF
0101 (5 Hex)
PREAMBLE
1100 (C Hex)
NAK
1010 (A Hex)
STALL
1110 (E Hex)
DATA0
0011 (3 Hex)
DATA1
1011 (B Hex)
Endpoint Select (Bits [3:0])
The Endpoint field, which allows addressing up to 16 different endpoints.
Reserved
All reserved bits should be written as ‘0’.
7.5.6
Host n Count Result Register [R]
• Host 1 Count Result Register 0xC088.
• Host 2 Count Result Register 0xC0A8.
Bit #
15
14
13
12
11
10
9
8
Read/Write
R
R
R
R
Default
0
0
R
R
R
R
0
0
0
0
0
0
Bit #
7
6
5
4
3
2
1
0
Field
Result...
Field
...Result
Read/Write
R
R
R
R
R
R
R
R
Default
0
0
0
0
0
0
0
0
Figure 7-25. Host n Count Result Register
Register Description
The Host n Count Result Register is a read-only register that contains the size difference in bytes between the Host Count Value
specified in the Host n Count Register and the last packet received. If an overflow or underflow condition occurs, i.e., the received
packet length differs from the value specified in the Host n Count Register, the Length Exception Flag bit in the Host n Endpoint
Status Register will be set. The value in this register is only value when the Length Exception Flag bit is set and the Error Flag
bit is not set, both bits are in the Host n Endpoint Status Register.
Result (Bits [15:0])
The Result field will contain the differences in bytes between the received packet and the value specified in the Host n Count
Register. If an overflow condition occurs, Result [15:10] will be set to ‘111111’, a 2’s complement value indicating the additional
byte count of the received packet. If an underflow condition occurs, Result [15:0] will indicate the excess bytes count (number of
bytes not used).
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PRELIMINARY
CY7C67300
Reserved
All reserved bits should be written as ‘0’.
7.5.7
Host n Device Address Register [W]
• Host 1 Device Address Register 0xC088.
• Host 2 Device Address Register 0xC0A8.
Bit #
15
14
13
12
Field
11
10
9
8
Reserved...
Read/Write
-
-
-
-
-
-
-
-
Default
0
0
0
0
0
0
0
0
Bit #
7
6
5
4
3
2
1
0
Field
...Reserved
Address
Read/Write
-
W
W
W
W
W
W
W
Default
0
0
0
0
0
0
0
0
Figure 7-26. Host n Device Address Register
Register Description
The Host n Device Address Register is a write-only register that contains the USB Device Address that the host wishes to
communicate with.
Address (Bits [6:0])
The Address field contains the value of the USB address for the next device that the host is going to communicate with. This
value needs to be written by firmware.
Reserved
All reserved bits should bit written as ‘0’.
7.5.8
Host n Interrupt Enable Register [R/W]
• Host 1 Interrupt Enable Register 0xC08C.
• Host 2 Interrupt Enable Register 0xC0AC.
Bit #
15
14
Field
VBUS
Interrupt
Enable
ID Interrupt
Enable
Read/Write
R/W
R/W
-
-
-
-
R/W
-
Default
0
0
0
0
0
0
0
0
Bit #
Field
7
13
6
Port B
Port A
Wake Interrupt Wake Interrupt
Enable
Enable
12
11
10
Reserved
5
4
Port B Connect
Change
Interrupt
Enable
Port A Connect
Change
Interrupt
Enable
3
2
9
8
SOF/EOP
Interrupt
Enable
Reserved
1
Reserved
0
Done
Interrupt
Enable
Read/Write
R/W
R/W
R/W
R/W
-
-
-
R/W
Default
0
0
0
0
0
0
0
0
Figure 7-27. Host n Interrupt Enable Register
Register Description
The Host n Interrupt Enable Register will allow control over host related interrupts.
In this register a bit set to ‘1’ enables the corresponding interrupt while ‘0’ disables the interrupt.
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VBUS Interrupt Enable (Bit 15)
The VBUS Interrupt Enable bit will enable or disable the OTG VBUS interrupt. When enabled this interrupt will trigger on both
rising and falling edge of VBUS at the 4.4V status (only supported in Port 1A). This bit is only available for Host 1and is a reserved
bit in Host 2.
1: Enable VBUS interrupt.
0: Disable VBUS interrupt.
ID Interrupt Enable (Bit 14)
The ID Interrupt Enable bit will enable or disable the OTG ID interrupt. When enabled this interrupt will trigger on both rising and
falling edge of OTG ID pin (only supported in Port 1A). This bit is only available for Host 1 and is a reserved bit in Host 2.
1: Enable ID interrupt.
0: Disable ID interrupt.
SOF/EOP Interrupt Enable (Bit 9)
The SOF/EOP Interrupt Enable bit will enable or disable the SOF/EOP timer interrupt
1: Enable SOF/EOP timer interrupt.
0: Disable SOF/EOP timer interrupt.
Port B Wake Interrupt Enable (Bit 7)
The Port B Wake Interrupt Enable bit will enable or disable the remote wake-up interrupt for Port B
1: Enable remote wake-up interrupt for Port B.
0: Disable remote wake-up interrupt for Port B.
Port A Wake Interrupt Enable (Bit 6)
The Port A Wake Interrupt Enable bit will enable or disable the remote wake-up interrupt for Port A
1: Enable remote wake-up interrupt for Port A.
0: Disable remote wake-up interrupt for Port A.
Port B Connect Change Interrupt Enable (Bit 5)
The Port B Connect Change Interrupt Enable bit will enable or disable the Port B Connect Change interrupt on Port B. This
interrupt will trigger when either a device is inserted (SE0 state to J state) or a device is removed (J state to SE0 state).
1: Enable Connect Change interrupt.
0: Disable Connect Change interrupt.
Port A Connect Change Interrupt Enable (Bit 4)
The Port A Connect Change Interrupt Enable bit will enable or disable the Connect Change interrupt on Port A. This interrupt will
trigger when either a device is inserted (SE0 state to J state) or a device is removed (J state to SE0 state).
1: Enable Connect Change interrupt.
0: Disable Connect Change interrupt.
Done Interrupt Enable (Bit 0)
The Done Interrupt Enable bit enables or disables the USB Transfer Done interrupt. The USB Transfer Done will trigger when
either the host responding with and ACK, or a device responds with any of the following: ACK, NAK, STALL, or Time-out. This
interrupt is used for both Port A and Port B.
1: Enable USB Transfer Done interrupt.
0: Disable USB Transfer Done interrupt.
Reserved
All reserved bits should be written as ‘0’.
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7.5.9
Host n Status Register [R/W]
• Host 1 Status Register 0xC090.
• Host 2 Status Register 0xC0B0.
Bit #
15
14
Field
VBUS Interrupt Flag
ID Interrupt Flag
13
12
11
10
Read/Write
R/W
R/W
-
-
-
-
R/W
-
Default
X
X
X
X
X
X
X
X
Reserved
Bit #
7
6
Field
Port B
Wake Interrupt
Flag
Port A
Wake Interrupt
Flag
5
Read/Write
R/W
R/W
R/W
Default
X
X
X
4
9
8
SOF/EOP
Interrupt Flag
Reserved
3
2
1
0
Port B
SE0
Status
Port A
SE0
Status
Reserved
Done Interrupt
Flag
R/W
R/W
R/W
-
R/W
X
X
X
X
X
Port B Connect Port A Connect
Change
Change Interrupt
Interrupt Flag
Flag
Figure 7-28. Host n Status Register
Register Description
The Host n Status Register will provide status information for host operation. Pending interrupts can be cleared by writing a ‘1’ to
the corresponding bit. This register can be accessed by the HPI interface.
VBUS Interrupt Flag (Bit 15)
The VBUS Interrupt Flag bit indicates the status of the OTG VBUS interrupt (only for Port 1A). When enabled this interrupt will
trigger on both the rising and falling edge of VBUS at 4.4V. This bit is only available for Host 1 and is a reserved bit in Host 2.
1: Interrupt triggered
0: Interrupt did not trigger
ID Interrupt Flag (Bit 14)
The ID Interrupt Flag bit indicates the status of the OTG ID interrupt (only for Port 1A). When enabled this interrupt will trigger on
both the rising and falling edge of the OTG ID pin. This bit is only available for Host 1 and is a reserved bit in Host 2.
1: Interrupt triggered
0: Interrupt did not trigger
SOF/EOP Interrupt Flag (Bit 9)
The SOF/EOP Interrupt Flag bit indicates the status of the SOF/EOP Timer interrupt. This bit will trigger ‘1’ when the SOF/EOP
timer expires.
1: Interrupt triggered
0: Interrupt did not trigger
Port B Wake Interrupt Flag (Bit 7)
The Port B Wake Interrupt Flag bit indicates remote wake-up on PortB
1: Interrupt triggered
0: Interrupt did not trigger
Port A Wake Interrupt Flag (Bit 6)
The Port A Wake Interrupt Flag bit indicates remote wake-up on PortA
1: Interrupt triggered
0: Interrupt did not trigger
Port B Connect Change Interrupt Flag (Bit 5)
The Port B Connect Change Interrupt Flag bit indicates the status of the Connect Change interrupt on Port B. This bit will trigger
‘1’ on either a rising edge or falling edge of a USB Reset condition (device inserted or removed). Together with the Port B SE0
Status bit, it can be determined whether a device was inserted or removed.
1: Interrupt triggered
0: Interrupt did not trigger
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CY7C67300
Port A Connect Change Interrupt Flag (Bit 4)
The Port A Connect Change Interrupt Flag bit indicates the status of the Connect Change interrupt on Port A. This bit will trigger
‘1’ on either a rising edge or falling edge of a USB Reset condition (device inserted or removed). Together with the Port A SE0
Status bit, it can be determined whether a device was inserted or removed.
1: Interrupt triggered
0: Interrupt did not trigger
Port B SE0 Status (Bit 3)
The Port B SE0 Status bit indicates if Port B is in a SE0 state or not. Together with the Port B Connect Change Interrupt Flag bit,
it can be determined whether a device was inserted (non-SE0 condition) or removed (SE0 condition).
1: SE0 condition
0: Non-SE0 condition
Port A SE0 Status (Bit 2)
The Port A SE0 Status bit indicates if Port A is in a SE0 state or not. Together with the Port A Connect change Interrupt Flag bit,
it can be determined whether a device was inserted (non-SE0 condition) or removed (SE0 condition).
1: SE0 condition
0: Non-SE0 condition
Done Interrupt Flag (Bit 0)
The Done Interrupt Flag bit indicates the status of the USB Transfer Done interrupt. The USB Transfer Done will trigger when
either the host responding with and ACK, or a device responds with any of the following: ACK, NAK, STALL, or Time-out. This
interrupt is used for both Port A and Port B.
1: Interrupt triggered
0: Interrupt did not trigger
7.5.10 Host n SOF/EOP Count Register [R/W]
• Host 1 SOF/EOP Count Register 0xC092
• Host 2 SOF/EOP Count Register 0xC0B2
Bit #
15
Field
14
13
12
11
Reserved
10
9
8
Count...
Read/Write
-
-
R/W
R/W
R/W
R/W
R/W
R/W
Default
0
0
1
0
1
1
1
0
Bit #
7
6
5
4
3
2
1
0
Field
...Count
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Default
1
1
1
0
0
0
0
0
Figure 7-29. Host n SOF/EOP Count Register
Register Description
The Host n SOF/EOP Count Register contains the SOF/EOP Count Value that is loaded into the SOF/EOP counter. This value
is loaded each time the SOF/EOP counter counts down to zero. The default value set in this register at power up is 0x2EE0 which
will generate a 1ms time frame. The SOF/EOP counter is a down counter decremented at a 12-MHz rate. When this register is
read, the value returned is the programmed SOF/EOP count value.
Count (Bits [13:0])
The Count field sets the SOF/EOP counter duration.
Reserved
All reserved bits should be written as ‘0’.
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7.5.11 Host n SOF/EOP Counter Register [R]
• Host 1 SOF/EOP Counter Register 0xC094
• Host 2 SOF/EOP Counter Register 0xC0B4
Bit #
15
Field
14
13
12
11
Reserved
10
9
8
Counter...
Read/Write
-
-
R
R
R
R
R
R
Default
X
X
X
X
X
X
X
X
Bit #
7
6
5
4
3
2
1
0
Field
...Counter
Read/Write
R
R
R
R
R
R
R
R
Default
X
X
X
X
X
X
X
X
Figure 7-30. Host n SOF/EOP Counter Register
Register Description
The Host n SOF/EOP Counter Register contains the current value of the SOF/EOP down counter. This value can be used to
determine the time remaining in the current frame.
Counter (Bits [13:0])
The Counter field contains the current value of the SOF/EOP down counter.
7.5.12 Host n Frame Register [R]
• Host 1 Frame Register 0xC096
• Host 2 Frame Register 0xC0B6
Bit #
15
14
Field
13
12
11
10
Reserved
9
8
Frame...
Read/Write
-
-
-
-
-
R
R
R
Default
0
0
0
0
0
0
0
0
Bit #
7
6
5
4
3
2
1
0
Field
...Frame
Read/Write
R
R
R
R
R
R
R
R
Default
0
0
0
0
0
0
0
0
Figure 7-31. Host n Frame Register
Register Description
The Host n Frame Register maintains the next frame number to be transmitted (current frame number + 1). This value is updated
after each SOF transmission. This register resets to 0x0000 after each CPU write to the Host n SOF/EOP Count Register (Host
1: 0xC092 Host 2: 0xC0B2).
Frame (Bits [10:0])
The Frame field contains the next frame number to be transmitted.
Reserved
All reserved bits should be written as ‘0’.
7.6
USB Device Only Registers
There are eleven sets of USB Device only registers. All sets consist of at least two registers, one for Device Port 1 and one for
Device Port 2. In addition, each Device port has eight possible endpoints. This gives each endpoint register set eight registers
for each Device Port for a total of sixteen registers per set. The USB Device only registers are covered in this section and
summarized in Figure 7-32.
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PRELIMINARY
Register Name
Device n Endpoint n Control Register
Device n Endpoint n Address Register
Device n Endpoint n Count Register
Device n Endpoint n Status Register
Device n Endpoint n Count Result Register
Device n Port Select Register
Device n Interrupt Enable Register
Device n Address Register
Device n Status Register
Device n Frame Number Register
Device n SOF/EOP Count Register
CY7C67300
Address (Device 1 / Device 2)
0x02n0
0x02n2
0x02n4
0x02n6
0x02n8
0xC084 / 0xC0A4
0xC08C / 0xC0AC
0xC08E / 0xC0AE
0xC090 / 0xCB0
0xC092 / 0xC0B2
0xC094 / 0xC0B4
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R
W
Figure 7-32. USB Device Only Registers
7.6.1
Device n Endpoint n Control Register [R/W]
• Device n Endpoint 0 Control Register [Device 1: 0x0200 Device 2: 0x0280]
• Device n Endpoint 1 Control Register [Device 1: 0x0210 Device 2: 0x0290]
• Device n Endpoint 2 Control Register [Device 1: 0x0220 Device 2: 0x02A0]
• Device n Endpoint 3 Control Register [Device 1: 0x0230 Device 2: 0x02B0]
• Device n Endpoint 4 Control Register [Device 1: 0x0240 Device 2: 0x02C0]
• Device n Endpoint 5 Control Register [Device 1: 0x0250 Device 2: 0x02D0]
• Device n Endpoint 6 Control Register [Device 1: 0x0260 Device 2: 0x02E0]
• Device n Endpoint 7 Control Register [Device 1: 0x0270 Device 2: 0x02F0]
Bit #
15
14
13
12
Field
11
10
9
8
Reserved
Read/Write
-
-
-
-
-
-
-
-
Default
X
X
X
X
X
X
X
X
Bit #
7
6
5
4
3
2
1
0
Field
IN/OUT
Ignore
Enable
Sequence
Select
Stall
Enable
ISO
Enable
NAK
Interrupt
Enable
Direction
Select
Enable
Arm
Enable
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Default
X
X
X
X
X
X
X
X
Figure 7-33. Device n Endpoint n Register
Register Description
The Device n Endpoint n Control Register provides control over a single EP in device mode. There are a total of eight endpoints
for each of the two ports. All endpoints have the same definition for their Device n Endpoint n Control Register.
IN/OUT Ignore Enable (Bit 6)
The IN/OUT Ignore Enable bit will force endpoint 0 (EP0) to ignore all IN and OUT requests. This bit should be set so that EP0
only excepts Setup packets at the start of each transfer. This bit must be cleared to except IN/OUT transactions. This bit only
applies to EP0.
1: Ignore IN/OUT requests
0: Do not ignore IN/OUT requests
Sequence Select (Bit 6)
The Sequence Select bit will determine whether a DATA0 or a DATA1 will be sent for the next data toggle. This bit has no effect
on receiving data packets, sequence checking must be handled in firmware.
1: Send a DATA1
0: Send a DATA0
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CY7C67300
Stall Enable (Bit 5)
The Stall Enable bit will send a Stall in response to the next request (unless it is a set-up request which are always ACKed). This
is a sticky bit and will continue to respond with Stalls until cleared by firmware.
1: Send Stall
0: Do not send Stall
ISO Enable (Bit 4)
The ISO Enable bit enables and disables an Isochronous transaction. This bit is only valid for EPs 1–7 and has no function for EP0.
1: Enable Isochronous transaction
0: Disable Isochronous transaction
NAK Interrupt Enable (Bit 3)
The NAK Interrupt Enable bit enables and disables the generation of an Endpoint n interrupt when the device responds to the
host with a NAK. The Endpoint n Interrupt Enable bit in the Device n Interrupt Enable Register must also be set. When a NAK is
sent to the host, the corresponding EP Interrupt Flag in the Device n Status Register will be set. In addition, the NAK Flag in the
Device n Endpoint n Status Register will be set.
1: Enable NAK interrupt
0: Disable NAK interrupt
Direction Select (Bit 2)
The Direction Select bit needs to be set according to the expected direction of the next data stage in the next transaction. If the
data stage direction is different from what is set it this bit, it will get NAKed and either the IN Exception Flag or the OUT Exception
Flag will be set in the Device n Endpoint n Status Register. If a set-up packet is received and the Direction Select bit is set
incorrectly, the set-up will get ACKed and the Set-up Status Flag will be set (please refer to the set-up bit of the Device n Endpoint
n Status Register for details).
1: OUT transfer (host to device)
0: IN transfer (device to host)
Enable (Bit 1)
The Enable bit must be set to allow transfers to the endpoint. If Enable is set to ‘0’ then all USB traffic to this endpoint will be
ignored. If Enable is set ‘1’ and Arm Enable (bit 0) is set ‘0’ then NAKs will automatically be returned from this endpoint (except
setup packets which are always ACKed as long as the Enable bit is set.)
1: Enable transfers to an endpoint
0: Do not allow transfers to an endpoint
Arm Enable (Bit 0)
The Arm Enable bit arms the endpoint to transfer or receive a packet. This bit is cleared to ‘0’ when a transaction is complete.
1: Arm endpoint
0: Endpoint disarmed
Reserved
All reserved bits should bit written as ‘0’.
7.6.2
Device n Endpoint n Address Register [R/W]
• Device n Endpoint 0 Address Register [Device 1: 0x0202 Device 2: 0x0282]
• Device n Endpoint 1 Address Register [Device 1: 0x0212 Device 2: 0x0292]
• Device n Endpoint 2 Address Register [Device 1: 0x0222 Device 2: 0x02A2]
• Device n Endpoint 3 Address Register [Device 1: 0x0232 Device 2: 0x02B2]
• Device n Endpoint 4 Address Register [Device 1: 0x0242 Device 2: 0x02C2]
• Device n Endpoint 5 Address Register [Device 1: 0x0252 Device 2: 0x02D2]
• Device n Endpoint 6 Address Register [Device 1: 0x0262 Device 2: 0x02E2]
• Device n Endpoint 7 Address Register [Device 1: 0x0272 Device 2: 0x02F2]
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PRELIMINARY
Bit #
15
14
13
12
Field
CY7C67300
11
10
9
8
Address...
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Default
X
X
X
X
X
X
X
X
Bit #
7
6
5
4
3
2
1
0
Field
...Address
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Default
X
X
X
X
X
X
X
X
Figure 7-34. Device n Endpoint n Address Register
Register Description
The Device n Endpoint n Address Register is used as the base pointer into memory space for the current Endpoint transaction.
There are a total of eight endpoints for each of the two ports. All endpoints have the same definition for their Device n Endpoint
n Address Register.
Address (Bits [15:0])
The Address field sets the base address for the current transaction on a signal endpoint.
7.6.3
Device n Endpoint n Count Register [R/W]
• Device n Endpoint 0 Count Register [Device 1: 0x0204 Device 2: 0x0284]
• Device n Endpoint 1 Count Register [Device 1: 0x0214 Device 2: 0x0294]
• Device n Endpoint 2 Count Register [Device 1: 0x0224 Device 2: 0x02A4]
• Device n Endpoint 3 Count Register [Device 1: 0x0234 Device 2: 0x02B4]
• Device n Endpoint 4 Count Register [Device 1: 0x0244 Device 2: 0x02C4]
• Device n Endpoint 5 Count Register [Device 1: 0x0254 Device 2: 0x02D4]
• Device n Endpoint 6 Count Register [Device 1: 0x0264 Device 2: 0x02E4]
• Device n Endpoint 7 Count Register [Device 1: 0x0274 Device 2: 0x02F4]
Bit #
15
14
13
Field
12
11
10
9
Reserved
8
Count...
Read/Write
-
-
-
-
-
-
R/W
R/W
Default
X
X
X
X
X
X
X
X
Bit #
7
6
5
4
3
2
1
0
Field
...Count
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Default
X
X
X
X
X
X
X
X
Figure 7-35. Device n Endpoint n Count Register
Register Description
The Device n Endpoint n Count Register designates the maximum packet size that can be received from the host for OUT
transfers for a single endpoint. This register also designates the packet size to be sent to the host in response to the next IN token
for a single endpoint. The maximum packet length is 1023 bytes in ISO mode. There are a total of eight endpoints for each of the
two ports. All endpoints have the same definition for their Device n Endpoint n Count Register.
Count (Bits [9:0])
The Count field sets the current transaction packet length for a single endpoint.
Reserved
All reserved bits should be written as ‘0’.
7.6.4
Device n Endpoint n Status Register [R/W]
• Device n Endpoint 0 Status Register [Device 1: 0x0206 Device 2: 0x0286]
• Device n Endpoint 1 Status Register [Device 1: 0x0216 Device 2: 0x0296]
• Device n Endpoint 2 Status Register [Device 1: 0x0226 Device 2: 0x02A6]
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PRELIMINARY
•
•
•
•
•
CY7C67300
Device n Endpoint 3 Status Register [Device 1: 0x0236 Device 2: 0x02B6]
Device n Endpoint 4 Status Register [Device 1: 0x0246 Device 2: 0x02C6]
Device n Endpoint 5 Status Register [Device 1: 0x0256 Device 2: 0x02D6]
Device n Endpoint 6 Status Register [Device 1: 0x0266 Device 2: 0x02E6]
Device n Endpoint 7 Status Register [Device 1: 0x0276 Device 2: 0x02F6]
Bit #
15
14
Field
13
12
Reserved
11
10
Overflow
Flag
Underflow
Flag
9
8
OUT
IN
Exception Flag Exception Flag
Read/Write
-
-
-
-
R/W
R/W
R/W
R/W
Default
X
X
X
X
X
X
X
X
Bit #
7
6
5
4
3
2
1
0
Field
Stall
Flag
NAK
Flag
Length
Exception Flag
Set-up
Flag
Sequence
Flag
Time-out
Flag
Error
Flag
ACK
Flag
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Default
X
X
X
X
X
X
X
X
Figure 7-36. Device n Endpoint n Status Register
Register Description
The Device n Endpoint n Status Register provides packet status information for the last transaction received or transmitted. This
register is updated in hardware and does not need to be cleared by firmware. There are a total of eight endpoints for each of the
two ports. All endpoints have the same definition for their Device n Endpoint n Status Register.
The Device n Endpoint n Status Register is a memory based register that should be initialized to 0x0000 before USB Device
operations are initiated. After initialization, this register should not be written to again.
Overflow Flag (Bit 11)
The Overflow Flag bit indicates that the received data in the last data transaction exceeded the maximum length specified in the
Device n Endpoint n Count Register. The Overflow Flag should be checked in response to a Length Exception signified by the
Length Exception Flag set to ‘1’.
1: Overflow condition occurred
0: Overflow condition did not occur
Underflow Flag (Bit 10)
The Underflow Flag bit indicates that the received data in the last data transaction was less then the maximum length specified
in the Device n Endpoint n Count Register. The Underflow Flag should be checked in response to a Length Exception signified
by the Length Exception Flag set to ‘1’.
1: Underflow condition occurred
0: Underflow condition did not occur
OUT Exception Flag (Bit 9)
The OUT Exception Flag bit will indicates when the device received an OUT packet when armed for an IN.
1: Received OUT when armed for IN
0: Received IN when armed for IN
IN Exception Flag (Bit 8)
The IN Exception Flag bit will indicates when the device received an IN packet when armed for an OUT.
1: Received IN when armed for OUT
0: Received OUT when armed for OUT
Stall Flag (Bit 7)
The Stall Flag bit indicates that a Stall packet was sent to the host.
1: Stall packet was sent to the host
0: Stall packet was not sent
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NAK Flag (Bit 6)
The NAK Flag bit indicates that a NAK packet was sent to the host.
1: NAK packet was sent to the host
0: NAK packet was not sent
Length Exception Flag (Bit 5)
The Length Exception Flag bit indicates the received data in the data stage of the last transaction does not equal the maximum
Endpoint Count specified in the Device n Endpoint n Count Register. A Length Exception can either mean an overflow or
underflow and the Overflow and Underflow flags (bits 11 and 10 respectively) should be checked to determine which event
occurred.
1: An overflow or underflow condition occurred
0: An overflow or underflow condition did not occur
Set-up Flag (Bit 4)
The Set-up Flag bit indicates that a set-up packet was received. In device mode set-up packets get stored at memory location
0x0300 for Device 1 and 0x0308 for Device 2. Set-up packets are always accepted regardless of the Direction Select and Arm
Enable bit settings as long as the Device n EP n Control Register Enable bit is set.
1: Set-up packet was received
0: Set-up packet was not received
Sequence Flag (Bit 3)
The Sequence Flag bit indicates whether the last data toggle received was a DATA1 or a DATA0. This bit has no effect on receiving
data packets, sequence checking must be handled in firmware.
1: DATA1 was received
0: DATA0 was received
Time-out Flag (Bit 2)
The Time-out Flag bit indicates whether a time-out condition occurred on the last transaction. On the device side, a time-out can
occur if the device sends a data packet in response to an IN request but then does not receive a handshake packet in a
predetermined time. It can also occur if the device does not receive the data stage of an OUT transfer in time.
1: Time-out occurred
0: Time-out condition did not occur
Error Flag (Bit 2)
The Error Flag bit will be set if a CRC5 and CRC16 error occurs, or if an incorrect packet type is received. Overflow and underflow
are not considered errors and do not affect this bit.
1: Error occurred
0: Error did not occur
ACK Flag (Bit 0)
The ACK Flag bit indicates whether the last transaction was ACKed.
1: ACK occurred
0: ACK did not occur
7.6.5
Device n Endpoint n Count Result Register [R/W]
• Device n Endpoint 0 Count Result Register [Device 1: 0x0208 Device 2: 0x0288]
• Device n Endpoint 1 Count Result Register [Device 1: 0x0218 Device 2: 0x0298]
• Device n Endpoint 2 Count Result Register [Device 1: 0x0228 Device 2: 0x02A8]
• Device n Endpoint 3 Count Result Register [Device 1: 0x0238 Device 2: 0x02B8]
• Device n Endpoint 4 Count Result Register [Device 1: 0x0248 Device 2: 0x02C8]
• Device n Endpoint 5 Count Result Register [Device 1: 0x0258 Device 2: 0x02D8]
• Device n Endpoint 6 Count Result Register [Device 1: 0x0268 Device 2: 0x02E8]
• Device n Endpoint 7 Count Result Register [Device 1: 0x0278 Device 2: 0x02F8]
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Bit #
15
14
13
CY7C67300
12
Field
11
10
9
8
Result...
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Default
X
X
X
X
X
X
X
X
Bit #
7
6
5
4
3
2
1
0
Field
...Result
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Default
X
X
X
X
X
X
X
X
Figure 7-37. Device n Endpoint n Count Result Register
Register Description
The Device n Endpoint n Count Result Register contains the size difference in bytes between the Endpoint Count specified in
the Device n Endpoint n Count Register and the last packet received. If an overflow or underflow condition occurs, i.e., the
received packet length differs from the value specified in the Device n Endpoint n Count Register, the Length Exception Flag bit
in the Device n Endpoint n Status Register will be set. The value in this register is only value when the Length Exception Flag bit
is set and the Error Flag bit is not set, both bits are in the Device n Endpoint n Status Register.
The Device n Endpoint n Count Result Register is a memory-based register that should be initialized to 0x0000 before USB
Device operations are initiated. After initialization, this register should not be written to again.
Result (Bits [15:0])
The Result field will contain the differences in bytes between the received packet and the value specified in the Device n Endpoint
n Count Register. If an overflow condition occurs, Result [15:10] will be set to ‘111111’, a “2”s complement value indicating the
additional byte count of the received packet. If an underflow condition occurs, Result [15:0] will indicate the excess bytes count
(number of bytes not used).
Reserved
All reserved bits should be written as ‘0’.
7.6.6
Device n Port Select Register [R/W]
• Device n Port Select Register 0xC084
• Device n Port Select Register 0xC0A4
Bit #
15
14
Field
Reserved
Port
Select
13
12
11
10
9
8
Read/Write
-
R/W
-
-
-
-
-
-
Default
0
0
0
0
0
0
0
0
Bit #
7
6
5
4
3
2
1
0
Reserved...
Field
...Reserved
Read/Write
-
-
-
-
-
-
-
-
Default
0
0
0
0
0
0
0
0
Figure 7-38. Device n Port Select Register
Register Description
The Device n Port Select Register selects either port A or port B for the static device port.
Port Select (Bit 14)
The Port Select bit selects which of the two ports is enabled
1: Port 1B or Port 2B is enabled
0: Port 1A or Port 2A is enabled
7.6.7
Device n Interrupt Enable Register [R/W]
• Device 1 Interrupt Enable Register 0xC08C
• Device 2 Interrupt Enable Register 0xC0AC
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Bit #
15
14
Field
VBUS
Interrupt Enable
ID Interrupt
Enable
13
12
Read/Write
R/W
R/W
-
-
Default
0
0
0
0
Reserved
CY7C67300
11
10
9
8
SOF/EOP
Time-out
Interrupt Enable
Reserved
SOF/EOP
Interrupt
Enable
Reset
Interrupt Enable
R/W
-
R/W
R/W
0
0
0
0
Bit #
7
6
5
4
3
2
1
0
Field
EP7 Interrupt
Enable
EP6 Interrupt
Enable
EP5 Interrupt
Enable
EP4 Interrupt
Enable
EP3 Interrupt
Enable
EP2 Interrupt
Enable
EP1 Interrupt
Enable
EP0 Interrupt
Enable
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Default
0
0
0
0
0
0
0
0
Figure 7-39. Device n Interrupt Enable Register
Register Description
The Device n Interrupt Enable Register provides control over device-related interrupts including eight different endpoint interrupts.
VBUS Interrupt Enable (Bit 15)
The VBUS Interrupt Enable bit will enable or disable the OTG VBUS interrupt. When enabled this interrupt will trigger on both
rising and falling edge of VBUS at the 4.4V status (only supported in Port 1A). This bit is only available for Device 1 and is a
reserved bit in Device 2.
1: Enable VBUS interrupt
0: Disable VBUS interrupt
ID Interrupt Enable (Bit 14)
The ID Interrupt Enable bit will enable or disable the OTG ID interrupt. When enabled this interrupt will trigger on both rising and
falling edge of OTG ID pin (only supported in Port 1A). This bit is only available for Device 1and is a reserved bit in Device 2.
1: Enable ID interrupt
0: Disable ID interrupt
SOF/EOP Time-out Interrupt Enable (Bit 11)
The SOF/EOP Time-out Interrupt Enable bit will enable or disable the SOF/EOP Time-out Interrupt. When enabled this interrupt
will trigger when the USB host fails to send a SOF or EOP packet within the time period specified in the Device n SOF/EOP Count
Register. In addition, the Device n Frame Register counts the number of times the SOF/EOP Time-out Interrupt triggers between
receiving SOF/EOPs.
1: SOF/EOP time-out occurred
0: SOF/EOP time-out did not occur
SOF/EOP Interrupt Enable (Bit 9)
The SOF/EOP Interrupt Enable bit will enable or disable the SOF/EOP received interrupt.
1: Enable SOF/EOP received interrupt
0: Disable SOF/EOP received interrupt
Reset Interrupt Enable (Bit 8)
The Reset Interrupt Enable bit will enable or disable the USB Reset Detected interrupt
1: Enable USB Reset Detected interrupt
0: Disable USB Reset Detected interrupt
EP7 Interrupt Enable (Bit 7)
The EP7 Interrupt Enable bit will enable or disable endpoint seven (EP7) Transaction Done interrupt. An EPx Transaction Done
interrupt will trigger when any of the following responses or events occur in a transaction for the device’s given Endpoint:
send/receive ACK, send STALL, Time-out occurs, IN Exception Error, or OUT Exception Error. In addition, the NAK Interrupt
Enable bit in the Device n Endpoint Control Register can also be set so that NAK responses will trigger this interrupt.
1: Enable EP7 Transaction Done interrupt
0: Disable EP7 Transaction Done interrupt
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CY7C67300
EP6 Interrupt Enable (Bit 6)
The EP6 Interrupt Enable bit will enable or disable endpoint seven (EP6) Transaction Done interrupt. An EPx Transaction Done
interrupt will trigger when any of the following responses or events occur in a transaction for the device’s given Endpoint:
send/receive ACK, send STALL, Time-out occurs, IN Exception Error, or OUT Exception Error. In addition, the NAK Interrupt
Enable bit in the Device n Endpoint Control Register can also be set so that NAK responses will trigger this interrupt.
1: Enable EP6 Transaction Done interrupt
0: Disable EP6 Transaction Done interrupt
EP5 Interrupt Enable (Bit 5)
The EP5 Interrupt Enable bit will enable or disable endpoint seven (EP5) Transaction Done interrupt. An EPx Transaction Done
interrupt will trigger when any of the following responses or events occur in a transaction for the device’s given Endpoint:
send/receive ACK, send STALL, Time-out occurs, IN Exception Error, or OUT Exception Error. In addition, the NAK Interrupt
Enable bit in the Device n Endpoint Control Register can also be set so that NAK responses will trigger this interrupt
1: Enable EP5 Transaction Done interrupt
0: Disable EP5 Transaction Done interrupt
EP4 Interrupt Enable (Bit 4)
The EP4 Interrupt Enable bit will enable or disable endpoint seven (EP4) Transaction Done interrupt. An EPx Transaction Done
interrupt will trigger when any of the following responses or events occur in a transaction for the device’s given Endpoint:
send/receive ACK, send STALL, Time-out occurs, IN Exception Error, or OUT Exception Error. In addition, the NAK Interrupt
Enable bit in the Device n Endpoint Control Register can also be set so that NAK responses will trigger this interrupt.
1: Enable EP4 Transaction Done interrupt
0: Disable EP4 Transaction Done interrupt
EP3 Interrupt Enable (Bit 3)
The EP3 Interrupt Enable bit will enable or disable endpoint seven (EP3) Transaction Done interrupt. An EPx Transaction Done
interrupt will trigger when any of the following responses or events occur in a transaction for the device’s given Endpoint:
send/receive ACK, send STALL, Time-out occurs, IN Exception Error, or OUT Exception Error. In addition, the NAK Interrupt
Enable bit in the Device n Endpoint Control Register can also be set so that NAK responses will trigger this interrupt.
1: Enable EP3 Transaction Done interrupt
0: Disable EP3 Transaction Done interrupt
EP2 Interrupt Enable (Bit 2)
The EP2 Interrupt Enable bit will enable or disable endpoint seven (EP2) Transaction Done interrupt. An EPx Transaction Done
interrupt will trigger when any of the following responses or events occur in a transaction for the device’s given Endpoint:
send/receive ACK, send STALL, Time-out occurs, IN Exception Error, or OUT Exception Error. In addition, the NAK Interrupt
Enable bit in the Device n Endpoint Control Register can also be set so that NAK responses will trigger this interrupt.
1: Enable EP2 Transaction Done interrupt
0: Disable EP2 Transaction Done interrupt
EP1 Interrupt Enable (Bit 1)
The EP1 Interrupt Enable bit will enable or disable endpoint seven (EP1) Transaction Done interrupt. An EPx Transaction Done
interrupt will trigger when any of the following responses or events occur in a transaction for the device’s given Endpoint:
send/receive ACK, send STALL, Time-out occurs, IN Exception Error, or OUT Exception Error. In addition, the NAK Interrupt
Enable bit in the Device n Endpoint Control Register can also be set so that NAK responses will trigger this interrupt.
1: Enable EP1 Transaction Done interrupt
0: Disable EP1 Transaction Done interrupt
EP0 Interrupt Enable (Bit 0)
The EP0 Interrupt Enable bit will enable or disable endpoint seven (EP0) Transaction Done interrupt. An EPx Transaction Done
interrupt will trigger when any of the following responses or events occur in a transaction for the device’s given Endpoint:
send/receive ACK, send STALL, Time-out occurs, IN Exception Error, or OUT Exception Error. In addition, the NAK Interrupt
Enable bit in the Device n Endpoint Control Register can also be set so that NAK responses will trigger this interrupt.
1: Enable EP0 Transaction Done interrupt
0: Disable EP0 Transaction Done interrupt
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CY7C67300
Reserved
All reserved bits should be written as ‘0’.
7.6.8
Device n Address Register [W]
• Device 1 Address Register 0xC08E
• Device 2 Address Register 0xC0AE
Bit #
15
14
13
12
Field
11
10
9
8
Reserved...
Read/Write
-
-
-
-
-
-
-
-
Default
0
0
0
0
0
0
0
0
Bit #
7
6
5
4
3
2
1
0
Field
...Reserved
Address
Read/Write
-
W
W
W
W
W
W
W
Default
0
0
0
0
0
0
0
0
Figure 7-40. Device n Address Register
Register Description
The Device n Address Register holds the device address assigned by the host. This register initializes to the default address 0
at reset but must be updated by firmware when the host assigns a new address. Only USB data sent to the address contained
in this register will be responded to, all others are ignored.
Address (Bits [6:0])
The Address field contains the USB address of the device assigned by the host.
Reserved
All reserved bits should be written as ‘0’.
7.6.9
Device n Status Register [R/W]
• Device 1 Status Register 0xC090
• Device 2 Status Register 0xC0B0
Bit #
15
14
Field
VBUS Interrupt
Flag
ID Interrupt
Flag
13
12
11
Read/Write
R/W
R/W
-
-
-
Default
X
X
X
X
X
Bit #
7
6
5
4
3
Field
EP7 Interrupt
Flag
EP6 Interrupt
Flag
EP5 Interrupt
Flag
EP4 Interrupt
Flag
Read/Write
R/W
R/W
R/W
Default
X
X
X
10
9
8
SOF/EOP
Interrupt Flag
Reset Interrupt
Flag
-
R/W
R/W
X
X
X
2
1
0
EP3 Interrupt
Flag
EP2 Interrupt
Flag
EP1 Interrupt
Flag
EP0 Interrupt
Flag
R/W
R/W
R/W
R/W
R/W
X
X
X
X
X
Reserved
Figure 7-41. Device n Status Register
Register Description
The Device n Status Register provides status information for device operation. Pending interrupts can be cleared by writing a ‘1’
to the corresponding bit. This register can be accessed by the HPI interface.
VBUS Interrupt Flag (Bit 15)
The VBUS Interrupt Flag bit indicates the status of the OTG VBUS interrupt (only for Port 1A). When enabled this interrupt will
trigger on both the rising and falling edge of VBUS at 4.4V. This bit is only available for Device 1 and is a reserved bit in Device 2.
1: Interrupt triggered
0: Interrupt did not trigger
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PRELIMINARY
CY7C67300
ID Interrupt Flag (Bit 14)
The ID Interrupt Flag bit indicates the status of the OTG ID interrupt (only for Port 1A). When enabled this interrupt will trigger on
both the rising and falling edge of the OTG ID pin. This bit is only available for Device 1 and is a reserved bit in Device 2.
1: Interrupt triggered
0: Interrupt did not trigger
SOF/EOP Interrupt Flag (Bit 9)
The SOF/EOP Interrupt Flag bit indicates if the SOF/EOP received interrupt has triggered.
1: Interrupt triggered
0: Interrupt did not trigger
Reset Interrupt Flag (Bit 8)
The Reset Interrupt Flag bit indicates if the USB Reset Detected interrupt has triggered.
1: Interrupt triggered
0: Interrupt did not trigger
EP7 Interrupt Flag (Bit 7)
The EP7 Interrupt Flag bit indicates if the endpoint seven (EP7) Transaction Done interrupt has triggered. An EPx Transaction
Done interrupt will trigger when any of the following responses or events occur in a transaction for the devices given EP:
send/receive ACK, send STALL, Time-out occurs, IN Exception Error, or OUT Exception Error. In addition, if the NAK Interrupt
Enable bit in the Device n Endpoint Control Register is set, this interrupt will also trigger when the device NAKs host requests.
1: Interrupt triggered
0: Interrupt did not trigger
EP6 Interrupt Flag (Bit 6)
The EP6 Interrupt Flag bit indicates if the endpoint six (EP6) Transaction Done interrupt has triggered. An EPx Transaction Done
interrupt will trigger when any of the following responses or events occur in a transaction for the devices given EP: send/receive
ACK, send STALL, Time-out occurs, IN Exception Error, or OUT Exception Error. In addition, if the NAK Interrupt Enable bit in
the Device n Endpoint Control Register is set, this interrupt will also trigger when the device NAKs host requests.
1: Interrupt triggered
0: Interrupt did not trigger
EP5 Interrupt Flag (Bit 5)
The EP5 Interrupt Flag bit indicates if the endpoint five (EP5) Transaction Done interrupt has triggered. An EPx Transaction Done
interrupt will trigger when any of the following responses or events occur in a transaction for the devices given EP: send/receive
ACK, send STALL, Time-out occurs, IN Exception Error, or OUT Exception Error. In addition, if the NAK Interrupt Enable bit in
the Device n Endpoint Control Register is set, this interrupt will also trigger when the device NAKs host requests.
1: Interrupt triggered
0: Interrupt did not trigger
EP4 Interrupt Flag (Bit 4)
The EP4 Interrupt Flag bit indicates if the endpoint four (EP4) Transaction Done interrupt has triggered. An EPx Transaction Done
interrupt will trigger when any of the following responses or events occur in a transaction for the devices given EP: send/receive
ACK, send STALL, Time-out occurs, IN Exception Error, or OUT Exception Error. In addition, if the NAK Interrupt Enable bit in
the Device n Endpoint Control Register is set, this interrupt will also trigger when the device NAKs host requests.
1: Interrupt triggered
0: Interrupt did not trigger
EP3 Interrupt Flag (Bit 3)
The EP3 Interrupt Flag bit indicates if the endpoint three (EP3) Transaction Done interrupt has triggered. An EPx Transaction
Done interrupt will trigger when any of the following responses or events occur in a transaction for the devices given EP:
send/receive ACK, send STALL, Time-out occurs, IN Exception Error, or OUT Exception Error. In addition, if the NAK Interrupt
Enable bit in the Device n Endpoint Control Register is set, this interrupt will also trigger when the device NAKs host requests.
1: Interrupt triggered
0: Interrupt did not trigger
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PRELIMINARY
CY7C67300
EP2 Interrupt Flag (Bit 2)
The EP2 Interrupt Flag bit indicates if the endpoint two (EP2) Transaction Done interrupt has triggered. An EPx Transaction Done
interrupt will trigger when any of the following responses or events occur in a transaction for the devices given EP: send/receive
ACK, send STALL, Time-out occurs, IN Exception Error, or OUT Exception Error. In addition, if the NAK Interrupt Enable bit in
the Device n Endpoint Control Register is set, this interrupt will also trigger when the device NAKs host requests.
1: Interrupt triggered
0: Interrupt did not trigger
EP1 Interrupt Flag (Bit 1)
The EP1 Interrupt Flag bit indicates if the endpoint one (EP1) Transaction Done interrupt has triggered. An EPx Transaction Done
interrupt will trigger when any of the following responses or events occur in a transaction for the devices given EP: send/receive
ACK, send STALL, Time-out occurs, IN Exception Error, or OUT Exception Error. In addition, if the NAK Interrupt Enable bit in
the Device n Endpoint Control Register is set, this interrupt will also trigger when the device NAKs host requests.
1: Interrupt triggered
0: Interrupt did not trigger
EP0 Interrupt Flag (Bit 0)
The EP0 Interrupt Flag bit indicates if the endpoint zero (EP0) Transaction Done interrupt has triggered. An EPx Transaction
Done interrupt will trigger when any of the following responses or events occur in a transaction for the devices given EP:
send/receive ACK, send STALL, Time-out occurs, IN Exception Error, or OUT Exception Error. In addition, if the NAK Interrupt
Enable bit in the Device n Endpoint Control Register is set, this interrupt will also trigger when the device NAKs host requests.
1: Interrupt triggered
0: Interrupt did not trigger
Reserved
All reserved bits should be written as ‘0’.
7.6.10 Device n Frame Number Register [R]
• Device 1 Frame Number Register 0xC092
• Device 2 Frame Number Register 0xC0B2
Bit #
15
Field
SOF/EOP
Time-out Flag
14
13
12
Read/Write
R
R
R
R
-
R
R
R
Default
0
0
0
0
0
0
0
0
Bit #
7
6
5
4
3
2
1
0
SOF/EOP
Time-out Interrupt Counter
11
10
Reserved
Field
9
8
Frame...
...Frame
Read/Write
R
R
R
R
R
R
R
R
Default
0
0
0
0
0
0
0
0
Figure 7-42. Device n Frame Number Register
Register Description
The Device n Frame Number Register is a read-only register that contains the Frame number of the last SOF packet received.
This register also contains a count of SOF/EOP Time-out occurrences.
SOF/EOP Time-out Flag (Bit 15)
The SOF/EOP Time-out Flag bit indicates when an SOF/EOP Time-out Interrupt occurs.
1: An SOF/EOP Time-out interrupt occurred.
0: An SOF/EOP Time-out interrupt did not occur.
SOF/EOP Time-out Interrupt Counter (Bits [14:12])
The SOF/EOP Time-out Interrupt Counter field will increment by 1 from 0 to 7 for each SOF/EOP Time-out Interrupt. This field
resets to 0 when a SOF/EOP is received. This field is only updated when the SOF/EOP Time-out Interrupt Enable bit in the Device
n Interrupt Enable Register is set.
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CY7C67300
Frame (Bits [10:0])
The Frame field contains the frame number from the last received SOF packet in full-speed mode. This field has no function for
low-speed mode. If a SOF Time-out occurs, this field will contain the last received Frame number.
7.6.11 Device n SOF/EOP Count Register [W]
• Device 1 SOF/EOP Count Register 0xC094
• Device 2 SOF/EOP Count Register 0xC0B4
Bit #
15
Field
14
13
12
11
Reserved
10
9
8
Count...
Read/Write
-
-
R
R
R
R
R
R
Default
0
0
1
0
1
1
1
0
Bit #
7
6
5
4
3
2
1
0
Field
...Count
Read/Write
R
R
R
R
R
R
R
R
Default
1
1
1
0
0
0
0
0
Figure 7-43. Device n SOF/EOP Count Register
Register Description
The Device n SOF/EOP Count Register should be written with the time expected between receiving a SOF/EOPs. If the SOF/EOP
counter expires before an SOF/EOP is received, an SOF/EOP Time-out Interrupt can be generated. The SOF/EOP Time-out
Interrupt Enable and SOF/EOP Time-out Interrupt Flag are located in the Device n Interrupt Enable and Status Registers respectively.
The SOF/EOP count should be set slightly greater than the expected SOF/EOP interval. The SOF/EOP counter decrements at
a 12-MHz rate. Therefore, in the case of an expected 1-ms SOF/EOP interval, the SOF/EOP count should be set slightly greater
then 0x2EE0.
Count (Bits [13:0])
The Count field contains the current value of the SOF/EOP down counter. At power-up and reset, this value is set to 0x2EE0 and
for expected 1-ms SOF/EOP intervals, this SOF/EOP count should be increased slightly.
Reserved
All reserved bits should be written as ‘0’.
7.7
OTG Control Registers
There is one register dedicated for On-The-Go operation. This register is covered in this section and summarized in Figure 7-44.
Register Name
Address
OTG Control Register
R/W
C098H
R/W
Figure 7-44. OTG Registers
7.7.1
OTG Control Register [0xC098] [R/W]
Bit #
15
Field
14
Reserved
13
12
VBUS
Pull-up Enable
Receive
Disable
11
10
Charge Pump
VBUS
Enable
Discharge Enable
9
8
D+
Pull-up Enable
D–
Pull-up Enable
Read/Write
-
-
R/W
R/W
R/W
R/W
R/W
R/W
Default
0
0
0
0
0
0
0
0
5
Bit #
7
6
4
Field
D+
Pull-down Enable
D–
Pull-down Enable
Read/Write
R/W
R/W
-
-
Default
0
0
0
0
3
2
1
0
OTG Data
Status
ID
Status
VBUS Valid
Flag
-
R
R
R
0
X
X
X
Reserved
Figure 7-45. OTG Control Register
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Register Description
The OTG Control Register allows control and monitoring over the OTG port on Port1A.
VBUS Pull-up Enable (Bit 13)
The VBUS Pull-up Enable bit enables or disables a 500Ω pull-up resistor onto OTG VBus.
1: 500Ω pull-up resistor enabled
0: 500Ω pull-up resistor disabled
Receive Disable (Bit 12)
The Receive Disable bit enables or powers down (disables) the OTG receiver section.
1: OTG receiver powered down and disabled
0: OTG receiver enabled
Charge Pump Enable (Bit 11)
The Charge Pump Enable bit enables or disables the OTG VBus charge pump.
1: OTG VBus charge pump enabled
0: OTG VBus charge pump disabled
VBUS Discharge Enable (Bit 10)
The VBUS Discharge Enable bit enables or disables a 2KΩ discharge pull-down resistor onto OTG VBus.
1: 2KΩ pull-down resistor enabled
0: 2KΩ pull-down resistor disabled
D+ Pull-up Enable (Bit 9)
The D+ Pull-up Enable bit enables or disables a pull-up resistor on the OTG D+ data line.
1: OTG D+ dataline pull-up resistor enabled
0: OTG D+ dataline pull-up resistor disabled
D– Pull-up Enable (Bit 8)
The D– Pull-up Enable bit enables or disables a pull-up resistor on the OTG D- data line.
1: OTG D– dataline pull-up resistor enabled
0: OTG D– dataline pull-up resistor disabled
D+ Pull-down Enable (Bit 7)
The D+ Pull-down Enable bit enables or disables a pull-down resistor on the OTG D+ data line.
1: OTG D+ dataline pull-down resistor enabled
0: OTG D+ dataline pull-down resistor disabled
D– Pull-down Enable (Bit 6)
The D– Pull-down Enable bit enables or disables a pull-down resistor on the OTG D– data line.
1: OTG D– dataline pull-down resistor enabled
0: OTG D– dataline pull-down resistor disabled
OTG Data Status (Bit 2)
The OTG Data Status bit is a read-only bit and indicates the TTL logic state of the OTG VBus pin.
1: OTG VBus is greater then 2.4V
0: OTG VBus is less then 0.8V
ID Status (Bit 1)
The ID Status bit is a read-only bit that indicates the state of the OTG ID pin on Port A.
1: OTG ID Pin is not connected directly to ground (>10kΩ)
0: OTG ID Pin is connected directly ground (< 10Ω)
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VBUS Valid Flag (Bit 0)
The VBUS Valid Flag bit indicates whether OTG VBus is greater then 4.4V. After turning on VBUS, firmware should wait at least
10 µs before this reading this bit.
1: OTG VBus is greater then 4.4V
0: OTG VBus is less then 4.4V
Reserved
All reserved bits should bit written as ‘0’.
7.8
GPIO Registers
There are seven registers dedicated for GPIO operations. These seven registers are covered in this section and summarized in
Figure 7-46.
Register Name
GPIO Control Register
GPIO0 Output Data Register
GPIO0 Input Data Register
GPIO0 Direction Register
GPIO1 Output Data Register
GPIO1 Input Data Register
GPIO1 Direction Register
Address
0xC006
0xC01E
0xC020
0xC022
0xC024
0xC026
0xC028
R/W
R/W
R/W
R
R/W
R/W
R
R/W
Figure 7-46. GPIO Registers
7.8.1
GPIO Control Register [0xC006] [R/W]
Bit #
15
14
Field
Write Protect
Enable
UD
13
12
11
10
Read/Write
R/W
R/W
-
-
R/W
R/W
R/W
R/W
Default
0
0
0
0
0
0
0
0
SAS
Enable
Reserved
9
8
Mode
Select
Bit #
7
6
5
4
3
2
1
0
Field
HSS
Enable
HSS XD
Enable
SPI
Enable
SPI XD
Enable
Interrupt 1
Polarity Select
Interrupt 1
Enable
Interrupt 0
Polarity Select
Interrupt 0
Enable
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Default
0
0
0
0
0
0
0
0
Figure 7-47. GPIO Control Register
Register Description
The GPIO Control Register configures the GPIO pins for various interface options. It also controls the polarity of the GPIO interrupt
on IRQ1 (GPIO25) and IRQ0 (GPIO24).
Write Protect Enable (Bit 15)
The Write Protect Enable bit enables or disables the GPIO write protect. When Write Protect is enabled, the GPIO Mode Select
[10:8] field read-only until a chip reset.
1: Enable Write Protect
0: Disable Write Protect
UD (Bit 14)
The UD bit routes the Host/Device 1A Port’s transmitter enable status to GPIO[30]. This is for use with an external ESD protection
circuit when needed.
1: Route the signal to GPIO[30]
0: Do not route the signal to GPIO[30]
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SAS Enable (Bit 11)
The SAS Enable bit, when in SPI mode, will reroute the SPI port SPI_nSSI pin to GPIO[15] rather then GPIO[9] or XD[9] (per
SG/SX).
1: Reroute SPI_nss to GPIO[30]
0: Leave SPI_nss on GPIO[9]
Mode Select (Bits [10:8])
The Mode Select field selects how GPIO[15:0] and GPIO[24:19] are used as defined in Table 7-10.
Table 7-10. Mode Select Definition
Mode Select [10:8]
111
GPIO Configuration
Reserved
110
SCAN — (HW) Scan diagnostic. For production test only. Not for normal operation
101
HPI — Host Port Interface
100
IDE — Integrated Drive Electronics or
011
Reserved
010
Reserved
001
Reserved
000
GPIO — General Purpose Input Output
HSS Enable (Bit 7)
The HSS Enable bit routes HSS to GPIO[26, 18:16]. If the HSS XD Enable bit is set, it will override this bit and HSS will be routed
to XD[15:12].
1: HSS is routed to GPIO
0: HSS is not routed to GPIOs. GPIO[26, 18:16] are free for other purposes.
HSS XD Enable (Bit 6)
The HSS XD Enable bit routes HSS to XD[15:12] (external memory data bus). This bit overrides the HSS Enable bit.
1: HSS is routed to XD[15:12]
0: HSS is not routed to XD[15:12]
SPI Enable (Bit 5)
The SPI Enable bit routes SPI to GPIO[11:8]. If the SAS Enable bit is set, it will override the SPI Enable and route SPI_nSSI to
GPIO15. If the SPI XD Enable bit is set, it will override both bits and the SPI will be routed to XD[11:8] (external memory data bus).
1: SPI is routed to GPIO[11:8]
0: SPI is not routed to GPIO[11:8]. GPIO[11:8] are free for other purposes.
SPI XD Enable (Bit 4)
The SPI XD Enable bit routes SPI to XD[11:8] (external memory data bus). This bit overrides the SPI Enable bit.
1: SPI is routed to XD[11:8]
0: SPI is not routed to XD[11:8]
Interrupt 1 Polarity Select (Bit 3)
The Interrupt 1 Polarity Select bit selects the polarity for IRQ1.
1: Sets IRQ1 to rising edge
0: Sets IRQ1 to falling edge
Interrupt 1 Enable (Bit 2)
The Interrupt 1 Enable bit enables or disables IRQ1. The GPIO bit on the interrupt Enable Register must also be set in order for
this for this interrupt to be enabled.
1: Enable IRQ1
0: Disable IRQ1
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Interrupt 0 Polarity Select (Bit 1)
The Interrupt 0 Polarity Select bit selects the polarity for IRQ0.
1: Sets IRQ0 to rising edge
0: Sets IRQ0 to falling edge
Interrupt 0 Enable (Bit 0)
The Interrupt 0 Enable bit enables or disables IRQ0. The GPIO bit on the interrupt Enable Register must also be set in order for
this for this interrupt to be enabled.
1: Enable IRQ0
0: Disable IRQ0
Reserved
All reserved bits should be written as ‘0’.
7.8.2
GPIO n Output Data Register [R/W]
• GPIO 0 Output Data Register 0xC01E
• GPIO 1 Output Data Register 0xC024
Bit #
15
14
13
12
Field
11
10
9
8
Data...
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Default
0
0
0
0
0
0
0
0
Bit #
7
6
5
4
3
2
1
0
Field
...Data
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Default
0
0
0
0
0
0
0
0
Figure 7-48. GPIO n Output Data Register
Register Description
The GPIO n Output Data Register controls the output data of the GPIO pins. The GPIO 0 Output Data Register controls GPIO15
to GPIO0 while the GPIO 1 Output Data Register controls GPIO31 to GPIO16. When read, this register reads back the last data
written, not the data on pins configured as inputs (see Input Data Register).
Data (Bits [15:0])
The Data field[15:0] writes to the corresponding GPIO 15–0 or GPIO31–16 pins as output data.
7.8.3
GPIO n Input Data Register [R]
• GPIO 0 Input Data Register 0xC020
• GPIO 1 Input Data Register 0xC026
Bit #
15
14
13
12
Field
11
10
9
8
Data...
Read/Write
R
R
R
R
R
R
R
R
Default
0
0
0
0
0
0
0
0
Bit #
7
6
5
4
3
2
1
0
Field
...Data
Read/Write
R
R
R
R
R
R
R
R
Default
0
0
0
0
0
0
0
0
Figure 7-49. GPIO n Input Data Register
Register Description
The GPIO n Input Data Register reads the input data of the GPIO pins. The GPIO 0 Input Data Register reads from GPIO15 to
GPIO0 while the GPIO 1 Input Data Register reads from GPIO31 to GPIO16.
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Data (Bits [15:0])
The Data field[15:0] contains the voltage values on the corresponding GPIO15–0 or GPIO31–16 input pins.
7.8.4
GPIO n Direction Register [R/W]
• GPIO 0 Direction Register 0xC022
• GPIO 1 Direction Register 0xC028
Bit #
15
14
13
Field
12
11
10
9
8
Direction Select...
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Default
0
0
0
0
0
0
0
0
Bit #
7
6
5
4
3
2
1
0
Field
...Direction Select
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Default
0
0
0
0
0
0
0
0
Figure 7-50. GPIO n Direction Register
Register Description
The GPIO n Direction Register controls the direction of the GPIO data pins (input/output). The GPIO 0 Direction Register controls
GPIO15 to GPIO0 while the GPIO 1 Direction Register controls GPIO31 to GPIO16.
Direction Select (Bits [15:0])
The Direction Select field[15:0] configures the corresponding GPIO15–0 or GPIO31–16 pins as either input or output. When any
bit of this register is set to ‘1’, the corresponding GPIO data pin becomes an output. When any bit of this register is set to ‘0’, the
corresponding GPIO data pin becomes an input.
7.9
IDE Registers
In addition to the standard IDE PIO Port registers, there are four registers dedicated to IDE operation. These registers are covered
in this section and summarized in Figure 7-51.
Register Name
Address
0xC048
0xC04A
0xC04C
0xC04E
0xC050-0xC06F
IDE Mode Register
IDE Start Address Register
IDE Stop Address Register
IDE Control Register
IDE PIO Port Registers
R/W
R/W
R/W
R/W
R/W
R/W
Figure 7-51. IDE Registers
7.9.1
IDE Mode Register [0xC048] [R/W]
Bit #
15
14
13
12
Field
11
10
9
8
Reserved...
Read/Write
-
-
-
-
-
-
-
-
Default
0
0
0
0
0
0
0
0
Bit #
7
6
5
4
3
2
1
0
Field
...Reserved
Mode Select
Read/Write
-
-
-
-
R/W
R/W
R/W
R/W
Default
0
0
0
0
0
0
0
0
Figure 7-52. IDE Mode Register
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Register Description
The IDE Mode Register allows the selection of IDE PIO Modes 0, 1, 2, 3, or 4. The default setting is zero which means IDE PIO
Mode 0.
Mode Select (Bits [2:0])
The Mode Select field sets PIO Mode 0 to 4 in IDE mode. Please refer to Table 7-11 for a definition of this field.
Table 7-11. Mode Select Definition
Mode Select [2:0]
Mode
000
IDE PIO Mode 0
001
IDE PIO Mode 1
010
IDE PIO Mode 2
011
IDE PIO Mode 3
100
IDE PIO Mode 4
101
Reserved
110
Reserved
111
Disable IDE port operations
Reserved
All reserved bits should be written as ‘0’.
7.9.2
IDE Start Address Register [0xC04A] [R/W]
Bit #
15
14
13
12
Field
11
10
9
8
Address...
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Default
0
0
0
0
0
0
0
0
Bit #
7
6
5
4
3
2
1
0
Field
...Address
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Default
0
0
0
0
0
0
0
0
Figure 7-53. IDE Start Address Register
Register Description
The IDE Start Address Register holds the start address for an IDE block transfer. This register is byte addressed and IDE block
transfers are 16-bit words, therefore the LSB of the start address is ignored. Block transfers begin at IDE Start Address and end
with the final word at IDE Stop Address. When IDE Start Address equals IDE Stop Address, the block transfer moves one word
of data.
The hardware keeps an internal memory address counter. The two MSBs of the addresses are not modified by the address
counter. Therefore the IDE Start Address and IDE Stop Address must reside within the same 16-Kbyte block.
Address (Bits [15:0])
The Address field sets the start address for an IDE block transfer.
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7.9.3
CY7C67300
IDE Stop Address Register [0xC04C] [R/W]
Bit #
15
14
13
12
11
10
9
8
Read/Write
R/W
R/W
R/W
R/W
Default
0
0
R/W
R/W
R/W
R/W
0
0
0
0
0
0
Bit #
7
6
5
4
3
2
1
0
Read/Write
R/W
R/W
R/W
R/W
Default
R/W
R/W
R/W
R/W
0
0
0
0
0
0
0
0
Field
Address...
Field
...Address
Figure 7-54. IDE Stop Address Register
Register Description
The IDE Stop Address Register holds the stop address for an IDE block transfer. This register is byte addressed and IDE block
transfers are 16-bit words therefore the LSB of the stop address is ignored. Block transfers begin at IDE Start Address and end
with the final word at IDE Stop Address. When IDE Start Address equals IDE Stop Address, the block transfer moves one word
of data.
The hardware keeps an internal memory address counter. The two MSBs of the addresses are not modified by the address
counter. Therefore the IDE Start Address and IDE Stop Address must reside within the same 16-Kbyte block.
Address (Bits [15:0])
The Address field sets the stop address for an IDE block transfer.
7.9.4
IDE Control Register [0xC04E] [R/W]
Bit #
15
14
13
12
Field
11
10
9
8
Reserved...
Read/Write
-
-
-
-
-
-
-
-
Default
0
0
0
0
0
0
0
0
Bit #
7
6
5
4
Field
...Reserved
3
2
1
0
Direction
Select
IDE
Interrupt
Enable
Done
Flag
IDE
Enable
Read/Write
-
-
-
-
R/W
R/W
R/W
R/W
Default
0
0
0
0
0
0
0
0
Figure 7-55. IDE Control Register
Register Description
The IDE Control Register controls block transfers in IDE mode.
Direction Select (Bit 3)
The Direction Select bit sets the block mode transfer direction.
1: Data is written to the external device
0: Data is read from the external device
IDE Interrupt Enable (Bit 2)
The IDE Interrupt Enable bit enables or disables the block transfer done interrupt. When enabled, the Done Flag is sent to the
CPU as cpuide_intr interrupt. When disabled, the cpuide_intr is set LOW.
1: Enable block transfer done interrupt
0: Disable block transfer done interrupt
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Done Flag (Bit 1)
The Done Flag bit is automatically set to ‘1’ by hardware when a block transfer is complete. The CPU clears this bit by writing a
‘0’ to it. When IDE Interrupt Enable is set this bit generates the signal for the cpuide_intr interrupt.
1: Block transfer is complete
0: Clears IDE Done Flag
IDE Enable (Bit 0)
The IDE Enable bit will start a block transfer. It is reset to ‘0’ when the block transfer is complete
1: Start block transfer
0: Block transfer complete
Reserved
All reserved bits should be written as ‘0’.
7.9.5
IDE PIO Port Registers [0xC050 - 0xC06F] [R/W]
All IDE PIO Port Registers [0xC050 - 0xC06F] in Table 7-12 are defined in detail in the Information Technology-AT Attachment 4 with Packet Interface Extension (ATA/ATAPI-4) Specification, T13/1153D Rev 18. In Table 7-12 below, the Address column
denotes the CY7C67300 register address for the corresponding ATA/ATAPI register. The IDE_nCS[1:0] field defines the ATA
interface CS addressing bits and the IDE_A[2:0] field define the ATA interface address bits. The combination of IDE_nCS and
IDE_A are the ATA interface register address.
Table 7-12. IDE PIO Port Registers
7.10
Address
ATA/ATAPI Register
IDE_nCS[1:0]
IDE_A[2:0]
0xC050
DATA Register
‘10’
‘000’
0xC052
Read: Error Register
Write: Feature Register
‘10’
‘001’
0xC054
Sector Count Register
‘10’
‘010’
0xC056
Sector Number Register
‘10’
‘011’
0xC058
Cylinder Low Register
‘10’
‘100’
0xC05A
Cylinder High Register
‘10’
‘101’
0xC05C
Device/Head Register
‘10’
‘110’
0xC05E
Read: Status Register
Write: Command Register
‘10’
‘111’
0xC060
Not Defined
‘01’
‘000’
0xC062
Not Defined
‘01’
‘001’
0xC064
Not Defined
‘01’
‘010’
0xC066
Not Defined
‘01’
‘011’
0xC068
Not Defined
‘01’
‘100’
0xC06A
Not Defined
‘01’
‘101’
0xC06C
Read: Alternate Status Register
Write: Device Control Register
‘01’
‘110’
0xC06E
Not Defined
‘01’
‘111’
HSS Registers
There are eight registers dedicated to HSS operation. Each of these registers are covered in this section and summarized in
Figure 7-56.
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Register Name
HSS Control Register
HSS Baud Rate Register
HSS Transmit Gap Register
HSS Data Register
HSS Receive Address Register
HSS Receive Length Register
HSS Transmit Address Register
HSS Transmit Length Register
CY7C67300
Address
0xC070
0xC072
0xC074
0xC076
0xC078
0xC07A
0xC07C
0xC07E
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Figure 7-56. HSS Registers
7.10.1
HSS Control Register [0xC070] [R/W]
Bit #
15
14
13
12
11
10
9
8
Field
HSS
Enable
RTS
Polarity
Select
CTS
Polarity
Select
XOFF
XOFF
Enable
CTS
Enable
Receive
Interrupt
Enable
Done
Interrupt
Enable
Read/Write
R/W
R/W
R/W
R
R/W
R/W
R/W
R/W
Default
0
0
0
0
0
0
0
0
7
6
Bit #
Field
Transmit
Receive
Done Interrupt Done Interrupt
Enable
Enable
5
4
3
2
1
0
One
Stop Bit
Transmit
Ready
Packet
Mode
Select
Receive
Overflow
Flag
Receive
Packet Ready
Flag
Receive
Ready
Flag
Read/Write
R/W
R/W
R/W
R
R/W
R/W
R
R
Default
0
0
0
0
0
0
0
0
Figure 7-57. HSS Control Register
Register Description
The HSS Control Register provides high-level status and control over the HSS port.
HSS Enable (Bit 15)
The HSS Enable bit enables or disables HSS operation.
1: Enables HSS operation
0: Disables HSS operation
RTS Polarity Select (Bit 14)
The RTS Polarity Select bit selects the polarity of RTS.
1: RTS is true when LOW
0: RTS is true when HIGH
CTS Polarity Select (Bit 13)
The CTS Polarity Select bit selects the polarity of CTS.
1: CTS is true when LOW
0: CTS is true when HIGH
XOFF (Bit 12)
The XOFF bit is a read-only bit that indicates if an XOFF has been received. This bit will automatically clear when an XON has
been received.
1: XOFF received
0: XON received
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XOFF Enable (Bit 11)
The XOFF Enable bit enables or disables XON/XOFF software handshaking.
1: Enable XON/XOFF software handshaking
0: Disable XON/XOFF software handshaking
CTS Enable (Bit 10)
The CTS Enable bit enables or disables CTS/RTS hardware handshaking.
1: Enable CTS/RTS hardware handshaking
0: Disable CTS/RTS hardware handshaking
Receive Interrupt Enable (Bit 9)
The Receive Interrupt Enable bit enables or disables the Receive Ready and Receive Packet Ready interrupts.
1: Enable the Receive Ready and Receive Packet Ready interrupts
0: Disable the Receive Ready and Receive Packet Ready interrupts
Done Interrupt Enable (Bit 8)
The Done Interrupt Enable bit enables or disables the Transmit Done and Receive Done interrupts.
1: Enable the Transmit Done and Receive Done interrupts
0: Disable the Transmit Done and Receive Done interrupts
Transmit Done Interrupt Flag (Bit 7)
The Transmit Done Interrupt Flag bit indicates the status of the Transmit Done Interrupt. It will set when a block transmit is finished.
To clear the interrupt, a ‘1’ should be written to this bit.
1: Interrupt triggered
0: Interrupt did not trigger
Receive Done Interrupt Flag (Bit 6)
The Receive Done Interrupt Flag bit indicates the status of the Receive Done Interrupt. It will set when a block transmit is finished.
To clear the interrupt, a ‘1’ should be written to this bit.
1: Interrupt triggered
0: Interrupt did not trigger
One Stop Bit (Bit 5)
The One Stop Bit bit selects between one and two stop bits for transmit byte mode. In receive mode, the number of stop bits may
vary and does not need to be fixed.
1: One stop bit
0: Two stop bits
Transmit Ready (Bit 4)
The Transmit Ready bit is a read-only bit that indicates if the HSS Transmit FIFO is ready for the CPU to load new data for
transmission.
1: HSS transmit FIFO ready for loading
0: HSS transmit FIFO not ready for loading
Packet Mode Select (Bit 3)
The Packet Mode Select bit selects between Receive Packet Ready and Receive Ready as the interrupt source for the RxIntr
interrupt.
1: Selects Receive Packet Ready as the source
0: Selects Receive Ready as the source
Receive Overflow Flag (Bit 2)
The Receive Overflow Flag bit indicates if the Receive FIFO overflowed when set. This flag can be cleared by writing a ‘1’ to this
bit.
1: Overflow occurred
0: Overflow did not occur
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Receive Packet Ready Flag (Bit 1)
The Receive Packet Ready Flag bit is a read only bit that indicates if the HSS receive FIFO is full with eight bytes or not.
1: HSS receive FIFO is full
0: HSS receive FIFO is not full
Receive Ready Flag (Bit 0)
The Receive Ready Flag is a read only bit that indicates if the HSS receive FIFO is empty or not.
1: HSS receive FIFO is not empty (one or more bytes is reading for reading)
0: HSS receive FIFO is empty
7.10.2
HSS Baud Rate Register [0xC072] [R/W]
Bit #
15
Field
14
13
12
11
Reserved
10
9
8
Baud...
Read/Write
-
-
-
R/W
R/W
R/W
R/W
R/W
Default
0
0
0
0
0
0
0
0
Bit #
7
6
5
4
3
2
1
0
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Default
0
0
0
1
0
1
1
1
Field
...Baud
Figure 7-58. HSS Baud Rate Register
Register Description
The HSS Baud Rate Register will set the HSS Baud Rate. At reset, the default value is 0x0017 which will set the baud rate to
2.0 MHz.
Baud (Bits [12:0])
The Baud field is the baud rate divisor minus one, in units of 1/48 MHz. Therefore the Baud Rate = 48 MHz/(Baud + 1). This puts
a constraint on the Baud Value as follows: (24 – 1) £ Baud Š (5000 – 1)
Reserved
All reserved bits should be written as ‘0’.
7.10.3
HSS Transmit Gap Register [0xC074] [R/W]
Bit #
15
14
13
12
Read/Write
-
-
-
-
-
-
-
-
Default
0
0
0
0
0
0
0
0
Bit #
7
6
5
4
3
2
1
0
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Default
0
0
0
0
1
0
0
1
Field
11
10
9
8
Reserved
Field
Transmit Gap Select
Figure 7-59. HSS Transmit Gap Register
Register Description
The HSS Transmit Gap Register is only valid in block transmit mode. It allows for a programmable number of stop bits to be
inserted thus overwriting the One Stop Bit in the HSS Control Register. The default reset value of this register is 0x0009, equivalent
to two stop bits.
Transmit Gap Select (Bits [7:0])
The Transmit Gap Select field sets the inactive time between transmitted bytes. The inactive time = (Transmit Gap Select – 7) *
bit time. Therefore an Transmit Gap Select Value of 8 is equal to having one Stop bit.
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Reserved
All reserved bits should be written as ‘0’.
7.10.4
HSS Data Register [0xC076] [R/W]
Bit #
15
14
13
12
Read/Write
-
-
-
-
-
-
-
-
Default
X
X
X
X
X
X
X
X
Bit #
7
6
5
4
3
2
1
0
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Default
X
X
X
X
X
X
X
X
Field
11
10
9
8
Reserved
Field
Data
Figure 7-60. HSS Data Register
Register Description
The HSS Data Register contains data received on the HSS port (not for block receive mode) when read. This receive data is valid
when the Receive Ready bit of the HSS Control Register is set to ‘1’. Writing to this register will initiate a single byte transfer of
data. The Transmit Ready Flag in the HSS Control Register should read ‘1’ before writing to this register (this avoids disrupting
the previous/current transmission).
Data (Bits [7:0])
The Data field contains the data received or to be transmitted on the HSS port.
Reserved
All reserved bits should be written as ‘0’.
7.10.5
HSS Receive Address Register [0xC078] [R/W]
Bit #
15
14
13
12
Field
11
10
9
8
Address...
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Default
0
0
0
0
0
0
0
0
Bit #
7
6
5
4
3
2
1
0
Field
...Address
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Default
0
0
0
0
0
0
0
0
Figure 7-61. HSS Receive Address Register
Register Description
The HSS Receive Address Register is used as the base pointer address for the next HSS block receive transfer.
Address (Bits [15:0])
The Address field sets the base pointer address for the next HSS block receive transfer.
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7.10.6
CY7C67300
HSS Receive Counter Register [0xC07A] [R/W]
Bit #
15
14
13
12
11
10
9
Read/Write
-
-
-
-
-
-
R/W
Default
0
R/W
0
0
0
0
0
0
0
Bit #
7
6
5
4
3
2
1
0
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Default
0
0
0
0
0
0
0
0
Field
Reserved
8
Counter...
Field
...Counter
Figure 7-62. HSS Receive Counter Register
Register Description
The HSS Receive Counter Register designates the block byte length for the next HSS receive transfer. This register should be
loaded with the word count minus one to start the block receive transfer. As each byte is received this register value is decremented. When read, this register indicates the remaining length of the transfer.
Counter (Bits [9:0])
The Counter field value is equal to the word count minus one giving a maximum value of 0x03FF (1023) or 2048 bytes. When
the transfer is complete this register returns 0x03FF until reloaded.
Reserved
All reserved bits should be written as ‘0’.
7.10.7
HSS Transmit Address Register [0xC07C] [R/W]
Bit #
15
14
13
12
Field
11
10
9
8
Address...
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Default
0
0
0
0
0
0
0
0
Bit #
7
6
5
4
3
2
1
0
Field
...Address
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Default
0
0
0
0
0
0
0
0
Figure 7-63. HSS Transmit Address Register
Register Description
The HSS Transmit Address Register is used as the base pointer address for the next HSS block transmit transfer.
Address (Bits [15:0])
The Address field sets the base pointer address for the next HSS block transmit transfer.
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7.10.8
CY7C67300
HSS Transmit Counter Register [0xC07E] [R/W]
Bit #
15
14
13
12
11
10
9
Read/Write
-
-
-
-
-
-
R/W
Default
0
R/W
0
0
0
0
0
0
0
Bit #
7
6
5
4
3
2
1
0
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Default
0
0
0
0
0
0
0
0
Field
Reserved
8
Counter...
Field
...Counter
Figure 7-64. HSS Transmit Counter Register
Register Description
The HSS Transmit Counter Register designates the block byte length for the next HSS transmit transfer. This register should be
loaded with the word count minus one to start the block transmit transfer. As each byte is transmitted this register value is
decremented. When read, this register indicates the remaining length of the transfer.
Counter (Bits [9:0])
The Counter field value is equal to the word count minus one giving a maximum value of 0x03FF (1023) or 2048 bytes. When
the transfer is complete this register returns 0x03FF until reloaded.
Reserved
All reserved bits should be written as ‘0’.
7.11
HPI Registers
There are five registers dedicated to HPI operation. In addition, there is an HPI status port which can be address over HPI. Each
of these registers is covered in this section and are summarized in Figure 7-65.
Register Name
Address
HPI Breakpoint Register
Interrupt Routing Register
SIE1msg Register
SIE2msg Register
HPI Mailbox Register
0x0140
0x0142
0x0144
0x0148
0xC0C6
R/W
R
R
W
W
R/W
Figure 7-65. HPI Registers
7.11.1
HPI Breakpoint Register [0x0140] [R]
Bit #
15
14
13
12
Field
11
10
9
8
Address...
Read/Write
R
R
R
R
R
R
R
R
Default
0
0
0
0
0
0
0
0
Bit #
7
6
5
4
3
2
1
0
Field
...Address
Read/Write
R
R
R
R
R
R
R
R
Default
0
0
0
0
0
0
0
0
Figure 7-66. HPI Breakpoint Register
Register Description
The HPI Breakpoint Register is a special on-chip memory location that the external processor can access using normal HPI
memory read/write cycles. The contents of this register have the same effect as the Breakpoint Register [0xC014]. This special
Breakpoint Register is used by software debuggers which interface through the HPI port instead of the serial port.
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CY7C67300
When the program counter matches the Breakpoint Address, the INT127 interrupt will trigger. To clear this interrupt, a zero value
should be written to this register.
Address (Bits [15:0])
The Address field is a 16-bit field containing the breakpoint address.
7.11.2
Interrupt Routing Register [0x0142] [R]
Bit #
15
14
Field
VBUS to HPI
Enable
ID to HPI
Enable
13
12
11
10
9
8
SOF/EOP2 to SOF/EOP2 to SOF/EOP1 to SOF/EOP1 to Reset2 to HPI
HPI Enable
CPU Enable
HPI Enable
CPU Enable
Enable
HPI Swap 1
Enable
Read/Write
-
-
-
-
-
-
-
-
Default
0
0
0
1
0
1
0
0
Bit #
7
6
5
4
3
2
1
0
Field
Resume2 to
HPI Enable
Resume1 to
HPI Enable
Reserved
Done2 to HPI Done1 to HPI Reset1 to HPI
Enable
Enable
Enable
HPI Swap 0
Enable
Read/Write
-
-
-
-
-
-
-
-
Default
0
0
0
0
0
0
0
0
Figure 7-67. Interrupt Routing Register
Register Description
The Interrupt Routing Register allows the HPI port to take over some or all of the SIE interrupts that usually go to the on-chip
CPU. This register is read only by the CPU but is read/write by the HPI port. By setting the appropriate bit to ‘1’, the SIE interrupt
is routed to the HPI port to become the HPI_INTR signal and also readable in the HPI Status Register. The bits in this register
select where the interrupts are routed. The individual interrupt enable is handled in the SIE interrupt enable register.
VBUS to HPI Enable (Bit 15)
The VBUS to HPI Enable bit routes the OTG VBUS interrupt to the HPI port instead of the on-chip CPU.
1: Route signal to HPI port
0: Do not route signal to HPI port
ID to HPI Enable (Bit 14)
The ID to HPI Enable bit routes the OTG ID interrupt to the HPI port instead of the on-chip CPU.
1: Route signal to HPI port
0: Do not route signal to HPI port
SOF/EOP2 to HPI Enable (Bit 13)
The SOF/EOP2 to HPI Enable bit routes the SOF/EOP2 interrupt to the HPI port.
1: Route signal to HPI port
0: Do not route signal to HPI port
SOF/EOP2 to CPU Enable (Bit 12)
The SOF/EOP2 to CPU Enable bit routes the SOF/EOP2 interrupt to the on-chip CPU. Since the SOF/EOP2 interrupt can be
routed to both the on-chip CPU and the HPI port the firmware must ensure only one of the two (CPU, HPI) resets the interrupt.
1: Route signal to CPU
0: Do not route signal to CPU
SOF/EOP1 to HPI Enable (Bit 11)
The SOF/EOP1 to HPI Enable bit routes the SOF/EOP1 interrupt to the HPI port.
1: Route signal to HPI port
0: Do not route signal to HPI port
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CY7C67300
SOF/EOP1 to CPU Enable (Bit 10)
The SOF/EOP1 to CPU Enable bit routes the SOF/EOP1 interrupt to the on-chip CPU. Since the SOF/EOP1 interrupt can be
routed to both the on-chip CPU and the HPI port the firmware must ensure only one of the two (CPU, HPI) resets the interrupt.
1: Route signal to CPU
0: Do not route signal to CPU
Reset2 to HPI Enable (Bit 9)
The Reset2 to HPI Enable bit routes the USB Reset interrupt that occurs on Device 2 to the HPI port instead of the onchip CPU.
1: Route signal to HPI port
0: Do not route signal to HPI port
HPI Swap 1 Enable (Bit 8)
Both HPI Swap bits (bits 8 and 0) must be set to identical values. When set to ‘00’, the most significant data byte goes to
HPI_D[15:8] and the least significant byte goes to HPI_D[7:0]. This is the default setting. By setting to ‘11’, the most significant
data byte goes to HPI_D[7:0] and the least significant byte goes to HPI_D[15:8].
Resume2 to HPI Enable (Bit 7)
The Resume2 to HPI Enable bit routes the USB Resume interrupt that occurs on Host 2 to the HPI port instead of the on-chip CPU.
1: Route signal to HPI port
0: Do not route signal to HPI port
Resume1 to HPI Enable (Bit 6)
The Resume1 to HPI Enable bit routes the USB Resume interrupt that occurs on Host 1 to the HPI port instead of the on-chip CPU.
1: Route signal to HPI port
0: Do not route signal to HPI port
Done2 to HPI Enable (Bit 3)
The Done2 to HPI Enable bit routes the Done interrupt for Host/Device 2 to the HPI port instead of the on-chip CPU.
1: Route signal to HPI port
0: Do not route signal to HPI port
Done1 to HPI Enable (Bit 2)
The Done1 to HPI Enable bit routes the Done interrupt for Host/Device 1 to the HPI port instead of the on-chip CPU.
1: Route signal to HPI port
0: Do not route signal to HPI port
Reset1 to HPI Enable (Bit 1)
The Reset1 to HPI Enable bit routes the USB Reset interrupt that occurs on Device 1 to the HPI port instead of the on-chip CPU.
1: Route signal to HPI port
0: Do not route signal to HPI port
HPI Swap 0 Enable (Bit 0)
Both HPI Swap bits (bits 8 and 0) must be set to identical values. When set to ‘00’, the most significant data byte goes to
HPI_D[15:8] and the least significant byte goes to HPI_D[7:0]. This is the default setting. By setting to ‘11’, the most significant
data byte goes to HPI_D[7:0] and the least significant byte goes to HPI_D[15:8].
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CY7C67300
7.11.3 SIEXmsg Register [W]
• SIE1msg Register 0x0144
• SIE2msg Register 0x0148
Bit #
15
14
13
12
Field
11
10
9
8
Data...
Read/Write
W
W
W
W
W
W
W
W
Default
X
X
X
X
X
X
X
X
Bit #
7
6
5
4
3
2
1
0
Field
...Data
Read/Write
W
W
W
W
W
W
W
W
Default
X
X
X
X
X
X
X
X
Figure 7-68. SIEXmsg Register
Register Description
The SIEXmsg Register allows an interrupt to be generated on the HPI port. Any write to this register will cause the SIEXmsg flag
in the HPI Status Port to go high and will also cause an interrupt on the HPI_INTR pin. The SIEXmsg flag is automatically cleared
when the HPI port reads from this register.
Data (Bits [15:0])
The Data field[15:0] simply needs to have any value written to it to cause SIExmsg flag in the HPI Status Port to go high.
7.11.4
HPI Mailbox Register [0xC0C6] [R/W]
Bit #
15
14
13
12
Field
11
10
9
8
Message...
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Default
0
0
0
0
0
0
0
0
Bit #
7
6
5
4
3
2
1
0
Field
...Message
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Default
0
0
0
0
0
0
0
0
Figure 7-69. HPI Mailbox Register
Register Description
The HPI Mailbox Register provides a common mailbox between the CY7C67300 and the external host processor.
If enabled, the HPI Mailbox RX Full interrupt will trigger when the external host processor writes to this register. When the
CY7C67300 reads this register the HPI Mailbox RX Full interrupt will automatically get cleared.
If enabled, the HPI Mailbox TX Empty interrupt will trigger when the external host processor reads from this register. The HPI
Mailbox TX Empty interrupt will automatically clear when the CY7C67300 writes to this register.
In addition, when the CY7C67300 writes to this register, the HPI_INTR signal on the HPI port will assert signaling the external
processor that there is data in the mailbox to read. The HPI_INTR signal will de-assert when the external host processor reads
from this register.
Message (Bits [15:0])
The Message field contains the message that the host processor wrote to the HPI Mailbox Register.
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7.11.5
CY7C67300
HPI Status Port [] [HPI: R]
Bit #
15
14
13
12
11
10
9
8
Field
VBUS
Flag
ID
Flag
Reserved
SOF/EOP2
Flag
Reserved
SOF/EOP1
Flag
Reset2
Flag
Mailbox In
Flag
Read/Write
R
R
-
R
-
R
R
R
Default
X
X
X
X
X
X
X
X
Bit #
7
6
5
4
3
2
1
0
Field
Resume2
Flag
Resume1
Flag
SIE2msg
SIE1msg
Done2
Flag
Done1
Flag
Reset1
Flag
Mailbox Out
Flag
Read/Write
R
R
R
R
R
R
R
R
Default
X
X
X
X
X
X
X
X
Figure 7-70. HPI Status Port
Register Description
The HPI Status Port provides the external host processor with the MailBox status bits plus several SIE status bits. This register
is not accessible from the on-chip CPU. The additional SIE status bits are provided to aid external device driver firmware
development, and are not recommended for applications that do not have an intimate relationship with the on-chip BIOS.
Reading from the HPI Status Port does not result in a CPU HPI interface memory access cycle. The external host may continuously poll this register without degrading the CPU or DMA performance.
VBUS Flag (Bit 15)
The VBUS Flag bit is a read-only bit that indicates whether OTG VBus is greater then 4.4V. After turning on VBUS, firmware
should wait at least 10 µs before this reading this bit.
1: OTG VBus is greater then 4.4V
0: OTG VBus is less then 4.4V
ID Flag (Bit 14)
The ID Flag bit is a read-only bit that indicates the state of the OTG ID pin.
SOF/EOP2 Flag (Bit 12)
The SOF/EOP2 Flag bit is a read-only bit that indicates if a SOF/EOP interrupt occurs on either Host/Device 2.
1: Interrupt triggered
0: Interrupt did not trigger
SOF/EOP1 Flag (Bit 10)
The SOF/EOP1 Flag bit is a read-only bit that indicates if a SOF/EOP interrupt occurs on either Host/Device 1.
1: Interrupt triggered
0: Interrupt did not trigger
Reset2 Flag (Bit 9)
The Reset2 Flag bit is a read-only bit that indicates if a USB Reset interrupt occurs on either Host/Device 2.
1: Interrupt triggered
0: Interrupt did not trigger
Mailbox In Flag (Bit 8)
The Mailbox In Flag bit is a read-only bit that indicates if a message is ready in the incoming mailbox. This interrupt clears when
on-chip CPU reads from the HPI Mailbox Register.
1: Interrupt triggered
0: Interrupt did not trigger
Resume2 Flag (Bit 7)
The Resume2 Flag bit is a read-only bit that indicates if a USB resume interrupt occurs on either Host/Device 2.
1: Interrupt triggered
0: Interrupt did not trigger
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CY7C67300
Resume1 Flag (Bit 6)
The Resume1 Flag bit is a read-only bit that indicates if a USB resume interrupt occurs on either Host/Device 1.
1: Interrupt triggered
0: Interrupt did not trigger
SIE2msg (Bit 5)
The SIE2msg Flag bit is a read only bit that indicates if the CY7C67300 CPU has written to the SIE2msg register. This bit will
clear on an HPI read.
1: The SIE2msg register has been written by the CY7C67300 CPU
0: The SIE2msg register has not been written by the CY7C67300 CPU
SIE1msg (Bit 4)
The SIE1msg Flag bit is a read only bit that indicates if the CY7C67300 CPU has written to the SIE1msg register. This bit will
clear on an HPI read.
1: The SIE1msg register has been written by the CY7C67300 CPU
0: The SIE1msg register has not been written by the CY7C67300 CPU
Done2 Flag (Bit 3)
In host mode the Done2 Flag bit is a read-only bit that indicates if a host packet done interrupt occurs on Host 2. In device mode
this read-only bit indicates if an any of the endpoint interrupts occurs on Device 2. Firmware will need to determine which endpoint
interrupt occurred.
1: Interrupt triggered
0: Interrupt did not trigger
Done1 Flag (Bit 2)
In host mode the Done 1 Flag bit is a read-only bit that indicates if a host packet done interrupt occurs on Host 1. In device mode
this read-only bit indicates if an any of the endpoint interrupts occurs on Device 1. Firmware will need to determine which endpoint
interrupt occurred.
1: Interrupt triggered
0: Interrupt did not trigger
Reset1 Flag (Bit 1)
The Reset1 Flag bit is a read-only bit that indicates if a USB Reset interrupt occurs on either Host/Device 1.
1: Interrupt triggered
0: Interrupt did not trigger
Mailbox Out Flag (Bit 0)
The Mailbox Out Flag bit is a read-only bit that indicates if a message is ready in the outgoing mailbox. This interrupt clears when
the external host reads from the HPI Mailbox Register.
1: Interrupt triggered
0: Interrupt did not trigger
7.12
SPI Registers
There are twelve registers dedicated to SPI operation. Each of these registers is covered in this section and summarized in
Figure 7-71.
Register Name
SPI Configuration Register
SPI Control Register
SPI Interrupt Enable Register
SPI Status Register
SPI Interrupt Clear Register
SPI CRC Control Register
Address
0xC0C8
0xC0CA
0xC0CC
0xC0CE
0xC0D0
0xC0D2
R/W
R/W
R/W
R/W
R
W
R/W
Figure 7-71. SPI Registers
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PRELIMINARY
SPI CRC Value
SPI Data Register
SPI Transmit Address Register
SPI Transmit Count Register
SPI Receive Address Register
SPI Receive Count Register
CY7C67300
0xC0D4
0xC0D6
0xC0D8
0xC0DA
0xC0DC
0xC0DE
R/W
R/W
R/W
R/W
R/W
R/W
Figure 7-71. SPI Registers (continued)
7.12.1
SPI Configuration Register [0xC0C8] [R/W]
Bit #
15
14
13
Field
3Wire
Enable
Phase
Select
SCK Polarity
Select
Read/Write
R/W
R/W
R/W
-
-
-
-
-
Default
1
0
0
0
0
0
0
0
4
3
2
1
0
Bit #
7
6
5
Field
Master
Active
Enable
Master
Enable
SS
Enable
Read/Write
R
R/W
Default
0
0
0
12
11
10
9
Scale Select
8
Reserved
SS Delay Select
R/W
R/W
R/W
R/W
R/W
1
1
1
1
1
Figure 7-72. SPI Configuration Register
Register Description
The SPI Configuration Register controls the SPI port. Fields apply to both master and slave mode unless otherwise noted.
3Wire Enable (Bit 15)
The 3Wire Enable bit indicates if the MISO and MOSI data lines are tied together allowing only half duplex operation.
1: MISO and MOSI data lines are tied together
0: Normal MISO and MOSI Full Duplex operation (not tied together)
Phase Select (Bit 14)
The Phase Select bit selects advanced or delayed SCK phase. This field only applies to master mode.
1: Advanced SCK phase
0: Delayed SCK phase
SCK Polarity Select (Bit 13)
This SCK Polarity Select bit selects the polarity of SCK.
1: Positive SCK polarity
0: Negative SCK polarity
Scale Select (Bits [12:9])
The Scale Select field provides control over the SCK frequency, based on 48 MHz. Please refer to Table 7-13 for a definition of
this field. This field only applies to master mode.
Table 7-13. Scale Select Field Definition for SCK Frequency
Scale Select [12:9]
SCK Frequency
0000
12 MHz
0001
8 MHz
0010
6 MHz
0011
4 MHz
0100
3 MHz
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Table 7-13. Scale Select Field Definition for SCK Frequency (continued)
Scale Select [12:9]
SCK Frequency
0101
2 MHz
0110
1.5 MHz
0111
1 MHz
1000
750 KHz
1001
500 KHz
1010
375 KHz
1011
250 KHz
1100
375 KHz
1101
250 KHz
1110
375 KHz
1111
250 KHz
Master Active Enable (Bit 7)
The Master Active Enable bit is a read only bit that indicates if the master state machine is active or idle. This field only applies
to master mode.
1: Master state machine is active
0: Master state machine is idle
Master Enable (Bit 6)
The Master Enable bit sets the SPI interface to master or slave. This bit is only writable when the Master Active Enable bit reads
‘0’, otherwise value will not change.
1: Master SPI interface
0: Slave SPI interface
SS Enable (Bit 5)
The SS Enable bit enables or disables the master SS output.
1: Enable master SS output
0: Disable master SS output (three-state master SS output, for single SS line in slave mode)
SS Delay Select (Bits [4:0])
When the SS Delay Select field is set to ‘00000’ this indicates manual mode. In manual mode SS is controlled by SS Manual bit
of the SPI Control Register. When the SS Delay Select field is set between ‘00001’ to ‘11111’, this value indicates the count in
half bit times of auto transfer delay for: SS low to SCK active, SCK inactive to SShigh, SS high time. This field only applies to
master mode.
7.12.2
SPI Control Register [0xC0CA] [R/W]
Bit #
15
14
13
12
11
10
9
8
Field
SCK
Strobe
FIFO
Init
Byte
Mode
Full Duplex
SS
Manual
Read
Enable
Transmit
Ready
Receive
Data
Ready
Read/Write
W
W
W
R
R
R
R
R/W
Default
0
0
0
0
0
0
0
1
5
4
3
2
1
0
Bit #
7
6
Field
Transmit
Empty
Receive
Full
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Default
1
0
0
0
0
0
0
0
Transmit Bit Length
Receive Bit Length
Figure 7-73. SPI Control Register
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Register Description
The SPI Control Register controls the SPI port. Fields apply to both master and slave mode unless otherwise noted.
SCK Strobe (Bit 15)
The SCK Strobe bit starts the SCK strobe at the selected frequency and polarity (set in the SPI Configuration Register), but not
phase. This bit feature can only be enabled when in master mode and must be during a period of inactivity. This bit is self clearing.
1: SCK Strobe Enable
0: No Function
FIFO Init (Bit 14)
The FIFO Init bit will initialize the FIFO and clear the FIFO Error Status bit. This bit is self clearing.
1: FIFO Init Enable
0: No Function
Byte Mode (Bit 13)
The Byte Mode bit selects between PIO (byte mode) and DMA (block mode) operation.
1: Set PIO (byte mode) operation
0: Set DMA (block mode) operation
Full Duplex (Bit 12)
The Full Duplex bit selects between full duplex and half duplex operation.
1: Enable full duplex. Full duplex is not allowed and will not set if the 3Wire Enable bit of the SPI Configuration Register is set to ‘1’
0: Enable half duplex operation
SS Manual (Bit 11)
The SS Manual bit activates or deactivates SS if the SS Delay Select field of the SPI Control Register is all zeros and is configured
as master interface. This field only applies to master mode.
1: Activate SS, master drives SS line asserted LOW
0: De-activate SS, master drives SS line deasserted HIGH
Read Enable (Bit 10)
The Read Enable bit will initiate a read phase for a master mode transfer or set the slave to receive (in slave mode).
1: Initiates a read phase for a master transfer or sets a slave to receive. In master mode this bit is sticky and remains set until
the read transfer begins.
0: Initiates the write phase for slave operation
Transmit Ready (Bit 9)
The Transmit Ready bit is a read-only bit that indicates if the transmit port is ready to empty and ready to be written.
1: Ready for data to be written to the port. The transmit FIFO is not full.
0: Not ready for data to be written to the port.
Receive Data Ready (Bit 8)
The Receive Data Ready bit is a read only bit that indicates if the receive port has data ready.
1: Receive port has data ready to read
0: Receive port does not have data ready
Transmit Empty (Bit 7)
The Transmit Empty bit is a read-only bit that indicates if the transmit FIFO is empty.
1: Transmit FIFO is empty
0: Transmit FIFO is not empty
Receive Full (Bit 6)
The Receive Full bit is a read only bit that indicates if the receive FIFO is full.
1: Receive FIFO is full
0: Receive FIFO is not full
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Transmit Bit Length (Bits [5:3])
The Transmit Bit Length field indicates the number of bits in the last transmitted byte or partial byte. If Transmit Bit Length is ‘000’
then the last transmitted byte is a full-byte transfer. If Transmit Bit Length is ‘001’ to ‘111’, then the value indicates the bit count
of the last transmitted partial byte.
Receive Bit Length (Bits [2:0])
The Receive Bit Length field indicates the number of bits in the last received byte or partial byte. If Receive Bit Length is ‘000’
then the last received byte is a full-byte transfer. If Receive Bit Length is ‘001’ to ‘111’, then the value indicates the bit count of
the last received partial byte.
7.12.3
SPI Interrupt Enable Register [0xC0CC] [R/W]
Bit #
15
14
13
12
Field
11
10
9
8
Reserved...
Read/Write
-
-
-
-
-
-
-
-
Default
0
0
0
0
0
0
0
0
Bit #
7
6
5
4
3
Field
...Reserved
2
1
0
Receive
Interrupt
Enable
Transmit
Interrupt
Enable
Transfer
Interrupt
Enable
Read/Write
-
-
-
-
-
R/W
R/W
R/W
Default
0
0
0
0
0
0
0
0
Figure 7-74. SPI Interrupt Enable Register
Register Description
The SPI Interrupt Enable Register controls the SPI port.
Receive Interrupt Enable (Bit 2)
The Receive Interrupt Enable bit will enable or disable the byte mode receive interrupt (RxIntVal).
1: Enable byte mode receive interrupt
0: Disable byte mode receive interrupt
Transmit Interrupt Enable (Bit 1)
The Transmit Interrupt Enable bit will enable or disable the byte mode transmit interrupt (TxIntVal).
1: Enables byte mode transmit interrupt
0: Disables byte mode transmit interrupt
Transfer Interrupt Enable (Bit 0)
The Transfer Interrupt Enable bit will enable or disable the block mode interrupt (XfrBlkIntVal).
1: Enables block mode interrupt
0: Disables block mode interrupt
Reserved
All reserved bits should be written as ‘0’.
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7.12.4
CY7C67300
SPI Status Register [0xC0CE] [R]
Bit #
15
14
13
12
Read/Write
-
-
-
-
-
-
-
-
Default
0
0
0
0
0
0
0
0
Bit #
7
6
5
4
3
2
1
0
Field
FIFO Error
Flag
Receive
Interrupt
Flag
Transmit
Interrupt
Flag
Transfer
Interrupt
Flag
Read/Write
R
-
-
-
-
R
R
R
Default
0
0
0
0
0
0
0
0
Field
11
10
9
8
Reserved
Reserved
Figure 7-75. SPI Status Register
Register Description
The SPI Status Register is a read-only register that provides status for the SPI port.
FIFO Error Flag (Bit 7)
The FIFO Error Flag bit is a read-only bit that indicates if a FIFO error occurred. When this bit is set to ‘1’ and the Transmit Empty
bit of the SPI Control Register is set to ‘1’, then a Tx FIFO underflow has occurred. Similarly, when set with the Receive Full bit
of the SPI Control Register, an Rx FIFO overflow has occured.This bit automatically clears when the SPI FIFO Init Enable bit of
the SPI Control register is set.
1: Indicates FIFO error
0: Indicates no FIFO error
Receive Interrupt Flag (Bit 2)
The Receive Interrupt Flag is a read-only bit that indicates a byte mode receive interrupt has triggered when set to ‘1’.
Transmit Interrupt Flag (Bit 1)
The Transmit Interrupt Flag is a read-only bit that indicates a byte mode transmit interrupt has triggered when set to ‘1’.
Transfer Interrupt Flag (Bit 0)
The Transfer Interrupt Flag is a read-only bit that indicates a block mode interrupt has triggered when set to ‘1’.
7.12.5
SPI Interrupt Clear Register [0xC0D0] [W]
Bit #
15
14
13
12
Field
11
10
9
8
Reserved
Read/Write
-
-
-
-
-
-
-
-
Default
0
0
0
0
0
0
0
0
Bit #
7
6
5
4
3
2
Field
Reserved
1
0
Transmit
Interrupt
Clear
Transfer
Interrupt
Clear
Read/Write
-
-
-
-
-
-
W
W
Default
0
0
0
0
0
0
0
0
Figure 7-76. SPI Interrupt Clear Register
Register Description
The SPI Interrupt Clear Register is a write-only register that allows the SPI Transmit and SPI Transfer Interrupts to be cleared.
Transmit Interrupt Clear (Bit 1)
The Transmit Interrupt Clear bit is a write-only bit that will clear the byte mode transmit interrupt when set to ‘1’. This bit is self
clearing.
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Transfer Interrupt Clear (Bit 0)
The Transfer Interrupt Clear bit is a write-only bit that will clear the block mode interrupt when set to ‘1’. This bit is self clearing.
Reserved
All reserved bits should be written as ‘0’.
7.12.6
SPI CRC Control Register [0xC0D2] [R/W]
Bit #
15
Field
14
CRC Mode
13
12
11
10
9
8
CRC
Enable
CRC
Clear
Receive
CRC
One in
CRC
Zero in
CRC
Reserved...
Read/Write
R/W
R/W
R/W
R/W
R/W
R
R
-
Default
0
0
0
0
0
0
0
0
Bit #
7
6
5
4
3
2
1
0
Read/Write
-
-
-
-
-
-
-
-
Default
0
0
0
0
0
0
0
0
Field
...Reserved
Figure 7-77. SPI CRC Control Register
Register Description
The SPI CRC Control Register provides control over the CRC source and polynomial value.
CRC Mode (Bits [15:14)
The CRCMode field selects the CRC polynomial as defined in Table 7-14.
Table 7-14. CRC Mode Definition
CRCMode [9:8]
00
01
10
11
CRC Polynomial
MMC 16-bit: X^16 + X^12 + X^5 + 1(CCITT Standard)
CRC7 7-bit: X^7+ X^3 + 1
MST 16-bit: X^16+ X^15 + X^2 + 1
Reserved, 16-bit polynomial 1.
CRC Enable (Bit 13)
The CRC Enable bit will enable or disable the CRC operation.
1: Enables CRC operation
0: Disables CRC operation
CRC Clear (Bit 12)
The CRC Clear bit will clear the CRC with a load of all ones. This bit is self clearing and always reads ‘0’.
1: Clear CRC with all ones
0: No Function
Receive CRC (Bit 11)
The Receive CRC bit determines whether the receive bit stream or the transmit bit stream is used for the CRC data input in full
duplex mode. This bit is a don’t care in half duplex mode.
1: Assigns the receive bit stream
0: Assigns the transmit bit stream
One in CRC (Bit 10)
The One in CRC bit is a read-only bit that indicates if the CRC value is all zeros or not
1: CRC value is not all zeros
0: CRC value is all zeros
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Zero in CRC (Bit 9)
The Zero in CRC bit is a read-only bit that indicates if the CRC value is all ones or not
1: CRC value is not all ones
0: CRC value is all ones
Reserved
All reserved bits should be written as ‘0’.
7.12.7
SPI CRC Value Register [0xC0D4] [R/W]
Bit #
15
14
13
12
11
10
9
8
Read/Write
R/W
R/W
R/W
R/W
Default
1
1
R/W
R/W
R/W
R/W
1
1
1
1
1
1
Bit #
7
6
5
4
3
2
1
0
Read/Write
R/W
R/W
R/W
R/W
Default
R/W
R/W
R/W
R/W
1
1
1
1
1
1
1
1
Field
CRC...
Field
...CRC
Figure 7-78. SPI CRC Value Register
Register Description
The SPI CRC Value Register contains the CRC value.
CRC (Bits [15:0])
The CRC field contains the SPI CRC. In CRC Mode CRC7, the CRC value will be a seven bit value [6:0]. Therefore bits [15:7]
are invalid in CRC7 mode.
7.12.8
SPI Data Register [0xC0D6] [R/W]
Bit #
15
14
13
12
Field
11
10
9
8
Reserved
Read/Write
-
-
-
-
-
-
-
-
Default
X
X
X
X
X
X
X
X
Bit #
7
6
5
4
3
2
1
0
Field
Data
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Default
X
X
X
X
X
X
X
X
Figure 7-79. SPI Data Register
Register Description
The SPI Data Register contains data received on the SPI port when read. Reading it empties the eight byte receive FIFO in PIO
byte mode. This receive data is valid when the receive bit of the SPI Interrupt Value is set to ‘1’ (RxIntVal triggers) or the Receive
Data Ready bit of the SPI Control Register is set to ‘1’. Writing to this register in PIO byte mode will initiate a transfer of data, the
number of bits defined by Transmit Bit Length field in the SPI Control Register.
Data (Bits [7:0])
The Data field contains data received or to be transmitted on the SPI port.
Reserved
All reserved bits should be written as ‘0’.
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7.12.9
CY7C67300
SPI Transmit Address Register [0xC0D8] [R/W]
Bit #
15
14
13
12
11
10
9
8
Read/Write
R/W
R/W
R/W
R/W
Default
0
0
R/W
R/W
R/W
R/W
0
0
0
0
0
0
Bit #
7
6
5
4
3
2
1
0
Read/Write
R/W
R/W
R/W
R/W
Default
R/W
R/W
R/W
R/W
0
0
0
0
0
0
0
0
9
8
Field
Address...
Field
...Address
Figure 7-80. SPI Transmit Address Register
Register Description
The SPI Transmit Address Register is used as the base address for the SPI transmit DMA.
Address (Bits [15:0])
The Address field sets the base address for the SPI transmit DMA.
7.12.10 SPI Transmit Count Register [0xC0DA] [R/W]
Bit #
15
14
Read/Write
12
11
10
-
-
-
-
-
R/W
Default
0
R/W
R/W
0
0
0
0
0
0
0
Bit #
7
6
5
4
3
2
1
0
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Default
0
0
0
0
0
0
0
0
Field
13
Reserved
Count...
Field
...Count
Figure 7-81. SPI Transmit Count Register
Register Description
The SPI Transmit Count Register designates the block byte length for the SPI transmit DMA transfer.
Count (Bits [10:0])
The Count field sets the count for the SPI transmit DMA transfer.
Reserved
All reserved bits should be written as ‘0’.
7.12.11 SPI Receive Address Register [0xC0DC [R/W]
Bit #
15
14
13
12
11
10
9
8
Read/Write
R/W
R/W
R/W
R/W
Default
0
0
R/W
R/W
R/W
R/W
0
0
0
0
0
0
Bit #
7
6
5
4
3
2
1
0
Read/Write
R/W
R/W
R/W
R/W
Default
R/W
R/W
R/W
R/W
0
0
0
0
0
0
0
0
Field
Address...
Field
...Address
Figure 7-82. SPI Receive Address Register
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Register Description
The SPI Receive Address Register is issued as the base address for the SPI Receive DMA.
Address (Bits [15:0])
The Address field sets the base address for the SPI receive DMA.
7.12.12 SPI Receive Count Register [0xC0DE] [R/W]
Bit #
15
14
Read/Write
-
-
Default
0
Bit #
13
12
11
10
-
-
-
R/W
R/W
R/W
0
0
0
0
0
0
0
7
6
5
4
3
2
1
0
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Default
0
0
0
0
0
0
0
0
Field
Reserved
9
8
Count...
Field
...Count
Figure 7-83. SPI Receive Count Register
Register Description
The SPI Receive Count Register designates the block byte length for the SPI receive DMA transfer.
Count (Bits [10:0])
The Count field sets the count for the SPI receive DMA transfer.
Reserved
All reserved bits should be written as ‘0’.
7.13
UART Registers
There are three registers dedicated to UART operation. Each of these registers is covered in this section and summarized in
Figure 7-84.
Register Name
Address
UART Control Register
UART Status Register
UART Data Register
0xC0E0
0xC0E2
0xC0E4
R/W
R/W
R
R/W
Figure 7-84. UART Registers
7.13.1
UART Control Register [0xC0E0] [R/W]
Bit #
15
14
13
12
Read/Write
-
-
-
-
-
-
-
-
Default
0
0
0
0
0
0
0
0
Bit #
7
6
5
4
3
2
1
0
Field
11
10
9
8
Reserved...
Field
...Reserved
Scale Select
Baud Select
UART Enable
Read/Write
-
-
-
R/W
R/W
R/W
R/W
R/W
Default
0
0
0
0
0
1
1
1
Figure 7-85. UART Control Register
Register Description
The UART Control Register enables or disables the UART allowing GPIO28 (UART_TXD) and GPIO27 (UART_RXD) to be freed
up for general use. This register must also be written to set the baud rate which is based on a 48-MHz clock.
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Scale Select (Bit 4)
The Scale Select bit acts as a prescaler that will divide the baud rate by eight.
1: Enable prescaler
0: Disable prescaler
Baud Select (Bits [3:1])
Please refer to Table 7-15 for a definition of this field.
Table 7-15. UART Baud Select Definition
Baud Select [3:1]
Baud Rate w/ DIV8 = 0
Baud Rate w/ DIV8 = 1
000
115.2 KBaud
14.4 KBaud
001
57.6 KBaud
7.2 KBaud
010
38.4 KBaud
4.8 KBaud
011
28.8 KBaud
3.6 KBaud
100
19.2 KBaud
2.4 KBaud
101
14.4 KBaud
1.8 KBaud
110
9.6 KBaud
1.2 KBaud
111
7.2 KBaud
0.9 KBaud
UART Enable (Bit 0)
The UART Enable bit enables or disables the UART.
1: Enable UART
0: Disable UART. This allows GPIO28 and GPIO27 to be used for general use.
Reserved
All reserved bits should bit written as ‘0’.
7.13.2
UART Status Register [0xC0E2] [R]
Bit #
15
14
13
12
Field
11
10
9
8
Reserved...
Read/Write
-
-
-
-
-
-
-
-
Default
0
0
0
0
0
0
0
0
Bit #
7
6
5
Field
4
3
2
...Reserved
1
0
Receive Full
Transmit Empty
Read/Write
-
-
-
-
-
-
R
R
Default
0
0
0
0
0
0
0
1
Figure 7-86. UART Status Register
Register Description
The UART Status Register is a read-only register that indicates the status of the UART buffer.
Receive Full (Bit 1)
The Receive Full bit indicates whether the receive buffer is full. It can be programmed to interrupt the CPU as interrupt #5 when
the buffer is full. This can be done though the UART bit of the Interrupt Enable Register (0xC00E). This bit will automatically get
cleared when data is read from the UART Data Register.
1: Receive buffer full
0: Receive buffer empty
Transmit Empty (Bit 0)
The Transmit Empty bit indicates whether the transmit buffer is empty or not. It can be programmed to interrupt the CPU as
interrupt #4 when the buffer is empty. This can be done though the UART bit of the Interrupt Enable Register (0xC00E). This bit
will automatically be set to ‘1’ after data is transmitted.
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1: Transmit buffer empty and ready for a new byte of data
0: Transmit buffer is not empty (transmit busy)
7.13.3
UART Data Register [0xC0E4] [R/W]
Bit #
15
14
13
12
Read/Write
-
-
-
-
-
-
-
-
Default
0
0
0
0
0
0
0
0
Bit #
7
6
5
4
3
2
1
0
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Default
0
0
0
0
0
0
0
0
Field
11
10
9
8
Reserved
Field
Data
Figure 7-87. UART Data Register
Register Description
The UART Data Register contains data to be transmitted or received from the UART port. Data written to this register will start a
data transmission and also causes the UART Transmit Empty Flag of the UART Status Register to set. When data received on
the UART port is read from this register, the UART Receive Full Flag of the UART Status Register will get cleared.
Data (Bits [7:0])
The Data field is where the UART data to be transmitted or received is located
Reserved
All reserved bits should be written as ‘0’.
7.14
PWM Registers
There are eleven registers dedicated to PWM operation. Each of these registers are covered in this section and summarized in
Figure 7-88.
Register Name
PWM Control Register
PWM Maximum Count Register
PWM0 Start Register
PWM0 Stop Register
PWM1 Start Register
PWM1 Stop Register
PWM2 Start Register
PWM2 Stop Register
PWM3 Start Register
PWM3 Stop Register
PWM Cycle Count Register
Address
0xC0E6
0xC0E8
0xC0EA
0xC0EC
0xC0EE
0xC0F0
0xC0F2
0xC0F4
0xC0F6
0xC0F8
0xC0FA
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Figure 7-88. PWM Registers
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PRELIMINARY
7.14.1
CY7C67300
PWM Control Register [0xC0E6] [R/W]
Bit #
15
14
13
12
11
Field
PWM
Enable
Read/Write
R/W
-
-
-
R/W
R/W
R/W
R/W
Default
0
0
0
0
0
0
0
0
Bit #
7
6
5
4
3
2
1
0
Field
PWM 3
Polarity
Select
PWM 2
Polarity
Select
PWM 1
Polarity
Select
PWM 0
Polarity
Select
PWM 3
Enable
PWM 2
Enable
PWM 1
Enable
PWM 0
Enable
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Default
0
0
0
0
0
0
0
0
Reserved
10
9
8
Prescale
Select
Mode
Select
Figure 7-89. PWM Control Register
Register Description
The PWM Control Register provides high-level control over all four of the PWM channels.
PWM Enable (Bit 15)
The PWM Enable bit starts and stops PWM operation.
1: Start operation
0: Stop operation
Prescale Select (Bits [11:9])
The Prescale Select field sets the frequency of all the PWM channels as defined in Table 7-16.
Table 7-16. Prescaler Select Definition
Prescale Select [11:9]
Frequency
000
48.00 MHz
001
24.00 MHz
010
06.00 MHz
011
01.50 MHz
100
375 kHz
101
93.80 kHz
110
23.40 kHz
111
05.90 kHz
Mode Select (Bit 8)
The Mode Select bit selects between continuous PWM cycling and one shot mode. The default is continuous repeat.
1: Enable One Shot mode. The mode runs the number of counter cycles set in the PWM Cycle Count Register and then stops.
0: Enable Continuous mode. Runs in continuous mode and starts over once the PWM cycle count is reached.
PWM 3 Polarity Select (Bit 7)
The PWM 3 Polarity Select bit selects the polarity for PWM 3.
1: Sets the polarity to active HIGH or rising edge pulse
0: Sets the polarity to active LOW
PWM 2 Polarity Select (Bit 6)
The PWM 2 Polarity Select bit selects the polarity for PWM 2.
1: Sets the polarity to active HIGH or rising edge pulse
0: Sets the polarity to active LOW
PWM 1 Polarity Select (Bit 5)
Document #: 38-08015 Rev. *D
Page 97 of 120
PRELIMINARY
CY7C67300
The PWM 1 Polarity Select bit selects the polarity for PWM 1.
1: Sets the polarity to active HIGH or rising edge pulse
0: Sets the polarity to active LOW
PWM 0 Polarity Select (Bit 4)
The PWM 0 Polarity Select bit selects the polarity for PWM 0.
1: Sets the polarity to active HIGH or rising edge pulse
0: Sets the polarity to active LOW
PWM 3 Enable (Bit 3)
The PWM 3 Enable bit enables or disables PWM 3.
1: Enable PWM 3
0: Disable PWM 3
PWM 2 Enable (Bit 2)
The PWM 2 Enable bit enables or disables PWM 2.
1: Enable PWM 2
0: Disable PWM 2
PWM 1 Enable (Bit 1)
The PWM 1 Enable bit enables or disables PWM 1.
1: Enable PWM 1
0: Disable PWM 1
PWM 0 Enable (Bit 0)
The PWM 0 Enable bit enables or disables PWM 0.
1: Enable PWM 0
0: Disable PWM 0
7.14.2
PWM Maximum Count Register [0xC0E8] [R/W]
Bit #
15
14
13
Field
12
11
10
9
Reserved
8
Count...
Read/Write
-
-
-
-
-
-
R/W
R/W
Default
0
0
0
0
0
0
0
0
Bit #
7
6
5
4
3
2
1
0
Field
...Count
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Default
0
0
0
0
0
0
0
0
Figure 7-90. PWM Maximum Count Register
Register Description
The PWM Maximum Count Register designates the maximum window for each pulse cycle. Each count tick is based on the clock
frequency set in the PWM Control Register.
Count (Bits [9:0])
The Count field sets the maximum cycle time.
Reserved
All reserved bits should be written as ‘0’.
7.14.3 PWM n Start Register [R/W]
• PWM 0 Start Register 0xC0EA
• PWM 1 Start Register 0xC0EE
Document #: 38-08015 Rev. *D
Page 98 of 120
PRELIMINARY
CY7C67300
• PWM 2 Start Register 0xC0F2
• PWM 3 Start Register 0xC0F6
Bit #
15
14
13
Field
12
11
10
9
Reserved
8
Address...
Read/Write
-
-
-
-
-
-
R/W
R/W
Default
0
0
0
0
0
0
0
0
Bit #
7
6
5
4
3
2
1
0
Field
...Address
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Default
0
0
0
0
0
0
0
0
Figure 7-91. PWM n Start Register
Register Description
The PWM n Start Register designates where in the window defined by the PWM Maximum Count Register to start the PWM pulse
for a given channel.
Address (Bits [9:0])
The Address field designates when to start the PWM pulse. If this start value is equal to the Stop Count Value then the output
stays at false.
Reserved
All reserved bits should be written as ‘0’.
7.14.4 PWM n Stop Register [R/W]
• PWM 0 Stop Register 0xC0EC
• PWM 1 Stop Register 0xC0F0
• PWM 2 Stop Register 0xC0F4
• PWM 3 Stop Register 0xC0F8
Bit #
15
14
13
Field
12
11
10
9
Reserved
8
Address...
Read/Write
-
-
-
-
-
-
R/W
R/W
Default
0
0
0
0
0
0
0
0
Bit #
7
6
5
4
3
2
1
0
Field
...Address
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Default
0
0
0
0
0
0
0
0
Figure 7-92. PWM n Stop Register
Register Description
The PWM n Stop Register designates where in the window defined by the PWM Maximum Count Register to stop the PWM pulse
for a given channel.
Address (Bits [9:0])
The Address field designates when to stop the PWM pulse. If the PWM Start value is equal to the PWM Stop value then the output
stays at ‘0’. If the PWM Stop value is greater then the PWM Maximum Count value then the output stays at true.
Reserved
All reserved bits should bit written as ‘0’.
Document #: 38-08015 Rev. *D
Page 99 of 120
PRELIMINARY
7.14.5
CY7C67300
PWM Cycle Count Register [0xC0FA] [R/W]
Bit #
15
14
13
12
11
10
9
8
Read/Write
R/W
R/W
R/W
R/W
Default
0
0
R/W
R/W
R/W
R/W
0
0
0
0
0
0
Bit #
7
6
5
4
3
2
1
0
Read/Write
R/W
R/W
R/W
R/W
Default
R/W
R/W
R/W
R/W
0
0
0
0
0
0
0
0
Field
Count...
Field
...Count
Figure 7-93. PWM Cycle Count Register
Register Description
The PWM Cycle Count Register designates the number of cycles to run when in one shot mode. One shot mode is enabled by
setting the Mode Select bit of the PWM Control Register to ‘1’.
Count (Bits [9:0])
The Count field designates the number of cycles (plus one) to run when in one shot mode. For example, Cycles = PWM Cycle
Count + 1, therefore for 2 cycles set PWM Cycle Count = 1.
Document #: 38-08015 Rev. *D
Page 100 of 120
PRELIMINARY
8.0
CY7C67300
Pin Diagram
D5
D7
D6
D4
D3
D2
D1
D0
Reserved
nRESET
GPIO7/D7
GPIO6/D6
VCC
GPIO5/D5
GPIO4/D4
GPIO3/D3
GPIO2/D2
GPIO1/D1
GPIO0/D0
A17
A18
A16
GND
nBEH
nBEL/A0
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76
A1
A2
1
75
2
74
A3
DM2B
3
73
4
72
D10/SCK
DP2B
AGND
5
71
6
70
A4
A5
7
69
D11/MOSI
D12/TXD
D13/RXD
8
68
D14/RTS
DM2A
9
67
D15/CTS
DP2A
OTGVBUS
10
66
GPIO8/D8/MISO
GPIO9/D9/nSSI
CY7C67300
11
65
GND
D8/MISO
D9/nSSI
63
nWR
VCC
14
62
nRD
15
61
16
60
GPIO10/D10/SCK
GPIO11/D11/MOSI
17
59
18
58
DP1B
19
57
GPIO14/D14
A7
20
56
AVCC
DM1A
DP1A
21
55
GPIO15/D15/nSSI
GPIO16/A0/TXD/PWM0
22
54
GPIO17/A1/RXD/PWM1
23
53
GPIO18/A2/RTS/PWM2
A8
A9
24
52
25
51
GPIO19/A0/CS0
GND
CSWITCHB
12
CSWITCHA
13
VSWITCH
BOOSTGND
BOOSTVCC
A6
DM1B
64
GPIO12/D12
GPIO13/D13
26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
GPIO20/A1/CS1
GPIO21/nCS
GPIO22/nWR/IOW
GPIO23/nRD/IOR
GPIO24/INT/IORDY/IRQ0
GPIO27/RX
GPIO25/IRQ1
GPIO26/CTS/PWM3
GPIO28/TX
GPIO29/OTGID
GPIO30/SDA
GPIO31/SCL
VCC
A15
nXRAMSEL
nXROMSEL
A14
nXMEMSEL
A13
A12
A11
XTALIN
XTALOUT
A10
GND
Figure 8-1. EZ-Host Pin Diagram
9.0
Pin Descriptions
Table 9-1. Pin Descriptions
Pin
67
Name
D15/CTS
Type
I/O
68
D14/RTS
I/O
69
D13/RXD
I/O
70
D12/TXD
I/O
71
D11/MOSI
I/O
Document #: 38-08015 Rev. *D
Description
D15: External Memory Data Bus
CTS: HSS CTS
D14: External Memory Data Bus
RTS: HSS RTS
D13: External Memory Data Bus
RXD: HSS RXD (Data is received on this pin)
D12: External Memory Data Bus
TXD: HSS TXD (Data is transmitted from this pin)
D11: External Memory Data Bus
MOSI: SPI MOSI
Page 101 of 120
PRELIMINARY
CY7C67300
Table 9-1. Pin Descriptions (continued)
Pin
72
Name
D10/SCK
Type
I/O
73
D9/nSSI
I/O
74
D8/MISO
I/O
76
77
78
79
80
81
82
83
33
32
31
30
27
25
24
20
17
8
7
3
2
1
99
D7
D6
D5
D4
D3
D2
D1
D0
A14
A13
A12
A11
A10
A9
A8
A7
A6
A5
A4
A3
A2
A1
nBEL/A0
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
98
64
62
97
95
96
34
35
36
38
39
nBEH
nWR
nRD
A16
A17
A18
nMEMSEL
nROMSEL
nRAMSEL
A15
GPIO31/SCK
Output
Output
Output
Output
Output
Output
Output
Output
Output
I/O
I/O
40
GPIO30/SDA
I/O
41
GPIO29/OTGID
I/O
42
GPIO28/TX
I/O
Document #: 38-08015 Rev. *D
Description
D10: External Memory Data Bus
SCK: SPI SCK
D9: External Memory Data Bus
nSSI: SPI nSSI
D8: External Memory Data Bus
MISO: SPI MISO
External Memory Data Bus
External Memory Address Bus
nBEL: Low Byte Enable for 16-bit Memories
A0: External Memory Address bit A0 for 0-8 bit memories
High Byte Enable for 16-bit memories
External Memory Write pulse
External Memory Read pulse
A16: External SRAM A16
A17: External SRAM A17
A18: External SRAM A18
External Memory Select 0
External Memory Select 1
External Memory Select 2
A15: External SRAM A15
GPIO31: General Purpose I/O
SCK: I2C EEPROM SCK
GPIO30: General Purpose I/O
SDA: I2C EEPROM SDA
GPIO29: General Purpose I/O
OTGID: Input for OTG ID pin. When used as OTGID, this pin should
be tied high through an external pull-up resistor. Assuming VCC=3.0V,
a 10K to 40K resistor should be used.
GPIO28: General Purpose I/O
TX: UART TX (Data is transmitted from this pin)
Page 102 of 120
PRELIMINARY
CY7C67300
Table 9-1. Pin Descriptions (continued)
Pin
43
Name
GPIO27/RX
Type
I/O
44
GPIO26/CTS/PWM3
I/O
45
GPIO25/IRQ1
I/O
46
GPIO24/INT/
IORDY/IRQ0
I/O
47
GPIO23/nRD/IOR
I/O
48
GPIO22/nWR/IOW
I/O
49
GPIO21/nCS
I/O
50
GPIO20/A1/CS1
I/O
52
GPIO19/A0/CS0
I/O
53
GPIO18/A2/RTS/
PWM2
I/O
54
GPIO17/A1/RXD/
PWM1
I/O
55
GPIO16/A0/TXD/
PWM0
I/O
56
GPIO15/D15/nSSI
I/O
57
GPIO14/D14
I/O
58
GPIO13/D13
I/O
59
GPIO12/D12
I/O
60
GPIO11/D11/MOSI
I/O
61
GPIO10/D10/SCK
I/O
Document #: 38-08015 Rev. *D
Description
GPIO27: General Purpose I/O
RX: UART RX (Data is received on this pin)
GPIO26: General Purpose I/O
CTS: HSS CTS
PWM3: PWM channel 3
GPIO25: General Purpose I/O
IRQ1: Interrupt Request 1. See Register 0xC006. This pin is also one
of two possible GPIO wakeup sources.
GPIO24: General Purpose I/O
INT: HPI INT
IORDY: IDE IORDY
IRQ0: Interrupt Request 0. See Register 0xC006. This pin is also one
of two possible GPIO wakeup sources.
GPIO23: General Purpose I/O
nRD: HPI nRD
IOR: IDE IOR
GPIO22: General Purpose I/O
nWR: HPI nWR
IOW: IDE IOW
GPIO21: General Purpose I/O
nCS: HPI nCS
GPIO20: General Purpose I/O
A1: HPI A1
CS1: IDE CS1
GPIO19: General Purpose I/O
A0: HPI A0
CS0: IDE CS0
GPIO18: General Purpose I/O
A2: IDE A2
RTS: HSS RTS
PWM2: PWM channel 2
GPIO17: General Purpose I/O
A1: IDE A1
RXD: HSS RXD (Data is received on this pin)
PWM1: PWM channel 1
GPIO16: General Purpose I/O
A0: IDE A0
TXD: HSS TXD (Data is transmitted from this pin)
PWM0: PWM channel 0
GPIO15: General Purpose I/O
D15: D15 for HPI or IDE
nSSI: SPI nSSI
GPIO14: General Purpose I/O
D14: D14 for HPI or IDE
GPIO13: General Purpose I/O
D13: D13 for HPI or IDE
GPIO12: General Purpose I/O
D12: D12 for HPI or IDE
GPIO11: General Purpose I/O
D11: D11 for HPI or IDE
MOSI: SPI MOSI
GPIO10: General Purpose I/O
D10: D10 for HPI or IDE
SCK: SPI SCK
Page 103 of 120
PRELIMINARY
CY7C67300
Table 9-1. Pin Descriptions (continued)
Pin
65
Name
GPIO9/D9/nSSI
Type
I/O
66
GPIO8/D8/MISO
I/O
86
GPIO7/D7
I/O
87
GPIO6/D6
I/O
89
GPIO5/D5
I/O
90
GPIO4/D4
I/O
91
GPIO3/D3
I/O
92
GPIO2/D2
I/O
93
GPIO1/D1
I/O
94
GPIO0/D0
I/O
22
23
18
19
9
10
4
5
29
28
85
84
16
14
DM1A
DP1A
DM1B
DP1B
DM2A
DP2A
DM2B
DP2B
XTALIN
XTALOUT
nRESET
Reserved
BOOSTVCC
VSWITCH
15
11
13
12
21
6
37, 63, 88
26, 51, 75,
100
BOOSTGND
OTGVBUS
CSWITCHA
CSWITCHB
AVCC
AGND
VCC
GND
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
Input
Output
Input
Power
Analog
Output
Ground
Analog I/O
Analog
Analog
Power
Ground
Power
Ground
Document #: 38-08015 Rev. *D
Description
GPIO9: General Purpose I/O
D9: D9 for HPI or IDE
nSSI: SPI nSSI
GPIO8: General Purpose I/O
D8: D8 for HPI or IDE
MISO: SPI MISO
GPIO7: General Purpose I/O
D7: D7 for HPI or IDE
GPIO6: General Purpose I/O
D6: D6 for HPI or IDE
GPIO5: General Purpose I/O
D5: D5 for HPI or IDE
GPIO4: General Purpose I/O
D4: D4 for HPI or IDE
GPIO3: General Purpose I/O
D3: D3 for HPI or IDE
GPIO2: General Purpose I/O
D2: D2 for HPI or IDE
GPIO1: General Purpose I/O
D1: D1 for HPI or IDE
GPIO0: General Purpose I/O
D0: D0 for HPI or IDE
USB Port 1A D–
USB Port 1A D+
USB Port 1B D–
USB Port 1B D+
USB Port 2A D–
USB Port 2A D+
USB Port 2B D–
USB Port 2B D+
Crystal input or Direct Clock input
Crystal output. Leave floating if direct clock source is used.
Reset
Tie to Gnd for normal operation.
Booster Power input: 2.7V to 3.6V
Booster switching output
Booster Ground
USB OTG Vbus
Charge Pump Capacitor
Charge Pump Capacitor
USB Power
USB Ground
Main VCC
Main Ground
Page 104 of 120
PRELIMINARY
10.0
CY7C67300
Absolute Maximum Ratings
This section lists the absolute maximum ratings. Stresses above those listed can cause permanent damage to the device.
Exposure to maximum rated conditions for extended periods can affect device operation and reliability.
Storage Temperature .................................................................................................................................... –40°C to +125°C
Ambient Temperature with Power Supplied .................................................................................................... –40°C to +85°C
Supply Voltage to Ground Potential ....................................................................................................................0.0V to +3.6V
DC Input Voltage to Any General Purpose Input Pin ....................................................................................................... 5.5V
DC Voltage Applied to XTALIN ............................................................................................................... –0.5V to VCC + 0.5V
Static Discharge Voltage ............................................................................................................................................ > 2000V
Max Output Current, per I/O ........................................................................................................................................... 4 mA
11.0
Operating Conditions
TA (Ambient Temperature Under Bias) ........................................................................................................... –40°C to +85°C
Supply Voltage (VCC, AVCC) .............................................................................................................................+3.0V to +3.6V
Supply Voltage (BoostVCC)[8] ............................................................................................................................+2.7V to +3.6V
Ground Voltage .................................................................................................................................................................... 0V
FOSC (Oscillator or Crystal Frequency) ...................................................................................................... 12 MHz ± 500 ppm
Parallel Resonant
12.0
Crystal Requirements (XTALIN, XTALOUT)
Table 12-1. Crystal Requirements
Crystal Requirements,
(XTALIN, XTALOUT)
Min.
Parallel Resonant Frequency
Typical
Max.
Unit
+500
PPM
12
Frequency Stability
-500
Load Capacitance
20
Driver Level
Start-up Time
MHz
33
pF
500
µW
5
ms
Mode of Vibration: Fundamental
Note:
8. The on-chip voltage booster circuit boosts BoostVCC to provide a nominal 3.3V VCC supply.
Document #: 38-08015 Rev. *D
Page 105 of 120
PRELIMINARY
13.0
CY7C67300
DC Characteristics
Table 13-1. DC Characteristics
Min.
Typ.
Max.
Unit
VCC, AVCC
Parameter
Supply Voltage
Description
Conditions
3.0
3.3
3.6
V
BoosVCC
Supply Voltage
2.7
3.6
V
VIH
Input HIGH Voltage
2.0
VIL
Input LOW Voltage
II
Input Leakage Current
0< VIN < VCC
-10.0
VOH
Output Voltage HIGH
IOUT = 4 mA
2.4
VOL
Output LOW Voltage
IOUT = –4 mA
IOH
5.5
V
0.8
V
+10.0
µA
0.4
V
Output Current HIGH
4
mA
IOL
Output Current LOW
4
mA
CIN
Input Pin Capacitance
Except D+/D–
10
pF
D+/D–
15
pF
V
VHYS
Hysteresis on nReset Pin
250
ICC
Supply Current
4 transceivers powered
80
100
mA
ICCB
Supply Current with Booster Enabled 4 transceivers powered
135
180
mA
ISLEEP
Sleep Current
210
500
µA
5
30
µA
190
500
µA
5
30
µA
Max.
Unit
5.25
V
USB Peripheral: includes 1.5K internal pull-up
Without 1.5K internal pull-up
ISLEEPB
Sleep Current with Booster Enabled USB Peripheral: includes 1.5K internal pull-up
Without 1.5K internal pull-up
mV
Table 13-2. DC Characteristics: Charge Pump
Parameter
Description
Conditions
VA_VBUS_OUT
Regulated OTGVBUS Voltage
8 mA< ILOAD < 10 mA
TA_VBUS_RISE
VBUS Rise Time
ILOAD = 10 mA
IA_VBUS_OUT
Maximum Load Current
CDRD_VBUS
OUTVBUS Bypass Capacitance
4.4V< VBUS < 5.25V
OTGVBUS not driven
Min.
Typ.
4.4
100
ms
8
10
mA
1.0
6.5
pF
200
mV
342
mV
20
mA
VA_VBUS_LKG
OTGVBUS Leakage Voltage
VDRD_DATA_LKG
Dataline Leakage Voltage
ICHARGE
Charge Pump Current Draw
ILOAD = 8 mA
ILOAD = 0 mA
0
1
mA
ICHARGEB
Charge Pump Current Draw with
Booster Active
ILOAD = 8 mA
30
45
mA
ILOAD = 0 mA
0
5
mA
IB_DSCHG_IN
B-Device (SRP Capable) Discharge Current
0V< VBUS < 5.25V
8
mA
VA_VBUS_VALID
A-Device VBUS Valid
4.4
VA_SESS_VALID
A-Device Session Valid
0.8
2.0
V
VB_SESS_VALID
B-Device Session Valid
0.8
4.0
V
VA_SESS_END
B-Device Session End
0.2
0.8
V
20
V
Notes:
9. All tests were conducted with Charge pump off.
10. ICC and ICCB values are the same regardless of USB host or peripheral configuration.
11. There is no appreciable difference in ICC and ICCB values when only two transceivers are powered.
Document #: 38-08015 Rev. *D
Page 106 of 120
PRELIMINARY
CY7C67300
Table 13-2. DC Characteristics: Charge Pump (continued)
Parameter
Description
E
Efficiency When Loaded
RPD
Data Line Pull-down
RA_BUS_IN
A-device VBUS Input Impedance
to GND
RB_SRP_UP
B-device VBUS SRP Pull-up
RB_SRP_DWN
B-device VBUS SRP Pull-down
13.1
Conditions
Min.
ILOAD = 8mA, VCC = 3.3V
Typ.
Max.
Unit
75
%
14.25
24.8
Ω
VBUS is not being driven
40
100
kΩ
Pull-up voltage = 3.0V
281
Ω
656
Ω
USB Transceiver
USB 2.0-certified in full- and low-speed modes.
14.0
AC Timing Characteristics
14.1
Reset Timing
tRESET
nRESET
tIOACT
nRD or nWRL or nWRH
Reset Timing
Parameter
Description
Min.
Typical
Max.
Unit
tRESET
nRESET pulse width
16
clocks[12]
tIOACT
nRESET HIGH to nRD or
nWRx active
200
µs
Note:
12. Clock is 12 MHz nominal.
Document #: 38-08015 Rev. *D
Page 107 of 120
PRELIMINARY
14.2
CY7C67300
Clock Timing
tCLK
tLOW
XTALIN
tFALL
tHIGH
tRISE
Clock Timing
Parameter
Description
fCLK
Clock frequency
vXINH
Clock input high
(XTALOUT left floating)
tCLK
Clock period
tHIGH
Clock high time
tLOW
Clock low time
tRISE
tFALL
Min.
Typical
Max.
12.0
Unit
MHz
1.5
3.0
3.6
V
83.17
83.33
83.5
ns
36
44
ns
36
44
ns
Clock rise time
5.0
ns
Clock fall time
5.0
ns
55
%
Duty Cycle
45
Note:
13. vXINH is required to be 3.0 V to obtain an internal 50/50 duty cycle clock.
Document #: 38-08015 Rev. *D
Page 108 of 120
PRELIMINARY
14.3
CY7C67300
SRAM Read Cycle
Address
CS
t AR
tCR
t RPW
RD
t CDH
t RDH
t AC
Din
Data Valid
Parameter
Description
Min.
Typical
Max.
Unit
tCR
CS LOW to RD LOW
1
ns
tRDH
RD HIGH to data hold
0
ns
CS HIGH to data hold
0
ns
RD LOW time
38
tCDH
tRPW
[14]
tAR
tAC
[15]
45
ns
RD LOW to address valid
0
ns
RAM access to data valid
12
ns
Notes:
14. 0 wait state cycle.
15. tAC External SRAM access time = 12 ns for zero and one wait states. The External SRAM access time = 12 ns + (n – 1)*T for wait states = n, n > 1, T = 48-MHz
clock period.
Document #: 38-08015 Rev. *D
Page 109 of 120
PRELIMINARY
14.4
CY7C67300
SRAM Write Cycle
Address
t AW
tCSW
CS
tWC
t WPW
WE
t DW
Dout
Parameter
t DH
Data Valid
Description
Min.
Typical
Max.
Unit
tAW
Write address valid to WE LOW
7
ns
tCSW
CS LOW to WE LOW
7
ns
tDW
Data valid to WE HIGH
15
ns
tWPW[16]
WE pulse width
15
ns
tDH
Data hold from WE HIGH
4.5
ns
tWC
WE HIGH to CS HIGH
13
ns
Note:
16. tWPW The write pulse width = 18.8 ns min. for zero and one wait states. The write pulse = 18.8 ns + (n – 1)*T for wait states = n, n > 1, T = 48-MHz clock period.
Document #: 38-08015 Rev. *D
Page 110 of 120
PRELIMINARY
14.5
CY7C67300
I2C EEPROM Timing
1. I2C EEPROM Bus Timing - Serial I/O
tHIGH
tLOW
tR
tF
SCL
tSU.STA
tSU.DAT
tHD.DAT
tHD.STA
tSU.STO
tBUF
SDA IN
tAA
tDH
SDA OUT
Parameter
Description
Min.
Typical
Max.
Unit
400
kHz
fSCL
Clock Frequency
tLOW
Clock Pulse Width Low
1300
ns
tHIGH
Clock Pulse Width High
600
ns
tAA
Clock Low to Data Out Valid
900
ns
tBUF
Bus Idle Before New Transmission
1300
ns
tHD.STA
Start Hold Time
600
ns
tSU.STA
Start Set-up Time
600
ns
tHD.DAT
Data In Hold Time
0
ns
tSU.DAT
Data In Set-up Time
100
ns
tR
Input Rise Time
300
ns
tF
Input Fall Time
300
ns
tSU.STO
Stop Set-up Time
tDH
Data Out Hold Time
Document #: 38-08015 Rev. *D
600
ns
0
ns
Page 111 of 120
PRELIMINARY
14.6
CY7C67300
HPI (Host Port Interface) Write Cycle Timing
tCYC
tASU
tWP
tAH
ADDR [1:0]
tCSH
tCSSU
nCS
nWR
nRD
Dout [15:0]
tDSU
Parameter
Description
Min.
–1
tWDH
Typical
Max.
Unit
tASU
Address set-up
ns
tAH
Address hold
–1
ns
tCSSU
Chip select set-up
–1
ns
tCSH
Chip select hold
–1
ns
tDSU
Data set-up
6
ns
tWDH
Write data hold
2
ns
tWP
Write pulse width
2
T[17]
tCYC
Write cycle time
6
T[17]
Note:
17. T = system clock period = 1/48 MHz.
Document #: 38-08015 Rev. *D
Page 112 of 120
PRELIMINARY
14.7
CY7C67300
HPI (Host Port Interface) Read Cycle Timing
tCYC
tASU
tWP
tAH
ADDR [1:0]
tCSH
tCSSU
nCS
tRDH
nWR
nRD
Din [15:0]
tACC
Parameter
Description
tRDH
Min.
Typical
Max.
Unit
tASU
Address set-up
–1
ns
tAH
Address hold
–1
ns
tCSSU
Chip select set-up
–1
ns
tCSH
Chip select hold
–1
ns
tACC
Data access time, from HPI_nRD falling
tRDH
Read data hold, relative to the earlier of
HPI_nRD rising or HPI_nCS rising
0
tRP
Read pulse width
2
T[17]
tCYC
Write cycle time
6
T[17]
Document #: 38-08015 Rev. *D
1
T[17]
7
ns
Page 113 of 120
PRELIMINARY
14.8
CY7C67300
IDE Timing
The IDE interface supports PIO mode 0-4 as specified in the Information Technology-AT Attachment–4 with Packet Interface
Extension (ATA/ATAPI-4) Specification, T13/1153D Rev 18.
14.9
HSS BYTE Mode Transmit
qt_clk
CPU may start another BYTE
transmit right after TxRdy
goes high
CPU_A[2:0]
CPUHSS_cs
CPU_wr
BT
BT
TxRdy flag
HSS_TxD
start bit
Byte transmit
triggered by a
CPU write to the
HSS_TxData register
bit 0
bit 1
bit 2
bit 3
bit 4
bit 5
bit 6
bit 7
start of last data bit to TxRdy high:
0 min, 4 T max.
(T is qt_clk period)
TxRdy low to start bit delay:
0 min, BT max when starting from IDEL.
For back to back transmit, new START Bit
begins immediately following previous STOP bit.
(BT = bit period)
stop bit
start bit
programmable
1 or 2 stop bits.
1 stop bit shown.
qt_clk, CPU_A, CPUHSS_cs, CPU_wr are internal signals, included in the diagram to illustrate relationship between CPU operations and HSS port operations.
Bit 0 is LSB of data byte. Data bits are HIGH true: HSS_TxD HIGH = data bit value ‘1’.
BT = bit time = 1/baud rate.
14.10
HSS Block Mode Transmit
BT
HSS_TxD
t
GAP
BLOCK mode transmit timing is similar to BYTE mode, except the STOP bit time is controlled by the HSS_GAP value.
The BLOCK mode STOP bit time, tGAP = (HSS_GAP – 9) BT, where BT is the bit time, and HSS_GAP is the content of the HSS
Transmit Gap Register 90xC074].
The default tGAP is 2 BT.
BT = bit time = 1/baud rate.
14.11
HSS BYTE and BLOCK Mode Receive
BT +/- 5%
received byte added to
receive FIFO during the final data bit time
BT +/- 5%
HSS_RxD
start bit
bit 0
bit 1
bit 2
bit 3
bit 4
bit 5
bit 6
bit 7
stop bit
start bit
10 BT +/- 5%
Receive data arrives asynchronously relative to the internal clock. Incoming data bit rate may deviate from the programmed baud
rate clock by as much as ±5% (with HSS_RATE value of 23 or higher).
BYTE mode received bytes are buffered in a FIFO. The FIFO not empty condition becomes the RxRdy flag.
BLOCK mode received bytes are written directly to the memory system.
Bit 0 is LSB of data byte. Data bits are HIGH true: HSS_RxD HIGH = data bit value ‘1’.
BT = bit time = 1/baud rate.
Document #: 38-08015 Rev. *D
Page 114 of 120
PRELIMINARY
14.12
CY7C67300
Hardware CTS/RTS Handshake
tCTShold
tCTShold
tCTSsetup
tCTSsetup
HSS_RTS
HSS_CTS
HSS_TxD
Start of transmission not delayed by HSS_CTS
Start of transmission delayed until HSS_CTS goes high
tCTSsetup: HSS_CTS set-up time before HSS_RTS = 1.5T min.
tCTShold: HSS_CTS hold time after START bit = 0 ns min.
T = 1/48 MHz.
When RTS/CTS hardware handshake is enabled, transmission can be help off by deasserting HSS_CTS at least 1.5T before
HSS_RTS. Transmission resumes when HSS_CTS returns HIGH. HSS_CTS must remain HIGH until START bit.
HSS_RTS is deasserted in the third data bit time.
An application may choose to hold HSS_CTS until HSS_RTS is deasserted, which always occurs after the START bit.
15.0
Registers Summary
Table 15-1. Register Summary
R/W
R
Address Register
0x0140
HPI Breakpoint
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
Default High
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Default Low
Address...
0000 0000
...Address
R
0x0142
Interrupt Routing
W
1: 0x0144 SIEXmsg
2: 0x0148
R/W
0x02n0
Device n Endpoint n Control
0000 0000
VBUS to HPI
Enable
ID to HPI
Enable
SOF/EOP2 to SOF/EOP2 to SOF/EOP1 to SOF/EOP1 to Reset2 to HPI HPI Swap 1
HPI Enable
CPU Enable HPI Enable CPU Enable Enable
Enable
Resume2 to
HPI Enable
Resume1 to
HPI Enable
Reserved
0x02n2
Device n Endpoint n Address
xxxx xxxx
...Data
xxxx xxxx
Reserved
xxxx xxxx
Stall
Enable
ISO
Enable
NAK Interrupt Direction
Enable
Select
Enable
ARM
Enable
Address...
R.W
0x02n4
Device n Endpoint n Count
Reserved
R/W
0x02n6
Device n Endpoint n Status
Reserved
xxxx xxxx
Count...
xxxx xxxx
...Count
Stall
Flag
R
0x02n8
0xC000
xxxx xxxx
NAK
Flag
Length
Setup
Exception Flag Flag
0xC002
0xC004
Underflow
Flag
OUT
IN
xxxx xxxx
Exception Flag Exception Flag
Sequence
Status
Timeout
Flag
Error
Flag
ACK
Flag
xxxx xxxx
xxxx xxxx
...Result
xxxx xxxx
CPU Flags
Reserved...
0000 0000
Bank
Global Interrupt Enable
Hardware Revision
Negative
Flag
Overflow
Flag
Carry
Flag
Zero
Flag
000x xxxx
Address...
0000 0001
...Address
R
Overflow
Flag
Device n Endpoint n Count Result Result...
...Reserved
R/W
Reserved
000x xxxx
Revision...
xxxx xxxx
...Revision
R/W
R/W
0xC006
0xC008
GPIO Control
CPU Speed
xxxx xxxx
Write Protect
Enable
UD
Reserved
HSS
Enable
HSS XD
Enable
SPI
Enable
SPI XD
Enable
0xC00A
Power Control
0xC00C
Watchdog Timer
Host/Device
2B Wake
Enable
Interrupt 1
Polarity
Select
Interrupt 1
Enable
0000 0000
Interrupt 0
Polarity
Select
Interrupt 0
Enable
0000 0000
0000 0000
Host/Device
2A Wake
Enable
Host/Device
1B Wake
Enable
Host/Device
1A Wake
Enable
OTG
Wake
Enable
0000 1111
Reserved
HSS
Wake
Enable
SPI
Wake
Enable
0000 0000
GPI
Reserved
Wake Enable
Boost 3V
OK
Sleep
Enable
Halt
Enable
0000 0000
Period
Select
Lock
Enable
WDT
Enable
Reset
Strobe
0000 0000
Reserved...
...Reserved
Document #: 38-08015 Rev. *D
Mode
Select
CPU Speed
HPI
Reserved
Wake Enable
R/W
SAS
Enable
Reserved...
.Reserved
R/W
xxxx xxxx
xxxx xxxx
...Address
R/W
0000 0000
Data...
IN/OUT
Sequence
Ignore Enable Select
R/W
Done2 to HPI Done1 to HPI Reset1 to HPI HPI Swap 0
Enable
Enable
Enable
Enable
0001 0100
0000 0000
Timeout
Flag
Page 115 of 120
PRELIMINARY
CY7C67300
Table 15-1. Register Summary (continued)
R/W
R/W
Address Register
0xC00E
Interrupt Enable
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
Default High
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Default Low
Reserved
HSS
Interrupt
Enable
R/W
0xC098
OTG Control
Reserved
D+ Pulldown
Enable
R/W
In Mailbox
Interrupt
Enable
D- Pulldown
Enable
OTG Interrupt SPI Interrupt Reserved
Enable
Enable
Host/Device 2 Host/Device 1 0000 0000
Interrupt
Interrupt
Enable
Enable
Out Mailbox
Interrupt
Enable
Reserved
UART
Interrupt
Enable
Timer 1
Interrupt
Enable
Timer 0
Interrupt
Enable
0001 0000
VBUS
Pullup
Enable
Receive
Disable
Charge Pump VBUS
Enable
Discharge
Enable
D+
Pullup
Enable
DPullup
Enable
0000 0000
ID
Status
VBUS Valid
Flag
0000 0xxx
Reserved
GPIO
Interrupt
Enable
OTG Data
Status
0: 0xC010 Timer n
1: 0xC012
Count...
1111 1111
...Count
1111 1111
0xC014
Address...
0000 0000
...Address
0000 0000
1: 0xC018 Extended Page n Map
2: 0xC01A
Address...
0000 0000
...Address
0000 0000
R/W
0: 0xC01E GPIO n Output Data
1: 0xC024
Data...
0000 0000
...Data
0000 0000
R
0: 0xC020 GPIO n Input Data
1: 0xC026
Data...
0000 0000
...Data
0000 0000
R/W
0: 0xC022 GPIO n Direction
1: 0xC028
Direction Select...
0000 0000
R/W
0xC03A
External Memory Control
Reserved
R/W
0xC03C
USB Diagnostic
R/W
R/W
W
0xC03E
Breakpoint
Memory Diagnostic
...Direction Select
0000 0000
XRAM
XROM
XMEM
XMEM
Merge Enable Merge Enable Width Select Wait Select
xxxx xxxx
XROM
Width Select
XROM
Wait Select
XRAM
XRAM
Width Select Wait Select
xxxx xxxx
Port 2B
Diagnostic
Enable
Port 2A
Diagnostic
Enable
Port 1B
Diagnostic
Enable
Port 1A
Diagnostic
Enable
Reserved...
0000 0000
...Reserved
Pulldown
Enable
LS Pullup
Enable
FS Pullup
Enable
Reserved
Reserved
Force Select
0000 0000
Memory
Arbitration
Select
0000 0000
Reserved
R/W
0xC048
IDE Mode
Monitor
Enable
Reserved...
0000 0000
0000 0000
...Reserved
Reserved
Mode Select
0000 0000
R/W
0xC04A
IDE Start Address
Address...
0000 0000
... Address
0000 0000
R/W
0xC04C
IDE Stop Address
Address...
0000 0000
...Address
0000 0000
R/W
0xC04E
IDE Control
Reserved...
0000 0000
...Reserved
-
0xC0500xC06E
IDE PIO Port
R/W
0xC070
HSS Control
R/W
R/W
R/W
R/W
0xC072
0xC074
0xC076
0xC078
HSS Baud Rate
HSS Transmit Gap
HSS Data
HSS Receive Address
Direction
Select
IDE Interrupt
Enable
Done
Flag
IDE
Enable
0000 0000
XOFF
XOFF
Enable
CTS
Enable
Receive
Interrupt
Enable
Done
Interrupt
Enable
0000 0000
Transmit Done Receive Done One
Interrupt Flag Interrupt Flag Stop Bit
Transmit
Ready
Packet Mode Receive
Receive Pack- Receive
Select
Overflow Flag et Ready Flag Ready Flag
Reserved
HSS Baud...
HSS
Enable
RTS
Polarity
Select
CTS
Polarity
Select
0000 0000
...Baud
0001 0111
Reserved
0000 0000
Transmit Gap Select
0000 1001
Reserved
xxxx xxxx
Data
xxxx xxxx
Address...
0000 0000
...Address
R/W
R/W
0xC07A
0xC07C
HSS Receive Counter
HSS Transmit Address
0000 0000
Reserved
Counter...
0000 0000
...Counter
0000 0000
Address..
0000 0000
...Address
R/W
0xC07E
HSS Transmit Counter
0000 0000
Reserved
Counter...
0000 0000
...Counter
R/W
R/W
0xC080
0xC0A0
Host n Control
0xC082
0xC0A2
Host n Address
0000 0000
Reserved
Preamble
Enable
Document #: 38-08015 Rev. *D
0000 0000
0000 0000
Sequence
Select
Sync
Enable
ISO
Enable
Reserved
Arm
Enable
0000 0000
Address...
0000 0000
...Address
0000 0000
Page 116 of 120
PRELIMINARY
CY7C67300
Table 15-1. Register Summary (continued)
R/W
R/W
R/W
R
Address Register
0xC084
0xC0A4
Host n Count
0xC084
0xC0A4
Device n Port Select
0xC086
0xC0A6
Host n PID
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
Default High
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Default Low
Reserved
Port Select
Reserved
0000 0000
...Count
Reserved
0000 0000
Port Select
Reserved...
0000 0000
...Reserved
0000 0000
Reserved
Stall
Flag
W
Count...
NAK
Flag
Length
Reserved
Exception Flag
Overflow
Flag
Underflow
Flag
Reserved
Sequence
Status
Timeout
Flag
Error
Flag
0000 0000
ACK
Flag
0000 0000
0xC086
0xC0A4
Host n EP Status
R
0xC088
0xC0A8
Host n Count Result
...Result
0000 0000
W
0xC088
0xC0A8
Host n Device Address
Reserved...
0000 0000
...Reserved
Address
R/W
0xC08A
0xC0AA
USB n Control
Port B
D+ Status
Port B
D- Status
Port A
Resistors
Enable
Port B
Force D+/State
VBUS
Interrupt
Enable
ID
Interrupt
Enable
R/W
0xC08C
Reserved
0000 0000
PID Select
Host 1 Interrupt Enable
Endpoint Select
0000 0000
0000 0000
Port A
D+ Status
R/W
R/W
0xC08C
Device 1 Interrupt Enable
0xC08E
0xC0AE
Device n Address
0xC090
Host 1 Status
Port A
D- Status
LOB
Port A
Force D+/State
VBUS
Interrupt
Enable
ID
Interrupt
Enable
Reserved
EP7
Interrupt
Enable
EP6
Interrupt
Enable
EP5
Interrupt
Enable
Port A Connect Change
Interrupt
Enable
0xC090
Port B Resistors Enable
xxxx 0000
Suspend
Enable
Port B
SOF/EOP
Enable
Port A
SOF/EOP
Enable
0000 0000
SOF/EOP
Interrupt
Enable
Reserved
0000 0000
Done
Interrupt
Enable
0000 0000
EP4
Interrupt
Enable
SOF/EOP
Timeout
Interrupt
Enable
Reserved
SOF/EOP
Interrupt
Enable
Reset
Interrupt
Enable
0000 0000
EP3
Interrupt
Enable
EP2
Interrupt
Enable
EP1
Interrupt
Enable
EP0
Interrupt
Enable
0000 0000
Reserved...
...Reserved
Device 1 Status
Mode
Select
Reserved
0000 0000
Address
0000 0000
VBUS
ID
Reserved
Interrupt Flag Interrupt Flag
Port B
Port A
Port B Connect Port A ConPort B
Wake Interrupt Wake Interrupt Change
nect Change SE0
Flag
Flag
Interrupt Flag Interrupt Flag Status
R/W
LOA
Reserved
Port B
Port A
Port B Connect
Wake Interrupt Wake Interrupt Change
Enable
Enable
Interrupt Enable
R/W
0000 0000
Result...
Port A
SE0
Status
VBUS
ID
Reserved
Interrupt Flag Interrupt Flag
SOF/EOP
Reserved
Interrupt Flag
xxxx xxxx
Reserved
xxxx xxxx
Done
Interrupt
Flag
SOF/EOP
Reset
xxxx xxxx
Interrupt Flag Interrupt Flag
EP7
EP6
EP5
EP4
EP3
EP2
EP1
EP0
xxxx xxxx
Interrupt Flag Interrupt Flag Interrupt Flag Interrupt Flag Interrupt Flag Interrupt Flag Interrupt Flag Interrupt Flag
R/W
0xC092
0xC0B2
Host n SOF/EOP Count
R
0xC092
0xC0B2
Device n Frame Number
R
0xC094
0xC0B4
Host n SOF/EOP Counter
W
0xC094
0xC0B4
Device n SOF/EOP Count
R
0xC096
0xC0B6
Host n Frame
0xC0AC
Host 2 Interrupt Enable
Reserved
Count...
0010 1110
...Count
SOF/EOP
Timeout
Flag
1110 0000
SOF/EOP
Timeout
Interrupt Count
Reserved
Frame...
0000 0000
...Frame
R/W
0000 0000
Reserved
Counter...
xxxx xxxx
Count...
0010 1110
...Counter
xxxx xxxx
Reserved
...Count
1110 0000
Reserved
Frame...
0000 0000
Reserved
SOF/EOP
Interrupt
Enable
Port B
Port A
Port B Connect
Wake Interrupt Wake Interrupt Change
Enable
Enable
Interrupt
Enable
R/W
0xC0AC
Device 2 Interrupt Enable
0xC0B0
Host 2 Status
EP6
Interrupt
Enable
EP5
Interrupt
Enable
EP4
Interrupt
Enable
Reserved
Reserved
0000 0000
Done
Interrupt
Enable
0000 0000
SOF/EOP
Timeout
Interrupt
Enable
Wake
Interrupt
Enable
SOF/EOP
Interrupt
Enable
Reset
Interrupt
Enable
0000 0000
EP3
Interrupt
Enable
EP2
Interrupt
Enable
EP1
Interrupt
Enable
EP0
Interrupt
Enable
0000 0000
SOF/EOP
Interrupt
Flag
Reserved
xxxx xxxx
Reserved
Done
Interrupt
Flag
xxxx xxxx
Reserved
Port B
Port A
Port B
Wake Interrupt Wake Interrupt Connect
Flag
Flag
Change
Interrupt Flag
Document #: 38-08015 Rev. *D
Port A Connect Change
Interrupt
Enable
Reserved
EP7
Interrupt
Enable
R/W
0000 0000
...Frame
Port A
Port B
Connect
SE0
Change
Status
Interrupt Flag
Port A
SE0
Status
Page 117 of 120
PRELIMINARY
CY7C67300
Table 15-1. Register Summary (continued)
R/W
R/W
Address Register
0xC0B0
Device 2 Status
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
Default High
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Default Low
SOF/EOP
Timeout
Interrupt
Enable
Wake
Interrupt
Flag
SOF/EOP
Interrupt
Flag
Reset
Interrupt
Flag
xxxx xxxx
Reserved
EP7
EP6
EP5
EP4
EP3
EP2
EP1
EP0
xxxx xxxx
Interrupt Flag Interrupt Flag Interrupt Flag Interrupt Flag Interrupt Flag Interrupt Flag Interrupt Flag Interrupt Flag
R/W
0xC0C6
HPI Mailbox
Message...
0000 0000
...Message
R/W
R/W
R/W
R
0xC0C8
0xC0CA
0xC0CC
0xC0CE
SPI Configuration
SPI Control
SPI Interrupt Enable
SPI Status
3Wire
Enable
0xC0D0
SPI Interrupt Clear
R/W
0xC0D2
SPI CRC Control
R/W
0xC0D4
SPI CRC Value
R/W
R/W
0xC0D6
0xC0D8
SPI Data Port t
SPI Transmit Address
SCK
Scale Select
Polarity Select
Reserved
Master
Master
Active Enable Enable
SS
Enable
SS Delay Select
SCK
Strobe
FIFO
Init
Byte
Mode
FullDuplex
Transmit
Empty
receive
Full
Transmit Bit Length
SS
Manual
0001 1111
Read
Enable
Transmit
Ready
receive
Data Ready
Receive Bit Length
R/W
0xC0DA
0xC0DC
SPI Transmit Count
SPI Receive Address
0000 0000
...Reserved
Receive Inter- Transmit Inter- Transfer Inter- 0000 0000
rupt Enable
rupt Enable
rupt Enable
Reserved...
0000 0000
Reserved
Receive
Transmit
Transfer
0000 0000
Interrupt Flag Interrupt Flag Interrupt Flag
Reserved...
0000 0000
...Reserved
Transmit
Transmit
0000 0000
Interrupt Clear Interrupt Clear
CRC Mode
CRC
Enable
CRC
Clear
Receive
CRC
One in CRC
Zero in CRC
Reserved...
0xC0DE
SPI Receive Count
0000 0000
CRC..
1111 1111
...CRC
1111 1111
Reserved
xxxx xxxx
Data
xxxx xxxx
Address...
0000 0000
0000 0000
Reserved
Count...
0000 0000
...Count
0000 0000
Address...
0000 0000
0000 0000
Reserved
Count...
0000 0000
...Count
R/W
0xC0E0
UART Control
0000 0000
Reserved...
0000 0000
...Reserved
R
0xC0E2
UART Status
Scale Select
Baud Select
UART Enable 0000 0111
Reserved...
0000 0000
...Reserved
R/W
0xC0E4
UART Data
Receive
Full
Transmit
Empty
Reserved
0xC0E6
PWM Control
PWM
Enable
0000 0000
Reserved
Prescale
Select
PWM3
PWM2
PWM1
PWM0
PWM3
Polarity Select Polarity Select Polarity Select Polarity Select Enable
R/W
0xC0E8
PWM Maximum Count
PWM2
Enable
Reserved
PWM1
Enable
Mode
Select
0000 0000
PWM0
Enable
0000 0000
Count...
0000 0000
...Count
R/W
R/W
R/W
0:
PWM n Start
0xC0EA
1:
0xC0EE
2: 0xC0F2
3: 0xC0F6
Reserved
0:
PWM n Stop
0xC0EC
1: 0xC0F0
2: 0xC0F4
3: 0xC0F8
Reserved
0xC0FA
PWM Cycle Count
0000 0000
Address...
0000 0000
...Address
0000 0000
Address...
0000 0000
...Address
0000 0000
Count...
0000 0000
...Count
R
HPI Status Port
VBUS
Flag
0000 0000
ID
Flag
Reserved
Resume2 Flag Resume1 Flag SIE2msg
Document #: 38-08015 Rev. *D
0000 0001
0000 0000
Data
R/W
0000 0000
...Reserved
...Address
R/W
0000 0001
1000 0000
...Address
R/W
1000 0000
Reserved...
FIFO Error
Flag
W
0000 0000
Phase
Select
SOF/EOP2
Flag
Reserved
SOF/EOP1
Flag
Reset2
Flag
Mailbox In
Flag
SIE1msg
Done2 Flag
Done1 Flag
Reset1 Flag
Mailbox Out
Flag
Page 118 of 120
PRELIMINARY
16.0
CY7C67300
Ordering Information
Table 16-1. Ordering Information
Ordering Code
Package Type
CY7C67300-100AI
100 TQFP
CY3663
Development Kit
17.0
Temperature Range
–40 to 85 °C
Package Diagrams
100-Pin Thin Plastic Quad Flat Pack (TQFP) A100
51-85048-*B
This document is subject to change, and may be found to contain errors of omission or changes in parameters. The reader, as
an early developer of USB 2.0 and under a nondisclosure agreement with Cypress, is encouraged to provide any information to
Cypress that may be used to improve this document. Purchase of I2C components from Cypress, or one of its sublicensed
Associated Companies, conveys a license under the Philips I2C Patent Rights to use these components in an I2C system,
provided that the system conforms to the I2C Standard Specification as defined by Philips. EZ-Host is a trademark of Cypress
Semiconductor. All product and company names mentioned in this document may be the trademarks of their respective holders.
Document #: 38-08015 Rev. *D
Page 119 of 120
© Cypress Semiconductor Corporation, 2003. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use
of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize
its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress
Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges.
PRELIMINARY
CY7C67300
Document History Page
Document Title: CY7C67300 EZ-Host™ Programmable Embedded USB Host/Peripheral Controller
Document Number: 38-08015
REV.
ECN NO. Issue Date
Orig. of
Change
Description of Change
**
111872
03/22/02
MUL
New Data Sheet
*A
116989
08/23/02
MUL
Preliminary Data Sheet
*B
125262
04/10/03
MUL
Added Memory Map Section and Ordering Information Section
Moved Functional Register Map Tables into Register section
General Clean-up
*C
126210
05/23/03
MUL
Added Interface Description Section and Power Savings and Reset Section
Added Char Data
General Clean-up
*D
127335
05/29/03
KKV
Corrected font to enable correct symbol display
Document #: 38-08015 Rev. *D
Page 120 of 120