MOTOROLA M68000 FAMILY Programmer`s Reference - PCS

MOTOROLA
M68000 FAMILY
Programmer’s Reference Manual
(Includes CPU32 Instructions)
MOTOROLA INC., 1992
TABLE OF CONTENTS
Paragraph
Number
Title
Page
Number
Section 1
Introduction
1.1
1.1.1
1.1.2
1.1.3
1.1.4
1.2
1.2.1
1.2.2
1.2.2.1
1.2.2.2
1.2.3
1.2.3.1
1.2.3.2
1.2.3.3
1.2.3.4
1.2.4
1.3
1.3.1
1.3.2
1.3.3
1.3.4
1.3.5
1.3.6
1.3.6.1
1.3.6.2
1.4
1.5
1.5.1
1.5.2
1.6
1.6.1
1.6.2
1.6.3
1.6.4
1.6.5
1.6.6
1.7
1.7.1
MOTOROLA
Integer Unit User Programming Model. . . . . . . . . . . . . . . . . . . . . . . . . . 1-2
Data Registers (D7 – D0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-2
Address Registers (A7 – A0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-2
Program Counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-3
Condition Code Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-3
Floating-Point Unit User Programming Model . . . . . . . . . . . . . . . . . . . . 1-4
Floating-Point Data Registers (FP7 – FP0) . . . . . . . . . . . . . . . . . . . . . 1-4
Floating-Point Control Register (FPCR) . . . . . . . . . . . . . . . . . . . . . . . 1-5
Exception Enable Byte. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-5
Mode Control Byte. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-5
Floating-Point Status Register (FPSR) . . . . . . . . . . . . . . . . . . . . . . . . 1-5
Floating-Point Condition Code Byte. . . . . . . . . . . . . . . . . . . . . . . . . 1-5
Quotient Byte. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-6
Exception Status Byte.. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-6
Accrued Exception Byte. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-7
Floating-Point Instruction Address Register (FPIAR) . . . . . . . . . . . . . 1-8
Supervisor Programming Model. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-8
Address Register 7 (A7) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-10
Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-10
Vector Base Register (VBR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-11
Alternate Function Code Registers (SFC and DFC) . . . . . . . . . . . . . 1-11
Acu Status Register (MC68EC030 only) . . . . . . . . . . . . . . . . . . . . . . 1-11
Transparent Translation/access Control Registers . . . . . . . . . . . . . . 1-12
Transparent Translation/access Control Register Fields for the
M68030. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-12
Transparent Translation/access Control Register Fields for the
M68040. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-13
Integer Data Formats . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-14
Floating-Point Data Formats . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-15
Packed Decimal Real Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-15
Binary Floating-Point Formats . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-16
Floating-Point Data Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-17
Normalized Numbers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-18
Denormalized Numbers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-18
Zeros . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-19
Infinities . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-19
Not-A-Numbers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-19
Data Format and Type Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-20
Organization of Data in Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-25
Organization of Integer Data Formats in Registers . . . . . . . . . . . . . . 1-25
M68000 FAMILY PROGRAMMER’S REFERENCE MANUAL
iii
TABLE OF CONTENTS (Continued)
Paragraph
Number
1.7.2
1.7.3
Title
Page
Number
Organization of Integer Data Formats in Memory . . . . . . . . . . . . . . . 1-27
Organization of Fpu Data Formats in Registers and Memory . . . . . . 1-30
Section 2
Addressing Capabilities
2.1
2.2
2.2.1
2.2.2
2.2.3
2.2.4
2.2.5
2.2.6
2.2.7
2.2.8
2.2.9
2.2.10
2.2.11
2.2.12
2.2.13
2.2.14
2.2.15
2.2.16
2.2.17
2.2.18
2.3
2.4
2.5
2.5.1
2.5.2
2.5.2.1
2.5.2.2
2.5.2.3
2.6
2.6.1
2.6.2
Instruction Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-1
Effective Addressing Modes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-4
Data Register Direct Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-5
Address Register Direct Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-5
Address Register Indirect Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-5
Address Register Indirect with Postincrement Mode. . . . . . . . . . . . . . 2-6
Address Register Indirect with Predecrement Mode . . . . . . . . . . . . . . 2-7
Address Register Indirect with Displacement Mode . . . . . . . . . . . . . . 2-8
Address Register Indirect with Index (8-Bit Displacement) Mode . . . . 2-9
Address Register Indirect with Index (Base Displacement) Mode. . . 2-10
Memory Indirect Postindexed Mode . . . . . . . . . . . . . . . . . . . . . . . . . 2-11
Memory Indirect Preindexed Mode . . . . . . . . . . . . . . . . . . . . . . . . . . 2-12
Program Counter Indirect with Displacement Mode . . . . . . . . . . . . . 2-13
Program Counter Indirect with Index (8-Bit Displacement) Mode . . . 2-14
Program Counter Indirect with Index (Base Displacement) Mode. . . 2-15
Program Counter Memory Indirect Postindexed Mode . . . . . . . . . . . 2-16
Program Counter Memory Indirect Preindexed Mode . . . . . . . . . . . . 2-17
Absolute Short Addressing Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-18
Absolute Long Addressing Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-18
Immediate Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-19
Effective Addressing Mode Summary . . . . . . . . . . . . . . . . . . . . . . . . . 2-19
Brief Extension Word Format Compatibility . . . . . . . . . . . . . . . . . . . . . 2-21
Full Extension Addressing Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-22
No Memory Indirect Action Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-24
Memory Indirect Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-25
Memory Indirect with Preindex. . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-25
Memory Indirect with Postindex. . . . . . . . . . . . . . . . . . . . . . . . . . . 2-26
Memory Indirect with Index Suppressed.. . . . . . . . . . . . . . . . . . . . 2-27
Other Data Structures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-28
System Stack. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-28
Queues . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-29
Section 3
Instruction Set Summary
3.1
3.1.1
3.1.2
iv
Instruction Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-1
Data Movement Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-5
Integer Arithmetic Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-6
M68000 FAMILY PROGRAMMER’S REFERENCE MANUAL
MOTOROLA
TABLE OF CONTENTS (Continued)
Paragraph
Number
3.1.3
3.1.4
3.1.5
3.1.6
3.1.7
3.1.8
3.1.9
3.1.10
3.1.11
3.1.12
3.1.13
3.2
3.3
3.3.1
3.3.2
3.3.3
3.3.4
3.3.5
3.4
3.5
3.5.1
3.5.2
3.6
3.6.1
3.6.2
3.7
Title
Page
Number
Logical Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-8
Shift and Rotate Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-8
Bit Manipulation Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-10
Bit Field Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-10
Binary-Coded Decimal Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . 3-11
Program Control Instructions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-11
System Control Instructions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-12
Cache Control Instructions (MC68040) . . . . . . . . . . . . . . . . . . . . . . . 3-14
Multiprocessor Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-14
Memory Management Unit (MMU) Instructions. . . . . . . . . . . . . . . . . 3-15
Floating-Point Arithmetic Instructions . . . . . . . . . . . . . . . . . . . . . . . . 3-15
Integer Unit Condition Code Computation . . . . . . . . . . . . . . . . . . . . . . 3-17
Instruction Examples . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-20
Using the Cas and Cas2 Instructions . . . . . . . . . . . . . . . . . . . . . . . . 3-20
Using the Moves Instruction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-20
Nested Subroutine Calls . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-20
Bit Field Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-20
Pipeline Synchronization with the Nop Instruction. . . . . . . . . . . . . . . 3-21
Floating-Point Instruction Details . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-21
Floating-Point Computational Accuracy . . . . . . . . . . . . . . . . . . . . . . . . 3-23
Intermediate Result . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-24
Rounding the Result . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-25
Floating-Point Postprocessing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-27
Underflow, Round, Overflow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-28
Conditional Testing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-28
Instruction Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-32
Section 4
Integer Instructions
Section 5
Floating Point Instructions
Section 6
Supervisor (Privileged) Instructions
Section 7
CPU32 Instructions
Section 8
Instruction Format Summary
8.1
MOTOROLA
Instruction Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-1
M68000 FAMILY PROGRAMMER’S REFERENCE MANUAL
v
TABLE OF CONTENTS (Continued)
Paragraph
Number
8.1.1
8.1.2
8.1.3
8.1.4
8.1.5
8.1.6
8.1.7
8.1.7.1
8.1.7.2
8.1.8
8.1.9
8.1.10
8.2
Title
Page
Number
Coprocessor ID Field. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Effective Address Field . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Register/Memory Field . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Source Specifier Field . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Destination Register Field . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Conditional Predicate Field . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Shift and Rotate Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Count Register Field. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Register Field. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Size Field. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Opmode Field . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Address/Data Field . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Operation Code Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
8-1
8-1
8-1
8-1
8-2
8-2
8-2
8-2
8-2
8-4
8-4
8-4
8-4
Appendix A
Processor Instruction Summary
A.1
A.1.1
A.1.2
A.2
A.2.1
A.2.2
A.3
A.3.1
A.3.2
A.4
A.4.1
A.4.2
A.5
A.5.1
A.5.2
A.6
A.6.1
A.6.2
MC68000, MC68008, MC68010 Processors . . . . . . . . . . . . . . . . . . . .
M68000, MC68008, and MC68010 Instruction Set . . . . . . . . . . . . . .
MC68000, MC68008, and MC68010 Addressing Modes . . . . . . . . .
MC68020 Processors. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
MC68020 Instruction Set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
MC68020 Addressing Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
MC68030 Processors. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
MC68030 Instruction Set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
MC68030 Addressing Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
MC68040 Processors. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
MC68040 Instruction Set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
MC68040 Addressing Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
MC68881/MC68882 Coprocessors . . . . . . . . . . . . . . . . . . . . . . . . . . .
MC68881/MC68882 Instruction Set . . . . . . . . . . . . . . . . . . . . . . . . .
MC68881/MC68882 Addressing Modes . . . . . . . . . . . . . . . . . . . . . .
MC68851 Coprocessors. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
MC68851 Instruction Set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
MC68851 Addressing Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
A-12
A-12
A-16
A-17
A-17
A-20
A-21
A-21
A-24
A-25
A-25
A-29
A-30
A-30
A-31
A-31
A-31
A-31
Appendix B
Exception Processing Reference
B.1
B.2
B.3
vi
Exception Vector Assignments for the M68000 Family . . . . . . . . . . . . . B-1
Exception Stack Frames . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B-3
Floating-Point Stack Frames . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B-10
M68000 FAMILY PROGRAMMER’S REFERENCE MANUAL
MOTOROLA
TABLE OF CONTENTS (Concluded)
Paragraph
Number
Title
Page
Number
Appendix C
S-Record Output Format
C.1
C.2
C.3
MOTOROLA
S-Record Content. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . C-1
S-Record Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . C-2
S-Record Creation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . C-3
M68000 FAMILY PROGRAMMER’S REFERENCE MANUAL
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viii
M68000 FAMILY PROGRAMMER’S REFERENCE MANUAL
MOTOROLA
LIST OF FIGURES
Figure
Number
Title
1-1
1-2
1-3
1-4
1-5
1-6
1-7
1-8
1-9
1-11
1-12
1-13
1-14
1-15
1-16
1-17
1-19
1-18
1-20
1-21
1-22
M68000 Family User Programming Model....................................................... 1-2
M68000 Family Floating-Point Unit User Programming Model ........................ 1-4
Floating-Point Control Register ........................................................................ 1-5
FPSR Condition Code Byte.............................................................................. 1-6
FPSR Quotient Code Byte ............................................................................... 1-6
FPSR Exception Status Byte ........................................................................... 1-6
FPSR Accrued Exception Byte ........................................................................ 1-7
Status Register............................................................................................... 1-11
MC68030 Transparent Translation/MC68EC030 Access
Control Register Format................................................................................. 1-12
MC68040 and MC68LC040 Transparent Translation/MC68EC040
Access Control Register Format .................................................................... 1-13
Packed Decimal Real Format ........................................................................ 1-16
Binary Floating-Point Data Formats ............................................................... 1-16
Normalized Number Format........................................................................... 1-18
Denormalized Number Format....................................................................... 1-18
Zero Format ................................................................................................... 1-19
Infinity Format ................................................................................................ 1-19
Not-A-Number Format.................................................................................... 1-19
Organization of Integer Data Formats in Address Registers.......................... 1-26
Organization of Integer Data Formats in Data Registers ............................... 1-26
Memory Operand Addressing ........................................................................ 1-27
Memory Organization for Integer Operands................................................... 1-29
Organization of FPU Data Formats in Memory .............................................. 1-30
2-1
2-2
2-3
2-4
2-5
2-6
2-7
2-8
Instruction Word General Format..................................................................... 2-1
Instruction Word Specification Formats ........................................................... 2-2
M68000 Family Brief Extension Word Formats.............................................. 2-21
Addressing Array Items.................................................................................. 2-23
No Memory Indirect Action............................................................................. 2-24
Memory Indirect with Preindex....................................................................... 2-26
Memory Indirect with Postindex .................................................................... 2-27
Memory Indirect with Index Suppress ........................................................... 2-27
3-1
3-2
3-3
Intermediate Result Format............................................................................ 3-24
Rounding Algorithm Flowchart ....................................................................... 3-26
Instruction Description Format ....................................................................... 3-33
B-1
B-2
B-3
B-4
MC68000 Group 1 and 2 Exception Stack Frame ...........................................B-3
MC68000 Bus or Address Error Exception Stack Frame.................................B-3
Four-Word Stack Frame, Format $0 ................................................................B-3
Throwaway Four-Word Stack Frame, Format $1.............................................B-3
1-10
MOTOROLA
M68000 FAMILY PROGRAMMER’S REFERENCE MANUAL
Page
Number
ix
LIST OF FIGURES (Concluded)
Figure
Number
Title
B-5
B-6
B-7
B-11
B-12
B-13
B-14
B-15
B-16
B-17
B-18
B-19
B-20
B-21
B-22
B-23
Six-Word Stack Frame, Format $2...................................................................B-4
MC68040 Floating-Point Post-Instruction Stack Frame, Format $3.................B-4
MC68EC040 and MC68LC040 Floating-Point Unimplemented
Stack Frame, Format $4 ..................................................................................B-5
MC68040 Access Error Stack Frame, Format $7 ...........................................B-5
MC68010 Bus and Address Error Stack Frame, Format $8 ...........................B-6
MC68020 Bus and MC68030 Coprocessor Mid-Instruction
Stack Frame, Format $9 ..................................................................................B-6
MC68020 and MC68030 Short Bus Cycle Stack Frame, Format $A ...............B-7
MC68020 and MC68030 Long Bus Cycle Stack Frame, Format $B...............B-8
CPU32 Bus Error for Prefetches and Operands Stack Frame, Format $C.....B-8
CPU32 Bus Error on MOVEM Operand Stack Frame, Format $C .................B-9
CPU32 Four- and Six-Word Bus Error Stack Frame, Format $C....................B-9
MC68881/MC68882 and MC68040 Null Stack Frame..................................B-10
MC68881 Idle Stack Frame ..........................................................................B-10
MC68881 Busy Stack Frame ........................................................................B-11
MC68882 Idle Stack Frame ...........................................................................B-11
MC68882 Busy Stack Frame .........................................................................B-11
MC68040 Idle Busy Stack Frame ..................................................................B-12
MC68040 Unimplimented Instruction Stack Frame........................................B-12
MC68040 Busy Stack Frame .........................................................................B-13
C-1
C-2
Five Fields of an S-Record...............................................................................C-1
Transmission of an S1 Record.........................................................................C-4
B-8
B-9
B-10
x
M68000 FAMILY PROGRAMMER’S REFERENCE MANUAL
Page
Number
MOTOROLA
LIST OF TABLES
Table
Number
Title
Page
Number
1-1
1-2
1-3
1-4
1-5
1-6
1-6
1-7
1-8
Supervisor Registers Not Related To Paged Memory Management .............. 1-9
Supervisor Registers Related To Paged Memory Management................... 1-10
Integer Data Formats .................................................................................... 1-15
Single-Precision Real Format Summary Data Format .................................. 1-21
Double-Precision Real Format Summary...................................................... 1-22
Extended-Precision Real Format Summary.................................................. 1-23
Extended-Precision Real Format Summary (Continued) .............................. 1-24
Packed Decimal Real Format Summary ....................................................... 1-24
MC68040 FPU Data Formats and Data Types ............................................. 1-30
2-1
2-2
2-3
2-4
Instruction Word Format Field Definitions ....................................................... 2-3
IS-I/IS Memory Indirect Action Encodings....................................................... 2-4
Immediate Operand Location........................................................................ 2-19
Effective Addressing Modes and Categories ................................................ 2-20
3-1
3-1
3-1
3-2
3-3
3-4
3-5
3-6
3-7
3-8
3-9
3-10
3-11
3-12
3-13
3-14
3-15
3-16
3-17
3-18
3-19
3-20
3-21
3-22
3-23
5-1
5-2
Notational Conventions ................................................................................... 3-2
Notational Conventions (Continued) ............................................................... 3-3
Notational Conventions (Concluded) .............................................................. 3-4
Data Movement Operation Format.................................................................. 3-6
Integer Arithmetic Operation Format............................................................... 3-7
Logical Operation Format................................................................................ 3-8
Shift and Rotate Operation Format ................................................................. 3-9
Bit Manipulation Operation Format ............................................................... 3-10
Bit Field Operation Format ............................................................................ 3-10
Binary-Coded Decimal Operation Format ..................................................... 3-11
Program Control Operation Format............................................................... 3-12
System Control Operation Format ................................................................ 3-13
Cache Control Operation Format .................................................................. 3-14
Multiprocessor Operations ............................................................................ 3-14
MMU Operation Format ................................................................................ 3-15
Dyadic Floating-Point Operation Format....................................................... 3-16
Dyadic Floating-Point Operations ................................................................. 3-16
Monadic Floating-Point Operation Format .................................................... 3-16
Monadic Floating-Point Operations............................................................... 3-17
Integer Unit Condition Code Computations................................................... 3-18
Conditional Tests .......................................................................................... 3-19
Operation Table Example (FADD Instruction)............................................... 3-22
FPCR Encodings........................................................................................... 3-25
FPCC Encodings........................................................................................... 3-29
Floating-Point Conditional Tests ................................................................... 3-31
Directly Supported Floating-Point Instructions ................................................ 5-2
Indirectly Supported Floating-Point Instructions.............................................. 5-3
MOTOROLA
M68000 FAMILY PROGRAMMER’S REFERENCE MANUAL
xi
LIST OF TABLES (Continued)
Table
Number
Title
Page
Number
7-1
7-2
7-3
MC68020 Instructions Not Supported ............................................................. 7-1
M68000 Family Addressing Modes................................................................. 7-2
CPU32 Instruction Set..................................................................................... 7-3
8-1
8-2
Conditional Predicate Field Encoding ............................................................. 8-3
Operation Code Map....................................................................................... 8-4
A-1
A-2
A-3
A-4
A-5
A-6
A-7
A-8
A-9
A-10
A-11
A-12
A-13
M68000 Family Instruction Set And Processor Cross-Reference................... A-1
M68000 Family Instruction Set........................................................................ A-8
MC68000 and MC68008 Instruction Set ....................................................... A-12
MC68010 Instruction Set............................................................................... A-14
MC68000, MC68008, and MC68010 Data Addressing Modes ..................... A-16
MC68020 Instruction Set Summary .............................................................. A-17
MC68020 Data Addressing Modes ............................................................... A-20
MC68030 Instruction Set Summary .............................................................. A-21
MC68030 Data Addressing Modes ............................................................... A-24
MC68040 Instruction Set............................................................................... A-25
MC68040 Data Addressing Modes ............................................................... A-29
MC68881/MC68882 Instruction Set .............................................................. A-30
MC68851 Instruction Set............................................................................... A-31
B-1
Exception Vector Assignments for the M68000 Family................................... B-2
C-1
C-2
Field Composition of an S-Record ..................................................................C-1
ASCII Code .....................................................................................................C-5
xii
M68000 FAMILY PROGRAMMER’S REFERENCE MANUAL
MOTOROLA
SECTION 5
FLOATING POINT INSTRUCTIONS
This section contains information about the floating-point instructions for the MC68881,
MC68882, and MC68040. In this section, all references to the MC68040 do not include the
MC68LC040 and MC68EC040. Each instruction is described in detail, and the instruction
descriptions are arranged in alphabetical order by instruction mnemonic.
All floating-point instructions apply to the MC68881 and MC68882 processors. The
MC68040 directly supports part of the floating-point instructions through hardware. It
indirectly supports the remainder by providing special traps and/or stack frames for the
unimplemented instructions and data types. The following identification is noted under the
instruction title for the MC68040:
Directly Supported—(MC6888X, MC68040)
Software Supported—(MC6888X, MC68040FPSW)
For all MC68040 floating-point instructions, the coprocessor ID field must be 001.
Table 5-1 lists the floating-point instructions directly supported by the MC68040, and Table
5-2 lists the floating-point instructions indirectly supported.
MOTOROLA
M68000 FAMILY PROGRAMMER’S REFERENCE MANUAL
5-1
Floating Point Instructions
Table 5-1. Directly Supported Floating-Point Instructions
Mnemonic
Description
FABS
Floating-Point Absolute Value
FADD
Floating-Point Add
FBcc
Floating-Point Branch Conditionally
FCMP
Floating-Point Compare
FDBcc
Floating-Point Test Condition, Decrement, and Branch
FDIV
Floating-Point Divide
FMOVE
Move Floating-Point Data Register
FMOVE
Move Floating-Point System Control Register
FMOVEM
Move Multiple Floating-Point System Data Register
FMOVEM
Move Multiple Floating-Point Control Data Register
FMUL
Floating-Point Multiply
FNEG
Floating-Point Negate
FNOP
No Operation
FRESTORE*
Restore Internal Floating-Point State*
FSAVE*
Save Internal Floating-Point State*
FScc
Set According to Floating-Point Condition
FSORT
Floating-Point Square Root
FSUB
Floating-Point Subtract
FSGLDIV
Floating-Point Single-Precision Divide
FSFLMUL
Floating-Point Single-Precision Multiply
FTRAPcc
Trap on Floating-Point Condition
FTST
Test Floating-Point Operand
*These are privileged instructions; refer to Section 6 Supervisor (Privaleged) Instructions for
detailed information.
5-2
M68000 FAMILY PROGRAMMER’S REFERENCE MANUAL
MOTOROLA
Floating Point Instructions
Table 5-2. Indirectly Supported Floating-Point Instructions
Mnemonic
MOTOROLA
Description
FACOS
Floating-Point Arc Cosine
FASIN
Floating-Point Arc Sine
FATAN
Floating-Point Arc Tangent
FATANH
Floating-Point Hyperbolic Arc Tangent
FCOS
Floating-Point Cosine
FCOSH
Floating-Point Hyperbolic Cosine
FETOX
Floating-Point ex
FETOXM1
Floating-Point ex – 1
FGETEXP
Floating-Point Get Exponent
FGETMAN
Floating-Point Get Mantissa
FINT
Floating-Point Integer Part
FINTRZ
Floating-Point Integer Part, Round-to- Zero
FLOG10
Floating-Point Log10
FLOG2
Floating-Point Log2
FLOGN
Floating-Point Loge
FLOGNP1
Floating-Point Loge (x + 1)
FMOD
Floating-Point Modulo Remainder
FMOVECR
Floating-Point Move Constant ROM
FREM
Floating-Point IEEE Remainder
FSCALE
Floating-Point Scale Exponent
FSIN
Floating-Point Sine
FSINCOS
Floating-Point Simultaneous Sine and Cosine
FSINH
Floating-Point Hyperbolic Sine
FTAN
Floating-Point Tangent
FTANH
Floating-Point Hyperbolic Tangent
FTENTOX
Floating-Point 10x
FTWOTOX
Floating-Point 2x
M68000 FAMILY PROGRAMMER’S REFERENCE MANUAL
5-3
Floating Point Instructions
FABS
FABS
Floating-Point Absolute Value
(MC6888X, MC68040)
Absolute Value of Source → FPn
Operation:
Assembler
Syntax:
FABS. < fmt >
< ea > ,FPn
FABS.X
FPm,FPn
FABS.X
FPn
*FrABS. < fmt > < ea > ,FPn
*FrABS.X
FPm,FPn
*FrABS.X
Pn
where r is rounding precision, S or D
*Supported by MC68040 only.
Attributes:
Format = (Byte, Word, Long, Single, Quad, Extended, Packed)
Description: Converts the source operand to extended precision (if necessary) and stores
the absolute value of that number in the destination floating-point data register.
FABS will round the result to the precision selected in the floating-point control register.
FSABS and FDABS will round the result to single or double precision, respectively,
regardless of the rounding precision selected in the floating-point control register.
Operation Table:
DESTINATION
Result
+
In Range
Absolute Value
– +
SOURCE
Zero
Absolute Value
– +
Infinity
–
Absolute Value
NOTE: If the source operand is a NAN, refer to 1.6.5 Not-A-Numbers for more information
5-4
M68000 FAMILY PROGRAMMER’S REFERENCE MANUAL
MOTOROLA
Floating Point Instructions
FABS
FABS
Floating-Point Absolute Value
(MC6888X, MC68040)
Floating-Point Status Register:
Condition Codes:
Affected as described in 3.6.2 Conditional Testing.
Quotient Byte:
Not affected.
Exception Byte:
BSUN
SNAN
OPERR
OVFL
UNFL
Cleared
Refer to 1.6.5 Not-A-Numbers
Cleared
Cleared
If the source is an extended-precision
denormalized number, refer to exception
processing in the appropriate user’s manual;
cleared otherwise.
Cleared
Cleared
If < fmt > is packed, refer to exception
processing in the appropriate user’s manual;
cleared otherwise.
DZ
INEX2
INEX1
Accrued Exception Byte:
Affected as described in exception processing; refer to the
appropriate user’s manual.
Instruction Format:
15
14
13
1
1
1
0
R/M
0
MOTOROLA
12
1
11
9
8
7
6
COPROCESSOR
ID
0
0
0
SOURCE
SPECIFIER
10
DESTINATION
REGISTER
5
4
3
2
1
0
EFFECTIVE ADDRESS
MODE
REGISTER
OPMODE
M68000 FAMILY PROGRAMMER’S REFERENCE MANUAL
5-5
Floating Point Instructions
FABS
Floating-Point Absolute Value
(MC6888X, MC68040)
FABS
Instruction Fields:
Effective Address field—Determines the addressing mode for external operands.
If R/M = 0, this field is unused and should be all zeros.
If R/M = 1, this field specifies the location of the source operand. Only data
addressing modes can be used as listed in the following table:
Addressing Mode
Mode
Register
Addressing Mode
Mode
Register
Dn
000
reg. number:Dn
(xxx).W
111
000
An
—
—
(xxx).L
111
001
(An)
010
reg. number:An
# < data >
111
100
(An) +
011
reg. number:An
– (An)
100
reg. number:An
(d16,An)
101
reg. number:An
(d16,PC)
111
010
(d8,An,Xn)
110
reg. number:An
(d8,PC,Xn)
111
011
(bd,An,Xn)
110
reg. number:An
(bd,PC,Xn)
111
011
([bd,An,Xn],od)
110
reg. number:An
([bd,PC,Xn],od)
111
011
([bd,An],Xn,od)
110
reg. number:An
([bd,PC],Xn,od)
111
011
*Only if < fmt > is byte, word, long, or single.
R/M field—Specifies the source operand address mode.
0 — The operation is register to register.
1 — The operation is < ea > to register.
5-6
M68000 FAMILY PROGRAMMER’S REFERENCE MANUAL
MOTOROLA
Floating Point Instructions
FABS
Floating-Point Absolute Value
(MC6888X, MC68040)
FABS
Source Specifier field—Specifies the source register or data format.
If R/M = 0, specifies the source floating-point data register.
If R/M = 1, specifies the source data format:
000 — Long-Word Integer (L)
001 — Single-Precision Real (S)
010 — Extended-Precision Real (X)
011 — Packed-Decimal Real (P)*
100 — Word Integer (W)
101 — Double-Precision Real (D)
110 — Byte Integer (B)
*This encoding will cause an unimplemented
data type exception in the MC68040 to allow emulation in software.
Destination Register field—Specifies the destination floating- point data register.
Opmode field—Specifies the instruction and rounding precision.
0011000 FABS
1011000 FSABS
1011100 FDABS
MOTOROLA
Rounding precision specified by the floating-point control
register.
Single-precision rounding specified.
Double-precision rounding specified.
M68000 FAMILY PROGRAMMER’S REFERENCE MANUAL
5-7
Floating Point Instructions
FACOS
FACOS
Arc Cosine
(MC6888X, M68040FPSP)
Operation:
Arc Cosine of Source → FPn
Assembler
Syntax:
FACOS. < fmt >
FACOS.X
FACOS.X
Attributes:
Format = (Byte, Word, Long, Single, Double, Extended, Packed)
< ea > ,FPn
FPm,FPn
FPn
Description: Converts the source operand to extended precision (if necessary) and
calculates the arc cosine of that number. Stores the result in the destination floatingpoint data register. This function is not defined for source operands outside of the range
[ – 1... + 1]; if the source is not in the correct range, a NAN is returned as the result and
the OPERR bit is set in the floating- point status register. If the source is in the correct
range, the result is in the range of [0...π].
Operation Table:
DESTINATION
+
Result
In Range
– +
Arc Cosine
SOURCE
Zero
– +
+ π/2
Infinity
–
NAN
NOTES:
1. If the source operand is a NAN, refer to 1.6.5 Not-A-Numbers for more information.
2. Sets the OPERR bit in the floating-point status register exception byte.
Floating-Point Status Register:
Condition Codes:
Affected as described in 3.6.2 Conditional Testing.
Quotient Byte:
Not affected.
Exception Byte:
BSUN
SNAN
OPERR
OVFL
UNFL
DZ
INEX2
INEX1
Accrued Exception Byte:
5-8
Cleared
Refer to 1.6.5 Not-A-Numbers.
Set if the source is infinity, > + 1 or < – 1;
cleared otherwise.
Cleared
Cleared
Cleared
Refer to inexact result in the appropriate
user’s manual.
If < fmt > is packed, refer to inexact result on
decimal input in the appropriate user’s
manual; cleared otherwise.
Affected as described in IEEE exception and trap compatibility in the appropriate user’s manual.
M68000 FAMILY PROGRAMMER’S REFERENCE MANUAL
MOTOROLA
Floating Point Instructions
FACOS
FACOS
Arc Cosine
(MC6888X, M68040FPSP)
Instruction Format:
15
14
13
12
1
1
1
1
0
R/M
11
10
9
COPROCESSOR
ID
SOURCE
SPECIFIER
0
8
7
6
0
0
0
DESTINATION
REGISTER
0
5
4
3
2
1
EFFECTIVE ADDRESS
MODE
0
1
0
REGISTER
1
1
0
0
Instruction Fields:
Coprocessor ID field—Specifies which coprocessor in the system is to execute this
instruction. Motorola assemblers default to ID = 1 for the floating-point
coprocessor.
Effective Address field—Determines the addressing mode for external operands.
If R/M = 0, this field is unused and should be all zeros.
If R/M = 1, this field is encoded with an M68000 family addressing mode as listed in
the following table:
Addressing Mode
Mode
Register
Addressing Mode
Mode
Register
Dn*
000
reg. number:Dn
(xxx).W
111
000
An
—
—
(xxx).L
111
001
(An)
010
reg. number:An
# < data >
111
100
(An) +
011
reg. number:An
– (An)
100
reg. number:An
(d16,An)
101
reg. number:An
(d16,PC)
111
010
(d8,An,Xn)
110
reg. number:An
(d8,PC,Xn)
111
011
(bd,An,Xn)
110
reg. number:An
(bd,PC,Xn)
111
011
([bd,An,Xn],od)
110
reg. number:An
([bd,PC,Xn],od)
111
011
([bd,An],Xn,od)
110
reg. number:An
([bd,PC],Xn,od)
111
011
*Only if < fmt > is byte, word, long, or single.
R/M field—Specifies the source operand address mode.
0 — The operation is register to register.
1 — The operation is < ea > to register.
MOTOROLA
M68000 FAMILY PROGRAMMER’S REFERENCE MANUAL
5-9
Floating Point Instructions
FACOS
Arc Cosine
(MC6888X, M68040FPSP)
FACOS
Source Specifier field—Specifies the source register or data format.
If R/M = 0, specifies the source floating-point data register.
If R/M = 1, specifies the source data format:
000 — Long-Word Integer (L)
001 — Single-Precision Real (S)
010 — Extended-Precision Real (X)
011 — Packed-Decimal Real (P)
100 — Word Integer (W)
101 — Double-Precision Real (D)
110 — Byte Integer (B)
Destination Register field—Specifies the destination floating- point data register. If R/
M = 0 and the source and destination fields are equal, then the input operand is
taken from the specified floating-point data register, and the result is then written
into the same register. If the single register syntax is used, Motorola assemblers
set the source and destination fields to the same value.
5-10
M68000 FAMILY PROGRAMMER’S REFERENCE MANUAL
MOTOROLA
Floating Point Instructions
FADD
FADD
Floating-Point Add
(MC6888X, MC68040)
Operation:
Source + FPn → FPn
Assembler
Syntax:
FADD. < fmt >
< ea > ,FPn
FADD.X
FPm,FPn
*FrADD. < fmt > < ea > ,FPn
*FrADD.X
FPm,FPn
where r is rounding precision, S or D
*Supported by MC68040 only.
Attributes:
Format = (Byte, Word, Long, Single, Double, Extended, Packed)
Description: Converts the source operand to extended precision (if necessary) and adds
that number to the number contained in the destination floating-point data register.
Stores the result in the destination floating-point data register.
FADD will round the result to the precision selected in the floating-point control register.
FSADD and FDADD will round the result to single or double-precision, respectively,
regardless of the rounding precision selected in the floating-point control register.
Operation Table:
DESTINATION
+
In Range
– +
In Range
+
–
Add
Add
Zero
+
–
Add
+ 0.0
0.02
Infinity
+
–
SOURCE1
Zero
+ inf
+ inf
– inf
– inf
– +
Infinity
–
+ inf
– inf
0.02 + inf
– 0.0
– inf
+ inf
NAN‡
NAN3
– inf
1. If either operand is a NAN, refer to 1.6.5 Not-A-Numbers for more information.
2. Returns + 0.0 in rounding modes RN, RZ, and RP; returns – 0.0 in RM.
3. Sets the OPERR bit in the floating-point status register exception byte.
MOTOROLA
M68000 FAMILY PROGRAMMER’S REFERENCE MANUAL
5-11
Floating Point Instructions
FADD
FADD
Floating-Point Add
(MC6888X, MC68040)
Floating-Point Status Register:
Condition Codes:
Affected as described in 3.6.2 Conditional Testing.
Quotient Byte:
Not affected.
Exception Byte:
BSUN
SNAN
OPERR
Cleared
Refer to 1.6.5 Not-A-Numbers.
Set if the source and the destination are
opposite-signed infinities; cleared otherwise.
Refer to exception processing in the
appropriate user’s manual.
Refer to exception processing in the
appropriate user’s manual.
Cleared
Refer to exception processing in the
appropriate user’s manual.
If < fmt > is packed, refer to exception
processing in the appropriate user’s manual;
cleared otherwise.
OVFL
UNFL
DZ
INEX2
INEX1
Accrued Exception Byte:
Affected as described in exception processing in the appropriate user’s manual.
Instruction Format:
15
14
13
12
1
1
1
1
0
R/M
11
10
9
COPROCESSOR
ID
SOURCE
SPECIFIER
0
8
7
6
0
0
0
DESTINATION
REGISTER
5
4
3
2
1
EFFECTIVE ADDRESS
MODE
0
REGISTER
OPMODE
Instruction Fields:
Effective Address field—Determines the addressing mode for external operands.
If R/M = 0, this field is unused and should be all zeros.
5-12
M68000 FAMILY PROGRAMMER’S REFERENCE MANUAL
MOTOROLA
Floating Point Instructions
FADD
FADD
Floating-Point Add
(MC6888X, MC68040)
If R/M = 1, specifies the location of the source operand location. Only data
addressing modes can be used as listed in the following table:
Addressing Mode
Mode
Register
Addressing Mode
Mode
Register
Dn
000
reg. number:Dn
(xxx).W
111
000
An
—
—
(xxx).L
111
001
(An)
010
reg. number:An
# < data >
111
100
(An) +
011
reg. number:An
– (An)
100
reg. number:An
(d16,An)
101
reg. number:An
(d16,PC)
111
010
(d8,An,Xn)
110
reg. number:An
(d8,PC,Xn)
111
011
(bd,An,Xn)
110
reg. number:An
(bd,PC,Xn)
111
011
([bd,An,Xn],od)
110
reg. number:An
([bd,PC,Xn],od)
111
011
([bd,An],Xn,od)
110
reg. number:An
([bd,PC],Xn,od)
111
011
*Only if < fmt > is byte, word, long, or single.
R/M field—Specifies the source operand address mode.
0 — The operation is register to register.
1 — The operation is < ea > to register.
Source Specifier field—Specifies the source register or data format.
If R/M = 0, specifies the source floating-point data register.
If R/M = 1, specifies the source data format:
000 — Long-Word Integer (L)
001 — Single-Precision Real (S)
010 — Extended-Precision Real (X)
011 — Packed-Decimal Real (P)*
100 — Word Integer (W)
101 — Double-Precision Real (D)
110 — Byte Integer (B)
*This encoding will cause an unimplemented data type exception to allow
emulation in software.
Destination Register field—Specifies the destination floating- point data register.
Opmode field—Specifies the instruction and rounding precision.
0100010 FADD
1100010 FSADD
1100110 FDADD
MOTOROLA
Rounding precision specified by the floating-point control
register.
Single-precision rounding specified.
Double-precision rounding specified.
M68000 FAMILY PROGRAMMER’S REFERENCE MANUAL
5-13
Floating Point Instructions
FASIN
FASIN
Arc Sine
(MC6888X, M68040FPSP)
Operation:
Arc Sine of the Source → FPn
Assembler
Syntax:
FASIN. < fmt >
FASIN.X
FASIN.X
Attributes:
Format = (Byte, Word, Long, Single, Double, Extended, Packed)
< ea > ,FPn
FPm,FPn
FPn
Description: Converts the source operand to extended precision (if necessary) and
calculates the arc sine of the number. Stores the result in the destination floating-point
data register. This function is not defined for source operands outside of the range [ –
1... + 1]; if the source is not in the correct range, a NAN is returned as the result and
the OPERR bit is set in the floating- point status register. If the source is in the correct
range, the result is in the range of [ – π/2... + π/2].
Operation Table:
DESTINATION
Result
+
In Range
Arc Sine
– +
+ 0.0
SOURCE1
Zero
– +
– 0.0
Infinity
–
NAN2
NOTES:
1. If the source operand is a NAN, refer to 1.6.5 Not-A-Numbers for more information.
2. Sets the OPERR bit in the floating-point status register exception byte.
5-14
M68000 FAMILY PROGRAMMER’S REFERENCE MANUAL
MOTOROLA
Floating Point Instructions
FASIN
FASIN
Arc Sine
(MC6888X, M68040FPSP)
Floating-Point Status Register:
Condition Codes:
Affected as described in 3.6.2 Conditional Testing.
Quotient Byte:
Not affected.
Exception Byte:
BSUN
SNAN
OPERR
Cleared
Refer to 1.6.5 Not-A-Numbers.
Set if the source is infinity, > + 1 or < – 1;
cleared otherwise
Cleared
Can be set for an underflow condition.
Cleared
Refer to inexact result in the appropriate
user’s manual.
If < fmt > is packed, refer to inexact result on
decimal input in the appropriate user’s
manual; cleared otherwise.
OVFL
UNFL
DZ
INEX2
INEX1
Accrued Exception Byte:
Affected as described in IEEE exception and trap compatibility in the appropriate user’s manual.
Instruction Format:
15
14
13
1
1
1
0
R/M
0
12
1
11
9
8
7
6
COPROCESSOR
ID
0
0
0
SOURCE
SPECIFIER
10
DESTINATION
REGISTER
0
5
0
4
3
2
1
0
EFFECTIVE ADDRESS
MODE
REGISTER
0
1
1
0
0
Instruction Fields:
Coprocessor ID field—Specifies which coprocessor in the system is to execute this
instruction. Motorola assemblers default to ID = 1 for the floating-point
coprocessor.
MOTOROLA
M68000 FAMILY PROGRAMMER’S REFERENCE MANUAL
5-15
Floating Point Instructions
FASIN
FASIN
Arc Sine
(MC6888X, M68040FPSP)
Effective Address field—Determines the addressing mode for external operands.
If R/M = 0, this field is unused and should be all zeros.
If R/M = 1, this field is encoded with an M68000 family addressing mode as listed in
the following table:
Addressing Mode
Mode
Register
Addressing Mode
Mode
Register
Dn*
000
reg. number:Dn
(xxx).W
111
000
An
—
—
(xxx).L
111
001
(An)
010
reg. number:An
# < data >
111
100
(An) +
011
reg. number:An
– (An)
100
reg. number:An
(d16,An)
101
reg. number:An
(d16,PC)
111
010
(d8,An,Xn)
110
reg. number:An
(d8,PC,Xn)
111
011
(bd,An,Xn)
110
reg. number:An
(bd,PC,Xn)
111
011
([bd,An,Xn],od)
110
reg. number:An
([bd,PC,Xn],od)
111
011
([bd,An],Xn,od)
110
reg. number:An
([bd,PC],Xn,od)
111
011
*Only if < fmt > is byte, word, long, or single.
R/M field—Specifies the source operand address mode.
0 — The operation is register to register.
1 — The operation is < ea > to register.
Source Specifier field—Specifies the source register or data format.
If R/M = 0, specifies the source floating-point data register.
If R/M = 1, specifies the source data format:
000 — Long-Word Integer (L)
001 — Single-Precision Real (S)
010 — Extended-Precision Real (X)
011 — Packed-Decimal Real (P)
100 — Word Integer (W)
101 — Double-Precision Real (D)
110 — Byte Integer (B)
Destination Register field—Specifies the destination floating- point data register. If R/
M = 0 and the source and destination fields are equal, then the input operand is
taken from the specified floating-point data register, and the result is then written
into the same register. If the single register syntax is used, Motorola assemblers
set the source and destination fields to the same value.
5-16
M68000 FAMILY PROGRAMMER’S REFERENCE MANUAL
MOTOROLA
Floating Point Instructions
FATAN
FATAN
Arc Tangent
(MC6888X, M68040FPSP)
Operation:
Arc Tangent of Source → FPn
Assembler
Syntax:
FATAN. < fmt >
FATAN.X
FATAN.X
Attributes:
Format = (Byte, Word, Long, Single, Double, Extended, Packed)
< ea > ,FPn
FPm,FPn
FPm,FPnz
Description: Converts the source operand to extended precision (if necessary) and
calculates the arc tangent of that number. Stores the result in the destination floatingpoint data register. The result is in the range of [ – π/2... + π/2].
Operation Table:
DESTINATION
+
Result
In Range
– +
Arc Tangent
+ 0.0
SOURCE
Zero
– +
– 0.0 + π/2
Infinity
–
– π/2
NOTE: If the source operand is a NAN, refer to 1.6.5 Not-A-Numbers for more information.
Floating-Point Status Register:
Condition Codes:
Affected as described in 3.6.2 Conditional Testing.
Quotient Byte:
Not affected.
Exception Byte:
BSUN
SNAN
OPERR
OVFL
UNFL
DZ
INEX2
INEX1
Accrued Exception Byte:
MOTOROLA
Cleared
Refer to 1.6.5 Not-A-Numbers.
Cleared
Cleared
Refer to underflow in the appropriate user’s
manual.
Cleared
Refer to inexact result in the appropriate
user’s manual.
If < fmt > is packed, refer to inexact result on
decimal input in the appropriate user’s
manual; cleared otherwise.
Affected as described in IEEE exception and trap compatibility in the appropriate user’s manual.
M68000 FAMILY PROGRAMMER’S REFERENCE MANUAL
5-17
Floating Point Instructions
FATAN
FATAN
Arc Tangent
(MC6888X, M68040FPSP)
Instruction Format:
15
14
13
1
1
1
0
R/M
0
12
1
11
9
8
7
6
COPROCESSOR
ID
10
0
0
0
SOURCE
SPECIFIER
DESTINATION
REGISTER
0
5
4
3
2
1
0
EFFECTIVE ADDRESS
MODE
REGISTER
0
0
1
1
0
0
Instruction Fields:
Coprocessor ID field—Specifies which coprocessor in the system is to execute this
instruction. Motorola assemblers default to ID = 1 for the floating-point
coprocessor.
Effective Address field—Determines the addressing mode for external operands.
If R/M = 0, this field is unused and should be all zeros.
If R/M = 1, this field is encoded with an M68000 family addressing mode as listed in
the following table:
Addressing Mode
Mode
Register
Addressing Mode
Mode
Register
Dn*
000
reg. number:Dn
(xxx).W
111
000
An
—
—
(xxx).L
111
001
(An)
010
reg. number:An
# < data >
111
100
(An) +
011
reg. number:An
– (An)
100
reg. number:An
(d16,An)
101
reg. number:An
(d16,PC)
111
010
(d8,An,Xn)
110
reg. number:An
(d8,PC,Xn)
111
011
(bd,An,Xn)
110
reg. number:An
(bd,PC,Xn)
111
011
([bd,An,Xn],od)
110
reg. number:An
([bd,PC,Xn],od)
111
011
([bd,An],Xn,od)
110
reg. number:An
([bd,PC],Xn,od)
111
011
*Only if < fmt > is byte, word, long, or single.
R/M field—Specifies the source operand address mode.
0 — The operation is register to register.
1 — The operation is < ea > to register.
5-18
M68000 FAMILY PROGRAMMER’S REFERENCE MANUAL
MOTOROLA
Floating Point Instructions
FATAN
Arc Tangent
(MC6888X, M68040FPSP)
FATAN
Source Specifier field—Specifies the source register or data format.
If R/M = 0, specifies the source floating-point data register.
If R/M = 1, specifies the source data format:
000 — Long-Word Integer (L)
001 — Single-Precision Real (S)
010 — Extended-Precision Real (X)
011 — Packed-Decimal Real (P)
100 — Word Integer (W)
101 — Double-Precision Real (D)
110 — Byte Integer (B)
Destination Register field—Specifies the destination floating- point data register. If R/
M = 0 and the source and destination fields are equal, then the input operand is
taken from the specified floating-point data register, and the result is then written
into the same register. If the single register syntax is used, Motorola assemblers
set the source and destination fields to the same value.
MOTOROLA
M68000 FAMILY PROGRAMMER’S REFERENCE MANUAL
5-19
Floating Point Instructions
FATANH
FATANH
Hyperbolic Arc Tangent
(MC6888X, M68040FPSP)
Operation:
Hyperbolic Arc Tangent of Source → FPn
Assembler
Syntax:
FATANH. < fmt > < ea > ,FPn
FATANH.X
FPm,FPn
FATANH.X
FPn
Attributes:
Format = (Byte, Word, Long, Single, Double, Extended, Packed)
Description: Converts the source operand to extended precision (if necessary) and
calculates the hyperbolic arc tangent of that value. Stores the result in the destination
floating-point data register. This function is not defined for source operands outside of
the range ( – 1... + 1); and the result is equal to – infinity or + infinity if the source is
equal to + 1 or – 1, respectively. If the source is outside of the range [ – 1... + 1], a NAN
is returned as the result, and the OPERR bit is set in the floating-point status register.
Operation Table:
DESTINATION
+
In Range
– +
Hyperbolic
Arc Tangent
Result
+ 0.0
SOURCE1
Zero
– +
– 0.0
Infinity
–
NAN2
NOTES:
1. If the source operand is a NAN, refer to 1.6.5 Not-A-Numbers for more information.
2. Sets the OPERR bit in the floating-point status register exception byte.
Floating-Point Status Register:
5-20
Condition Codes:
Affected as described in 3.6.2 Conditional Testing.
Quotient Byte:
Not affected.
M68000 FAMILY PROGRAMMER’S REFERENCE MANUAL
MOTOROLA
Floating Point Instructions
FATANH
FATANH
Hyperbolic Arc Tangent
(MC6888X, M68040FPSP)
Exception Byte:
BSUN
SNAN
OPERR
Cleared
Refer to 1.6.5 Not-A-Numbers.
Set if the source is > + 1 or < – 1; cleared
otherwise.
Cleared
Refer to underflow in the appropriate user’s
manual.
Set if the source is equal to + 1 or – 1; cleared
otherwise.
Refer to inexact result in the appropriate
user’s manual.
If < fmt > is packed, refer to inexact result on
decimal input in the appropriate user’s
manual; cleared otherwise.
OVFL
UNFL
DZ
INEX2
INEX1
Accrued Exception Byte:
Affected as described in IEEE exception and trap compatibility in the appropriate user’s manual.
Instruction Format:
15
14
13
1
1
1
0
R/M
0
12
1
11
9
8
7
6
COPROCESSOR
ID
0
0
0
SOURCE
SPECIFIER
10
DESTINATION
REGISTER
0
5
0
4
3
2
1
0
EFFECTIVE ADDRESS
MODE
REGISTER
0
1
1
0
1
Instruction Fields:
Coprocessor ID field—Specifies which coprocessor in the system is to execute this
instruction. Motorola assemblers default to ID = 1 for the floating-point
coprocessor.
MOTOROLA
M68000 FAMILY PROGRAMMER’S REFERENCE MANUAL
5-21
Floating Point Instructions
FATANH
FATANH
Hyperbolic Arc Tangent
(MC6888X, M68040FPSP)
Effective Address field—Determines the addressing mode for external operands.
If R/M = 0, this field is unused and should be all zeros.
If R/M = 1, this field is encoded with an M68000 family addressing mode as listed in
the following table:
Addressing Mode
Mode
Register
Addressing Mode
Mode
Register
Dn*
000
reg. number:Dn
(xxx).W
111
000
An
—
—
(xxx).L
111
001
(An)
010
reg. number:An
# < data >
111
100
(An) +
011
reg. number:An
– (An)
100
reg. number:An
(d16,An)
101
reg. number:An
(d16,PC)
111
010
(d8,An,Xn)
110
reg. number:An
(d8,PC,Xn)
111
011
(bd,An,Xn)
110
reg. number:An
(bd,PC,Xn)
111
011
([bd,An,Xn],od)
110
reg. number:An
([bd,PC,Xn],od)
111
011
([bd,An],Xn,od)
110
reg. number:An
([bd,PC],Xn,od)
111
011
*Only if < fmt > is byte, word, long, or single.
R/M field—Specifies the source operand address mode.
0 — The operation is register to register.
1 — The operation is < ea > to register.
Source Specifier field—Specifies the source register or data format.
If R/M = 0, specifies the source floating-point data register.
If R/M = 1, specifies the source data format:
000 — Long-Word Integer (L)
001 — Single-Precision Real (S)
010 — Extended-Precision Real (X)
011 — Packed-Decimal Real (P)
100 — Word Integer (W)
101 — Double-Precision Real (D)
110 — Byte Integer (B)
Destination Register field—Specifies the destination floating- point data register. If R/
M = 0 and the source and destination fields are equal, then the input operand is
taken from the specified floating-point data register, and the result is then written
into the same register. If the single register syntax is used, Motorola assemblers
set the source and destination fields to the same value.
5-22
M68000 FAMILY PROGRAMMER’S REFERENCE MANUAL
MOTOROLA
Floating Point Instructions
FBcc
Operation:
Floating-Point Branch Conditionally
(MC6888X, MC68040)
FBcc
If Condition True
Then PC + dn → PC
Assembler:
Syntax:
FBcc. < size > , < label >
Attributes:
Size = (Word, Long)
Description: If the specified floating-point condition is met, program execution continues at
the location (PC) + displacement. The displacement is a twos-complement integer that
counts the relative distance in bytes. The value of the program counter used to
calculate the destination address is the address of the branch instruction plus two. If
the displacement size is word, then a 16- bit displacement is stored in the word
immediately following the instruction operation word. If the displacement size is long
word, then a 32-bit displacement is stored in the two words immediately following the
instruction operation word. The conditional specifier cc selects any one of the 32
floating- point conditional tests as described in 3.6.2 Conditional Testing.
Floating-Point Status Register:
Condition Codes:
Not affected.
Quotient Byte:
Not affected.
Exception Byte:
BSUN
SNAN
OPERR
OVF
UNFL
DZ
INEX2
INEX1
Accrued Exception Byte:
MOTOROLA
Set if the NAN condition code is set and the
condition selected is an IEEE nonaware test.
Not Affected.
Not Affected.
Not Affected.
Not Affected.
Not Affected.
Not Affected.
Not Affected.
The IOP bit is set if the BSUN bit is set in the exception
byte. No other bit is affected.
M68000 FAMILY PROGRAMMER’S REFERENCE MANUAL
5-23
Floating Point Instructions
FBcc
Floating-Point Branch Conditionally
(MC6888X, MC68040)
FBcc
Instruction Format:
15
14
1
1
13
12
11
10
9
8
7
6
5
4
3
2
1
COPROCESSOR
1
1
0
1
SIZE
CONDITIONAL PREDICATE
ID
16-BIT DISPLACEMENT OR MOST SIGNIFICANT WORD OF 32-BITDISPLACEMENT
LEAST SIGNIFICANT WORD OF 32-BIT DISPLACEMENT (IF NEEDED)
0
Instruction Fields:
Size field—Specifies the size of the signed displacement.
If Format = 0, then the displacement is 16 bits and is sign- extended before use.
If Format = 1, then the displacement is 32 bits.
Conditional Predicate field—Specifies one of 32 conditional tests as defined in Table
3-23 Floating-Point Conditional Tests.
NOTE
When a BSUN exception occurs, the main processor takes a
preinstruction exception. If the exception handler returns without
modifying the image of the program counter on the stack frame
(to point to the instruction following the FBcc), then it must clear
the cause of the exception (by clearing the NAN bit or disabling
the BSUN trap), or the exception will occur again immediately
upon return to the routine that caused the exception.
5-24
M68000 FAMILY PROGRAMMER’S REFERENCE MANUAL
MOTOROLA
Floating Point Instructions
FCMP
FCMP
Floating-Point Compare
(MC6888X, MC68040)
Operation:
FPn – Source
Assembler
Syntax:
FCMP. < fmt > < ea > ,FPn
FCMP.X FPm,FPn
Attributes:
Format = (Byte, Word, Long, Single, Double, Extended, Packed)
Description: Converts the source operand to extended precision (if necessary) and
subtracts the operand from the destination floating- point data register. The result of the
subtraction is not retained, but it is used to set the floating-point condition codes as
described in 3.6.2 Conditional Testing.
Operation Table: The entries in this operation table differ from those of the tables
describing most of the floating-point instructions. For each combination of input
operand types, the condition code bits that may be set are indicated. If the name of a
condition code bit is given and is not enclosed in brackets, then it is always set. If the
name of a condition code bit is enclosed in brackets, then that bit is either set or
cleared, as appropriate. If the name of a condition code bit is not given, then that bit is
always cleared by the operation. The infinity bit is always cleared by the FCMP
instruction since it is not used by any of the conditional predicate equations. Note that
the NAN bit is not shown since NANs are always handled in the same manner (as
described in 1.6.5 Not-A-Numbers).
DESTINATION
In Range
Zero
–
Infinity
+
In Range
– +
+ {NZ}
– N
none none
{NZ} N
+ N
N
none Z
none NZ
+ none
– N
none none
N N
SOURCE
Zero
– +
Infinity
–
none N
N N
none
none
Z N
NZ N
none
none
none Z
N N
none
NZ
NOTE: If the source operand is a NAN, refer to 1.6.5 Not-A-Numbers for more information.
MOTOROLA
M68000 FAMILY PROGRAMMER’S REFERENCE MANUAL
5-25
Floating Point Instructions
FCMP
FCMP
Floating-Point Compare
(MC6888X, MC68040)
Floating-Point Status Register:
Condition Codes:
Affected as described in the preceding operation table.
Quotient Byte:
Not affected.
Exception Byte:
BSUN
SNAN
OPERR
OVFL
UNFL
DZ
INEX2
INEX1
Accrued Exception Byte:
Affected as described in exception processing in the appropriate user’s manual.
Cleared
Refer to 1.6.5 Not-A-Numbers.
Cleared
Cleared
Cleared
Cleared
Cleared
If < fmt > is packed, refer to exception
processing in the appropriate user’s manual;
cleared otherwise.
Instruction Format:
15
14
13
1
1
1
0
R/M
0
5-26
12
1
11
9
8
7
6
COPROCESSOR
ID
0
0
0
SOURCE
SPECIFIER
10
DESTINATION
REGISTER
0
5
0
4
3
2
1
0
EFFECTIVE ADDRESS
MODE
REGISTER
0
1
M68000 FAMILY PROGRAMMER’S REFERENCE MANUAL
1
0
0
MOTOROLA
Floating Point Instructions
FCMP
FCMP
Floating-Point Compare
(MC6888X, MC68040)
Instruction Fields:
Effective Address field—Determines the addressing mode for external operands.
If R/M = 0, this field is unused and should be all zeros.
If R/M = 1, specifies the location of the source operand location. Only data
addressing modes can be used as listed in the following table:
Addressing Mode
Mode
Register
Addressing Mode
Mode
Register
Dn*
000
reg. number:Dn
(xxx).W
111
000
An
—
—
(xxx).L
111
001
(An)
010
reg. number:An
# < data >
111
100
(An) +
011
reg. number:An
– (An)
100
reg. number:An
(d16,An)
101
reg. number:An
(d16,PC)
111
010
(d8,An,Xn)
110
reg. number:An
(d8,PC,Xn)
111
011
(bd,An,Xn)
110
reg. number:An
(bd,PC,Xn)
111
011
([bd,An,Xn],od)
110
reg. number:An
([bd,PC,Xn],od)
111
011
([bd,An],Xn,od)
110
reg. number:An
([bd,PC],Xn,od)
111
011
*Only if < fmt > is byte, word, long, or single.
R/M field—Specifies the source operand address mode.
0 — The operation is register to register.
1 — The operation is < ea > to register.
Source Specifier field—Specifies the source register or data format.
If R/M = 0, specifies the source floating-point data register.
If R/M = 1, specifies the source data format:
000 — Long-Word Integer (L)
001 — Single-Precision Real (S)
010 — Extended-Precision Real (X)
011 — Packed-Decimal Real (P)*
100 — Word Integer (W)
101 — Double-Precision Real (D)
110 — Byte Integer (B)
*This encoding in the MC68040 will cause an unimplemented data type
exception to allow emulation in software.
Destination Register field—Specifies the destination floating- point data register.
MOTOROLA
M68000 FAMILY PROGRAMMER’S REFERENCE MANUAL
5-27
Floating Point Instructions
FCOS
FCOS
Cosine
(MC6888X, M68040FPSP)
Operation:
Cosine of Source → FPn
Assembler
Syntax:
FCOS. < fmt > < ea > ,FPn
FCOS.X FPm,FPn FCOS.X FPn
Attributes:
Format = (Byte, Word, Long, Single, Double, Extended, Packed)
Description: Converts the source operand to extended precision (if necessary) and
calculates the cosine of that number. Stores the result in the destination floating-point
data register. This function is not defined for source operands of ± infinity. If the source
operand is not in the range of [ – 2π... + 2π], then the argument is reduced to within that
range before the cosine is calculated. However, large arguments may lose accuracy
during reduction, and very large arguments (greater than approximately 1020) lose all
accuracy. The result is in the range of [ – 1... + 1].
Operation Table:
DESTINATION
Result
+
In Range
Cosine
– +
SOURCE1
Zero
– +
+ 1.0
Infinity
–
NAN2
NOTES:
1. If the source operand is a NAN, refer to 1.6.5 Not-A-Numbers for more information.
2. Sets the OPERR bit in the floating-point status register exception byte.
5-28
M68000 FAMILY PROGRAMMER’S REFERENCE MANUAL
MOTOROLA
Floating Point Instructions
FCOS
FCOS
Cosine
(MC6888X, M68040FPSP)
Floating-Point Status Register:
Condition Codes:
Affected as described in 3.6.2 Conditional Testing.
Quotient Byte:
Not affected
Exception Byte:
BSUN
SNAN
OPERR
Cleared
Refer to 1.6.5 Not-A-Numbers.
Set if the source operand is ± infinity; cleared
otherwise.
Cleared
Cleared
Cleared
Refer to inexact result in the appropriate
user’s manual.
If < fmt > is packed, refer to inexact result on
decimal input in the appropriate user’s
manual; cleared otherwise.
OVFL
UNFL
DZ
INEX2
INEX1
Accrued Exception Byte:
Affected as described in IEEE exception and trap compatibility in the appropriate user’s manual.
Instruction Format:
15
14
13
1
1
1
0
R/M
0
12
1
11
9
8
7
6
COPROCESSOR
ID
0
0
0
SOURCE
SPECIFIER
10
DESTINATION
REGISTER
0
5
0
4
3
2
1
0
EFFECTIVE ADDRESS
MODE
REGISTER
1
1
1
0
1
Instruction Fields:
Coprocessor ID field—Specifies which coprocessor in the system is to execute this
instruction. Motorola assemblers default to ID = 1 for the floating-point
coprocessor.
MOTOROLA
M68000 FAMILY PROGRAMMER’S REFERENCE MANUAL
5-29
Floating Point Instructions
FCOS
FCOS
Cosine
(MC6888X, M68040FPSP)
Effective Address field—Determines the addressing mode for external operands.
If R/M = 0, this field is unused and should contain zeros.
If R/M = 1, this field is encoded with an M68000 family addressing mode as listed in
the following table:
Addressing Mode
Mode
Register
Addressing Mode
Mode
Register
Dn*
000
reg. number:Dn
(xxx).W
111
000
An
—
—
(xxx).L
111
001
(An)
010
reg. number:An
# < data >
111
100
(An) +
011
reg. number:An
– (An)
100
reg. number:An
(d16,An)
101
reg. number:An
(d16,PC)
111
010
(d8,An,Xn)
110
reg. number:An
(d8,PC,Xn)
111
011
(bd,An,Xn)
110
reg. number:An
(bd,PC,Xn)
111
011
([bd,An,Xn],od)
110
reg. number:An
([bd,PC,Xn],od)
111
011
([bd,An],Xn,od)
110
reg. number:An
([bd,PC],Xn,od)
111
011
*Only if < fmt > is byte, word, long, or single.
R/M field—Specifies the source operand address mode.
0 — The operation is register to register.
1 — The operation is < ea > to register.
Source Specifier field—Specifies the source register or data format.
If R/M = 0, specifies the source floating-point data register.
If R/M = 1, specifies the source data format:
000 — Long-Word Integer (L)
001 — Single-Precision Real (S)
010 — Extended-Precision Real (X)
011 — Packed-Decimal Real (P)
100 — Word Integer (W)
101 — Double-Precision Real (D)
110 — Byte Integer (B)
Destination Register field—Specifies the destination floating- point data register. If R/
M = 0 and the source and destination fields are equal, then the input operand is
taken from the specified floating-point data register, and the result is written into
the same register. If the single register syntax is used, Motorola assemblers set
the source and destination fields to the same value.
5-30
M68000 FAMILY PROGRAMMER’S REFERENCE MANUAL
MOTOROLA
Floating Point Instructions
FCOSH
FCOSH
Hyperbolic Cosine
(MC6888X, M68040FPSP)
Operation:
Hyperbolic Cosine of Source → FPn
Assembler
Syntax:
FCOSH. < fmt > < ea > ,FPn
FCOSH.X FPm,FPn FCOSH.X FPn
Attributes:
Format = (Byte, Word, Long, Single, Double, Extended, Packed)
Description: Converts the source operand to extended precision (if necessary) and
calculates the hyperbolic cosine of that number. Stores the result in the destination
floating-point data register.
Operation Table:
DESTINATION
Result
+
In Range
– +
Hyperbolic Cosine
SOURCE
Zero
– +
+ 1.0
Infinity
–
+ inf
NOTE: If the source operand is a NAN, refer to 1.6.5 Not-A-Numbers for more information.
Floating-Point Status Register:
Condition Codes:
Affected as described in 3.6.2 Conditional Testing.
Quotient Byte:
Not affected.
Exception Byte:
BSUN
SNAN
OPERR
OVFL
UNFL
DZ
INEX2
INEX1
Accrued Exception Byte:
MOTOROLA
Cleared
Refer to 1.6.5 Not-A-Numbers.
Cleared
Refer to overflow in the appropriate user’s
manual.
Cleared
Cleared
Refer to inexact result in the appropriate
user’s manual.
If < fmt > is packed, refer to inexact result on
decimal input in the appropriate user’s
manual; cleared otherwise.
Affected as described in IEEE exception and trap compatibility in the appropriate user’s manual.
M68000 FAMILY PROGRAMMER’S REFERENCE MANUAL
5-31
Floating Point Instructions
FCOSH
FCOSH
Hyperbolic Cosine
(MC6888X, M68040FPSP)
Instruction Format:
15
14
13
1
1
1
0
R/M
0
12
1
11
9
8
7
6
COPROCESSOR
ID
10
0
0
0
SOURCE
SPECIFIER
DESTINATION
REGISTER
0
5
0
4
3
2
1
0
EFFECTIVE ADDRESS
MODE
REGISTER
1
1
1
0
1
Instruction Fields:
Coprocessor ID field—Specifies which coprocessor in the system is to execute this
instruction. Motorola assemblers default to ID = 1 for the floating-point coprocessor.
Effective Address field—Determines the addressing mode for external operands.
If R/M = 0, this field is unused and should be all zeros.
If R/M = 1, this field is encoded with an M68000 family addressing mode as listed in
the following table:
Addressing Mode
Mode
Register
Addressing Mode
Mode
Register
Dn*
000
reg. number:Dn
(xxx).W
111
000
An
—
—
(xxx).L
111
001
(An)
010
reg. number:An
# < data >
111
100
(An) +
011
reg. number:An
– (An)
100
reg. number:An
(d16,An)
101
reg. number:An
(d16,PC)
111
010
(d8,An,Xn)
110
reg. number:An
(d8,PC,Xn)
111
011
(bd,An,Xn)
110
reg. number:An
(bd,PC,Xn)
111
011
([bd,An,Xn],od)
110
reg. number:An
([bd,PC,Xn],od)
111
011
([bd,An],Xn,od)
110
reg. number:An
([bd,PC],Xn,od)
111
011
*Only if < fmt > is byte, word, long, or single.
5-32
M68000 FAMILY PROGRAMMER’S REFERENCE MANUAL
MOTOROLA
Floating Point Instructions
FCOSH
Hyperbolic Cosine
(MC6888X, M68040FPSP)
FCOSH
R/M field—Specifies the source operand address mode.
0 — The operation is register to register.
1 — The operation is < ea > to register.
Source Specifier field—Specifies the source register or data format.
If R/M = 0, specifies the source floating-point data register.
If R/M = 1, specifies the source data format:
000 — Long-Word Integer (L)
001 — Single-Precision Real (S)
010 — Extended-Precision Real (X)
011 — Packed-Decimal Real (P)
100 — Word Integer (W)
101 — Double-Precision Real (D)
110 — Byte Integer (B)
Destination Register field—Specifies the destination floating- point data register. If R/
M = 0 and the source and destination fields are equal, then the input operand is
taken from the specified floating-point data register, and the result is written into
the same register. If the single register syntax is used, Motorola assemblers set
the source and destination fields to the same value.
MOTOROLA
M68000 FAMILY PROGRAMMER’S REFERENCE MANUAL
5-33
Floating Point Instructions
FDBcc
Floating-Point Test Condition,
Decrement, and Branch
FDBcc
(MC6888X, MC68040)
Operation:
If Condition True
Then No Operation
Else Dn – 1 → Dn
If Dn ≠ – 1
Then PC + dn → PC
Else Execute Next Instruction
Assembler
Syntax:
FDBcc Dn, < label >
Attributes:
Unsized
Description: This instruction is a looping primitive of three parameters: a floating-point
condition, a counter (data register), and a 16-bit displacement. The instruction first tests
the condition to determine if the termination condition for the loop has been met, and if
so, execution continues with the next instruction in the instruction stream. If the
termination condition is not true, the low-order 16 bits of the counter register are
decremented by one. If the result is – 1, the count is exhausted, and execution
continues with the next instruction. If the result is not equal to – 1, execution continues
at the location specified by the current value of the program counter plus the signextended 16-bit displacement. The value of the program counter used in the branch
address calculation is the address of the displacement word.
The conditional specifier cc selects any one of the 32 floating- point conditional tests
as described in 3.6.2 Conditional Testing.
Floating-Point Status Register:
Condition Codes:
Not affected.
Quotient Byte:
Not affected.
Exception Byte:
BSUN
SNAN
OPERR
OVFL
UNFL
DZ
NEX2
INEX1
Accrued Exception Byte:
5-34
Set if the NAN condition code is set and the
condition selected is an IEEE nonaware test.
Not Affected.
Not Affected.
Not Affected.
Not Affected.
Not Affected.
Not Affected.
Not Affected.
The IOP bit is set if the BSUN bit is set in the exception
byte. No other bit is affected.
M68000 FAMILY PROGRAMMER’S REFERENCE MANUAL
MOTOROLA
Floating Point Instructions
FDBcc
FDBcc
Floating-Point Test Condition,
Decrement, and Branch
(MC6888X, MC68040)
Instruction Format:
15
14
13
12
1
1
1
1
0
0
0
0
11
10
9
8
7
6
COPROCESSOR
0
0
1
ID
0
0
0
0
0
0
16-BIT DISPLACEMENT
5
0
4
3
2
1
0
COUNT
0
1
REGISTER
CONDITIONAL PREDICATE
Instruction Fields:
Count Register field—Specifies data register that is used as the counter.
Conditional Predicate field—Specifies one of the 32 floating-point conditional tests as
described in 3.6.2 Conditional Testing.
Displacement field—Specifies the branch distance (from the address of the instruction
plus two) to the destination in bytes.
NOTE
The terminating condition is like that defined by the UNTIL loop
constructs of high-level languages. For example: FDBOLT can
be stated as "decrement and branch until ordered less than".
There are two basic ways of entering a loop: at the beginning or
by branching to the trailing FDBcc instruction. If a loop structure
terminated with FDBcc is entered at the beginning, the control
counter must be one less than the number of loop executions
desired. This count is useful for indexed addressing modes and
dynamically specified bit operations. However, when entering a
loop by branching directly to the trailing FDBcc instruction, the
count should equal the loop execution count. In this case, if the
counter is zero when the loop is entered, the FDBcc instruction
does not branch, causing a complete bypass of the main loop.
When a BSUN exception occurs, a preinstruction exception is
taken by the main processor. If the exception handler returns
without modifying the image of the program counter on the stack
frame (to point to the instruction following the FDBcc), then it
must clear the cause of the exception (by clearing the NAN bit or
disabling the BSUN trap), or the exception will occur again immediately upon return to the routine that caused the exception.
MOTOROLA
M68000 FAMILY PROGRAMMER’S REFERENCE MANUAL
5-35
Floating Point Instructions
FDIV
FDIV
Floating-Point Divide
(MC6888X, MC68040)
Operation:
FPn ÷ Source → FPn
Assembler
Syntax:
FDIV. < fmt > < ea > ,FPn
FDIV.X FPm,FPn
*FrDIV. < fmt > < ea > ,FPn
*FrDIV.X FPm,FPn
where r is rounding precision, S or D
*Supported by MC68040 only
Attributes:
Format = (Byte, Word, Long, Single, Double, Extended, Packed)
Description: Converts the source operand to extended precision (if necessary) and divides
that number into the number in the destination floating-point data register. Stores the
result in the destination floating-point data register.
FDIV will round the result to the precision selected in the floating-point control register.
FSDIV and FDDIV will round the result to single or double precision, respectively,
regardless of the rounding precision selected in the floating-point control register.
Operation Table:
DESTINATION
In Range
+
+
–
Zero
+ + 0.0
– – 0.0
Infinity
+ + inf
– – inf
In Range
SOURCE1
Zero
– +
+
–
Divide
inf2
inf2
+ 0.0
+ 0.0
– inf + inf
+ inf – inf
– +
–
+
inf2
inf2
NAN3
Infinity
–
+ 0.0
– 0.0
– 0.0
+ 0.0
+ 0.0
– 0.0
– 0.0
+ 0.0
– inf
+ inf
NAN‡
NOTES:
1. If the source operand is a NAN, refer to 1.6.5 Not-A-Numbers for more information.
2. Sets the DZ bit in the floating-point status register exception byte.
3. Sets the OPERR bit in the floating-point status register exception byte.
5-36
M68000 FAMILY PROGRAMMER’S REFERENCE MANUAL
MOTOROLA
Floating Point Instructions
FDIV
FDIV
Floating-Point Divide
(MC6888X, MC68040)
Floating-Point Status Register:
Condition Codes:
Affected as described in 3.6.2 Conditional Testing.
Quotient Byte:
Not affected.
Exception Byte:
BSUN
SNAN
OPERR
Cleared
Refer to 1.6.5 Not-A-Numbers.
Set for 0 ÷ 0 or infinity ÷ infinity; cleared
otherwise.
Refer to exception processing in the
appropriate user’s manual.
Refer to exception processing in the
appropriate user’s manual.
Set if the source is zero and the destination is
in range; cleared otherwise.
Refer to exception processing in the
appropriate user’s manual.
If < fmt > is packed, refer to exception
processing in the appropriate user’s manual;
cleared otherwise.
OVFL
UNFL
DZ
INEX2
INEX1
Accrued Exception Byte:
Affected as described in exception processing in the appropriate user’s manual.
Instruction Format:
15
14
13
1
1
1
0
R/M
0
MOTOROLA
12
1
11
9
8
7
6
COPROCESSOR
ID
0
0
0
SOURCE
SPECIFIER
10
DESTINATION
REGISTER
5
4
3
2
1
0
EFFECTIVE ADDRESS
MODE
REGISTER
OPMODE
M68000 FAMILY PROGRAMMER’S REFERENCE MANUAL
5-37
Floating Point Instructions
FDIV
FDIV
Floating-Point Divide
(MC6888X, MC68040)
Instruction Fields:
Effective Address field—Determines the addressing mode for external operands.
If R/M = 0, this field is unused and should be all zeros.
If R/M = 1, specifies the location of the source operand location. Only data
addressing modes can be used as listed in the following table:
Addressing Mode
Mode
Register
Addressing Mode
Mode
Register
Dn*
000
reg. number:Dn
(xxx).W
111
000
An
—
—
(xxx).L
111
001
(An)
010
reg. number:An
# < data >
111
100
(An) +
011
reg. number:An
– (An)
100
reg. number:An
(d16,An)
101
reg. number:An
(d16,PC)
111
010
(d8,An,Xn)
110
reg. number:An
(d8,PC,Xn)
111
011
(bd,An,Xn)
110
reg. number:An
(bd,PC,Xn)
111
011
([bd,An,Xn],od)
110
reg. number:An
([bd,PC,Xn],od)
111
011
([bd,An],Xn,od)
110
reg. number:An
([bd,PC],Xn,od)
111
011
*Only if < fmt > is byte, word, long, or single.
R/M field—Specifies the source operand address mode.
0 — The operation is register to register.
1 — The operation is < ea > to register.
Source Specifier field—Specifies the source register or data format.
If R/M = 0, specifies the source floating-point data register.
If R/M = 1, specifies the source data format:
000 — Long-Word Integer (L)
001 — Single-Precision Real (S)
010 — Extended-Precision Real (X)
011 — Packed-Decimal Real (P)*
100 — Word Integer (W)
101 — Double-Precision Real (D)
110 — Byte Integer (B)
*This encoding in the MC68040 will cause an unimplemented data type
exception to allow emulation in software.
5-38
M68000 FAMILY PROGRAMMER’S REFERENCE MANUAL
MOTOROLA
Floating Point Instructions
FDIV
Floating-Point Divide
(MC6888X, MC68040)
FDIV
Destination Register field—Specifies the destination floating- point data register.
Opmode field—Specifies the instruction and rounding precision.
0100000 FDIV
1100000 FSDIV
1100100 FDDIV
MOTOROLA
Rounding precision specified by the floating- point
control register.
Single-precision rounding specified.
Double-precision rounding specified.
M68000 FAMILY PROGRAMMER’S REFERENCE MANUAL
5-39
Floating Point Instructions
FETOX
FETOX
ex
(MC6888X, M68040FPSP)
Operation:
eSource → FPn
Assembler
Syntax:
Syntax:
FETOX. < fmt > < ea > ,FPn
FETOX.X FPm,FPn
FETOX.X FPn
Attributes:
Format = (Byte, Word, Long, Single, Double, Extended, Packed)
Description: Converts the source operand to extended precision (if necessary) and
calculates e to the power of that number. Stores the result in the destination floatingpoint data register.
Operation Table:
DESTINATION
+
In Range
– +
ex
Result
SOURCE
Zero
+ 1.0
– +
+ inf
Infinity
–
+ 0.0
NOTE: If the source operand is a NAN, refer to 1.6.5 Not-A-Numbers for more information.
Floating-Point Status Register:
Condition Codes:
Affected as described in 3.6.2 Conditional Testing.
Quotient Byte:
Not affected.
Exception Byte:
BSUN
SNAN
OPERR
OVFL
UNFL
DZ
INEX2
INEX1
Accrued Exception Byte:
5-40
Cleared
Refer to 1.6.5 Not-A-Numbers.
Cleared
Refer to overflow in the appropriate user’s
manual.
Refer to underflow in the appropriate user’s
manual.
Cleared
Refer to inexact result in the appropriate
user’s manual.
If < fmt > is packed, refer to inexact result on
decimal input in the appropriate user’s
manual; cleared otherwise.
Affected as described in IEEE exception and trap compatibility in the appropriate user’s manual.
M68000 FAMILY PROGRAMMER’S REFERENCE MANUAL
MOTOROLA
Floating Point Instructions
FETOX
FETOX
ex
(MC6888X, M68040FPSP)
Instruction Format:
15
14
13
1
1
1
0
R/M
0
12
1
11
9
8
7
6
COPROCESSOR
ID
10
0
0
0
SOURCE
SPECIFIER
DESTINATION
REGISTER
0
5
0
4
3
2
1
0
EFFECTIVE ADDRESS
MODE
REGISTER
0
1
1
0
0
Instruction Fields:
Coprocessor ID field—Specifies which coprocessor in the system is to execute this
instruction. Motorola assemblers default to ID = 1 for the floating-point
coprocessor.
Effective Address field—Determines the addressing mode for external operands.
If R/M = 0, this field is unused and should be all zeros.
If R/M = 1, this field is encoded with an M68000 family addressing mode as listed in
the following table:
Addressing Mode
Mode
Register
Addressing Mode
Mode
Register
Dn*
000
reg. number:Dn
(xxx).W
111
000
An
—
—
(xxx).L
111
001
(An)
010
reg. number:An
# < data >
111
100
(An) +
011
reg. number:An
– (An)
100
reg. number:An
(d16,An)
101
reg. number:An
(d16,PC)
111
010
(d8,An,Xn)
110
reg. number:An
(d8,PC,Xn)
111
011
(bd,An,Xn)
110
reg. number:An
(bd,PC,Xn)
111
011
([bd,An,Xn],od)
110
reg. number:An
([bd,PC,Xn],od)
111
011
([bd,An],Xn,od)
110
reg. number:An
([bd,PC],Xn,od)
111
011
*Only if < fmt > is byte, word, long, or single.
MOTOROLA
M68000 FAMILY PROGRAMMER’S REFERENCE MANUAL
5-41
Floating Point Instructions
FETOX
ex
(MC6888X, M68040FPSP)
FETOX
R/M field—Specifies the source operand address mode.
0 — The operation is register to register.
1 — The operation is < ea > to register.
Source Specifier Field—Specifies the source register or data format.
If R/M = 0, specifies the source floating-point data register.
If R/M = 1, specifies the source data format:
000 — Long-Word Integer (L)
001 — Single-Precision Real (S)
010 — Extended-Precision Real (X)
011 — Packed-Decimal Real (P)*
100 — Word Integer (W)
101 — Double-Precision Real (D)
110 — Byte Integer (B)
Destination Register field—Specifies the destination floating- point data register. If R/
M = 0 and the source and destination fields are equal, then the input operand is
taken from the specified floating-point data register, and the result is written into
the same register. If the single register syntax is used, Motorola assemblers set
the source and destination fields to the same value.
5-42
M68000 FAMILY PROGRAMMER’S REFERENCE MANUAL
MOTOROLA
Floating Point Instructions
FETOXM1
FETOXM1
ex – 1
(MC6888X, M68040FPSP)
Operation:
eSource – 1 → FPn
Assembler
Syntax:
FETOXM1. < fmt > < ea > ,FPn
FETOXM1.X FPm,FPn
FETOXM1.X FPn
Attributes:
Format = (Byte, Word, Long, Single, Double, Extended, Packed)
Description: Converts the source operand to extended precision (if necessary) and
calculates e to the power of that number. Subtracts one from the value and stores the
result in the destination floating-point data register.
Operation Table:
DESTINATION
+
In Range
ex
Result
– +
–1
+ 0.0
SOURCE
Zero
– +
– 0.0 + inf
Infinity
–
– 1.0
NOTE: If the source operand is a NAN, refer to 1.6.5 Not-A-Numbers for more information.
Floating-Point Status Register:
Condition Codes:
Affected as described in 3.6.2 Conditional Testing.
Quotient Byte:
Exception Byte:
Not affected.
BSUN
SNAN
OPERR
OVFL
UNFL
DZ
INEX2
INEX1
Accrued Exception Byte:
MOTOROLA
Cleared
Refer to 1.6.5 Not-A-Numbers.
Cleared
Refer to overflow in the appropriate user’s
manual.
Refer to underflow in the appropriate user’s
manual.
Cleared
Refer to inexact result in the appropriate
user’s manual.
If < fmt > is packed, refer to inexact result on
decimal input in the appropriate user’s
manual; cleared otherwise.
Affected as described in IEEE exception and trap compatibility in the appropriate user’s manual.
M68000 FAMILY PROGRAMMER’S REFERENCE MANUAL
5-43
Floating Point Instructions
FETOXM1
FETOXM1
ex – 1
(MC6888X, M68040FPSP)
Instruction Format:
15
14
13
1
1
1
0
R/M
0
12
1
11
9
8
7
6
COPROCESSOR
ID
10
0
0
0
SOURCE
SPECIFIER
DESTINATION
REGISTER
0
5
0
4
3
2
1
0
EFFECTIVE ADDRESS
MODE
REGISTER
0
1
1
0
0
Instruction Fields:
Coprocessor ID field—Specifies which coprocessor in the system is to execute this
instruction. Motorola assemblers default to ID = 1 for the floating-point
coprocessor.
Effective Address field—Determines the addressing mode for external operands.
If R/M = 0, this field is unused and should be all zeros.
If R/M = 1, this field is encoded with an M68000 family addressing mode as listed in
the following table:
Addressing Mode
Mode
Register
Addressing Mode
Mode
Register
Dn*
000
reg. number:Dn
(xxx).W
111
000
An
—
—
(xxx).L
111
001
(An)
010
reg. number:An
# < data >
111
100
(An) +
011
reg. number:An
– (An)
100
reg. number:An
(d16,An)
101
reg. number:An
(d16,PC)
111
010
(d8,An,Xn)
110
reg. number:An
(d8,PC,Xn)
111
011
(bd,An,Xn)
110
reg. number:An
(bd,PC,Xn)
111
011
([bd,An,Xn],od)
110
reg. number:An
([bd,PC,Xn],od)
111
011
([bd,An],Xn,od)
110
reg. number:An
([bd,PC],Xn,od)
111
011
*Only if < fmt > is byte, word, long, or single.
5-44
M68000 FAMILY PROGRAMMER’S REFERENCE MANUAL
MOTOROLA
Floating Point Instructions
FETOXM1
ex – 1
(MC6888X, M68040FPSP)
FETOXM1
R/M field—Specifies the source operand address mode.
0 — The operation is register to register.
1 — The operation is < ea > to register.
Source Specifier Field—Specifies the source register or data format.
If R/M = 0, specifies the source floating-point data register.
If R/M = 1, specifies the source data format:
000 — Long-Word Integer (L)
001 — Single-Precision Real (S)
010 — Extended-Precision Real (X)
011 — Packed-Decimal Real (P)
100 — Word Integer (W)
101 — Double-Precision Real (D)
110 — Byte Integer (B)
Destination Register field—Specifies the destination floating- point data register. If R/
M = 0 and the source and destination fields are equal, then the input operand is
taken from the specified floating-point data register, and the result is written into
the same register. If the single register syntax is used, Motorola assemblers set
the source and destination fields to the same value.
MOTOROLA
M68000 FAMILY PROGRAMMER’S REFERENCE MANUAL
5-45
Floating Point Instructions
FGETEXP
FGETEXP
Get Exponent
(MC6888X, M68040FPSP)
Operation:
Exponent of Source → FPn
Assembler
Syntax:
FGETEXP. < fmt > < ea > ,FPn
FGETEXP.X FPm,FPn
FGETEXP.X FPn
Attributes:
Format = (Byte, Word, Long, Single, Double, Extended, Packed)
Description: Converts the source operand to extended precision (if necessary) and
extracts the binary exponent. Removes the exponent bias, converts the exponent to an
extended-precision floating- point number, and stores the result in the destination
floating- point data register.
Operation Table:
DESTINATION
+
Result
In Range
– +
Exponent
+ 0.0
SOURCE1
Zero
– +
– 0.0
Infinity
–
NAN2
NOTES:
1. If the source operand is a NAN, refer to 1.6.5 Not-A-Numbers for more information.
2. Sets the OPERR bit in the floating-point status register exception byte.
Floating-Point Status Register:
Condition Codes:
Affected as described in 3.6.2 Conditional Testing.
Quotient Byte:
Not affected.
Exception Byte:
BSUN
SNAN
OPERR
OVFL
UNFL
DZ
INEX2
INEX1
Accrued Exception Byte:
5-46
Cleared
Refer to 1.6.5 Not-A-Numbers.
Set if the source is ± infinity; cleared
otherwise.
Cleared
Cleared
Cleared
Cleared
If < fmt > is packed, refer to inexact result on
decimal input in the appropriate user’s
manual; cleared otherwise.
Affected as described in IEEE exception and trap compatibility in the appropriate user’s manual.
M68000 FAMILY PROGRAMMER’S REFERENCE MANUAL
MOTOROLA
Floating Point Instructions
FGETEXP
FGETEXP
Get Exponent
(MC6888X, M68040FPSP)
Instruction Format:
15
14
13
1
1
1
0
R/M
0
12
1
11
9
8
7
6
COPROCESSOR
ID
10
0
0
0
SOURCE
SPECIFIER
DESTINATION
REGISTER
0
5
4
3
2
1
0
EFFECTIVE ADDRESS
MODE
REGISTER
0
1
1
1
1
0
Instruction Fields:
Coprocessor ID field—Specifies which coprocessor in the system is to execute this
instruction. Motorola assemblers default to ID = 1 for the floating-point
coprocessor.
Effective Address field—Determines the addressing mode for external operands.
If R/M = 0, this field is unused and should be all zeros.
If R/M = 1, this field is encoded with an M68000 family addressing mode as listed in
the following table:
Addressing Mode
Mode
Register
Addressing Mode
Mode
Register
Dn*
000
reg. number:Dn
(xxx).W
111
000
An
—
—
(xxx).L
111
001
(An)
010
reg. number:An
# < data >
111
100
(An) +
011
reg. number:An
– (An)
100
reg. number:An
(d16,An)
101
reg. number:An
(d16,PC)
111
010
(d8,An,Xn)
110
reg. number:An
(d8,PC,Xn)
111
011
(bd,An,Xn)
110
reg. number:An
(bd,PC,Xn)
111
011
([bd,An,Xn],od)
110
reg. number:An
([bd,PC,Xn],od)
111
011
([bd,An],Xn,od)
110
reg. number:An
([bd,PC],Xn,od)
111
011
*Only if < fmt > is byte, word, long, or single.
R/M field—Specifies the source operand address mode.
0 — The operation is register to register.
1 — The operation is < ea > to register.
MOTOROLA
M68000 FAMILY PROGRAMMER’S REFERENCE MANUAL
5-47
Floating Point Instructions
FGETEXP
Get Exponent
(MC6888X, M68040FPSP)
FGETEXP
Source Specifier field—Specifies the source register or data format.
If R/M = 0, specifies the source floating-point data register.
If R/M = 1, specifies the source data format:
000 — Long-Word Integer (L)
001 — Single-Precision Real (S)
010 — Extended-Precision Real (X)
011 — Packed-Decimal Real (P)
100 — Word Integer (W)
101 — Double-Precision Real (D)
110 — Byte Integer (B)
Destination Register field—Specifies the destination floating- point data register. If R/
M = 0 and the source and destination fields are equal, then the input operand is
taken from the specified floating-point data register, and the result is written into
the same register. If the single register syntax is used, Motorola assemblers set
the source and destination fields to the same value.
5-48
M68000 FAMILY PROGRAMMER’S REFERENCE MANUAL
MOTOROLA
Floating Point Instructions
FGETMAN
FGETMAN
Get Mantissa
(MC6888X, M68040FPSP)
Operation:
Mantissa of Source → FPn
Assembler
Syntax:
FGETMAN. < fmt > < ea > ,FPn
FGETMAN.X FPm,FPn
FGETMAN.X FPn
Attributes:
Format = (Byte, Word, Long, Single, Double, Extended, Packed)
Description: Converts the source operand to extended precision (if necessary) and
extracts the mantissa. Converts the mantissa to an extended-precision value and
stores the result in the destination floating-point data register. The result is in the range
[1.0...2.0] with the sign of the source mantissa, zero, or a NAN.
Operation Table:
DESTINATION
+
Result
In Range
– +
Mantissa
+ 0.0
SOURCE1
Zero
– +
– 0.0
Infinity
–
NAN2
NOTES:
1. If the source operand is a NAN, refer to 1.6.5 Not-A-Numbers for more information.
2. Sets the OPERR bit in the floating-point status register exception byte.
Floating-Point Status Register:
Condition Codes:
Affected as described in 3.6.2 Conditional Testing.
Quotient Byte:
Not affected.
Exception Byte:
BSUN
SNAN
OPERR
OVFL
UNFL
DZ
INEX2
INEX1
Accrued Exception Byte:
MOTOROLA
Cleared
Refer to 1.6.5 Not-A-Numbers.
Set if the source is ± infinity; cleared
otherwise.
Cleared
Cleared
Cleared
Cleared
If < fmt > is packed, refer to inexact result on
decimal input in the appropriate user’s
manual; cleared otherwise.
Affected as described in IEEE exception and trap compatibility in the appropriate user’s manual.
M68000 FAMILY PROGRAMMER’S REFERENCE MANUAL
5-49
Floating Point Instructions
FGETMAN
FGETMAN
Get Mantissa
(MC6888X, M68040FPSP)
Instruction Format:
15
14
13
1
1
1
0
R/M
0
12
1
11
9
8
7
6
COPROCESSOR
ID
10
0
0
0
SOURCE
SPECIFIER
DESTINATION
REGISTER
0
5
4
3
2
1
0
EFFECTIVE ADDRESS
MODE
REGISTER
0
1
1
1
1
1
Instruction Fields:
Coprocessor ID field—Specifies which coprocessor in the system is to execute this
instruction. Motorola assemblers default to ID = 1 for the floating-point
coprocessor.
Effective Address field—Determines the addressing mode for external operands.
If R/M = 0, this field is unused and should be all zeros.
If R/M = 1, this field is encoded with an M68000 family addressing mode as listed in
the following table:
Addressing Mode
Mode
Register
Addressing Mode
Mode
Register
Dn*
000
reg. number:Dn
(xxx).W
111
000
An
—
—
(xxx).L
111
001
(An)
010
reg. number:An
# < data >
111
100
(An) +
011
reg. number:An
– (An)
100
reg. number:An
(d16,An)
101
reg. number:An
(d16,PC)
111
010
(d8,An,Xn)
110
reg. number:An
(d8,PC,Xn)
111
011
(bd,An,Xn)
110
reg. number:An
(bd,PC,Xn)
111
011
([bd,An,Xn],od)
110
reg. number:An
([bd,PC,Xn],od)
111
011
([bd,An],Xn,od)
110
reg. number:An
([bd,PC],Xn,od)
111
011
*Only if < fmt > is byte, word, long, or single.
R/M field—Specifies the source operand address mode.
0 — The operation is register to register.
1 — The operation is < ea > to register.
5-50
M68000 FAMILY PROGRAMMER’S REFERENCE MANUAL
MOTOROLA
Floating Point Instructions
FGETMAN
Get Mantissa
(MC6888X, M68040FPSP)
FGETMAN
Source Specifier field—Specifies the source register or data format.
If R/M = 0, specifies the source floating-point data register.
If R/M = 1, specifies the source data format:
000 — Long-Word Integer (L)
001 — Single-Precision Real (S)
010 — Extended-Precision Real (X)
011 — Packed-Decimal Real (P)
100 — Word Integer (W)
101 — Double-Precision Real (D)
110 — Byte Integer (B)
Destination Register field—Specifies the destination floating- point data register. If R/
M = 0 and the source and destination fields are equal, then the input operand is
taken from the specified floating-point data register, and the result is written into
the same register. If the single register syntax is used, Motorola assemblers set
the source and destination fields to the same value.
MOTOROLA
M68000 FAMILY PROGRAMMER’S REFERENCE MANUAL
5-51
Floating Point Instructions
FINT
FINT
Integer Part
(MC6888X, M68040FPSP)
Operation:
Integer Part of Source → FPn
Assembler
Syntax:
FINT. < fmt > < ea > ,FPn
FINT.X FPm,FPn
FINT.X FPn
Attributes:
Format = (Byte, Word, Long, Single, Double, Extended, Packed)
Description: Converts the source operand to extended precision (if necessary), extracts
the integer part, and converts it to an extended-precision floating-point number. Stores
the result in the destination floating-point data register. The integer part is extracted by
rounding the extended-precision number to an integer using the current rounding mode
selected in the floating-point control register mode control byte. Thus, the integer part
returned is the number that is to the left of the radix point when the exponent is zero,
after rounding. For example, the integer part of 137.57 is 137.0 for the round-to-zero
and round-to- negative infinity modes and 138.0 for the round-to-nearest and round-topositive infinity modes. Note that the result of this operation is a floating-point number.
Operation Table:
DESTINATION
Result
+
In Range
Integer
– +
+ 0.0
SOURCE
Zero
– +
– 0.0
Infinity
–
+ inf – inf
NOTE: If the source operand is a NAN, refer to 1.6.5 Not-A-Numbers for more information.
5-52
M68000 FAMILY PROGRAMMER’S REFERENCE MANUAL
MOTOROLA
Floating Point Instructions
FINT
FINT
Integer Part
(MC6888X, M68040FPSP)
Floating-Point Status Register:
Condition Codes:
Affected as described in 3.6.2 Conditional Testing.
Quotient Byte:
Not affected.
Exception Byte:
BSUN
SNAN
OPERR
OVFL
UNFL
DZ
INEX2
Cleared
Refer to 1.6.5 Not-A-Numbers.
Cleared
Cleared
Cleared
Cleared
Refer to inexact result in the appropriate
user’s manual.
If < fmt > is packed, refer to inexact result on
decimal input in the appropriate user’s
manual; cleared otherwise.
INEX1
Accrued Exception Byte:
Affected as described in IEEE exception and trap compatibility in the appropriate user’s manual.
Instruction Format:
15
14
13
1
1
1
0
R/M
0
12
1
11
9
8
7
6
COPROCESSOR
ID
0
0
0
SOURCE
SPECIFIER
10
DESTINATION
REGISTER
0
5
0
4
3
2
1
0
EFFECTIVE ADDRESS
MODE
REGISTER
0
0
0
0
1
Instruction Fields:
Coprocessor ID field—Specifies which coprocessor in the system is to execute this
instruction. Motorola assemblers default to ID = 1 for the floating-point
coprocessor.
MOTOROLA
M68000 FAMILY PROGRAMMER’S REFERENCE MANUAL
5-53
Floating Point Instructions
FINT
FINT
Integer Part
(MC6888X, M68040FPSP)
Effective Address field—Determines the addressing mode for external operands.
If R/M = 0, this field is unused and should be all zeros.
If R/M = 1, this field is encoded with an M68000 family addressing mode as listed in
the following table:
Addressing Mode
Mode
Register
Addressing Mode
Mode
Register
Dn*
000
reg. number:Dn
(xxx).W
111
000
An
—
—
(xxx).L
111
001
(An)
010
reg. number:An
# < data >
111
100
(An) +
011
reg. number:An
– (An)
100
reg. number:An
(d16,An)
101
reg. number:An
(d16,PC)
111
010
(d8,An,Xn)
110
reg. number:An
(d8,PC,Xn)
111
011
(bd,An,Xn)
110
reg. number:An
(bd,PC,Xn)
111
011
([bd,An,Xn],od)
110
reg. number:An
([bd,PC,Xn],od)
111
011
([bd,An],Xn,od)
110
reg. number:An
([bd,PC],Xn,od)
111
011
*Only if < fmt > is byte, word, long, or single.
R/M field—Specifies the source operand address mode.
0 — The operation is register to register.
1 — The operation is < ea > to register.
Source Specifier field—Specifies the source register or data format.
If R/M = 0, specifies the source floating-point data register.
If R/M = 1, specifies the source data format:
000 — Long-Word Integer (L)
001 — Single-Precision Real (S)
010 — Extended-Precision Real (X)
011 — Packed-Decimal Real (P)
100 — Word Integer (W)
101 — Double-Precision Real (D)
110 — Byte Integer (B)
Destination Register field—Specifies the destination floating- point data register. If R/
M = 0 and the source and destination fields are equal, then the input operand is
taken from the specified floating-point data register, and the result is written into
the same register. If the single register syntax is used, Motorola assemblers set
the source and destination fields to the same value.
5-54
M68000 FAMILY PROGRAMMER’S REFERENCE MANUAL
MOTOROLA
Floating Point Instructions
FINTRZ
FINTRZ
Integer Part, Round-to-Zero
(MC6888X, M68040FPSP)
Operation:
Integer Part of Source → FPn
Assembler
Syntax:
FINTRZ. < fmt > < ea > ,FPn
FINTRZ.X FPm,FPn
FINTRZ.X FPn
Attributes:
Format = (Byte, Word, Long, Single, Double, Extended, Packed)
Description: Converts the source operand to extended precision (if necessary) and
extracts the integer part and converts it to an extended-precision floating-point number.
Stores the result in the destination floating-point data register. The integer part is
extracted by rounding the extended-precision number to an integer using the round-tozero mode, regardless of the rounding mode selected in the floating-point control
register mode control byte (making it useful for FORTRAN assignments). Thus, the
integer part returned is the number that is to the left of the radix point when the
exponent is zero. For example, the integer part of 137.57 is 137.0; the integer part of
0.1245 x 102 is 12.0. Note that the result of this operation is a floating-point number.
Operation Table:
DESTINATION
Result
+
In Range
Integer, Forced
Round-to- Zero
– +
+ 0.0
SOURCE
Zero
– +
– 0.0 + inf
Infinity
–
– inf
NOTE: If the source operand is a NAN, refer to 1.6.5 Not-A-Numbers for more information.
MOTOROLA
M68000 FAMILY PROGRAMMER’S REFERENCE MANUAL
5-55
Floating Point Instructions
FINTRZ
FINTRZ
Integer Part, Round-to-Zero
(MC6888X, M68040FPSP)
Floating-Point Status Register:
Condition Codes:
Affected as described in 3.6.2 Conditional Testing.
Quotient Byte:
Not affected.
Exception Byte:
BSUN
SNAN
OPERR
OVFL
UNFL
DZ
INEX2
Cleared
Refer to 1.6.5 Not-A-Numbers.
Cleared
Cleared
Cleared
Cleared
Refer to inexact result in the appropriate
user’s manual.
If < fmt > is packed, refer to inexact result on
decimal input in the appropriate user’s
manual; cleared otherwise.
INEX1
Accrued Exception Byte:
Affected as described in IEEE exception and trap compatibility in the appropriate user’s manual.
Instruction Format:
15
14
13
1
1
1
0
R/M
0
12
1
11
9
8
7
6
COPROCESSOR
ID
0
0
0
SOURCE
SPECIFIER
10
DESTINATION
REGISTER
0
5
0
4
3
2
1
0
EFFECTIVE ADDRESS
MODE
REGISTER
0
0
0
1
1
Instruction Fields:
Coprocessor ID field—Specifies which coprocessor in the system is to execute this
instruction. Motorola assemblers default to ID = 1 for the floating-point
coprocessor.
5-56
M68000 FAMILY PROGRAMMER’S REFERENCE MANUAL
MOTOROLA
Floating Point Instructions
FINTRZ
FINTRZ
Integer Part, Round-to-Zero
(MC6888X, M68040FPSP)
Effective Address field—Determines the addressing mode for external operands.
If R/M = 0, this field is unused and should be all zeros.
If R/M = 1, this field is encoded with an M68000 family addressing mode as listed in
the following table:
Addressing Mode
Mode
Register
Addressing Mode
Mode
Register
Dn*
000
reg. number:Dn
(xxx).W
111
000
An
—
—
(xxx).L
111
001
(An)
010
reg. number:An
# < data >
111
100
(An) +
011
reg. number:An
– (An)
100
reg. number:An
(d16,An)
101
reg. number:An
(d16,PC)
111
010
(d8,An,Xn)
110
reg. number:An
(d8,PC,Xn)
111
011
(bd,An,Xn)
110
reg. number:An
(bd,PC,Xn)
111
011
([bd,An,Xn],od)
110
reg. number:An
([bd,PC,Xn],od)
111
011
([bd,An],Xn,od)
110
reg. number:An
([bd,PC],Xn,od)
111
011
*Only if < fmt > is byte, word, long, or single.
R/M field—Specifies the source operand address mode.
0 — The operation is register to register.
1 — The operation is < ea > to register.
Source Specifier field—Specifies the source register or data format.
If R/M = 0, specifies the source floating-point data register.
If RM = 1, specifies the source data format:
000 — Long-Word Integer (L)
001 — Single-Precision Real (S)
010 — Extended-Precision Real (X)
011 — Packed-Decimal Real (P)
100 — Word Integer (W)
101 — Double-Precision Real (D)
110 — Byte Integer (B)
Destination Register field—Specifies the destination floating- point data register. If R/
M = 0 and the source and destination fields are equal, then the input operand is
taken from the specified floating-point data register, and the result is written into
the same register. If the single register syntax is used, Motorola assemblers set
the source and destination fields to the same value.
MOTOROLA
M68000 FAMILY PROGRAMMER’S REFERENCE MANUAL
5-57
Floating Point Instructions
FLOG10
FLOG10
Log10
(MC6888X, M68040FPSP)
Operation:
Log10 of Source → FPn
Assembler
Syntax:
FLOG10. < fmt > < ea > ,FPn
FLOG10.X FPm,FPn
FLOG10.X FPn
Attributes:
Format = (Byte, Word, Long, Single, Double, Extended, Packed)
Description: Convert the source operand to extended precision (if necessary) and
calculates the logarithm of that number using base 10 arithmetic. Stores the result in
the destination floating-point data register. This function is not defined for input values
less than zero.
Operation Table:
DESTINATION
+
In Range
NAN2
Log10
Result
– +
SOURCE1
Zero
–
inf3
– +
+ inf
Infinity
–
NAN2
NOTES:
1. If the source operand is a NAN, refer to 1.6.5 Not-A-Numbers for more information.
2. Sets the OPERR bit in the floating-point status register exception byte.
3. Sets the DZ bit in the floating-point status register exception byte.
Floating-Point Status Register:
Condition Codes:
Affected as described in 3.6.2 Conditional Testing.
Quotient Byte:
Not affected.
Exception Byte:
BSUN
SNAN
OPERR
OVFL
UNFL
DZ
INEX2
INEX1
Accrued Exception Byte:
5-58
Cleared
Refer to 1.6.5 Not-A-Numbers.
Set if the source operand is < 0; cleared
otherwise.
Cleared
Cleared
Set if the source is ± 0; cleared otherwise
Refer to inexact result in the appropriate
user’s manual.
If < fmt > is packed, refer to inexact result on
decimal input in the appropriate user’s
manual; cleared otherwise.
Affected as described in IEEE exception and trap compatibility in the appropriate user’s manual.
M68000 FAMILY PROGRAMMER’S REFERENCE MANUAL
MOTOROLA
Floating Point Instructions
FLOG10
FLOG10
Log10
(MC6888X, M68040FPSP)
Instruction Format:
15
14
13
1
1
1
0
R/M
0
12
1
11
9
8
7
6
COPROCESSOR
ID
10
0
0
0
SOURCE
SPECIFIER
DESTINATION
REGISTER
0
5
0
4
3
2
1
0
EFFECTIVE ADDRESS
MODE
REGISTER
1
0
1
0
1
Instruction Fields:
Coprocessor ID field—Specifies which coprocessor in the system is to execute this
instruction. Motorola assemblers default to ID = 1 for the floating-point
coprocessor.
Effective Address field—Determines the addressing mode for external operands.
If R/M = 0, this field is unused and should be all zeros.
If R/M = 1, this field is encoded with an M68000 family addressing mode as listed in
the following table:
Addressing Mode
Mode
Register
Addressing Mode
Mode
Register
Dn*
000
reg. number:Dn
(xxx).W
111
000
An
—
—
(xxx).L
111
001
(An)
010
reg. number:An
# < data >
111
100
(An) +
011
reg. number:An
– (An)
100
reg. number:An
(d16,An)
101
reg. number:An
(d16,PC)
111
010
(d8,An,Xn)
110
reg. number:An
(d8,PC,Xn)
111
011
(bd,An,Xn)
110
reg. number:An
(bd,PC,Xn)
111
011
([bd,An,Xn],od)
110
reg. number:An
([bd,PC,Xn],od)
111
011
([bd,An],Xn,od)
110
reg. number:An
([bd,PC],Xn,od)
111
011
*Only if < fmt > is byte, word, long, or single.
MOTOROLA
M68000 FAMILY PROGRAMMER’S REFERENCE MANUAL
5-59
Floating Point Instructions
FLOG10
Log10
(MC6888X, M68040FPSP)
FLOG10
R/M field—Specifies the source operand address mode.
0 — The operation is register to register.
1 — The operation is < ea > to register.
Source Specifier field—Specifies the source register or data format.
If R/M = 0, specifies the source floating-point data register.
If R/M = 1, specifies the source data format:
000 — Long-Word Integer (L)
001 — Single-Precision Real (S)
010 — Extended-Precision Real (X)
011 — Packed-Decimal Real (P)
100 — Word Integer (W)
101 — Double-Precision Real (D)
110 — Byte Integer (B)
Destination Register field—Specifies the destination floating- point data register. If R/
M = 0 and the source and destination fields are equal, then the input operand is
taken from the specified floating-point data register, and the result is written into
the same register. If the single register syntax is used, Motorola assemblers set
the source and destination fields to the same value.
5-60
M68000 FAMILY PROGRAMMER’S REFERENCE MANUAL
MOTOROLA
Floating Point Instructions
FLOG2
FLOG2
Log2
(MC6888X, M68040FPSP)
Operation:
Log2 of Source → FPn
Assembler
Syntax:
FLOG2. < fmt > < ea > ,FPn
FLOG2.X FPm,FPn
FLOG2.X FPn
Attributes:
Format = (Byte, Word, Long, Single, Double, Extended, Packed)
Description: Converts the source operand to extended precision (if necessary) and
calculates the logarithm of that number using base two arithmetic. Stores the result in
the destination floating- point data register. This function is not defined for input values
less than zero.
Operation Table:
DESTINATION
+
In Range
NAN2
Log2
Result
– +
SOURCE1
Zero
–
inf3
– +
+ inf
Infinity
–
NAN2
NOTES:
1. If the source operand is a NAN, refer to 1.6.5 Not-A-Numbers for more information.
2. Sets the OPERR bit in the floating-point status register exception byte.
3. Sets the DZ bit in the floating-point status register exception byte.
Floating-Point Status Register:
Condition Codes:
Affected as described in 3.6.2 Conditional Testing.
Quotient Byte:
Not affected.
Exception Byte:
BSUN
SNAN
OPERR
OVFL
UNFL
DZ
INEX2
INEX1
Accrued Exception Byte:
MOTOROLA
Cleared
Refer to 1.6.5 Not-A-Numbers.
Set if the source is < 0; cleared otherwise
Cleared
Cleared
Set if the source is ± 0; cleared otherwise
Refer to inexact result in the appropriate
user’s manual.
If < fmt > is packed, refer to inexact result on
decimal input in the appropriate user’s
manual; cleared otherwise.
Affected as described in IEEE exception and trap compatibility in the appropriate user’s manual.
M68000 FAMILY PROGRAMMER’S REFERENCE MANUAL
5-61
Floating Point Instructions
FLOG2
FLOG2
Log2
(MC6888X, M68040FPSP)
Instruction Format:
15
14
13
1
1
1
0
R/M
0
12
1
11
9
8
7
6
COPROCESSOR
ID
10
0
0
0
SOURCE
SPECIFIER
DESTINATION
REGISTER
0
5
0
4
3
2
1
0
EFFECTIVE ADDRESS
MODE
REGISTER
1
0
1
1
0
Instruction Fields:
Coprocessor ID field—Specifies which coprocessor in the system is to execute this
instruction. Motorola assemblers default to ID = 1 for the floating-point
coprocessor.
Effective Address field—Determines the addressing mode for external operands.
If R/M = 0, this field is unused and should be all zeros.
If R/M = 1, this field is encoded with an M68000 family addressing mode as listed in
the following table:
Addressing Mode
Mode
Register
Addressing Mode
Mode
Register
Dn*
000
reg. number:Dn
(xxx).W
111
000
An
—
—
(xxx).L
111
001
(An)
010
reg. number:An
# < data >
111
100
(An) +
011
reg. number:An
– (An)
100
reg. number:An
(d16,An)
101
reg. number:An
(d16,PC)
111
010
(d8,An,Xn)
110
reg. number:An
(d8,PC,Xn)
111
011
(bd,An,Xn)
110
reg. number:An
(bd,PC,Xn)
111
011
([bd,An,Xn],od)
110
reg. number:An
([bd,PC,Xn],od)
111
011
([bd,An],Xn,od)
110
reg. number:An
([bd,PC],Xn,od)
111
011
*Only if < fmt > is byte, word, long, or single.
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M68000 FAMILY PROGRAMMER’S REFERENCE MANUAL
MOTOROLA
Floating Point Instructions
FLOG2
Log2
(MC6888X, M68040FPSP)
FLOG2
R/M field—Specifies the source operand address mode.
0 — The operation is register to register.
1 — The operation is < ea > to register.
Source Specifier field—Specifies the source register or data format.
If R/M = 0, specifies the source floating-point data register.
If R/M = 1, specifies the source data format:
000 — Long-Word Integer (L)
001 — Single-Precision Real (S)
010 — Extended-Precision Real (X)
011 — Packed-Decimal Real (P)
100 — Word Integer (W)
101 — Double-Precision Real (D)
110 — Byte Integer (B)
Destination Register field—Specifies the destination floating- point data register. If R/
M = 0 and the source and destination fields are equal, then the input operand is
taken from the specified floating-point data register, and the result is written into
the same register. If the single register syntax is used, Motorola assemblers set
the source and destination fields to the same value.
MOTOROLA
M68000 FAMILY PROGRAMMER’S REFERENCE MANUAL
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Floating Point Instructions
FLOGN
FLOGN
Loge
(MC6888X, M68040FPSP)
Operation:
Loge of Source → FPn
Assembler
Syntax:
FLOGN. < fmt > < ea > ,FPn
FLOGN.X FPm,FPn
FLOGN.X FPn
Attributes:
Format = (Byte, Word, Long, Single, Double, Extended, Packed)
Description: Converts the source operand to extended precision (if necessary) and
calculates the natural logarithm of that number. Stores the result in the destination
floating-point data register. This function is not defined for input values less than zero.
Operation Table:
DESTINATION
Result
+
In Range
– +
NAN2
In(x)
SOURCE1
Zero
–
inf3
– +
+ inf
Infinity
–
NAN2
NOTES:
1. If the source operand is a NAN, refer to 1.6.5 Not-A-Numbers for more information.
2. Sets the OPERR bit in the floating-point status register exception byte.
3. Sets the DZ bit in the floating-point status register exception byte.
Floating-Point Status Register:
Condition Codes:
Affected as described in 3.6.2 Conditional Testing.
Quotient Byte:
Not affected.
Exception Byte:
BSUN
SNAN
OPERR
OVFL
UNFL
DZ
INEX2
INEX1
Accrued Exception Byte:
5-64
Cleared
Refer to 1.6.5 Not-A-Numbers.
Set if the source operand is < 0; cleared
otherwise.
Cleared
Cleared
Set if the source is ± 0; cleared otherwise
Refer to inexact result in the appropriate
user’s manual.
If < fmt > is packed, refer to inexact result on
decimal input in the appropriate user’s
manual; cleared otherwise.
Affected as described in IEEE exception and trap compatibility in the appropriate user’s manual.
M68000 FAMILY PROGRAMMER’S REFERENCE MANUAL
MOTOROLA
Floating Point Instructions
FLOGN
FLOGN
Loge
(MC6888X, M68040FPSP)
Instruction Format:
15
14
13
1
1
1
0
R/M
0
12
1
11
9
8
7
6
COPROCESSOR
ID
10
0
0
0
SOURCE
SPECIFIER
DESTINATION
REGISTER
0
5
0
4
3
2
1
0
EFFECTIVE ADDRESS
MODE
REGISTER
1
0
1
0
0
Instruction Fields:
Coprocessor ID field—Specifies which coprocessor in the system is to execute this
instruction. Motorola assemblers default to ID = 1 for the floating-point
coprocessor.
Effective Address field—Determines the addressing mode for external operands.
If R/M = 0, this field is unused and should be all zeros.
If R/M = 1, this field is encoded with an M68000 family addressing mode as listed in
the following table:
Addressing Mode
Mode
Register
Addressing Mode
Mode
Register
Dn*
000
reg. number:Dn
(xxx).W
111
000
An
—
—
(xxx).L
111
001
(An)
010
reg. number:An
# < data >
111
100
(An) +
011
reg. number:An
– (An)
100
reg. number:An
(d16,An)
101
reg. number:An
(d16,PC)
111
010
(d8,An,Xn)
110
reg. number:An
(d8,PC,Xn)
111
011
(bd,An,Xn)
110
reg. number:An
(bd,PC,Xn)
111
011
([bd,An,Xn],od)
110
reg. number:An
([bd,PC,Xn],od)
111
011
([bd,An],Xn,od)
110
reg. number:An
([bd,PC],Xn,od)
111
011
*Only if < fmt > is byte, word, long, or single.
MOTOROLA
M68000 FAMILY PROGRAMMER’S REFERENCE MANUAL
5-65
Floating Point Instructions
FLOGN
Loge
(MC6888X, M68040FPSP)
FLOGN
R/M field—Specifies the source operand address mode.
0 — The operation is register to register.
1 — The operation is < ea > to register.
Source Specifier field—Specifies the source register or data format.
If R/M = 0, specifies the source floating-point data register.
If R/M = 1, specifies the source data format:
000 — Long-Word Integer (L)
001 — Single-Precision Real (S)
010 — Extended-Precision Real (X)
011 — Packed-Decimal Real (P)
100 — Word Integer (W)
101 — Double-Precision Real (D)
110 — Byte Integer (B)
Destination Register field—Specifies the destination floating- point data register. If R/
M = 0 and the source and destination fields are equal, then the input operand is
taken from the specified floating-point data register, and the result is written into
the same register. If the single register syntax is used, Motorola assemblers set
the source and destination fields to the same value.
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M68000 FAMILY PROGRAMMER’S REFERENCE MANUAL
MOTOROLA
Floating Point Instructions
FLOGNP1
FLOGNP1
Loge (x + 1)
(MC6888X, M68040FPSP)
Operation:
Loge of (Source + 1) → FPn
Assembler
Syntax:
FLOGNP1. < fmt > < ea > ,FPn
FLOGNP1.X FPm,FPn
FLOGNP1.X FPn
Attributes:
Format = (Byte, Word, Long, Single, Double, Extended, Packed)
Description: Converts the source operand to extended precision (if necessary), adds one
to that value, and calculates the natural logarithm of that intermediate result. Stores the
result in the destination floating-point data register. This function is not defined for input
values less than – 1.
Operation Table:
DESTINATION
Result
+
In Range
In(x + 1)
In(x +
– +
1)2
+ 0.0
SOURCE1
Zero
– +
– 0.0 + inf
Infinity
–
NAN23
NOTES:
1. If the source operand is a NAN, refer to 1.6.5 Not-A-Numbers for more information.
2. If the source is – 1, sets the DZ bit in the floating-point status register
exception byte and returns a NAN. If the source is < – 1, sets the OPERR bit
in the floating-point status register exception byte and returns a NAN.
3. Sets the OPERR bit in the floating-point status register exception byte.
Floating-Point Status Register:
Condition Codes:
Affected as described in 3.6.2 Conditional Testing.
Quotient Byte:
Not affected.
MOTOROLA
M68000 FAMILY PROGRAMMER’S REFERENCE MANUAL
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Floating Point Instructions
FLOGNP1
FLOGNP1
Loge (x + 1)
(MC6888X, M68040FPSP)
Exception Byte:
BSUN
SNAN
OPERR
Cleared
Refer to 1.6.5 Not-A-Numbers.
Set if the source operand is < – 1; cleared
otherwise.
Cleared
Refer to underflow in the appropriate user’s
manual.
Set if the source operand is – 1; cleared
otherwise
Refer to inexact result in the appropriate
user’s manual.
If < fmt > is packed, refer to inexact result on
decimal input in the appropriate user’s
manual; cleared otherwise.
OVFL
UNFL
DZ
INEX2
INEX1
Accrued Exception Byte:
Affected as described in IEEE exception and trap compatibility in the appropriate user’s manual.
Instruction Format:
15
14
13
1
1
1
0
R/M
0
12
1
11
9
8
7
6
COPROCESSOR
ID
0
0
0
SOURCE
SPECIFIER
10
DESTINATION
REGISTER
0
5
0
4
3
2
1
0
EFFECTIVE ADDRESS
MODE
REGISTER
0
0
1
1
0
Instruction Fields:
Coprocessor ID field—Specifies which coprocessor in the system is to execute this
instruction. Motorola assemblers default to ID = 1 for the floating-point
coprocessor.
5-68
M68000 FAMILY PROGRAMMER’S REFERENCE MANUAL
MOTOROLA
Floating Point Instructions
FLOGNP1
FLOGNP1
Loge (x + 1)
(MC6888X, M68040FPSP)
Effective Address field—Determines the addressing mode for external operands.
If R/M = 0, this field is unused and should be all zeros.
If R/M = 1, this field is encoded with an M68000 family addressing mode as listed in
the following table:
Addressing Mode
Mode
Register
Addressing Mode
Mode
Register
Dn*
000
reg. number:Dn
(xxx).W
111
000
An
—
—
(xxx).L
111
001
(An)
010
reg. number:An
# < data >
111
100
(An) +
011
reg. number:An
– (An)
100
reg. number:An
(d16,An)
101
reg. number:An
(d16,PC)
111
010
(d8,An,Xn)
110
reg. number:An
(d8,PC,Xn)
111
011
(bd,An,Xn)
110
reg. number:An
(bd,PC,Xn)
111
011
([bd,An,Xn],od)
110
reg. number:An
([bd,PC,Xn],od)
111
011
([bd,An],Xn,od)
110
reg. number:An
([bd,PC],Xn,od)
111
011
*Only if < fmt > is byte, word, long, or single.
R/M field—Specifies the source operand address mode.
0 — The operation is register to register.
1 — The operation is < ea > to register.
Source Specifier field—Specifies the source register or data format.
If R/M = 0, specifies the source floating-point data register.
If R/M = 1, specifies the source data format:
000 — Long-Word Integer (L)
001 — Single-Precision Real (S)
010 — Extended-Precision Real (X)
011 — Packed-Decimal Real (P)
100 — Word Integer (W)
101 — Double-Precision Real (D)
110 — Byte Integer (B)
Destination Register field—Specifies the destination floating- point data register. If R/
M = 0 and the source and destination fields are equal, then the input operand is
taken from the specified floating-point data register, and the result is written into
the same register. If the single register syntax is used, Motorola assemblers set
the source and destination fields to the same value.
MOTOROLA
M68000 FAMILY PROGRAMMER’S REFERENCE MANUAL
5-69
Floating Point Instructions
FMOD
FMOD
Modulo Remainder
(MC6888X, M68040FPSP)
Operation:
Modulo Remainder of (FPn ÷ Source) → FPn
Assembler
Syntax:
FMOD. < fmt > < ea > ,FPn
FMOD.X FPm,FPn
Attributes:
Format = (Byte, Word, Long, Single, Double, Extended, Packed)
Description: Converts the source operand to extended precision (if necessary) and
calculates the modulo remainder of the number in the destination floating-point data
register, using the source operand as the modulus. Stores the result in the destination
floating-point data register and stores the sign and seven least significant bits of the
quotient in the floating-point status register quotient byte (the quotient is the result of
FPn ÷ Source). The modulo remainder function is defined as:
FPn – (Source x N)
where N = INT(FPn ÷ Source) in the round-to-zero mode.
The FMOD function is not defined for a source operand equal to zero or for a destination
operand equal to infinity. Note that this function is not the same as the FREM instruction,
which uses the round-to-nearest mode and thus returns the remainder that is required by
the IEEE Specification for Binary Floating-Point Arithmetic.
Operation Table:
DESTINATION
+
In Range
– +
SOURCE1
Zero#
– +
Infinity
In Range
+
–
Modulo Remainder
NAN2
FPn3
Zero
+
–
+ 0.0
– 0.0
NAN2
+ 0.0
– 0.0
Infinity
+
–
NAN2
NAN2
NAN2
–
NOTES:
1. If the source operand is a NAN, refer to 1.6.5 Not-A-Numbers for more information.
2. Sets the OPERR bit in the floating-point status register exception byte.
3. Returns the value of FPn before the operation. However, the result is
processed by the normal instruction termination procedure to round it as
required. Thus, an overflow and/or inexact result may occur if the rounding
precision has been changed to a smaller size since the FPn value was
loaded
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M68000 FAMILY PROGRAMMER’S REFERENCE MANUAL
MOTOROLA
Floating Point Instructions
FMOD
FMOD
Modulo Remainder
(MC6888X, M68040FPSP)
Floating-Point Status Register:
Condition Codes:
Affected as described in 3.6.2 Conditional Testing.
Quotient Byte:
Loaded with the sign and least significant seven bits of the
quotient (FPn ÷ Source). The sign of the quotient is the
exclusive-OR of the sign bits of the source and destination
operands.
Exception Byte:
BSUN
SNAN
OPERR
Cleared
Refer to 1.6.5 Not-A-Numbers.
Set if the source is zero or the destination is
infinity; cleared otherwise.
Cleared
Refer to underflow in the appropriate user’s
manual.
Cleared
Refer to inexact result in the appropriate
user’s manual.
If < fmt > is packed, in the appropriate user’s
manual for inexact result on decimal input;
cleared otherwise.
OVFL
UNFL
DZ
INEX2
INEX1
Accrued Exception Byte:
Affected as described in IEEE exception and trap compatibility in the appropriate user’s manual.
Instruction Format:
15
14
13
1
1
1
0
R/M
0
12
1
11
9
8
7
6
COPROCESSOR
ID
0
0
0
SOURCE
SPECIFIER
10
DESTINATION
REGISTER
0
5
1
4
3
2
1
0
EFFECTIVE ADDRESS
MODE
REGISTER
0
1
1
0
1
Instruction Fields:
Coprocessor ID field—Specifies which coprocessor in the system is to execute this
instruction. Motorola assemblers default to ID = 1 for the floating-point
coprocessor.
MOTOROLA
M68000 FAMILY PROGRAMMER’S REFERENCE MANUAL
5-71
Floating Point Instructions
FMOD
FMOD
Modulo Remainder
(MC6888X, M68040FPSP)
Effective Address field—Determines the addressing mode for external operands.
If R/M = 0, this field is unused and should be all zeros.
If R/M = 1, this field is encoded with an M68000 family addressing mode as listed in
the following table:
Addressing Mode
Mode
Register
Addressing Mode
Mode
Register
Dn
000
reg. number:Dn
(xxx).W
111
000
An
—
—
(xxx).L
111
001
(An)
010
reg. number:An
# < data >
111
100
(An) +
011
reg. number:An
– (An)
100
reg. number:An
(d16,An)
101
reg. number:An
(d16,PC)
111
010
(d8,An,Xn)
110
reg. number:An
(d8,PC,Xn)
111
011
(bd,An,Xn)
110
reg. number:An
(bd,PC,Xn)
111
011
([bd,An,Xn],od)
110
reg. number:An
([bd,PC,Xn],od)
111
011
([bd,An],Xn,od)
110
reg. number:An
([bd,PC],Xn,od)
111
011
*Only if < fmt > is byte, word, long, or single.
R/M field—Specifies the source operand address mode.
0 — The operation is register to register.
1 — The operation is < ea > to register.
Source Specifier field—Specifies the source register or data format.
If R/M = 0, specifies the source floating-point data register.
If R/M = 1, specifies the source data format:
000 — Long-Word Integer (L)
001 — Single-Precision Real (S)
010 — Extended-Precision Real (X)
011 — Packed-Decimal Real (P)
100 — Word Integer (W)
101 — Double-Precision Real (D)
110 — Byte Integer (B)
Destination Register field—Specifies the destination floating- point data register.
5-72
M68000 FAMILY PROGRAMMER’S REFERENCE MANUAL
MOTOROLA
Floating Point Instructions
FMOVE
Move Floating-Point Data Register
(MC6888X, MC68040)
Operation:
Source → Destination
Assembler
Syntax:
FMOVE. < fmt > < ea > ,FPn
FMOVE. < fmt > FPm, < ea >
FMOVE.P FPm, < ea > {Dn}
FMOVE.P FPm, < ea > {k}
*FrMOVE. < fmt > < ea > ,FPn
where r is rounding precision, S or D
FMOVE
*Supported by MC68040 only
Attributes:
Format = (Byte, Word, Long, Single, Double, Extended, Packed)
Description: Moves the contents of the source operand to the destination operand.
Although the primary function of this instruction is data movement, it is also considered
an arithmetic instruction since conversions from the source operand format to the
destination operand format are performed implicitly during the move operation. Also,
the source operand is rounded according to the selected rounding precision and mode.
Unlike the MOVE instruction, the FMOVE instruction does not support a memory-tomemory format. For such transfers, it is much faster to utilize the MOVE instruction to
transfer the floating- point data than to use the FMOVE instruction. The FMOVE
instruction only supports memory-to-register, register-to- register, and register-tomemory operations (in this context, memory may refer to an integer data register if the
data format is byte, word, long, or single). The memory-to-register and register- to-register operation uses a command word encoding distinctly different from that used by
the register-to-memory operation; these two operation classes are described separately.
Memory-to-Register and Register-to-Register Operation: Converts the source operand
to an extended-precision floating-point number (if necessary) and stores it in the
destination floating-point data register. MOVE will round the result to the precision
selected in the floating-point control register. FSMOVE and FDMOVE will round the
result to single or double precision, respectively, regardless of the rounding precision
selected in the floating-point control register. Depending on the source data format and
the rounding precision, some operations may produce an inexact result. In the following
table, combinations that can produce an inexact result are marked with a dot (⋅), but all
other combinations produce an exact result.
MOTOROLA
M68000 FAMILY PROGRAMMER’S REFERENCE MANUAL
5-73
Floating Point Instructions
FMOVE
FMOVE
Move Floating-Point Data Register
(MC6888X, MC68040)
Rounding
Precision
Source Format
B
W
L
S
⋅
Single
Double
D
X
P
⋅
⋅
⋅
⋅
⋅
⋅
Extended
Floating-Point Status Register ( < ea > to Register):
Condition Codes:
Affected as described in 3.6.2 Conditional Testing.
Quotient Byte:
Not affected.
Exception Byte:
BSUN
SNAN
OPERR
OVFL
UNFL
DZ
INEX2
INEX1
Accrued Exception Byte:
5-74
Cleared
Refer to 1.6.5 Not-A-Numbers.
Cleared
Cleared
Refer to exception processing in the
appropriate user’s manual if the source is an
extended-precision denormalized number;
cleared otherwise.
Cleared
Refer to exception processing in the
appropriate user’s manual if < fmt > is L,D, or
X; cleared otherwise.
Refer to exception processing in the
appropriate user’s manual if < fmt > is P;
cleared otherwise.
Affected as described in exception processing in the appropriate user’s manual.
M68000 FAMILY PROGRAMMER’S REFERENCE MANUAL
MOTOROLA
Floating Point Instructions
FMOVE
FMOVE
Move Floating-Point Data Register
(MC6888X, MC68040)
Instruction Format:
< EA > TO REGISTER
15
14
13
1
1
1
0
R/M
0
12
1
11
9
8
7
6
COPROCESSOR
ID
10
0
0
0
SOURCE
SPECIFIER
5
4
3
2
1
0
EFFECTIVE ADDRESS
MODE
REGISTER
DESTINATION
REGISTER
OPMODE
Instruction Fields:
Effective Address field—Determines the addressing mode for external operands.
If R/M = 0, this field is unused and should be all zeros.
If R/M = 1, specifies the location of the source operand. Only data addressing modes
can be used as listed in the following table:
Addressing Mode
Mode
Register
Addressing Mode
Mode
Register
Dn*
000
reg. number:Dn
(xxx).W
111
000
An
—
—
(xxx).L
111
001
(An)
010
reg. number:An
# < data >
111
100
(An) +
011
reg. number:An
– (An)
100
reg. number:An
(d16,An)
101
reg. number:An
(d16,PC)
111
010
(d8,An,Xn)
110
reg. number:An
(d8,PC,Xn)
111
011
(bd,An,Xn)
110
reg. number:An
(bd,PC,Xn)
111
011
([bd,An,Xn],od)
110
reg. number:An
([bd,PC,Xn],od)
111
011
([bd,An],Xn,od)
110
reg. number:An
([bd,PC],Xn,od)
111
011
*Only if < fmt > is byte, word, long, or single.
R/M field—Specifies the source operand address mode.
0 — The operation is register to register.
1 — The operation is < ea > to register.
MOTOROLA
M68000 FAMILY PROGRAMMER’S REFERENCE MANUAL
5-75
Floating Point Instructions
FMOVE
Move Floating-Point Data Register
(MC6888X, MC68040)
FMOVE
Source Specifier field—Specifies the source register or data format.
If R/M = 0, specifies the source floating-point data register.
If R/M = 1, specifies the source data format:
000 — Long-Word Integer (L)
001 — Single-Precision Real (S)
010 — Extended-Precision Real (X)
011 — Packed-Decimal Real (P)*
100 — Word Integer (W)
101 — Double-Precision Real (D)
110 — Byte Integer (B)
*This encoding in the MC68040 will cause an unimplemented data type
exception to allow emulation in software.
Destination Register field—Specifies the destination floating- point data register.
Opmode field—Specifies the instruction and rounding precision.
0000000 FMOVE
Rounding precision specified by the floating-point
control register.
1000000 FSMOVE Single-precision rounding specified.
1000100 FDMOVE Double-precision rounding specified.
Register-to-Memory Operation: Rounds the source operand to the size of the specified
destination format and stores it at the destination effective address. If the format of the
destination is packed decimal, a third operand is required to specify the format of the
resultant string. This operand, called the k-factor, is a 7-bit signed integer (twos
complement) and may be specified as an immediate value or in an integer data
register. If a data register contains the k-factor, only the least significant seven bits are
used, and the rest of the register is ignored.
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M68000 FAMILY PROGRAMMER’S REFERENCE MANUAL
MOTOROLA
Floating Point Instructions
FMOVE
Move Floating-Point Data Register
(MC6888X, MC68040)
FMOVE
Floating-Point Status Register (Register-to-Memory):
Condition Codes:
Not affected.
Quotient Byte:
Not affected.
Exception Byte:
BSUN
Cleared
< fmt > is B, W, or L
SNAN
Refer to 1.6.5 Not-A-Numbers.
OPERR
Set if the source operand is infinity or if the
destination size is exceeded after conversion
and rounding; cleared otherwise.
Cleared
Cleared
Cleared
Refer to exception processing in the
appropriate user’s manual.
Cleared
Cleared
Refer to 1.6.5 Not-A-Numbers
Refer to exception processing in the
appropriate user’s manual.
Refer to exception processing in the
appropriate user’s manual.
Cleared
Refer to exception processing in the
appropriate user’s manual.
Cleared
Cleared
Refer to 1.6.5 Not-A-Numbers.
Set if the k-factor > + 17 or the magnitude of
the decimal exponent exceeds three digits;
cleared otherwise.
Cleared
Cleared
Cleared
Refer to exception processing in the
appropriate user’s manual.
Cleared
OVFL
UNFL
DZ
INEX2
< fmt > is S, D, or X
INEX1
BSUN
SNAN
OVFL
UNFL
DZ
INEX2
INEX1
BSUN
SNAN
OPERR
< fmt > is P
OVFL
UNFL
DZ
INEX2
INEX1
Accrued Exception Byte:
MOTOROLA
Affected as described in exception processing in the appropriate user’s manual.
M68000 FAMILY PROGRAMMER’S REFERENCE MANUAL
5-77
Floating Point Instructions
FMOVE
Move Floating-Point Data Register
(MC6888X, MC68040)
FMOVE
Instruction Format:
REGISTER—TO-MEMORY
15
14
13
12
11
10
1
1
1
COPROCESSOR
ID
0
1
1
DESTINATION
FORMAT
9
8
7
6
1
0
0
0
SOURCE
REGISTER
5
4
3
2
1
0
EFFECTIVE ADDRESS
MODE
REGISTER
K-FACTOR
(IF REQUIRED)
Instruction Fields:
Effective Address field—Specifies the destination location. Only data alterable
addressing modes can be used as listed in the following table:
Addressing Mode
Mode
Register
Addressing Mode
Mode
Register
Dn*
000
reg. number:Dn
(xxx).W
111
000
An
—
—
(xxx).L
111
001
(An)
010
reg. number:An
# < data >
—
—
(An) +
011
reg. number:An
– (An)
100
reg. number:An
(d16,An)
101
reg. number:An
(d16,PC)
—
—
(d8,An,Xn)
110
reg. number:An
(d8,PC,Xn)
—
—
(bd,An,Xn)
110
reg. number:An
(bd,PC,Xn)
—
—
([bd,An,Xn],od)
110
reg. number:An
([bd,PC,Xn],od)
—
—
([bd,An],Xn,od)
110
reg. number:An
([bd,PC],Xn,od)
—
—
*Only if < fmt > is byte, word, long, or single.
Destination Format field—Specifies the data format of the destination operand:
000 — Long-Word Integer (L)
001 — Single-Precision Real (S)
010 — Extended-Precision Real (X)
011 — Packed-Decimal Real with Static k-Factor (P{#k})*
100 — Word Integer (W)
101 — Double-Precision Real (D)
110 — Byte Integer (B)
111 — Packed-Decimal Real with Dynamic k-Factor (P{Dn})*
*This encoding will cause an unimplemented data type exception in the
MC68040 to allow emulation in software.
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M68000 FAMILY PROGRAMMER’S REFERENCE MANUAL
MOTOROLA
Floating Point Instructions
FMOVE
Move Floating-Point Data Register
(MC6888X, MC68040)
FMOVE
Source Register field—Specifies the source floating-point data register.
k-Factor field—If the destination format is packed decimal, used to specify the format
of the decimal string. For any other destination format, this field should be set to
all zeros. For a static k-factor, this field is encoded with a twos-complement
integer where the value defines the format as follows:
– 64 to 0—Indicates the number of significant digits to the right of the decimal
point (FORTRAN "F" format).
+ 1 to + 17—Indicates the number of significant digits in the mantissa (FORTRAN "E" format).
+ 18 to + 63—Sets the OPERR bit in the floating-point status register exception
byte and treated as + 17.
The format of this field for a dynamic k-factor is:
rrr0000
where "rrr" is the number of the main processor data register that contains the k-factor
value.
The following table gives several examples of how the k-factor value affects the format
of the decimal string that is produced by the floating-point coprocessor. The format of
the string that is generated is independent of the source of the k-factor (static or
dynamic).
k- Factor Source Operand Value
MOTOROLA
Destination String
–5
+ 12345.678765
+ 1.234567877E + 4
–3
+ 12345.678765
+ 1.2345679E + 4
–1
+ 12345.678765
+ 1.23457E + 4
0
+ 12345.678765
+ 1.2346E + 4
+1
+ 12345.678765
+ 1.E + 4
+3
+ 12345.678765
+ 1.23E + 4
+5
+ 12345.678765
+ 1.2346E + 4
M68000 FAMILY PROGRAMMER’S REFERENCE MANUAL
5-79
Floating Point Instructions
FMOVE
FMOVE
Move Floating-Point
System Control Register
(MC6888X, MC68040)
Operation:
Source → Destination
Assembler
Syntax:
FMOVE.L < ea > ,FPCR
FMOVE.L FPCR, < ea >
Attributes:
Size = (Long)
Description: Moves the contents of a floating-point system control register (floating-point
control register, floating-point status register, or floating-point instruction address
register) to or from an effective address. A 32-bit transfer is always performed, even
though the system control register may not have 32 implemented bits. Unimplemented
bits of a control register are read as zeros and are ignored during writes (must be zero
for compatibility with future devices). For the MC68881, this instruction does not cause
pending exceptions (other than protocol violations) to be reported. Furthermore, a write
to the floating-point control register exception enable byte or the floating-point status
register exception status byte cannot generate a new exception, regardless of the
value written.
Floating-Point Status Register: Changed only if the destination is the floating-point status
register, in which case all bits are modified to reflect the value of the source operand.
Instruction Format:
15
14
13
1
1
1
1
0
dr
5-80
12
1
11
9
8
7
6
COPROCESSOR
ID
0
0
0
0
0
0
REGISTER
SELECT
10
0
5
0
4
3
2
1
0
EFFECTIVE ADDRESS
MODE
REGISTER
0
0
M68000 FAMILY PROGRAMMER’S REFERENCE MANUAL
0
0
0
MOTOROLA
Floating Point Instructions
FMOVE
FMOVE
Move Floating-Point
System Control Register
(MC6888X, MC68040)
Instruction Fields:
Effective Address field—(Memory-to-Register) All addressing modes can be used as
listed in the following table:
Addressing Mode
Mode
Register
Addressing Mode
Mode
Register
Dn
000
reg. number:Dn
(xxx).W
111
000
An*
001
reg. number:An
(xxx).L
111
001
(An)
010
reg. number:An
# < data >
111
100
(An) +
011
reg. number:An
– (An)
100
reg. number:An
(d16,An)
101
reg. number:An
(d16,PC)
111
010
(d8,An,Xn)
110
reg. number:An
(d8,PC,Xn)
111
011
(bd,An,Xn)
110
reg. number:An
(bd,PC,Xn)
111
011
([bd,An,Xn],od)
110
reg. number:An
([bd,PC,Xn],od)
111
011
([bd,An],Xn,od)
110
reg. number:An
([bd,PC],Xn,od)
111
011
*Only if the source register is the floating-point instruction address register.
Effective Address field—(Register-to-Memory) Only alterable addressing modes can
be used as listed in the following table:
Addressing Mode
Mode
Register
Addressing Mode
Mode
Register
Dn
000
reg. number:Dn
(xxx).W
111
000
An*
001
reg. number:An
(xxx).L
111
001
(An)
010
reg. number:An
# < data >
—
—
(An) +
011
reg. number:An
– (An)
100
reg. number:An
(d16,An)
101
reg. number:An
(d16,PC)
—
—
(d8,An,Xn)
110
reg. number:An
(d8,PC,Xn)
—
—
(bd,An,Xn)
110
reg. number:An
(bd,PC,Xn)
—
—
([bd,An,Xn],od)
110
reg. number:An
([bd,PC,Xn],od)
—
—
([bd,An],Xn,od)
110
reg. number:An
([bd,PC],Xn,od)
—
—
*Only if the source register is the floating-point instruction address register.
MOTOROLA
M68000 FAMILY PROGRAMMER’S REFERENCE MANUAL
5-81
Floating Point Instructions
FMOVE
Move Floating-Point
System Control Register
FMOVE
(MC6888X, MC68040)
dr field—Specifies the direction of the data transfer.
0 — From < ea > to the specified system control register.
1 — From the specified system control register to < ea > .
Register Select field—Specifies the system control register to be moved:
100 Floating-Point Control Register
010 Floating-Point Status Register
001 Floating-Point Instruction Address Register
5-82
M68000 FAMILY PROGRAMMER’S REFERENCE MANUAL
MOTOROLA
Floating Point Instructions
FMOVECR
FMOVECR
Move Constant ROM
(MC6888X, M68040FPSP)
Operation:
ROM Constant → FPn
Assembler
Syntax:
FMOVECR.X
Attributes:
Format = (Extended)
# < ccc > ,FPn
Description: Fetches an extended-precision constant from the floating- point coprocessor
on-chip ROM, rounds the mantissa to the precision specified in the floating-point
control register mode control byte, and stores it in the destination floating-point data
register. The constant is specified by a predefined offset into the constant ROM. The
values of the constants contained in the ROM are shown in the offset table at the end
of this description.
Floating-Point Status Register:
Condition Codes:
Affected as described in 3.6.2 Conditional Testing.
Quotient Byte:
Not affected.
Exception Byte:
BSUN
SNAN
OPERR
OVFL
UNFL
DZ
INEX2
Cleared
Cleared
Cleared
Cleared
Cleared
Cleared
Refer to inexact result in the appropriate
user’s manual.
Cleared
INEX1
Accrued Exception Byte:
Affected as described in IEEE exception and trap compatibility in the appropriate user’s manual.
Instruction Format:
15
14
13
12
1
1
1
1
0
1
0
1
MOTOROLA
11
10
9
COPROCESSOR
ID
1
1
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
0
DESTINATION
REGISTER
ROM OFFSET
M68000 FAMILY PROGRAMMER’S REFERENCE MANUAL
5-83
Floating Point Instructions
FMOVECR
Move Constant ROM
(MC6888X, M68040FPSP)
FMOVECR
Instruction Fields:
Coprocessor ID field—Specifies which coprocessor in the system is to execute this
instruction. Motorola assemblers default to ID = 1 for the floating-point
coprocessor.
Destination Register field—Specifies the destination floating- point data register.
ROM Offset field—Specifies the offset into the floating-point coprocessor on-chip
constant ROM where the desired constant is located. The offsets for the available
constants are as follows:
Offset
$00
$0B
$0C
$0D
$0E
$0F
$30
$31
$32
$33
Constant
π
Log10(2)
e
Log2(e)
Log10(e)
0.0
1n(2)
1n(10)
100
101
$34
102
$35
104
$36
108
$37
1016
$38
1032
$39
1064
$3A
10128
$3B
10256
$3C
10512
$3D
101024
$3E
102048
$3F
104096
The on-chip ROM contains other constants useful only to the on- chip microcode routines. The values contained at offsets other than those defined above are reserved for
the use of Motorola and may be different on various mask sets of the floating-point
coprocessor. These undefined values yield the value 0.0 in the M68040FPSP.
5-84
M68000 FAMILY PROGRAMMER’S REFERENCE MANUAL
MOTOROLA
Floating Point Instructions
FMOVEM
Move Multiple Floating-Point
Data Registers
FMOVEM
(MC6888X, MC68040)
Operation:
Register List → Destination
Source → Register List
Assembler
Syntax:
FMOVEM.X < list > , < ea >
FMOVEM.X Dn, < ea >
FMOVEM.X < ea > , < list > FMOVEM.X < ea > ,Dn
Attributes:
Format = (Extended)
Description:Moves one or more extended-precision numbers to or from a list of floatingpoint data registers. No conversion or rounding is performed during this operation, and
the floating-point status register is not affected by the instruction. For the MC68881, this
instruction does not cause pending exceptions (other than protocol violations) to be
reported. Furthermore, a write to the floating- point control register exception enable
byte or the floating-point status register exception status byte connot generate a new
exception, despite the value written.
Any combination of the eight floating-point data registers can be transferred, with the
selected registers specified by a user- supplied mask. This mask is an 8-bit number,
where each bit corresponds to one register; if a bit is set in the mask, that register is
moved. The register select mask may be specified as a static value contained in the
instruction or a dynamic value in the least significant eight bits of an integer data register (the remaining bits of the register are ignored).
FMOVEM allows three types of addressing modes: the control modes, the predecrement mode, or the postincrement mode. If the effective address is one of the control
addressing modes, the registers are transferred between the processor and memory
starting at the specified address and up through higher addresses. The order of the
transfer is from FP0 – FP7.
MOTOROLA
M68000 FAMILY PROGRAMMER’S REFERENCE MANUAL
5-85
Floating Point Instructions
FMOVEM
FMOVEM
Move Multiple Floating-Point
Data Registers
(MC6888X, MC68040)
If the effective address is the predecrement mode, only a register- to-memory operation is allowed. The registers are stored starting at the address contained in the
address register and down through lower addresses. Before each register is stored, the
address register is decremented by 12 (the size of an extended-precision number in
memory) and the floating-point data register is then stored at the resultant address.
When the operation is complete, the address register points to the image of the last
floating- point data register stored. The order of the transfer is from FP7 – FP0.
If the effective address is the postincrement mode, only a memory- to-register operation is allowed. The registers are loaded starting at the specified address and up
through higher addresses. After each register is stored, the address register is incremented by 12 (the size of an extended-precision number in memory). When the operation is complete, the address register points to the byte immediately following the
image of the last floating-point data register loaded. The order of the transfer is the
same as for the control addressing modes: FP0 – FP7.
Floating-Point Status Register: Not Affected. Note that the FMOVEM instruction provides
the only mechanism for moving a floating- point data item between the floating-point
unit and memory without performing any data conversions or affecting the condition
code and exception status bits.
Instruction Format:
15
14
13
1
1
1
1
1
dr
5-86
12
11
1
MODE
9
8
7
6
COPROCESSOR
ID
10
0
0
0
0
0
0
5
4
3
2
1
0
EFFECTIVE ADDRESS
MODE
REGISTER
REGISTER LIST
M68000 FAMILY PROGRAMMER’S REFERENCE MANUAL
MOTOROLA
Floating Point Instructions
FMOVEM
FMOVEM
Move Multiple Floating-Point
Data Registers
(MC6888X, MC68040)
Instruction Fields:
Effective Address field—(Memory-to-Register) Only control addressing modes or the
postincrement addressing mode can be used as listed in the following table:
Addressing Mode
Mode
Register
Addressing Mode
Mode
Register
Dn
—
—
(xxx).W
111
000
An
—
—
(xxx).L
111
001
(An)
010
reg. number:An
# < data >
—
—
(An) +
011
reg. number:An
– (An)
—
—
(d16,An)
101
reg. number:An
(d16,PC)
111
010
(d8,An,Xn)
110
reg. number:An
(d8,PC,Xn)
111
011
(bd,An,Xn)
110
reg. number:An
(bd,PC,Xn)
111
011
([bd,An,Xn],od)
110
reg. number:An
([bd,PC,Xn],od)
111
011
([bd,An],Xn,od)
110
reg. number:An
([bd,PC],Xn,od)
111
011
Effective Address field—(Register-to-Memory) Only control alterable addressing
modes or the predecrement addressing mode can be used as listed in the
following table:
MOTOROLA
Addressing Mode
Mode
Register
Addressing Mode
Mode
Register
Dn
—
—
(xxx).W
111
000
An
—
—
(xxx).L
111
001
(An)
010
reg. number:An
# < data >
—
—
(An) +
—
—
– (An)
100
reg. number:An
(d16,An)
101
reg. number:An
(d16,PC)
—
—
(d8,An,Xn)
110
reg. number:An
(d8,PC,Xn)
—
—
(bd,An,Xn)
110
reg. number:An
(bd,PC,Xn)
—
—
([bd,An,Xn],od)
110
reg. number:An
([bd,PC,Xn],od)
—
—
([bd,An],Xn,od)
110
reg. number:An
([bd,PC],Xn,od)
—
—
M68000 FAMILY PROGRAMMER’S REFERENCE MANUAL
5-87
Floating Point Instructions
FMOVEM
FMOVEM
Move Multiple Floating-Point
Data Registers
(MC6888X, MC68040)
dr field—Specifies the direction of the transfer.
0 — Move the listed registers from memory to the floating-point unit.
1 — Move the listed registers from the floating-point unit to memory.
Mode field—Specifies the type of the register list and addressing mode.
00 — Static register list, predecrement addressing mode.
01 — Dynamic register list, predecrement addressing mode.
10 — Static register list, postincrement or control addressing mode.
11 — Dynamic register list, postincrement or control addressing mode.
Register List field:
Static list—contains the register select mask. If a register is to be moved, the corresponding bit in the mask is set as shown below; otherwise it is clear.
Dynamic list—contains the integer data register number, rrr, as listed in the following
table:
List Type
Register List Format
Static, – (An)
FP7
FP6
FP5
FP4
FP3
FP2
FP1
FP0
Static, (An) + ,
or Control
FP0
FP1
FP2
FP3
FP4
FP5
FP6
FP7
Dynamic
0
r
r
r
0
0
0
0
The format of the dynamic list mask is the same as for the static list and is contained
in the least significant eight bits of the specified main processor data register.
Programming Note: This instruction provides a very useful feature, dynamic register list
specification, that can significantly enhance system performance. If the calling
conventions used for procedure calls utilize the dynamic register list feature, the
number of floating-point data registers saved and restored can be reduced.
To utilize the dynamic register specification feature of the FMOVEM instruction, both
the calling and the called procedures must be written to communicate information
about register usage. When one procedure calls another, a register mask must be
passed to the called procedure to indicate which registers must not be altered upon
return to the calling procedure. The called procedure then saves only those registers
that are modified and are already in use. Several techniques can be used to utilize this
mechanism, and an example follows.
5-88
M68000 FAMILY PROGRAMMER’S REFERENCE MANUAL
MOTOROLA
Floating Point Instructions
FMOVEM
Move Multiple Floating-Point
Data Registers
FMOVEM
(MC6888X, MC68040)
In this example, a convention is defined by which each called procedure is passed a
word mask in D7 that identifies all floating-point registers in use by the calling procedure. Bits 15 – 8 identify the registers in the order FP0 – FP7, and bits 7 – 0 identify the
registers in the order FP7 – FP0 (the two masks are required due to the different transfer order used by the predecrement and postincrement addressing modes). The code
used by the calling procedure consists of simply moving the mask (which is generated
at compile time) for the floating-point data registers currently in use into D7:
Calling procedure...
MOVE.W
#ACTIVE,D7
BSR
PROC_2
Load the list of FP registers that are
in use.
The entry code for all other procedures computes two masks. The first mask identifies
the registers in use by the calling procedure that are used by the called procedure (and
therefore saved and restored by the called procedure). The second mask identifies the
registers in use by the calling procedure that are used by the called procedure (and
therefore not saved on entry). The appropriate registers are then stored along with the
two masks:
Called procedure...
MOVE.W
AND.W
FMOVEM
MOVE.W
EOR.W
MOVE.W
D7,D6
#WILL_USE,D7
registers.
D7, – (A7)
D7, – (A7)
D7,D6
registers.
D6, – (A7)
Copy the list of active registers.
Generate the list of doubly-used
Save those registers.
Save the register list.
Generate the list of not saved active
Save it for later use.
If the second procedure calls a third procedure, a register mask is passed to the third
procedure that indicates which registers must not be altered by the third procedure.
This mask identifies any registers in the list from the first procedure that were not saved
by the second procedure, plus any registers used by the second procedure that must
not be altered by the third procedure.
MOTOROLA
M68000 FAMILY PROGRAMMER’S REFERENCE MANUAL
5-89
Floating Point Instructions
FMOVEM
Move Multiple Floating-Point
Data Registers
FMOVEM
(MC6888X, MC68040)
An example of the calculation of this mask is as follows:
Nested calling sequence...
MOVE.W
OR.W
BSR
UNSAVED (A7),D7 Load the list of active registers not
saved at entry.
#WILL_USE,D7
Combine with those active at this time
PROC_3
Upon return from a procedure, the restoration of the necessary registers follows the
same convention, and the register mask generated during the save operation on entry
is used to restore the required floating-point data registers:
Return to caller...
ADDQ.L
MOVE.B
FMOVEM
*
*
*
RTS
5-90
#2,A7
(A7) + ,D7
use byte).
(A7) + ,D7
Discard the list of registers not saved.
Get the saved register list (pop word,
Restore the registers.
Return to the calling routine.
M68000 FAMILY PROGRAMMER’S REFERENCE MANUAL
MOTOROLA
Floating Point Instructions
FMOVEM
Move Multiple Floating-Point
Control Registers
FMOVEM
(MC6888X, MC68040)
Operation:
Register List → Destination
Source → Register List
Assembler
Syntax:
FMOVEM.L < list > , < ea >
FMOVEM.L < ea > , < list >
Attributes:
Size = (Long)
Description: Moves one or more 32-bit values into or out of the specified system control
registers. Any combination of the three system control registers may be specified. The
registers are always moved in the same order, regardless of the addressing mode
used; the floating-point control register is moved first, followed by the floating-point
status register, and the floating-point instruction address register is moved last. If a
register is not selected for the transfer, the relative order of the transfer of the other
registers is the same. The first register is transferred between the floating-point unit and
the specified address, with successive registers located up through higher addresses.
For the MC68881, this instruction does not cause pending exceptions (other than protocol violations) to be reported. Furthermore, a write to the floating-point control register exception enable byte or the floating-point status register exception status byte
connot generate a new exception, despite the value written.
When more than one register is moved, the memory or memory- alterable addressing
modes can be used as shown in the addressing mode tables. If the addressing mode
is predecrement, the address register is first decremented by the total size of the register images to be moved (i.e., four times the number of registers), and then the registers are transferred starting at the resultant address. For the postincrement addressing
mode, the selected registers are transferred to or from the specified address, and then
the address register is incremented by the total size of the register images transferred.
If a single system control register is selected, the data register direct addressing mode
may be used; if the only register selected is the floating-point instruction address register, then the address register direct addressing mode is allowed. Note that if a single
register is selected, the opcode generated is the same as for the FMOVE single system
control register instruction.
MOTOROLA
M68000 FAMILY PROGRAMMER’S REFERENCE MANUAL
5-91
Floating Point Instructions
FMOVEM
FMOVEM
Move Multiple Floating-Point
Control Registers
(MC6888X, MC68040)
Floating-Point Status Register: Changed only if thedestinationlist includes the floatingpoint status register in which case all bits are modified to reflect the value of the source
register image.
Instruction Format:
15
14
13
1
1
1
1
0
dr
12
1
11
9
8
7
6
COPROCESSOR
ID
10
0
0
0
0
0
0
REGISTER
LIST
0
5
0
4
3
2
1
0
EFFECTIVE ADDRESS
MODE
REGISTER
0
0
0
0
0
Instruction Fields:
Effective Address field—Determines the addressing mode for the operation.
Memory-to-Register—Only control addressing modes or the postincrement
addressing mode can be used as listed in the following table:
Addressing Mode
Mode
Register
Addressing Mode
Mode
Register
Dn*
000
reg. number:Dn
(xxx).W
111
000
An**
001
reg. number:An
(xxx).L
111
001
(An)
010
reg. number:An
# < data >
111
100
(An) +
011
reg. number:An
– (An)
100
reg. number:An
(d16,An)
101
reg. number:An
(d16,PC)
111
010
(d8,An,Xn)
110
reg. number:An
(d8,PC,Xn)
111
011
(bd,An,Xn)
110
reg. number:An
(bd,PC,Xn)
111
011
([bd,An,Xn],od)
110
reg. number:An
([bd,PC,Xn],od)
111
011
([bd,An],Xn,od)
110
reg. number:An
([bd,PC],Xn,od)
111
011
*Only if a single floating-point instruction address register, floating-point status register, or
floating-point control register is selected.
**Only if the floating-point instruction address register is the single register selected.
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M68000 FAMILY PROGRAMMER’S REFERENCE MANUAL
MOTOROLA
Floating Point Instructions
FMOVEM
FMOVEM
Move Multiple Floating-Point
Control Registers
(MC6888X, MC68040)
Register-to-Memory—Only control alterable addressing modes or the predecrement
addressing mode can be used as listed in the following table:
Addressing Mode
Mode
Register
Addressing Mode
Mode
Register
Dn*
000
reg. number:Dn
(xxx).W
111
000
An**
001
reg. number:An
(xxx).L
111
001
(An)
010
reg. number:An
# < data >
—
—
(An) +
011
reg. number:An
– (An)
100
reg. number:An
(d16,An)
101
reg. number:An
(d16,PC)
—
—
(d8,An,Xn)
110
reg. number:An
(d8,PC,Xn)
—
—
(bd,An,Xn)
110
reg. number:An
(bd,PC,Xn)
—
—
([bd,An,Xn],od)
110
reg. number:An
([bd,PC,Xn],od)
—
—
([bd,An],Xn,od)
110
reg. number:An
([bd,PC],Xn,od)
—
—
*Only if a single floating-point control register is selected.
**Only if the floating-point instruction address register is the single register selected.
dr field—Specifies the direction of the transfer.
0 — Move the listed registers from memory to the floating-point unit.
1 — Move the listed registers from the floating-point unit to memory.
Register List field—Contains the register select mask. If a register is to be moved, the
corresponding bit in the list is set; otherwise, it is clear. At least one register must
be specified.
MOTOROLA
Bit Number
Register
12
Floating-Point Control Register
11
Floating-Point Status Register
10
Floating-Point Instruction
Address Register
M68000 FAMILY PROGRAMMER’S REFERENCE MANUAL
5-93
Floating Point Instructions
FMUL
FMUL
Floating-Point Multiply
(MC6888X, MC68040)
Operation:
Source x FPn → FPn
Assembler
Syntax:
FMUL. < fmt > < ea > ,FPn
FMUL.X FPm,FPn
*FrMUL < fmt > < ea > ,FPn
*FrMUL.X FPm,FPn
where r is rounding precision, S or D
*Supported by MC68040 only
Attributes:
Format = (Byte, Word, Long, Single, Double, Extended, Packed)
Description: Converts the source operand to extended precision (if necessary) and
multiplies that number by the number in the destination floating-point data register.
Stores the result in the destination floating-point data register.
FMUL will round the result to the precision selected in the floating-point control register.
FSMUL and FDMUL will round the result to single or double precision, respectively,
regardless of the rounding precision selected in the floating-point control register.
Operation Table:
DESTINATION
In Range
+
+
–
Zero
+ + 0.0
– – 0.0
Infinity
+ + inf
– – inf
In Range
– +
SOURCE1
Zero
+ 0.0
– 0.0
Multiply
Infinity
– 0.0 + inf
+ 0.0 – inf
– 0.0 + 0.0
+ 0.0 – 0.0
– inf
+ inf
– +
– 0.0
+ 0.0
NAN2
–
– inf
+ inf
NAN2
+ inf
– inf
– inf
+ inf
NOTES:
1. If the source operand is a NAN, refer to 1.6.5 Not-A-Numbers for more information.
2. Sets the OPERR bit in the floating-point status register exception byte.
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M68000 FAMILY PROGRAMMER’S REFERENCE MANUAL
MOTOROLA
Floating Point Instructions
FMUL
FMUL
Floating-Point Multiply
(MC6888X, MC68040)
Floating-Point Status Register:
Condition Codes:
Affected as described in 3.6.2 Conditional Testing.
Quotient Byte:
Not affected.
Exception Byte:
BSUN
SNAN
OPERR
OVFL
Cleared
Refer to 1.6.5 Not-A-Numbers.
Set for 0 x infinity; cleared otherwise.
Refer to exception processing in the
appropriate user’s manual.
Refer to exception processing in the
appropriate user’s manual.
Cleared
Refer to exception processing in the
appropriate user’s manual.
If < fmt > is packed, refer to exception
processing in the appropriate user’s manual;
cleared otherwise.
UNFL
DZ
INEX2
INEX1
Accrued Exception Byte:
Affected as described in exception processing in the appropriate user’s manual.
Instruction Format:
15
14
13
1
1
1
0
R/M
0
MOTOROLA
12
1
11
9
8
7
6
COPROCESSOR
ID
0
0
0
SOURCE
SPECIFIER
10
DESTINATION
REGISTER
5
4
3
2
1
0
EFFECTIVE ADDRESS
MODE
REGISTER
OPMODE
M68000 FAMILY PROGRAMMER’S REFERENCE MANUAL
5-95
Floating Point Instructions
FMUL
FMUL
Floating-Point Multiply
(MC6888X, MC68040)
Instruction Fields:
Effective Address field—Determines the addressing mode for external operands.
If R/M = 0, this field is unused and should be all zeros.
If R/M = 1, specifies the location of the source operand location. Only data
addressing modes can be used as listed in the following table:
Addressing Mode
Mode
Register
Addressing Mode
Mode
Register
Dn*
000
reg. number:Dn
(xxx).W
111
000
An
—
—
(xxx).L
111
001
(An)
010
reg. number:An
# < data >
111
100
(An) +
011
reg. number:An
– (An)
100
reg. number:An
(d16,An)
101
reg. number:An
(d16,PC)
111
010
(d8,An,Xn)
110
reg. number:An
(d8,PC,Xn)
111
011
(bd,An,Xn)
110
reg. number:An
(bd,PC,Xn)
111
011
([bd,An,Xn],od)
110
reg. number:An
([bd,PC,Xn],od)
111
011
([bd,An],Xn,od)
110
reg. number:An
([bd,PC],Xn,od)
111
011
*Only if < fmt > is byte, word, long, or single.
R/M field—Specifies the source operand address mode.
0 — The operation is register to register.
1 — The operation is < ea > to register.
Source Specifier field—Specifies the source register or data format.
If R/M = 0, specifies the source floating-point data register.
If R/M = 1, specifies the source data format:
000 — Long-Word Integer (L)
001 — Single-Precision Real (S)
010 — Extended-Precision Real (X)
011 — Packed-Decimal Real (P)*
100 — Word Integer (W)
101 — Double-Precision Real (D)
110 — Byte Integer (B)
*This encoding will cause an unimplemented data type exception in the
MC68040 to allow emulation in software.
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M68000 FAMILY PROGRAMMER’S REFERENCE MANUAL
MOTOROLA
Floating Point Instructions
FMUL
Floating-Point Multiply
(MC6888X, MC68040)
FMUL
Destination Register field—Specifies the destination floating- point data register.
Opmode field—Specifies the instruction and rounding precision.
0100011 FMUL
1100011
1100111
MOTOROLA
FSMUL
FDMUL
Rounding precision specified by the floating-point
control register.
Single-precision rounding specified.
Double-precision rounding specified.
M68000 FAMILY PROGRAMMER’S REFERENCE MANUAL
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Floating Point Instructions
FNEG
FNEG
Floating-Point Negate
(MC6888X, MC68040)
Operation:
– (Source) → FPn
Assembler
Syntax:
FNEG. < fmt > < ea > ,FPn
FNEG.X FPm,FPn
FNEG.X FPn
*FrNEG. < fmt > < ea > ,FPn
*FrNEG.X FPm,FPn
*FrNEG.X FPn
where r is rounding precision, S or D
*Supported by MC68040 only
Attributes:
Format = (Byte, Word, Long, Single, Double, Extended, Packed)
Description: Converts the source operand to extended precision (if necessary) and inverts
the sign of the mantissa. Stores the result in the destination floating-point data register.
FNEG will round the result to the precision selected in the floating-point control register.
FSNEG and FDNEG will round the result to single or double precision, respectively,
regardless of the rounding precision selected in the floating-point control register.
Operation Table:
DESTINATION
Result
+
In Range
Negate
– +
– 0.0
SOURCE
Zero
– +
+ 0.0 – inf
Infinity
–
+ inf
NOTE: If the source operand is a NAN, refer to 1.6.5 Not-A-Numbers for more information.
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M68000 FAMILY PROGRAMMER’S REFERENCE MANUAL
MOTOROLA
Floating Point Instructions
FNEG
FNEG
Floating-Point Negate
(MC6888X, MC68040)
Floating-Point Status Register:
Condition Codes:
Affected as described in 3.6.2 Conditional Testing.
Quotient Byte:
Not affected.
Exception Byte:
BSUN
SNAN
OPERR
OVFL
UNFL
Cleared
Refer to 1.6.5 Not-A-Numbers.
Cleared
Cleared
If source is an extended-precision
denormalized number, refer to exception
processing in the appropriate user’s manual;
cleared otherwise.
Cleared
Cleared
If < fmt > is packed, refer to exception
processing in the appropriate user’s manual;
cleared otherwise.
DZ
INEX2
INEX1
Accrued Exception Byte:
Affected as described in exception processing in the appropriate user’s manual.
Instruction Format:
15
14
13
1
1
1
0
R/M
0
MOTOROLA
12
1
11
9
8
7
6
COPROCESSOR
ID
0
0
0
SOURCE
SPECIFIER
10
DESTINATION
REGISTER
5
4
3
2
1
0
EFFECTIVE ADDRESS
MODE
REGISTER
OPMODE
M68000 FAMILY PROGRAMMER’S REFERENCE MANUAL
5-99
Floating Point Instructions
FNEG
FNEG
Floating-Point Negate
(MC6888X, MC68040)
Instruction Fields:
Effective Address field—Determines the addressing mode for external operands.
If R/M = 0, this field is unused and should be all zeros.
If R/M = 1, specifies the location of the source operand. Only data addressing modes
can be used as listed in the following table:
Addressing Mode
Mode
Register
Addressing Mode
Mode
Register
Dn*
000
reg. number:Dn
(xxx).W
111
000
An
—
—
(xxx).L
111
001
(An)
010
reg. number:An
# < data >
111
100
(An) +
011
reg. number:An
– (An)
100
reg. number:An
(d16,An)
101
reg. number:An
(d16,PC)
111
010
(d8,An,Xn)
110
reg. number:An
(d8,PC,Xn)
111
011
(bd,An,Xn)
110
reg. number:An
(bd,PC,Xn)
111
011
([bd,An,Xn],od)
110
reg. number:An
([bd,PC,Xn],od)
111
011
([bd,An],Xn,od)
110
reg. number:An
([bd,PC],Xn,od)
111
011
*Only if < fmt > is byte, word, long, or single.
R/M field—Specifies the source operand address mode.
0 — The operation is register to register.
1 — The operation is < ea > to register.
Source Specifier field—Specifies the source register or data format.
If R/M = 0, specifies the source floating-point data register.
If R/M = 1, specifies the source data format:
000 — Long-Word Integer (L)
001 — Single-Precision Real (S)
010 — Extended-Precision Real (X)
011 — Packed-Decimal Real (P)*
100 — Word Integer (W)
101 — Double-Precision Real (D)
110 — Byte Integer (B)
*This encoding will cause an unimplemented data type exception to allow
emulation in software.
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M68000 FAMILY PROGRAMMER’S REFERENCE MANUAL
MOTOROLA
Floating Point Instructions
FNEG
Floating-Point Negate
(MC6888X, MC68040)
FNEG
Destination Register field—Specifies the destination floating- point data register. If R/
M = 0 and the source and destination fields are equal, then the input operand is
taken from the specified floating-point data register and the result is written into
the same register. If the single register syntax is used, Motorola assemblers set
the source and destination fields to the same value.
Opmode field—Specifies the instruction and rounding precision.
0011010 FNEG
1011010 FSNEG
1011110 FDNEG
MOTOROLA
Rounding precision specified by the floating-point
control register.
Single-precision rounding specified.
Double-precision rounding specified.
M68000 FAMILY PROGRAMMER’S REFERENCE MANUAL
5-101
Floating Point Instructions
FNOP
No Operation
(MC6888X, MC68040)
Operation:
None
Assembler
Syntax:
FNOP
Attributes:
Unsized
FNOP
Description: This instruction does not perform any explicit operation. However, it is useful
to force synchronization of the floating- point unit with an integer unit or to force
processing of pending exceptions. For most floating-point instructions, the integer unit
is allowed to continue with the execution of the next instruction once the floating-point
unit has any operands needed for an operation, thus supporting concurrent execution
of floating-point and integer instructions. The FNOP instruction synchronizes the
floating-point unit and the integer unit by causing the integer unit to wait until all
previous floating-point instructions have completed. Execution of FNOP also forces
any exceptions pending from the execution of a previous floating-point instruction to be
processed as a preinstruction exception.
The MC68882 may not wait to begin execution of another floating- point instruction until
it has completed execution of the current instruction. The FNOP instruction synchronizes the coprocessor and microprocessor unit by causing the microprocessor unit to
wait until the current instruction (or both instructions) have completed.
The FNOP instruction also forces the processing of exceptions pending from the execution of previous instructions. This is also inherent in the way that the floating-point
coprocessor utilizes the M68000 family coprocessor interface. Once the floating-point
coprocessor has received the input operand for an arithmetic instruction, it always
releases the main processor to execute the next instruction (regardless of whether or
not concurrent execution is prevented for the instruction due to tracing) without reporting the exception during the execution of that instruction. Then, when the main processor attempts to initiate the execution of the next floating-point coprocessor instruction,
a preinstruction exception may be reported to initiate exception processing for an
exception that occurred during a previous instruction. By using the FNOP instruction,
the user can force any pending exceptions to be processed without performing any
other operations.
Floating-Point Status Register: Not Affected.
5-102
M68000 FAMILY PROGRAMMER’S REFERENCE MANUAL
MOTOROLA
Floating Point Instructions
FNOP
FNOP
No Operation
(MC6888X, MC68040)
Instruction Format:
15
1
0
14
1
0
13
1
0
12
1
0
11
10
9
COPROCESSOR ID
0
0
0
8
0
0
7
1
0
6
0
0
5
0
0
4
0
0
3
0
0
2
0
0
1
0
0
0
0
0
Instruction Fields:
Coprocessor ID field—Specifies which coprocessor in the system is to execute this
instruction. Motorola assemblers default to ID = 1 for the floating-point
coprocessor.
NOTE
FNOP uses the same opcode as the FBcc.W < label > instruction, with cc = F (nontrapping false) and < label > = + 2 (which
results in a displacement of 0).
MOTOROLA
M68000 FAMILY PROGRAMMER’S REFERENCE MANUAL
5-103
Floating Point Instructions
FREM
FREM
IEEE Remainder
(MC6888X, M68040FPSP)
Operation:
IEEE Remainder of (FPn ÷ Source) → FPn
Assembler
Syntax:
FREM. < fmt > < ea > ,FPn
FREM.X FPm,FPn
Attributes:
Format = (Byte, Word, Long, Single, Double, Extended, Packed)
Description: Converts the source operand to extended precision (if necessary) and
calculates the modulo remainder of the number in the destination floating-point data
register, using the source operand as the modulus. Stores the result in the destination
floating-point data register and stores the sign and seven least significant bits of the
quotient in the floating-point status register quotient byte (the quotient is the result of
FPn ÷ Source). The IEEE remainder function is defined as:
FPn – (Source x N)
where N = INT (FPn ÷ Source) in the round-to-nearest mode.
The FREM function is not defined for a source operand equal to zero or for a destination operand equal to infinity. Note that this function is not the same as the FMOD
instruction, which uses the round-to-zero mode and thus returns a remainder that is different from the remainder required by the IEEE Specification for Binary Floating-Point
Arithmetic.
Operation Table:
DESTINATION
+
In Range
– +
SOURCE1
Zero#
– +
Infinity
In Range
+
–
IEEE Remainder
NAN2
FPn2
Zero
+
–
+ 0.0
– 0.0
NAN2
+ 0.0
– 0.0
Infinity
+
–
NAN2
NAN2
NAN†2
–
NOTES:
1. If the source operand is a NAN, refer to 1.6.5 Not-A-Numbers for more information.
2. Sets the OPERR bit in the floating-point status register exception byte.
3. Returns the value of FPn before the operation. However, the result is
processed by the normal instruction termination procedure to round it as
required. Thus, an overflow and/or inexact result may occur if the rounding
precision has been changed to a smaller size since the FPn value was loaded.
5-104
M68000 FAMILY PROGRAMMER’S REFERENCE MANUAL
MOTOROLA
Floating Point Instructions
FREM
FREM
IEEE Remainder
(MC6888X, M68040FPSP)
Floating-Point Status Register:
Condition Codes:
Affected as described in 3.6.2 Conditional Testing.
Quotient Byte:
Loaded with the sign and least significant seven bits of the
qotient (FPn ÷ Source). The sign of the quotient is the
exclusive-OR of the sign bits of the source and destination
operands.
Exception Byte:
BSUN
SNAN
OPERR
Cleared
Refer to 1.6.5 Not-A-Numbers.
Set if the source is zero or the destination is
infinity; cleared otherwise.
Cleared
Refer to underflow in the appropriate user’s
manual.
Cleared
Cleared
If < fmt > is packed, refer to inexact result on
decimal input in the appropriate user’s
manual; cleared otherwise.
OVFL
UNFL
DZ
INEX2
INEX1
Accrued Exception Byte:
Affected as described in IEEE exception and trap compatibility in the appropriate user’s manual.
Instruction Format:
15
14
13
1
1
1
0
R/M
0
12
1
11
9
8
7
6
COPROCESSOR
ID
0
0
0
SOURCE
SPECIFIER
10
DESTINATION
REGISTER
0
5
1
4
3
2
1
0
EFFECTIVE ADDRESS
MODE
REGISTER
0
0
1
0
1
Instruction Fields:
Coprocessor ID field—Specifies which coprocessor in the system is to execute this
instruction. Motorola assemblers default to ID = 1 for the floating-point
coprocessor.
MOTOROLA
M68000 FAMILY PROGRAMMER’S REFERENCE MANUAL
5-105
Floating Point Instructions
FREM
FREM
IEEE Remainder
(MC6888X, M68040FPSP)
Effective Address field—Determines the addressing mode for external operands.
If R/M = 0, this field is unused and should be all zeros.
If R/M = 1, this field is encoded with an M68000 family addressing mode as listed in
the following table:
Addressing Mode
Mode
Register
Addressing Mode
Mode
Register
Dn*
000
reg. number:Dn
(xxx).W
111
000
An
—
—
(xxx).L
111
001
(An)
010
reg. number:An
# < data >
111
100
(An) +
011
reg. number:An
– (An)
100
reg. number:An
(d16,An)
101
reg. number:An
(d16,PC)
111
010
(d8,An,Xn)
110
reg. number:An
(d8,PC,Xn)
111
011
(bd,An,Xn)
110
reg. number:An
(bd,PC,Xn)
111
011
([bd,An,Xn],od)
110
reg. number:An
([bd,PC,Xn],od)
111
011
([bd,An],Xn,od)
110
reg. number:An
([bd,PC],Xn,od)
111
011
*Only if < fmt > is byte, word, long, or single.
R/M field—Specifies the source operand address mode.
0 — The operation is register to register.
1 — The operation is < ea > to register.
Source Specifier field—Specifies the source register or data format.
If R/M = 0, specifies the source floating-point data register.
If R/M = 1, specifies the source data format:
000 — Long-Word Integer (L)
001 — Single-Precision Real (S)
010 — Extended-Precision Real (X)
011 — Packed-Decimal Real (P)
100 — Word Integer (W)
101 — Double-Precision Real (D)
110 — Byte Integer (B)
Destination Register field—Specifies the destination floating- point data register.
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M68000 FAMILY PROGRAMMER’S REFERENCE MANUAL
MOTOROLA
Floating Point Instructions
FSCALE
FSCALE
Scale Exponent
(MC6888X, M68040FPSP)
Operation:
FPn x INT(2Source) → FPn
Assembler
Syntax:
FSCALE. < fmt > < ea > ,FPn
FSCALE.X FPm,FPn
Attributes:
Format = (Byte, Word, Long, Single, Double, Extended, Packed)
Description: Converts the source operand to an integer (if necessary) and adds that integer
to the destination exponent. Stores the result in the destination floating-point data
register. This function has the effect of multiplying the destination by 2Source, but is
much faster than a multiply operation when the source is an integer value.
The floating-point coprocessor assumes that the scale factor is an integer value before
the operation is executed. If not, the value is chopped (i.e., rounded using the roundto-zero mode) to an integer before it is added to the exponent. When the absolute value
of the source operand is ≥ 214, an overflow or underflow always results.
Operation Table:
SOURCE1
DESTINATION
+
In Range + –
In Range
– +
Zero
– +
2
Scale Exponent
Infinity
–
NAN3
FPn
Zero + –
+ 0.0
– 0.0 + 0.0
– 0.0
NAN3
Infinity + –
+ inf
– inf + inf
– inf
NAN3
NOTES:
1. If the source operand is a NAN, refer to 1.6.5 Not-A-Numbers for more information.
2. Returns the value of FPn before the operation. However, the result is
processed by the normal instruction termination procedure to round it as
required. Thus, an overflow and/or inexact result may occur if the rounding
precision has been changed to a smaller size since the FPn value was
loaded.
3. Sets the OPERR bit in the floating-point status register exception byte.
MOTOROLA
M68000 FAMILY PROGRAMMER’S REFERENCE MANUAL
5-107
Floating Point Instructions
FSCALE
FSCALE
Scale Exponent
(MC6888X, M68040FPSP)
Floating-Point Status Register:
Condition Codes:
Affected as described in 3.6.2 Conditional Testing.
Quotient Byte:
Not affected
Exception Byte:
BSUN
Cleared
SNAN
OPERR
Refer to 1.6.5 Not-A-Numbers.
Set if the source operand is ± infinity; cleared
otherwise.
Refer to overflow in the appropriate user’s
manual.
Refer to underflow in the appropriate user’s
manual.
Cleared
Cleared
If < fmt > is packed, refer to inexact result on
decimal input in the appropriate user’s
manual; cleared otherwise.
OVFL
UNFL
DZ
INEX2
INEX1
Accrued Exception Byte:
Affected as described in IEEE exception and trap compatibility in the appropriate user’s manual.
Instruction Format:
15
14
13
1
1
1
0
R/M
0
12
1
11
9
8
7
6
COPROCESSOR
ID
0
0
0
SOURCE
SPECIFIER
10
DESTINATION
REGISTER
0
5
1
4
3
2
1
0
EFFECTIVE ADDRESS
MODE
REGISTER
0
0
1
1
0
Instruction Fields:
Coprocessor ID field—Specifies which coprocessor in the system is to execute this
instruction. Motorola assemblers default to ID = 1 for the floating-point
coprocessor.
5-108
M68000 FAMILY PROGRAMMER’S REFERENCE MANUAL
MOTOROLA
Floating Point Instructions
FSCALE
FSCALE
Scale Exponent
(MC6888X, M68040FPSP)
Effective Address field—Determines the addressing mode for external operands.
If R/M = 0, this field is unused and should be all zeros.
If R/M = 1, this field is encoded with an M68000 family addressing mode as listed in
the following table:
Addressing Mode
Mode
Register
Addressing Mode
Mode
Register
Dn*
000
reg. number:Dn
(xxx).W
111
000
An
—
—
(xxx).L
111
001
(An)
010
reg. number:An
# < data >
111
100
(An) +
011
reg. number:An
– (An)
100
reg. number:An
(d16,An)
101
reg. number:An
(d16,PC)
111
010
(d8,An,Xn)
110
reg. number:An
(d8,PC,Xn)
111
011
(bd,An,Xn)
110
reg. number:An
(bd,PC,Xn)
111
011
([bd,An,Xn],od)
110
reg. number:An
([bd,PC,Xn],od)
111
011
([bd,An],Xn,od)
110
reg. number:An
([bd,PC],Xn,od)
111
011
*Only if < fmt > is byte, word, long, or single.
R/M field—Specifies the source operand address mode.
0 — The operation is register to register.
1 — The operation is < ea > to register.
Source Specifier field—Specifies the source register or data format.
If R/M = 0, specifies the source floating-point data register.
If R/M = 1, specifies the source data format:
000 — Long-Word Integer (L)
001 — Single-Precision Real (S)
010 — Extended-Precision Real (X)
011 — Packed-Decimal Real (P)
100 — Word Integer (W)
101 — Double-Precision Real (D)
110 — Byte Integer (B)
Destination Register field—Specifies the destination floating- point data register.
MOTOROLA
M68000 FAMILY PROGRAMMER’S REFERENCE MANUAL
5-109
Floating Point Instructions
FScc
Set According to Floating-Point Condition
Operation:
(MC6888X, MC68040)
FScc
If (Condition True)
Then 1s → Destination
Else 0s → Destination
Assembler
Syntax:
FScc. < size > < ea >
Attributes:
Size = (Byte)
Description: If the specified floating-point condition is true, sets the byte integer operand at
the destination to TRUE (all ones); otherwise, sets the byte to FALSE (all zeros). The
conditional specifier cc may select any one of the 32 floating-point conditional tests as
described in Table 3-23 Floating-Point Conditional Tests.
Floating-Point Status Register:
Condition Codes:
Not affected.
Quotient Byte:
Not affected.
Exception Byte:
BSUN
SNAN
OPERR
OVFL
UNFL
DZ
INEX2
INEX1
Accrued Exception Byte:
5-110
Set if the NAN condition code is set and the
condition selected is an IEEE nonaware test.
Not Affected.
Not Affected.
Not Affected.
Not Affected.
Not Affected.
Not Affected.
Not Affected.
The IOP bit is set if the BSUN bit is set in the exception
byte. No other bit is affected.
M68000 FAMILY PROGRAMMER’S REFERENCE MANUAL
MOTOROLA
Floating Point Instructions
FScc
FScc
Set According to Floating-Point Condition
(MC6888X, MC68040)
Instruction Format:
15
14
13
12
11
10
9
8
7
6
0
0
1
0
0
0
1
1
1
1
COPROCESSOR
ID
0
0
0
0
0
0
0
5
4
3
2
1
0
EFFECTIVE ADDRESS
MODE
REGISTER
CONDITIONAL PREDICATE
Instruction Fields:
Effective Address field—Specifies the addressing mode for the byte integer operand.
Only data alterable addressing modes can be used as listed in the following table:
Addressing Mode
Mode
Register
Addressing Mode
Mode
Register
Dn
000
reg. number:Dn
(xxx).W
111
000
An
—
—
(xxx).L
111
001
(An)
010
reg. number:An
# < data >
—
—
(An) +
011
reg. number:An
– (An)
100
reg. number:An
(d16,An)
101
reg. number:An
(d16,PC)
—
—
(d8,An,Xn)
110
reg. number:An
(d8,PC,Xn)
—
—
(bd,An,Xn)
110
reg. number:An
(bd,PC,Xn)
—
—
([bd,An,Xn],od)
110
reg. number:An
([bd,PC,Xn],od)
—
—
([bd,An],Xn,od)
110
reg. number:An
([bd,PC],Xn,od)
—
—
Conditional Predicate field—Specifies one of 32 conditional tests as defined in 3.6.2
Conditional Testing.
NOTE
When a BSUN exception occurs, a preinstruction exception is
taken. If the exception handler returns without modifying the image of the program counter on the stack frame (to point to the
instruction following the FScc), then it must clear the cause of
the exception (by clearing the NAN bit or disabling the BSUN
trap) or the exception occurs again immediately upon return to
the routine that caused the exception.
MOTOROLA
M68000 FAMILY PROGRAMMER’S REFERENCE MANUAL
5-111
Floating Point Instructions
FSGLDIV
FSGLDIV
Single-Precision Divide
(MC6888X, MC68040)
Operation:
FPn ÷ Source → FPn
Assembler
Syntax:
FSGLDIV. < fmt > < ea > ,FPn
FSGLDIV.X
FPm,FPn
Attributes:
Format = (Byte, Word, Long, Single, Double, Extended, Packed)
Description: Converts the source operand to extended precision (if necessary) and divides
that number into the number in the destination floating-point data register. Stores the
result in the destination floating-point data register, rounded to single precision (despite
the current rounding precision). This function is undefined for 0 ÷ 0 and infinity ÷ infinity.
Both the source and destination operands are assumed to be representable in the single-precision format. If either operand requires more than 24 bits of mantissa to be
accurately represented, the extraneous mantissa bits are trancated prior to the division, hence the accuracy of the result is not guaranteed. Furthermore, the result exponent may exceed the range of single precision, regardless of the rounding precision
selected in the floating-point control register mode control byte. Refer to 3.6.1 Underflow, Round, Overflow for more information.
The accuracy of the result is not affected by the number of mantissa bits required to
represent each input operand since the input operands just change to extended precision. The result mantissa is rounded to single precision, and the result exponent is
rounded to extended precision, despite the rounding precision selected in the floatingpoint control register.
Operation Table:
DESTINATION
In Range
+
+
–
In Range
– +
Divide
(Single Precision)
Zero
+ + 0.0
– – 0.0
Infinity
+ + inf
– – inf
SOURCE3,1
Zero
inf2
2
– inf2
+ inf2
+
– inf
– 0.0
+ 0.0
– inf + inf
+ inf – inf
– +
NAN3
Infinity
–
+ 0.0
– 0.0
– 0.0
+ 0.0
+ 0.0
– 0.0
– 0.0
+ 0.0
– inf
+ inf
NAN3
NOTES:
1. If the source operand is a NAN, refer to 1.6.5 Not-A-Numbers for more information.
2. Sets the DZ bit in the floating-point status register exception byte.
3. Sets the OPERR bit in the floating-point status register exception byte.
5-112
M68000 FAMILY PROGRAMMER’S REFERENCE MANUAL
MOTOROLA
Floating Point Instructions
FSGLDIV
FSGLDIV
Single-Precision Divide
(MC6888X, MC68040)
Floating-Point Status Register:
Condition Codes:
Affected as described in 3.6.2 Conditional Testing.
Quotient Byte:
Not affected.
Exception Byte:
BSUN
SNAN
OPERR
OVFL
Cleared
Refer to 1.6.5 Not-A-Numbers.
Set for 0 ÷ 0 or infinity ÷ infinity.
Refer to overflow in the appropriate user’s
manual.
Refer to underflow in the appropriate user’s
manual.
Set if the source is zero and the destination is
in range; cleared otherwise.
Refer to inexact result in the appropriate
user’s manual.
If < fmt > is packed, refer to the appropriate
user’s manual for inexact result on decimal
input; cleared otherwise.
UNFL
DZ
INEX2
INEX1
Accrued Exception Byte:
Affected as described in IEEE exception and trap compatibility in the appropriate user’s manual.
Instruction Format:
15
14
13
1
1
1
0
R/M
0
12
1
11
9
8
7
6
COPROCESSOR
ID
0
0
0
SOURCE
SPECIFIER
10
DESTINATION
REGISTER
0
5
1
4
3
2
1
0
EFFECTIVE ADDRESS
MODE
REGISTER
0
0
1
0
0
Instruction Fields:
Coprocessor ID field—Specifies which coprocessor in the system is to execute this
instruction. Motorola assemblers default to ID = 1 for the floating-point
coprocessor.
MOTOROLA
M68000 FAMILY PROGRAMMER’S REFERENCE MANUAL
5-113
Floating Point Instructions
FSGLDIV
FSGLDIV
Single-Precision Divide
(MC6888X, MC68040)
Effective Address field—Determines the addressing mode for external operands.
If R/M = 0, this field is unused and should be all zeros.
If R/M = 1, this field is encoded with an M68000 family addressing mode as listed in
the following table:
Addressing Mode
Mode
Register
Addressing Mode
Mode
Register
Dn*
000
reg. number:Dn
(xxx).W
111
000
An
—
—
(xxx).L
111
001
(An)
010
reg. number:An
# < data >
111
100
(An) +
011
reg. number:An
– (An)
100
reg. number:An
(d16,An)
101
reg. number:An
(d16,PC)
111
010
(d8,An,Xn)
110
reg. number:An
(d8,PC,Xn)
111
011
(bd,An,Xn)
110
reg. number:An
(bd,PC,Xn)
111
011
([bd,An,Xn],od)
110
reg. number:An
([bd,PC,Xn],od)
111
011
([bd,An],Xn,od)
110
reg. number:An
([bd,PC],Xn,od)
111
011
*Only if < fmt > is byte, word, long, or single.
R/M field—Specifies the source operand address mode.
0 — The operation is register to register.
1 — The operation is < ea > to register.
Source Specifier field—Specifies the source register or data format.
If R/M = 0, specifies the source floating-point data register.
If R/M = 1, specifies the source data format:
000 — Long-Word Integer (L)
001 — Single-Precision Real (S)
010 — Extended-Precision Real (X)
011 — Packed-Decimal Real (P)
100 — Word Integer (W)
101 — Double-Precision Real (D)
110 — Byte Integer (B)
Destination Register field—Specifies the destination floating- point data register.
5-114
M68000 FAMILY PROGRAMMER’S REFERENCE MANUAL
MOTOROLA
Floating Point Instructions
FSGLMUL
FSGLMUL
Single-Precision Multiply
(MC6888X, MC68040)
Operation:
Source x FPn → FPn
Assembler
Syntax:
FSGLMUL. < fmt > < ea > ,FPn
FSGLMUL.X FPm,FPn
Attributes:
Format = (Byte, Word, Long, Single, Double, Extended, Packed)
Description: Converts the source operand to extended precision (if necessary) and
multiplies that number by the number in the destination floating-point data register.
Stores the result in the destination floating-point data register, rounded to single
precision (regardless of the current rounding precision).
Both the source and destination operands are assumed to be representable in the single-precision format. If either operand requires more than 24 bits of mantissa to be
accurately represented, the extraneous mantissa bits are truncated prior to the multipliction; hence, the accuracy of the result is not guaranteed. Furthermore, the result
exponent may exceed the range of single precision, regardless of the rounding precision selected in the floating-point control register mode control byte. Refer to 3.6.1
Underflow, Round, Overflow for more information.
Operation Table:
DESTINATION
In Range
+
+
–
In Range
– +
Multiply
(Single Precision)
Zero
+ + 0.0
– – 0.0
Infinity
+ + inf
– – inf
SOURCE1
Zero
+ 0.0
– 0.0
Infinity
– 0.0 + inf
+ 0.0 – inf
– 0.0 + 0.0
+ 0.0 – 0.0
– inf
+ inf
– +
– 0.0
+ 0.0
NAN
–
– inf
+ inf
NAN2
+ inf
– inf
– inf
+ inf
NOTES:
1. If the source operand is a NAN, refer to 1.6.5 Not-A-Numbers for more information.
2. Sets the OPERR bit in the floating-point status register exception byte.
NOTE
The input operand mantissas truncate to single precision before
the multiply operation. The result mantissa rounds to single precision despite the rounding precision selected in the floatingpoint control register.
MOTOROLA
M68000 FAMILY PROGRAMMER’S REFERENCE MANUAL
5-115
Floating Point Instructions
FSGLMUL
FSGLMUL
Single-Precision Multiply
(MC6888X, MC68040)
Floating-Point Status Register:
Condition Codes:
Affected as described in 3.6.2 Conditional Testing.
Quotient Byte:
Not affected.
Exception Byte:
BSUN
Cleared
SNAN
OPERR
Refer to 1.6.5 Not-A-Numbers.
Set if one operand is zero and the other is
infinity; cleared otherwise.
Refer to overflow in the appropriate user’s
manual.
Refer to underflow in the appropriate user’s
manual.
Cleared
Refer to inexact result in the appropriate
user’s manual.
If < fmt > is packed, refer to inexact result on
decimal input in the appropriate user’s
manual; cleared otherwise.
OVFL
UNFL
DZ
INEX2
INEX1
Accrued Exception Byte:
Affected as described in IEEE exception and trap compatibility in the appropriate user’s manual.
Instruction Format:
15
14
13
1
1
1
0
R/M
0
12
1
11
9
8
7
6
COPROCESSOR
ID
0
0
0
SOURCE
SPECIFIER
10
DESTINATION
REGISTER
0
5
1
4
3
2
1
0
EFFECTIVE ADDRESS
MODE
REGISTER
0
0
1
1
1
Instruction Fields:
Coprocessor ID field—Specifies which coprocessor in the system is to execute this
instruction. Motorola assemblers default to ID = 1 for the floating-point
coprocessor.
5-116
M68000 FAMILY PROGRAMMER’S REFERENCE MANUAL
MOTOROLA
Floating Point Instructions
FSGLMUL
FSGLMUL
Single-Precision Multiply
(MC6888X, MC68040)
Effective Address field—Determines the addressing mode for external operands.
If R/M = 0, this field is unused and should be all zeros.
If R/M = 1, this field is encoded with an M68000 family addressing mode as listed in
the following table:
Addressing Mode
Mode
Register
Addressing Mode
Mode
Register
Dn*
000
reg. number:Dn
(xxx).W
111
000
An
—
—
(xxx).L
111
001
(An)
010
reg. number:An
# < data >
111
100
(An) +
011
reg. number:An
– (An)
100
reg. number:An
(d16,An)
101
reg. number:An
(d16,PC)
111
010
(d8,An,Xn)
110
reg. number:An
(d8,PC,Xn)
111
011
(bd,An,Xn)
110
reg. number:An
(bd,PC,Xn)
111
011
([bd,An,Xn],od)
110
reg. number:An
([bd,PC,Xn],od)
111
011
([bd,An],Xn,od)
110
reg. number:An
([bd,PC],Xn,od)
111
011
*Only if < fmt > is byte, word, long, or single.
R/M field—Specifies the source operand address mode.
0 — The operation is register to register.
1 — The operation is < ea > to register.
Source Specifier field—Specifies the source register or data format.
If R/M = 0, specifies the source floating-point data register.
If R/M = 1, specifies the source data format:
000 — Long-Word Integer (L)
001 — Single-Precision Real (S)
010 — Extended-Precision Real (X)
011 — Packed-Decimal Real (P)
100 — Word Integer (W)
101 — Double-Precision Real (D)
110 — Byte Integer (B)
Destination Register field—Specifies the destination floating- point data register.
MOTOROLA
M68000 FAMILY PROGRAMMER’S REFERENCE MANUAL
5-117
Floating Point Instructions
FSIN
FSIN
Sine
(MC6888X, M68040FPSP)
Operation:
Sine of Source → FPn
Assembler
Syntax:
FSIN. < fmt > < ea > ,FPn
FSIN.X FPm,FPn
FSIN.X FPn
Attributes:
Format = (Byte, Word, Long, Single, Double, Extended, Packed)
Description: Converts the source operand to extended precision (if necessary) and
calculates the sine of that number. Stores the result in the destination floating-point
data register. This function is not defined for source operands of ± infinity. If the source
operand is not in the range of [ – 2π... + 2π], the argument is reduced to within that
range before the sine is calculated. However, large arguments may lose accuracy
during reduction, and very large arguments (greater than approximately 1020) lose all
accuracy. The result is in the range of [ – 1... + 1].
Operation Table:
DESTINATION
+
In Range
Result
– +
Sine
+ 0.0
SOURCE1
Zero
– +
– 0.0
Infinity
–
NAN2
NOTES:
1. If the source operand is a NAN, refer to 1.6.5 Not-A-Numbers for more information.
2. Sets the OPERR bit in the floating-point status register exception byte.
Floating-Point Status Register:
5-118
Condition Codes:
Affected as described in 3.6.2 Conditional Testing.
Quotient Byte:
Not affected.
M68000 FAMILY PROGRAMMER’S REFERENCE MANUAL
MOTOROLA
Floating Point Instructions
FSIN
FSIN
Sine
(MC6888X, M68040FPSP)
Exception Byte:
BSUN
SNAN
OPERR
Cleared
Refer to 1.6.5 Not-A-Numbers.
Set if the source is ± infinity; cleared
otherwise.
Cleared
Refer to underflow in the appropriate user’s
manual.
Cleared
Refer to inexact result in the appropriate
user’s manual.
If < fmt > is packed, refer to inexact result on
decimal input in the appropriate user’s
manual; cleared otherwise.
OVFL
UNFL
DZ
INEX2
INEX1
Accrued Exception Byte:
Affected as described in IEEE exception and trap compatibility in the appropriate user’s manual.
Instruction Format:
15
14
13
1
1
1
0
R/M
0
12
1
11
9
8
7
6
COPROCESSOR
ID
0
0
0
SOURCE
SPECIFIER
10
DESTINATION
REGISTER
0
5
0
4
3
2
1
0
EFFECTIVE ADDRESS
MODE
REGISTER
0
1
1
1
0
Instruction Fields:
Coprocessor ID field—Specifies which coprocessor in the system is to execute this
instruction. Motorola assemblers default to ID = 1 for the floating-point
coprocessor.
MOTOROLA
M68000 FAMILY PROGRAMMER’S REFERENCE MANUAL
5-119
Floating Point Instructions
FSIN
FSIN
Sine
(MC6888X, M68040FPSP)
Effective Address field—Determines the addressing mode for external operands.
If R/M = 0, this field is unused and should be all zeros.
If R/M = 1, this field is encoded with an M68000 family addressing mode as listed in
the following table:
Addressing Mode
Mode
Register
Addressing Mode
Mode
Register
Dn*
000
reg. number:Dn
(xxx).W
111
000
An
—
—
(xxx).L
111
001
(An)
010
reg. number:An
# < data >
111
100
(An) +
011
reg. number:An
– (An)
100
reg. number:An
(d16,An)
101
reg. number:An
(d16,PC)
111
010
(d8,An,Xn)
110
reg. number:An
(d8,PC,Xn)
111
011
(bd,An,Xn)
110
reg. number:An
(bd,PC,Xn)
111
011
([bd,An,Xn],od)
110
reg. number:An
([bd,PC,Xn],od)
111
011
([bd,An],Xn,od)
110
reg. number:An
([bd,PC],Xn,od)
111
011
*Only if < fmt > is byte, word, long, or single.
R/M field—Specifies the source operand address mode.
0 — The operation is register to register.
1 — The operation is < ea > to register.
Source Specifier field—Specifies the source register or data format.
If R/M = 0, specifies the source floating-point data register.
If R/M = 1, specifies the source data format:
000 — Long-Word Integer (L)
001 — Single-Precision Real (S)
010 — Extended-Precision Real (X)
011 — Packed-Decimal Real (P)
100 — Word Integer (W)
101 — Double-Precision Real (D)
110 — Byte Integer (B)
Destination Register field—Specifies the destination floating- point data register. If R/
M = 0 and the source and destination fields are equal, then the input operand is
taken from the specified floating-point data register, and the result is written into
the same register. If the single register syntax is used, Motorola assemblers set
the source and destination fields to the same value.
5-120
M68000 FAMILY PROGRAMMER’S REFERENCE MANUAL
MOTOROLA
Floating Point Instructions
FSINCOS
FSINCOS
Simultaneous Sine and Cosine
(MC6888X, M68040FPSP)
Operation:
Sine of Source → FPs
Cosine of Source → FPc
Assembler
Syntax:
FSINCOS. < fmt > < ea > ,FPc,FPs
FSINCOS.X FPm,FPc,FPs
Attributes:
Format = (Byte, Word, Long, Single, Double, Extended, Packed)
Description: Converts the source operand to extended precision (if necessary) and
calculates both the sine and the cosine of that number. Calculates both functions
simultaneously; thus, this instruction is significantly faster than performing separate
FSIN and FCOS instructions. Loads the sine and cosine results into the destination
floating-point data register. Sets the condition code bits according to the sine result. If
FPs and FPc are specified to be the same register, the cosine result is first loaded into
the register and then is overwritten with the sine result. This function is not defined for
source operands of ± infinity.
If the source operand is not in the range of [ – 2π... + 2π], the argument is reduced to
within that range before the sine and cosine are calculated. However, large arguments
may lose accuracy during reduction, and very large arguments (greater than approximately 1020) lose all accuracy. The results are in the range of [ – 1... + 1].
Operation Table:
DESTINATION
+
In Range
FPs
Sine
FPc
Cosine
– +
SOURCE1
Zero
+ 0.0
– +
– 0.0
+ 1.0
Infinity
–
NAN2
NAN2
NOTES:
1. If the source operand is a NAN, refer to 1.6.5 Not-A-Numbers for more information.
2. Sets the OPERR bit in the floating-point status register exception byte.
MOTOROLA
M68000 FAMILY PROGRAMMER’S REFERENCE MANUAL
5-121
Floating Point Instructions
FSINCOS
FSINCOS
Simultaneous Sine and Cosine
(MC6888X, M68040FPSP)
Floating-Point Status Register:
Condition Codes:
Affected as described in 3.6.2 Conditional Testing (for the
sine result).
Quotient Byte:
Not affected.
Exception Byte:
BSUN
SNAN
OPERR
Cleared
Refer to 1.6.5 Not-A-Numbers.
Set if the source is ± infinity; cleared
otherwise.
Cleared
Set if a sine underflow occurs, in which case
the cosine result is 1. Cosine cannot
underflow. Refer to underflow in the
appropriate user’s manual.
Cleared
Refer to inexact result in the appropriate
user’s manual.
If < fmt > is packed, refer to inexact result on
decimal input in the appropriate user’s
manual; cleared otherwise.
OVFL
UNFL
DZ
INEX2
INEX1
Accrued Exception Byte:
Affected as described in IEEE exception and trap compatibility in the appropriate user’s manual.
Instruction Format:
15
14
13
1
1
1
0
R/M
0
12
1
11
9
8
7
6
COPROCESSOR
ID
0
0
0
SOURCE
SPECIFIER
10
DESTINATION
REGISTER, FPs
0
5
1
4
3
2
1
0
EFFECTIVE ADDRESS
MODE
REGISTER
DESTINATION
1
0
REGISTER FPc
Instruction Fields:
Coprocessor ID field—Specifies which coprocessor in the system is to execute this
instruction. Motorola assemblers default to ID = 1 for the floating-point
coprocessor.
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M68000 FAMILY PROGRAMMER’S REFERENCE MANUAL
MOTOROLA
Floating Point Instructions
FSINCOS
Simultaneous Sine and Cosine
(MC6888X, M68040FPSP)
FSINCOS
Effective Address field—Determines the addressing mode for external operands.
If R/M = 0, this field is unused and should be all zeros.
If R/M = 1, this field is encoded with an M68000 family addressing mode as listed in
the following table:
Addressing Mode
Mode
Register
Addressing Mode
Mode
Register
Dn*
000
reg. number:Dn
(xxx).W
111
000
An
—
—
(xxx).L
111
001
(An)
010
reg. number:An
# < data >
111
100
(An) +
011
reg. number:An
– (An)
100
reg. number:An
(d16,An)
101
reg. number:An
(d16,PC)
111
010
(d8,An,Xn)
110
reg. number:An
(d8,PC,Xn)
111
011
(bd,An,Xn)
110
reg. number:An
(bd,PC,Xn)
111
011
([bd,An,Xn],od)
110
reg. number:An
([bd,PC,Xn],od)
111
011
([bd,An],Xn,od)
110
reg. number:An
([bd,PC],Xn,od)
111
011
*Only if < fmt > is byte, word, long, or single.
R/M field—Specifies the source operand address mode.
0 — The operation is register to register.
1 — The operation is < ea > to register.
Source Specifier field—Specifies the source register or data format.
If R/M = 0, specifies the source floating-point data register.
If R/M = 1, specifies the source data format:
000 — Long-Word Integer (L)
001 — Single-Precision Real (S)
010 — Extended-Precision Real (X)
011 — Packed-Decimal Real (P)
100 — Word Integer (W)
101 — Double-Precision Real (D)
110 — Byte Integer (B)
Destination Register, FPc field—Specifies the destination floating- point data register,
FPc. The cosine result is stored in this register.
MOTOROLA
M68000 FAMILY PROGRAMMER’S REFERENCE MANUAL
5-123
Floating Point Instructions
FSINCOS
Simultaneous Sine and Cosine
(MC6888X, M68040FPSP)
FSINCOS
Destination Register, FPs field—Specifies the destination floating- point data register, FPs.
The sine result is stored in this register. If FPc and FPs specify the same floating-point
data register, the sine result is stored in the register, and the cosine result is discarded.
If R/M = 0 and the source register field is equal to either of the destination register
fields, the input operand is taken from the specified floating-point data register, and the
appropriate result is written into the same register.
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M68000 FAMILY PROGRAMMER’S REFERENCE MANUAL
MOTOROLA
Floating Point Instructions
FSINH
FSINH
Hyperbolic Sine
(MC6888X, M68040FPSP)
Operation:
Hyperbolic Sine of Source → FPn
Assembler
Syntax:
FSINH. < fmt > < ea > ,FPn
FSINH.X FPm,FPn
FSINH.X FPn
Attributes:
Format = (Byte, Word, Long, Single, Double, Extended, Packed)
Description: Converts the source operand to extended precision (if necessary) and
calculates the hyperbolic sine of that number. Stores the result in the destination
floating-point data register.
Operation Table:
DESTINATION
Result
+
In Range
– +
Hyperbolic Sine
+ 0.0
SOURCE
Zero
– +
– 0.0 + inf
Infinity
–
– inf
NOTE: If the source operand is a NAN, refer to 1.6.5 Not-A-Numbers for more information.
Floating-Point Status Register:
Condition Codes:
Affected as described in 3.6.2 Conditional Testing.
Quotient Byte:
Not affected.
Exception Byte:
BSUN
SNAN
OPERR
OVFL
UNFL
DZ
INEX2
INEX1
Accrued Exception Byte:
MOTOROLA
Cleared
Refer to 1.6.5 Not-A-Numbers.
Cleared
Refer to overflow in the appropriate user’s
manual.
Refer to underflow in the appropriate user’s
manual.
Cleared
Refer to inexact result in the appropriate
user’s manual.
If < fmt > is packed, refer to inexact result on
decimal input in the appropriate user’s
manual; cleared otherwise.
Affected as described in IEEE exception and trap compatibility in the appropriate user’s manual.
M68000 FAMILY PROGRAMMER’S REFERENCE MANUAL
5-125
Floating Point Instructions
FSINH
FSINH
Hyperbolic Sine
(MC6888X, M68040FPSP)
Instruction Format:
15
14
13
1
1
1
0
R/M
0
12
1
11
9
8
7
6
COPROCESSOR
ID
10
0
0
0
SOURCE
SPECIFIER
DESTINATION
REGISTER
0
5
0
4
3
2
1
0
EFFECTIVE ADDRESS
MODE
REGISTER
0
0
0
1
0
Instruction Fields:
Coprocessor ID field—Specifies which coprocessor in the system is to execute this
instruction. Motorola assemblers default to ID = 1 for the floating-point
coprocessor.
Effective Address field—Determines the addressing mode for external operands.
If R/M = 0, this field is unused and should be all zeros.
If R/M = 1, this field is encoded with an M68000 family addressing mode as listed in
the following table:
Addressing Mode
Mode
Register
Addressing Mode
Mode
Register
Dn*
000
reg. number:Dn
(xxx).W
111
000
An
—
—
(xxx).L
111
001
(An)
010
reg. number:An
# < data >
111
100
(An) +
011
reg. number:An
– (An)
100
reg. number:An
(d16,An)
101
reg. number:An
(d16,PC)
111
010
(d8,An,Xn)
110
reg. number:An
(d8,PC,Xn)
111
011
(bd,An,Xn)
110
reg. number:An
(bd,PC,Xn)
111
011
([bd,An,Xn],od)
110
reg. number:An
([bd,PC,Xn],od)
111
011
([bd,An],Xn,od)
110
reg. number:An
([bd,PC],Xn,od)
111
011
*Only if < fmt > is byte, word, long, or single.
5-126
M68000 FAMILY PROGRAMMER’S REFERENCE MANUAL
MOTOROLA
Floating Point Instructions
FSINH
Hyperbolic Sine
(MC6888X, M68040FPSP)
FSINH
R/M field—Specifies the source operand address mode.
0 — The operation is register to register.
1 — The operation is < ea > to register.
Source Specifier field—Specifies the source register or data format.
If R/M = 0, specifies the source floating-point data register.
If R/M = 1, specifies the source data format:
000 — Long-Word Integer (L)
001 — Single-Precision Real (S)
010 — Extended-Precision Real (X)
011 — Packed-Decimal Real (P)
100 — Word Integer (W)
101 — Double-Precision Real (D)
110 — Byte Integer (B)
Destination Register field—Specifies the destination floating- point data register. If R/
M = 0 and the source and destination fields are equal, the input operand is taken
from the specified floating-point data register, and the result is written into the
same register. If the single register syntax is used, Motorola assemblers set the
source and destination fields to the same value.
MOTOROLA
M68000 FAMILY PROGRAMMER’S REFERENCE MANUAL
5-127
Floating Point Instructions
FSQRT
FSQRT
Floating-Point Square Root
(MC6888X, MC68040)
Operation:
Square Root of Source → FPn
Assembler
Syntax:
FSQRT. < fmt > < ea > ,FPn
FSQRT.X FPm,FPn
FSQRT.X FPn
*FrSQRT. < fmt > < ea > ,FPn
*FrSQRT FPm,FPn
*FrSQRT FPn
where r is rounding precision, S or D
*Supported by MC68040 only
Attributes:
Format = (Byte, Word, Long, Single, Double, Extended, Packed)
Description: Converts the source operand to extended precision (if necessary) and
calculates the square root of that number. Stores the result in the destination floatingpoint data register. This function is not defined for negative operands.
FSQRT will round the result to the precision selected in the floating-point control register. FSFSQRT and FDFSQRT will round the result to single or double precision,
respectively, regardless of the rounding precision selected in the floating-point control
register.Operation Table:
DESTINATION
Result
+
In Range
x
– +
NAN2 + 0.0
SOURCE1
Zero
– +
– 0.0 + inf
Infinity
–
NAN2
NOTES:
1. If the source operand is a NAN, refer to 1.6.5 Not-A-Numbers for more information.
2. Sets the OPERR bit in the floating-point status register exception byte.
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M68000 FAMILY PROGRAMMER’S REFERENCE MANUAL
MOTOROLA
Floating Point Instructions
FSQRT
FSQRT
Floating-Point Square Root
(MC6888X, MC68040)
Floating-Point Status Register:
Condition Codes:
Affected as described in 3.6.2 Conditional Testing.
Quotient Byte:
Not affected.
Exception Byte:
BSUN
SNAN
OPERR
Cleared
Refer to 1.6.5 Not-A-Numbers.
Set if the source operand is not zero and is
negative; cleared otherwise.
Cleared
Cleared
Cleared
Refer to exception processing in the
appropriate user’s manual.
If < fmt > is packed, refer to exception
processing in the appropriate user’s manual;
cleared otherwise.
OVFL
UNFL
DZ
INEX2
INEX1
Accrued Exception Byte:
Affected as described in exception processing in the appropriate user’s manual.
Instruction Format:
15
14
13
1
1
1
0
R/M
0
MOTOROLA
12
1
11
9
8
7
6
COPROCESSOR
ID
0
0
0
SOURCE
SPECIFIER
10
DESTINATION
REGISTER
5
4
3
2
1
0
EFFECTIVE ADDRESS
MODE
REGISTER
OPMODE
M68000 FAMILY PROGRAMMER’S REFERENCE MANUAL
5-129
Floating Point Instructions
FSQRT
FSQRT
Floating-Point Square Root
(MC6888X, MC68040)
Instruction Fields:
Effective Address field—Determines the addressing mode for external operands.
If R/M = 0, this field is unused and should be all zeros.
If R/M = 1, specifies the location of the source operand. Only data addressing modes
can be used as listed in the following table:
Addressing Mode
Mode
Register
Addressing Mode
Mode
Register
Dn*
000
reg. number:Dn
(xxx).W
111
000
An
—
—
(xxx).L
111
001
(An)
010
reg. number:An
# < data >
111
100
(An) +
011
reg. number:An
– (An)
100
reg. number:An
(d16,An)
101
reg. number:An
(d16,PC)
111
010
(d8,An,Xn)
110
reg. number:An
(d8,PC,Xn)
111
011
(bd,An,Xn)
110
reg. number:An
(bd,PC,Xn)
111
011
([bd,An,Xn],od)
110
reg. number:An
([bd,PC,Xn],od)
111
011
([bd,An],Xn,od)
110
reg. number:An
([bd,PC],Xn,od)
111
011
*Only if < fmt > is byte, word, long, or single.
R/M field—Specifies the source operand address mode.
0 — The operation is register to register.
1 — The operation is < ea > to register.
Source Specifier field—Specifies the source register or data format.
If R/M = 0, specifies the source floating-point data register.
If R/M = 1, specifies the source data format:
000 — Long-Word Integer (L)
001 — Single-Precision Real (S)
010 — Extended-Precision Real (X)
011 — Packed-Decimal Real (P)*
100 — Word Integer (W)
101 — Double-Precision Real (D)
110 — Byte Integer (B)
*This encoding will cause an unimplemented data type exception in the
MC68040 to allow emulation in software.
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M68000 FAMILY PROGRAMMER’S REFERENCE MANUAL
MOTOROLA
Floating Point Instructions
FSQRT
Floating-Point Square Root
(MC6888X, MC68040)
FSQRT
Destination Register field—Specifies the destination floating- point data register. If R/
M = 0 and the source and destination fields are equal, the input operand is taken
from the specified floating-point data register, and the result is written into the
same register. If the single register syntax is used, Motorola assemblers set the
source and destination fields to the same value.
Opmode field—Specifies the instruction and rounding precision.
0000100 FSQRT
Rounding precision specified by the floating-point
control register.
1000001 FSSQRT Single-precision rounding specified.
1000101 FDSQRT Double-precision rounding specified.
MOTOROLA
M68000 FAMILY PROGRAMMER’S REFERENCE MANUAL
5-131
Floating Point Instructions
FSUB
FSUB
Floating-Point Subtract
(MC6888X, MC68040)
FPn – Source → FPn
Operation:
Assembler
Syntax:
FSUB. < fmt > < ea > ,FPn
FSUB.X FPm,FPn
*FrSUB. < fmt > < ea > ,FPn
*FrSUB.X FPm,FPn
where r is rounding precision, S or D
*Supported by MC68040 only
Attributes:
Format = (Byte, Word, Long, Single, Double, Extended, Packed)
Description: Converts the source operand to extended precision (if necessary) and
subtracts that number from the number in the destination floating-point data register.
Stores the result in the destination floating-point data register.
Operation Table:
DESTINATION
+
In Range
In Range
+
–
Subtract
Zero
+
–
Subtract
Infinity
+
–
+ inf
– inf
– +
SOURCE1
Zero
Subtract
+ 0.02
+ 0.0
+ inf
– inf
– +
Infinity
–
– inf
+ inf
+ 0.0 – inf
+ 0.02
+ inf
NAN2
– inf
– inf
NAN2
NOTES:
1. If the source operand is a NAN, refer to 1.6.5 Not-A-Numbers for more information.
2. Returns + 0.0 in rounding modes RN, RZ, and RP; returns – 0.0 in RM.
3. Sets the OPERR bit in the floating-point status register exception byte.
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M68000 FAMILY PROGRAMMER’S REFERENCE MANUAL
MOTOROLA
Floating Point Instructions
FSUB
FSUB
Floating-Point Subtract
(MC6888X, MC68040)
Floating-Point Status Register:
Condition Codes:
Affected as described in 3.6.2 Conditional Testing.
Quotient Byte:
Not affected.
Exception Byte:
BSUN
SNAN
OPERR
Cleared
Refer to 1.6.5 Not-A-Numbers.
Set if both the source and destination are
like-signed infinities; cleared otherwise.
Refer to exception processing in the
appropriate user’s manual.
Refer to exception processing in the
appropriate user’s manual.
Cleared
Refer to exception processing in the
appropriate user’s manual.
If < fmt > is packed, refer to exception
processing in the appropriate user’s manual;
cleared otherwise.
OVFL
UNFL
DZ
INEX2
INEX1
Accrued Exception Byte:
Affected as described in IEEE exception and trap compatibility in the appropriate user’s manual.
Instruction Format:
15
14
13
1
1
1
0
R/M
0
MOTOROLA
12
1
11
9
8
7
6
COPROCESSOR
ID
0
0
0
SOURCE
SPECIFIER
10
DESTINATION
REGISTER
5
4
3
2
1
0
EFFECTIVE ADDRESS
MODE
REGISTER
OPMODE
M68000 FAMILY PROGRAMMER’S REFERENCE MANUAL
5-133
Floating Point Instructions
FSUB
FSUB
Floating-Point Subtract
(MC6888X, MC68040)
Instruction Fields:
Effective Address field—Determines the addressing mode for external operands.
If R/M = 0, this field is unused and should be all zeros.
If R/M = 1, specifies the location of the source operand. Only data addressing modes
can be used as listed in the following table:
Addressing Mode
Mode
Register
Addressing Mode
Mode
Register
Dn*
000
reg. number:Dn
(xxx).W
111
000
An
—
—
(xxx).L
111
001
(An)
010
reg. number:An
# < data >
111
100
(An) +
011
reg. number:An
– (An)
100
reg. number:An
(d16,An)
101
reg. number:An
(d16,PC)
111
010
(d8,An,Xn)
110
reg. number:An
(d8,PC,Xn)
111
011
(bd,An,Xn)
110
reg. number:An
(bd,PC,Xn)
111
011
([bd,An,Xn],od)
110
reg. number:An
([bd,PC,Xn],od)
111
011
([bd,An],Xn,od)
110
reg. number:An
([bd,PC],Xn,od)
111
011
*Only if < fmt > is byte, word, long, or single.
R/M field—Specifies the source operand address mode.
0 — The operation is register to register.
1 — The operation is < ea > to register.
Source Specifier field—Specifies the source register or data format.
If R/M = 0, specifies the source floating-point data register.
If R/M = 1, specifies the source data format:
000 — Long-Word Integer (L)
001 — Single-Precision Real (S)
010 — Extended-Precision Real (X)
011 — Packed-Decimal Real (P)*
100 — Word Integer (W)
101 — Double-Precision Real (D)
110 — Byte Integer (B)
*This encoding will cause an unimplemented data type exception in the
MC68040 to allow emulation in software.
5-134
M68000 FAMILY PROGRAMMER’S REFERENCE MANUAL
MOTOROLA
Floating Point Instructions
FSUB
Floating-Point Subtract
(MC6888X, MC68040)
FSUB
Destination Register field—Specifies the destination floating- point data register.
Opmode field—Specifies the instruction and rounding precision.
0101000 FSUB
1101000 FSSUB
1101100 FDSUB
MOTOROLA
Rounding precision specified by the floating- point
control register.
Single-precision rounding specified.
Double-precision rounding specified.
M68000 FAMILY PROGRAMMER’S REFERENCE MANUAL
5-135
Floating Point Instructions
FTAN
FTAN
Tangent
(MC6888X/004SW)
Operation:
Tangent of Source → FPn
Assembler
Syntax:
FTAN. < fmt > < ea > ,FPn
FTAN.X FPm,FPn
FTAN.X FPn
Attributes:
Format = (Byte, Word, Long, Single, Double, Extended, Packed)
Description: Converts the source operand to extended precision (if necessary) and
calculates the tangent of that number. Stores the result in the destination floating-point
data register. This function is not defined for source operands of ± infinity. If the source
operand is not in the range of [ – π/2... + π/2], the argument is reduced to within that
range before the tangent is calculated. However, large arguments may lose accuracy
during reduction, and very large arguments (greater than approximately 1020) lose all
accuracy.
Operation Table:
DESTINATION
Result
+
In Range
Tangent
– +
+ 0.0
SOURCE1
Zero
– +
– 0.0
Infinity
–
NAN2
NOTES:
1. If the source operand is a NAN, refer to 1.6.5 Not-A-Numbers for more information.
2. Sets the OPERR bit in the floating-point status register exception byte.
5-136
M68000 FAMILY PROGRAMMER’S REFERENCE MANUAL
MOTOROLA
Floating Point Instructions
FTAN
FTAN
Tangent
(MC6888X/004SW)
Floating-Point Status Register:
Condition Codes:
Affected as described in 3.6.2 Conditional Testing.
Quotient Byte:
Not affected.
Exception Byte:
BSUN
SNAN
OPERR
Cleared
Refer to 1.6.5 Not-A-Numbers.
Set if the source is ± infinity; cleared
otherwise.
Refer to overflow in the appropriate user’s
manual.
Refer to underflow in the appropriate user’s
manual.
Cleared
Refer to inexact result in the appropriate
user’s manual.
If < fmt > is packed, refer to inexact result on
decimal input in the appropriate user’s
manual; cleared otherwise.
OVFL
UNFL
DZ
INEX2
INEX1
Accrued Exception Byte:
Affected as described in IEEE exception and trap compatibility in the appropriate user’s manual.
Instruction Format:
15
14
13
1
1
1
0
R/M
0
12
1
11
9
8
7
6
COPROCESSOR
ID
0
0
0
SOURCE
SPECIFIER
10
DESTINATION
REGISTER
0
5
0
4
3
2
1
0
EFFECTIVE ADDRESS
MODE
REGISTER
0
1
1
1
1
Instruction Fields:
Coprocessor ID field—Specifies which coprocessor in the system is to execute this
instruction. Motorola assemblers default to ID = 1 for the floating-point
coprocessor.
MOTOROLA
M68000 FAMILY PROGRAMMER’S REFERENCE MANUAL
5-137
Floating Point Instructions
FTAN
FTAN
Tangent
(MC6888X/004SW)
Effective Address field—Determines the addressing mode for external operands.
If R/M = 0, this field is unused and should be all zeros.
If R/M = 1, this field is encoded with an M68000 family addressing mode as listed in
the following table:
Addressing Mode
Mode
Register
Addressing Mode
Mode
Register
Dn*
000
reg. number:Dn
(xxx).W
111
000
An
—
—
(xxx).L
111
001
(An)
010
reg. number:An
# < data >
111
100
(An) +
011
reg. number:An
– (An)
100
reg. number:An
(d16,An)
101
reg. number:An
(d16,PC)
111
010
(d8,An,Xn)
110
reg. number:An
(d8,PC,Xn)
111
011
(bd,An,Xn)
110
reg. number:An
(bd,PC,Xn)
111
011
([bd,An,Xn],od)
110
reg. number:An
([bd,PC,Xn],od)
111
011
([bd,An],Xn,od)
110
reg. number:An
([bd,PC],Xn,od)
111
011
*Only if < fmt > is byte, word, long, or single.
R/M field—Specifies the source operand address mode.
0 — The operation is register to register.
1 — The operation is < ea > to register.
Source Specifier field—Specifies the source register or data format.
If R/M = 0, specifies the source floating-point data register.
If R/M = 1, specifies the source data format:
000 — Long-Word Integer (L)
001 — Single-Precision Real (S)
010 — Extended-Precision Real (X)
011 — Packed-Decimal Real (P)
100 — Word Integer (W)
101 — Double-Precision Real (D)
110 — Byte Integer (B)
Destination Register field—Specifies the destination floating- point data register. If R/
M = 0 and the source and destination fields are equal, the input operand is taken
from the specified floating-point data register, and the result is written into the
same register. If the single register syntax is used, Motorola assemblers set the
source and destination fields to the same value.
5-138
M68000 FAMILY PROGRAMMER’S REFERENCE MANUAL
MOTOROLA
Floating Point Instructions
FTANH
FTANH
Hyperbolic Tangent
(MC6888X, M68040FPSP)
Operation:
Hyperbolic Tangent of Source → FPn
Assembler
Syntax:
FTANH. < fmt > < ea > ,FPn
FTANH.X FPm,FPn
FTANH.X FPn
Attributes:
Format = (Byte, Word, Long, Single, Double, Extended, Packed)
Description: Converts the source operand to extended precision (if necessary) and
calculates the hyperbolic tangent of that number. Stores the result in the destination
floating-point data register.
Operation Table:
DESTINATION
+
Result
In Range
– +
Hyperbolic Tangent
+ 0.0
SOURCE
Zero
– +
– 0.0 + 1.0
Infinity
–
– 1.0
NOTE: If the source operand is a NAN, refer to 1.6.5 Not-A-Numbers for more information.
Floating-Point Status Register:
Condition Codes:
Affected as described in 3.6.2 Conditional Testing.
Quotient Byte:
Not affected.
Exception Byte:
BSUN
SNAN
OPERR
OVFL
UNFL
DZ
INEX2
INEX1
Accrued Exception Byte:
MOTOROLA
Cleared
Refer to 1.6.5 Not-A-Numbers.
Cleared
Cleared
Refer to underflow in the appropriate user’s
manual.
Cleared
Refer to inexact result in the appropriate
user’s manual.
If < fmt > is packed, refer to inexact result on
decimal input in the appropriate user’s
manual; cleared otherwise.
Affected as described in IEEE exception and trap compatibility in the appropriate user’s manual.
M68000 FAMILY PROGRAMMER’S REFERENCE MANUAL
5-139
Floating Point Instructions
FTANH
FTANH
Hyperbolic Tangent
(MC6888X, M68040FPSP)
Instruction Format:
15
14
13
1
1
1
0
R/M
0
12
1
11
9
8
7
6
COPROCESSOR
ID
10
0
0
0
SOURCE
SPECIFIER
DESTINATION
REGISTER
0
5
4
3
2
1
0
EFFECTIVE ADDRESS
MODE
REGISTER
0
0
1
0
0
1
Instruction Fields:
Coprocessor ID field—Specifies which coprocessor in the system is to execute this
instruction. Motorola assemblers default to ID = 1 for the floating-point
coprocessor.
Effective Address field—Determines the addressing mode for external operands.
If R/M = 0, this field is unused and should be all zeros.
If R/M = 1, this field is encoded with an M68000 family addressing mode as listed in
the following table:
Addressing Mode
Mode
Register
Addressing Mode
Mode
Register
Dn*
000
reg. number:Dn
(xxx).W
111
000
An
—
—
(xxx).L
111
001
(An)
010
reg. number:An
# < data >
111
100
(An) +
011
reg. number:An
– (An)
100
reg. number:An
(d16,An)
101
reg. number:An
(d16,PC)
111
010
(d8,An,Xn)
110
reg. number:An
(d8,PC,Xn)
111
011
(bd,An,Xn)
110
reg. number:An
(bd,PC,Xn)
111
011
([bd,An,Xn],od)
110
reg. number:An
([bd,PC,Xn],od)
111
011
([bd,An],Xn,od)
110
reg. number:An
([bd,PC],Xn,od)
111
011
*Only if < fmt > is byte, word, long, or single.
R/M field—Specifies the source operand address mode.
0 — The operation is register to register.
1 — The operation is < ea > to register.
5-140
M68000 FAMILY PROGRAMMER’S REFERENCE MANUAL
MOTOROLA
Floating Point Instructions
FTANH
Hyperbolic Tangent
(MC6888X, M68040FPSP)
FTANH
Source Specifier field—Specifies the source register or data format.
If R/M = 0, specifies the source floating-point data register.
If R/M = 1, specifies the source data format:
000 — Long-Word Integer (L)
001 — Single-Precision Real (S)
010 — Extended-Precision Real (X)
011 — Packed-Decimal Real (P)
100 — Word Integer (W)
101 — Double-Precision Real (D)
110 — Byte Integer (B)
Destination Register field—Specifies the destination floating- point data register. If R/
M = 0 and the source and destination fields are equal, the input operand is taken
from the specified floating-point data register, and the result is written into the
same register. If the single register syntax is used, Motorola assemblers set the
source and destination fields to the same value.
MOTOROLA
M68000 FAMILY PROGRAMMER’S REFERENCE MANUAL
5-141
Floating Point Instructions
FTENTOX
FTENTOX
10x
(MC6888X, M68040FPSP)
Operation:
10Source → FPn
Assembler
Syntax:
FTENTOX. < fmt > < ea > ,FPn
FTENTOX.X FPm,FPn
FTENTOX.X FPn
Attributes:
Format = (Byte, Word, Long, Single, Double, Extended, Packed)
Description: Converts the source operand to extended precision (if necessary) and
calculates 10 to the power of that number. Stores the result in the destination floatingpoint data register.
Operation Table:
DESTINATION
+
In Range
– +
10x
Result
SOURCE
Zero
+ 1.0
– +
+ inf
Infinity
–
+ 0.0
NOTE: If the source operand is a NAN, refer to 1.6.5 Not-A-Numbers for more information.
Floating-Point Status Register:
Condition Codes:
Affected as described in 3.6.2 Conditional Testing.
Quotient Byte:
Not affected.
Exception Byte:
BSUN
SNAN
OPERR
OVFL
UNFL
DZ
INEX2
INEX1
Accrued Exception Byte:
5-142
Cleared
Refer to 1.6.5 Not-A-Numbers.
Cleared
Refer to overflow in the appropriate user’s
manual.
Refer to underflow in the appropriate user’s
manual.
Cleared
Refer to inexact result in the appropriate
user’s manual.
If < fmt > is packed, refer to the appropriate
user’s manual inexact result on decimal
input; cleared otherwise.
Affected as described in IEEE exception and trap compatibility in the appropriate user’s manual.
M68000 FAMILY PROGRAMMER’S REFERENCE MANUAL
MOTOROLA
Floating Point Instructions
FTENTOX
FTENTOX
10x
(MC6888X, M68040FPSP)
Instruction Format:
15
14
13
1
1
1
0
R/M
0
12
1
11
9
8
7
6
COPROCESSOR
ID
10
0
0
0
SOURCE
SPECIFIER
DESTINATION
REGISTER
0
5
0
4
3
2
1
0
EFFECTIVE ADDRESS
MODE
REGISTER
1
0
0
1
0
Instruction Fields:
Coprocessor ID field—Specifies which coprocessor in the system is to execute this
instruction. Motorola assemblers default to ID = 1 for the floating-point
coprocessor.
Effective Address field—Determines the addressing mode for external operands.
If R/M = 0, this field is unused and should be all zeros.
If R/M = 1, this field is encoded with an M68000 family addressing mode as listed in
the following table:
Addressing Mode
Mode
Register
Addressing Mode
Mode
Register
Dn*
000
reg. number:Dn
(xxx).W
111
000
An
—
—
(xxx).L
111
001
(An)
010
reg. number:An
# < data >
111
100
(An) +
011
reg. number:An
– (An)
100
reg. number:An
(d16,An)
101
reg. number:An
(d16,PC)
111
010
(d8,An,Xn)
110
reg. number:An
(d8,PC,Xn)
111
011
(bd,An,Xn)
110
reg. number:An
(bd,PC,Xn)
111
011
([bd,An,Xn],od)
110
reg. number:An
([bd,PC,Xn],od)
111
011
([bd,An],Xn,od)
110
reg. number:An
([bd,PC],Xn,od)
111
011
*Only if < fmt > is byte, word, long, or single.
MOTOROLA
M68000 FAMILY PROGRAMMER’S REFERENCE MANUAL
5-143
Floating Point Instructions
FTENTOX
10x
(MC6888X, M68040FPSP)
FTENTOX
R/M field—Specifies the source operand address mode.
0 — The operation is register to register.
1 — The operation is < ea > to register.
Source Specifier field—Specifies the source register or data format.
If R/M = 0, specifies the source floating-point data register.
If R/M = 1, specifies the source data format:
000 — Long-Word Integer (L)
001 — Single-Precision Real (S)
010 — Extended-Precision Real (X)
011 — Packed-Decimal Real (P)
100 — Word Integer (W)
101 — Double-Precision Real (D)
110 — Byte Integer (B)
Destination Register field—Specifies the destination floating- point data register. If R/
M = 0 and the source and destination fields are equal, the input operand is taken
from the specified floating-point data register, and the result is written into the
same register. If the single register syntax is used, Motorola assemblers set the
source and destination fields to the same value.
5-144
M68000 FAMILY PROGRAMMER’S REFERENCE MANUAL
MOTOROLA
Floating Point Instructions
FTRAPcc
Trap on Floating-Point Condition
(MC6888X, MC68040)
Operation:
If Condition True
Then TRAP
Assembler
Syntax:
FTRAPcc
FTRAPcc.W # < data >
FTRAPcc.L # < data >
Attributes:
Size = (Word, Long)
FTRAPcc
Description: If the selected condition is true, the processor initiates exception processing.
A vector number is generated to reference the TRAPcc exception vector. The stacked
program counter points to the next instruction. If the selected condition is not true, there
is no operation performed and execution continues with the next instruction in
sequence. The immediate data operand is placed in the word(s) following the
conditional predicate word and is available for user definition for use within the trap
handler.
The conditional specifier cc selects one of the 32 conditional tests defined in 3.6.2
Conditional Testing.
Floating-Point Status Register:
Condition Codes:
Not affected.
Quotient Byte:
Not affected.
Exception Byte:
BSUN
SNAN
OPERR
OVFL
UNFL
DZ
INEX2
INEX1
Accrued Exception Byte:
MOTOROLA
Set if the NAN condition code is set and the
condition selected is an IEEE nonaware test.
Not Affected.
Not Affected.
Not Affected.
Not Affected.
Not Affected.
Not Affected.
Not Affected.
The IOP bit is set if the BSUN bit is set in the exception
byte; no other bit is affected.
M68000 FAMILY PROGRAMMER’S REFERENCE MANUAL
5-145
Floating Point Instructions
FTRAPcc
Trap on Floating-Point Condition
(MC6888X, MC68040)
FTRAPcc
Instruction Format:
15
14
1
1
0
0
13
12
11
10
9
8
7
6
5
4
3
2
1
COPROCESSOR
1
1
0
0
1
1
1
1
MODE
ID
0
0
0
0
0
0
0
0
CONDITIONAL PREDICATE
16-BIT OPERAND OR MOST SIGNIFICANT WORD OF 32-BIT OPERAND (IFNEEDED)
LEAST SIGNIFICANT WORD OR 32-BIT OPERAND (IF NEEDED)
0
Instruction Fields:
Mode field—Specifies the form of the instruction.
010 — The instruction is followed by a word operand.
011 — The instruction is followed by a long-word operand.
100 — The instruction has no operand.
Conditional Predicate field—Specifies one of 32 conditional tests as described in 3.6.2
Conditional Testing.
Operand field—Contains an optional word or long-word operand that is user defined.
NOTE
When a BSUN exception occurs, a preinstruction exception is
taken by the main processor. If the exception handler returns
without modifying the image of the program counter on the stack
frame (to point to the instruction following the FTRAPcc), it must
clear the cause of the exception (by clearing the NAN bit or disabling the BSUN trap), or the exception occurs again immediately upon return to the routine that caused the exception.
5-146
M68000 FAMILY PROGRAMMER’S REFERENCE MANUAL
MOTOROLA
Floating Point Instructions
FTST
FTST
Test Floating-Point Operand
(MC6888X, MC68040)
Operation:
Condition Codes for Operand → FPCC
Assembler
Syntax:
FTST. < fmt > < ea >
FTST.X FPm
Attributes:
Format = (Byte, Word, Long, Single, Double, Extended, Packed)
Description: Converts the source operand to extended precision (if necessary) and sets the
condition code bits according to the data type of the result.
Operation Table: The contents of this table differfromtheother operation tables. A letter in
an entry of this table indicates that the designated condition code bit is always set by
the FTST operation. All unspecified condition code bits are cleared during the
operation.
DESTINATION
+
In Range
none
Result
– +
N Z
SOURCE
Zero
– +
NZ I
Infinity
–
NI
NOTE: If the source operand is a NAN, set the NAN condition code bit. If the source
operand is an SNAN, set the SNAN bit in the floating-point status register
exception byte
Floating-Point Status Register:
Condition Codes:
Affected as described in 3.6.2 Conditional Testing.
Quotient Byte:
Not affected.
Exception Byte:
BSUN
SNAN
OPERR
OVFL
UNFL
DZ
INEX2
INEX1
Accrued Exception Byte:
Affected as described in exception processing in the appropriate user’s manual.
MOTOROLA
Cleared
Refer to 1.6.5 Not-A-Numbers.
Cleared
Cleared
Cleared
Cleared
Cleared
If < fmt > is packed, refer to exception
processing in the appropriate user’s manual;
cleared otherwise.
M68000 FAMILY PROGRAMMER’S REFERENCE MANUAL
5-147
Floating Point Instructions
FTST
FTST
Test Floating-Point Operand
(MC6888X, MC68040)
Instruction Format:
15
14
13
1
1
1
0
R/M
0
12
1
11
9
8
7
6
COPROCESSOR
ID
10
0
0
0
SOURCE
SPECIFIER
DESTINATION
REGISTER
0
5
1
4
3
2
1
0
EFFECTIVE ADDRESS
MODE
REGISTER
1
1
0
1
0
Instruction Fields:
Effective Address field—Determines the addressing mode for external operands.
If R/M = 0, this field is unused and should be all zeros.
If R/M = 1, specifies the location of the source operand. Only data addressing modes
can be used as listed in the following table:
Addressing Mode
Mode
Register
Addressing Mode
Mode
Register
Dn*
000
reg. number:Dn
(xxx).W
111
000
An
—
—
(xxx).L
111
001
(An)
010
reg. number:An
# < data >
111
100
(An) +
011
reg. number:An
– (An)
100
reg. number:An
(d16,An)
101
reg. number:An
(d16,PC)
111
010
(d8,An,Xn)
110
reg. number:An
(d8,PC,Xn)
111
011
(bd,An,Xn)
110
reg. number:An
(bd,PC,Xn)
111
011
([bd,An,Xn],od)
110
reg. number:An
([bd,PC,Xn],od)
111
011
([bd,An],Xn,od)
110
reg. number:An
([bd,PC],Xn,od)
111
011
*Only if < fmt > is byte, word, long, or single.
5-148
M68000 FAMILY PROGRAMMER’S REFERENCE MANUAL
MOTOROLA
Floating Point Instructions
FTST
Test Floating-Point Operand
(MC6888X, MC68040)
FTST
R/M field—Specifies the source operand address mode.
0 — The operation is register to register.
1 — The operation is < ea > to register.
Source Specifier field—Specifies the source register or data format.
If R/M = 0, specifies the source floating-point data register.
If R/M = 1, specifies the source data format:
000 — Long-Word Integer (L)
001 — Single-Precision Real (S)
010 — Extended-Precision Real (X)
011 — Packed-Decimal Real (P)*
100 — Word Integer (W)
101 — Double-Precision Real (D)
110 — Byte Integer (B)
*This encoding will cause an unimplemented data type exception in the
MC68040 to allow emulation in software.
Destination Register field—Since the floating-point unit uses a common command
word format for all of the arithmetic instructions (including FTST), this field is
treated in the same manner for FTST as for the other arithmetic instructions, even
though the destination register is not modified. This field should be set to zero to
maintain compatibility with future devices; however, the floating-point unit does
not signal an illegal instruction trap if it is not zero.
MOTOROLA
M68000 FAMILY PROGRAMMER’S REFERENCE MANUAL
5-149
Floating Point Instructions
FTWOTOX
FTWOTOX
2x
(MC6888X, M68040FPSP)
Operation:
2Source → FPn
Assembler
Syntax:
FTWOTOX. < fmt > < ea > ,FPn
FTWOTOX.X FPm,FPn
FTWOTOX.X FPn
Attributes:
Format = (Byte, Word, Long, Single, Double, Extended, Packed)
Description: Converts the source operand to extended precision (if necessary) and
calculates two to the power of that number. Stores the result in the destination floatingpoint data register.
Operation Table:
DESTINATION
+
In Range
– +
2x
Result
SOURCE
Zero
+ 1.0
– +
+ inf
Infinity
–
+ 0.0
NOTE: If the source operand is a NAN, refer to 1.6.5 Not-A-Numbers for more information.
Floating-Point Status Register:
Condition Codes:
Affected as described in 3.6.2 Conditional Testing.
Quotient Byte:
Not affected.
Exception Byte:
BSUN
SNAN
OPERR
OVFL
UNFL
DZ
INEX2
INEX1
Accrued Exception Byte:
5-150
Cleared
Refer to 1.6.5 Not-A-Numbers.
Cleared
Refer to overflow in the appropriate user’s
manual.
Refer to underflow in the appropriate user’s
manual.
Cleared
Refer to inexact result in the appropriate
user’s manual.
If < fmt > is packed, refer to inexact result on
decimal input in the appropriate user’s
manual; cleared otherwise.
Affected as described in IEEE exception and trap compatibility in the appropriate user’s manual.
M68000 FAMILY PROGRAMMER’S REFERENCE MANUAL
MOTOROLA
Floating Point Instructions
FTWOTOX
FTWOTOX
2x
(MC6888X, M68040FPSP)
Instruction Format:
15
14
13
1
1
1
0
R/M
0
12
1
11
9
8
7
6
COPROCESSOR
ID
10
0
0
0
SOURCE
SPECIFIER
DESTINATION
REGISTER
0
5
4
3
2
1
0
EFFECTIVE ADDRESS
MODE
REGISTER
0
1
0
0
0
1
Instruction Fields:
Coprocessor ID field—Specifies which coprocessor in the system is to execute this
instruction. Motorola assemblers default to ID = 1 for the floating-point
coprocessor.
Effective Address field—Determines the addressing mode for external operands.
If R/M = 0, this field is unused and should be all zeros.
If R/M = 1, this field is encoded with an M68000 family addressing mode as listed in
the following table:
Addressing Mode
Mode
Register
Addressing Mode
Mode
Register
Dn*
000
reg. number:Dn
(xxx).W
111
000
An
—
—
(xxx).L
111
001
(An)
010
reg. number:An
# < data >
111
100
(An) +
011
reg. number:An
– (An)
100
reg. number:An
(d16,An)
101
reg. number:An
(d16,PC)
111
010
(d8,An,Xn)
110
reg. number:An
(d8,PC,Xn)
111
011
(bd,An,Xn)
110
reg. number:An
(bd,PC,Xn)
111
011
([bd,An,Xn],od)
110
reg. number:An
([bd,PC,Xn],od)
111
011
([bd,An],Xn,od)
110
reg. number:An
([bd,PC],Xn,od)
111
011
*Only if < fmt > is byte, word, long, or single.
MOTOROLA
M68000 FAMILY PROGRAMMER’S REFERENCE MANUAL
5-151
Floating Point Instructions
FTWOTOX
2x
(MC6888X, M68040FPSP)
FTWOTOX
R/M field—Specifies the source operand address mode.
0 — The operation is register to register.
1 — The operation is < ea > to register.
Source Specifier field—Specifies the source register or data format.
If R/M = 0, specifies the source floating-point data register.
If R/M = 1, specifies the source data format:
000 — Long-Word Integer (L)
001 — Single-Precision Real (S)
010 — Extended-Precision Real (X)
011 — Packed-Decimal Real (P)
100 — Word Integer (W)
101 — Double-Precision Real (D)
110 — Byte Integer (B)
Destination Register field—Specifies the destination floating- point data register. If R/
M = 0 and the source and destination fields are equal, the input operand is taken
from the specified floating-point data register, and the result is written into the
same register. If the single register syntax is used, Motorola assemblers set the
source and destination fields to the same value.
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M68000 FAMILY PROGRAMMER’S REFERENCE MANUAL
MOTOROLA
SECTION 6
SUPERVISOR (PRIVILEGED) INSTRUCTIONS
This section contains information about the supervisor privileged instructions for the
M68000 family. Each instruction is described in detail, and the instruction descriptions are
arranged in alphabetical order by instruction mnemonic.
Any differences within the M68000 family of instructions are identified in the instruction. If an
instruction only applies to a certain processor or processors, the processor(s) that the
instruction pertains to is identified under the title of the instruction. For example:
Invalidate Cache Lines
(MC68040)
All references to the MC68000, MC68020, and MC68030 include references to the
corresponding embedded controllers, MC68EC000, MC68EC020, and MC68EC030. All
references to the MC68040 include the MC68LC040 and MC68EC040. This applies
throughout this section unless otherwise specified.
If the instruction applies to all the M68000 family but a processor or processors may use a
different instruction field, instruction format, etc., the differences will be identified within the
paragraph. For example:
MC68020, MC68030 and MC68040 only
(bd,An,Xn)*
110
reg. number: An
(bd,PC,Xn)*
—
—
*Can be used with CPU32 processo
The following instructions are listed separately for each processor due to the many
differences involved within the instruction:
PFLUSH
PMOVE
PTEST
Flush ATC Entries
Move PMMU Register
Test Logical Address
Appendix A Processor Instruction Summary provides a listing of all processors and the
instructions that apply to them for quick reference.
MOTOROLA
M68000 FAMILY PROGRAMMER’S REFERENCE MANUAL
6-1
Supervisor (Privileged) Instructions
ANDI
to SR
ANDI
to SR
AND Immediate to the Status Register
(M68000 Family)
If Supervisor State
Then Source L SR → SR
ELSE TRAP
Operation:
Assembler
Syntax:
ANDI # < data > ,SR
Attributes:
size = (word)
Description: Performs an AND operation of the immediate operand with the contents of the
status register and stores the result in the status register. All implemented bits of the
status register are affected.
Condition Codes:
X
∗
N
∗
Z
∗
V
∗
C
∗
X—Cleared if bit 4 of immediate operand is zero; unchanged otherwise.
N—Cleared if bit 3 of immediate operand is zero; unchanged otherwise.
Z—Cleared if bit 2 of immediate operand is zero; unchanged otherwise.
V—Cleared if bit 1 of immediate operand is zero; unchanged otherwise.
C—Cleared if bit 0 of immediate operand is zero; unchanged otherwise.
Instruction Format:
5
0
6-2
14
0
13
0
12
0
11
0
10
0
9
1
8
7
6
0
0
1
16-BIT WORD DATA
5
1
4
1
3
1
M68000 FAMILY PROGRAMMER’S REFERENCE MANUAL
2
1
1
0
0
0
MOTOROLA
Supervisor (Privileged) Instructions
CINV
Operation:
Assembler
Syntax:
Invalidate Cache Lines
(MC68040, MC68LC040)
CINV
If Supervisor State
Then Invalidate Selected Cache Lines
ELSE TRAP
CINVL < caches > ,(An)
CINVP < caches > ,(An)
CINVA < caches >
Where < caches > specifies the instruction cache,
data cache, both caches, or neither cache.
Attributes:
Unsized
Description: Invalidates selected cache lines. The data cache, instruction cache, both
caches, or neither cache can be specified. Any dirty data in data cache lines that
invalidate are lost; the CPUSH instruction must be used when dirty data may be
contained in the data cache.
Specific cache lines can be selected in three ways:
1. CINVL invalidates the cache line (if any) matching the physical address in the
specified address register.
2. CINVP invalidates the cache lines (if any) matching the physical memory page
in the specified address register. For example, if 4K-byte page sizes are selected and An contains $12345000, all cache lines matching page $12345000 invalidate.
3. CINVA invalidates all cache entries.
Condition Codes:
Not affected.
MOTOROLA
M68000 FAMILY PROGRAMMER’S REFERENCE MANUAL
6-3
Supervisor (Privileged) Instructions
CINV
CINV
Invalidate Cache Lines
(MC68040, MC68LC040)
Instruction Format:
15
1
14
1
13
1
12
1
11
0
10
1
9
0
8
0
7
6
CACHE
5
0
4
3
SCOPE
2
1
0
REGISTER
Instruction Fields:
Cache field—Specifies the Cache.
00—No Operation
01—Data Cache
10—Instruction Cache
11—Data and Instruction Caches
Scope field—Specifies the Scope of the Operation.
00—Illegal (causes illegal instruction trap)
01—Line
10—Page
11—All
Register field—Specifies the address register for line and page operations. For line
operations, the low-order bits 3–0 of the address are don‘t cares. Bits 11–0 or 12–
0 of the address are don‘t care for 4K-byte or 8K-byte page operations,
respectively.
6-4
M68000 FAMILY PROGRAMMER’S REFERENCE MANUAL
MOTOROLA
Supervisor (Privileged) Instructions
cpRESTORE
cpRESTORE
Coprocessor
Restore Functions
(MC68020, MC68030)
If Supervisor State
Then Restore Internal State of Coprocessor
ELSE TRAP
Operation:
Assembler
Syntax:
cpRESTORE < ea >
Attributes:
Unsized
Description: Restores the internal state of a coprocessor usually after it has been saved by
a preceding cpSAVE instruction.
Condition Codes:
Not affected.
Instruction Format:
15
14
13
12
1
1
1
1
MOTOROLA
11
10
9
COPROCESSOR
ID
8
7
6
1
0
1
5
4
3
2
1
0
EFFECTIVE ADDRESS
MODE
REGISTER
M68000 FAMILY PROGRAMMER’S REFERENCE MANUAL
6-5
Supervisor (Privileged) Instructions
cpRESTORE
Coprocessor
Restore Functions
cpRESTORE
(MC68020, MC68030)
Instruction Fields:
Coprocessor ID field—Identifies the coprocessor that is to be restored. Coprocessor ID
of 000 results in an F-line exception for the MC68030.
Effective Address field—Specifies the location where the internal state of the
coprocessor is located. Only postincrement or control addressing modes can be
used as listed in the following table:
Addressing Mode
Mode
Register
Addressing Mode
Mode
Register
Dn
—
—
(xxx).W
111
000
An
—
—
(xxx).L
111
001
(An)
010
reg. number:An
# < data >
111
100
(An) +
011
reg. number:An
— (An)
—
—
(d16,An)
101
reg. number:An
(d16,PC)
111
010
(d8,An,Xn)
110
reg. number:An
(d8,PC,Xn)
111
011
(bd,An,Xn)
110
reg. number:An
(bd,PC,Xn)
111
011
([bd,An,Xn], od)
110
reg. number:An
([bd,PC,Xn], od)
111
011
([bd,An],Xn,od)
110
reg.number:An
([bd,PC],Xn, od
111
011
NOTE
If the format word returned by the coprocessor indicates “come
again”, pending interrupts are not serviced.
6-6
M68000 FAMILY PROGRAMMER’S REFERENCE MANUAL
MOTOROLA
Supervisor (Privileged) Instructions
cpSAVE
cpSAVE
Coprocessor Save Function
(MC68020, MC68030)
If Supervisor State
Then Save Internal State of Coprocessor
ELSE TRAP
Operation:
Assembler
Syntax:
cpSAVE < ea >
Attributes:
Unsized
Description: Saves the internal state of a coprocessor in a format that can be restored by
a cpRESTORE instruction.
Condition Codes:
Not affected.
Instruction Format:
15
14
13
12
1
1
1
1
11
10
9
COPROCESSOR
ID
8
7
6
1
0
0
5
4
3
2
1
0
EFFECTIVE ADDRESS
MODE
REGISTER
Instruction Fields:
Coprocessor ID field—Identifies the coprocessor for this operation. Coprocessor ID of
000 results in an F-line exception for the MC68030.
Effective Address field—Specifies the location where the internal state of the
coprocessor is to be saved. Only predecrement or control alterable addressing
modes can be used as listed in the following table:
MOTOROLA
Addressing Mode
Mode
Register
Addressing Mode
Mode
Register
Dn
—
—
(xxx).W
111
000
An
—
—
(xxx).L
111
001
(An)
010
reg. number:An
# < data >
—
—
(An) +
—
—
— (An)
100
reg. number:An
(d16,An)
101
reg. number:An
(d16,PC)
—
—
(d8,An,Xn)
110
reg. number:An
(d8,PC,Xn)
—
—
(bd,An,Xn)
110
reg. number:An
(bd,PC,Xn)
—
—
([bd,An,Xn], od)
110
reg. number:An
([bd,PC,Xn],od)
—
—
([bd,An],Xn, od)
110
reg. number:An
([bd,PC],Xn, od)
—
—
M68000 FAMILY PROGRAMMER’S REFERENCE MANUAL
6-7
Supervisor (Privileged) Instructions
CPUSH
Push and Invalidate Cache Lines
(MC68040, MC68LC040)
Operation:
If Supervisor State
Then If Data Cache
Then Push Selected Dirty Data Cache Lines
Invalidate Selected Cache Lines
ELSE TRAP
Assembler
Syntax:
CPUSHL < caches > ,(An)
CPUSHP < caches > ,(An)
CPUSHA < caches >
CPUSH
Where < caches > specifies the instruction cache, data cache,
both caches, or neither cache.
Attributes:
Unsized
Description: Pushes and then invalidates selected cache lines. The DATA cache,
instruction cache, both caches, or neither cache can be specified. When the data cache
is specified, the selected data cache lines are first pushed to memory (if they contain
dirty DATA) and then invalidated. Selected instruction cache lines are invalidated.
Specific cache lines can be selected in three ways:
1. CPUSHL pushes and invalidates the cache line (if any) matching the physical
address in the specified address register.
2. CPUSHP pushes and invalidates the cache lines (if any) matching the physical
memory page in the specified address register. For example, if 4K-byte page
sizes are selected and An contains $12345000, all cache lines matching page
$12345000 are selected.
3. CPUSHA pushes and invalidates all cache entries.
Condition Codes:
Not affected.
Instruction Format:
15
1
6-8
14
1
13
1
12
1
11
0
10
1
9
0
8
0
7
6
CACHE
5
1
4
3
SCOPE
M68000 FAMILY PROGRAMMER’S REFERENCE MANUAL
2
1
0
REGISTER
MOTOROLA
Supervisor (Privileged) Instructions
CPUSH
Push and Invalidate Cache Lines
(MC68040, MC68LC040)
CPUSH
Instruction Fields:
Cache field—Specifies the Cache.
00—No Operation
01—Data Cache
10—Instruction Cache
11—Data and Instruction Caches
Scope field—Specifies the Scope of the Operation.
00—Illegal (causes illegal instruction trap)
01—Line
10—Page
11—All
Register field—Specifies the address register for line and page operations. For line
operations, the low-order bits 3–0 of the address are don‘t care. Bits 11–0 or 12–
0 of the address are don‘t care for 4K-byte or 8K-byte page operations,
respectively.
MOTOROLA
M68000 FAMILY PROGRAMMER’S REFERENCE MANUAL
6-9
Supervisor (Privileged) Instructions
EORI
to SR
EORI
to SR
Exclusive-OR Immediate to the Status Register
(M68000 Family)
Operation:
If Supervisor State
Then Source ⊕ SR → SR
ELSE TRAP
Assembler
Syntax:
EORI # < data > ,SR
Attributes:
Size = (Word)
Description: Performs an exclusive-OR operation on the contents of the status register
using the immediate operand and stores the result in the status register. All
implemented bits of the status register are affected.
Condition Codes:
X
∗
N
∗
Z
∗
V
∗
C
∗
X—Changed if bit 4 of immediate operand is one; unchanged otherwise.
N—Changed if bit 3 of immediate operand is one; unchanged otherwise.
Z—Changed if bit 2 of immediate operand is one; unchanged otherwise.
V—Changed if bit 1 of immediate operand is one; unchanged otherwise.
C—Changed if bit 0 of immediate operand is one; unchanged otherwise.
Instruction Format:
15
0
6-10
14
0
13
0
12
0
11
1
10
0
9
1
8
7
6
0
0
1
16-BIT WORD DATA
5
1
4
1
3
1
M68000 FAMILY PROGRAMMER’S REFERENCE MANUAL
2
1
1
0
0
0
MOTOROLA
Supervisor (Privileged) Instructions
FRESTORE
Restore Internal
Floating-Point State
FRESTORE
(MC68881, MC68882, MC68040 only)
Operation:
If in Supervisor State
Then FPU State Frame → Internal State
ELSE TRAP
Assembler
Syntax:
FRESTORE < ea >
Attributes:
Unsized
Description: Aborts the execution of any floating-point operation in progress and loads a
new floating-point unit internal state from the state frame located at the effective
address. The first word at the specified address is the format word of the state frame.
It specifies the size of the frame and the revision number of the floating-point unit that
created it. A format word is invalid if it does not recognize the size of the frame or the
revision number does not match the revision of the floating-point unit. If the format word
is invalid, FRESTORE aborts, and a format exception is generated. If the format word
is valid, the appropriate state frame is loaded, starting at the specified location and
proceeding through higher addresses.
The FRESTORE instruction does not normally affect the programmer’s model registers
of the floating-point coprocessor, except for the NULL state size, as described below.
It is only for restoring the user invisible portion of the machine. The FRESTORE
instruction is used with the FMOVEM instruction to perform a full context restoration of
the floating-point unit, including the floating- point data registers and system control
registers. To accomplish a complete restoration, the FMOVEM instructions are first
executed to load the programmer’s model, followed by the FRESTORE instruction to
load the internal state and continue any previously suspended operation.
MOTOROLA
M68000 FAMILY PROGRAMMER’S REFERENCE MANUAL
6-11
Supervisor (Privileged) Instructions
FRESTORE
Restore Internal
Floating-Point State
FRESTORE
(MC68881, MC68882, MC68040 only)
The current implementation supports the following four state frames:
NULL:
This state frame is 4 bytes long, with a format word of $0000. An FRESTORE operation with this size state frame is equivalent to a hardware reset
of the floating-point unit. The programmer’s model is set to the reset state,
with nonsignaling NANs in the floating-point data registers and zeros in the
floating-point control register, floating-point status register, and floatingpoint instruction address register. (Thus, it is unnecessary to load the programmer’s model before this operation.)
IDLE:
This state frame is 4 bytes long in the MC68040, 28 ($1C) bytes long in the
MC68881, and 60 ($3C) bytes long in the MC68882. An FRESTORE operation with this state frame causes the floating-point unit to be restored to the
idle state, waiting for the initiation of the next instruction, with no exceptions
pending. The programmer’s model is not affected by loading this type of
state frame.
UNIMP:
This state frame is generated only by the MC68040. It is 48 ($30) bytes long.
An FSAVE that generates this size frame indicates either an unimplemented
floating-point instruction or only an E1 exception is pending. This frame is
never generated when an unsupported data type exception is pending or an
E3 exception is pending. If both E1 and E3 exceptions are pending, a BUSY
frame is generated.
BUSY:
This state frame is 96 ($60) bytes long in the MC68040, 184 ($B8) bytes long
in the MC68881, and 216 ($D8) bytes long in the MC68882. An FRESTORE
operation with this size state frame causes the floating-point unit to be
restored to the busy state, executing the instructions that were suspended
by a previous FSAVE operation. The programmer’s model is not affected by
loading this type of state frame; however, the completion of the suspended
instructions after the restore is executed may modify the programmer’s
model.
Floating-Point Status Register: Cleared if the state size is NULL; otherwise, not affected.
6-12
M68000 FAMILY PROGRAMMER’S REFERENCE MANUAL
MOTOROLA
Supervisor (Privileged) Instructions
FRESTORE
FRESTORE
Restore Internal
Floating-Point State
(MC68881, MC68882, MC68040 only)
Instruction Format:
15
14
13
12
1
1
1
1
11
10
9
COPROCESSOR
ID
8
7
6
1
0
1
5
4
3
2
1
0
EFFECTIVE ADDRESS
MODE
REGISTER
Instruction Field:
Effective Address field—Determines the addressing mode for the state frame. Only
postincrement or control addressing modes can be used as listed in the following
table:
MOTOROLA
Addressing Mode
Mode
Register
Addressing Mode
Mode
Register
Dn
—
—
(xxx).W
111
000
An
—
—
(xxx).L
111
001
(An)
010
reg. number:An
# < data >
—
—
(An) +
011
reg. number:An
—(An)
—
—
(d16,An)
101
reg. number:An
(d16,PC)
111
010
(d8,An,Xn)
110
reg. number:An
(d8,PC,Xn)
111
011
(bd,An,Xn)
110
reg. number:An
(bd,PC,Xn)
111
011
([bd,An,Xn], od)
110
reg. number:An
([bd,PC,Xn], od)
111
011
([bd,An],Xn, od)
110
reg. number:An
([bd,PC],Xn, od)
111
011
M68000 FAMILY PROGRAMMER’S REFERENCE MANUAL
6-13
Supervisor (Privileged) Instructions
FSAVE
Operation:
Save Internal Floating-Point State
(MC68881, MC68882, MC68040 only)
FSAVE
If in Supervisor State
Then FPU Internal State → State Frame
ELSE TRAP
Assembler
Syntax:
FSAVE < ea >
Attributes:
Unsized
Description: FSAVE allows the completion of any floating-point operation in progress for
the MC68040. It saves the internal state of the floating-point unit in a state frame
located at the effective address. After the save operation, the floating-point unit is in the
idle state, waiting for the execution of the next instruction. The first word written to the
state frame is the format word specifying the size of the frame and the revision number
of the floating-point unit.
Any floating-point operations in progress when an FSAVE instruction is encountered
can be completed before the FSAVE executes, saving an IDLE state frame. Execution
of instructions already in the floating-point unit pipeline continues until completion of all
instructions in the pipeline or generation of an exception by one of the instructions. An
IDLE state frame is created by the FSAVE if no exceptions occurred; otherwise, a
BUSY or an UNIMP stack frame is created.
FSAVE suspends the execution of any operation in progress and saves the internal
state in a state frame located at the effective address for the MC68881/MC68882. After
the save operation, the floating-point coprocessor is in the idle state, waiting for the
execution of the next instruction. The first word written to the state frame is the format
word, specifying the size of the frame and the revision number of the floating-point
coprocessor. The microprocessor unit initiates the FSAVE instruction by reading the
floating-point coprocessor save CIR. The floating-point coprocessor save CIR is
encoded with a format word that indicates the appropriate action to be taken by the
main processor. The current implementation of the floating-point coprocessor always
returns one of five responses in the save CIR:
Value
Definition
$0018
Save NULL state frame
$0118
Not ready, come again
$0218
Illegal, take format exception
$XX18
Save IDLE state frame
$XXB4
Save BUSY state frame
NOTE: XX is the floating-point coprocessor version
number.
6-14
M68000 FAMILY PROGRAMMER’S REFERENCE MANUAL
MOTOROLA
Supervisor (Privileged) Instructions
FSAVE
Save Internal Floating-Point State
(MC68881, MC68882, MC68040 only)
FSAVE
The not ready format word indicates that the floating-point coprocessor is not prepared
to perform a state save and that the microprocessor unit should process interrupts, if
necessary, and re-read the save CIR. The floating-point coprocessor uses this format
word to cause the main processor to wait while an internal operation completes, if possible, to allow an IDLE frame rather than a BUSY frame to be saved. The illegal format
word aborts an FSAVE instruction that is attempted while the floating-point coprocessor executes a previous FSAVE instruction. All other format words cause the microprocessor unit to save the indicated state frame at the specified address. For state frame
details see state frames in the appropriate user’s manual.
The following state frames apply to both the MC68040 and the MC68881/MC68882.
NULL:
This state frame is 4 bytes long. An FSAVE instruction that generates this
state frame indicates that the floating-point unit state has not been modified
since the last hardware reset or FRESTORE instruction with a NULL state
frame. This indicates that the programmer’s model is in the reset state, with
nonsignaling NANs in the floating-point data registers and zeros in the floating- point control register, floating-point status register, and floating-point
instruction address register. (Thus, it is not necessary to save the programmer’s model.)
IDLE:
This state frame is 4 bytes long in the MC68040, 28 ($1C) bytes long in the
MC68881, and 60 ($3C) bytes long in the MC68882. An FSAVE instruction
that generates this state frame indicates that the floating-point unit finished
in an idle condition and is without any pending exceptions waiting for the initiation of the next instruction.
UNIMP:
This state frame is generated only by the MC68040. It is 48 ($30) bytes long.
An FSAVE that generates this size frame indicates either an unimplemented
floating-point instruction or that only an E1 exception is pending. This frame
is never generated when an unsupported data type exception or an E3
exception is pending. If both E1 and E3 exceptions are pending, a BUSY
frame is generated.
BUSY:
This state frame is 96 ($60) bytes long in the MC68040, 184 ($B8) bytes long
in the MC68881, and 216 ($D8) bytes long in the MC68882. An FSAVE
instruction that generates this size state frame indicates that the floatingpoint unit encountered an exception while attempting to complete the execution of the previous floating-point instructions.
MOTOROLA
M68000 FAMILY PROGRAMMER’S REFERENCE MANUAL
6-15
Supervisor (Privileged) Instructions
FSAVE
Save Internal Floating-Point State
(MC68881, MC68882, MC68040 only)
FSAVE
The FSAVE does not save the programmer’s model registers of the floating-point unit;
it saves only the user invisible portion of the machine. The FSAVE instruction may be
used with the FMOVEM instruction to perform a full context save of the floating-point
unit that includes the floating-point data registers and system control registers. To
accomplish a complete context save, first execute an FSAVE instruction to suspend
the current operation and save the internal state, then execute the appropriate
FMOVEM instructions to store the programmer’s model.
Floating-Point Status Register: Not affected.
Instruction Format:
15
14
13
12
1
1
1
1
11
10
9
COPROCESSOR
ID
8
7
6
1
0
0
5
4
3
2
1
0
EFFECTIVE ADDRESS
MODE
REGISTER
Instruction Field:
Effective Address field—Determines the addressing mode for the state frame. Only
predecrement or control alterable addressing modes can be used as listed in the
following table:
6-16
Addressing Mode
Mode
Register
Addressing Mode
Mode
Register
Dn
—
—
(xxx).W
111
000
An
—
—
(xxx).L
111
001
(An)
010
reg. number:An
# < data >
—
—
(An) +
—
—
—(An)
100
reg. number:An
(d16,An)
101
reg. number:An
(d16,PC)
—
—
(d8,An,Xn)
110
reg. number:An
(d8,PC,Xn)
—
—
(bd,An,Xn)
110
reg. number:An
(bd,PC,Xn)
—
—
([bd,An,Xn] ,od)
110
reg. number:An
([bd,PC,Xn] ,od)
—
—
([bd,An],Xn ,od)
110
reg. number:An
([bd,PC],Xn ,od)
—
—
M68000 FAMILY PROGRAMMER’S REFERENCE MANUAL
MOTOROLA
Supervisor (Privileged) Instructions
MOVE
from SR
MOVE
from SR
Move from the Status Register
(MC68EC000, MC68010, MC68020,
MC68030, MC68040, CPU32)
Operation:
If Supervisor State
Then SR → Destination
Else TRAP
Assembler
Syntax:
MOVE SR, < ea >
Attributes:
Size = (Word)
Description: Moves the data in the status register to the destination location. The
destination is word length. Unimplemented bits are read as zeros.
Condition Codes:
Not affected.
Instruction Format:
15
14
13
12
11
10
9
8
7
6
0
1
0
0
0
0
0
0
1
1
MOTOROLA
5
4
3
2
1
0
EFFECTIVE ADDRESS
MODE
REGISTER
M68000 FAMILY PROGRAMMER’S REFERENCE MANUAL
6-17
Supervisor (Privileged) Instructions
MOVE
from SR
Move from the Status Register
(MC68EC000, MC68010, MC68020,
MC68030, MC68040, CPU32)
MOVE
from SR
Instruction Field:
Effective Address field—Specifies the destination location. Only data alterable
addressing modes can be used as listed in the following tables:
Addressing Mode
Mode
Register
Addressing Mode
Mode
Register
Dn
000
reg. number:Dn
(xxx).W
111
000
An
—
—
(xxx).L
111
001
(An)
010
reg. number:An
# < data >
—
—
(An) +
011
reg. number:An
—(An)
100
reg. number:An
(d16,An)
101
reg. number:An
(d16,PC)
—
—
(d8,An,Xn)
110
reg. number:An
(d8,PC,Xn)
—
—
MC68020, MC68030, and MC68040 only
(bd,An,Xn)*
110
reg. number:An
(bd,PC,Xn)*
—
—
([bd,An,Xn] ,od)
110
reg. number:An
([bd,PC,Xn] ,od)
—
—
([bd,An],Xn ,od)
110
reg. number:An
([bd,PC],Xn ,od)
—
—
*Available for the CPU32.
NOTE
Use the MOVE from CCR instruction to access only the
condition codes.
6-18
M68000 FAMILY PROGRAMMER’S REFERENCE MANUAL
MOTOROLA
Supervisor (Privileged) Instructions
MOVE
to SR
MOVE
to SR
Move to the Status Register
(M68000 Family)
Operation:
If Supervisor State
Then Source → SR
Else TRAP
Assembler
Syntax:
MOVE < ea > ,SR
Attributes:
Size = (Word)
Description: Moves the data in the source operand to the status register. The source
operand is a word, and all implemented bits of the status register are affected.
Condition Codes:
Set according to the source operand.
Instruction Format:
15
14
13
12
11
10
9
8
7
6
0
1
0
0
0
1
1
0
1
1
MOTOROLA
5
4
3
2
1
0
EFFECTIVE ADDRESS
MODE
REGISTER
M68000 FAMILY PROGRAMMER’S REFERENCE MANUAL
6-19
Supervisor (Privileged) Instructions
MOVE
to SR
MOVE
to SR
Move to the Status Register
(M68000 Family)
Instruction Field:
Effective Address field—Specifies the location of the source operand. Only data
addressing modes can be used as listed in the following tables:
Addressing Mode
Mode
Register
Addressing Mode
Mode
Register
Dn
000
reg. number:Dn
(xxx).W
111
000
An
—
—
(xxx).L
111
001
(An)
010
reg. number:An
# < data >
111
100
(An) +
011
reg. number:An
—(An)
100
reg. number:An
(d16,An)
101
reg. number:An
(d16,PC)
111
010
(d8,An,Xn)
110
reg. number:An
(d8,PC,Xn)
111
011
MC68020, MC68030, and MC68040 only
(bd,An,Xn)*
110
reg. number:An
(bd,PC,Xn)*
111
011
([bd,An,Xn] ,od)
110
reg. number:An
([bd,PC,Xn] ,od)
111
011
([bd,An],Xn ,od)
110
reg. number:An
([bd,PC],Xn ,od)
111
011
*Available for the CPU32.
6-20
M68000 FAMILY PROGRAMMER’S REFERENCE MANUAL
MOTOROLA
Supervisor (Privileged) Instructions
MOVE
USP
MOVE
USP
Move User Stack Pointer
(M68000 Family)
Operation:
If Supervisor State
Then USP → An or An → USP
Else TRAP
Assembler
Syntax:
MOVE USP,An
MOVE An,USP
Attributes:
Size = (Long)
Description: Moves the contents of the user stack pointer to or from the specified address
register.
Condition Codes:
Not affected.
Instruction Format:
15
0
14
1
13
0
12
0
11
1
10
1
9
1
8
0
7
0
6
1
5
1
4
0
3
dr
2
1
0
REGISTER
Instruction Fields:
dr field—Specifies the direction of transfer.
0—Transfer the address register to the user stack pointer.
1—Transfer the user stack pointer to the address register.
Register field—Specifies the address register for the operation.
MOTOROLA
M68000 FAMILY PROGRAMMER’S REFERENCE MANUAL
6-21
Supervisor (Privileged) Instructions
MOVEC
Move Control Register
(MC68010, MC68020, MC68030, MC68040, CPU32)
Operation:
If Supervisor State
Then Rc → Rn or Rn → Rc
Else TRAP
Assembler
Syntax:
MOVEC Rc,Rn
MOVEC Rn,Rc
Attributes:
Size = (Long)
MOVEC
Description: Moves the contents of the specified control register (Rc) to the specified
general register (Rn) or copies the contents of the specified general register to the
specified control register. This is always a 32-bit transfer, even though the control
register may be implemented with fewer bits. Unimplemented bits are read as zeros.
Condition Codes:
Not affected.
Instruction Format:
15
0
A/D
14
1
13
12
0
0
REGISTER
11
1
10
1
9
1
8
0
7
0
6
5
4
1
1
1
CONTROL REGISTER
3
1
2
0
1
1
0
dr
Instruction Fields:
dr field—Specifies the direction of the transfer.
0—Control register to general register.
1—General register to control register.
A/D field—Specifies the type of general register.
0—Data Register
1—Address Rregister
6-22
M68000 FAMILY PROGRAMMER’S REFERENCE MANUAL
MOTOROLA
Supervisor (Privileged) Instructions
MOVEC
Move Control Register
(MC68010, MC68020, MC68030, MC68040, CPU32)
MOVEC
Register field—Specifies the register number.
Control Register field—Specifies the control register.
Hex1
Control Register
MC68010/MC68020/MC68030/MC68040/CPU32
000
Source Function Code (SFC)
001
Destination Function Code (DFC)
800
User Stack Pointer (USP)
801
Vector Base Register (VBR)
MC68020/MC68030/MC68040
002
Cache Control Register (CACR)
802
Cache Address Register (CAAR)2
803
Master Stack Pointer (MSP)
804
Interrupt Stack Pointer (ISP)
MC68040/MC68LC040
003
MMU Translation Control Register (TC)
004
Instruction Transparent Translation Register 0 (ITT0)
005
Instruction Transparent Translation Register 1 (ITT1)
006
Data Transparent Translation Register 0 (DTT0)
007
Data Transparent Translation Register 1 (DTT1)
805
MMU Status Register (MMUSR)
806
User Root Pointer (URP)
807
Supervisor Root Pointer (SRP)
MC68EC040 only
004
Instruction Access Control Register 0 (IACR0)
005
Instruction Access Control Register 1 (IACR1)
006
Data Access Control Register 0 (DACR1)
007
Data Access Control Register 1 (DACR1)
NOTES:
1. Any other code causes an illegal instruction exception
2. For the MC68020 and MC68030 only.
MOTOROLA
M68000 FAMILY PROGRAMMER’S REFERENCE MANUAL
6-23
Supervisor (Privileged) Instructions
MOVES
Move Address Space
(MC68010, MC68020, MC68030, MC68040, CPU32)
MOVES
Operation:
If Supervisor State
Then Rn → Destination [DFC] or Source [SFC] → Rn
Else TRAP
Assembler
Syntax:
MOVES Rn, < ea >
MOVES < ea > ,Rn
Attributes:
Size = (Byte, Word, Long)
Description: This instruction moves the byte, word, or long operand from the specified
general register to a location within the address space specified by the destination
function code (DFC) register, or it moves the byte, word, or long operand from a
location within the address space specified by the source function code (SFC) register
to the specified general register. If the destination is a data register, the source operand
replaces the corresponding low-order bits of that data register, depending on the size
of the operation. If the destination is an address register, the source operand is signextended to 32 bits and then loaded into that address register.
Condition Codes:
Not affected.
Instruction Format:
15
14
13
12
11
10
9
8
0
0
0
0
1
1
1
0
dr
0
0
0
A/D
6-24
REGISTER
7
6
5
0
0
SIZE
0
4
3
2
1
0
EFFECTIVE ADDRESS
MODE
REGISTER
0
0
0
0
0
M68000 FAMILY PROGRAMMER’S REFERENCE MANUAL
MOTOROLA
Supervisor (Privileged) Instructions
MOVES
Move Address Space
(MC68010, MC68020, MC68030, MC68040, CPU32)
MOVES
Instruction Fields:
Size field—Specifies the size of the operation.
00—Byte Operation
01—Word Operation
10—Long Operation
Effective Address field—Specifies the source or destination location within the alternate
address space. Only memory alterable addressing modes can be used as listed in
the following tables:
Addressing Mode
Mode
Register
Addressing Mode
Mode
Register
Dn
—
—
(xxx).W
111
000
An
—
—
(xxx).L
111
001
(An)
010
reg. number:An
# < data >
—
—
(An) +
011
reg. number:An
—(An)
100
reg. number:An
(d16,An)
101
reg. number:An
(d16,PC)
—
—
(d8,An,Xn)
110
reg. number:An
(d8,PC,Xn)
—
—
MC68020, MC68030, and MC68040 only
(bd,An,Xn)*
110
reg. number:An
(bd,PC,Xn)*
—
—
([bd,An,Xn] ,od)
110
reg. number:An
([bd,PC,Xn] ,od)
—
—
([bd,An],Xn ,od)
110
reg. number:An
([bd,PC],Xn ,od)
—
—
*Available for the CPU32.
A/D field—Specifies the type of general register.
0—Data Register
1—Address Register
Register field—Specifies the register number.
dr field—Specifies the direction of the transfer.
0—From < ea > to general register.
1—From general register to < ea > .
MOTOROLA
M68000 FAMILY PROGRAMMER’S REFERENCE MANUAL
6-25
Supervisor (Privileged) Instructions
MOVES
Move Address Space
(MC68010, MC68020, MC68030, MC68040, CPU32)
MOVES
NOTE
The value stored is undefined for either of the two following
examples with the same address register as both source and
destination.
MOVES.x An,(An) +
MOVES.x An,D(An)
The current implementations of the MC68010, MC68020,
MC68030, and MC68040 store the incremented or decremented
value of An. Check the following code sequence to determine
what value is stored for each case.
MOVEA.L #$1000,A0
MOVES.L A0,(A0) +
MOVES.L A0,D(A0)
Because the MC68040 implements a merged instruction and
data space, the MC68040’s integer unit into data references
(SFC/DFC = 5 or 1) translates MOVES accesses to the
OinstructionO address spaces (SFC/DFC = 6 or 2). The data
memory unit handles these translated accesses as normal data
accesses. If the access fails due to an ATC fault or a physical
bus error, the resulting access error stack frame contains the
converted function code in the TM field for the faulted access. To
maintain cache coherency, MOVES accesses to write the
OinstructionO address space must be preceded by invalidation
of the instruction cache line containing the referenced location.
6-26
M68000 FAMILY PROGRAMMER’S REFERENCE MANUAL
MOTOROLA
Supervisor (Privileged) Instructions
ORI
to SR
ORI
to SR
Inclusive-OR Immediate to the Status Register
(M68000 Family)
Operation:
If Supervisor State
Then Source V SR → SR
Else TRAP
Assembler
Syntax:
ORI # < data > ,SR
Attributes:
Size = (Word)
Description: Performs an inclusive-OR operation of the immediate operand and the status
register’s contents and stores the result in the status register. All implemented bits of
the status register are affected.
Condition Codes:
X
∗
N
∗
Z
∗
V
∗
C
∗
X—Set if bit 4 of immediate operand is one; unchanged otherwise.
N—Set if bit 3 of immediate operand is one; unchanged otherwise.
Z—Set if bit 2 of immediate operand is one; unchanged otherwise.
V—Set if bit 1 of immediate operand is one; unchanged otherwise.
C—Set if bit 0 of immediate operand is one; unchanged otherwise.
Instruction Format:
15
0
14
0
MOTOROLA
13
0
12
0
11
0
10
0
9
0
8
7
6
0
0
1
16—BIT WORD DATA
5
1
4
1
3
1
M68000 FAMILY PROGRAMMER’S REFERENCE MANUAL
2
1
1
0
0
0
6-27
Supervisor (Privileged) Instructions
PBcc
PBcc
Branch on PMMU Condition
(MC68851)
Operation:
If Supervisor State
Then If cc True
Then (PC) + dn → PC
Else TRAP
Assembler
Syntax:
PBcc. < size > < label >
Attributes:
Size = (Word, Long)
Description: If the specified paged memory management unit condition is met, execution
continues at location (PC) + displacement. The displacement is a twos complement
integer that counts the relative distance in bytes. The value in the program counter is
the address of the displacement word(s). The displacement may be either 16 or 32 bits.
The condition specifier cc indicates the following conditions:
Specifier
Description Condition Field
Specifier
Description Condition Field
BS
B set
000000
BC
B clear
000001
LS
L set
000010
LC
L clear
000011
SS
S set
000100
SC
S clear
000101
AS
A set
000110
AC
A clear
000111
WS
W set
001000
WC
W clear
001001
IS
I set
001010
IC
I clear
001011
GS
G set
001100
GC
G clear
001101
CS
C set
001110
CC
C clear
001111
PMMU Status Register: Not affected.
Instruction Format:
15
1
6-28
14
1
13
1
12
11
10
9
8
7
6
5
4
3
2
1
1
0
0
0
0
1
SIZE
MC68851 CONDITION
16-BIT DISPLACEMENT OR MOST SIGNIFICANT WORD OF 32-BITDISPLACEMENT
LEAST SIGNIFICANT WORD OF 32-BIT DISPLACEMENT (IF NEEDED)
M68000 FAMILY PROGRAMMER’S REFERENCE MANUAL
0
MOTOROLA
Supervisor (Privileged) Instructions
PBcc
Branch on PMMU Condition
(MC68851)
PBcc
Instruction Fields:
Size field—Specifies the size of the displacement.
0—Displacement is 16 bits.
1—Displacement is 32 bits.
MC68851 Condition field—Specifies the coprocessor condition to be tested. This field
is passed to the MC68851, which provides directives to the main processor for
processing this instruction.
Word Displacement field—The shortest displacement form for MC68851 branches is
16 bits.
Long-Word Displacement field—Allows a displacement larger than 16 bits.
MOTOROLA
M68000 FAMILY PROGRAMMER’S REFERENCE MANUAL
6-29
Supervisor (Privileged) Instructions
PDBcc
Operation:
Test, Decrement, and Branch
(MC68851)
PDBcc
If Supervisor State
Then If cc False
Then (DnD1 → Dn; If Dn < > D1 then (PC) + d 3 PC)
Else No Operation
Else TRAP
Assembler
Syntax:
PDBcc Dn, < label >
Attributes:
Size = (Word)
Description: This instruction is a looping primitive of three parameters: an MC68851
condition, a counter (an MC68020 data register), and a 16-bit displacement. The
instruction first tests the condition to determine if the termination condition for the loop
has been met. If so, the main processor executes the next instruction in the instruction
stream. If the termination condition is not true, the low-order 16 bits of the counter
register are decremented by one. If the result is not D1, execution continues at the
location specified by the current value of the program counter plus the sign-extended
16-bit displacement. The value of the program counter used in the branch address
calculation is the address of the PDBcc instruction plus two.
The condition specifier cc indicates the following conditions:
Specifier
6-30
Description Condition Field
Specifier
Description Condition Field
BS
B set
000000
BC
B clear
000001
LS
L set
000010
LC
L clear
000011
SS
S set
000100
SC
S clear
000101
AS
A set
000110
AC
A clear
000111
WS
W set
001000
WC
W clear
001001
IS
I set
001010
IC
I clear
001011
GS
G set
001100
GC
G clear
001101
CS
C set
001110
CC
C clear
001111
M68000 FAMILY PROGRAMMER’S REFERENCE MANUAL
MOTOROLA
Supervisor (Privileged) Instructions
PDBcc
PDBcc
Test, Decrement, and Branch
(MC68851)
PMMU Status Register:Not affected.
Instruction Format:
15
1
0
14
1
0
13
1
0
12
1
0
11
0
0
10
0
0
9
8
7
6
0
0
0
1
0
0
0
0
16-BIT DISPLACEMENT
5
0
4
0
3
2
1
0
1
COUNT REGISTER
MC68851 CONDITION
Instruction Fields:
Register field—Specifies the data register in the main processor to be used as the
counter.
MC68851 Condition field—Specifies the MC68851 condition to be tested. This field is
passed to the MC68851, which provides directives to the main processor for
processing this instruction.
Displacement field—Specifies the distance of the branch in bytes.
MOTOROLA
M68000 FAMILY PROGRAMMER’S REFERENCE MANUAL
6-31
Supervisor (Privileged) Instructions
PFLUSH
Flush Entry in the ATC
(MC68030 only)
PFLUSH
Operation:
If Supervisor State
Then Invalidate ATC Entries for Destination Addresses
Else TRAP
Assembler
Syntax:
PFLUSHA
PFLUSH FC,MASK
PFLUSH FC,MASK, < ea >
Attributes:
Unsized
Description: PFLUSH invalidates address translation cache entries. The instruction has
three forms. The PFLUSHA instruction invalidates all entries. When the instruction
specifies a function code and mask, the instruction invalidates all entries for a selected
function code(s). When the instruction also specifies an < ea > , the instruction
invalidates the page descriptor for that effective address entry in each selected function
code.
The mask operand contains three bits that correspond to the three function code bits.
Each bit in the mask that is set to one indicates that the corresponding bit of the FC
operand applies to the operation. Each bit in the mask that is zero indicates a bit of FC
and of the ignored function code. For example, a mask operand of 100 causes the
instruction to consider only the most significant bit of the FC operand. If the FC operand
is 001, function codes 000, 001, 010, and 011 are selected.
The FC operand is specified in one of the following ways:
1. Immediate—Three bits in the command word.
2. Data Register—The three least significant bits of the data register specified in
the instruction.
3. Source Function Code (SFC) Register
4. Destination Function Code (DFC) Register
Condition Codes:
Not affected.
MMU Status Register:
Not affected.
6-32
M68000 FAMILY PROGRAMMER’S REFERENCE MANUAL
MOTOROLA
Supervisor (Privileged) Instructions
PFLUSH
PFLUSH
Flush Entry in the ATC
(MC68030 only)
Instruction Format:
15
14
13
12
11
10
9
8
7
6
1
1
1
1
0
0
0
0
0
0
0
0
1
0
0
MODE
MASK
5
4
3
2
1
0
EFFECTIVE ADDRESS
MODE
REGISTER
FC
Instruction Fields:
Effective Address field—Specifies a control alterable address. The address translation
cache entry for this address is invalidated. Valid addressing modes are in the
following table:
Addressing Mode
Mode
Register
Addressing Mode
Mode
Register
Dn
—
—
(xxx).W
111
000
An
—
—
(xxx).L
111
001
(An)
010
reg. number:An
# < data >
—
—
(An) +
—
—
—(An)
—
—
(d16,An)
101
reg. number:An
(d16,PC)
—
—
(d8,An,Xn)
110
reg. number:An
(d8,PC,Xn)
—
—
(bd,An,Xn)
110
reg. number:An
(bd,PC,Xn)
—
—
([bd,An,Xn] ,od)
110
reg. number:An
([bd,PC,Xn] ,od)
—
—
([bd,An],Xn ,od)
110
reg. number:An
([bd,PC],Xn ,od)
—
—
NOTE
The address field must provide the memory management unit
with the effective address to be flushed from the address
translation cache, not the effective address describing where the
PFLUSH operand is located. For example, to flush the address
translation cache entry corresponding to a logical address that
is temporarily stored on top of the system stack, the instruction
PFLUSH [(SP)] must be used since PFLUSH (SP) would
invalidate the address translation cache entry mapping the
system stack (i.e., the effective address passed to the memory
management unit is the effective address of the system stack,
not the effective address formed by the operand located on the
top of the stack).
MOTOROLA
M68000 FAMILY PROGRAMMER’S REFERENCE MANUAL
6-33
Supervisor (Privileged) Instructions
PFLUSH
Flush Entry in the ATC
(MC68030 only)
PFLUSH
Mode field—Specifies the type of flush operation.
001—Flush all entries.
100—Flush by function code only.
110—Flush by function code and effective address.
Mask field—Mask for selecting function codes. Ones in the mask correspond to
applicable bits; zeros are bits to be ignored. When mode is 001, mask must be
000.
FC field—Function code of entries to be flushed. If the mode field is 001, FC field must
be 00000; otherwise:
10XXX — Function code is specified as bits XXX.
01DDD — Function code is specified as bits 2–0 of data register DDD.
00000 — Function code is specified as SFC register.
00001 — Function code is specified as DFC register.
6-34
M68000 FAMILY PROGRAMMER’S REFERENCE MANUAL
MOTOROLA
Supervisor (Privileged) Instructions
PFLUSH
Flush ATC Entries
(MC68040, MC68LC040)
PFLUSH
Operation:
If Supervisor State
Then Invalidate Instruction and Data ATC Entries for Destination
Address
Else TRAP
Assembler
Syntax:
Syntax:
Syntax:
PFLUSH (An)
PFLUSHN (An)
PFLUSHA
PFLUSHAN
Attributes:
Unsized
Description: Invalidates address translation cache entries in both the instruction and data
address translation caches. The instruction has two forms. The PFLUSHA instruction
invalidates all entries. The PFLUSH (An) instruction invalidates the entry in each
address translation cache which matches the logical address in An and the specified
function code.
The function code for PFLUSH is specified in the destination function code register.
Destination function code values of 1 or 2 will result in flushing of user address translation cache entries in both address translation caches; whereas, values of 5 or 6 will
result in flushing of supervisor address translation cache entries. PFLUSH is undefined
for destination function code values of 0, 3, 4, and 7 and may cause flushing of an
unexpected entry.
The PFLUSHN and PFLUSHAN instructions have a global option specified and invalidate only nonglobal entries. For example, if only page descriptors for operating system
code have the global bit set, these two PFLUSH variants can be used to flush only user
address translation cache entries during task swaps.
Condition Codes:
Not affected.
MOTOROLA
M68000 FAMILY PROGRAMMER’S REFERENCE MANUAL
6-35
Supervisor (Privileged) Instructions
PFLUSH
PFLUSH
Flush ATC Entries
(MC68040, MC68LC040)
Instruction Format:
Postincrement Source and Destination
15
1
14
1
13
1
12
1
11
0
10
1
9
0
8
1
7
0
6
0
5
0
4
3
OPMODE
2
1
0
REGISTER
Instruction Fields:
Opmode field—Specifies the flush operation.
Opcode
Operation
00
Flush page entry if not global
01
Flush page entry
10
Flush all except global entries
11
Flush all entries
Assembler Syntax
PFLUSHN (An)
PFLUSH (An)
PFLUSHAN
PFLUSHA
Register field—Specifies the address register containing the effective address to be
flushed when flushing a page entry.
6-36
M68000 FAMILY PROGRAMMER’S REFERENCE MANUAL
MOTOROLA
Supervisor (Privileged) Instructions
PFLUSH
PFLUSH
Flush ATC Entries
(MC68EC040)
Operation:
If Supervisor State
Then No Operation
Else TRAP
Assembler
Syntax:
PFLUSH (An)
PFLUSHN (An)
Attributes:
Unsized
Description: This instruction should not be executed when using an MC68EC040. The
PFLUSH encoding suspends operation of the MC68EC040 for an indefinite period of
time and subsequently continues with no adverse effects.
Condition Codes:
Not affected.
Instruction Format:
Postincrement Source and Destination
15
1
14
1
13
1
12
1
11
0
10
1
9
0
8
1
7
0
6
0
5
0
4
3
OPMODE
2
1
0
REGISTER
Instruction Fields:
Opmode field—Specifies the flush operation.
Opcode
Operation
00
Flush page entry if not global
01
Flush page entry
10
Flush all except global entries
11
Flush all entries
Assembler Syntax
PFLUSHN (An)
PFLUSH (An)
PFLUSHAN
PFLUSHA
Register field—Specifies the address register containing the effective address to be
flushed when flushing a page entry.
MOTOROLA
M68000 FAMILY PROGRAMMER’S REFERENCE MANUAL
6-37
Supervisor (Privileged) Instructions
PFLUSH
PFLUSHA
PFLUSHS
Invalidate Entries in the ATC
(MC68851)
PFLUSH
PFLUSHA
PFLUSHS
Operation:
If Supervisor State
Then Address Translation Cache Entries For Destination Address
Are Invalidated
Else TRAP
Assembler
Syntax:
PFLUSHA
PFLUSH FC,MASK
PFLUSHS FC,MASK
PFLUSH FC,MASK, < ea >
PFLUSHS FC,MASK, < ea >
Attributes:
Unsigned
Description: PFLUSHA invalidates all entries in the address translation cache.
PFLUSH invalidates a set of address translation cache entries whose function code
bits satisfy the relation: (address translation cache function code bits and mask) = (FC
and MASK) for all entries whose task alias matches the task alias currently active when
the instruction is executed. With an additional effective address argument, PFLUSH
invalidates a set of address translation cache entries whose function code satisfies the
relation above and whose effective address field matches the corresponding bits of the
evaluated effective address argument. In both of these cases, address translation
cache entries whose SG bit is set will not be invalidated unless the PFLUSHS is specified.
The function code for this operation may be specified as follows:
1. Immediate—The function code is four bits in the command word.
2. Data Register—The function code is in the lower four bits of the MC68020 data
register specified in the instruction.
3. Source Function Code (SFC) Register—The function code is in the CPU SFC
register. Since the SFC of the MC68020 has only three implemented bits, only
function codes $0D$7 can be specified in this manner.
4. Destination Function Code (DFC) Register—The function code is in the CPU
DFC register. Since the DFC of the MC68020 has only three implemented bits,
only function codes $0D$7 can be specified in this manner.
6-38
M68000 FAMILY PROGRAMMER’S REFERENCE MANUAL
MOTOROLA
Supervisor (Privileged) Instructions
PFLUSH
PFLUSHA
PFLUSHS
PFLUSH
PFLUSHA
PFLUSHS
Invalidate Entries in the ATC
(MC68851)
PMMU Status Register: Not affected.
Instruction Format:
15
14
13
12
11
10
9
8
7
6
1
1
1
1
0
0
0
0
0
0
0
0
1
MODE
0
MASK
5
4
3
2
1
0
EFFECTIVE ADDRESS
MODE
REGISTER
FC
Instruction Fields:
Effective Address field—Specifies an address whose page descriptor is to be flushed
from (invalidated) the address translation cache. Only control alterable addressing
modes can be used as listed in the following table:
MOTOROLA
Addressing Mode
Mode
Register
Addressing Mode
Mode
Register
Dn
—
—
(xxx).W
111
000
An
—
—
(xxx).L
111
001
(An)
010
reg. number:An
# < data >
—
—
(An) +
—
—
—(An)
—
—
(d16,An)
101
reg. number:An
(d16,PC)
—
—
(d8,An,Xn)
110
reg. number:An
(d8,PC,Xn)
—
—
(bd,An,Xn)
110
reg. number:An
(bd,PC,Xn)
—
—
([bd,An,Xn] ,od)
110
reg. number:An
([bd,PC,Xn] ,od)
—
—
([bd,An],Xn ,od)
110
reg. number:An
([bd,PC],Xn ,od)
—
—
M68000 FAMILY PROGRAMMER’S REFERENCE MANUAL
6-39
Supervisor (Privileged) Instructions
PFLUSH
PFLUSHA
PFLUSHS
Invalidate Entries in the ATC
(MC68851)
PFLUSH
PFLUSHA
PFLUSHS
NOTE
The effective address field must provide the MC68851 with the
effective address of the entry to be flushed from the address
translation cache, not the effective address describing where the
PFLUSH operand is located. For example, in order to flush the
address translation cache entry corresponding to a logical
address that is temporarily stored on the top of the system stack,
the instruction PFLUSH [(SP)] must be used since PFLUSH
(SP) would invalidate the address translation cache entry
mapping the system stack (i.e., the effective address passed to
the MC68851 is the effective address of the system stack, not
the effective address formed by the operand located on the top
of the stack).
Mode field—Specifies how the address translation cache is to be flushed.
001—Flush all entries.
100—Flush by function code only.
101—Flush by function code including shared entries.
110—Flush by function code and effective address.
111—Flush by function code and effective address including shared entries.
Mask field—Indicates which bits are significant in the function code compare. A zero
indicates that the bit position is not significant; a one indicates that the bit position
is significant. If mode = 001 (flush all entries), mask must be 0000.
FC field—Function code of address to be flushed. If the mode field is 001 (flush all
entries), function code must be 00000; otherwise:
1DDDD — Function code is specified as four bits DDDD.
01RRR — Function code is contained in CPU data register RRR.
00000 — Function code is contained in CPU SFC register.
00001 — Function code is contained in CPU DFC register.
6-40
M68000 FAMILY PROGRAMMER’S REFERENCE MANUAL
MOTOROLA
Supervisor (Privileged) Instructions
PFLUSHR
Operation:
PFLUSHR
Invalidate ATC and RPT Entries
(MC68851)
If Supervisor State
Then RPT Entry (If Any) Matching Root Pointer Specified by < ea >
Corresponding Address Translation Cache Entries Are Invalidated
Else TRAP
Assembler
Syntax:
PFLUSHR < ea >
Attributes:
Unsized
Description: The quad word pointed to by < ea > is regarded as a previously used value of
the CPU root pointer register. The root pointer table entry matching this CPU root
pointer register (if any) is flushed, and all address translation cache entries loaded with
this value of CPU root pointer register (except for those that are globally shared) are
invalidated. If no entry in the root pointer table matches the operand of this instruction,
no action is taken.
If the supervisor root pointer is not in use, the operating system should not issue the
PFLUSHR command to destroy a task identified by the current CPU root pointer register. It should wait until the CPU root pointer register has been loaded with the root
pointer identifying the next task until using the PFLUSHR instruction. At any time, execution of the PFLUSHR instruction for the current CPU root pointer register causes the
current task alias to be corrupted.
Instruction Format:
15
14
13
12
11
10
9
8
7
6
1
1
1
1
0
0
0
0
0
0
1
0
1
0
0
0
0
0
0
0
MOTOROLA
5
0
4
3
2
1
0
EFFECTIVE ADDRESS
MODE
REGISTER
0
0
0
0
0
M68000 FAMILY PROGRAMMER’S REFERENCE MANUAL
6-41
Supervisor (Privileged) Instructions
PFLUSHR
Invalidate ATC and RPT Entries
(MC68851)
PFLUSHR
Instruction Field:
Effective Address field—Specifies the address of a previous value of the CPU root
pointer register register. Only memory addressing modes can be used as listed in
the following table:
Addressing Mode
Mode
Register
Addressing Mode
Mode
Register
Dn
—
—
(xxx).W
111
000
An
—
—
(xxx).L
111
001
(An)
010
reg. number:An
# < data >
111
100
(An) +
011
reg. number:An
—(An)
100
reg. number:An
(d16,An)
101
reg. number:An
(d16,PC)
111
010
(d8,An,Xn)
110
reg. number:An
(d8,PC,Xn)
111
011
(bd,An,Xn)
110
reg. number:An
(bd,PC,Xn)
111
011
([bd,An,Xn] ,od)
110
reg. number:An
([bd,PC,Xn] ,od)
111
011
([bd,An],Xn ,od)
110
reg. number:An
([bd,PC],Xn ,od)
111
011
NOTE
The effective address usage of this instruction is different than
that of other PFLUSH variants.
6-42
M68000 FAMILY PROGRAMMER’S REFERENCE MANUAL
MOTOROLA
Supervisor (Privileged) Instructions
PLOAD
Load an Entry into the ATC
(MC68030 only, MC68851)
PLOAD
Operation:
If Supervisor State
Then Search Translation Table and Make Address Translation
Cache Entry for Effective Address
Else TRAP
Assembler
Syntax:
PLOADR FC, < ea >
PLOADW FC, < ea >
Attributes:
Unsized
Description: For the MC68851, PLOAD searches the translation table for a translation of
the specified effective address. If one is found, it is flushed from the address translation
cache, and an entry is made as if a bus master had run a bus cycle. Used and modified
bits in the table are updated as part of the table search. The MC68851 ignores the
logical bus arbitration signals during the flush and load phases at the end of this
instruction. This prevents the possibility of an entry temporarily disappearing from the
address translation cache and causing a false table search.
This instruction will cause a paged memory management unit illegal operation exception (vector $39) if the E-bit of the translation control register is clear.
The function code for this operation may be specified to be:
1. Immediate—The function code is specified as four bits in the command word.
2. Data Register—The function code is contained in the lower four bits in the
MC68020 data register specified in the instruction.
3. Source Function Code (SFC) Register—The function code is in the CPU SFC
register. Since the SFC of the MC68020 has only three implemented bits, only
function codes $0D$7 can be specified in this manner.
4. Destination Function Code (DFC) Register—The function code is in the CPU
DFC register. Since the DFC of the MC68020 has only three implemented bits,
only function codes $0D$7 can be specified in this manner.
MOTOROLA
M68000 FAMILY PROGRAMMER’S REFERENCE MANUAL
6-43
Supervisor (Privileged) Instructions
PLOAD
PLOAD
Load an Entry into the ATC
(MC68030 only, MC68851)
For the MC68030, PLOAD searches the address translation cache for the specified
effective address. It also searches the translation table for the descriptor corresponding
to the specified effective address. It creates a new entry as if the MC68030 had
attempted to access that address. Sets the used and modified bits appropriately as part
of the search. The instruction executes despite the value of the E-bit in the translation
control register or the state of the MMUDIS signal.
The < function code > operand is specified in one of the following ways:
1. Immediate—Three bits in the command word.
2. Data Register—The three least significant bits of the data register specified in
the instruction.
3. Source Function Code (SFC) Register
4. Destination Function Code (DFC) Register
The effective address field specifies the logical address whose translation is to be
loaded.
PLOADR causes U bits in the translation tables to be updated as if a read access had
occurred. PLOADW causes U and M bits in the translation tables to be updated as if a
write access had occurred.
PMMU Status Register: Not affected.
Instruction Format:
15
14
13
12
11
10
9
8
7
6
1
1
1
1
0
0
0
0
0
0
0
0
1
0
0
0
R/ W
0
0
0
6-44
5
0
4
3
2
1
0
EFFECTIVE ADDRESS
MODE
REGISTER
FC
M68000 FAMILY PROGRAMMER’S REFERENCE MANUAL
MOTOROLA
Supervisor (Privileged) Instructions
PLOAD
PLOAD
Load an Entry into the ATC
(MC68030 only, MC68851)
Instruction Fields:
Effective Address field—Specifies the logical address whose translation is to be loaded
into the address translation cache. Only control alterable addressing modes are
allowed as listed in the following table:
Addressing Mode
Mode
Register
Addressing Mode
Mode
Register
Dn
—
—
(xxx).W
111
000
An
—
—
(xxx).L
111
001
(An)
010
reg. number:An
# < data >
—
—
(An) +
—
—
—(An)
—
—
(d16,An)
101
reg. number:An
(d16,PC)
—
—
(d8,An,Xn)
110
reg. number:An
(d8,PC,Xn)
—
—
(bd,An,Xn)
110
reg. number:An
(bd,PC,Xn)
—
—
([bd,An,Xn] ,od)
110
reg. number:An
([bd,PC,Xn] ,od)
—
—
([bd,An],Xn ,od)
110
reg. number:An
([bd,PC],Xn ,od)
—
—
NOTE
The effective address field must provide the MC68851 with the
effective address of the entry to be loaded into the address
translation cache, not the effective address describing where the
PLOAD operand is located. For example, to load an address
translation cache entry to map a logical address that is
temporarily stored on the system stack, the instruction PLOAD
[(SP)] must be used since PLOAD (SP) would load an address
translation cache entry mapping the system stack (i.e., the
effective address passed to the MC68851 is the effective
address of the system stack, not the effective address formed by
the operand located on the top of the stack).
R/W field—Specifies whether the tables should be updated for a read or a write.
1—Read
0—Write
MOTOROLA
M68000 FAMILY PROGRAMMER’S REFERENCE MANUAL
6-45
Supervisor (Privileged) Instructions
PLOAD
Load an Entry into the ATC
(MC68030 only, MC68851)
PLOAD
FC field (MC68851)—Function code of address to load.
1DDDD — Function code is specified as four bits DDDD.
01RRR — Function code is contained in CPU data register RRR.
00000 — Function code is contained in CPU SFC register.
00001 — Function code is contained in CPU DFC register.
FC field (MC68030)—Function code of address corresponding to entry to be loaded.
10XXX — Function code is specified as bits XXX.
01DDD — Function code is specified as bits 2–0 of data register DDD.
00000 — Function code is specified as SFC register.
00001 — Function code is specified as DFC register.
6-46
M68000 FAMILY PROGRAMMER’S REFERENCE MANUAL
MOTOROLA
Supervisor (Privileged) Instructions
PMOVE
Move to/from MMU Registers
(MC68030 only)
Operation:
If Supervisor State
Then (Source) → MRn or MRn → (Destination)
Assembler
Syntax:
PMOVE MRn, < ea >
PMOVE < ea > ,MRn
PMOVEFD < ea > ,MRn
Attributes:
Size = (Word, Long, Quad)
PMOVE
Description: Moves the contents of the source effective address to the specified memory
management unit register or moves the contents of the memory management unit
register to the destination effective address.
The instruction is a quad-word (8 byte) operation for the CPU root pointer and the
supervisor root pointer. It is a long-word operation for the translation control register
and the transparent translation registers (TT0 and TT1). It is a word operation for the
MMU status register.
The PMOVEFD form of this instruction sets the FD-bit to disable flushing the address
translation cache when a new value loads into the supervisor root pointer, CPU root
pointer, TT0, TT1 or translation control register (but not the MMU status register).
Writing to the following registers has the indicated side effects:
CPU Root Pointer—When the FD-bit is zero, it flushes the address translation cache.
If the operand value is invalid for a root pointer descriptor, the instruction takes an
memory management unit configuration error exception after moving the operand to
the CPU root pointer.
Supervisor Root Pointer—When the FD-bit is zero, it flushes the address translation
cache. If the operand value is invalid as a root pointer descriptor, the instruction takes
an memory management unit configuration error exception after moving the operand
to the supervisor root pointer.
Translation Control Register—When the FD-bit is zero, it flushes the address translation cache. If the E-bit = 1, consistency checks are performed on the PS and TIx fields.
If the checks fail, the instruction takes an memory management unit configuration
exception after moving the operand to the translation control register. If the checks
pass, the translation control register is loaded with the operand and the E-bit is cleared.
TT0, TT1—When the FD-bit is zero, it flushes the address translation cache. It enables
or disables the transparent translation register according to the E-bit written. If the Ebit = 1, the transparent translation register is enabled. If the E- bit = 0, the register is
disabled.
MOTOROLA
M68000 FAMILY PROGRAMMER’S REFERENCE MANUAL
6-47
Supervisor (Privileged) Instructions
PMOVE
PMOVE
Move to/from MMU Registers
(MC68030 only)
Condition Codes:
Not affected.
MMU Status Register:
Not affected (unless the MMU status register is specified as the destination operand).
Instruction Format:
SRP, CRP, and TC Registers
15
14
13
12
11
10
9
8
7
6
1
1
1
1
0
0
0
0
0
0
0
1
0
R/ W
FD
0
0
P-REGISTER
5
0
4
3
2
1
0
EFFECTIVE ADDRESS
MODE
REGISTER
0
0
0
0
0
Instruction Fields:
Effective Address field—Specifies the memory location for the transfer. Only control
alterable addressing modes can be used as in the following table:
6-48
Addressing Mode
Mode
Register
Addressing Mode
Mode
Register
Dn
—
—
(xxx).W
111
000
An
—
—
(xxx).L
111
001
(An)
010
reg. number:An
# < data >
—
—
(An) +
—
—
—(An)
—
—
(d16,An)
101
reg. number:An
(d16,PC)
—
—
(d8,An,Xn)
110
reg. number:An
(d8,PC,Xn)
—
—
(bd,An,Xn)
110
reg. number:An
(bd,PC,Xn)
—
—
([bd,An,Xn] ,od)
110
reg. number:An
([bd,PC,Xn] ,od)
—
—
([bd,An],Xn ,od)
110
reg. number:An
([bd,PC],Xn ,od)
—
—
M68000 FAMILY PROGRAMMER’S REFERENCE MANUAL
MOTOROLA
Supervisor (Privileged) Instructions
PMOVE
PMOVE
Move to/from MMU Registers
(MC68030 only)
P-Register field—Specifies the memory management unit register.
000—Translation Control Register
010—Supervisor Root Pointer
011—CPU Root Pointer
R/W field—Specifies the direction of transfer.
0—Memory to memeory management unit register.
1—Memeory management unit register to memory.
FD field—Disables flushing of the address translation cache on writes to memeory
management unit registers.
0—Address translation cache is flushed.
1—Address translation cache is not flushed.
Instruction Format:
MMU Status Register
15
14
13
12
11
10
9
8
7
6
1
1
1
1
0
0
0
0
0
0
0
1
1
0
0
0
R/ W
0
0
0
5
0
4
3
2
1
0
EFFECTIVE ADDRESS
MODE
REGISTER
0
0
0
0
0
Instruction Fields:
Effective Address field—Specifies the memory location for the transfer. Control
alterable addressing modes shown for supervisor root pointer register apply.
R/W field—Specifies the direction of transfer.
0—Memory to MMU status register.
1—MMU status register to memory.
NOTE
The syntax of assemblers for the MC68851 use the symbol
PMMU status register for the MMU status register.
MOTOROLA
M68000 FAMILY PROGRAMMER’S REFERENCE MANUAL
6-49
Supervisor (Privileged) Instructions
PMOVE
PMOVE
Move to/from MMU Registers
(MC68030 only)
Instruction Format:
TT Registers
15
14
13
12
11
10
9
8
7
6
1
1
1
1
0
0
0
0
0
0
0
0
0
R/ W
FD
0
0
P-REGISTER
5
0
4
3
2
1
0
EFFECTIVE ADDRESS
MODE
REGISTER
0
0
0
0
0
Instruction Fields:
Effective Address field—Specifies the memory location for the transfer. Control
alterable addressing modes shown for supervisor root pointer register apply.
P-Register field—Specifies the transparent translation register.
010—Transparent Translation Register 0
011—Transparent Translation Register 1
R/W field—Specifies the direction of transfer.
0—Memory to MMU status register.
1—MMU status register to memory.
FD field—Disables flushing of the address translation cache.
0—Address translation cache is flushed.
1—Address translation cache does not flush.
6-50
M68000 FAMILY PROGRAMMER’S REFERENCE MANUAL
MOTOROLA
Supervisor (Privileged) Instructions
PMOVE
PMOVE
Move to/from MMU Registers
(MC68EC030)
Operation:
If Supervisor State
Then (Source) → MRn or MRn → (Destination)
Assembler
Syntax:
PMOVE MRn, < ea >
PMOVE < ea > ,MRn
Attributes:
Size = (Word, Long, Quad)
Description: Moves the contents of the source effective address to an access control
register or moves the contents of an access control register to the destination effective
address.
The instruction is a long-word operation for the access control registers (AC0 and
AC1). It is a word operation for the access control unit status register (ACUSR).
Writing to the ACx registers enables or disables the access control register according
to the E-bit written. If the E-bit = 1, the access control register is enabled. If the E-bit =
0, the register is disabled
Condition Codes:
Not affected.
ACUSR:
Not affected unless the ACUSR is specified as the destination operand.
Instruction Format:
ACUSR
15
14
13
12
11
10
9
8
7
6
1
1
1
1
0
0
0
0
0
0
0
1
1
0
0
0
R/W
0
0
0
5
0
4
3
2
1
0
EFFECTIVE ADDRESS
MODE
REGISTER
0
0
0
0
0
Instruction Fields:
Effective Address field—Specifies the memory location for the transfer.
R/W field—Specifies the direction of transfer.
0—Memory to ACUSR
1—ACUSR to memory
MOTOROLA
M68000 FAMILY PROGRAMMER’S REFERENCE MANUAL
6-51
Supervisor (Privileged) Instructions
PMOVE
PMOVE
Move to/from MMU Registers
(MC68EC030)
NOTE
Assembler syntax for the MC68851 uses the symbol PMMU
status register for the ACUSR; and for the MC68030, the
symbols TT0 and TT1 for AC0 and AC1.
Instruction Format:
ACx Registers
15
14
13
12
11
10
9
8
7
6
1
1
1
1
0
0
0
0
0
0
0
0
0
R/W
0
0
0
P-REGISTER
5
0
4
3
2
1
0
EFFECTIVE ADDRESS
MODE
REGISTER
0
0
0
0
0
Instruction Fields:
Effective Address field—Specifies the memory location for the transfer.
P-Register field—Specifies the ACx register.
001—Access Control Register 0
011—Access Control Register 1
R/W field—Specifies the direction of transfer.
0—Memory to ACUSR
1—ACUSR to memory
6-52
M68000 FAMILY PROGRAMMER’S REFERENCE MANUAL
MOTOROLA
Supervisor (Privileged) Instructions
PMOVE
Move PMMU Register
(MC68851)
Operation:
If Supervisor State
Then MC68851 Register →Destination
Or Source → MC68851 Register
Else TRAP
Assembler
Syntax:
PMOVE < PMMU Register > , < ea >
PMOVE < ea > , < PMMU Register >
Attributes:
Size = (Byte, Word, Long, Double Long)
PMOVE
Description: The contents of the MC68851 register copies to the address specified by < ea
> , or the data at < ea > copies into the MC68851 register.
The instruction is a quad-word operation for CPU root pointer, supervisor root pointer,
and DMA root pointer registers. It is a long-word operation for the translation control
register and a word operation for the breakpoint acknowledge control, breakpoint
acknowledge data, access control, PMMU status, and PMMU cache status registers.
PMOVE is a byte operation for the current access level, valid access level, and stack
change control registers.
The following side effects occur when data is read into certain registers:
CPU Root Pointer—Causes the internal root pointer table to be searched for the
new value. If there is no matching value, an entry in the root pointer table is selected
for replacement, and all address translation cache entries associated with the
replaced entry are invalidated.
Supervisor Root Pointer—Causes all entries in the address translation cache that
were formed with the supervisor root pointer (even globally shared entries) to be
invalidated.
DMA Root Pointer—Causes all entries in the address translation cache that were
formed with the DMA root pointer (even globally shared entries) to be invalidated.
Translation Control Register—If data written to the translation control register
attempts to set the E-bit and the E-bit is currently clear, a consistency check is performed on the IS, TIA, TIB, TIC, TID, and PS fields.
MOTOROLA
M68000 FAMILY PROGRAMMER’S REFERENCE MANUAL
6-53
Supervisor (Privileged) Instructions
PMOVE
PMOVE
Move PMMU Register
(MC68851)
PMMU Status Register: Not affected unless the PMMU status register is written to by the
instruction.
Instruction Format 1:
PMOVE to/from TC, CRP, DRP, SRP, CAL, VAL, SCC, AC
15
14
13
12
11
10
9
8
7
6
1
1
1
1
0
0
0
0
0
0
0
1
0
R/ W
0
0
0
P-REGISTER
5
0
4
3
2
1
0
EFFECTIVE ADDRESS
MODE
REGISTER
0
0
0
0
0
Instruction Fields:
Effective Address field—for memory-to-register transfers, any addressing mode is
allowed as listed in the following table:
Addressing Mode
Mode
Register
Addressing Mode
Mode
Register
Dn*
000
reg. number:Dn
(xxx).W
111
000
An*
001
reg. number:An
(xxx).L
111
001
(An)
010
reg. number:An
# < data >
111
100
(An) +
011
reg. number:An
—(An)
100
reg. number:An
(d16,An)
101
reg. number:An
(d16,PC)
111
010
(d8,An,Xn)
110
reg. number:An
(d8,PC,Xn)
111
011
(bd,An,Xn)
110
reg. number:An
(bd,PC,Xn)
111
011
([bd,An,Xn] ,od)
110
reg. number:An
([bd,PC,Xn] ,od)
111
011
([bd,An],Xn ,od)
110
reg. number:An
([bd,PC],Xn ,od)
111
011
*PMOVE to CRP, SRP, and DMA root pointer not allowed with these modes
6-54
M68000 FAMILY PROGRAMMER’S REFERENCE MANUAL
MOTOROLA
Supervisor (Privileged) Instructions
PMOVE
PMOVE
Move PMMU Register
(MC68851)
For register-to-memory transfers, only alterable addressing modes can be used as
listed in the following table:
Addressing Mode
Mode
Register
Addressing Mode
Mode
Register
Dn*
000
reg. number:Dn
(xxx).W
111
000
An*
001
reg. number:An
(xxx).L
111
001
(An)
010
reg. number:An
# < data >
—
—
(An) +
011
reg. number:An
—(An)
100
reg. number:An
(d16,An)
101
reg. number:An
(d16,PC)
—
—
(d8,An,Xn)
110
reg. number:An
(d8,PC,Xn)
—
—
(bd,An,Xn)
110
reg. number:An
(bd,PC,Xn)
—
—
([bd,An,Xn] ,od)
110
reg. number:An
([bd,PC,Xn] ,od)
—
—
([bd,An],Xn ,od)
110
reg. number:An
([bd,PC],Xn ,od)
—
—
*PMOVE to CRP, SRP, and DMA root pointer not allowed with these modes
Register field—Specifies the MC68851 register.
000—Translation Control Register
001—DMA Root Pointer
010—Supervisor Root Pointer
011—CPU Root Pointer
100—Current Access Level
101—Valid Access Level
110—Stack Change Control Register
111—Access Control Register
R/W field—Specifies the direction of transfer.
0—Transfer < ea > to MC68851 register.
1—Transfer MC68851 register to < ea > .
Instruction Format 2:
PMOVE to/from BADx, BACx
15
14
13
12
11
10
9
8
7
6
1
1
1
1
0
0
0
0
0
0
0
1
1
R/ W
0
0
0
MOTOROLA
P-REGISTER
5
0
4
3
2
1
0
EFFECTIVE ADDRESS
MODE
REGISTER
NUM
0
0
M68000 FAMILY PROGRAMMER’S REFERENCE MANUAL
6-55
Supervisor (Privileged) Instructions
PMOVE
PMOVE
Move PMMU Register
(MC68851)
Instruction Fields:
Effective Address field—Same as format 1.
P-Register field—Specifies the type of MC68851 register.
100—Breakpoint Acknowledge Data
101—Breakpoint Acknowledge Control
R/W field—Specifies the direction of transfer.
0—Transfer < ea > to MC68851 register
1—Transfer MC68851 register to < ea >
Num field—Specifies the number of the BACx or BADx register to be used.
Instruction Format 3:
PMOVE to/from PSR, from PCSR
15
14
13
12
11
10
9
8
7
6
1
1
1
1
0
0
0
0
0
0
0
1
1
R/ W
0
0
0
P-REGISTER
5
0
4
3
2
1
0
EFFECTIVE ADDRESS
MODE
REGISTER
0
0
0
0
0
Instruction Fields:
Effective Address field—Same as format 1.
P Register field—Specifies the MC68851 register.
000 — PMMU Status Register
001 — PMMU Cache Status Register
R/W field—Specifies direction of transfer.
0—Transfer < ea > to MC68851 register.
1—Transfer MC68851 register to < ea > (must be one to access PMMU cache
status register using this format).
6-56
M68000 FAMILY PROGRAMMER’S REFERENCE MANUAL
MOTOROLA
Supervisor (Privileged) Instructions
PRESTORE
Operation:
PMMU Restore Function
(MC68851)
PRESTORE
If Supervisor State
Then MC68851 State Frame → Internal State, Programmer
Registers
Else TRAP
Assembler
Syntax:
PRESTORE < ea >
Attributes:
Unsized, Privileged
Description: The MC68851 aborts execution of any operation in progress. New
programmer registers and internal states are loaded from the state frame located at the
effective address. The first word at the specified address is the format word of the state
frame, specifying the size of the frame and the revision number of the MC68851 that
created it. The MC68020 writes the first word to the MC68851 restore coprocessor
interface register, initiating the restore operation. Then it reads the response
coprocessor interface register to verify that the MC68851 recognizes the format as
valid. The format is invalid if the MC68851 does not recognize the frame size or the
revision number does not match. If the format is invalid, the MC68020 takes a format
exception, and the MC68851 returns to the idle state with its user visible registers
unchanged. However, if the format is valid, then the appropriate state frame loads,
starting at the specified location and proceeding up through the higher addresses.
The PRESTORE instruction restores the nonuser visible state of the MC68851 as well
as the PMMU status register, CPU root pointer, supervisor root pointer, current access
level, valid access level, and stack change control registers of the user programming
model. In addition, if any breakpoints are enabled, all breakpoint acknowledge control
and breakpoint acknowledge data registers are restored. This instruction is the inverse
of the PSAVE instruction.
The current implementation of the MC68851 supports four state frame sizes:
NULL:
This state frame is 4 bytes long, with a format word of $0. A PRESTORE with
this size state frame places the MC68851 in the idle state with no coprocessor or module operations in progress.
IDLE:
This state frame is 36 ($24) bytes long. A PRESTORE with this size state
frame causes the MC68851 to place itself in an idle state with no coprocessor operations in progress and no breakpoints enabled. A module operation
may or may not be in progress. This state frame restores the minimal set of
MC68851 registers.
MOTOROLA
M68000 FAMILY PROGRAMMER’S REFERENCE MANUAL
6-57
Supervisor (Privileged) Instructions
PRESTORE
PRESTORE
PMMU Restore Function
(MC68851)
MID-COPROCESSOR: This state frame is 44 ($2C) bytes long. A PRESTORE with
this size frame restores the MC68851 to a state with a coprocessor operation
in progress and no breakpoints enabled.
BREAKPOINTS ENABLED: This state frame is 76 ($4C) bytes long. A PRESTORE
with this size state frame restores all breakpoint registers, along with other
states. A coprocessor operation may or may not be in progress.
PMMU Status Register: Set according to restored data.
Instruction Format:
15
14
13
12
11
10
9
8
7
6
1
1
1
1
0
0
0
1
0
1
5
4
3
2
1
0
EFFECTIVE ADDRESS
MODE
REGISTER
Instruction Fields:
Effective Address field—Specifies the source location. Only control or post-increment
addressing modes can be used as listed in the following table:
6-58
Addressing Mode
Mode
Register
Addressing Mode
Mode
Register
Dn
—
—
(xxx).W
111
000
An
—
—
(xxx).L
111
001
(An)
010
reg. number:An
# < data >
—
—
(An) +
011
reg. number:An
—(An)
—
—
(d16,An)
101
reg. number:An
(d16,PC)
111
010
(d8,An,Xn)
110
reg. number:An
(d8,PC,Xn)
111
011
(bd,An,Xn)
110
reg. number:An
(bd,PC,Xn)
111
011
([bd,An,Xn] ,od)
110
reg. number:An
([bd,PC,Xn] ,od)
111
011
([bd,An],Xn ,od)
110
reg. number:An
([bd,PC],Xn ,od)
111
011
M68000 FAMILY PROGRAMMER’S REFERENCE MANUAL
MOTOROLA
Supervisor (Privileged) Instructions
PSAVE
Operation:
PMMU Save Function
(MC68851)
PSAVE
If Supervisor State
Then MC68851 Internal State, Programmer
Registers → State Frame
Else TRAP
Assembler
Syntax:
PSAVE < ea >
Attributes:
Unsized, Privileged
Description: The MC68851 suspends execution of any operation that it is performing and
saves its internal state and some programmer registers in a state frame located at the
effective address. The following registers are copied: PMMU status, control root
pointer, supervisor root pointer, current access level, valid access level, and stack
change control. If any breakpoint is enabled, all breakpoint acknowledge control and
breakpoint acknowledge data registers are copied. After the save operation, the
MC68851 is in an idle state waiting for another operation to be requested. Programmer
registers are not changed.
The state frame format saved by the MC68851 depends on its state at the time of the
PSAVE operation. In the current implementation, three state frames are possible:
IDLE:
This state frame is 36 ($24) bytes long. A PSAVE of this size state frame indicates that the MC68851 was in an idle state with no coprocessor operations
in progress and no breakpoints enabled. A module call operation may or may
not have been in progress when this state frame was saved.
MID-COPROCESSOR:This state frame is 44 ($2C) bytes long. A PSAVE of this size
frame indicates that the MC68851 was in a state with a coprocessor or module call operation in progress and no breakpoints enabled.
BREAKPOINTS ENABLED:This state frame is 76 ($4C) bytes long. A PSAVE of this
size state frame indicates that one or more breakpoints were enabled. A
coprocessor or module call operation may or may not have been in progress.
PMMU Status Register: Not affected
MOTOROLA
M68000 FAMILY PROGRAMMER’S REFERENCE MANUAL
6-59
Supervisor (Privileged) Instructions
PSAVE
PSAVE
PMMU Save Function
(MC68851)
Instruction Format:
15
14
13
12
11
10
9
8
7
6
1
1
1
1
0
0
0
1
0
0
5
4
3
2
1
0
EFFECTIVE ADDRESS
MODE
REGISTER
Instruction Fields:
Effective Address field—Specifies the destination location. Only control or
predecrement addressing modes can be used as listed in the following table:
6-60
Addressing Mode
Mode
Register
Addressing Mode
Mode
Register
Dn
—
—
(xxx).W
111
000
An
—
—
(xxx).L
111
001
(An)
010
reg. number:An
# < data >
—
—
(An) +
—
—
—(An)
100
reg. number:An
(d16,An)
101
reg. number:An
(d16,PC)
—
—
(d8,An,Xn)
110
reg. number:An
(d8,PC,Xn)
—
—
(bd,An,Xn)
110
reg. number:An
(bd,PC,Xn)
—
—
([bd,An,Xn] ,od)
110
reg. number:An
([bd,PC,Xn] ,od)
—
—
([bd,An],Xn ,od)
110
reg. number:An
([bd,PC],Xn ,od)
—
—
M68000 FAMILY PROGRAMMER’S REFERENCE MANUAL
MOTOROLA
Supervisor (Privileged) Instructions
PScc
Operation:
PScc
Set on PMMU unit Condition
(MC68851)
If Supervisor State
Then If cc True
Then 1s → Destination
Else 0s → Destination
Else TRAP
Assembler
Syntax:
PScc < ea >
Attributes:
Size = (Byte)
Description: The specified MC68851 condition code is tested. If the condition is true, the
byte specified by the effective address is set to TRUE (all ones); otherwise, that byte is
set to FALSE (all zeros).
The condition code specifier cc may specify the following conditions:
Specifier
Description Condition Field
Specifier
Description Condition Field
BS
B set
000000
BC
B clear
000001
LS
L set
000010
LC
L clear
000011
SS
S set
000100
SC
S clear
000101
AS
A set
000110
AC
A clear
000111
WS
W set
001000
WC
W clear
001001
IS
I set
001010
IC
I clear
001011
GS
G set
001100
GC
G clear
001101
CS
C set
001110
CC
C clear
001111
PMMU Status Register: Not affected
MOTOROLA
M68000 FAMILY PROGRAMMER’S REFERENCE MANUAL
6-61
Supervisor (Privileged) Instructions
PScc
PScc
Set on PMMU Condition
(MC68851)
Instruction Format:
15
14
13
12
11
10
9
8
7
6
1
1
1
1
0
0
0
0
0
1
0
0
0
0
0
0
0
0
0
0
5
4
3
2
1
0
EFFECTIVE ADDRESS
MODE
REGISTER
MC68851 CONDITION
Instruction Fields:
Effective Address field—Specifies the destination location. Only data alterable
addressing modes can be used as listed in the following table:
Addressing Mode
Mode
Register
Addressing Mode
Mode
Register
Dn
000
reg. number:Dn
(xxx).W
111
000
An
—
—
(xxx).L
111
001
(An)
010
reg. number:An
# < data >
—
—
(An) +
011
reg. number:An
—(An)
100
reg. number:An
(d16,An)
101
reg. number:An
(d16,PC)
—
—
(d8,An,Xn)
110
reg. number:An
(d8,PC,Xn)
—
—
(bd,An,Xn)
110
reg. number:An
(bd,PC,Xn)
—
—
([bd,An,Xn] ,od)
110
reg. number:An
([bd,PC,Xn] ,od)
—
—
([bd,An],Xn ,od)
110
reg. number:An
([bd,PC],Xn ,od)
—
—
MC68851 Condition field—Specifies the coprocessor condition to be tested. This field
is passed to the MC68851, which provides directives to the main processor for
processing this instruction.
6-62
M68000 FAMILY PROGRAMMER’S REFERENCE MANUAL
MOTOROLA
Supervisor (Privileged) Instructions
PTEST
Test a Logical Address
(MC68030 only)
Operation:
If Supervisor State
Then Logical Address Status → MMUSR
Else TRAP
Assembler
Syntax:
PTESTR FC, < ea > ,# < level >
PTESTR FC, < ea > ,# < level > ,An
PTESTW FC, < ea > ,# < level >
PTESTW FC, < ea > ,# < level > ,An
Attributes:
Unsized
PTEST
Description: This instruction searches the address translation cache or the translation
tables to a specified level. Searching for the translation descriptor corresponding to the
< ea > field, it sets the bits of the MMU status register according to the status of the
descriptor. Optionally, PTEST stores the physical address of the last table entry
accessed during the search in the specified address register. The PTEST instruction
searches the address translation cache or the translation tables to obtain status
information, but alters neither the used or modified bits of the translation tables nor the
address translation cache. When the level operand is zero, only the transparent
translation of either read or write accesses causes the operations of the PTESTR and
PTESTW to return different results.
The < function code > operand is specified as one of the following:
1. Immediate—Three bits in the command word.
2. Data Register—The three least significant bits of the data register specified in
the instruction.
3. Source Function Code (SFC) Register
4. Destination Function Code (DFC) Register
The effective address is the address to test. The < level > operand specifies the level
of the search. Level 0 specifies searching the addrass translation cache only. Levels
1–7 specify searching the translation tables only. The search ends at the specified
level. A level 0 test does not return the same MMU status register values as a test at a
nonzero level number.
Execution of the instruction continues to the requested level or until detecting one of
the following conditions:
•
Invalid Descriptor
•
Limit Violation
•
Bus Error Assertion (Physical Bus Error)
MOTOROLA
M68000 FAMILY PROGRAMMER’S REFERENCE MANUAL
6-63
Supervisor (Privileged) Instructions
PTEST
PTEST
Test a Logical Address
(MC68030 only)
The instruction accumulates status as it accesses successive table entries. When the
instruction specifies an address translation cache search with an address register
operand, the MC68030 takes an F-line unimplemented instruction exception.
If there is a parameter specification for a translation table search, the physical address
of the last descriptor successfully fetched loads into the address register. A successfully fetched descriptor occurs only if all portions of the descriptor can be read by the
MC68030 without abnormal termination of the bus cycle. If the root pointer’s DT field
indicates page descriptor, the returned address is $0. For a long descriptor, the
address of the first long word is returned. The size of the descriptor (short or long) is
not returned and must be determined from a knowledge of the translation table.
Condition Codes:
Not affected.
MMUSR:
B
∗
6-64
L
∗
S
∗
0
W
∗
I
∗
M
∗
0
0
T
0
0
0
0
M68000 FAMILY PROGRAMMER’S REFERENCE MANUAL
N
∗
MOTOROLA
Supervisor (Privileged) Instructions
PTEST
PTEST
Test a Logical Address
(MC68030 only)
The MMU status register contains the results of the search. The values in the fields of
the MMU status register for an address translation cache search are given in the following table:
MMUSR Bit
PTEST, Level 0
PTEST, Levels 1–7
Bus Error (B)
This bit is set if the bus error bit is set in the This bit is set if a bus error is encountered
ATC entry for the specified logical address. during the table search for the PTEST instruction.
Limit (L)
This bit is cleared.
This bit is set if an index exceeds a limit
during the table search.
Supervis or
Violatio n (S)
This bit is cleared.
This bit is set if the S-bit of a long (S) format
table descriptor or long format page descriptor encountered during the search is
set and if the FC2-bit of the function code
specified by the PTEST instruction is not
equal to one. The S-bit is undefined if the Ibit is set.
Write
Protecte d (W)
The bit is set if the WP-bit of the ATC entry This bit is set if a descriptor or page deis set. It is undefined if the I-bit is set.
scriptor is encountered with the WP-bit set
during the table search. The W-bit is undefined if the I-bit is set.
Invalid (I)
This bit indicates an invalid translation. The
I- bit is set if the translation for the specified
logical address is not resident in the ATC
or if the B-bit of the corresponding ATC entry is set.
Modified (M)
This bit is set if the ATC entry correspond- This bit is set if the page descriptor for the
ing to the specified address has the modi- specified address has the modified bit set.
fied bit set. It is undefined if the I-bit is set. It is undefined if I-bit is set.
Transparent (T)
This bit is set if a match occurred in either This bit is set to zero.
(or both) of the transparent translation registers (TT0 or TT1).
Number of
Levels (N)
This 3-bit field is set to zero.
MOTOROLA
This bit indicates an invalid translation. The
I-bit is set if the DT field of a table or a page
descriptor encountered during the search
is set to invalid or if either the B or L bits of
the MMUSR are set during the table
search.
This 3-bit field contains the actual number
of tables accessed during the search.
M68000 FAMILY PROGRAMMER’S REFERENCE MANUAL
6-65
Supervisor (Privileged) Instructions
PTEST
PTEST
Test a Logical Address
(MC68030 only)
Instruction Format:
15
14
13
12
11
10
9
8
7
6
1
1
1
1
0
0
0
0
0
0
1
0
0
R/ W
A
LEVEL
5
REGISTER
4
3
2
1
0
EFFECTIVE ADDRESS
MODE
REGISTER
FC
Instruction Fields:
Effective Address field—Specifies the logical address to be tested. Only control
alterable addressing modes can be used as listed in the following table:
Addressing Mode
Mode
Register
Addressing Mode
Mode
Register
Dn
—
—
(xxx).W
111
000
An
—
—
(xxx).L
111
001
(An)
010
reg. number:An
# < data >
—
—
(An) +
—
—
—(An)
—
—
(d16,An)
101
reg. number:An
(d16,PC)
—
—
(d8,An,Xn)
110
reg. number:An
(d8,PC,Xn)
—
—
(bd,An,Xn)
110
reg. number:An
(bd,PC,Xn)
—
—
([bd,An,Xn] ,od)
110
reg. number:An
([bd,PC,Xn] ,od)
—
—
([bd,An],Xn ,od)
110
reg. number:An
([bd,PC],Xn ,od)
—
—
Level field—Specifies the highest numbered level to be searched in the table. When
this field contains 0, the A field and the register field must also be 0. The
instruction takes an F-line exception when the level field is 0 and the A field is not
0.
R/W field—Specifies simulating a read or write bus cycle (no difference for MC68030
MMU).
0—Write
1—Read
A field—Specifies the address register option.
0—No address register.
1—Return the address of the last descriptor searched in the address register specified in the register field.
6-66
M68000 FAMILY PROGRAMMER’S REFERENCE MANUAL
MOTOROLA
Supervisor (Privileged) Instructions
PTEST
Test a Logical Address
(MC68030 only)
PTEST
Register field—Specifies an address register for the instruction. When the A field
contains 0, this field must contain 0.
FC field—Function code of address to be tested.
10XXX — Function code is specified as bits XXX.
01DDD — Function code is specified as bits 2–0 of data register DDD.
00000 — Function code is specified as source function code register.
00001 — Function code is specified as destination function code register.
MOTOROLA
M68000 FAMILY PROGRAMMER’S REFERENCE MANUAL
6-67
Supervisor (Privileged) Instructions
PTEST
PTEST
Test a Logical Address
(MC68EC030)
Operation:
If Supervisor State
Then Logical Address Status → ACUSR
Else TRAP
Assembler
Syntax:
PTESTR FC, < ea >
PTESTW FC, < ea >
Attributes:
Unsized
Description: This instruction searches the access control registers for the address
descriptor corresponding to the < ea > field and sets the bit of the access control unit
status register (ACUSR) according to the status of the descriptor.
The < function code > operand is specified in one of the following ways:
1. Immediate—Three bits in the command word.
2. Data Register—The three least significant bits of the data register specified in
the instruction.
3. Source Function Code (SFC) Register
4. Destination Function Code (DFC) Register
The effective address is the address to test.
Condition Codes:
Not affected.
ACUSR:
x
x
x
0
x
x
x
0
0
AC
0
0
0
x
x
x
x = May be 0 or 1.
The AC-bit is set if a match occurs in either (or both) of the access control registers.
Instruction Format:
15
14
13
12
11
10
9
8
7
6
1
1
1
1
0
0
0
0
0
0
1
0
0
0
0
0
R/ W
0
6-68
REGISTER
5
4
3
2
1
0
EFFECTIVE ADDRESS
MODE
REGISTER
FC
M68000 FAMILY PROGRAMMER’S REFERENCE MANUAL
MOTOROLA
Supervisor (Privileged) Instructions
PTEST
PTEST
Test a Logical Address
(MC68EC030)
Instruction Fields:
Effective Address field—Specifies the logical address to be tested. Only control
alterable addressing modes can be used as listed in the following table:
Addressing Mode
Mode
Register
Addressing Mode
Mode
Register
Dn
—
—
(xxx).W
111
000
An
—
—
(xxx).L
111
001
(An)
010
reg. number:An
# < data >
—
—
(An) +
—
—
—(An)
—
—
(d16,An)
101
reg. number:An
(d16,PC)
—
—
(d8,An,Xn)
110
reg. number:An
(d8,PC,Xn)
—
—
(bd,An,Xn)
110
reg. number:An
(bd,PC,Xn)
—
—
([bd,An,Xn] ,od)
110
reg. number:An
([bd,PC,Xn] ,od)
—
—
([bd,An],Xn ,od)
110
reg. number:An
([bd,PC],Xn ,od)
—
—
R/W field—Specifies simulating a read or write bus cycle.
0—Write
1—Read
Register field—Specifies an address register for the instruction. When the A field
contains 0, this field must contain 0.
FC field—Function code of address to be tested.
10XXX — Function code is specified as bits XXX.
01DDD — Function code is specified as bits 2–0 of data register DDD.
00000 — Function code is specified as source function code register.
00001 — Function code is specified as destination function code register.
NOTE
Assembler syntax for the MC68030 is PTESTR FC, < ea > ,#0
and PTESTW FC, < ea > ,#0.
MOTOROLA
M68000 FAMILY PROGRAMMER’S REFERENCE MANUAL
6-69
Supervisor (Privileged) Instructions
PTEST
PTEST
Test a Logical Address
(MC68040, MC68LC040)
Operation:
If Supervisor State
Then Logical Address Status → MMUSR; Entry → ATC
Else TRAP
Assembler
Syntax:
PTESTR (An)
PTESTW (An)
Attributes:
Unsized
Description: This instruction searches the translation tables for the page descriptor
corresponding to the test address in An and sets the bits of the MMU status register
according to the status of the descriptors. The upper address bits of the translated
physical address are also stored in the MMU status register. The PTESTR instruction
simulates a read access and sets the U-bit in each descriptor during table searches;
PTESTW simulates a write access and also sets the M-bit in the descriptors, the
address translation cache entry, and the MMU status register.
A matching entry in the address translation cache (data or instruction) specified by the
function code will be flushed by PTEST. Completion of PTEST results in the creation
of a new address translation cache entry. The specification of the function code for the
test address is in the destination function code (DFC) register. A PTEST instruction
with a DFC value of 0, 3, 4, or 7 is undefined and will return an unknown value in the
MMUSR.
Execution of the instruction continues until one of the following conditions occurs:
•
Match with one of the two transparent translation registers.
•
Transfer Error Assertion (physical transfer error)
•
Invalid Descriptor
•
Valid Page Descriptor
Condition Codes:
Not affected.
MMU Status Register:
PHYSICAL ADDRESS
∗
6-70
B
∗
G
∗
U1
∗
U0
∗
S
∗
CM
∗
M
∗
0
M68000 FAMILY PROGRAMMER’S REFERENCE MANUAL
W
∗
T
∗
R
∗
MOTOROLA
Supervisor (Privileged) Instructions
PTEST
PTEST
Test a Logical Address
(MC68040, MC68LC040)
The MMUSR contains the results of the search. The values in the fields of the MMUSR
for a search are:
Physical Address—This 20-bit field contains the upper bits of the translated physical
address. Merging these bits with the lower bits of the logical address forms the
actual physical address.
Bus Error (B)—Set if a transfer error is encountered during the table search for the
PTEST instruction. If this bit is set, all other bits are zero.
Globally Shared (G)—Set if the G-bit is set in the page descriptor.
User Page Attributes (U1, U0)—Set if corresponding bits in the page descriptor are set.
Supervisor Protection (S)—Set if the S-bit in the page descriptor is set. This bit does
not indicate that a violation has occurred.
Cache Mode (CM)—This 2-bit field is copied from the CM-bit in the page descriptor.
Modified (M)—Set if the M-bit is set in the page descriptor associated with the address.
Write Protect (W)—Set if the W-bit is set in any of the descriptors encountered during
the table search. Setting of this bit does not indicate that a violation occurred.
Transparent Translation Register Hit (T)—Set if the PTEST address matches an
instruction or data transparent translation register and the R-bit is set; all other bits
are zero.
Resident (R)—Set if the PTEST address matches a transparent translation register or
if the table search completes by obtaining a valid page descriptor.
Instruction Format:
15
1
14
1
13
1
12
1
11
0
10
1
9
0
8
1
7
0
6
1
5
R/ W
4
0
3
1
2
1
0
REGISTER
Instruction Fields:
R/W field—Specifies simulating a read or write bus transfer.
0—Write
1—Read
Register field—Specifies the address register containing the effective address for the
instruction.
MOTOROLA
M68000 FAMILY PROGRAMMER’S REFERENCE MANUAL
6-71
Supervisor (Privileged) Instructions
PTEST
PTEST
Test a Logical Address
(MC68EC040)
Operation:
If Supervisor State
Then No Operation, Possibly Run Extraneous Bus Cycles
Else TRAP
Assembler
Syntax:
PTESTR (An)
PTESTW (An)
Attributes:
Unsized
Description: This instruction must not be executed on an MC68EC040. This instruction
may cause extraneous bus cycles to occur and may result in unexpected exception
types.
Instruction Format:
15
1
14
1
13
1
12
1
11
0
10
1
9
0
8
1
7
0
6
1
5
R/ W
4
0
3
1
2
1
0
REGISTER
Instruction Fields:
R/W field—Specifies simulating a read or write bus transfer.
0—Write
1—Read
Register field—Specifies the address register containing the effective address for the
instruction.
6-72
M68000 FAMILY PROGRAMMER’S REFERENCE MANUAL
MOTOROLA
Supervisor (Privileged) Instructions
PTEST
Get Information About Logical Address
(MC68851)
PTEST
Operation:
If Supervisor State
Then Information About Logical Address → PSTATUS
Else TRAP
Assembler
Syntax:
PTESTR FC, < ea > ,# < level > ,(An)
PTESTW FC, < ea > ,# < level > ,(An)
Attributes:
Unsized
Description: If the E-bit of the translation control register is set, information about the logical
address specified by FC and < ea > is placed in the PMMU status register. If the E-bit
of the translation control register is clear, this instruction will cause a paged memory
management unit illegal operation exception (vector $39).
The function code for this operation may be specified as follows:
1. Immediate—The function code is four bits in the command word.
2. Data Register—The function code is in the lower four bits in the MC68020 data
register specified in the instruction.
3. Source Function Code (SFC) Register—The function code is in the SFC register
in the CPU. Since the SFC of the MC68020 has only three implemented bits,
only function codes $0D$7 can be specified in this manner.
4. Destination Function Code (DFC) Register—The function code is in the DFC
register in the CPU. Since the DFC of the MC68020 has only three implemented
bits, only function codes $0D$7 can be specified in this manner.
The effective address field specifies the logical address to be tested.
The # < level > parameter specifies the depth to which the translation table is to be
searched. A value of zero specifies a search of the address translation cache only. Values 1–7 cause the address translation cache to be ignored and specify the maximum
number of descriptors to fetch.
NOTE
Finding an address translation cache entry with < level > set to
zero may result in a different value in the PMMU status register
than forcing a table search. Only the I, W, G, M, and C bits of the
PMMU status register are always the same in both cases.
MOTOROLA
M68000 FAMILY PROGRAMMER’S REFERENCE MANUAL
6-73
Supervisor (Privileged) Instructions
PTEST
Get Information About Logical Address
(MC68851)
PTEST
Either PTESTR or PTESTW must be specified. These two instructions differ in the setting of the A-bit of the PMMU status register. For systems where access levels are not
in use, either PTESTR or PTESTW may be used. U and M bits in the translation table
are not modified by this instruction.
If there is a specified address register parameter, the physical address of the last successfully fetched descriptor is loaded into the address register. A descriptor is successfully fetched if all portions of the descriptor can be read by the MC68851 without
abnormal termination of the bus cycle. If the DT field of the root pointer used indicates
page descriptor, the returned address is $0.
The PTEST instruction continues searching the translation tables until reaching the
requested level or until a condition occurs that makes further searching impossible (i.e.,
a DT field set to invalid, a limit violation, or a bus error from memory). The information
in the PMMU status register reflects the accumulated values.
PMMU Status Register:
Bus Error (B)—Set if a bus error was received during a descriptor fetch, or if < level >
= 0 and an entry was found in the address translation cache with its BERR bit set;
cleared otherwise.
Limit (L)—Set if the limit field of a long descriptor was exceeded; cleared otherwise.
Supervisor Violation (S)—Set if a long descriptor indicated supervisor-only access and
the < fc > parameter did not have bit 2 set; cleared otherwise.
Access Level Violation (A)—If PTESTR was specified, set if the RAL field of a long
descriptor would deny access. If PTESTW was specified, set if a WAL or RAL field
of a long descriptor would deny access; cleared otherwise.
Write Protection (W)—Set if the WP-bit of a descriptor was set or if a WAL field of a
long descriptor would deny access; cleared otherwise.
Invalid (I)—Set if a valid translation was not available; cleared otherwise.
Modified (M)—If the tested address is found in the address translation cache, set to the
value of the M-bit in the address translation cache. If the tested address is found
in the translation table, set if the M-bit of the page descriptor is set; cleared
otherwise.
6-74
M68000 FAMILY PROGRAMMER’S REFERENCE MANUAL
MOTOROLA
Supervisor (Privileged) Instructions
PTEST
Get Information About Logical Address
(MC68851)
PTEST
Gate (G)—If the tested address is found in the address translation cache, set to the
value of the G-bit in the address translation cache. If the tested address is found in
the translation table, set if the G-bit of the page descriptor is set; cleared otherwise.
Globally Shared (C)—Set if the address is globally shared; cleared otherwise.
Level Number (N)—Set to the number of levels searched. A value of zero indicates an
early termination of the table search in the root pointer (DT = page descriptor) if
the level specification was not zero. If the level specification was zero, N is always
set to zero.
Instruction Format:
15
14
13
12
11
10
9
8
7
6
1
1
1
1
0
0
0
0
0
0
1
0
0
MOTOROLA
LEVEL
R/ W
A-REGISTER
5
4
3
2
1
0
EFFECTIVE ADDRESS
MODE
REGISTER
FC
M68000 FAMILY PROGRAMMER’S REFERENCE MANUAL
6-75
Supervisor (Privileged) Instructions
PTEST
Get Information About Logical Address
(MC68851)
PTEST
Instruction Fields:
Effective Address field—Specifies the logical address about which information is
requested. Only control alterable addressing modes can be used as listed in the
following table:
Addressing Mode
Mode
Register
Addressing Mode
Mode
Register
Dn
—
—
(xxx).W
111
000
An
—
—
(xxx).L
111
001
(An)
010
reg. number:An
# < data >
—
—
(An) +
—
—
—(An)
—
—
(d16,An)
101
reg. number:An
(d16,PC)
—
—
(d8,An,Xn)
110
reg. number:An
(d8,PC,Xn)
—
—
(bd,An,Xn)
110
reg. number:An
(bd,PC,Xn)
—
—
([bd,An,Xn] ,od)
110
reg. number:An
([bd,PC,Xn] ,od)
—
—
([bd,An],Xn ,od)
110
reg. number:An
([bd,PC],Xn ,od)
—
—
NOTE
The effective address field must provide the MC68851 with the
effective address of the logical address to be tested, not the
effective address describing where the PTEST operand is
located. For example, to test a logical address that is temporarily
stored on the system stack, the instruction PTEST [(SP)] must
be used since PTEST (SP) would test the mapping of the system
stack (i.e., the effective address passed to the MC68851 is the
effective address of the system stack, not the effective address
formed by the operand located on the top of the stack).
6-76
M68000 FAMILY PROGRAMMER’S REFERENCE MANUAL
MOTOROLA
Supervisor (Privileged) Instructions
PTEST
Get Information About Logical Address
(MC68851)
PTEST
Level field—Specifies the depth to which the translation table should be searched.
R/W field—Specifies whether the A-bit should be updated for a read or a write.
1—Read
0—Write
A-Register field—Specifies the address register in which to load the last descriptor
address.
0xxx — Do not return the last descriptor address to an address register.
1RRR — Return the last descriptor address to address register RRR.
NOTE
When the PTEST instruction specifies a level of zero, the Aregister field must be 0000. Otherwise, an F-line exception is
generated.
FC field—Function code of address to test.
1DDDD — Function code is specified as four bits DDDD.
01RRR — Function code is contained in CPU data register RRR.
00000 — Function code is contained in CPU source function code register.
00001 — Function code is contained in CPU destination function code
register.
MOTOROLA
M68000 FAMILY PROGRAMMER’S REFERENCE MANUAL
6-77
Supervisor (Privileged) Instructions
PTRAPcc
PTRAPcc
TRAP on PMMU Condition
(M68851)
Operation:
If Supervisor State
Then If cc True
Then TRAP
Else TRAP
Assembler
Syntax:
PTRAPcc
PTRAPcc.W # < data > PTRAPcc.L # < data >
Attributes:
Unsized or Size = (Word, Long)
Description: If the selected MC68851 condition is true, the processor initiates exception
processing. The vector number is generated referencing the cpTRAPcc exception
vector; the stacked program counter is the address of the next instruction. If the
selected condition is not true, no operation is performed, and execution continues with
the next instruction. The immediate data operand is placed in the next word(s) following
the MC68851 condition and is available for user definition to be used within the trap
handler. Following the condition word, there may be a user-defined data operand,
specified as immediate data, to be used by the trap handler.
The condition specifier cc may specify the following conditions:
Specifier
Description Condition Field
Specifier
Description Condition Field
BS
B set
000000
BC
B clear
000001
LS
L set
000010
LC
L clear
000011
SS
S set
000100
SC
S clear
000101
AS
A set
000110
AC
A clear
000111
WS
W set
001000
WC
W clear
001001
IS
I set
001010
IC
I clear
001011
GS
G set
001100
GC
G clear
001101
CS
C set
001110
CC
C clear
001111
PMMU Status Register: Not affected
6-78
M68000 FAMILY PROGRAMMER’S REFERENCE MANUAL
MOTOROLA
Supervisor (Privileged) Instructions
PTRAPcc
TRAP on PMMU Condition
(M68851)
PTRAPcc
Instruction Format:
15
1
0
14
1
0
13
1
0
12
11
10
9
8
7
6
5
4
3
2
1
1
0
0
0
0
0
1
1
1
1
OPMODE
0
0
0
0
0
0
0
MC68851 CONDITION
16-BIT OPERAND OR MOST SIGNIFICANT WORD OF 32-BIT OPERAND (IFNEEDED)
LEAST SIGNIFICANT WORD OF 32-BIT OPERAND (IF NEEDED)
0
Instruction Fields:
Opmode field—Selects the instruction form.
010 — Instruction is followed by one operand word.
011 — Instruction is followed by two operand words.
100 — Instruction has no following operand words.
MC68851 Condition field—Specifies the coprocessor condition to be tested. This field
is passed to the MC68851, which provides directives to the main processor for
processing this instruction.
MOTOROLA
M68000 FAMILY PROGRAMMER’S REFERENCE MANUAL
6-79
Supervisor (Privileged) Instructions
PVALID
PVALID
Validate a Pointer
(MC68851)
Operation:
If (Source AL Bits) → (Destination AL Bits)
Then TRAP
Assembler
Syntax:
PVALID VAL, < ea >
PVALID An, < ea >
Attributes:
Size = (Long)
Description: The upper bits of the source, VAL or An, compare with the upper bits of the
destination, < ea > . The ALC field of the access control register defines the number of
bits compared. If the upper bits of the source are numerically greater than (less
privileged than) the destination, they cause a memory management access level
exception. Otherwise, execution continues with the next instruction. If the MC field of
the access control register = 0, then this instruction always causes a paged memory
management unit access level exception.
PMMU Status Register: Not affected.
Instruction Format 1:
VAL Contains Access Level to Test Against
15
14
13
12
11
10
9
8
7
6
1
1
1
1
0
0
0
0
0
0
0
0
1
0
1
0
0
0
0
0
6-80
5
0
4
3
2
1
0
EFFECTIVE ADDRESS
MODE
REGISTER
0
0
0
0
0
M68000 FAMILY PROGRAMMER’S REFERENCE MANUAL
MOTOROLA
Supervisor (Privileged) Instructions
PVALID
PVALID
Validate a Pointer
(MC68851)
Instruction Field:
Effective Address field—Specifies the logical address to be evaluated and compared
against the valid access level register. Only control alterable addressing modes can
be used as listed in the following table:
MOTOROLA
Addressing Mode
Mode
Register
Addressing Mode
Mode
Register
Dn
—
—
(xxx).W
111
000
An
—
—
(xxx).L
111
001
(An)
010
reg. number:An
# < data >
—
—
(An) +
—
—
—(An)
—
—
(d16,An)
101
reg. number:An
(d16,PC)
—
—
(d8,An,Xn)
110
reg. number:An
(d8,PC,Xn)
—
—
(bd,An,Xn)
110
reg. number:An
(bd,PC,Xn)
—
—
([bd,An,Xn] ,od)
110
reg. number:An
([bd,PC,Xn] ,od)
—
—
([bd,An],Xn ,od)
110
reg. number:An
([bd,PC],Xn ,od)
—
—
M68000 FAMILY PROGRAMMER’S REFERENCE MANUAL
6-81
Supervisor (Privileged) Instructions
PVALID
PVALID
Validate a Pointer
(MC68851)
Instruction Format 2:
Main Processor Register Contains Access Level to Test Against
15
14
13
12
11
10
9
8
7
6
1
1
1
1
0
0
0
0
0
0
0
0
1
0
1
0
0
0
0
0
5
0
4
3
2
1
0
EFFECTIVE ADDRESS
MODE
REGISTER
0
0
REGISTER
Instruction Fields:
Effective Address field—Specifies the logical address to be evaluated and compared
against specified main processor address register. Only control alterable addressing
modes can be used as listed in the following table:
Addressing Mode
Mode
Register
Addressing Mode
Mode
Register
Dn
—
—
(xxx).W
111
000
An
—
—
(xxx).L
111
001
(An)
010
reg. number:An
# < data >
—
—
(An) +
—
—
—(An)
—
—
(d16,An)
101
reg. number:An
(d16,PC)
—
—
(d8,An,Xn)
110
reg. number:An
(d8,PC,Xn)
—
—
(bd,An,Xn)
110
reg. number:An
(bd,PC,Xn)
—
—
([bd,An,Xn] ,od)
110
reg. number:An
([bd,PC,Xn] ,od)
—
—
([bd,An],Xn ,od)
110
reg. number:An
([bd,PC],Xn ,od)
—
—
NOTE
The effective address field must provide the MC68851 with the
effective address of the logical address to be validated, not the
effective address describing where the PVALID operand is
located. For example, to validate a logical address that is
temporarily stored on the system stack, the instruction PVALID
VAL,[(SP)] must be used since PVALID VAL,(SP) would validate
the mapping on the system stack (i.e., the effective address
passed to the MC68851 is the effective address of the system
stack, not the effective address formed by the operand located
on the top of the stack).
Register field—Specifies the main processor address register to be used in the
compare.
6-82
M68000 FAMILY PROGRAMMER’S REFERENCE MANUAL
MOTOROLA
Supervisor (Privileged) Instructions
RESET
Operation:
RESET
Reset External Devices
(M68000 Family)
If Supervisor State
Then Assert RESET (RSTO, MC68040 Only) Line
Else TRAP
Assembler
Syntax:
RESET
Attributes:
Unsized
Description: Asserts the RSTO signal for 512 (124 for MC68000, MC68EC000,
MC68HC000, MC68HC001, MC68008, MC68010, and MC68302) clock periods,
resetting all external devices. The processor state, other than the program counter, is
unaffected, and execution continues with the next instruction.
Condition Codes:
Not affected.
Instruction Format:
15
0
14
1
MOTOROLA
13
0
12
0
11
1
10
1
9
1
8
0
7
0
6
1
5
1
4
1
3
0
M68000 FAMILY PROGRAMMER’S REFERENCE MANUAL
2
0
1
0
0
0
6-83
Supervisor (Privileged) Instructions
RTE
RTE
Return from Exception
(M68000 Family)
Operation:
If Supervisor State
Then (SP) → SR; SP + 2 → SP; (SP) → PC; SP + 4 → SP; Restore
State and Deallocate Stack According to (SP)
Else TRAP
Assembler
Syntax:
RTE
Attributes:
Unsized
Description: Loads the processor state information stored in the exception stack frame
located at the top of the stack into the processor. The instruction examines the stack
format field in the format/offset word to determine how much information must be
restored.
Condition Codes:
Set according to the condition code bits in the status register value restored from the
stack.
Instruction Format:
15
0
14
1
13
0
12
0
11
1
10
1
9
1
8
0
7
0
6
1
5
1
4
1
3
0
2
0
1
1
0
1
3
2
1
0
Format/Offset Word (in Stack Frame):
MC68010, MC68020, MC68030, MC68040, CPU32
15
14
13
FORMAT
12
11
0
10
0
9
8
7
6
5
4
VECTOR OFFSET
Format Field of Format/Offset Word:
Contains the format code, which implies the stack frame size (including the format/
offset word). For further information, refer to Appendix B Exception Processing
Reference.
6-84
M68000 FAMILY PROGRAMMER’S REFERENCE MANUAL
MOTOROLA
Supervisor (Privileged) Instructions
STOP
STOP
Load Status Register and Stop
(M68000 Family)
Operation:
If Supervisor State
Then Immediate Data → SR; STOP
Else TRAP
Assembler
Syntax:
STOP # < data >
Attributes:
Unsized
Description: Moves the immediate operand into the status register (both user and
supervisor portions), advances the program counter to point to the next instruction, and
stops the fetching and executing of instructions. A trace, interrupt, or reset exception
causes the processor to resume instruction execution. A trace exception occurs if
instruction tracing is enabled (T0 = 1, T1 = 0) when the STOP instruction begins
execution. If an interrupt request is asserted with a priority higher than the priority level
set by the new status register value, an interrupt exception occurs; otherwise, the
interrupt request is ignored. External reset always initiates reset exception processing.
Condition Codes:
Set according to the immediate operand.
Instruction Format:
15
0
14
1
13
0
12
0
11
1
10
1
9
1
8
7
0
0
IMMEDIATE DATA
6
1
5
1
4
1
3
0
2
0
1
1
0
0
Instruction Fields:
Immediate field—Specifies the data to be loaded into the status register.
MOTOROLA
M68000 FAMILY PROGRAMMER’S REFERENCE MANUAL
6-85
Supervisor (Privileged) Instructions
6-86
M68000 FAMILY PROGRAMMER’S REFERENCE MANUAL
MOTOROLA
SECTION 7
CPU32 INSTRUCTIONS
This section describes the instructions provided for the CPU32. The CPU32 can execute
object code from an MC68000 and MC68010 and many of the instructions of the MC68020.
There are three new instructions provided for the CPU32: enter background mode (BGND),
low-power stop (LPSTOP), and table lookup and interpolate (TBLS, TBLSN, TBLU, and
TBLUN). Table 7-1 lists the MC68020 instructions not supported by the CPU32.
Table 7-1. MC68020 Instructions Not Supported
Description
Mnemonic
MOTOROLA
BFCHG
Test Bit Field and Change
BFCLR
Test Bit Field and Clear
BFEXTS
Signed Bit Field Extract
BFEXTU
Unsigned Bit Field Extract
BFFFO
Bit Field Find First One
BFINS
Bit Field Insert
BFSET
Test Bit Field and Set
BFTST
Test Bit Field
CALLM
CALL Module
CAS
Compare and Swap Operands
CAS2
Compare and Swap Dual Operands
cpBcc
Branch on Coprocessor Condition
cpDBcc
Test Coprocessor Condition Decrement and Branch
cpGEN
Coprocessor General Function
cpRESTORE
Coprocessor Restore Function
cpSAVE
Coprocessor Save Function
cpScc
Set on Coprocessor Condition
cpTRAPcc
Trap on Coprocessor Condition
RTM
Return from Module
PACK
Pack BCD
UNPK
Unpack BCD
M68000 FAMILY PROGRAMMER’S REFERENCE MANUAL
7-1
CPU32 Instructions
Addressing in the CPU32 is register oriented. Most instructions allow the results of the
specified operation to be placed either in a register or directly in memory. This flexibility
eliminates the need for extra instructions to store register contents in memory. Table 7- 2 lists
the M68000 family addressing modes with cross-references to the MC68000, MC68010,
CPU32, and MC68020. When referring to instructions in the previous sections, refer to Table
7-2 to identify the addressing modes available to the CPU32. Table 7-3 lists the instructions
for the CPU32.
Table 7-2. M68000 Family Addressing Modes
Syntax
MC68000
MC68010
CPU32
MC68020
Rn
X
X
X
(An)
X
X
X
Address Register Indirect with Postincrement
(An) +
X
X
X
Address Register Indirect with Postdecrement
– (An)
X
X
X
(d16,An)
X
X
X
Address Register Indirect with Index
(8-Bit Displacement)
(d8,An,Xn)
X
X
X
Address Register Indirect with Index
(Base Displacement)
(d8,An,Xn∗SCALE)
X
X
Memory Indirect with Postincrement
([bd,An],Xn, od)
X
Memory Indirect with Preincrement
([bd,An],Xn, od)
X
Addressing Mode
Register Indirect
Address Register Indirect
Address Register Indirect with Displacement
Absolute Short
(xxx).W
X
X
X
Absolute Long
(xxx).L
X
X
X
(d16,PC)
X
X
X
Program Counter Indirect with Index
(8-Bit Displacement)
(d8,PC,Xn)
X
X
X
Program Counter Indirect with Index
(Base Displacement)
(d8,PC,Xn*SC ALE)
X
X
X
X
Program Counter Indirect with Displacement
Immediate
# < data >
X
PC Memory Indirect with Postincrement
([bd,PC],Xn, od)
X
PC Memory Indirect with Predecrement
([bd,PC],Xn, od)
X
NOTE: Xn,SIZE*SCALE—Denotes index register n (data or address), the index size (W for word, L for long
word and scale factor (1, 2, 4, or 8 for no-word, long-word, or 8 for quad- word scaling, respectively).
X—Supported
7-2
M68000 FAMILY PROGRAMMER’S REFERENCE MANUAL
MOTOROLA
CPU32 Instructions
Table 7-3. CPU32 Instruction Set
Mnemonic
ABCD
ADD
ADDA
ADDI
ADDQ
ADDX
AND
ANDI
ANDI to CCR
ANDI to SR
ASL, ASR
Description
Add Decimal with Extend
Add
Add Address
Add Immediate
Add Quick
Add with Extend
Logical AND
Logical AND Immediate
AND Immediate to Condition Code
Register
AND Immediate to Status Register
Arithmetic Shift Left and Right
Bcc
BCHG
BCLR
BGND
BKPT
BRA
BSET
BSR
BTST
Branch Conditionally
Test Bit and Change
Test Bit and Clear
Enter Background Mode
Breakpoint
Branch
Test Bit and Set
Branch to Subroutine
Test Bit
CHK
CHK2
CLR
CMP
CMPA
CMPI
CMPM
CMP2
DBcc
DIVS, DIVSL
DIVU, DIVUL
EOR
EORI
EORI to CCR
EORI to SR
EXG
EXT, LSR
ILLEGAL
JMP
JSR
LEA
LINK
LPSTOP
LSL, LSR
MOTOROLA
Check Register Against Bound
Check Register Against Upper and
Lower Bound
Clear
Compare
Compare Address
Compare Immediate
Compare Memory to Memory
Compare Register Against Upper and
Lower Bounds
Test Condition, Decrement, and
Branch
Signed Divide
Unsigned Divide
Logical Exclusive-OR
Logical Exclusive-OR Immediate
Exclusive-OR Immediate to
Condition Code Register
Exclusive-OR Immediate to
Status Register
Exchange Registers
Sign-Extend
Take Illegal Instruction Trap
Jump
Jump to Subroutine
Load Effective Address
Link and Allocate
Low Power Stop
Logical Shift Left and Right
Mnemonic
Description
MOVE
MOVEA
MOVE from
CCR
Move from SR
MOVE to SR
MOVE USP
MOVEC
MOVEM
MOVEP
MOVEQ
MOVES
MULS
MULU
Move
Move Address
Move Condition Code Register
Move from Status Register
Move to Status Register
Move User Stack Pointer
Move Control Register
Move Multiple Registers
Move Peripheral
Move Quick
Move Alternate Address Space
Signed Multiply
Unsigned Multiply
NBCD
NEG
NEGX
NOP
NOT
PEA
Negate Decimal with Extend
Negate
Negate with Extend
No Operation
Logical Complement
Push Effective Address
RESET
ROL, ROR
ROXL, ROXR
RTD
RTE
RTR
RTS
Reset External Devices
Rotate Left and Right
Rotate with Extend Left and Right
Return and Deallocate
Return from Exception
Return and Restore Codes
Return from Subroutine
SBCD
Scc
STOP
SUB
SUBA
SUBI
SUBQ
SUBX
SWAP
Subtract Decimal with Extend
Set Conditionally
Stop
Subtract
Subtract Address
Subtract Immediate
Subtract Quick
Subtract with Extend
Swap Register Words
TAS
TBLS, TBLSN
TRAP
TRAPcc
TRAPV
TST
Test Operand and Set
Signed/Unsigned Table Lookup and
Interpolate
Signed/Unsigned Table Lookup and
Interpolate
Trap
Trap Conditionally
Trap an Overflow
Test Operand
UNLK
Unlink
TBLU, TBLUN
M68000 FAMILY PROGRAMMER’S REFERENCE MANUAL
7-3
CPU32 Instructions
BGND
BGND
Enter Background Mode
(CPU32)
Operation:
If Background Mode Enabled
Then Enter Background Mode
Else Format/Vector Offset → – (SSP);
PC → – (SSP)
SR → – (SSP)
(Vector) → PC
Assembler
Syntax:
BGND
Attributes:
Size = (Unsized)
Description: The processor suspends instruction execution and enters background mode
if background mode is enabled. The freeze output is asserted to acknowledge entrance
into background mode. Upon exiting background mode, instruction execution
continues with the instruction pointed to by the current program counter. If background
mode is not enabled, the processor initiates illegal instruction exception processing.
The vector number is generated to reference the illegal instruction exception vector.
Refer to the appropriate user’s manual for detailed information on background mode.
Condition Codes:
X
—
X
N
Z
V
C
N
—
Z
—
V
—
C
—
— Not affected.
— Not affected.
— Not affected.
— Not affected.
— Not affected.
Instruction Format:
15
0
7-4
14
1
13
0
12
0
11
1
10
0
9
1
8
0
7
1
6
1
5
1
4
1
3
1
M68000 FAMILY PROGRAMMER’S REFERENCE MANUAL
2
0
1
1
0
0
MOTOROLA
CPU32 Instructions
LPSTOP
LPSTOP
Low-Power Stop
(CPU32)
Operation:
If Supervisor State
Immediate Data → SR
Interrupt Mask → External Bus Interface (EBI)
STOP
Else TRAP
Assembler
Syntax:
LPSTOP # < data >
Attributes:
Size = (Word) Privileged
Description: The immediate operand moves into the entire status register, the program
counter advances to point to the next instruction, and the processor stops fetching and
executing instructions. A CPU LPSTOP broadcast cycle is executed to CPU space $3
to copy the updated interrupt mask to the external bus interface (EBI). The internal
clocks are stopped.
Instruction execution resumes when a trace, interrupt, or reset exception occurs. A
trace exception will occur if the trace state is on when the LPSTOP instruction is
executed. If an interrupt request is asserted with a higher priority that the current
priority level set by the new status register value, an interrupt exception occurs;
otherwise, the interrupt request is ignored. If the bit of the immediate data
corresponding to the S-bit is off, execution of the instruction will cause a privilege
violation. An external reset always initiates reset exception processing.
Condition Codes:
Set according to the immediate operand.
Instruction Format:
15
1
0
14
1
0
13
1
0
12
1
0
11
1
0
10
0
0
9
0
0
8
7
0
0
1
1
IMMEDIATE DATA
6
0
1
5
0
0
4
0
0
3
0
0
2
0
0
1
0
0
0
0
0
Instruction Fields:
Immediate field—Specifies the data to be loaded into the status register.
MOTOROLA
M68000 FAMILY PROGRAMMER’S REFERENCE MANUAL
7-5
CPU32 Instructions
TBLS
TBLSN
Operation:
Table Lookup and Interpolate (Signed)
(CPU32)
TBLS
TBLSN
Rounded:
ENTRY(n) + {(ENTRY(n + 1) – ENTRY(n)) x Dx 7 – 0} ÷ 256 → Dx
Unrounded:
ENTRY(n) x 256 + {(ENTRY(n + 1) – ENTRY(n)) x Dx 7 – 0} → Dx
Where ENTRY(n) and ENTRY(n + 1) are either:
1. Consecutive entries in the table pointed to by the < ea > and
indexed by Dx 15 – 8 π SIZE or;
2. The registers Dym, Dyn respectively.
Assembler
Syntax:
TBLS. < size > < ea > ,Dx
TBLSN. < size > < ea > ,Dx
TBLS. < size > Dym:Dyn, Dx
TBLSN. < size > Dym:Dyn, Dx
Attributes:
Size = (Byte, Word, Long)
Result rounded
Result not rounded
Result rounded
Result not rounded
Description: The TBLS and TBLSN instructions allow the efficient use of piecewise linear
compressed data tables to model complex functions. The TBLS instruction has two
modes of operation: table lookup and interpolate mode and data register interpolate
mode.
For table lookup and interpolate mode, data register Dx 15 – 0 contains the
independent variable X. The effective address points to the start of a signed byte, word,
or long-word table containing a linearized representation of the dependent variable, Y,
as a function of X. In general, the independent variable, located in the low-order word
of Dx, consists of an 8-bit integer part and an 8-bit fractional part. An assumed radix
point is located between bits 7 and 8. The integer part, Dx 15 – 8, is scaled by the
operand size and is used as an offset into the table. The selected entry in the table is
subtracted from the next consecutive entry. A fractional portion of this difference is
taken by multiplying by the interpolation fraction, Dx 7 – 0 .The adjusted difference is
then added to the selected table entry. The result is returned in the destination data
register, Dx.
7-6
M68000 FAMILY PROGRAMMER’S REFERENCE MANUAL
MOTOROLA
CPU32 Instructions
TBLS
TBLSN
TBLS
TBLSN
Table Lookup and Interpolate (Signed)
(CPU32)
For register interpolate mode, the interpolation occurs using the Dym and Dyn registers
in place of the two table entries. For this mode, only the fractional portion, Dx 7 – 0, is
used in the interpolation, and the integer portion, Dx 15 – 8, is ignored. The register
interpolation mode may be used with several table lookup and interpolations to model
multidimensional functions.
Signed table entries range from – 2n – 1 to 2n – 1 – 1; whereas, unsigned table entries
range from 0 to 2n – 1 where n is 8, 16, or 32 for byte, word, and long-word tables,
respectively.
Rounding of the result is optionally selected via the "R" instruction field. If R = 0
(TABLE), the fractional portion is rounded according to the round-to-nearest algorithm.
The following table summerizes the rounding procedure:
Adjusted Difference
Fraction
Rounding
Adjustment
≤ – 1/2
–1
> – 1/2 and < 1/2
+0
≥ 1/2
+1
The adjusted difference is then added to the selected table entry. The rounded result
is returned in the destination data register, Dx. Only the portion of the register
corresponding to the selected size is affected.
BYTE
WORD
LONG
MOTOROLA
31
24
UNAFFECTED
UNAFFECTED
RESULT
23
16
UNAFFECTED
UNAFFECTED
RESULT
15
8
UNAFFECTED
RESULT
RESULT
M68000 FAMILY PROGRAMMER’S REFERENCE MANUAL
7
0
RESULT
RESULT
RESULT
7-7
CPU32 Instructions
TBLS
TBLSN
TBLS
TBLSN
Table Lookup and Interpolate (Signed)
(CPU32)
If R = 1 (TABLENR), the result is returned in register Dx without rounding. If the size is
byte, the integer portion of the result is returned in Dx 15 – 8; the integer portion of a
word result is stored in Dx 23 – 8; the least significant 24 bits of a long result are stored
in Dx 31 – 8. Byte and word results are sign-extended to fill the entire 32-bit register.
BYTE
WORD
LONG
31
24
SIGN-EXTENDED
SIGN-EXTENDED
RESULT
23
16
SIGN-EXTENDED
RESULT
RESULT
15
8
RESULT
RESULT
RESULT
7
0
FRACTION
FRACTION
FRACTION
NOTE
The long-word result contains only the least significant 24 bits of
integer precision.
For all sizes, the 8-bit fractional portion of the result is returned to the low byte of the
data register, Dx 7 – 0. User software can make use of the fractional data to reduce
cumulative errors in lengthy calculations or implement rounding algorithms different
from that provided by other forms of TBLS. The previously described assumed radix
point places two restrictions on the programmer:
1. Tables are limited to 257 entries in length.
2. Interpolation resolution is limited to 1/256, the distance between consecutive table entries. The assumed radix point should not, however, be construed by the
programmer as a requirement that the independent variable be calculated as a
fractional number in the range 0 < π < 255. On the contrary, X should be considered an integer in the range 0 < π < 65535, realizing that the table is actually a
compressed representation of a linearized function in which only every 256th
value is actually stored in memory.
7-8
M68000 FAMILY PROGRAMMER’S REFERENCE MANUAL
MOTOROLA
CPU32 Instructions
TBLS
TBLSN
TBLS
TBLSN
Table Lookup and Interpolate (Signed)
(CPU32)
Condition Codes:
X
—
N
∗
Z
∗
V
∗
C
0
X
N
Z
V
— Not affected.
— Set if the most significant bit of the result is set; cleared otherwise.
— Set if the result is zero; cleared otherwise.
— Set if the integer portion of an unrounded long result is not in the range, – (223)
≤ Result ≤ (223) – 1; cleared otherwise.
C — Always cleared.
Instruction Format:
TABLE LOOKUP AND INTERPOLATE
15
14
13
12
11
10
9
8
7
6
1
1
1
1
1
0
0
0
0
0
1
R
0
1
0
REGISTER Dx
SIZE
5
0
4
3
2
1
0
EFFECTIVE ADDRESS
MODE
REGISTER
0
0
0
0
0
DATA REGISTER INTERPOLATE
15
1
0
14
13
12
1
1
1
REGISTER Dx
MOTOROLA
11
1
1
10
0
R
9
0
0
8
0
1
7
0
6
0
SIZE
5
0
0
4
0
0
3
0
0
M68000 FAMILY PROGRAMMER’S REFERENCE MANUAL
2
1
0
REGISTER Dym
REGISTER Dyn
7-9
CPU32 Instructions
TBLS
TBLSN
Table Lookup and Interpolate (Signed)
(CPU32)
TBLS
TBLSN
Instruction Fields:
Effective address field (table lookup and interpolate mode only)—Specifies the
destination location. Only control alterable addressing modes are allowed as listed
in the following table:
Addressing Mode
Mode
Register
Addressing Mode
Mode
Register
Dn
—
—
(xxx).W
111
000
An
—
—
(xxx).L
111
001
(An)
—
—
# < data >
—
—
(An) +
—
—
– (An)
100
reg. number:An
(d16,An)
101
reg. number:An
(d16,PC)
111
010
(d8,An,Xn)
110
reg. number:An
(d8,PC,Xn)
111
011
(bd,An,Xn)
110
reg. number:An
(bd,PC,Xn)
111
011
Size Field—Specifies the size of operation.
00 — Byte Operation
01 — Word Operation
10 — Long Operation
Register field—Specifies the destination data register, Dx. On entry, the register
contains the interpolation fraction and entry number.
Dym, Dyn field—If the effective address mode field is nonzero, this operand register is
unused and should be zero. If the effective address mode field is zero, the surface
interpolation variant of this instruction is implied, and Dyn specifies one of the two
source operands.
Rounding mode field—The R-bit controls the rounding of the final result. When R = 0,
the result is rounded according to the round-to-nearest algorithm. When R = 1, the
result is returned unrounded.
7-10
M68000 FAMILY PROGRAMMER’S REFERENCE MANUAL
MOTOROLA
CPU32 Instructions
TBLU
TBLUN
Operation:
Table Lookup and Interpolation (Unsigned)
(CPU32)
TBLU
TBLUN
Rounded:
ENTRY(n) + {(ENTRY(n + 1) – ENTRY(n)) x Dx 7 – 0} ÷ 256 → Dx
Unrounded:
ENTRY(n) x 256 + {(ENTRY(n + 1) – ENTRY(n)) x Dx 7 – 0} → Dx
Where ENTRY(n) and ENTRY(n + 1) are either:
1. Consecutive entries in the table pointed to by the < ea > and
indexed by Dx 15 – 8 π SIZE or;
2. The registers Dym, Dyn respectively
Assembler
Syntax:
TBLU. < size > < ea > ,Dx
TBLUN. < size > < ea > ,Dx
TBLU. < size > Dym:Dyn, Dx
TBLUN. < size > Dym:Dyn, Dx
Attributes:
Size = (Byte, Word, Long)
Result rounded
Result not rounded
Result rounded
Result not rounded
Description: The TBLU and TBLUN instructions allow the efficient use of piecewise linear,
compressed data tables to model complex functions. The TBLU instruction has two
modes of operation: table lookup and interpolate mode and data register interpolate
mode.
For table lookup and interpolate mode, data register Dx 15 – 0 contains the
independent variable X. The effective address points to the start of a unsigned byte,
word, or long-word table containing a linearized representation of the dependent
variable, Y, as a function of X. In general, the independent variable, located in the loworder word of Dx, consists of an 8-bit integer part and an 8-bit fractional part. An
assumed radix point is located between bits 7 and 8. The integer part, Dx 15 – 8, is
scaled by the operand size and is used as an offset into the table. The selected entry
in the table is subtracted from the next consecutive entry. A fractional portion of this
difference is taken by multiplying by the interpolation fraction, Dx 7 – 0. The adjusted
difference is then added to the selected table entry. The result is returned in the
destination data register, Dx.
MOTOROLA
M68000 FAMILY PROGRAMMER’S REFERENCE MANUAL
7-11
CPU32 Instructions
TBLU
TBLUN
TBLU
TBLUN
Table Lookup and Interpolation (Unsigned)
(CPU32)
For register interpolate mode, the interpolation occurs using the Dym and Dyn registers
in place of the two table entries. For this mode, only the fractional portion, Dx 7 – 0, is
used in the interpolation and the integer portion, Dx 15 – 8, is ignored. The register
interpolation mode may be used with several table lookup and interpolations to model
multidimensional functions.
Signed table entries range from – 2n – 1 to 2n – 1 – 1; whereas, unsigned table entries
range from 0 to 2n – 1 where n is 8, 16, or 32 for byte, word, and long-word tables,
respectively. The unsigned and unrounded table results will be zero-extended instead
of sign-extended.
Rounding of the result is optionally selected via the "R" instruction field. If R = 0
(TABLE), the fractional portion is rounded according to the round-to-nearest algorithm.
The rounding procedure can be summarized by the following table:
Adjusted Difference
Fraction
Rounding
Adjustme
nt
≥ 1/2
+1
< 1/2
+0
The adjusted difference is then added to the selected table entry. The rounded result
is returned in the destination data register, Dx. Only the portion of the register
corresponding to the selected size is affected.
BYTE
WORD
LONG
31
24
UNAFFECTED
UNAFFECTED
RESULT
23
16
UNAFFECTED
UNAFFECTED
RESULT
15
8
UNAFFECTED
RESULT
RESULT
7
0
RESULT
RESULT
RESULT
If R = 1 (TBLUN), the result is returned in register Dx without rounding. If the size is
byte, the integer portion of the result is returned in Dx 15 – 8; the integer portion of a
word result is stored in Dx 23 – 8; the least significant 24 bits of a long result are stored
in Dx 31 – 8. Byte and word results are sign-extended to fill the entire 32-bit register.
7-12
M68000 FAMILY PROGRAMMER’S REFERENCE MANUAL
MOTOROLA
CPU32 Instructions
TBLU
TBLUN
Table Lookup and Interpolation (Unsigned)
BYTE
WORD
LONG
(CPU32)
31
24
SIGN-EXTENDED
SIGN-EXTENDED
RESULT
23
16
SIGN-EXTENDED
RESULT
RESULT
15
8
RESULT
RESULT
RESULT
TBLU
TBLUN
7
0
FRACTION
FRACTION
FRACTION
NOTE
The long-word result contains only the least significant 24 bits of
integer precision.
For all sizes, the 8-bit fractional portion of the result is returned in the low byte of the
data register, Dx 7 – 0. User software can make use of the fractional data to reduce
cumulative errors in lengthy calculations or implement rounding algorithms different
from that provided by other forms of TBLU. The previously described assumed radix
point places two restrictions on the programmer:
1. Tables are limited to 257 entries in length.
2. Interpolation resolution is limited to 1/256, the distance between consecutive table entries. The assumed radix point should not, however, be construed by the
programmer as a requirement that the independent variable be calculated as a
fractional number in the range 0 ≤ X ≤ 255. On the contrary, X should be considered to be an integer in the range 0 ≤ X ≤ 65535, realizing that the table is actually a compressed representation of a linearized function in which only every
256th value is actually stored in memory.
Condition Codes:
X
—
N
∗
Z
∗
V
∗
C
0
X — Not affected.
N — Set if the most significant bit of the result is set; cleared otherwise.
Z — Set if the result is zero; cleared otherwise.
V — Set if the integer portion of an unrounded long result is not in the range, – (223)
≤ Result ≤ (223) – 1; cleared otherwise.
C — Always cleared.
MOTOROLA
M68000 FAMILY PROGRAMMER’S REFERENCE MANUAL
7-13
CPU32 Instructions
TBLU
TBLUN
Table Lookup and Interpolation (Unsigned)
(CPU32)
TBLU
TBLUN
Instruction Format:
TABLE LOOKUP AND INTERPOLATE
15
14
13
12
11
10
9
8
7
6
1
1
1
1
1
0
0
0
0
0
0
R
0
1
SIZE
0
0
REGISTER Dx
5
0
4
3
2
1
0
EFFECTIVE ADDRESS
MODE
REGISTER
0
0
0
0
0
DATA REGISTER INTERPOLATE
15
1
0
14
13
12
1
1
1
REGISTER Dx
11
1
0
10
0
R
9
0
0
8
0
0
7
0
SIZE
6
0
5
0
0
4
0
0
3
0
0
2
1
0
REGISTER Dym
REGISTER Dyn
Instruction Fields:
Effective address field (table lookup and interpolate mode only)—Specifies the
destination location. Only control alterable addressing modes are allowed as listed
in the following table:
Addressing Mode
Mode
Register
Addressing Mode
Mode
Register
Dn
—
—
(xxx).W
111
000
An
—
—
(xxx).L
111
001
(An)
010
reg. number:An
# < data >
—
—
(An) +
—
—
– (An)
100
reg. number:An
(d16,An)
101
reg. number:An
(d16,PC)
111
010
(d8,An,Xn)
110
reg. number:An
(d8,PC,Xn)
111
011
(bd,An,Xn)
110
reg. number:An
(bd,PC,Xn)
111
011
Size field—Specifies the size of operation.
00 — Byte Operation
01 — Word Operation
10 — Long Operation
7-14
M68000 FAMILY PROGRAMMER’S REFERENCE MANUAL
MOTOROLA
CPU32 Instructions
TBLU
TBLUN
Table Lookup and Interpolation (Unsigned)
(CPU32)
TBLU
TBLUN
Register field—Specifies the destination data register, Dx. On entry, the register
contains the interpolation fraction and entry number.
Dym, Dyn field—If the effective address mode field is nonzero, this operand register is
unused and should be zero. If the effective address mode field is zero, the surface
interpolation variant of this instruction is implied, and Dyn specifies one of the two
source operands.
Rounding mode field—The R-bit controls the rounding of the final result. When R = 0,
the result is rounded according to the round-to-nearest algorithm. When R = 1,
the result is returned unrounded.
MOTOROLA
M68000 FAMILY PROGRAMMER’S REFERENCE MANUAL
7-15
CPU32 Instructions
7-16
M68000 FAMILY PROGRAMMER’S REFERENCE MANUAL
MOTOROLA
SECTION 8
INSTRUCTION FORMAT SUMMARY
This section contains a listing of the M68000 family instructions in binary format. It is listed
in opcode order for the M68000 family instruction set.
8.1 INSTRUCTION FORMAT
The following paragraphs present a summary of the binary encoding fields.
8.1.1 Coprocessor ID Field
This field specifies which coprocessor in a system is to perform the operation. When using
directly supported floating-point instructions for the MC68040, this field must be set to one.
8.1.2 Effective Address Field
This field specifies which addressing mode is to be used. For some operations, there are
hardware-enforced restrictions on the available addressing modes allowed.
8.1.3 Register/Memory Field
This field is common to all arithmetic instructions. A zero in this field indicates a register-toregister operation, and a one indicates an < ea > -to-register operation.
8.1.4 Source Specifier Field
This field is common to all artihmetic instructions. The value of the register/memory (R/M)
field affects this field,s definition. If R/M = 0, specifies the source floating-point data register
(FPDR). If R/M = 1, specifies the source operand data format.
000
001
010
011
100
101
110
MOTOROLA
— Long-Word Integer (L)
— Single-Precision Real (S)
— Extended-Precision Real (X)
— Packed-Decimal Real (P)
— Word Integer (W)
— Double-Precision Real (D)
— Byte Integer (B)
M68000 FAMILY PROGRAMMER’S REFERENCE MANUAL
8-1
Instruction Format Summary
8.1.5 Destination Register Field
This field is common to all arithmetic instructions. It specifies the FPDR that that will be the
destination. The results are always stored in this register.
8.1.6 Conditional Predicate Field
This field is common to all conditional instructions and specifies the conditional test that is
to be evaluated. Table 8-1 shows the binary encodings for the conditional tests.
8.1.7 Shift and Rotate Instructions
The following paragraphs define the fields used with the shift and rotate instructions.
8.1.7.1 Count Register Field. If i/r = 0, this field contains the rotate (shift) count of 1 – 8 (a
zero specifies 8). If i/r = 1, this field specifies a data register that contains the rotate (shift)
count. The following shift and rotate fields are encoded as follows:
dr field
0 — Rotate (shift) Right
1 — Rotate (shift) Left
i/r field
0 — Immediate Rotate (shift) Count
1 — Register Rotate (shift) Count
8.1.7.2 Register Field. This field specifies a data register to be rotated (shifted).
8-2
M68000 FAMILY PROGRAMMER’S REFERENCE MANUAL
MOTOROLA
Instruction Format Summary
Table 8-1. Conditional Predicate Field Encoding
Conditional
Predicate
MOTOROLA
Mnemonic
Definition
000000
F
False
000001
EQ
Equal
000010
OGT
Ordered Greater Than
000011
OGE
Ordered Greater Than or Equal
000100
OLT
Ordered Less Than
000101
OLE
Ordered Less Than or Equal
000110
OGL
Ordered Greater Than or Less Than
000111
OR
Ordered
001000
UN
Unordered
001001
UEQ
Unordered or Equal
001010
UGT
Unordered or Greater Than
001011
UGE
Unordered or Greater Than or Equal
001100
ULT
Unordered or Less Than
001101
ULE
Unordered or Less Than or Equal
001110
NE
Not Equal
001111
T
True
010000
SF
Signaling False
010001
SEQ
Signaling Equal
010010
GT
Greater Than
010011
GE
Greater Than or Equal
010100
LT
Less Than
010101
LE
Less Than or Equal
010110
GL
Greater Than or Less Than
010111
GLE
011000
NGLE
011001
NGL
Not (Greater Than or Less Than)
011010
NLE
Not (Less Than or Equal)
011011
NLT
Not (Less Than)
011100
NGE
Not (Greater Than or Equal)
011101
NGT
Not (Greater Than)
011110
SNE
Signaling Not Equal
011111
ST
Greater Than or Less Than or Equal
Not (Greater Than or Less Than or Equal)
Signaling True
M68000 FAMILY PROGRAMMER’S REFERENCE MANUAL
8-3
Instruction Format Summary
8.1.8 Size Field
This field specifies the size of the operation. The encoding is as follows:
00 — Byte Operation
01 — Word Operation
10 — Long Operation
8.1.9 Opmode Field
Refer to the applicable instruction descriptions for the encoding of this field in Section 4
Integer Instructions, Section 5 Floating Point Instructions, Section 6 Supervisor
(Privaleged) Instructions, and Section 7 CPU32 Instructions.
8.1.10 Address/Data Field
This field specifies the type of general register. The encoding is:
0 — Data Register
1 — Address Register
8.2 OPERATION CODE MAP
Table 8-2 lists the encoding for bits 15 – 12 and the operation performed.
Table 8-2. Operation Code Map
Bits 15 – 12
8-4
Operation
0000
Bit Manipulation/MOVEP/Immed iate
0001
Move Byte
0010
Move Long
0011
Move Word
0100
Miscellaneous
0101
ADDQ/SUBQ/Scc/DBcc/TRAPc c
0110
Bcc/BSR/BRA
0111
MOVEQ
1000
OR/DIV/SBCD
1001
SUB/SUBX
1010
(Unassigned, Reserved)
1011
CMP/EOR
1100
AND/MUL/ABCD/EXG
1101
ADD/ADDX
1110
Shift/Rotate/Bit Field
1111
Coprocessor Interface/MC68040 and
CPU32 Extensions
M68000 FAMILY PROGRAMMER’S REFERENCE MANUAL
MOTOROLA
Instruction Format Summary
ORI to CCR
15
0
0
14
0
0
13
0
0
12
0
0
11
0
0
10
0
0
9
0
0
8
0
0
14
0
13
0
12
0
11
0
10
0
9
0
15
14
13
12
11
10
9
8
0
0
0
0
0
0
0
0
7
0
6
0
5
1
4
3
1
1
8-BIT BYTE DATA
2
1
1
0
0
0
8
7
6
0
0
1
16-BIT WORD DATA
5
1
4
1
2
1
1
0
0
0
6
5
4
3
2
1
0
EFFECTIVE ADDRESS
MODE
REGISTER
8-BIT BYTE DATA
6
0
5
1
4
3
1
1
8-BIT BYTE DATA
8
7
6
0
0
1
16-BIT WORD DATA
5
1
4
1
5
4
ORI to SR
15
0
3
1
ORI
7
SIZE
16-BIT WORD DATA
32-BIT LONG DATA
ANDI to CCR
15
0
0
14
0
0
13
0
0
12
0
0
11
0
0
10
0
0
9
1
0
8
0
0
14
0
13
0
12
0
11
0
10
0
9
1
15
14
13
12
11
10
9
8
0
0
0
0
0
0
0
0
7
0
2
1
1
0
0
0
2
1
1
0
0
0
ANDI to SR
15
0
3
1
ANDI
7
6
SIZE
16-BIT WORD DATA
3
2
1
0
EFFECTIVE ADDRESS
MODE
REGISTER
8-BIT BYTE DATA
32-BIT LONG DATA
MOTOROLA
M68000 FAMILY PROGRAMMER’S REFERENCE MANUAL
8-5
Instruction Format Summary
SUBI
15
14
13
12
11
10
9
8
0
0
0
0
0
1
0
0
7
6
5
SIZE
16-BIT WORD DATA
4
3
2
1
0
EFFECTIVE ADDRESS
MODE
REGISTER
8-BIT BYTE DATA
32-BIT LONG DATA
RTM
15
0
14
0
13
0
12
0
11
0
10
1
9
1
8
0
7
1
6
1
5
0
4
0
5
4
3
D/A
2
1
0
REGISTER
CALLM
15
14
13
12
11
10
9
8
7
6
0
0
0
0
0
1
1
0
1
1
0
0
0
0
0
0
0
0
15
14
13
12
11
10
9
8
7
6
5
0
0
0
0
0
1
1
0
5
3
2
1
0
EFFECTIVE ADDRESS
MODE
REGISTER
ARGUMENT COUNT
ADDI
SIZE
16-BIT WORD DATA
4
3
2
1
0
EFFECTIVE ADDRESS
MODE
REGISTER
8-BIT BYTE DATA
32-BIT LONG DATA
CMP2
15
14
13
12
11
0
0
0
0
0
D/A
REGISTER
10
9
SIZE
8
7
6
0
1
1
0
0
0
0
0
0
0
10
9
8
7
6
5
0
1
1
0
0
0
4
3
2
1
0
EFFECTIVE ADDRESS
MODE
REGISTER
0
0
0
0
0
CHK2
15
14
13
12
11
0
0
0
0
0
D/A
8-6
REGISTER
1
SIZE
0
0
0
4
3
2
1
0
EFFECTIVE ADDRESS
MODE
REGISTER
0
0
0
0
0
M68000 FAMILY PROGRAMMER’S REFERENCE MANUAL
MOTOROLA
Instruction Format Summary
EORI to CCR
15
0
0
14
0
0
13
0
0
12
0
0
11
1
0
10
0
0
9
1
0
8
0
0
14
0
13
0
12
0
11
1
10
0
9
1
15
14
13
12
11
10
9
8
0
0
0
0
1
0
1
0
7
0
6
0
5
1
4
3
2
1
1
1
BYTE DATA (8 BITS)
8
7
6
0
0
1
16-BIT WORD DATA
5
1
4
1
6
5
4
6
5
1
0
0
0
1
0
0
0
EORI to SR
15
0
3
1
2
1
EORI
7
SIZE
16-BIT WORD DATA
3
2
1
0
EFFECTIVE ADDRESS
MODE
REGISTER
16-BIT BYTE DATA
32-BIT LONG DATA
CMPI
15
14
13
12
11
10
9
8
0
0
0
0
1
1
0
0
7
SIZE
16-BIT WORD DATA
4
3
2
1
0
EFFECTIVE ADDRESS
MODE
REGISTER
8-BIT BYTE DATA
32-BIT LONG DATA
BTST
BIT NUMBER STATIC, SPECIFIED AS IMMEDIATE DATA
15
14
13
12
11
10
9
8
7
6
0
0
0
0
1
0
0
0
0
0
0
0
0
0
0
0
0
0
15
14
13
12
11
10
9
8
7
6
0
0
0
0
1
0
0
0
0
1
0
0
0
0
0
0
0
0
5
4
3
2
1
0
EFFECTIVE ADDRESS
MODE
REGISTER
BIT NUMBER
BCHG
BIT NUMBER STATIC, SPECIFIED AS IMMEDIATE DATA
MOTOROLA
5
4
3
2
1
0
EFFECTIVE ADDRESS
MODE
REGISTER
BIT NUMBER
M68000 FAMILY PROGRAMMER’S REFERENCE MANUAL
8-7
Instruction Format Summary
BCLR
BIT NUMBER STATIC, SPECIFIED AS IMMEDIATE DATA
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
EFFECTIVE ADDRESS
MODE
REGISTER
BIT NUMBER
0
0
0
0
1
0
0
0
1
0
0
0
0
0
0
0
0
0
15
14
13
12
11
10
9
8
7
6
0
0
0
0
1
0
0
0
1
1
0
0
0
0
0
0
0
15
14
13
12
11
10
9
8
7
6
5
0
0
0
0
1
1
1
0
dr
0
0
0
0
0
0
11
1
0
0
10
9
8
0
6
1
0
0
0
0
7
1
Du1
Du2
5
1
0
0
4
1
0
0
10
9
8
7
6
5
4
0
1
1
BSET
BIT NUMBER STATIC, SPECIFIED AS IMMEDIATE DATA
5
4
3
2
1
0
EFFECTIVE ADDRESS
MODE
REGISTER
BIT NUMBER
MOVES
A/D
REGISTER
SIZE
4
3
2
1
0
EFFECTIVE ADDRESS
MODE
REGISTER
0
0
0
0
0
CAS2
15
0
D/A1
D/A2
14
0
13
0
Rn1
Rn2
12
0
SIZE
3
1
0
0
2
1
1
0
Dc1
Dc2
0
0
CAS
15
14
13
12
11
0
0
0
0
1
0
0
0
0
0
15
14
13
12
0
0
0
0
SIZE
0
0
Du
0
3
2
1
0
EFFECTIVE ADDRESS
MODE
REGISTER
0
0
Dc
BTST
BIT NUMBER DYNAMIC, SPECIFIED IN A REGISTER
8-8
11
10
REGISTER
9
8
7
6
1
0
0
5
4
3
2
1
0
EFFECTIVE ADDRESS
MODE
REGISTER
M68000 FAMILY PROGRAMMER’S REFERENCE MANUAL
MOTOROLA
Instruction Format Summary
BCHG
BIT NUMBER DYNAMIC, SPECIFIED IN A REGISTER
15
14
13
12
0
0
0
0
15
14
13
12
0
0
0
0
15
14
13
12
0
0
0
0
15
14
13
12
0
0
0
0
11
10
9
REGISTER
8
7
6
1
0
1
5
4
3
2
1
0
EFFECTIVE ADDRESS
MODE
REGISTER
BCLR
BIT NUMBER DYNAMIC, SPECIFIED IN A REGISTER
11
10
9
REGISTER
8
7
6
1
1
0
5
4
3
2
1
0
EFFECTIVE ADDRESS
MODE
REGISTER
BSET
BIT NUMBER DYNAMIC, SPECIFIED IN A REGISTER
11
10
9
REGISTER
8
7
6
1
1
1
8
7
6
5
4
3
2
1
0
EFFECTIVE ADDRESS
MODE
REGISTER
MOVEP
11
10
9
DATA REGISTER
OPMODE
5
4
3
2
0
0
1
5
4
3
2
SOURCE
1
0
ADDRESS
REGISTER
16-BIT DISPLACEMENT
MOVEA
15
14
0
0
13
12
11
10
9
DESTINATION
REGISTER
SIZE
8
7
6
0
0
1
MODE
1
0
REGISTER
MOVE
15
14
0
0
13
12
11
SIZE
10
9
8
7
DESTINATION
REGISTER
MODE
6
5
4
3
2
SOURCE
MODE
1
0
REGISTER
MOVE from SR
15
14
13
12
11
10
9
8
7
6
0
1
0
0
0
0
0
0
1
1
MOTOROLA
5
4
3
2
SOURCE
MODE
M68000 FAMILY PROGRAMMER’S REFERENCE MANUAL
1
0
REGISTER
8-9
Instruction Format Summary
MOVE from CCR
15
14
13
12
11
10
9
8
7
6
5
0
1
0
0
0
0
1
0
1
1
15
14
13
12
11
10
9
8
7
6
5
0
1
0
0
0
0
0
0
15
14
13
12
11
10
9
8
6
5
0
1
0
0
0
0
1
0
5
4
3
2
1
0
EFFECTIVE ADDRESS
MODE
REGISTER
NEGX
SIZE1
4
3
2
1
0
EFFECTIVE ADDRESS
MODE
REGISTER
CLR
7
SIZE
4
3
2
1
0
EFFECTIVE ADDRESS
MODE
REGISTER
MOVE to CCR
15
14
13
12
11
10
9
8
7
6
0
1
0
0
0
1
0
0
1
1
15
14
13
12
11
10
9
8
7
6
5
0
1
0
0
0
1
0
0
15
14
13
12
11
10
9
8
6
5
0
1
0
0
0
1
1
0
5
4
3
2
1
0
EFFECTIVE ADDRESS
MODE
REGISTER
NEG
SIZE
4
3
2
1
0
EFFECTIVE ADDRESS
MODE
REGISTER
NOT
7
SIZE
4
3
2
1
0
EFFECTIVE ADDRESS
MODE
REGISTER
MOVE to SR
15
14
13
12
11
10
9
8
7
6
0
1
0
0
0
1
1
0
1
1
8-10
4
3
2
1
0
EFFECTIVE ADDRESS
MODE
REGISTER
M68000 FAMILY PROGRAMMER’S REFERENCE MANUAL
MOTOROLA
Instruction Format Summary
EXT, EXTB
15
0
14
1
13
0
12
0
11
1
10
0
9
0
8
7
OPMODE
6
5
0
4
0
3
0
2
1
0
REGISTER
14
1
13
0
12
0
11
1
10
0
5
0
4
0
3
1
2
1
0
REGISTER
15
14
13
12
11
10
9
8
7
6
5
4
0
1
0
0
1
0
0
0
0
0
14
1
13
0
12
0
11
1
10
0
9
0
8
0
7
0
6
1
5
0
4
0
3
0
2
14
1
13
0
12
0
11
1
10
0
9
0
8
0
7
0
6
1
5
0
4
0
3
1
2
15
14
13
12
11
10
9
8
7
6
5
4
0
1
0
0
1
0
0
0
0
1
14
1
13
0
12
0
11
1
10
0
9
1
8
0
7
1
6
1
LINK
LONG
15
0
9
8
7
6
0
0
0
0
HIGH-ORDER DISPLACEMENT
LOW-ORDER DISPLACEMENT
NBCD
3
2
1
0
EFFECTIVE ADDRESS
MODE
REGISTER
SWAP
15
0
1
0
REGISTER
BKPT
15
0
1
VECTOR
0
PEA
3
2
1
0
EFFECTIVE ADDRESS
MODE
REGISTER
BGND
15
0
MOTOROLA
5
1
4
1
3
1
M68000 FAMILY PROGRAMMER’S REFERENCE MANUAL
2
0
1
1
0
0
8-11
Instruction Format Summary
ILLEGAL
15
0
14
1
13
0
12
0
11
1
10
0
9
1
8
0
7
1
6
1
5
1
4
1
15
14
13
12
11
10
9
8
7
6
5
4
0
1
0
0
1
0
1
0
1
1
15
14
13
12
11
10
9
8
7
6
5
0
1
0
0
1
0
1
0
15
14
13
12
11
10
9
8
7
6
5
0
1
0
0
1
1
0
0
0
0
0
SIZE
0
0
0
0
0
5
3
1
2
1
1
0
0
0
TAS
3
2
1
0
EFFECTIVE ADDRESS
MODE
REGISTER
TST
SIZE
4
3
2
1
0
EFFECTIVE ADDRESS
MODE
REGISTER
MULU
LONG
0
REGISTER DI
4
3
2
1
0
EFFECTIVE ADDRESS
MODE
REGISTER
0
0
REGISTER Dh
MULS
LONG
15
14
13
12
11
10
9
8
7
6
0
1
0
0
1
1
0
0
0
0
1
SIZE
0
0
0
0
0
5
0
REGISTER DI
4
3
2
1
0
EFFECTIVE ADDRESS
MODE
REGISTER
0
0
REGISTER Dh
DIVU, DIVUL
LONG
15
14
13
12
11
10
9
8
7
6
0
1
0
0
1
1
0
0
0
0
0
SIZE
0
0
0
0
0
8-12
REGISTER Dq
0
4
3
2
1
0
EFFECTIVE ADDRESS
MODE
REGISTER
0
0
REGISTER Dr
M68000 FAMILY PROGRAMMER’S REFERENCE MANUAL
MOTOROLA
Instruction Format Summary
DIVS, DIVSL
LONG
15
14
13
12
11
10
9
8
7
6
0
1
0
0
1
1
0
0
0
1
1
SIZE
0
0
0
0
0
8
0
7
0
0
REGISTER Dq
5
4
3
2
1
0
EFFECTIVE ADDRESS
MODE
REGISTER
0
0
REGISTER Dr
TRAP
15
0
14
1
13
0
12
0
11
1
10
1
9
1
6
1
5
0
4
0
3
2
1
VECTOR
0
14
1
13
0
12
0
11
1
10
1
9
8
7
6
1
0
0
1
WORD DISPLACEMENT
5
0
4
1
3
0
2
1
0
REGISTER
14
1
13
0
12
0
11
1
10
1
9
1
8
0
7
0
6
1
5
0
4
1
3
1
2
1
0
REGISTER
14
1
13
0
12
0
11
1
10
1
9
1
8
0
7
0
6
1
5
1
4
0
3
dr
2
1
0
REGISTER
14
1
13
0
12
0
11
1
10
1
9
1
8
0
7
0
6
1
5
1
4
1
3
0
2
0
1
0
0
0
14
1
13
0
12
0
11
1
10
1
9
1
8
0
7
0
6
1
5
1
4
1
3
0
2
0
1
0
0
1
LINK
WORD
15
0
UNLK
15
0
MOVE USP
15
0
RESET
15
0
NOP
15
0
MOTOROLA
M68000 FAMILY PROGRAMMER’S REFERENCE MANUAL
8-13
Instruction Format Summary
STOP
15
0
14
1
13
0
12
0
11
1
10
1
9
1
14
1
13
0
12
0
11
1
10
1
9
1
14
1
13
0
12
0
11
1
14
1
13
0
12
0
14
1
13
0
14
1
13
0
8
7
0
0
IMMEDIATE DATA
6
1
5
1
4
1
3
0
2
0
1
1
0
0
6
1
5
1
4
1
3
0
2
0
1
1
0
1
10
1
9
8
7
6
1
0
0
1
16-BIT DISPLACEMENT
5
1
4
1
3
0
2
1
1
0
0
0
11
1
10
1
9
1
8
0
7
0
6
1
5
1
4
1
3
0
2
1
1
0
0
1
12
0
11
1
10
1
9
1
8
0
7
0
6
1
5
1
4
1
3
0
2
1
1
1
0
0
12
0
11
1
10
1
9
1
8
0
7
0
6
1
5
1
4
1
3
0
2
1
1
1
0
1
13
12
0
0
REGISTER
11
1
10
1
9
1
8
0
7
0
6
5
4
1
1
1
CONTROL REGISTER
3
1
2
0
1
1
0
dr
RTE
15
0
8
0
7
0
RTD
15
0
RTS
15
0
TRAPV
15
0
RTR
15
0
MOVEC
15
0
A/D
8-14
14
1
M68000 FAMILY PROGRAMMER’S REFERENCE MANUAL
MOTOROLA
Instruction Format Summary
JSR
15
14
13
12
11
10
9
8
7
6
0
1
0
0
1
1
1
0
1
0
15
14
13
12
11
10
9
8
7
6
0
1
0
0
1
1
1
0
1
1
5
4
3
2
1
0
EFFECTIVE ADDRESS
MODE
REGISTER
JMP
5
4
3
2
1
0
EFFECTIVE ADDRESS
MODE
REGISTER
MOVEM
15
14
13
12
11
10
9
8
7
6
0
1
0
0
1
dr
0
0
1
SIZE
5
4
3
2
1
0
EFFECTIVE ADDRESS
MODE
REGISTER
REGISTER LIST MASK
LEA
15
14
13
12
0
1
0
0
15
14
13
12
0
1
0
0
15
14
13
12
0
1
0
1
15
14
13
12
0
1
0
1
11
10
9
REGISTER
8
7
6
1
1
1
8
7
6
5
4
3
2
1
0
EFFECTIVE ADDRESS
MODE
REGISTER
CHK
11
10
9
REGISTER
SIZE
5
0
4
3
2
1
0
EFFECTIVE ADDRESS
MODE
REGISTER
ADDQ
11
10
9
DATA
8
7
0
6
5
6
5
SIZE
4
3
2
1
0
EFFECTIVE ADDRESS
MODE
REGISTER
SUBQ
MOTOROLA
11
10
DATA
9
8
1
7
SIZE
4
3
2
1
0
EFFECTIVE ADDRESS
MODE
REGISTER
M68000 FAMILY PROGRAMMER’S REFERENCE MANUAL
8-15
Instruction Format Summary
DBcc
15
0
14
1
13
0
12
1
11
10
9
8
7
6
CONDITION
1
1
16-BIT DISPLACEMENT
5
0
4
0
3
1
2
1
0
REGISTER
14
1
13
0
12
1
11
10
9
CONDITION
6
1
5
1
4
1
3
1
2
15
14
13
12
11
7
6
5
4
0
1
0
1
1
1
14
1
13
1
12
0
11
10
9
8
7
6
5
4
3
2
0
0
0
0
8-BIT DISPLACEMENT
16-BIT DISPLACEMENT IF 8-BIT DISPLACEMENT = $00
32-BIT DISPLACEMENT IF 8-BIT DISPLACEMENT = $FF
1
0
14
1
13
1
12
0
11
10
9
8
7
6
5
4
3
2
0
0
0
1
8-BIT DISPLACEMENT
16-BIT DISPLACEMENT IF 8-BIT DISPLACEMENT = $00
32-BIT DISPLACEMENT IF 8-BIT DISPLACEMENT = $FF
1
0
14
1
13
1
12
0
11
1
0
TRAPcc
15
0
8
7
1
OPTIONAL WORD
OR LONG WORD
1
OPMODE
0
Scc
10
9
CONDITION
8
3
2
1
0
EFFECTIVE ADDRESS
MODE
REGISTER
BRA
15
0
BSR
15
0
Bcc
15
0
8-16
10
9
8
7
6
5
4
3
2
CONDITION
8-BIT DISPLACEMENT
16-BIT DISPLACEMENT IF 8-BIT DISPLACEMENT = $00
32-BIT DISPLACEMENT IF 8-BIT DISPLACEMENT = $FF
M68000 FAMILY PROGRAMMER’S REFERENCE MANUAL
MOTOROLA
Instruction Format Summary
MOVEQ
15
0
14
1
13
1
12
1
11
11
10
9
REGISTER
8
0
7
6
5
4
3
2
1
0
DATA
DIVU, DIVUL
WORD
15
14
13
12
1
0
0
0
14
0
13
0
14
0
14
0
10
9
8
7
6
5
4
3
2
1
0
EFFECTIVE ADDRESS
MODE
REGISTER
REGISTER
0
1
1
12
0
11
10
9
REGISTER Dy/Ay
8
1
7
0
6
0
5
0
4
0
3
R/M
2
1
0
REGISTER Dx/Ax
13
0
12
0
11
10
9
8
7
6
5
REGISTER Dy/Ay
1
0
1
0
16-BIT EXTENSION: ADJUSTMENT
4
0
3
R/M
2
1
0
REGISTER Dx/Ax
13
0
12
0
11
10
9
8
7
6
5
REGISTER Dy/Ay
1
1
0
0
16-BIT EXTENSION: ADJUSTMENT
4
0
3
R/M
2
1
0
REGISTER Dx/Ax
11
SBCD
15
1
PACK
15
1
UNPK
15
1
DIVS, DIVSL
WORD
15
14
13
12
1
0
0
0
15
14
13
12
1
0
0
0
10
9
REGISTER
8
7
6
1
1
1
8
7
6
5
4
3
2
1
0
EFFECTIVE ADDRESS
MODE
REGISTER
OR
MOTOROLA
11
10
REGISTER
9
OPMODE
5
4
3
2
1
0
EFFECTIVE ADDRESS
MODE
REGISTER
M68000 FAMILY PROGRAMMER’S REFERENCE MANUAL
8-17
Instruction Format Summary
SUBX
15
1
14
0
13
0
12
1
11
10
9
REGISTER Dy/Ay
8
1
7
15
14
13
12
11
8
7
1
0
0
1
15
14
13
12
1
0
0
1
REGISTER
14
0
13
1
12
1
11
10
9
REGISTER Ax
8
1
7
15
14
13
12
11
8
7
1
0
1
1
15
14
13
12
1
0
1
1
15
14
13
12
1
0
1
1
6
5
0
4
0
6
5
4
6
5
6
5
0
4
0
6
5
4
6
5
6
5
SIZE
3
R/M
2
1
0
REGISTER Dx/Ax
SUB
10
9
REGISTER
OPMODE
3
2
1
0
EFFECTIVE ADDRESS
MODE
REGISTER
SUBA
11
10
9
8
7
OPMODE
4
3
2
1
0
EFFECTIVE ADDRESS
MODE
REGISTER
CMPM
15
1
SIZE
3
1
2
1
0
REGISTER Ay
CMP
10
9
REGISTER
OPMODE
3
2
1
0
EFFECTIVE ADDRESS
MODE
REGISTER
CMPA
11
10
9
8
REGISTER
7
OPMODE
4
3
2
1
0
EFFECTIVE ADDRESS
MODE
REGISTER
EOR
8-18
11
10
REGISTER
9
8
7
OPMODE
4
3
2
1
0
EFFECTIVE ADDRESS
MODE
REGISTER
M68000 FAMILY PROGRAMMER’S REFERENCE MANUAL
MOTOROLA
Instruction Format Summary
MULU
WORD
15
14
13
12
1
1
0
0
14
1
13
0
15
14
1
11
10
9
8
7
6
5
4
3
2
1
0
EFFECTIVE ADDRESS
MODE
REGISTER
REGISTER
0
1
1
12
0
11
10
9
REGISTER Rx
8
1
7
0
6
0
5
0
4
0
13
12
11
8
7
6
5
4
1
0
0
REGISTER
1
1
1
14
1
13
0
12
0
11
10
9
REGISTER Rx
8
1
7
6
5
OPMODE
4
15
14
13
12
11
8
7
6
5
4
1
1
0
0
REGISTER
14
1
13
0
12
1
11
10
9
REGISTER Rx
8
1
7
SIZE
6
5
0
4
0
15
14
13
12
11
8
7
6
5
4
1
1
0
1
ABCD
15
1
3
R/M
2
1
0
REGISTER Ry
MULS
WORD
10
9
3
2
1
0
EFFECTIVE ADDRESS
MODE
REGISTER
EXG
15
1
3
2
1
0
REGISTER Ry
AND
10
9
OPMODE
3
2
1
0
EFFECTIVE ADDRESS
MODE
REGISTER
ADDX
15
1
3
R/M
2
1
0
REGISTER Ry
ADDA
MOTOROLA
10
REGISTER
9
OPMODE
3
2
1
0
EFFECTIVE ADDRESS
MODE
REGISTER
M68000 FAMILY PROGRAMMER’S REFERENCE MANUAL
8-19
Instruction Format Summary
ADD
15
14
13
12
1
1
0
1
11
10
9
8
REGISTER
7
6
5
5
OPMODE
4
3
2
1
0
EFFECTIVE ADDRESS
MODE
REGISTER
ASL, ASR
MEMORY SHIFT
15
14
13
12
11
10
9
8
7
6
1
1
1
0
0
0
0
dr
1
1
4
3
2
1
0
EFFECTIVE ADDRESS
MODE
REGISTER
LSL, LSR
MEMORY SHIFT
15
14
13
12
11
10
9
8
7
6
1
1
1
0
0
0
1
dr
1
1
5
4
3
2
1
0
EFFECTIVE ADDRESS
MODE
REGISTER
ROXL, ROXR
MEMORY ROTATE
15
14
13
12
11
10
9
8
7
6
1
1
1
0
0
1
0
dr
1
1
5
4
3
2
1
0
EFFECTIVE ADDRESS
MODE
REGISTER
ROL, ROR
MEMORY ROTATE
15
14
13
12
11
10
9
8
7
6
1
1
1
0
0
1
1
dr
1
1
15
14
13
12
11
10
9
8
7
6
1
1
1
0
1
0
0
0
1
1
0
0
0
0
Do
5
4
3
2
1
0
EFFECTIVE ADDRESS
MODE
REGISTER
BFTST
8-20
OFFSET
5
Dw
4
3
2
1
0
EFFECTIVE ADDRESS
MODE
REGISTER
WIDTH
M68000 FAMILY PROGRAMMER’S REFERENCE MANUAL
MOTOROLA
Instruction Format Summary
BFEXTU
15
14
13
12
11
10
9
8
7
6
1
1
1
0
1
0
0
1
1
1
0
REGISTER
Do
OFFSET
5
Dw
4
3
2
1
0
EFFECTIVE ADDRESS
MODE
REGISTER
WIDTH
BFCHG
15
14
13
12
11
10
9
8
7
6
1
1
1
0
1
0
1
0
1
1
0
0
0
0
Do
OFFSET
5
Dw
4
3
2
1
0
EFFECTIVE ADDRESS
MODE
REGISTER
WIDTH
BFEXTS
15
14
13
12
11
10
9
8
7
6
1
1
1
0
1
0
1
1
1
1
0
REGISTER
Do
OFFSET
5
Dw
4
3
2
1
0
EFFECTIVE ADDRESS
MODE
REGISTER
WIDTH
BFCLR
15
14
13
12
11
10
9
8
7
6
1
1
1
0
1
1
0
0
1
1
0
0
0
0
Do
15
14
13
12
11
10
9
8
7
6
1
1
1
0
1
1
0
1
1
1
OFFSET
5
Dw
4
3
2
1
0
EFFECTIVE ADDRESS
MODE
REGISTER
WIDTH
BFFFO
0
REGISTER
Do
OFFSET
5
Dw
4
3
2
1
0
EFFECTIVE ADDRESS
MODE
REGISTER
WIDTH
BFSET
15
14
13
12
11
10
9
8
7
6
1
1
1
0
1
1
1
0
1
1
0
0
0
0
Do
MOTOROLA
OFFSET
5
Dw
4
3
2
1
0
EFFECTIVE ADDRESS
MODE
REGISTER
WIDTH
M68000 FAMILY PROGRAMMER’S REFERENCE MANUAL
8-21
Instruction Format Summary
BFINS
15
14
13
12
11
10
9
8
7
6
1
1
1
0
1
1
1
1
1
1
0
REGISTER
Do
OFFSET
5
Dw
4
3
2
1
0
EFFECTIVE ADDRESS
MODE
REGISTER
WIDTH
ASL, ASR
REGISTER SHIFT
15
14
13
12
1
1
1
0
11
10
9
COUNT/
REGISTER
8
7
dr
6
SIZE
5
4
3
i/r
0
0
5
4
3
i/r
0
1
5
4
3
i/r
1
0
5
4
3
i/r
1
1
5
4
2
1
0
REGISTER
LSL, LSR
REGISTER SHIFT
15
14
13
12
1
1
1
0
11
10
9
COUNT/
REGISTER
8
7
dr
6
SIZE
2
1
0
REGISTER
ROXL, ROXR
REGISTER ROTATE
15
14
13
12
1
1
1
0
11
10
9
COUNT/
REGISTER
8
7
dr
6
SIZE
2
1
0
REGISTER
ROL, ROR
REGISTER ROTATE
15
14
13
12
11
10
9
COUNT/
REGISTER
8
7
1
1
1
0
15
14
13
12
11
10
9
8
7
6
1
1
1
1
0
0
0
0
0
0
0
0
0
R/W
0
0
0
dr
6
SIZE
2
1
0
REGISTER
PMOVE
MC68EC030, ACX REGISTERS
8-22
P REGISTER
0
3
2
1
0
EFFECTIVE ADDRESS
MODE
REGISTER
0
0
0
0
0
M68000 FAMILY PROGRAMMER’S REFERENCE MANUAL
MOTOROLA
Instruction Format Summary
PMOVE
MC68030 ONLY, TT REGISTERS
15
14
13
12
11
10
9
8
7
6
1
1
1
1
0
0
0
0
0
0
0
0
0
R/W
FD
0
0
0
15
14
13
12
11
10
9
8
7
6
5
1
1
1
1
0
0
0
0
0
0
0
0
1
0
0
0
R/W
0
0
0
15
14
13
12
11
10
9
8
7
6
1
1
1
1
0
0
0
0
0
0
0
0
1
0
1
0
0
0
0
0
P REGISTER
5
4
3
2
1
0
EFFECTIVE ADDRESS
MODE
REGISTER
0
0
0
0
0
PLOAD
0
4
3
2
1
0
EFFECTIVE ADDRESS
MODE
REGISTER
FC
PVALID
VAL CONTAINS ACCESS LEVEL TO TEST AGAINST
5
0
4
3
2
1
0
EFFECTIVE ADDRESS
MODE
REGISTER
0
0
0
0
0
PVALID
MAIN PROCESSOR REGISTER CONTAINS ACCESS LEVEL TO TEST AGAINST
15
14
13
12
11
10
9
8
7
6
5
1
1
1
1
0
0
0
0
0
0
0
0
1
0
1
0
0
0
0
0
0
5
4
3
2
1
0
EFFECTIVE ADDRESS
MODE
REGISTER
0
0
REGISTER
PFLUSH
MC68030 ONLY
15
14
13
12
11
10
9
8
7
6
1
1
1
1
0
0
0
0
0
0
0
0
1
0
0
MOTOROLA
MODE
MASK
4
3
2
1
0
EFFECTIVE ADDRESS
MODE
REGISTER
FC
M68000 FAMILY PROGRAMMER’S REFERENCE MANUAL
8-23
Instruction Format Summary
PFLUSH
PFLUSHA
PFLUSHS
MC68851
15
14
13
12
11
10
9
8
7
6
1
1
1
1
0
0
0
0
0
0
0
0
1
MODE
0
5
MASK
4
3
2
1
0
EFFECTIVE ADDRESS
MODE
REGISTER
FC
PMOVE
MC68851, TO/FROM TC, CRP, DRP, SRP, CAL, VAL, SCC, AND AC REGISTERS
15
14
13
12
11
10
9
8
7
6
1
1
1
1
0
0
0
0
0
0
0
1
0
R/W
0
0
0
15
14
13
12
11
10
9
8
7
6
1
1
1
1
0
0
0
0
0
0
0
1
0
R/W
FD
0
0
15
14
13
12
11
10
9
8
7
6
1
1
1
1
0
0
0
0
0
0
0
1
1
0
0
0
R/W
0
0
0
15
14
13
12
11
10
9
8
7
6
1
1
1
1
0
0
0
0
0
0
0
1
1
0
0
0
R/W
0
0
0
P REGISTER
5
0
4
3
2
1
0
EFFECTIVE ADDRESS
MODE
REGISTER
0
0
0
0
0
PMOVE
MC68030 ONLY, SRP, CRP, AND TC REGISTERS
P REGISTER
5
0
4
3
2
1
0
EFFECTIVE ADDRESS
MODE
REGISTER
0
0
0
0
0
PMOVE
MC68030 ONLY, MMUSR
5
0
4
3
2
1
0
EFFECTIVE ADDRESS
MODE
REGISTER
0
0
0
0
0
PMOVE
MC68EC030, ACUSR
8-24
5
0
4
3
2
1
0
EFFECTIVE ADDRESS
MODE
REGISTER
0
0
0
0
0
M68000 FAMILY PROGRAMMER’S REFERENCE MANUAL
MOTOROLA
Instruction Format Summary
PMOVE
MC68851, TO/FROM PSR AND PCSR REGISTERS
15
14
13
12
11
10
9
8
7
6
1
1
1
1
0
0
0
0
0
0
0
1
1
R/W
0
0
0
15
14
13
12
11
10
9
8
7
6
1
1
1
1
0
0
0
0
0
0
0
1
1
R/W
0
0
0
0
15
14
13
12
11
10
9
8
7
6
5
1
1
1
1
0
0
0
0
0
0
1
0
0
0
0
0
R/W
0
15
14
13
12
11
10
9
8
7
6
1
1
1
1
0
0
0
0
0
0
1
0
0
R/W
A
15
14
13
12
11
10
9
8
7
6
1
1
1
1
0
0
0
0
0
0
1
0
0
P REGISTER
5
0
4
3
2
1
0
EFFECTIVE ADDRESS
MODE
REGISTER
0
0
0
0
0
PMOVE
MC68851, TO/FROM BADX AND BACX REGISTERS
P REGISTER
5
4
3
2
1
0
EFFECTIVE ADDRESS
MODE
REGISTER
NUM
0
0
PTEST
MC68EC030
REGISTER
4
3
2
1
0
EFFECTIVE ADDRESS
MODE
REGISTER
FC
PTEST
MC68030 ONLY
LEVEL
5
REGISTER
4
3
2
1
0
EFFECTIVE ADDRESS
MODE
REGISTER
FC
PTEST
MC68851
MOTOROLA
LEVEL
R/W
A REGISTER
5
4
3
2
1
0
EFFECTIVE ADDRESS
MODE
REGISTER
FC
M68000 FAMILY PROGRAMMER’S REFERENCE MANUAL
8-25
Instruction Format Summary
PFLUSHR
15
14
13
12
11
10
9
8
7
6
5
1
1
1
1
0
0
0
0
0
0
1
0
1
0
0
0
0
0
0
0
0
15
14
13
12
11
10
9
8
7
6
5
1
1
1
1
0
0
0
0
0
1
0
0
0
0
0
0
0
0
0
0
14
1
0
13
1
0
12
1
0
11
0
0
10
0
0
9
8
7
6
0
0
0
1
0
0
0
0
16-BIT DISPLACEMENT
4
3
2
1
0
EFFECTIVE ADDRESS
MODE
REGISTER
0
0
0
0
0
PScc
4
3
2
1
0
EFFECTIVE ADDRESS
MODE
REGISTER
MC68851 CONDITION
PDBcc
15
1
0
5
0
4
0
3
2
1
0
1
COUNT REGISTER
MC68851 CONDITION
PTRAPcc
15
1
0
14
1
0
13
1
0
12
11
10
9
8
7
6
5
4
3
2
1
1
0
0
0
0
0
1
1
1
1
OPMODE
0
0
0
0
0
0
0
MC68851 CONDITION
16-BIT OPERAND OR MOST SIGNIFICANT WORD OF 32-BIT OPERAND (IF NEEDED)
LEAST SIGNIFICANT WORD OF 32-BIT OPERAND (IF NEEDED)
14
1
13
1
15
14
13
12
11
10
9
8
7
6
1
1
1
1
0
0
0
1
0
0
0
PBcc
15
1
12
11
10
9
8
7
6
5
4
3
2
1
1
0
0
0
0
1
SIZE
MC68851 CONDITION
16-BIT DISPLACEMENT OR MOST SIGNIFICANT WORD OF 32-BIT DISPLACEMENT
LEAST SIGNIFICANT WORD OF 32-BIT DISPLACEMENT (IF NEEDED)
0
PSAVE
8-26
5
4
3
2
1
0
EFFECTIVE ADDRESS
MODE
REGISTER
M68000 FAMILY PROGRAMMER’S REFERENCE MANUAL
MOTOROLA
Instruction Format Summary
PRESTORE
15
14
13
12
11
10
9
8
7
6
1
1
1
1
0
0
0
1
0
1
5
4
3
2
1
0
EFFECTIVE ADDRESS
MODE
REGISTER
PFLUSH
MC68EC040, POSTINCREMENT SOURCE AND DESTINATION
15
1
14
1
13
1
12
1
11
0
10
1
9
0
8
1
7
0
6
0
14
1
13
1
12
1
11
0
10
1
14
1
13
1
12
1
11
0
10
1
9
0
14
1
13
1
12
1
11
0
10
1
9
0
8
1
7
0
14
1
13
1
12
1
11
0
10
1
9
0
8
0
7
6
CACHE
13
1
12
1
11
0
10
1
9
0
8
0
7
6
CACHE
5
0
4
3
OPMODE
2
1
0
REGISTER
5
0
4
3
OPMODE
2
1
0
REGISTER
PFLUSH
MC68040/MC68LC040
15
1
9
0
8
1
7
0
6
0
PTEST
MC68040/MC68LC040
15
1
8
1
7
0
6
1
5
R/W
4
0
3
1
2
1
0
REGISTER
6
1
5
R/W
4
0
3
1
2
1
0
REGISTER
5
0
4
3
SCOPE
2
1
0
REGISTER
5
1
4
3
SCOPE
2
1
0
REGISTER
PTEST
MC68EC040
15
1
CINV
15
1
CPUSH
15
1
14
1
MOTOROLA
M68000 FAMILY PROGRAMMER’S REFERENCE MANUAL
8-27
Instruction Format Summary
MOVE16
ABSOLUTE LONG ADDRESS SOURCE OR DESTINATION
15
1
14
1
13
1
12
1
11
0
10
1
9
8
7
6
1
0
0
0
HIGH-ORDER ADDRESS
LOW-ORDER ADDRESS
5
0
4
3
OPMODE
2
1
0
REGISTER Ay
MOVE16
POSTINCREMENT SOURCE AND DESTINATION
15
1
1
14
13
12
1
1
1
REGISTER Ay
11
0
0
10
1
0
9
1
0
8
0
0
7
0
0
6
0
0
5
1
0
4
0
0
3
0
0
2
1
0
REGISTER Ax
0
0
0
TBLU, TBLUN
TABLE LOOKUP AND INTERPOLATE
15
14
13
12
11
10
9
8
7
6
1
1
1
1
1
0
0
0
0
0
0
R
0
1
SIZE
0
0
REGISTER Dx
5
0
4
3
2
1
0
EFFECTIVE ADDRESS
MODE
REGISTER
0
0
0
0
0
TBLS, TBLSN
TABLE LOOKUP AND INTERPOLATE
15
14
13
12
11
10
9
8
7
6
1
1
1
1
1
0
0
0
0
0
1
R
0
1
11
1
0
10
0
R
0
REGISTER Dx
SIZE
5
0
4
3
2
1
0
EFFECTIVE ADDRESS
MODE
REGISTER
0
0
0
0
0
TBLU, TBLUN
DATA REGISTER INTERPOLATE
15
1
0
8-28
14
13
12
1
1
1
REGISTER Dx
9
0
0
8
0
0
7
0
6
0
SIZE
5
0
0
4
0
0
3
0
0
M68000 FAMILY PROGRAMMER’S REFERENCE MANUAL
2
1
0
REGISTER Dym
REGISTER Dyn
MOTOROLA
Instruction Format Summary
TBLS, TBLSN
DATA REGISTER INTERPOLATE
15
1
0
14
13
12
1
1
1
REGISTER Dx
11
1
1
10
0
R
9
0
0
10
0
0
9
0
0
8
0
0
7
0
6
0
5
0
0
4
0
0
3
0
0
2
1
0
REGISTER Dym
REGISTER Dyn
6
0
1
5
0
0
4
0
0
3
0
0
2
0
0
1
0
0
0
0
0
SIZE
LPSTOP
15
1
0
14
1
0
13
1
0
12
1
0
11
1
0
11
10
9
COPROCESSOR
ID
8
7
0
0
1
1
IMMEDIATE DATA
FMOVECR
15
14
13
12
1
1
1
1
0
1
0
1
1
1
15
14
13
12
11
10
1
1
1
1
0
R/M
0
15
14
13
12
1
1
1
1
0
R/M
0
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
0
DESTINATION
REGISTER
ROM
OFFSET
FINT
9
8
7
6
COPROCESSOR
ID
0
0
0
SOURCE
SPECIFIER
DESTINATION
REGISTER
5
4
3
2
1
0
EFFECTIVE ADDRESS
MODE
REGISTER
0
0
0
5
4
0
0
0
1
FSINH
11
10
9
8
7
6
COPROCESSOR
ID
0
0
0
SOURCE
SPECIFIER
DESTINATION
REGISTER
3
2
1
0
EFFECTIVE ADDRESS
MODE
REGISTER
0
0
0
5
4
0
0
1
0
FINTRZ
15
14
13
12
1
1
1
1
0
R/M
0
MOTOROLA
11
9
8
7
6
COPROCESSOR
ID
0
0
0
SOURCE
SPECIFIER
10
DESTINATION
REGISTER
0
0
3
2
1
0
EFFECTIVE ADDRESS
MODE
REGISTER
0
0
M68000 FAMILY PROGRAMMER’S REFERENCE MANUAL
0
1
1
8-29
Instruction Format Summary
FLOGNP1
15
14
13
12
1
1
1
1
0
R/M
0
11
10
9
8
7
6
COPROCESSOR
ID
0
0
0
SOURCE
SPECIFIER
DESTINATION
REGISTER
5
4
3
2
1
0
EFFECTIVE ADDRESS
MODE
REGISTER
0
0
0
5
4
0
1
1
0
FETOXM1
15
14
13
12
1
1
1
1
0
R/M
0
11
10
9
8
7
6
COPROCESSOR
ID
0
0
0
SOURCE
SPECIFIER
DESTINATION
REGISTER
3
2
1
0
EFFECTIVE ADDRESS
MODE
REGISTER
0
0
0
5
4
1
0
0
0
FTANH
15
14
13
12
1
1
1
1
0
R/M
0
15
14
13
12
1
1
1
1
0
R/M
0
15
14
13
12
1
1
1
1
0
R/M
0
11
10
9
8
7
6
COPROCESSOR
ID
0
0
0
SOURCE
SPECIFIER
DESTINATION
REGISTER
3
2
1
0
EFFECTIVE ADDRESS
MODE
REGISTER
0
0
0
5
4
1
0
0
1
FATAN
11
10
9
8
7
6
COPROCESSOR
ID
0
0
0
SOURCE
SPECIFIER
DESTINATION
REGISTER
3
2
1
0
EFFECTIVE ADDRESS
MODE
REGISTER
0
0
0
5
4
1
0
1
0
FASIN
8-30
11
9
8
7
6
COPROCESSOR
ID
0
0
0
SOURCE
SPECIFIER
10
DESTINATION
REGISTER
0
0
3
2
1
0
EFFECTIVE ADDRESS
MODE
REGISTER
0
1
M68000 FAMILY PROGRAMMER’S REFERENCE MANUAL
1
0
0
MOTOROLA
Instruction Format Summary
FATANH
15
14
13
12
1
1
1
1
0
R/M
0
15
14
13
12
1
1
1
1
0
R/M
0
15
14
13
12
1
1
1
1
0
R/M
0
11
10
9
8
7
6
COPROCESSOR
ID
0
0
0
SOURCE
SPECIFIER
DESTINATION
REGISTER
5
4
3
2
1
0
EFFECTIVE ADDRESS
MODE
REGISTER
0
0
0
5
4
1
1
0
1
FSIN
11
10
9
8
7
6
COPROCESSOR
ID
0
0
0
SOURCE
SPECIFIER
DESTINATION
REGISTER
3
2
1
0
EFFECTIVE ADDRESS
MODE
REGISTER
0
0
0
5
4
1
1
1
0
FTAN
11
10
9
8
7
6
COPROCESSOR
ID
0
0
0
SOURCE
SPECIFIER
DESTINATION
REGISTER
3
2
1
0
EFFECTIVE ADDRESS
MODE
REGISTER
0
0
0
5
4
1
1
1
1
FETOX
15
14
13
12
1
1
1
1
0
R/M
0
11
10
9
8
7
6
COPROCESSOR
ID
0
0
0
SOURCE
SPECIFIER
DESTINATION
REGISTER
3
2
1
0
EFFECTIVE ADDRESS
MODE
REGISTER
0
0
1
5
4
0
0
0
0
FTWOTOX
15
14
13
12
1
1
1
1
0
R/M
0
11
10
9
8
7
6
COPROCESSOR
ID
0
0
0
SOURCE
SPECIFIER
DESTINATION
REGISTER
3
2
1
0
EFFECTIVE ADDRESS
MODE
REGISTER
0
0
1
5
4
0
0
0
1
FTENTOX
15
14
13
12
1
1
1
1
0
R/M
0
MOTOROLA
11
9
8
7
6
COPROCESSOR
ID
0
0
0
SOURCE
SPECIFIER
10
DESTINATION
REGISTER
0
0
3
2
1
0
EFFECTIVE ADDRESS
MODE
REGISTER
1
0
M68000 FAMILY PROGRAMMER’S REFERENCE MANUAL
0
1
0
8-31
Instruction Format Summary
FLOGN
15
14
13
12
1
1
1
1
0
R/M
0
11
10
9
8
7
6
COPROCESSOR
ID
0
0
0
SOURCE
SPECIFIER
DESTINATION
REGISTER
5
4
3
2
1
0
EFFECTIVE ADDRESS
MODE
REGISTER
0
0
1
5
4
0
1
0
0
FLOG10
15
14
13
12
1
1
1
1
0
R/M
0
11
10
9
8
7
6
COPROCESSOR
ID
0
0
0
SOURCE
SPECIFIER
DESTINATION
REGISTER
3
2
1
0
EFFECTIVE ADDRESS
MODE
REGISTER
0
0
1
5
4
0
1
0
1
FLOG2
15
14
13
12
1
1
1
1
0
R/M
0
11
10
9
8
7
6
COPROCESSOR
ID
0
0
0
SOURCE
SPECIFIER
DESTINATION
REGISTER
3
2
1
0
EFFECTIVE ADDRESS
MODE
REGISTER
0
0
1
5
4
0
1
1
0
FCOSH
15
14
13
12
1
1
1
1
0
R/M
0
11
10
9
8
7
6
COPROCESSOR
ID
0
0
0
SOURCE
SPECIFIER
DESTINATION
REGISTER
3
2
1
0
EFFECTIVE ADDRESS
MODE
REGISTER
0
0
1
5
4
1
0
0
1
FACOS
15
14
13
12
1
1
1
1
0
R/M
0
15
14
13
12
1
1
1
1
0
R/M
0
11
10
9
8
7
6
COPROCESSOR
ID
0
0
0
SOURCE
SPECIFIER
DESTINATION
REGISTER
3
2
1
0
EFFECTIVE ADDRESS
MODE
REGISTER
0
0
1
5
4
1
1
0
0
FCOS
8-32
11
9
8
7
6
COPROCESSOR
ID
0
0
0
SOURCE
SPECIFIER
10
DESTINATION
REGISTER
0
0
3
2
1
0
EFFECTIVE ADDRESS
MODE
REGISTER
1
1
M68000 FAMILY PROGRAMMER’S REFERENCE MANUAL
1
0
1
MOTOROLA
Instruction Format Summary
FGETEXP
15
14
13
12
1
1
1
1
0
R/M
0
11
10
9
8
7
6
COPROCESSOR
ID
0
0
0
SOURCE
SPECIFIER
DESTINATION
REGISTER
5
4
3
2
1
0
EFFECTIVE ADDRESS
MODE
REGISTER
0
0
1
5
4
1
1
1
0
FGETMAN
15
14
13
12
1
1
1
1
0
R/M
0
15
14
13
12
1
1
1
1
0
R/M
0
11
10
9
8
7
6
COPROCESSOR
ID
0
0
0
SOURCE
SPECIFIER
DESTINATION
REGISTER
3
2
1
0
EFFECTIVE ADDRESS
MODE
REGISTER
0
0
1
5
4
1
1
1
1
FMOD
11
10
9
8
7
6
COPROCESSOR
ID
0
0
0
SOURCE
SPECIFIER
DESTINATION
REGISTER
3
2
1
0
EFFECTIVE ADDRESS
MODE
REGISTER
0
1
0
5
4
0
0
0
1
FSGLDIV
15
14
13
12
1
1
1
1
0
R/M
0
15
14
13
12
1
1
1
1
0
R/M
0
11
10
9
8
7
6
COPROCESSOR
ID
0
0
0
SOURCE
SPECIFIER
DESTINATION
REGISTER
3
2
1
0
EFFECTIVE ADDRESS
MODE
REGISTER
0
1
0
5
4
0
1
0
0
FREM
11
10
9
8
7
6
COPROCESSOR
ID
0
0
0
SOURCE
SPECIFIER
DESTINATION
REGISTER
3
2
1
0
EFFECTIVE ADDRESS
MODE
REGISTER
0
1
0
5
4
0
1
0
1
FSCALE
15
14
13
12
1
1
1
1
0
R/M
0
MOTOROLA
11
9
8
7
6
COPROCESSOR
ID
0
0
0
SOURCE
SPECIFIER
10
DESTINATION
REGISTER
0
1
3
2
1
0
EFFECTIVE ADDRESS
MODE
REGISTER
0
0
M68000 FAMILY PROGRAMMER’S REFERENCE MANUAL
1
1
0
8-33
Instruction Format Summary
FSGLMUL
15
14
13
12
1
1
1
1
0
R/M
0
11
10
9
8
7
6
COPROCESSOR
ID
0
0
0
SOURCE
SPECIFIER
DESTINATION
REGISTER
5
4
3
2
1
0
EFFECTIVE ADDRESS
MODE
REGISTER
0
1
0
5
4
0
1
1
1
FSINCOS
15
14
13
12
1
1
1
1
0
R/M
0
15
14
13
12
1
1
1
1
0
R/M
0
15
14
13
12
1
1
1
1
0
R/M
0
15
14
13
12
1
1
1
1
0
R/M
0
15
14
13
12
1
1
1
1
0
R/M
0
11
10
9
8
7
6
COPROCESSOR
ID
0
0
0
SOURCE
SPECIFIER
DESTINATION
REGISTER
0
1
5
3
2
1
0
EFFECTIVE ADDRESS
MODE
REGISTER
DESTINATION
1
0
REGISTER, FPc
FCMP
11
10
9
8
7
6
COPROCESSOR
ID
0
0
0
SOURCE
SPECIFIER
DESTINATION
REGISTER
4
3
2
1
0
EFFECTIVE ADDRESS
MODE
REGISTER
0
1
1
5
4
1
0
0
0
FTST
11
10
9
8
7
6
COPROCESSOR
ID
0
0
0
SOURCE
SPECIFIER
DESTINATION
REGISTER
3
2
1
0
EFFECTIVE ADDRESS
MODE
REGISTER
0
1
1
5
4
1
0
1
0
FABS
11
10
9
8
7
6
COPROCESSOR
ID
0
0
0
SOURCE
SPECIFIER
3
2
1
0
EFFECTIVE ADDRESS
MODE
REGISTER
DESTINATION
REGISTER
OPMODE
FADD
8-34
11
9
8
7
6
COPROCESSOR
ID
0
0
0
SOURCE
SPECIFIER
10
DESTINATION
REGISTER
5
4
3
2
1
0
EFFECTIVE ADDRESS
MODE
REGISTER
OPMODE
M68000 FAMILY PROGRAMMER’S REFERENCE MANUAL
MOTOROLA
Instruction Format Summary
FDIV
15
14
13
12
1
1
1
1
0
R/M
0
11
10
9
8
7
6
COPROCESSOR
ID
0
0
0
SOURCE
SPECIFIER
5
4
3
2
1
0
EFFECTIVE ADDRESS
MODE
REGISTER
DESTINATION
REGISTER
OPMODE
FMOVE
DATA REGISTER, EFFECTIVE ADDRESS TO REGISTER
15
14
13
12
1
1
1
1
0
R/M
0
14
13
11
10
9
8
7
6
COPROCESSOR
ID
0
0
0
SOURCE
SPECIFIER
5
4
3
2
1
0
EFFECTIVE ADDRESS
MODE
REGISTER
DESTINATION
REGISTER
OPMODE
FMUL
15
1
1
1
0
R/M
0
14
13
12
1
11
9
8
7
6
COPROCESSOR
ID
10
0
0
0
SOURCE
SPECIFIER
5
4
3
2
1
0
EFFECTIVE ADDRESS
MODE
REGISTER
DESTINATION
REGISTER
OPMODE
FNEG
15
1
1
1
0
R/M
0
12
1
11
9
8
7
6
COPROCESSOR
ID
10
0
0
0
SOURCE
SPECIFIER
5
4
3
2
1
0
EFFECTIVE ADDRESS
MODE
REGISTER
DESTINATION
REGISTER
OPMODE
FSQRT
15
14
13
1
1
1
0
R/M
0
14
13
12
1
11
9
8
7
6
COPROCESSOR
ID
10
0
0
0
SOURCE
SPECIFIER
5
4
3
2
1
0
EFFECTIVE ADDRESS
MODE
REGISTER
DESTINATION
REGISTER
OPMODE
FSUB
15
1
1
1
0
R/M
0
MOTOROLA
12
1
11
9
8
7
6
COPROCESSOR
ID
0
0
0
SOURCE
SPECIFIER
10
DESTINATION
REGISTER
5
4
3
2
1
0
EFFECTIVE ADDRESS
MODE
REGISTER
OPMODE
M68000 FAMILY PROGRAMMER’S REFERENCE MANUAL
8-35
Instruction Format Summary
FMOVE
DATA REGISTER, REGISTER TO MEMORY
15
14
13
12
11
10
9
8
7
6
1
1
1
1
0
0
1
0
0
0
0
1
1
14
13
SOURCE
SPECIFIER
5
DESTINATION
REGISTER
4
3
2
1
0
EFFECTIVE ADDRESS
MODE
REGISTER
K-FACTOR
(IF REQUIRED)
FMOVE
SYSTEM CONTROL REGISTER
15
1
1
1
1
0
dr
12
11
1
10
9
8
7
6
COPROCESSOR
ID
0
0
0
0
0
0
REGISTER
SELECT
0
5
4
3
2
1
0
EFFECTIVE ADDRESS
MODE
REGISTER
0
0
5
4
0
0
0
0
FMOVEM
CONTROL REGISTERS
15
14
13
12
1
1
1
1
1
0
dr
11
10
9
8
7
6
COPROCESSOR
ID
0
0
0
0
0
0
REGISTER
SELECT
0
3
2
1
0
EFFECTIVE ADDRESS
MODE
REGISTER
0
0
5
4
0
0
0
0
FMOVEM
DATA REGISTERS
15
14
13
1
1
1
1
1
dr
14
13
12
11
1
9
8
7
6
COPROCESSOR
ID
0
0
0
0
0
0
10
9
8
7
6
MODE
10
3
2
1
0
EFFECTIVE ADDRESS
MODE
REGISTER
REGISTER LIST
cpGEN
15
1
8-36
1
12
11
5
4
3
2
1
0
EFFECTIVE ADDRESS
1
1
0
0
0
MODE
REGISTER
COPROCESSOR ID-DEPENDENT COMMAND WORD
OPTIONAL EFFECTIVE ADDRESS OR COPROCESSOR ID-DEFINED EXTENSION WORDS
COPROCESSOR
ID
M68000 FAMILY PROGRAMMER’S REFERENCE MANUAL
MOTOROLA
Instruction Format Summary
FScc
15
14
13
12
1
1
1
0
0
14
11
10
9
8
7
6
5
4
1
COPROCESSOR
ID
0
0
1
0
0
0
0
0
0
0
0
13
12
11
10
9
8
7
9
8
COPROCESSOR
ID
0
3
2
1
0
EFFECTIVE ADDRESS
MODE
REGISTER
CONDITIONAL PREDICATE
6
5
4
7
6
5
4
1
SIZE
cpScc
15
1
1
0
0
3
2
1
0
EFFECTIVE ADDRESS
1
1
0
0
1
MODE
REGISTER
0
0
0
0
0
0
0
0
COPROCESSOR ID CONDITION
OPTIONAL EFFECTIVE ADDRESS OR COPROCESSOR ID-DEFINED EXTENSION WORDS
COPROCESSOR
ID
FBcc
15
14
13
12
1
1
1
1
11
10
3
2
1
0
CONDITIONAL PREDICATE
16-BIT DISPLACEMENT OR MOST SIGNIFICANT WORD OF 32-BIT DISPLACEMENT
LEAST SIGNIFICANT WORD OF 32-BIT DISPLACEMENT (IF NEEDED)
cpBcc
15
14
13
12
1
1
1
1
13
12
11
10
9
8
7
6
5
4
3
2
1
COPROCESSOR
0
1
SIZE
COPROCESSOR ID CONDITION
ID
OPTIONAL COPROCESSOR ID-DEFINED EXTENSION WORDS
WORD OR
LONG-WORD DISPLACEMENT
0
cpSAVE
15
1
14
1
1
1
15
14
13
12
1
1
1
1
11
9
8
7
6
COPROCESSOR
ID
10
1
0
0
9
8
7
6
COPROCESSOR
ID
1
0
0
5
4
3
2
1
0
EFFECTIVE ADDRESS
MODE
REGISTER
FSAVE
MOTOROLA
11
10
5
4
3
2
1
0
EFFECTIVE ADDRESS
MODE
REGISTER
M68000 FAMILY PROGRAMMER’S REFERENCE MANUAL
8-37
Instruction Format Summary
cpRESTORE
15
14
13
12
1
1
1
1
13
12
11
10
9
8
7
6
COPROCESSOR
ID
1
0
1
9
8
7
6
COPROCESSOR
ID
1
0
1
5
4
3
2
1
0
EFFECTIVE ADDRESS
MODE
REGISTER
FRESTORE
15
1
14
1
1
1
15
14
13
12
1
1
1
1
0
0
0
0
11
10
5
4
3
2
1
0
EFFECTIVE ADDRESS
MODE
REGISTER
FDBcc
11
10
9
8
7
6
COPROCESSOR
0
0
1
ID
0
0
0
0
0
0
16-BIT DISPLACEMENT
5
0
4
3
2
1
0
COUNT
0
1
REGISTER
CONDITIONAL PREDICATE
cpDBcc
15
14
13
12
1
1
1
1
0
0
0
0
13
12
11
10
9
8
7
6
5
4
3
2
1
0
COPROCESSOR
0
0
1
0
0
1
REGISTER
ID
0
0
0
0
0
0
COPROCESSOR ID CONDITION
OPTIONAL COPROCESSOR ID-DEFINED EXTENSION WORDS
16-BIT DISPLACEMENT
FTRAPcc
15
14
1
1
0
0
8-38
11
10
9
8
7
6
5
4
3
2
1
COPROCESSOR
1
1
0
0
1
1
1
1
MODE
ID
0
0
0
0
0
0
0
0
CONDITIONAL PREDICATE
16-BIT OPERAND OR MOST SIGNIFICANT WORD OF 32-BIT OPERAND (IF NEEDED)
LEAST SIGNIFICANT WORD OR 32-BIT OPERAND (IF NEEDED)
M68000 FAMILY PROGRAMMER’S REFERENCE MANUAL
0
MOTOROLA
Instruction Format Summary
cpTRAPcc
15
14
13
12
1
1
1
1
0
0
0
0
15
14
13
12
1
1
1
1
0
0
0
0
11
10
9
8
7
6
5
4
3
2
1
COPROCESSOR
0
0
1
1
1
1
OPMODE
ID
0
0
0
0
0
0
COPROCESSOR ID CONDITION
OPTIONAL COPROCESSOR ID-DEFINED EXTENSION WORDS
OPTIONAL WORD
OR LONG-WORD OPERAND
0
FNOP
MOTOROLA
11
10
9
COPROCESSOR
ID
0
0
0
8
7
6
5
4
3
2
1
0
0
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
M68000 FAMILY PROGRAMMER’S REFERENCE MANUAL
8-39
Instruction Format Summary
8-40
M68000 FAMILY PROGRAMMER’S REFERENCE MANUAL
MOTOROLA
APPENDIX A
PROCESSOR INSTRUCTION SUMMARY
This appendix provides a quick reference of the M68000 family instructions. The organization of this section is by processors and their addressing modes. All references to the
MC68000, MC68020, and MC68030 include references to the corresponding embedded
controllers, MC68EC000, MC68EC020, and MC68EC030. All references to the MC68040
include the MC68LC040 and MC68EC040. This referencing applies throughout this section
unless otherwise specified. Table A-1 lists the M68000 family instructions by mnemonic and
indicates which processors they apply to.
Table A-1. M68000 Family Instruction Set And
Processor Cross-Reference
Mnemonic
68881/
68882
68000
68008
68010
68020
68030
68040
ABCD
ADD
ADDA
ADDI
ADDQ
ADDX
AND
ANDI
ANDI to CCR
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
ANDI to SR1
ASL, ASR
Bcc
BCHG
BCLR
BFCHG
BFCLR
BFEXTS
BFEXTU
BFFFO
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
MOTOROLA
MC68000 FAMILY PROGRAMMER’S REFERENCE MANUAL
68851
CPU32
A-1
Processor Instruction Summary
Table A-1. M68000 Family Instruction Set And
Processor Cross-Reference (Continued)
Mnemonic
BFINS
BFSET
BFTST
BGND
BKPT
BRA
BSET
BSR
BTST
CALLM
CAS, CAS2
CHK
CHK2
CINV1
CLR
CMP
CMPA
CMPI
CMPM
CMP2
cpBcc
cpDBcc
cpGEN
68000
68008
68010
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
68030
68040
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
cpSAVE1
cpScc
cpTRAPcc
X
X
X
X
X
X
A-2
68851
CPU32
X
cpRESTORE1
CPUSH1
DBcc
DIVS
DIVSL
DIVU
DIVUL
68881/
68882
68020
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
MC68000 FAMILY PROGRAMMER’S REFERENCE MANUAL
X
X
X
X
X
MOTOROLA
Processor Instruction Summary
Table A-1. M68000 Family Instruction Set And
Processor Cross-Reference (Continued)
Mnemonic
68881/
68882
68000
68008
68010
68020
68030
68040
EOR
EORI
EORI to CCR
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
EORI to SR1
EXG
EXT
EXTB
FABS
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
FSABS,
FDABS
FACOS
FADD
FSADD,
FDADD
FASIN
FATAN
FATANH
FBcc
X2
CPU32
X
X2
2,3
X
X2
X
X2
2,3
X
X
X
X2
X
2,3
2,3
FCMP
X2
X
FCOS
FCOSH
FDBcc
2,3
2,3
X
X
X2
X
2
X
FDIV
X
FSDIV, FDDIV
X2
FETOX
FETOXM1
FGETEXP
FGETMAN
FINT
FINTRZ
FLOG10
FLOG2
FLOGN
2,3
MOTOROLA
68851
2,3
2,3
2,3
2,3
2,3
2,3
2,3
2,3
X
X
X
X
X
X
X
X
X
MC68000 FAMILY PROGRAMMER’S REFERENCE MANUAL
A-3
Processor Instruction Summary
Table A-1. M68000 Family Instruction Set And
Processor Cross-Reference (Continued)
Mnemonic
FLOGNP1
FMOD
FMOVE
FSMOVE,
68000
68008
68010
68020
68030
68040
68881/
68882
2,3
X
X2
X
2,3
X2
X
FMUL
X2
X
FDMUL
FNEG
FSNEG,
X
X2
X2
X
X2
FDNEG
FNOP
X2
X
FREM
2,3
X
FRESTORE1
X2
X
FSAVE*
X2
X
FSCALE
FScc
2,3
X
X2
X
FSGLDIV
FSGLMUL
FSIN
FSINCOS
FSINH
FSQRT
2,3
2,3
X
X
X
X
X
X2
X
FSSQRT,
FDSQRT
FSUB
FSSUB,
FDSUB
FTAN
FTANH
FTENTOX
FTRAPcc
FTST
A-4
CPU32
X2
FDMOVE
FMOVECR
FMOVEM
FSMUL,
68851
2,3
2,3
2,3
2,3
X2
X2
X
X2
2,3
X
X
X
X2
X
X2
X
2,3
2,3
MC68000 FAMILY PROGRAMMER’S REFERENCE MANUAL
MOTOROLA
Processor Instruction Summary
Table A-1. M68000 Family Instruction Set And
Processor Cross-Reference (Continued)
Mnemonic
FTWOTOX
ILLEGAL
JMP
JSR
LEA
LINK
LPSTOP
LSL,LSR
MOVE
MOVEA
MOVE from CCR
MOVE to CCR
MOVE
from SR1
MOVE
to SR1
MOVE USP1
MOVE16
68000
68008
68020
68030
68040
68881/
68882
2,3
X
68851
CPU32
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
4
4
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
MOVEC1
MOVEM
MOVEP
MOVEQ
X
X
X
X
X
X
MOVES1
MULS
MULU
NBCD
NEG
NEGX
NOP
NOT
OR
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
MOTOROLA
68010
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
MC68000 FAMILY PROGRAMMER’S REFERENCE MANUAL
A-5
Processor Instruction Summary
Table A-1. M68000 Family Instruction Set And
Processor Cross-Reference (Continued)
Mnemonic
68881/
68882
68000
68008
68010
68020
68030
68040
ORI
ORI to CCR
X
X
X
X
X
X
X
X
X
X
X
X
68851
X
X
ORI to SR1
PACK
X
X
X
X
X
X
X
X
X
X
PBcc1
X
PDBcc1
X
PEA
X
X
PFLUSH1
X
X
X
X
X5
X
PFLUSHA1
X5
CPU32
X
X
X
PFLUSHR1
X
PFLUSHS1
X
1
PLOAD
5
X
X
PMOVE1
X
X
1
X
PRESTORE
1
PSAVE
X
PScc1
X
PTEST1
X
X
PTRAPcc1
X
X
PVALID
X
RESET1
X
X
X
X
X
X
X
ROL,ROR
ROXL,
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
ROXR
RTD
RTE1
RTM
RTR
RTS
SBCD
Scc
STOP1
SUB
SUBA
SUBI
SUBQ
SUBX
A-6
MC68000 FAMILY PROGRAMMER’S REFERENCE MANUAL
MOTOROLA
Processor Instruction Summary
Table A-1. M68000 Family Instruction Set And
Processor Cross-Reference (Concluded)
Mnemonic
SWAP
TAS
TBLS,
68000
68008
68010
68020
68030
68040
X
X
X
X
X
X
X
X
X
X
X
X
68881/
68882
CPU32
X
X
X
TBLSN
TBLU,
TBLUN
TRAP
TRAPcc
TRAPV
TST
UNLK
UNPK
68851
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
NOTES:
1. Privileged (Supervisor) Instruction.
2. Not applicable to MC68EC040 and MC68LC040
3. These instructions are software supported on the MC68040.
4. This instruction is not privileged for the MC68000 and MC68008.
5. Not applicable to MC68EC030.
MOTOROLA
MC68000 FAMILY PROGRAMMER’S REFERENCE MANUAL
A-7
Processor Instruction Summary
Table A-2 lists the M68000 family instructions by mnemonics, followed by the descriptive
name.
Table A-2. M68000 Family Instruction Set
Mnemonic
ABCD
ADD
ADDA
ADDI
ADDQ
ADDX
AND
ANDI
ANDI to CCR
ANDI to SR
ASL, ASR
Bcc
BCHG
BCLR
BFCHG
BFCLR
BFEXTS
BFEXTU
BFFFO
BFINS
BFSET
BFTST
BGND
BKPT
BRA
BSET
BSR
BTST
CALLM
CAS
CAS2
CHK
CHK2
CINV
CLR
CMP
CMPA
CMPI
CMPM
CMP2
cpBcc
cpDBcc
cpGEN
cpRESTORE
A-8
Description
Add Decimal with Extend
Add
Address
Add Immediate
Add Quick
Add with Extend
Logical AND
Logical AND Immediate
AND Immediate to Condition Code Register
AND Immediate to Status Register
Arithmetic Shift Left and Right
Branch Conditionally
Test Bit and Change
Test Bit and Clear
Test Bit Field and Change
Test Bit Field and Clear
Signed Bit Field Extract
Unsigned Bit Field Extract
Bit Field Find First One
Bit Field Insert
Test Bit Field and Set
Test Bit Field
Enter Background Mode
Breakpoint
Branch
Test Bit and Set
Branch to Subroutine
Test Bit
CALL Module
Compare and Swap Operands
Compare and Swap Dual Operands
Check Register Against Bound
Check Register Against Upper and Lower Bounds
Invalidate Cache Entries
Clear
Compare
Compare Address
Compare Immediate
Compare Memory to Memory
Compare Register Against Upper and Lower Bounds
Branch on Coprocessor Condition
Test Coprocessor Condition Decrement and Branch
Coprocessor General Function
Coprocessor Restore Function
MC68000 FAMILY PROGRAMMER’S REFERENCE MANUAL
MOTOROLA
Processor Instruction Summary
Table A-2. M68000 Family Instruction Set (Continued)
Mnemonic
cpSAVE
cpScc
cpTRAPcc
CPUSH
DBcc
DIVS, DIVSL
DIVU, DIVUL
EOR
EORI
EORI to CCR
EORI to SR
EXG
EXT, EXTB
FABS
FSFABS, FDFABS
FACOS
FADD
FSADD, FDADD
FASIN
FATAN
FATANH
FBcc
FCMP
FCOS
FCOSH
FDBcc
FDIV
FSDIV, FDDIV
FETOX
FETOXM1
FGETEXP
FGETMAN
FINT
FINTRZ
FLOG10
FLOG2
FLOGN
FLOGNP1
FMOD
FMOVE
FSMOVE,FDMOVE
FMOVECR
FMOVEM
FMUL
FSMUL,FDMUL
FNEG
FSNEG,FDNEG
FNOP
MOTOROLA
Description
Coprocessor Save Function
Set on Coprocessor Condition
Trap on Coprocessor Condition
Push then Invalidate Cache Entries
Test Condition, Decrement and Branch
Signed Divide
Unsigned Divide
Logical Exclusive-OR
Logical Exclusive-OR Immediate
Exclusive-OR Immediate to Condition Code Register
Exclusive-OR Immediate to Status Register
Exchange Registers
Sign Extend
Floating-Point Absolute Value
Floating-Point Absolute Value (Single/Double Precision)
Floating-Point Arc Cosine
Floating-Point Add
Floating-Point Add (Single/Double Precision)
Floating-Point Arc Sine
Floating-Point Arc Tangent
Floating-Point Hyperbolic Arc Tangent
Floating-Point Branch
Floating-Point Compare
Floating-Point Cosine
Floating-Point Hyperbolic Cosine
Floating-Point Decrement and Branch
Floating-Point Divide
Floating-Point Divide (Single/Double Precision)
Floating-Point ex
Floating-Point ex - 1
Floating-Point Get Exponent
Floating-Point Get Mantissa
Floating-Point Integer Part
Floating-Point Integer Part, Round-to-Zero
Floating-Point Log10
Floating-Point Log2
Floating-Point Loge
Floating-Point Loge (x + 1)
Floating-Point Modulo Remainder
Move Floating-Point Register
Move Floating-Point Register (Single/Double Precision)
Move Constant ROM
Move Multiple Floating-Point Registers
Floating-Point Multiply
Floating-Point Multiply (Single/Double Precision)
Floating-Point Negate
Floating-Point Negate (Single/Double Precision)
Floating-Point No Operation
MC68000 FAMILY PROGRAMMER’S REFERENCE MANUAL
A-9
Processor Instruction Summary
Table A-2. M68000 Family Instruction Set (Continued)
Mnemonic
FREM
FRESTORE
FSAVE
FSCALE
FScc
FSGLDIV
FSGLMUL
FSIN
FSINCOS
FSINH
FSQRT
FSSQRT,FDSQRT
FSUB
FSSUB,FDSUB
FTAN
FTANH
FTENTOX
FTRAPcc
FTST
FTWOTOX
ILLEGAL
JMP
JSR
LEA
LINK
LPSTOP
LSL, LSR
MOVE
MOVEA
MOVE from CCR
MOVE from SR
MOVE to CCR
MOVE to SR
MOVE USP
MOVE16
MOVEC
MOVEM
MOVEP
MOVEQ
MOVES
MULS
MULU
NBCD
NEG
NEGX
NOP
NOT
A-10
Description
IEEE Remainder
Restore Floating-Point Internal State
Save Floating-Point Internal State
Floating-Point Scale Exponent
Floating-Point Set According to Condition
Single-Precision Divide
Single-Precision Multiply
Sine
Simultaneous Sine and Cosine
Hyperbolic Sine
Floating-Point Square Root
Floating-Point Square Root (Single/Double Precision)
Floating-Point Subtract
Floating-Point Subtract (Single/Double Precision)
Tangent
Hyperbolic Tangent
Floating-Point 10x
Floating-Point Trap On Condition
Floating-Point Test
Floating-Point 2x
Take Illegal Instruction Trap
Jump
Jump to Subroutine
Load Effective Address
Link and Allocate
Low-Power Stop
Logical Shift Left and Right
Move
Move Address
Move from Condition Code Register
Move from Status Register
Move to Condition Code Register
Move to Status Register
Move User Stack Pointer
16-Byte Block Move
Move Control Register
Move Multiple Registers
Move Peripheral
Move Quick
Move Alternate Address Space
Signed Multiply
Unsigned Multiply
Negate Decimal with Extend
Negate
Negate with Extend
No Operation
Logical Complement
MC68000 FAMILY PROGRAMMER’S REFERENCE MANUAL
MOTOROLA
Processor Instruction Summary
Table A-2. M68000 Family Instruction Set (Concluded)
Mnemonic
OR
ORI
ORI to CCR
ORI to SR
PACK
PBcc
PDBcc
PEA
PFLUSH
PFLUSHA
PFLUSHR
PFLUSHS
PLOAD
PMOVE
PRESTORE
PSAVE
PScc
PTEST
PTRAPcc
PVALID
RESET
ROL, ROR
ROXL, ROXR
RTD
RTE
RTM
RTR
RTS
SBCD
Scc
STOP
SUB
SUBA
SUBI
SUBQ
SUBX
SWAP
TAS
TBLS, TBLSN
TBLU, TBLUN
TRAP
TRAPcc
TRAPV
TST
UNLK
UNPK
MOTOROLA
Description
Logical Inclusive-OR
Logical Inclusive-OR Immediate
Inclusive-OR Immediate to Condition Code Register
Inclusive-OR Immediate to Status Register
Pack BCD
Branch on PMMU Condition
Test, Decrement, and Branch on PMMU Condition
Push Effective Address
Flush Entry(ies) in the ATCs
Flush Entry(ies) in the ATCs
Flush Entry(ies) in the ATCs and RPT Entries
Flush Entry(ies) in the ATCs
Load an Entry into the ATC
Move PMMU Register
PMMU Restore Function
PMMU Save Function
Set on PMMU Condition
Test a Logical Address
Trap on PMMU Condition
Validate a Pointer
Reset External Devices
Rotate Left and Right
Rotate with Extend Left and Right
Return and Deallocate
Return from Exception
Return from Module
Return and Restore
Return from Subroutine
Subtract Decimal with Extend
Set Conditionally
Stop
Subtract
Subtract Address
Subtract Immediate
Subtract Quick
Subtract with Extend
Swap Register Words
Test Operand and Set
Signed Table Lookup with Interpolate
Unsigned Table Lookup with Interpolate
Trap
Trap Conditionally
Trap on Overflow
Test Operand
Unlink
Unpack BCD
MC68000 FAMILY PROGRAMMER’S REFERENCE MANUAL
A-11
Processor Instruction Summary
A.1 MC68000, MC68008, MC68010 PROCESSORS
The following paragraphs provide information on the MC68000, MC68008, and MC68010
instruction set and addressing modes.
A.1.1 M68000, MC68008, and MC68010 Instruction Set
Table A-3 lists the instructions used with the MC68000 and MC68008 processors, and Table
A-4 lists the instructions used with MC68010.
Table A-3. MC68000 and MC68008 Instruction Set
Mnemonic
ABCD
ADD
ADDA
ADDI
ADDQ
ADDX
AND
ANDI
ANDI to CCR
ANDI to SR
ASL, ASR
Bcc
BCHG
BCLR
BRA
BSET
BSR
BTST
CHK
CLR
CMP
CMPA
CMPI
CMPM
DBcc
DIVS
DIVU
EOR
EORI
EORI to CCR
EORI to SR
EXG
EXT
ILLEGAL
JMP
JSR
A-12
Description
Add Decimal with Extend
Add
Add Address
Add Immediate
Add Quick
Add with Extend
Logical AND
Logical AND Immediate
AND Immediate to Condition Code Register
AND Immediate to Status Register
Arithmetic Shift Left and Right
Branch Conditionally
Test Bit and Change
Test Bit and Clear
Branch
Test Bit and Set
Branch to Subroutine
Test Bit
Check Register Against Bound
Clear
Compare
Compare Address
Compare Immediate
Compare Memory to Memory
Test Condition, Decrement, and Branch
Signed Divide
Unsigned Divide
Logical Exclusive-OR
Logical Exclusive-OR Immediate
Exclusive-OR Immediate to Condition Code Register
Exclusive-OR Immediate to Status Register
Exchange Registers
Sign Extend
Take Illegal Instruction Trap
Jump
Jump to Subroutine
MC68000 FAMILY PROGRAMMER’S REFERENCE MANUAL
MOTOROLA
Processor Instruction Summary
Table A-3. MC68000 and MC68008 Instruction Set
(Continued)
Mnemonic
LEA
LINK
LSL, LSR
MOVE
MOVEA
MOVE to CCR
MOVE from SR
MOVE to SR
MOVE USP
MOVEM
MOVEP
MOVEQ
MULS
MULU
NBCD
NEG
NEGX
NOP
NOT
OR
ORI
ORI to CCR
ORI to SR
PEA
RESET
ROL, ROR
ROXL, ROXR
RTE
RTR
RTS
SBCD
Scc
STOP
SUB
SUBA
SUBI
SUBQ
SUBX
SWAP
TAS
TRAP
TRAPV
TST
UNLK
MOTOROLA
Description
Load Effective Address
Link and Allocate
Logical Shift Left and Right
Move
Move Address
Move to Condition Code Register
Move from Status Register
Move to Status Register
Move User Stack Pointer
Move Multiple Registers
Move Peripheral
Move Quick
Signed Multiply
Unsigned Multiply
Negate Decimal with Extend
Negate
Negate with Extend
No Operation
Logical Complement
Logical Inclusive-OR
Logical Inclusive-OR Immediate
Inclusive-OR Immediate to Condition Code Register
Inclusive-OR Immediate to Status Register
Push Effective Address
Reset External Devices
Rotate Left and Right
Rotate with Extend Left and Right
Return from Exception
Return and Restore
Return from Subroutine
Subtract Decimal with Extend
Set Conditionally
Stop
Subtract
Subtract Address
Subtract Immediate
Subtract Quick
Subtract with Extend
Swap Register Words
Test Operand and Set
Trap
Trap on Overflow
Test Operand
Unlink
MC68000 FAMILY PROGRAMMER’S REFERENCE MANUAL
A-13
Processor Instruction Summary
Table A-4. MC68010 Instruction Set
Mnemonic
ABCD
ADD
ADDA
ADDI
ADDQ
ADDX
AND
ANDI
ANDI to CCR
ANDI to SR
ASL, ASR
Bcc
BCHG
BCLR
BKPT
BRA
BSET
BSR
BTST
CHK
CLR
CMP
CMPA
CMPI
CMPM
DBcc
DIVS
DIVU
EOR
EORI
EORI to CCR
EORI to SR
EXG
EXT
ILLEGAL
JMP
JSR
A-14
Description
Add Decimal with Extend
Add
Add Address
Add Immediate
Add Quick
Add with Extend
Logical AND
Logical AND Immediate
AND Immediate to Condition Code Register
AND Immediate to Status Register
Arithmetic Shift Left and Right
Branch Conditionally
Test Bit and Change
Test Bit and Clear
Breakpoint
Branch
Test Bit and Set
Branch to Subroutine
Test Bit
Check Register Against Bound
Clear
Compare
Compare Address
Compare Immediate
Compare Memory to Memory
Test Condition, Decrement and Branch
Signed Divide
Unsigned Divide
Logical Exclusive-OR
Logical Exclusive-OR Immediate
Exclusive-OR Immediate to Condition Code Register
Exclusive-OR Immediate to Status Register
Exchange Registers
Sign Extend
Take Illegal Instruction Trap
Jump
Jump to Subroutine
MC68000 FAMILY PROGRAMMER’S REFERENCE MANUAL
MOTOROLA
Processor Instruction Summary
Table A-4. MC68010 Instruction Set (Continued)
Mnemonic
LEA
LINK
LSL, LSR
MOVE
MOVEA
MOVE from CCR
MOVE from SR
MOVE to CCR
MOVE to SR
MOVE USP
MOVEC
MOVEM
MOVEP
MOVEQ
MOVES
MULS
MULU
NBCD
NEG
NEGX
NOP
NOT
OR
ORI
ORI to CCR
ORI to SR
PEA
RESET
ROL, ROR
ROXL, ROXR
RTD
RTE
RTR
RTS
SBCD
Scc
STOP
SUB
SUBA
SUBI
SUBQ
SUBX
SWAP
TAS
TRAP
TRAPV
TST
UNLK
MOTOROLA
Description
Load Effective Address
Link and Allocate
Logical Shift Left and Right
Move
Move Address
Move from Condition Code Register
Move from Status Register
Move to Condition Code Register
Move to Status Register
Move User Stack Pointer
Move Control Register
Move Multiple Registers
Move Peripheral
Move Quick
Move Address Space
Signed Multiply
Unsigned Multiply
Negate Decimal with Extend
Negate
Negate with Extend
No Operation
Logical Complement
Logical Inclusive-OR
Logical Inclusive-OR Immediate
Inclusive-OR Immediate to Condition Code Register
Inclusive-OR Immediate to Status Register
Push Effective Address
Reset External Devices
Rotate Left and Right
Rotate with Extend Left and Right
Return and Deallocate
Return from Exception
Return and Restore
Return from Subroutine
Subtract Decimal with Extend
Set Conditionally
Stop
Subtract
Subtract Address
Subtract Immediate
Subtract Quick
Subtract with Extend
Swap Register Words
Test Operand and Set
Trap
Trap on Overflow
Test Operand
Unlink
MC68000 FAMILY PROGRAMMER’S REFERENCE MANUAL
A-15
Processor Instruction Summary
A.1.2 MC68000, MC68008, and MC68010 Addressing Modes
The MC68000, MC68008, and MC68010 support 14 addressing modes as shown in Table
A-5.
Table A-5. MC68000, MC68008, and MC68010
Data Addressing Modes
Mode
Register Direct Addressing
Data Register Direct
Address Register Direct
Absolute Data Addressing
Absolute Short
Absolute Long
Program Counter Relative Addressing
Relative with Offset
Relative with Index and Offset
Register Indirect Addressing
Register Indirect
Postincrement Register Indirect
Predecrement Register Indirect
Register Indirect with Offset
Indexed Register Indirect with Offset
Immediate Data Addressing
Immediate
Quick Immediate
Implied Addressing
Implied Register
Generation
<ea> = Dn
<ea> = An
<ea> = (Next Word)
<ea> = (Next Two Words)
<ea> = (PC) + d16
<ea> = (PC) + d8
<ea> = (An)
<ea> = (An), An ¯ An + N
An ¯ An–N, <ea> = (An)
<ea> = (An) + d16
<ea> = (An) + (Xn) + d8
DATA = Next Word(s)
Inherent Data
<ea> = SR, USP, SSP, PC, VBR,
SFC, DFC
N = 1 for byte, 2 for word, and 4 for long word. If An is the stack pointer and
the operand size is byte, N = 2 to keep the stack pointer on a word
boundary.
A-16
MC68000 FAMILY PROGRAMMER’S REFERENCE MANUAL
MOTOROLA
Processor Instruction Summary
A.2 MC68020 PROCESSORS
The following paragraphs provide information on the MC68020 instruction set and addressing modes.
A.2.1 MC68020 Instruction Set
Table A-6 lists the instructions used with the MC68020 processors.
Table A-6. MC68020 Instruction Set Summary
Mnemonic
ABCD
ADD
ADDA
ADDI
ADDQ
ADDX
AND
ANDI
ANDI to CCR
ANDI to SR
ASL, ASR
Bcc
BCHG
BCLR
BFCHG
BFCLR
BFEXTS
BFEXTU
BFFFO
BFINS
BFSET
BFTST
BKPT
BRA
BSET
BSR
BTST
CALLM
CAS
CAS2
CHK
CHK2
CLR
CMP
CMP2
CMPA
CMPI
MOTOROLA
Description
Add Decimal with Extend
Add
Add Address
Add Immediate
Add Quick
Add with Extend
Logical AND
Logical AND Immediate
AND Immediate to Condition Code Register
AND Immediate to Status Register
Arithmetic Shift Left and Right
Branch Conditionally
Test Bit and Change
Test Bit and Clear
Test Bit Field and Change
Test Bit Field and Clear
Signed Bit Field Extract
Unsigned Bit Field Extract
Bit Field Find First One
Bit Field Insert
Test Bit Field and Set
Test Bit Field
Breakpoint
Branch
Test Bit and Set
Branch to Subroutine
Test Bit
CALL Module
Compare and Swap Operands
Compare and Swap Dual Operands
Check Register Against Bound
Check Register Against Upper and Lower Bounds
Clear
Compare
Compare Register Against Upper and Lower Bounds
Compare Address
Compare Immediate
MC68000 FAMILY PROGRAMMER’S REFERENCE MANUAL
A-17
Processor Instruction Summary
Table A-6. MC68020 Instruction Set Summary
(Continued)
Mnemonic
CMPM
cpBcc
cpDBcc
cpGEN
cpRESTORE
cpSAVE
cpScc
cpTRACPcc
DBcc
DIVS, DIVSL
DIVU, DIVUL
EOR
EORI
EORI to CCR
EORI to SR
EXG
EXT, EXTB
ILLEGAL
JMP
JSR
LEA
LINK
LSL, LSR
MOVE
MOVEA
MOVE from CCR
MOVE from SR
MOVE to CCR
MOVE to SR
MOVE USP
MOVEC
MOVEM
MOVEP
MOVEQ
MOVES
MULS
MULU
NBCD
NEG
NEGX
NOP
NOT
A-18
Description
Compare Memory to Memory
Branch to Coprocessor Condition
Test Coprocessor Condition, Decrement and Branch
Coprocessor General Function
Coprocessor Restore Function
Coprocessor Save Function
Set on Coprocessor Condition
Trap on Coprocessor Condition
Test Condition, Decrement, and Branch
Signed Divide
Unsigned Divide
Logical Exclusive-OR
Logical Exclusive-OR Immediate
Exclusive-OR Immediate to Condition Code Register
Exclusive-OR Immediate to Status Register
Exchange Registers
Sign Extend
Take Illegal Instruction Trap
Jump
Jump to Subroutine
Load Effective Address
Link and Allocate
Logical Shift Left and Right
Move
Move Address
Move from Condition Code Register
Move from Status Register
Move to Condition Code Register
Move to Status Register
Move User Stack Pointer
Move Control Register
Move Multiple Registers
Move Peripheral
Move Quick
Move Alternate Address Space
Signed Multiply
Unsigned Multiply
Negate Decimal with Extend
Negate
Negate with Extend
No Operation
Logical Complement
MC68000 FAMILY PROGRAMMER’S REFERENCE MANUAL
MOTOROLA
Processor Instruction Summary
Table A-6. MC68020 Instruction Set Summary
(Concluded)
Mnemonic
OR
ORI
ORI to CCR
ORI to SR
PACK
PEA
RESET
ROL, ROR
ROXL, ROXR
RTD
RTE
RTM
RTR
RTS
SBCD
Scc
STOP
SUB
SUBA
SUBI
SUBQ
SUBX
SWAP
TAS
TRAP
TRAPcc
TRAPV
TST
UNLK
UNPK
MOTOROLA
Description
Logical Inclusive-OR
Logical Inclusive-OR Immediate
Inclusive-OR Immediate to Condition Code Register
Inclusive-OR Immediate to Status Register
Pack BCD
Push Effective Address
Reset External Devices
Rotate Left and Right
Rotate with Extend Left and Right
Return and Deallocate
Return from Exception
Return from Module
Return and Restore
Return from Subroutine
Subtract Decimal with Extend
Set Conditionally
Stop
Subtract
Subtract Address
Subtract Immediate
Subtract Quick
Subtract with Extend
Swap Register Words
Test Operand and Set
Trap
Trap Conditionally
Trap on Overflow
Test Operand
Unlink
Unpack BCD
MC68000 FAMILY PROGRAMMER’S REFERENCE MANUAL
A-19
Processor Instruction Summary
A.2.2 MC68020 Addressing Modes
The MC68020 supports 18 addressing modes as shown in Table A-7.
Table A-7. MC68020 Data Addressing Modes
Addressing Modes
Register Direct
Address Register Direct
Address Register Direct
Register Indirect
Address Register Indirect
Address Register Indirect with Postincrement
Address Register Indirect with Predecrement
Address Register Indirect with Displacement
Dn
An
(An)
(An)+
–(An)
(d16,An)
Register Indirect with Index
Address Register Indirect with Index (8-Bit Displacement)
Address Register Indirect with Index (Base Displacement)
(d8,An,Xn)
(bd,An,Xn)
Memory Indirect
Memory Indirect Postindexed
Memory Indirect Preindexed
Program Counter Indirect with Displacement
([bd,An],Xn,od)
([bd,An,Xn],od)
(d16,PC)
Program Counter Indirect with Index
PC Indirect with Index (8-Bit Displacement)
PC Indirect with Index (Base Displacement)
(d8,PC,Xn)
(bd,PC,Xn)
Program Counter Memory Indirect
PC Memory Indirect Postindexed
PC Memory Indirect Preindexed
Absolute
Absolute Short
Absolute Long
Immediate
A-20
Syntax
([bd,PC],Xn,od)
([bd,PC,Xn],od)
(xxx).W
(xxx).L
#<data>
MC68000 FAMILY PROGRAMMER’S REFERENCE MANUAL
MOTOROLA
Processor Instruction Summary
A.3 MC68030 PROCESSORS
The following paragraphs provide information on the MC68030 instruction set and addressing modes.
A.3.1 MC68030 Instruction Set
Table A-8 lists the instructions used with the MC68030 processors.
Table A-8. MC68030 Instruction Set Summary
Mnemonic
ABCD
ADD
ADDA
ADDI
ADDQ
ADDX
AND
ANDI
ANDI to CCR
ANDI to SR
ASL, ASR
Bcc
BCHG
BCLR
BFCHG
BFCLR
BFEXTS
BFEXTU
BFFFO
BFINS
BFSET
BFTST
BKPT
BRA
BSET
BSR
BTST
CAS
CAS2
CHK
CHK2
CLR
CMP
CMPA
CMPI
CMPM
MOTOROLA
Description
Add Decimal with Extend
Add
Add Address
Add Immediate
Add Quick
Add with Extend
Logical AND
Logical AND Immediate
AND Immediate to Condition Code Register
AND Immediate to Status Register
Arithmetic Shift Left and Right
Branch Conditionally
Test Bit and Change
Test Bit and Clear
Test Bit Field and Change
Test Bit Field and Clear
Signed Bit Field Extract
Unsigned Bit Field Extract
Bit Field Find First One
Bit Field Insert
Test Bit Field and Set
Test Bit Field
Breakpoint
Branch
Test Bit and Set
Branch to Subroutine
Test Bit
Compare and Swap Operands
Compare and Swap Dual Operands
Check Register Against Bound
Check Register Against Upper and Lower Bounds
Clear
Compare
Compare Address
Compare Immediate
Compare Memory to Memory
MC68000 FAMILY PROGRAMMER’S REFERENCE MANUAL
A-21
Processor Instruction Summary
Table A-8. MC68030 Instruction Set Summary
(Continued)
Mnemonic
CMP2
cpBcc
cpDBcc
cpGEN
cpRESTORE
cpSAVE
cpScc
cpTRAPcc
DBcc
DIVS, DIVSL
DIVU, DIVUL
EOR
EORI
EORI to CCR
EORI to SR
EXG
EXT, EXTB
ILLEGAL
JMP
JSR
LEA
LINK
LSL, LSR
MOVE
MOVEA
MOVE from CCR
MOVE to CCR
MOVE from SR
MOVE to SR
MOVE USP
MOVEC
MOVEM
MOVEP
MOVEQ
MOVES
MULS
MULU
NBCD
NEG
NEGX
NOP
NOT
A-22
Description
Compare Register Against Upper and Lower Bounds
Branch on Coprocessor Condition
Test Coprocessor Condition, Decrement and Branch
Coprocessor General Function
Coprocessor Restore Function
Coprocessor Save Function
Set on Coprocessor Condition
Trap on Coprocessor Condition
Test Condition, Decrement and Branch
Signed Divide
Unsigned Divide
Logical Exclusive-OR
Logical Exclusive-OR Immediate
Exclusive-OR Immediate to Condition Code Register
Exclusive-OR Immediate to Status Register
Exchange Registers
Sign Extend
Take Illegal Instruction Trap
Jump
Jump to Subroutine
Load Effective Address
Link and Allocate
Logical Shift Left and Right
Move
Move Address
Move from Condition Code Register
Move to Condition Code Register
Move from Status Register
Move to Status Register
Move User Stack Pointer
Move Control Register
Move Multiple Registers
Move Peripheral
Move Quick
Move Alternate Address Space
Signed Multiply
Unsigned Multiply
Negate Decimal with Extend
Negate
Negate with Extend
No Operation
Logical Complement
MC68000 FAMILY PROGRAMMER’S REFERENCE MANUAL
MOTOROLA
Processor Instruction Summary
Table A-8. MC68030 Instruction Set Summary
(Concluded)
Mnemonic
NBCD
NEG
NEGX
NOP
NOT
OR
ORI
ORI to CCR
ORI to SR
PACK
PEA
PFLUSH*
PFLUSHA*
PLOAD*
PMOVE
PTEST
RESET
ROL, ROR
ROXL, ROXR
RTD
RTE
RTR
RTS
SBCD
Scc
STOP
SUB
SUBA
SUBI
SUBQ
SUBX
SWAP
TAS
TRAP
TRAPcc
TRAPV
TST
UNLK
UNPK
Description
Negate Decimal with Extend
Negate
Negate with Extend
No Operation
Logical Complement
Logical Inclusive-OR
Logical Inclusive-OR Immediate
Inclusive-OR Immediate to Condition Code Register
Inclusive-OR Immediate to Status Register
Pack BCD
Push Effective Address
Invalidate Entries in the ATC
Invalidate all Entries in the ATC
Load an Entry into the ATC
Move PMMU Register
Get Information about Logical Address
Reset External Devices
Rotate Left and Right
Rotate with Extend Left and Right
Return and Deallocate
Return from Exception
Return and Restore
Return from Subroutine
Subtract Decimal with Extend
Set Conditionally
Stop
Subtract
Subtract Address
Subtract Immediate
Subtract Quick
Subtract with Extend
Swap Register Words
Test Operand and Set
Trap
Trap Conditionally
Trap on Overflow
Test Operand
Unlink
Unpack BCD
*Not applicable to the MC68EC030
MOTOROLA
MC68000 FAMILY PROGRAMMER’S REFERENCE MANUAL
A-23
Processor Instruction Summary
A.3.2 MC68030 Addressing Modes
The MC68030 supports 18 addressing modes as shown in Table A-9.
Table A-9. MC68030 Data Addressing Modes
Addressing Modes
Register Direct
Data Register Direct
Address Register Direct
Register Indirect
Address Register Indirect
Address Register Indirect with Postincrement
Address Register Indirect with Predecrement
Address Register Indirect with Displacement
Dn
An
(An)
(An)+
–(An)
(d16,An)
Register Indirect with Index
Address Register Indirect with Index (8-Bit Displacement)
Address Register Indirect with Index (Base Displacement)
(d8,An,Xn)
(bd,An,Xn)
Memory Indirect
Memory Indirect Postindexed
Memory Indirect Preindexed
Program Counter Indirect with Displacement
([bd,An],Xn,od)
([bd,An,Xn],od)
(d16,PC)
Program Counter Indirect with Index
PC Indirect with Index (8-Bit Displacement)
PC Indirect with Index (Base Displacement)
(d8,PC,Xn)
(bd,PC,Xn)
Program Counter Memory Indirect
PC Memory Indirect Postindexed
PC Memory Indirect Preindexed
Absolute
Absolute Short
Absolute Long
Immediate
A-24
Syntax
([bd,PC],Xn,od)
([bd,PC,Xn],od)
(xxx).W
(xxx).L
#<data>
MC68000 FAMILY PROGRAMMER’S REFERENCE MANUAL
MOTOROLA
Processor Instruction Summary
A.4 MC68040 PROCESSORS
The following paragraphs provide information on the MC68040 instruction set and addressing modes.
A.4.1 MC68040 Instruction Set
Table A-10 lists the instructions used with the MC68040 processor.
Table A-10. MC68040 Instruction Set
Mnemonic
ABCD
ADD
ADDA
ADDI
ADDQ
ADDX
AND
ANDI
ANDI to CCR
ANDI to SR
ASL, ASR
Bcc
BCHG
BCLR
BFCHG
BFCLR
BFEXTS
BFEXTU
BFFFO
BFINS
BFSET
BFTST
BKPT
BRA
BSET
BSR
BTST
CAS
CAS2
CHK
CHK2
CINV
CLR
CMP
CMPA
MOTOROLA
Description
Add Decimal with Extend
Add
Add Address
Add Immediate
Add Quick
Add with Extend
Logical AND
Logical AND Immediate
AND Immediate to Condition Code Register
AND Immediate to Status Register
Arithmetic Shift Left and Right
Branch Conditionally
Test Bit and Change
Test Bit and Clear
Test Bit Field and Change
Test Bit Field and Clear
Signed Bit Field Extract
Unsigned Bit Field Extract
Bit Field Find First One
Bit Field Insert
Test Bit Field and Set
Test Bit Field
Breakpoint
Branch
Test Bit and Set
Branch to Subroutine
Test Bit
Compare and Swap Operands
Compare and Swap Dual Operands
Check Register Against Bound
Check Register Against Upper and Lower Bounds
Invalidate Cache Entries
Clear
Compare
Compare Address
MC68000 FAMILY PROGRAMMER’S REFERENCE MANUAL
A-25
Processor Instruction Summary
Table A-10. MC68040 Instruction Set (Continued)
Mnemonic
Description
CMPI
CMPM
CMP2
CPUSH
DBcc
DIVS, DIVSL
DIVU, DIVUL
EOR
EORI
EORI to CCR
EORI to SR
EXG
EXT, EXTB
Compare Immediate
Compare Memory to Memory
Compare Register Against Upper and Lower Bounds
Push then Invalidate Cache Entries
Test Condition, Decrement and Branch
Signed Divide
Unsigned Divide
Logical Exclusive-OR
Logical Exclusive-OR Immediate
Exclusive-OR Immediate to Condition Code Register
Exclusive-OR Immediate to Status Register
Exchange Registers
Sign Extend
Floating-Point Absolute Value
FABS1
Floating-Point Absolute Value (Single/Double Precision)
FSABS, FDABS1
Floating-Point Arc Cosine
1,2
FACOS
Floating-Point Add
1
FADD
Floating-Point Add (Single/Double Precision)
FSADD, FDADD1
Floating-Point Arc Sine
1,2
FASIN
Floating-Point Arc Tangent
1,2
FATAN
Floating-Point Hyperbolic Arc Tangent
1,2
FATANH
Floating-Point Branch
1
FBcc
Floating-Point Compare
FCMP1
Floating-Point Cosine
1,2
FCOS
Floating-Point Hyperbolic Cosine
1,2
FCOSH
Floating-Point Decrement and Branch
1
FDBcc
Floating-Point Divide
1
FDIV
Floating-Point Divide (Single/Double Precision)
FSDIV, FDDIV1
1,2
FETOX
Floating-Point ex
FETOXM11,2
FGETEXP1,2
Floating-Point ex - 1
Floating-Point Get Exponent
FGETMAN1,2
Floating-Point Get Mantissa
FINT1,2
Floating-Point Integer Part
Floating-Point Integer Part, Round-to-Zero
1,2
FINTRZ
Floating-Point Log10
1,2
FLOG10
1,2
Floating-Point Log2
1,2
FLOGN
Floating-Point Loge
FLOGNP11,2
Floating-Point Loge (x + 1)
FLOG2
Floating-Point Modulo Remainder
1,2
FMOD
Move Floating-Point Register
1
FMOVE
1
FSMOVE, FDMOVE
Move Constant ROM
FMOVEM1
Move Multiple Floating-Point Registers
Floating-Point Multiply
1
FMUL
1
FSMUL, FDMUL
A-26
Move Floating-Point Register (Single/Double Precision)
FMOVECR
1
Floating-Point Multiply (Single/Double Precision)
MC68000 FAMILY PROGRAMMER’S REFERENCE MANUAL
MOTOROLA
Processor Instruction Summary
Table A-10. MC68040 Instruction Set (Continued)
Mnemonic
Description
Floating-Point Negate
FNEG1
1
FSNEG, FDNEG
Floating-Point Negate (Single/Double Precision)
1
Floating-Point No Operation
1,2
IEEE Remainder
FNOP
FREM
Restore Floating-Point Internal State
FRESTORE1
Save Floating-Point Internal State
1
FSAVE
Floating-Point Scale Exponent
1,2
FSCALE
Floating-Point Set According to Condition
1
FScc
FSGLDIV
Single-Precision Divide
FSGLMUL1,2
Single-Precision Multiply
1,2
Sine
1,2
FSIN
Simultaneous Sine and Cosine
1,2
FSINCOS
Hyperbolic Sine
1,2
FSINH
FSQRT
Floating-Point Square Root
FSSQRT, FDSQRT1
Floating-Point Square Root (Single/Double Precision)
1
Floating-Point Subtract
1
FSUB
1
FSSUB, FDSUB
Floating-Point Subtract (Single/Double Precision)
Tangent
1,2
FTAN
FTANH
Hyperbolic Tangent
FTENTOX1,2
FTRAPcc1,2
Floating-Point 10x
Floating-Point Trap On Condition
FTST1
Floating-Point Test
1,2
1,2
FTWOTOX
ILLEGAL
JMP
JSR
LEA
LINK
LSL, LSR
MOVE
MOVEA
MOVE from CCR
MOVE to CCR
MOVE from SR
MOVE to SR
MOVE USP
MOVEC
MOVEM
MOVEP
MOVEQ
MOVES
MOVE16
MULS
MULU
MOTOROLA
Floating-Point 2x
Take Illegal Instruction Trap
Jump
Jump to Subroutine
Load Effective Address
Link and Allocate
Logical Shift Left and Right
Move
Move Address
Move from Condition Code Register
Move to Condition Code Register
Move from Status Register
Move to Status Register
Move User Stack Pointer
Move Control Register
Move Multiple Registers
Move Peripheral
Move Quick
Move Alternate Address Space
16-Byte Block Move
Signed Multiply
Unsigned Multiply
MC68000 FAMILY PROGRAMMER’S REFERENCE MANUAL
A-27
Processor Instruction Summary
Table A-10. MC68040 Instruction Set (Concluded)
Mnemonic
NBCD
NEG
NEGX
NOP
NOT
OR
ORI
ORI to CCR
ORI to SR
PACK
PEA
PFLUSH
PFLUSHA
PTEST
RESET
ROL, ROR
ROXL, ROXR
RTD
RTE
RTR
RTS
SBCD
Scc
STOP
SUB
SUBA
SUBI
SUBQ
SUBX
SWAP
TAS
TRAP
TRAPcc
TRAPV
TST
UNLK
UNPK
Description
Negate Decimal with Extend
Negate
Negate with Extend
No Operation
Logical Complement
Logical Inclusive-OR
Logical Inclusive-OR Immediate
Inclusive-OR Immediate to Condition Code Register
Inclusive-OR Immediate to Status Register
Pack BCD
Push Effective Address
Flush Entry(ies) in the ATCs
Flush all Entry(ies) in the ATCs
Test a Logical Address
Reset External Devices
Rotate Left and Right
Rotate with Extend Left and Right
Return and Deallocate
Return from Exception
Return and Restore
Return from Subroutine
Subtract Decimal with Extend
Set Conditionally
Stop
Subtract
Subtract Address
Subtract Immediate
Subtract Quick
Subtract with Extend
Swap Register Words
Test Operand and Set
Trap
Trap Conditionally
Trap on Overflow
Test Operand
Unlink
Unpack BCD
NOTES:
1. Not applicable to the MC68EC040 and MC68LC040.
2. These instructions are software supported.
A-28
MC68000 FAMILY PROGRAMMER’S REFERENCE MANUAL
MOTOROLA
Processor Instruction Summary
A.4.2 MC68040 Addressing Modes
The MC68040 supports 18 addressing modes as shown in Table A-11.
Table A-11. MC68040 Data Addressing Modes
Addressing Modes
Register Direct
Data Register Direct
Address Register Direct
Register Indirect
Address Register Indirect
Address Register Indirect with Postincrement
Address Register Indirect with Predecrement
Address Register Indirect with Displacement
Register Indirect with Index
Address Register Indirect with Index (8-Bit Displacement)
Address Register Indirect with Index (Base Displacement)
Memory Indirect
Memory Indirect Postindexed
Memory Indirect Preindexed
Program Counter Indirect with Displacement
Program Counter Indirect with Index
PC Indirect with Index (8-Bit Displacement)
PC Indirect with Index (Base Displacement)
Program Counter Memory Indirect
PC Memory Indirect Postindexed
PC Memory Indirect Preindexed
Absolute
Absolute Short
Absolute Long
Immediate
MOTOROLA
Syntax
Dn
An
(An)
(An) +
–(An)
(d16,An)
(d8,An,Xn)
(bd,An,Xn)
([bd,An],Xn,od)
([bd,An,Xn],od)
(d16,PC)
(d8,PC,Xn)
(bd,PC,Xn)
([bd,PC],Xn,od)
([bd,PC,Xn],od)
xxx.W
xxx.L
# < data >
MC68000 FAMILY PROGRAMMER’S REFERENCE MANUAL
A-29
Processor Instruction Summary
A.5 MC68881/MC68882 COPROCESSORS
The following paragraphs provide information on the MC68881/MC68882 instruction set and
addressing modes.
A.5.1 MC68881/MC68882 Instruction Set
Table A-12 lists the instructions used with the MC68881/MC68882 coprocessors.
Table A-12. MC68881/MC68882 Instruction Set
Mnemonic
FABS
FACOS
FADD
FASIN
FATAN
FATANH
FBcc
FCMP
FCOS
FCOSH
FDBcc
FDIV
FETOX
FETOXM1
FGETEXP
FGETMAN
FINT
FINTRZ
FLOG10
FLOG2
FLOGN
FLOGNP1
FMOD
FMOVE
FMOVECR
FMOVEM
FMUL
FNEG
FNOP
FREM
FRESTORE
FSAVE
FSCALE
FScc
FSGLDIV
FSGLMUL
FSIN
FSINCOS
FSINH
A-30
Description
Floating-Point Absolute Value
Floating-Point Arc Cosine
Floating-Point Add
Floating-Point Arc Sine
Floating-Point Arc Tangent
Floating-Point Hyperbolic Arc Tangent
Floating-Point Branch
Floating-Point Compare
Floating-Point Cosine
Floating-Point Hyperbolic Cosine
Floating-Point Decrement and Branch
Floating-Point Divide
Floating-Point ex
Floating-Point ex - 1
Floating-Point Get Exponent
Floating-Point Get Mantissa
Floating-Point Integer Part
Floating-Point Integer Part, Round-to-Zero
Floating-Point Log10
Floating-Point Log2
Floating-Point Loge
Floating-Point Loge (x + 1)
Floating-Point Modulo Remainder
Move Floating-Point Register
Move Constant ROM
Move Multiple Floating-Point Registers
Floating-Point Multiply
Floating-Point Negate
Floating-Point No Operation
IEEE Remainder
Restore Floating-Point Internal State
Save Floating-Point Internal State
Floating-Point Scale Exponent
Floating-Point Set According to Condition
Single-Precision Divide
Single-Precision Multiply
Sine
Simultaneous Sine and Cosine
Hyperbolic Sine
MC68000 FAMILY PROGRAMMER’S REFERENCE MANUAL
MOTOROLA
Processor Instruction Summary
Table A-12. MC68881/MC68882 Instruction Set
Mnemonic
FSQRT
FSUB
FTAN
FTANH
FTENTOX
FTRAPcc
FTST
FTWOTOX
Description
Floating-Point Square Root
Floating-Point Subtract
Tangent
Hyperbolic Tangent
Floating-Point 10x
Floating-Point Trap On Condition
Floating-Point Test
Floating-Point 2x
A.5.2 MC68881/MC68882 Addressing Modes
The MC68881/MC68882 does not perform address calculations. When the floating-point
coprocessor instructs the processor to transfer an operand via the coprocessor interface,
the processor performs the addressing mode calculation requested in the instruction.
A.6 MC68851 COPROCESSORS
The following paragraphs provide information on the MC68851 instruction set and addressing modes.
A.6.1 MC68851 Instruction Set
Table A-13 lists the instructions used with the MC68851 coprocessor.
Table A-13. MC68851 Instruction Set
Mnemonic
PBcc
PDBcc
PFLUSH
PFLUSHA
PFLUSHR
PFLUSHS
PLOAD
PMOVE
PRESTORE
PSAVE
PScc
PTEST
PTRAPcc
PVALID
Description
Branch on PMMU Condition
Test, Decrement, and Branch on PMMU Condition
Flush Entry(ies) in the ATCs
Flush Entry(ies) in the ATCs
Flush Entry(ies) in the ATCs and RPT Entries
Flush Entry(ies) in the ATCs
Load an Entry into the ATC
Move PMMU Register
PMMU Restore Function
PMMU Save Function
Set on PMMU Condition
Test a Logical Address
Trap on PMMU Condition
Validate a Pointer
A.6.2 MC68851 Addressing Modes
The MC68851 supports the same addressing modes as the MC68020 (see Table A-7).
MOTOROLA
MC68000 FAMILY PROGRAMMER’S REFERENCE MANUAL
A-31
Processor Instruction Summary
A-32
MC68000 FAMILY PROGRAMMER’S REFERENCE MANUAL
MOTOROLA
APPENDIX B
EXCEPTION PROCESSING REFERENCE
This appendix provides a quick reference for system programmers who are already familiar
with the stack frames. For more detail, please refer to the appropriate userOs manual.
B.1 EXCEPTION VECTOR ASSIGNMENTS FOR THE M68000 FAMILY
Table B-1 lists all vector assignments up to and including the MC68040 and its derivatives.
Many of these vector assignments are processor specific. For instance, vector 13, the
coprocessor protocol violation vector, only applies to the MC68020, MC68EC020,
MC68030, and MC68EC030. Refer to the appropriate user’s manual to determine which
exception type is applicable to a specific processor.
MOTOROLA
MC68000 FAMILY PROGRAMMER’S REFERENCE MANUAL
B-1
Exception Processing Reference
Table B-1. Exception Vector Assignments for the M68000 Family
B-2
Vector
Number( s)
Vector
Offset (Hex)
0
000
Reset Initial Interrupt Stack Pointer
1
004
Reset Initial Program Counter
2
008
Access Fault
3
00C
Address Error
4
010
Illegal Instruction
5
014
Integer Divide by Zero
6
018
CHK, CHK2 Instruction
7
01C
FTRAPcc, TRAPcc, TRAPV Instructions
8
020
Privilege Violation
9
024
Trace
10
028
Line 1010 Emulator (Unimplemented A- Line Opcode)
11
02C
Line 1111 Emulator (Unimplemented F-Line Opcode)
12
030
(Unassigned, Reserved)
13
034
Coprocessor Protocol Violation
14
038
Format Error
15
03C
Uninitialized Interrupt
16–23
040–05C
24
060
Spurious Interrupt
25
064
Level 1 Interrupt Autovector
26
068
Level 2 Interrupt Autovector
27
06C
Level 3 Interrupt Autovector
28
070
Level 4 Interrupt Autovector
29
074
Level 5 Interrupt Autovector
30
078
Level 6 Interrupt Autovector
Level 7 Interrupt Autovector
Assignment
(Unassigned, Reserved)
31
07C
32–47
080–0BC
48
0C0
FP Branch or Set on Unordered Condition
49
0C4
FP Inexact Result
TRAP #0 D 15 Instruction Vectors
50
0C8
FP Divide by Zero
51
0CC
FP Underflow
52
0D0
FP Operand Error
53
0D4
FP Overflow
54
0D8
FP Signaling NAN
55
0DC
FP Unimplemented Data Type (Defined for MC68040)
56
0E0
MMU Configuration Error
57
0E4
MMU Illegal Operation Error
MMU Access Level Violation Error
58
0E8
59–63
0ECD0FC
(Unassigned, Reserved)
64–255
100D3FC
User Defined Vectors (192)
MC68000 FAMILY PROGRAMMER’S REFERENCE MANUAL
MOTOROLA
Exception Processing Reference
B.2 EXCEPTION STACK FRAMES
Figures B-1 through B-15 illustrate all exception stack frames for the M68000 family..
ODD BYTE
EVEN BYTE
7
15
0
0
0 7
SP
STATUS REGISTER
PROGRAM COUNTER HIGH
PROGRAM COUNTER LOW
HIGHER
ADDRESS
Figure B-1. MC68000 Group 1 and 2 Exception Stack Frame
LOWER
ADDRESS
5
15
4
3
R/W I/N
ACCESS ADDRESS
2
0
FUNCTION CODE
HIGH
LOW
INSTRUCTION REGISTER
STATUS REGISTER
PROGRAM COUNTER
HIGH
LOW
R/W (READ/WRITE): WRITE = 0, READ = 1. I/N
(INSTRUCTION/NOT): INSTRUCTION = 0, NOT = 1.
Figure B-2. MC68000 Bus or Address Error Exception Stack Frame
15
0
STATUS REGISTER
SP
+$02
PROGRAM COUNTER
+$06
0000
VECTOR OFFSET
Figure B-3. Four-Word Stack Frame, Format $0
15
0
STATUS REGISTER
SP
+$02
+$06
PROGRAM COUNTER
0001
VECTOR OFFSET
Figure B-4. Throwaway Four-Word Stack Frame, Format $1
MOTOROLA
MC68000 FAMILY PROGRAMMER’S REFERENCE MANUAL
B-3
Exception Processing Reference
15
0
STATUS REGISTER
SP
+$02
PROGRAM COUNTER
+$06
+$08
0010
VECTOR OFFSET
ADDRESS
Figure B-5. Six-Word Stack Frame, Format $2
15
0
SP
+$02
+$06
+$08
STATUS REGISTER
PROGRAM COUNTER
0010
VECTOR OFFSET
EFFECTIVE ADDRESS
Figure B-6. MC68040 Floating-Point Post-Instruction Stack Frame, Format $3
B-4
MC68000 FAMILY PROGRAMMER’S REFERENCE MANUAL
MOTOROLA
Exception Processing Reference
15
0
SP
+$02
STATUS REGISTER
PROGRAM COUNTER
+$06
+$08
0100
VECTOR OFFSET
EFFECTIVE ADDRESS (EA)
PC OF FAULTED
INSTRUCTION
+$0C
Figure B-7. MC68EC040 and MC68LC040 Floating-Point Unimplemented Stack
Frame, Format $4
15
0
SP
+$02
+$06
+$08
+$0A
+$0C
+$0E
+$10
+$12
+$14
+$18
+$1C
+$20
+$24
+$28
+$2C
+$30
+$34
+$38
STATUS REGISTER
PROGRAM COUNTER
0111
VECTOR OFFSET
EFFECTIVE ADDRESS (EA)
$00
$00
$00
SPECIAL STATUS WORD
WRITEBACK 3 STATUS (WB3S)
WRITEBACK 2 STATUS (WB2S)
WRITEBACK 1 STATUS (WB1S)
FAULT ADDRESS (FA)
WRITEBACK 3 ADDRESS (WB3A)
WRITEBACK 3 DATA (WB3D)
WRITEBACK 2 ADDRESS (WB2A)
WRITEBACK 2 DATA (WB2D)
WRITEBACK 1 ADDRESS (WB1A)
WRITEBACK 1 DATA/PUSH DATA LW0 (WB1D/PD0)
PUSH DATA LW 1 (PD1)
PUSH DATA LW 2 (PD2)
PUSH DATA LW 3 (PD3)
Figure B-8. MC68040 Access Error Stack Frame, Format $7
MOTOROLA
MC68000 FAMILY PROGRAMMER’S REFERENCE MANUAL
B-5
Exception Processing Reference
15
SP
+$02
+$06
+$08
+$0C
+$10
+$14
+$16
+$18
$1A
+$50
0
STATUS REGISTER
PROGRAM COUNTER HIGH
PROGRAM COUNTER LOW
1 0 0 0
VECTOR OFFSET
SPECIAL STATUS WORD
FAULT ADDRESS HIGH
FAULT ADDRESS LOW
UNUSED, RESERVED
DATA OUTPUT BUFFER
UNUSED, RESERVED
DATA INPUT BUFFER
UNUSED, RESERVED
INSTRUCTION OUTPUT BUFFER
|VERSION|
|NUMBER|
INTERNAL INFORMATION, 16 WORDS
NOTE: The stack pointer decrements by 29 words,
although only 26 words of information actually
write to memory. Motorola reserves the three
additional words for future use.
Figure B-9. MC68010 Bus and Address Error Stack Frame, Format $8
15
0
SP
STATUS REGISTER
+$02
+$06
+$08
PROGRAM COUNTER
1 0 0 1
VECTOR OFFSET
INSTRUCTION ADDRESS
+$0C
INTERNAL REGISTERS
4 WORDS
+$12
Figure B-10. MC68020 Bus and MC68030 Coprocessor Mid-Instruction Stack Frame,
Format $9
B-6
MC68000 FAMILY PROGRAMMER’S REFERENCE MANUAL
MOTOROLA
Exception Processing Reference
15
0
SP
STATUS REGISTER
+$02
+$06
+$08
+$0A
+$0C
+$0E
+$10
+$12
+$14
+$16
+$18
+$1A
+$1C
+$1E
PROGRAM COUNTER
1 0 1 0
VECTOR OFFSET
INTERNAL REGISTER
SPECIAL STATUS REGISTER
INSTRUCTION PIPE STAGE C
INSTRUCTION PIPE STATE B
DATA CYCLE FAULT ADDRESS
INTERNAL REGISTER
INTERNAL REGISTER
DATA OUTPUT BUFFER
INTERNAL REGISTER
INTERNAL REGISTER
Figure B-11. MC68020 and MC68030 Short Bus Cycle Stack Frame, Format $A
MOTOROLA
MC68000 FAMILY PROGRAMMER’S REFERENCE MANUAL
B-7
Exception Processing Reference
15
0
SP
STATUS REGISTER
+$02
+$06
+$08
+$0A
+$0C
+$0E
+$10
+$12
+$14
+$16
+$18
+$1A
+$1C
+$1E
PROGRAM COUNTER
1 0 1 1
VECTOR OFFSET
INTERNAL REGISTER
SPECIAL STATUS REGISTER
INSTRUCTION PIPE STAGE C
INSTRUCTION PIPE STAGE B
DATA CYCLE FAULT ADDRESS
INTERNAL REGISTER
INTERNAL REGISTER
DATA OUTPUT BUFFER
INTERNAL REGISTERS, 4 WORDS
+$22
+$24
STAGE B ADDRESS
+$28
+$2A
+$2C
INTERNAL REGISTERS, 2 WORDS
DATA INPUT BUFFER
+$30
INTERNAL REGISTERS, 3 WORDS
+$36
+$38
VERSION #
INTERNAL INFORMATION
INTERNAL REGISTERS 18 WORDS
+$5A
Figure B-12. MC68020 and MC68030 Long Bus Cycle Stack Frame, Format $B
15
SP
+$02
+$06
+$08
+$0C
+$10
+$14
+$16
0
STATUS REGISTER
RETURN PROGRAM COUNTER HIGH
RETURN PROGRAM COUNTER LOW
1 1 0 0
VECTOR OFFSET
FAULTED ADDRESS HIGH
FAULTED ADDRESS LOW
DBUF HIGH
DBUF LOW
CURRENT INSTRUCTION PROG. COUNTER HIGH
CURRENT INSTRUCTION PROG. COUNTER LOW
INTERNAL TRANSFER COUNT REGISTER
0 0
SPECIAL STATUS WORD
Figure B-13. CPU32 Bus Error for Prefetches and Operands Stack Frame, Format $C
B-8
MC68000 FAMILY PROGRAMMER’S REFERENCE MANUAL
MOTOROLA
Exception Processing Reference
15
SP
+$02
+$06
+$08
+$0C
+$10
+$14
+$16
0
STATUS REGISTER
RETURN PROGRAM COUNTER HIGH
RETURN PROGRAM COUNTER LOW
1 1 0 0
VECTOR OFFSET
FAULTED ADDRESS HIGH
FAULTED ADDRESS LOW
DBUF HIGH
DBUF LOW
CURRENT INSTRUCTION PROG. COUNTER HIGH
CURRENT INSTRUCTION PROG. COUNTER LOW
INTERNAL TRANSFER COUNT REGISTER
0 1
SPECIAL STATUS WORD
Figure B-14. CPU32 Bus Error on MOVEM Operand Stack Frame, Format $C
15
SP
+$02
+$06
+$08
+$0C
+$10
+$14
+$16
0
STATUS REGISTER
RETURN PROGRAM COUNTER HIGH
RETURN PROGRAM COUNTER LOW
1 1 0 0
VECTOR OFFSET
FAULTED ADDRESS HIGH
FAULTED ADDRESS LOW
DBUF HIGH
DBUF LOW
CURRENT INSTRUCTION PROG. COUNTER HIGH
CURRENT INSTRUCTION PROG. COUNTER LOW
INTERNAL TRANSFER COUNT REGISTER
1 0
SPECIAL STATUS WORD
Figure B-15. CPU32 Four- and Six-Word Bus Error Stack Frame, Format $C
MOTOROLA
MC68000 FAMILY PROGRAMMER’S REFERENCE MANUAL
B-9
Exception Processing Reference
B.3 FLOATING-POINT STACK FRAMES
Figures B-16 through B-23 illustrate floating-point stack frames for the MC68881/MC68882
and the MC68040.
31
+$00
23
$00
15
(UNDEFINED)
7
(RESERVED)
0
Figure B-16. MC68881/MC68882 and MC68040 Null Stack Frame
31
23
15
+$18
VERSION NUMBER
COMMAND/CONDITION REGISTER
+$04
+$08
EXCEPTIONAL OPERAND
+$0C
(12 BYTES)
+$10
OPERAND REGISTER
+$14
+$00
+$18
7
(RESERVED)
(RESERVED)
0
BIU FLAGS
Figure B-17. MC68881 Idle Stack Frame
B-10
MC68000 FAMILY PROGRAMMER’S REFERENCE MANUAL
MOTOROLA
Exception Processing Reference
+$00
+$04
+$08
+$0C
31
23
VERSION NUMBER
15
+$B4
7
(RESERVED)
0
INTERNAL REGISTERS
(180 BYTES)
+$AC
+$B0
+$B4
Figure B-18. MC68881 Busy Stack Frame
31
23
+$38
VERSION NUMBER
COMMAND/CONDITION REGISTER
+$04
15
+$00
7
(RESERVED)
(RESERVED)
0
+$08
INTERNAL REGISTERS
(32 BYTES)
+$24
+$28
EXCEPTIONAL OPERAND
(12 BYTES)
+$2C
+$30
OPERAND REGISTER
+$34
+$38
BIU FLAGS
Figure B-19. MC68882 Idle Stack Frame
+$00
31
23
VERSION NUMBER
15
+$D4
7
(RESERVED)
0
+$04
+$08
+$0C
+$CC
+$D0
+$D4
INTERNAL REGISTERS
(212 BYTES)
Figure B-20. MC68882 Busy Stack Frame
B-11
MC68000 FAMILY PROGRAMMER’S REFERENCE MANUAL
MOTOROLA
B-12
MC68000 FAMILY PROGRAMMER’S REFERENCE MANUAL
Reserved
E3
WBT
M1
SBIT
T
WBT
E15
15
ETM 31–00
$30
(RESERVED)
Figure B-22. MC68040 Unimplimented Instruction Stack Frame
ETM 63–32
$2C
ETE
FPTE
CMDREG1B
WBT
M0
CMDREG3B
$30
16
FPTM 31–00
$28
ETS
E1
WBT
M66
24 23
15
Figure B-21. MC68040 Idle Stack Frame
$00
16
$24
DTAG
STAG
VERSION = $41
VERSION $41
24 23
FPTM 63–32
FPTS
31
31
$20
$1C
$18
$14
$10
$0C
$08
$04
$00
$00
0
0
Exception Processing Reference
MOTOROLA
B-13
Reserved
WBT
M1
MC68000 FAMILY PROGRAMMER’S REFERENCE MANUAL
ETM 31–00
$60
Figure B-23. MC68040 Busy Stack Frame
ETM 63–32
ETE
T
$5C
$58
ETS
FPTE
FPTM 63–32
E3
WBT
E15
FPIARCU
FPTM 31–00
E1
CMDREG1B
SBIT
15
$54
DTAG
WBT
M0
16
$50
$4C
$48
$44
$40
$3C
$38
$34
$30
$2C
$28
$24
FPTS
WBT
M66
CMDREG3B
$60
WBTM 65–34
WBTE 14–00
24 23
WBTM 33–02
STAG
CU_SAVEPC
VERSION = $41
$20
WBTS
31
$1C
$18
$14
$10
$0C
$08
$04
$00
0
Exception Processing Reference
MOTOROLA
Exception Processing Reference
B-14
MC68000 FAMILY PROGRAMMER’S REFERENCE MANUAL
MOTOROLA
APPENDIX C
S-RECORD OUTPUT FORMAT
The S-record format for output modules is for encoding programs or data files in a printable
format for transportation between computer systems. The transportation process can be
visually monitored, and the S-records can be easily edited.
C.1 S-RECORD CONTENT
Visually, S-records are essentially character strings made of several fields that identify the
record type, record length, memory address, code/data, and checksum. Each byte of binary
data encodes as a two- character hexadecimal number: the first character represents the
high- order four bits, and the second character represents the low-order four bits of the byte.
Figure C-1 illustrates the five fields that comprise an S-record. Table C-1 lists the composition of each S- record field.
TYPE
RECORD LENGTH
ADDRESS
CODE/DATA
CHECKSUM
Figure C-1. Five Fields of an S-Record
Table C-1. Field Composition of an S-Record
Field
Type
Record Length
Address
Printable
Characters
2
S-record type—S0, S1, etc.
2
The count of the character pairs in the record, excluding the type
and record length.
4, 6, or 8
The 2-, 3-, or 4-byte address at which the data field is to be loaded
into memory.
0–2n
From 0 to n bytes of executable code, memory loadable data, or
descriptive information. For compatibility with teletypewriters,
some programs may limit the number of bytes to as few as 28 (56
printable characters in the S-record).
2
The least significant byte of the one’s complement of the sum of
the values represented by the pairs of characters making up the
record length, address, and the code/data fields.
Code/Data
Checksum
MOTOROLA
Contents
MC68000 FAMILY PROGRAMMER’S REFERENCE MANUAL
C-1
S-Record Output Format
When downloading S-records, each must be terminated with a CR. Additionally, an S-record
may have an initial field that fits other data such as line numbers generated by some timesharing systems. The record length (byte count) and checksum fields ensure transmission
accuracy.
C.2 S-RECORD TYPES
There are eight types of S-records to accommodate the encoding, transportation, and
decoding functions. The various Motorola record transportation control programs (e.g.
upload, download, etc.), cross assemblers, linkers, and other file creating or debugging programs, only utilize S-records serving the programOs purpose. For more information on support of specific S-records, refer to the userOs manual for that program.
An S-record format module may contain S-records of the following types:
S0 — The header record for each block of S-records. The code/data field may contain any descriptive information identifying the following block of S-records.
Under VERSAdos, the resident linkerOs IDENT command can be used to designate module name, version number, revision number, and description information that will make up the header record. The address field is normally zeros.
S1 — A record containing code/data and the 2-byte address at which the code/data
is to reside.
S2 — A record containing code/data and the 3-byte address at which the code/data
is to reside.
S3 — A record containing code/data and the 4-byte address at which the code/data
is to reside.
S5 — A record containing the number of S1, S2, and S3 records transmitted in a particular block. This count appears in the address field. There is no code/data
field.
S7 — A termination record for a block of S3 records. The address field may optionally
contain the 4-byte address of the instruction to which control is to be passed.
There is no code/data field.
S8 — A termination record for a block of S2 records. The address field may optionally
contain the 3-byte address of the instruction to which control is to be passed.
There is no code/data field.
S9 — A termination record for a block of S1 records. The address field may optionally
contain the 2-byte address of the instruction to which control is to be passed.
Under VERSAdos, the resident linkerOs ENTRY command can be used to
specify this address. If this address is not specified, the first entry point specification encountered in the object module input will be used. There is no code/
data field.
Each block of S-records uses only one termination record. S7 and S8 records are only active
when control is to be passed to a 3- or 4- byte address; otherwise, an S9 is used for termination. Normally, there is only one header record, although it is possible for multiple header
records to occur.
C-2
MC68000 FAMILY PROGRAMMER’S REFERENCE MANUAL
MOTOROLA
S-Record Output Format
C.3 S-RECORD CREATION
Dump utilities, debuggers, a VERSAdos resident linkage editor, or cross assemblers and
linkers produce S-record format programs. On VERSAdos systems, the build load module
(MBLM) utility allows an executable load module to be built from S-records. It has a counterpart utility in BUILDS that allows an S-record file to be created from a load module.
Programs are available for downloading or uploading a file in S- record format from a host
system to an 8- or 16-bit microprocessor- based system. A typical S-record-format module
is printed or displayed as follows:
S00600004844521B
S1130000285F245F2212226A000424290008237C2A
S11300100002000800082629001853812341001813
S113002041E900084E42234300182342000824A952
S107003000144ED492
S9030000FC
The module has an S0 record, four S1 records, and an S9 record. The following character
pairs comprise the S-record-format module.
S0 Record:
S0 — S-record type S0, indicating that it is a header record.
06 — Hexadecimal 06 (decimal 6), indicating that six character pairs (or ASCII bytes)
follow.
0000—A 4-character, 2-byte address field; zeros in this example.
48 — ASCII H
44 — ASCII D
52 — ASCII R
1B — The checksum.
First S1 Record:
S1 — S-record type S1, indicating that it is a code/data record to be loaded/verified at
a 2-byte address.
13 — Hexadecimal 13 (decimal 19), indicating that 19 character pairs, representing
19 bytes of binary data, follow.
0000—A 4-character, 2-byte address field (hexadecimal address 0000) indicating
where the data that follows is to be loaded.
MOTOROLA
MC68000 FAMILY PROGRAMMER’S REFERENCE MANUAL
C-3
S-Record Output Format
The next 16 character pairs of the first S1 record are the ASCII bytes of the actual program
code/data. In this assembly language example, the programOs hexadecimal opcodes are
sequentially written in the code/data fields of the S1 records.
Opcode
Instruction
285F
MOVE.L
(A7) +, A4
245F
MOVE.L
(A7) +, A2
2212
MOVE.L
(A2), D1
226A0004
MOVE.L
4(A2), A1
24290008
MOVE.L
FUNCTION(A1), D2
237C
MOVE.L
#FORCEFUNC, FUNCTION(A1)
The rest of this code continues in the remaining S1 recordOs code/data fields and stores in
memory location 0010, etc.
2A — The checksum of the first S1 record.
The second and third S1 records also contain hexadecimal 13 (decimal 19) character pairs
and end with checksums 13 and 52, respectively. The fourth S1 record contains 07 character pairs and has a checksum of 92.
S9 Record:
S9 — S-record type S9, indicating that it is a termination record.
03 — Hexadecimal 03, indicating that three character pairs (3 bytes) follow.
0000—The address field, zeros.
FC — The checksum of the S9 record.
Each printable character in an S-record encodes in hexadecimal (ASCII in this example)
representation of the binary bits that transmit. Figure C-2 illustrates the sending of the first
S1 record. Table C-2 lists the ASCII code for S-records.
.
RECORD LENGTH
ADDRESS
CODE/DATA
1
3
0
0
0
0
2
8
5
F
5 3 3 1 3 1 3 3 3 0 3 0 3 0 3 0 3 2 3 8 3 5 4 6
010100110011000100110001001100110011000000110000001100000011000000110010001110000011010101000110
TYPE
S
1
CHECKSUM
2
A
****
**** 3 2 4 1
**** 0011001001000001
Figure C-2. Transmission of an S1 Record
C-4
MC68000 FAMILY PROGRAMMER’S REFERENCE MANUAL
MOTOROLA
S-Record Output Format
Table C-2. ASCII Code
MOTOROLA
Least
Significant
Digit
0
1
2
3
4
5
6
7
0
NUL
DLE
SP
0
@
P
‘
p
1
SOH
DC1
!
1
A
Q
a
q
2
STX
DC2
“
2
B
R
b
r
Most Significant Digit
3
ETX
DC3
#
3
C
S
c
s
4
EOT
DC4
$
4
D
T
d
t
5
ENQ
NAK
%
5
E
U
e
u
6
ACK
SYN
&
6
F
V
f
v
7
BEL
ETB
’
7
G
W
g
w
8
BS
CAN
(
8
H
X
h
x
9
HT
EM
)
9
I
Y
i
y
A
LF
SUB
*
:
J
Z
j
z
B
VT
ESC
+
;
K
[
k
{
C
FF
FS
,
<
L
\
l
|
D
CR
GS
–
=
M
]
m
}
E
SO
RS
.
>
N
^
n
~
F
SI
US
/
?
O
_
o
DEL
MC68000 FAMILY PROGRAMMER’S REFERENCE MANUAL
C-5
S-Record Output Format
C-6
MC68000 FAMILY PROGRAMMER’S REFERENCE MANUAL
MOTOROLA