KS0040 - Pacific Display Devices

KS0040
65 COM / 132 SEG DRIVER & CONTROLLER FOR STN LCD
July. 1999.
Ver. 1.3
Prepared by:
Tae-Kwang, Park
parktk@samsung.co.kr
Contents in this document are subject to change without notice. No part of this document may be reproduced
or transmitted in any form or by any means, electronic or mechanical, for any purpose, without the express
written permission of LCD Driver IC Team.
KS0040
65 COM / 132 SEG DRIVER & CONTROLLER FOR STN LCD
KS0040 Specification Revision History
Version
0.0
1.0
1.1
1.2
1.3
2
Content
Original
1) Changed function
MPU interface pin & method are changed.
DDRAM extended style is changed from horizontal to vertical.
Reference voltage can be selected between internal VREF and VDD by REF pin.
2) Removed function
Horizontal display shift function is removed.
3) Added function
Double height character display function
Center mode display function
CGRAM full graphic function
Line cursor function
Vertical shift by character & first line fix and vertical shift function
4-bit interface mode
4) Changed pin name
DT1 → DUMMY (Not connected)
DT0 → REF (Reference voltage selection)
DIRC → MI (6800- / 8080-series selection)
DIRS → IF (8- / 4- bit interface length selection)
RES → RESET (H/W reset)
RW → RW_WR (Read / Write selection in 6800-series, Write enable in 8080-series)
E → E_RD (Read / Write enable in 6800-series, Read enable in 8080-series)
COMS1, 2 → COMI1, 2 (Common icon)
SEGS1 ~ SEGS4 → SEGI1 ~ SEGI4 (Segment icons)
1) Changed pin name
VC5ON → TEST3 (Connect to VSS)
TMPS0 → TEST4 (Connect to VSS)
TMPS1 → TEST5 (Connect to VSS)
2) DC Spec changed
IDD (3V): 150µA Max. → 180µA Max.
IDD (5V): 250µA Max. → 280µA Max.
3) Power ON / OFF sequence is added.
Page 1, 3, 23: CGROM character size is changed from 8,192 to 8,160.
Page 63, 64: VREF Item, REF = H → REF = L
Page 6: X-coordinates are changed (Pad No.206 to 246)
Date
Mar.1998
Jun.1998
Apr.1999
Jun.1999
Jul.1999
65 COM / 132 SEG DRIVER & CONTROLLER FOR STN LCD
KS0040
CONTENTS
INTRODUCTION ......................................................................................................................................... 1
FEATURES ................................................................................................................................................. 1
BLOCK DIAGRAM ...................................................................................................................................... 3
PAD CONFIGURATION .............................................................................................................................. 4
PAD CENTER COORDINATES................................................................................................................... 5
PIN DESCRIPTION ..................................................................................................................................... 8
POWER SUPPLY................................................................................................................................. 8
LCD DRIVER SUPPLY......................................................................................................................... 8
SYSTEM CONTROL ............................................................................................................................ 9
MPU INTERFACE ................................................................................................................................ 9
LCD DRIVER OUTPUT .......................................................................................................................10
TEST PIN ............................................................................................................................................10
FUNCTION DESCRIPTION ........................................................................................................................11
SYSTEM INTERFACE.........................................................................................................................11
RAM MAP ...........................................................................................................................................14
CHARACTER GENERATOR ROM FOR A FULL-SIZE FONT (FCGROM)...........................................23
CHARACTER GENERATOR ROM FOR A HALF-SIZE FONT (HCGROM) ..........................................23
LOW POWER CONSUMPTION MODE ...............................................................................................26
LCD DRIVING CIRCUIT ......................................................................................................................26
DISPLAY SHIFT CONTROL ................................................................................................................27
INSTRUCTION DESCRIPTION...................................................................................................................28
INITIALIZING & POWER SAVE MODE SETUP..........................................................................................40
HARDWARE RESET...........................................................................................................................40
INITIALIZING BY INSTRUCTION ........................................................................................................42
SLEEP MODE SET OR RELEASE BY INSTRUCTION........................................................................43
RECOMMENDATION OF POWER ON / OFF SEQUENCE .................................................................44
LCD DRIVING POWER SUPPLY CIRCUIT ................................................................................................45
VOLTAGE CONVERTER ....................................................................................................................46
VOLTAGE REGULATOR.....................................................................................................................48
LCD BIAS RESISTOR & FOLLOWER .................................................................................................52
USE THE EXTERNAL POWER SUPPLY ............................................................................................53
APPLICATION INFORMATION ..................................................................................................................54
MPU INTERFACE METHOD ...............................................................................................................54
LCD PANEL CONNECTION METHOD (1/65 DUTY CONFIGURATION) .............................................56
FRAME FREQUENCY................................................................................................................................60
MAXIMUM ABSOLUTE RATE....................................................................................................................63
ELECTRICAL CHARACTERISTICS...........................................................................................................64
DC CHARACTERISTICS.....................................................................................................................64
AC CHARACTERISTICS .....................................................................................................................66
3
65 COM / 132 SEG DRIVER & CONTROLLER FOR STN LCD
KS0040
INTRODUCTION
The KS0040 is a LCD driver and controller LSI for liquid crystal dot matrix character display systems. It can
display 1 to 4 lines of 8 characters with 16 x 16 dots format. So it is suitable for display of Asian characters such
as Korean, Chinese and Japanese. Also 8 x 16 dot half size alphanumeric characters can be displayed. And it can
display 64 x 128 dots graphic LCD using internal CGRAM. Voltage converter (2 to 4 times), voltage regulator and
voltage follower & bias circuits are built in the IC.
FEATURES
Driver Output Circuits
−
−
Common outputs: 64 common + 1 common for icon
Segment outputs: 128 segment + 4 segment for icon
Applicable Duty Ratios
Display size
Duty
Contents of outputs
1-line x 8 characters
1/17
1 x 8 characters + 16 x 4 vertical icons + 128 horizontal icons
2-line x 8 characters
1/33
2 x 8 characters + 32 x 4 vertical icons + 128 horizontal icons
3-line X 8 characters
1/49
3 x 8 characters + 48 x 4 vertical icons + 128 horizontal icons
4-line X 8 characters
1/65
4 x 8 characters + 64 x 4 vertical icons + 128 horizontal icons
On-chip Display Data RAM
−
−
−
−
−
Full-size Character Generator ROM (FCGROM): 2,088,960 bits (8,160 characters x 16 x 16 dot)
Half-size Character Generator ROM (HCGROM): 16,384 bits (128 characters x 8 x 16 dot)
Character Generator RAM (CGRAM): 8,192 bits (32 characters x 16 x 16 dot)
Display Data RAM (DDRAM): 1,024 bits (64 characters x 2 byte)
Icon RAM (ICONRAM): 384 bits (128 horizontal icons + 64 x 4 vertical icons)
Microprocessor Interface
−
−
8- / 4- bit parallel interface mode: 6800-series, 8080-series
Serial interface mode: 4 pins clock synchronous serial interface
Function Set
−
−
−
Various instruction sets: vertical dot-by-dot display shift, double height character, power control, etc.
COM / SEG bi-directional
H/W reset
On-chip Analog Circuit
−
−
−
Automatically adjusted oscillator circuit by duty set
Electrical volume for contrast control (64 steps)
o
Voltage converter (2 to 4 times) / voltage regulator (temperature coefficient = -0.05%/ C)
/ voltage follower & bias circuit
Operating Voltage Range
−
−
Supply voltage (VDD): 2.4 to 5.5V
LCD driving voltage (VLCD = V0 - VSS) = 13.0V
1
KS0040
65 COM / 132 SEG DRIVER & CONTROLLER FOR STN LCD
Low Power Consumption
−
−
Sleep mode operation (VDD = 3V: 5uA Max.)
Normal mode operation (VDD = 3V, V0 = 9V: 150uA Typ.)
Package Type
−
2
Gold bumped chip or TCP
65 COM / 132 SEG DRIVER & CONTROLLER FOR STN LCD
KS0040
BLOCK DIAGRAM
RESET
Oscillator
CK
PS
MI
IF
CSB
RS
RW_WR
E_RD
DB7
(SI)
DB6
(SCL)
DB5 to
DB4
Timing Generator
System
Interface
8 Instruction
Register
(IR)
Instruction
Decoder
4 bit/8 bit
Address
Counter
Serial
Interface
8
Display
data RAM
(DDRAM)
128X8 bits
128-bits
Shift
Register
Data
register
(DR)
8
I/O Buffer
8
DB3 to
DB0
Address Generator
3
13
7
Character
generator
(ICONRAM)
RAM
48 bytes
(CGRAM)
1,024 bytes
Icon RAM
8
VDD
16
Character
generator
ROM for
full size
char. font
(FCGROM)
2,088,960bit
128-bits
Latch
Circuit
(Bi-dir)
Segment
Driver
COM1 to
COM64
COMI1
COMI2
SEG1 to
SEG128
SEGI1
4 bits
Latch
Circuit
Cursor
blink
control
Character
generator
ROM for
half size
char. font
(HCGROM)
16,384 bits
SEGI2
SEGI3
SEGI4
LCD
Driver
Voltage
Selector
16
Display attribute control circuit
16
VSS
Common
Driver
8
8
4
65 bits
Shift
Register
(Bi-dir)
8
Parallel to serial converter &
Scroll Control circuit
LCD Driving Power Circuit
Voltage Converter
Voltage Regulator
Voltage Follower
& Bias Resistor
V4
V3
V2
V1
V0
VR
REF
VOUT
CAP3-
CAP3+
CAP2-
CAP2+
CAP1-
CAP1+
Figure 1. Block Diagram
3
KS0040
65 COM / 132 SEG DRIVER & CONTROLLER FOR STN LCD
PAD CONFIGURATION
.......................
155
154
298
299
Y
…..
X
(0,0)
335
1
118
117
KS0040
............
.
DUMMY
PAD
Figure 2. Pad Configuration
Table 1. KS0040 Pad Dimensions
Item
Pad No.
Chip size
-
Pad pitch
Bumped pad size
Bumped pad height
12160
3860
118 to 335
70
1 to 117
56
114
118 to 154
108
50
155 to 298
50
108
229 to 335
108
50
1 to 138
µm
17 (Typ.)
ILB Align Key Coordinate
108µm
42µm
(+5738, +1800)
42µm
(-5738, +1800)
108µm
42µm
(+5886.5, -1543)
42µm
30µm
60µm
108µm
108µm
4
Y
90
30µm 30µm 30µm
30µm 30µm 30µm
(-5886.5, -1558)
Unit
X
1 to 117
COG Align Key Coordinate
30µm 30µm 30µm
Size
65 COM / 132 SEG DRIVER & CONTROLLER FOR STN LCD
KS0040
PAD CENTER COORDINATES
Table 2. Pad Center Coordinates
[Unit: µm]
Pad
No.
Pad
Name
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
DUMMY
DUMMY
VSS
TEST1
VDD
DUMMY
VSS
REF
VDD
MI
VSS
IF
VDD
PS
VSS
CSB
VDD
RESET
RS
RW_WR
E_RD
DB7
DB6
DB5
DB4
DB3
DB2
DB1
DB0
DUMMY
DUMMY
DUMMY
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
Coordinate
X
-5220
-5130
-5040
-4950
-4860
-4770
-4680
-4590
-4500
-4410
-4320
-4230
-4140
-4050
-3960
-3870
-3780
-3690
-3600
-3510
-3420
-3330
-3240
-3150
-3060
-2970
-2880
-2790
-2700
-2610
-2520
-2430
-2340
-2250
-2160
-2070
-1980
-1890
-1800
-1710
-1620-
Y
-1806
-1806
-1806
-1806
-1806
-1806
-1806
-1806
-1806
-1806
-1806
-1806
-1806
-1806
-1806
-1806
-1806
-1806
-1806
-1806
-1806
-1806
-1806
-1806
-1806
-1806
-1806
-1806
-1806
-1806
-1806
-1806
-1806
-1806
-1806
-1806
-1806
-1806
-1806
-1806
-1806
Pad
No.
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
Pad
Name
VSS
DUMMY
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
DUMMY
VOUT
VOUT
VOUT
VOUT
DUMMY
CAP3+
CAP3+
CAP3+
CAP3+
CAP3CAP3CAP3CAP3CAP1+
CAP1+
CAP1+
CAP1+
CAP1CAP1CAP1CAP1CAP2+
CAP2+
CAP2+
CAP2+
CAP2CAP2CAP2-
Coordinate
X
Y
Pad
No.
-1530
-1440
-1350
-1260
-1170
-1080
-990
-900
-810
-720
-630
-540
-450
-360
-270
-180
-90
0
90
180
270
360
450
540
630
720
810
900
990
1080
1170
1260
1350
1440
1530
1620
1710
1800
1890
1980
2070
-1806
-1806
-1806
-1806
-1806
-1806
-1806
-1806
-1806
-1806
-1806
-1806
-1806
-1806
-1806
-1806
-1806
-1806
-1806
-1806
-1806
-1806
-1806
-1806
-1806
-1806
-1806
-1806
-1806
-1806
-1806
-1806
-1806
-1806
-1806
-1806
-1806
-1806
-1806
-1806
-1806
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
Pad
Name
CAP2DUMMY
DUMMY
VR
VR
VR
VR
DUMMY
V0
V0
V0
V0
DUMMY
V1
V1
V2
V2
V3
V3
V4
V4
DUMMY
VSS
TEST3
VDD
TEST5
VSS
TEST4
VDD
TEST2
VSS
CK
VDD
DUMMY
DUMMY
DUMMY
COMI1
COM1
COM2
COM3
COM4
Coordinate
X
2160
2250
2340
2430
2520
2610
2700
2790
2880
2970
3060
3150
3240
3330
3420
3510
3600
3690
3780
3870
3960
4050
4140
4230
4320
4410
4500
4590
4680
4770
4860
4950
5040
5130
5220
5920
5920
5920
5920
5920
5920
Y
-1806
-1806
-1806
-1806
-1806
-1806
-1806
-1806
-1806
-1806
-1806
-1806
-1806
-1806
-1806
-1806
-1806
-1806
-1806
-1806
-1806
-1806
-1806
-1806
-1806
-1806
-1806
-1806
-1806
-1806
-1806
-1806
-1806
-1806
-1806
-1326
-1256
-1186
-1116
-1046
-976
5
KS0040
65 COM / 132 SEG DRIVER & CONTROLLER FOR STN LCD
Table 2. Pad Center Coordinates (Continued)
[Unit: µm]
6
Pad
Pad
No.
Name
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
COM5
COM6
COM7
COM8
COM17
COM18
COM19
COM20
COM21
COM22
COM23
COM24
COM33
COM34
COM35
COM36
COM37
COM38
COM39
COM40
COM49
COM50
COM51
COM52
COM53
COM54
COM55
COM56
SEGI1
SEGI2
DUMMY
DUMMY
DUMMY
DUMMY
DUMMY
DUMMY
DUMMY
DUMMY
DUMMY
SEG1
SEG2
Coordinate
Pad
Pad
X
Y
No.
Name
-906
-836
-766
-696
-626
-556
-486
-416
-346
-276
-206
-136
-66
4
74
144
214
284
354
424
494
564
634
704
774
844
914
984
1054
1124
1194
1770
1770
1770
1770
1770
1770
1770
1770
1770
1770
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
5920
5920
5920
5920
5920
5920
5920
5920
5920
5920
5920
5920
5920
5920
5920
5920
5920
5920
5920
5920
5920
5920
5920
5920
5920
5920
5920
5920
5920
5920
5920
5005
4935
4865
4795
4725
4655
4585
4515
4445
4375
SEG3
SEG4
SEG5
SEG6
SEG7
SEG8
SEG9
SEG10
SEG11
SEG12
SEG13
SEG14
SEG15
SEG16
SEG17
SEG18
SEG19
SEG20
SEG21
SEG22
SEG23
SEG24
SEG25
SEG26
SEG27
SEG28
SEG29
SEG30
SEG31
SEG32
SEG33
SEG34
SEG35
SEG36
SEG37
SEG38
SEG39
SEG40
SEG41
SEG42
SEG43
Coordinate
Pad
Pad
X
No.
Name
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
240
241
242
243
244
245
246
SEG44
SEG45
SEG46
SEG47
SEG48
SEG49
SEG50
SEG51
SEG52
SEG53
SEG54
SEG55
SEG56
SEG57
SEG58
SEG59
SEG60
SEG61
SEG62
SEG63
SEG64
SEG65
SEG66
SEG67
SEG68
SEG69
SEG70
SEG71
SEG72
SEG73
SEG74
SEG75
SEG76
SEG77
SEG78
SEG79
SEG80
SEG81
SEG82
SEG83
SEG84
4305
4235
4165
4095
4025
3955
3885
3815
3745
3675
3605
3535
3465
3395
3325
3255
3185
3115
3045
2975
2905
2835
2765
2695
2625
2555
2485
2415
2345
2275
2205
2135
2065
1995
1925
1855
1785
1715
1645
1575
1505
Y
1770
1770
1770
1770
1770
1770
1770
1770
1770
1770
1770
1770
1770
1770
1770
1770
1770
1770
1770
1770
1770
1770
1770
1770
1770
1770
1770
1770
1770
1770
1770
1770
1770
1770
1770
1770
1770
1770
1770
1770
1770
Coordinate
X
1435
1365
1295
1225
1155
1085
1015
945
875
805
735
665
595
525
455
385
315
245
175
105
35
-35
-105
-175
-245
-315
-385
-455
-525
-595
-665
-735
-805
-875
-945
-1015
-1085
-1155
-1225
-1295
-1365
Y
1770
1770
1770
1770
1770
1770
1770
1770
1770
1770
1770
1770
1770
1770
1770
1770
1770
1770
1770
1770
1770
1770
1770
1770
1770
1770
1770
1770
1770
1770
1770
1770
1770
1770
1770
1770
1770
1770
1770
1770
1770
65 COM / 132 SEG DRIVER & CONTROLLER FOR STN LCD
KS0040
Table 2. Pad Location (Continued)
[Unit: µm]
Pad
Pad
No.
Name
247
248
249
250
251
252
253
254
255
256
257
258
259
260
261
262
263
264
265
266
267
268
269
270
271
272
273
274
275
276
SEG85
SEG86
SEG87
SEG88
SEG89
SEG90
SEG91
SEG92
SEG93
SEG94
SEG95
SEG96
SEG97
SEG98
SEG99
SEG100
SEG101
SEG102
SEG103
SEG104
SEG105
SEG106
SEG107
SEG108
SEG109
SEG110
SEG111
SEG112
SEG113
SEG114
Coordinate
Pad
Pad
X
Y
No.
Name
1770
1770
1770
1770
1770
1770
1770
1770
1770
1770
1770
1770
1770
1770
1770
1770
1770
1770
1770
1770
1770
1770
1770
1770
1770
1770
1770
1770
1770
1770
277
278
279
280
281
282
283
284
285
286
287
288
289
290
291
292
293
294
295
296
297
298
299
300
301
302
303
304
305
306
SEG115
SEG116
SEG117
SEG118
SEG119
SEG120
SEG121
SEG122
SEG123
SEG124
SEG125
SEG126
SEG127
SEG128
DUMMY
DUMMY
DUMMY
DUMMY
DUMMY
DUMMY
DUMMY
DUMMY
DUMMY
SEGI3
SEGI4
COMI2
COM64
COM63
COM62
COM61
-1435
-1505
-1575
-1645
-1715
-1785
-1855
-1925
-1995
-2065
-2135
-2205
-2275
-2345
-2415
-2485
-2555
-2625
-2695
-2765
-2835
-2905
-2975
-3045
-3115
-3185
-3255
-3325
-3395
-3465
Coordinate
Pad
Pad
X
No.
Name
307
308
309
310
311
312
313
314
315
316
317
318
319
320
321
322
323
324
325
326
327
328
329
330
331
332
333
334
335
COM60
COM59
COM58
COM57
COM48
COM47
COM46
COM45
COM44
COM43
COM42
COM41
COM32
COM31
COM30
COM29
COM28
COM27
COM26
COM25
COM16
COM15
COM14
COM13
COM12
COM11
COM10
COM9
DUMMY
-3535
-3605
-3675
-3745
-3815
-3885
-3955
-4025
-4095
-4165
-4235
-4305
-4375
-4445
-4515
-4585
-4655
-4725
-4795
-4865
-4935
-5005
-5920
-5920
-5920
-5920
-5920
-5920
-5920
-5920
Y
1770
1770
1770
1770
1770
1770
1770
1770
1770
1770
1770
1770
1770
1770
1770
1770
1770
1770
1770
1770
1770
1770
1194
1124
1054
984
914
844
774
704
Coordinate
X
-5920
-5920
-5920
-5920
-5920
-5920
-5920
-5920
5920
-5920
-5920
-5920
-5920
-5920
-5920
-5920
-5920
-5920
-5920
-5920
-5920
-5920
-5920
-5920
-5920
-5920
-5920
-5920
-5920
Y
634
564
494
424
354
284
214
144
74
4
-66
-136
-206
-276
-346
-416
-486
-556
-626
-696
-766
-836
-906
-976
-1046
-1116
-1186
-1256
-1326
7
KS0040
65 COM / 132 SEG DRIVER & CONTROLLER FOR STN LCD
PIN DESCRIPTION
POWER SUPPLY
Table 3. Pin Description
Name
VDD
I/O
Power
VSS
V0
Description
Power supply
Connect to MPU power supply pin
0V (GND)
Bias voltage level for LCD driving
Voltages have the following relationship:
V0 ≥ V1 ≥ V2 ≥ V3 ≥ V4 ≥ VSS
When the on-chip power circuit is active, these voltages are generated according to
the state of LCD bias, as following table.
V1
V2
V3
V4
I/O
LCD bias
V1
V2
V3
V4
1/9 bias
(8/9) x V0
(7/9) x V0
(2/9) x V0
(1/9) x V0
1/8 bias
(7/8) x V0
(6/8) x V0
(2/8) x V0
(1/8) x V0
1/7 bias
(6/7) x V0
(5/7) x V0
(2/7) x V0
(1/7) x V0
1/5 bias
(4/5) x V0
(3/5) x V0
(2/5) x V0
(1/5) x V0
LCD DRIVER SUPPLY
Table 3. Pin Description (Continued)
Name
Description
CAP1+
Capacitor1+ connect for the internal voltage converter
CAP1-
Capacitor1- connect for the internal voltage converter
CAP2+
CAP2-
O
Capacitor2+ connect for the internal voltage converter
Capacitor2- connect for the internal voltage converter
CAP3+
Capacitor3+ connect for the internal voltage converter
CAP3-
Capacitor3- connect for the internal voltage converter
VOUT
I/O
VR
I
V0 voltage adjustment pin which is valid only when using external resistors
I
Select the reference voltage of internal voltage regulator
REF = "High": The reference voltage of internal voltage regulator is the voltage of
VDD.
REF = "Low": The reference voltage of internal voltage regulator is the internal VREF
(2.0V).
REF
8
I/O
Voltage converter output
65 COM / 132 SEG DRIVER & CONTROLLER FOR STN LCD
KS0040
SYSTEM CONTROL
Table 3. Pin Description (Continued)
Name
I/O
CK
I
MI
I
IF
I
PS
I
Description
External clock input
It must be fixed to "High" or “Low” when the internal oscillation circuit is used.
In case of external clock mode, used as the clock input and OSC bit should be OFF.
Select the kinds of the MPU to interface
When MI = "High": 6800-series MPU interface mode
When MI = "Low": 8080-series MPU interface
Select the interface bit length when parallel interfacing (PS = "High")
When IF = "High": 8-bit interface mode
When IF = "Low": 4-bit interface mode
Select Interface mode with the MPU
When PS = "High": parallel interface mode
When PS = "Low": serial interface mode
MPU INTERFACE
Table 3. Pin Description (Continued)
Name
I/O
Description
RESET
I
Hardware reset input
Initialization is performed by edge sensing (rising or falling) of the RESET signal.
CSB
I
Used as chip selection input
When CSB = "High", not selected
When CSB = "Low", selected
RS
I
Used as register selection input
When RS = "High", data register
When RS = "Low", instruction register
RW_WR
I
When MI = "High"(6800-series MPU interfacing), used as read (RW_WR = "High") /
write (RW_WR = "Low") selection input (R/W).
When MI = "Low "(8080-series MPU interfacing), used as write enable input (WR).
E_RD
I
DB0 to
DB7
I/O
When MI = "High"(6800-series MPU interfacing), used as read/write enable input (E).
When MI = "Low "(8080-series MPU interfacing), used as read enable input (RD).
When 8-bit interface mode, DB0 to DB7 are used as bi-directional data bus pin.
When 4-bit interface mode, only DB4 to DB7 are used as data input pin and DB0 to
DB3 are not used.
When serial mode, DB6 (SCL) is used as serial clock input pin, DB7 (SI) is used as
serial data input pin and the others are not used.
9
KS0040
65 COM / 132 SEG DRIVER & CONTROLLER FOR STN LCD
LCD DRIVER OUTPUT
Table 3. Pin Description (Continued)
Name
I/O
Description
COM1 to
COM64
O
Common signal output for character display
COMI1,
COMI2
O
Common signal output for horizontal icon display
These are the same signal but the name is different.
SEG1 to
SEG128
O
Segment signal output for character display
SEGI1 to
SEGI4
O
Segment signal output for vertical icon display
TEST PIN
Table 3. Pin Description (Continued)
Name
I/O
TEST1 to
TEST5
I
Description
Test pin
Connect these to "Low".
NOTE: DUMMY - These pins should be opened (floated).
10
65 COM / 132 SEG DRIVER & CONTROLLER FOR STN LCD
KS0040
FUNCTION DESCRIPTION
SYSTEM INTERFACE
KS0040 has two kinds interface type with MPU: bus mode (8- / 4-bit length), serial mode. Serial and bus mode is
selected by PS pin.
Table 4. Various Kinds of MPU Interface
PS
Bus
mode (H)
Serial
mode
(L)
MI
IF
CSB
RS
RW_WR
E_RD
DB0-3
DB4-5
DB6
DB7
6800series
(H)
8 bit (H)
CSB
RS
R/W
E
DB0-3
DB4-5
DB6
DB7
4 bit (L)
CSB
RS
(L)
E
*
DB4-5
DB6
DB7
8080series
(L)
8 bit (H)
CSB
RS
WR
RD
DB0-3
DB4-5
DB6
DB7
4 bit (L)
CSB
RS
WR
(H)/(L)
*
DB4-5
DB6
DB7
(H)/(L)
(H)/(L)
CSB
RS
(H)/(L)
(H)/(L)
*
*
SCL
SI
NOTE: “*” - Don’t care ("High", "Low" or "Open").
(H)/(L): fixed “High” (VDD) or “Low” (VSS)
NOTE: Read operation is not permitted to 4-bit or serial interface mode.
PS: "High" = parallel interface mode,
MI: "High" = 6800-series MPU interface,
IF: "High" = 8-bit interface mode,
CSB: "High" = chip not selected,
RS: "High" = data Register select,
RW_WR: 6800-series read / write select,
E_RD: 6800-series "Low" enable,
SCL (DB6): serial clock input
SI (DB7): serial data input
"Low" = serial interface mode
"Low" = 8080-series MPU interface mode
"Low" = 4-bit interface mode
"Low" = chip selected
"Low" = instruction register select
8080-series active "High " write enable
8080-series active "Low " read enable
11
KS0040
65 COM / 132 SEG DRIVER & CONTROLLER FOR STN LCD
Interface with MPU in Parallel Bus Mode (PS = "High")
In parallel interface mode, 6800-series and 8080-series MPU is selected by MI pin, and interface bit length (8- / 4bit) is selected by IF pin. During write operation, the 16-bit data register (DR) and the 8-bit instruction register (IR)
is used. The data register (DR) is used as temporary data storage place from MPU for being written into DDRAM
/ CGRAM / ICONRAM. The target RAM is selected by RAM selection instruction. The instruction register (IR) is
used only to store instruction code transferred from MPU. To select either DR or IR, use the RS input pin in
parallel mode or serial mode.
8-Bit Bus Mode (IF = "High")
CSB
4-Bit Bus Mode (IF = "Low")
IF
RS
RW_WR
E_RD
DB7 to DB0
D7 to D0
Instruction
Write
D7 to D0
Data
Write
XX
D7
~D0
Dummy
Read
Data
Read
D7 to D4
D3 to D0
D7 to D4 D3 to D0
Instruction
Write
Data
Write
Figure 3. Timing Diagram of 6800-series Bus Mode Data Transfer (MI = "High")
8-Bit Bus Mode (IF = "High")
CSB
4-Bit Bus Mode (IF = "Low")
IF
RS
RW_WR
E_RD
DB7 to DB0
D7 to D0
Instruction
Write
D7 to D0
Data
Write
XX
Dummy
Read
D7
- D0
Data
Read
D7 to D4
D3 to D0
Instruction
Write
D7 to D4 D3 to D0
Data
Write
Figure 4. Timing Diagram of 8080-Series Bus Mode Data Transfer (MI = "Low")
12
65 COM / 132 SEG DRIVER & CONTROLLER FOR STN LCD
KS0040
Interface with MPU in Serial Bus Mode (PS = "Low")
When PS input pin is "Low", clock synchronized serial interface mode is selected. At this time, the following four
ports, SCL (DB6, synchronizing transfer clock input), SI (DB7, serial data input), and RS (register selection input),
CSB (chip selection input) are used. By setting CSB to "Low", KS0040 can receive SCL input. If CSB is set to
"High", KS0040 initialize the interface circuit (8-bit shift register and 3-bit counter). Serial data is input in the order
of "D7, D6, D5, D4, D3, D2, D1, D0" from the serial data input pin (SI = DB7) at the rising edge of serial clock
(SCL = DB6).
At the rising edge of the 8th serial clock, the serial data (D7-D0) is converted into 8-bit bus data. The RS input of
the DR / IR selection is latched at the rising edge of the 8th serial clock (SCL).
CSB
SI(DB7)
SCL(DB6)
D7
1
D6
2
D5
3
D4
4
D3
5
D2
6
D1
7
D0
8
D7
1
D6
2
D5
3
D4
4
D3
5
RS
Figure 5. Timing Diagram of Serial Data Transfer
13
KS0040
65 COM / 132 SEG DRIVER & CONTROLLER FOR STN LCD
RAM MAP
Internal RAM has total 1,200 bytes, and consist of DDRAM (128 bytes), ICONRAM (48 bytes) and CGRAM (1,024
bytes).
Table 5. RAM Map
R3 R2 R1 R0
0 0 0 0
0 0 0 1
1 0 0 0
1 0 0 1
1 0 1 0
1 0 1 1
1 1 0 0
1 1 0 1
1 1 1 0
1 1 1 1
Address
00H - 0FH
10H - 1FH
20H - 2FH
30H - 3FH
40H - 4FH
50H - 5FH
60H - 6FH
70H - 7FH
00H - 0FH
10H - 1FH
20H - 2FH
00H - 1FH
20H - 3FH
40H - 5FH
60H - 7FH
00H - 1FH
20H - 3FH
40H - 5FH
60H - 7FH
00H - 1FH
20H - 3FH
40H - 5FH
60H - 7FH
00H - 1FH
20H - 3FH
40H - 5FH
60H - 7FH
00H - 1FH
20H - 3FH
40H - 5FH
60H - 7FH
00H - 1FH
20H - 3FH
40H - 5FH
60H - 7FH
00H - 1FH
20H - 3FH
40H - 5FH
60H - 7FH
00H - 1FH
20H - 3FH
40H - 5FH
60H - 7FH
RAM data usage (D7~D0)
DDRAM (1 line)
DDRAM (2nd line)
EXT = 0
DDRAM (3rd line)
DDRAM (4th line)
EXT = 1
DDRAM (5th line)
DDRAM (6th line)
DDRAM (7th line)
DDRAM (8th line)
ICONRAM upper 128 icons (C1 ~ C128)
ICONRAM lower 128 icons (C129 ~ C256)
ICONRAM COMS data (S1 ~ S128)
CGRAM 1st 16 x 16 pattern
CGRAM 2nd 16 x 16 pattern
CGRAM 3rd 16 x 16 pattern
CGRAM 4th 16 x 16 pattern
CGRAM 5th 16 x 16 pattern
CGRAM 6th 16 x 16 pattern
CGRAM 7th 16 x 16 pattern
CGRAM 8th 16 x 16 pattern
CGRAM 9th 16 x 16 pattern
CGRAM 10th 16 x 16 pattern
CGRAM 11th 16 x 16 pattern
CGRAM 12th 16 x 16 pattern
CGRAM 13th 16 x 16 pattern
CGRAM 14th 16 x 16 pattern
CGRAM 15th 16 x 16 pattern
CGRAM 16th 16 x 16 pattern
CGRAM 17th 16 x 16 pattern
th
CGRAM 18 16 x 16 pattern
th
CGRAM 19 16 x 16 pattern
CGRAM 20th 16 x 16 pattern
CGRAM 21st 16 x 16 pattern
CGRAM 22nd 16 x 16 pattern
CGRAM 23rd 16 x 16 pattern
CGRAM 24th 16 x 16 pattern
CGRAM 25th 16 x 16 pattern
CGRAM 26th 16 x 16 pattern
CGRAM 27th 16 x 16 pattern
CGRAM 28th 16 x 16 pattern
th
CGRAM 29 16 x 16 pattern
th
CGRAM 30 16 x 16 pattern
st
CGRAM 31 16 x 16 pattern
nd
CGRAM 32 16 x 16 pattern
NOTE: R3- R0: RAM / system select register
14
RAM size
st
128byte
48byte
128byte
(page 0)
128byte
(page 1)
128byte
(page 2)
128byte
(page 3)
128byte
(page 4)
128byte
(page 5)
128byte
(page 6)
128byte
(page 7)
65 COM / 132 SEG DRIVER & CONTROLLER FOR STN LCD
KS0040
Display Data RAM (DDRAM)
DDRAM stores 16-bits character code in FCGROM / CGRAM and 8-bits character code in HCGROM, and its
maximum number is 128-byte (64-word: 64 Characters of full-size fonts or 128 characters of half-size fonts). The
displayable area is 64-byte and the other is extended data area. To display extended DDRAM data, set the EXT
bit "High" in system register set instruction.
DDRAM address is set by the address counter (AC) as a hexadecimal number.
MSB
AC6
LSB
AC5
AC4
AC3
AC2
AC1
AC0
The Relations of DDRAM Address and Display Position
When DDRAM is set to normal mode (EXT = "Low")
1st
COM1
|
COM16
COM17
|
COM32
COM33
|
COM48
COM49
|
COM64
00
01
2nd
02
03
3rd
4th
5th
6th
10
11
12
13
14
15
16
17
18
19
1A
1B
1C
1D
1E
1F
20
21
22
23
24
25
26
27
28
29
2A
2B
2C
2D
2E
2F
30
31
32
33
34
35
36
37
38
39
3A
3B
3C
3D
3E
3F
04
05
06
07
08
09
0A
0B
7th
0C 0D
8th
0E
0F
(a) Display Shift is not performed
COM1
|
COM16
COM17
|
COM32
COM33
|
COM48
COM49
|
COM64
1st
10
11
2nd
12 13
3rd
14 15
4th
16
17
5th
18
19
1A
6th
1B
1C
7th
1D
1E
8th
1F
20
21
22
23
24
25
26
27
28
29
2A
2B
2C
2D
2E
2F
30
31
32
33
34
35
36
37
38
39
3A
3B
3C
3D
3E
3F
00
01
02
03
04
05
06
07
08
09
0A
0B
0C
0D
0E
0F
(b) Display Shift Up is performed
st
nd
1
COM1
|
COM16
COM17
|
COM32
COM33
|
COM48
COM49
|
COM64
rd
2
th
3
4
30
31
32
33
34
35
36
37
38
5th
39
6th
3A 3B
7th
3C 3D
8th
3E 3F
00
01
02
03
04
05
06
07
08
09
0A
0B
0C
0D
0E
0F
10
11
12
13
14
15
16
17
18
19
1A
1B
1C
1D
1E
1F
20
21
22
23
24
25
26
27
28
29
2A
2B
2C
2D
2E
2F
(c) Display Shift Down is performed
Figure 6. Normal Mode DDRAM Address (EXT = "Low")
15
KS0040
65 COM / 132 SEG DRIVER & CONTROLLER FOR STN LCD
When DDRAM is Set to Extended Mode (EXT = "High")
1st
COM1
|
COM16
COM17
|
COM32
COM33
|
COM48
COM49
|
COM64
00
01
2nd
02 03
10
11
12
13
14
15
16
17
18
19
1A
1B
1C
1D
1E
1F
20
21
22
23
24
25
26
27
28
29
2A
2B
2C
2D
2E
2F
30
31
32
33
34
35
36
37
38
39
3A
3B
3C
3D
3E
3F
40
50
41
51
42
52
43
53
44
54
45
55
46
56
47
57
48
58
49
59
4A
5A
4B
5B
4C
5C
4D
5D
4E
5E
4F
5F
60
70
61
71
62
72
63
73
64 65 66 67 68 69 6A
74 75 76 77 78 79 7A
(a) Display Shift is not performed
6B
7B
6C
7C
6D
7D
6E
7E
6F
7F
10
11
2nd
12 13
14
3rd
15
16
17
18
19
6th
1A 1B
7th
1C 1D
8th
1E 1F
20
21
22
23
24
25
26
27
28
29
2A
2B
2C
2D
2E
2F
30
31
32
33
34
35
36
37
38
39
3A
3B
3C
3D
3E
3F
40
41
42
43
44
45
46
47
48
49
4A
4B
4C
4D
4E
4F
50
60
70
00
51
61
71
01
52
62
72
02
53
63
73
03
54 55 56 57 58 59 5A
64 65 66 67 68 69 6A
74 75 76 77 78 79 7A
04 05 06 07 08 09 0A
(b) Display Shift-up is performed
5B
6B
7B
0B
5C
6C
7C
0C
5D
6D
7D
0D
5E
6E
7E
0E
5F
6F
7F
0F
70
71
2nd
72
73
74
75
76
77
78
00
01
02
03
04
05
06
07
10
11
12
13
14
15
16
20
21
22
23
24
25
30
31
32
33
34
40
50
41
51
42
52
43
53
44
54
60
61
62
63
1st
COM1
|
COM16
COM17
|
COM32
COM33
|
COM48
COM49
|
COM64
1st
COM1
|
COM16
COM17
|
COM32
COM33
|
COM48
COM49
|
COM64
3rd
4th
5th
04
05
06
07
08
4th
7th
0C 0D
8th
0E 0F
5th
4th
3rd
09
6th
0A 0B
5th
79
6th
7A 7B
7th
7C 7D
8th
7E 7F
08
09
0A
0B
0C
0D
0E
0F
17
18
19
1A
1B
1C
1D
1E
1F
26
27
28
29
2A
2B
2C
2D
2E
2F
35
36
37
38
39
3A
3B
3C
3D
3E
3F
45
55
46
56
47
57
48
58
49
59
4A
5A
4B
5B
4C
5C
4D
5D
4E
5E
4F
5F
64
65 66 67 68
69 6A
(c) Display Shift-down is performed
6B
6C
6D
6E
6F
Figure 7. Extended Mode DDRAM Address (EXT = "High")
16
65 COM / 132 SEG DRIVER & CONTROLLER FOR STN LCD
KS0040
Character Generator RAM (CGRAM)
CGRAM is used for user defined character pattern. It can generate 32,16 X 16 dots full-size fonts include cursor
position. The capacity of CGRAM can support bitmap graphics 128 X 64 dot. To use the character pattern in
CGRAM write the character code into DDRAM like table 6.
Table 6. Relationship between Character Code (DDRAM) and Character Pattern (CGRAM)
Character code
(DDRAM data)
0000h
:
001Fh
CGRAM address
RRRR
3 2 1 0
AAAAAA
654321
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
:
1111
1111
1111
1111
1111
1111
1111
1111
1111
1111
1111
1111
1111
1111
1111
1111
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
CGRAM data
(A0 = 0)
D D D D D DDD
7 6 5 4 3 21 0
CGRAM data
(A0 = 1)
D D D D D DD D
7 6 5 4 3 21 0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
:
110000
110001
110010
110011
110100
110101
110110
110111
111000
111001
111010
111011
111100
111101
111110
111111
Pattern
number
Pattern 1
:
:
:
Pattern 32
17
KS0040
65 COM / 132 SEG DRIVER & CONTROLLER FOR STN LCD
Table 7. Example for Bitmap Graphic by CGRAM
Character code
(DDRAM data)
0000h
0001h
:
CGRAM data
(A0 = 0)
CGRAM address
CGRAM data
(A0 = 1)
RRRR
3 2 1 0
AAAAAA
654321
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
Pattern 1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
:
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
:
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
Pattern 2
CGRAM0 CGRAM1
CGRAM2 CGRAM3
D D D D D DD D D D D D DD DD
7 6 5 4 3 21 0 7 6 5 4 32 1 0
:
Character Display
Figure 8. Example for Bitmap Display with Character
18
Pattern
number
:
:
65 COM / 132 SEG DRIVER & CONTROLLER FOR STN LCD
KS0040
|
|
|
|
|
|
|
(*1024)
|
|
(*16)
|
|
(*1023)
|
|
(*15)
|
|
|
|
|
|
|
(*1012)
(*1014)
(*4)
(*1011)
(*6)
(*3)
(*1010)
(*1013)
(*2)
(*1009)
(*5)
(*1)
Figure 9. Relationship between CGRAM Full Graphic Mode Data Writing and Display Pattern (FG = "High")
During CGROM full graphic mode, CGRAM data is written from (*1) to (*1024) by 8-bit length
Table 8. The Order of CGRAM Data Writing
(*1)
(*17)
(*2)
(*18)
(*3)
(*19)
(*4)
(*20)
(*5)
*(21)
(*6)
(*22)
-----
-----
-----
-----
(*15)
(*31)
(*16)
(*32)
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
(*1009)
(*1010)
(*1011)
(*1012)
(*1013)
(*1014)
---
---
---
(*1022)
(*1023)
(*1024)
19
KS0040
65 COM / 132 SEG DRIVER & CONTROLLER FOR STN LCD
Segment & Common Icon RAM (ICONRAM)
ICONRAM has Segment / Common Icon pattern data. COMI1 or COMI2 and SEGI1~4 makes the data of
ICONRAM enable to display icons.
Table 9. Relationship between ICONRAM Address and Display Pattern
ICONRAM address
A5 A4
0 0
0 1
1 0
ICONRAM bits
A3 A2 A1 A0
D7
D6
D5
D4
D3
D2
D1
D0
0 0 0 0
VL1
VL2
VR1
VR2
VL3
VL4
VR3
VR4
0 0 0 1
VL5
VL6
VR5
VR6
VL7
VL8
VR7
VR8
:
:
1 1 1 0
VL57
VL58
VR57
VR58
VL59
VL60
VR59
VR60
1 1 1 1
VL61
VL62
VR61
VR62
VL63
VL64
VR63
VR64
0 0 0 0
VL65
VL66
VR65
VR66
VL67
VL68
VR67
VR68
0 0 0 1
VL69
VL70
VR69
VR70
VL71
VL72
VR71
VR72
:
:
1 1 1 0
VL121
VL122
VR121 VR122
VL123
VL124
VR123 VR124
1 1 1 1
VL125
VL126
VR125 VR126
VL127
VL128
VR127 VR128
0 0 0 0
H1
H2
H3
H4
H5
H6
H7
H8
0 0 0 1
H9
H10
H11
H12
H13
H14
H15
H16
:
20
Upper 128
SEGI icons
data (*1)
Lower 128
SEGI icons
data (*2)
COMI icons
data (*3)
:
1 1 1 0
H113
H114
H115
H116
H117
H118
H119
H120
1 1 1 1
H121
H122
H123
H124
H125
H126
H127
H128
NOTE: VLn: vertical left n-th icon, VRn: vertical right n-th icon
Hn: horizontal n-th icon (where n = 1 to 128)
Icons
65 COM / 132 SEG DRIVER & CONTROLLER FOR STN LCD
KS0040
(*3)
COMI1 -
H1
H2
H3
H4 --- H127
H128
COM1 -
VL1
VL2
VR1
VR2
COM2 -
VL3
VL4
VR3
VR4
COM3 |
COM31 -
|
|
|
|
COM32 -
VL63
VL64
VR63
VR64
COM33 -
VL65
VL66
VR65
VR66
COM34 |
COM62 -
|
|
|
|
Character Display Area
(*2)
SEGI4-
SEGI3-
SEG128-
SEG127-
|
SEG4-
SEG3-
SEG2-
VR127 VR128
SEG1-
VR125 VR126
VL127 VL128
SEGI2-
VL125 VL126
COM64 -
SEGI1-
COM63 -
(*1)
-SEGI1
VL2
VR1
VR2
VL3
VL4
VR3
VR4
COM62 |
COM34 -
|
|
|
|
COM33 -
VL63
VL64
VR63
VR64
COM32 -
VL65
VL66
VR65
VR66
COM31 |
COM3 -
|
|
|
|
-SEG1
VL1
COM63 -
-SEG2
COM64 -
|
-SEGI2
-SEG125
-SEG126
-SEGI3
-SEG127
-SEGI4
-SEG128
Figure 10. Relationship between Icon Pattern Data and COM / SEG Line (When DIRC = 0, DIRS = 0)
(*1)
Character Display Area
COM2 -
VL125 VL126
VR125 VR126
COM1 -
VL127 VL128
VR127 VR128
COMI1 -
H1
H2
H3
H4 -- H127
(*2)
H128
(*3)
Figure 11. Relationship between Icon Pattern Data and COM / SEG Line (When DIRC = 1, DIRS = 1)
21
KS0040
65 COM / 132 SEG DRIVER & CONTROLLER FOR STN LCD
(*3)
COMI1 -
H1
H2
H3
H4 -- H127
H128
COM1 -
VL1
VL2
VR1
VR2
COM2 -
VL3
VL4
VR3
VR4
COM3 |
COM31 -
|
|
|
|
COM32 -
VL63
VL64
VR63
VR64
COM33 -
VL65
VL66
VR65
VR66
COM34 |
COM62 -
|
|
|
|
(*1)
Character Display Area
SEGI1-
SEGI2-
SEG1-
SEG2-
~
SEG125-
SEG126-
SEG127-
VR127 VR128
SEG128-
VR125 VR126
VL127 VL128
SEGI3-
VL125 VL126
COM64 -
SEGI4-
COM63 -
(*2)
-SEGI3
-SEGI4
-SEG128
VR2
VR3
VR4
COM62 |
COM34 -
|
|
|
|
COM33 -
VL63
VL64
VR63
VR64
COM32 -
VL65
VL66
VR65
VR66
COM31 |
COM3 -
|
|
|
|
(*1)
COM2 -
VL125 VL126
COM1 -
VL127 VL128
COMI1 -
|
VR1
VL4
-SEG4
VL2
VL3
-SEG3
VL1
COM63 -
-SEG2
-SEGI2
COM64 -
-SEG1
-SEGI1
-SEG127
Figure 12. Relationship between Icon Pattern Data and COM / SEG Line (When DIRC = 0, DIRS = 1)
Character Display Area
(*2)
VR125 VR126
VR127 VR128
H1
H2
H3
H4 -- H127
H128
(*3)
Figure 13. Relationship between Icon Pattern Data and COM / SEG Line (When DIRC = 1, DIRS = 0)
22
65 COM / 132 SEG DRIVER & CONTROLLER FOR STN LCD
KS0040
CHARACTER GENERATOR ROM FOR A FULL-SIZE FONT (FCGROM)
FCGROM generates 16 x 16 characters pattern from Character Generate code in DDRAM. FCGROM has 16 X
16-dot 8,160 character pattern include cursor position for Asian language character font (like Chinese, Japanese
Kanji, Korean). If the data in cursor position bit are high, the data are included to the character pattern. So, the
selected positions are always ON without regard to cursor position.
CHARACTER GENERATOR ROM FOR A HALF-SIZE FONT (HCGROM)
HCGROM generates 8 x 16 characters pattern from Character Generate code in DDRAM. HCGROM has 8 X 16dot 128 character pattern include cursor position for half-size font (like alphanumeric characters and symbols). If
the data in cursor position bit are high, the data are included to the character pattern. So, the selected positions
are always ON without regard to cursor position.
Table 10. Relationship between CGROM Address and Font Pattern (KS0040-00 Font)
FCGROM address
A13 ~ A0
0380(h)
Font data (D15 ~ D0)
FEFCBA9876543210
HCGROM address
A6 ~ A0
Font data (D7 ~ D0)
76543210
41(h)
23
KS0040
65 COM / 132 SEG DRIVER & CONTROLLER FOR STN LCD
Table 11. KS0040-00 Font (KSC5601 Code) Map
24
KSC5601 code
KS0040 FCGROM code
Font data
-
0000 (H) ~ 001F (H)
CGRAM font area
A1A1 (H) ~ ACFE (H)
0020 (H) ~ 037F (H)
Symbol character area
B0A1 (H) ~ B0FE (H)
B1A1 (H) ~ B1FE (H)
B2A1 (H) ~ B2FE (H)
B3A1 (H) ~ B3FE (H)
B4A1 (H) ~ B4FE (H)
B5A1 (H) ~ B5FE (H)
B6A1 (H) ~ B6FE (H)
B7A1 (H) ~ B7FE (H)
B8A1 (H) ~ B8FE (H)
B9A1 (H) ~ B9FE (H)
BAA1 (H) ~ BAFE (H)
BBA1 (H) ~ BBFE (H)
BCA1 (H) ~ BCFE (H)
BDA1 (H) ~ BDFE (H)
BEA1 (H) ~ BEFE (H)
BFA1 (H) ~ BFFE (H)
C0A1 (H) ~ C0FE (H)
C1A1 (H) ~ C1FE (H)
C2A1 (H) ~ C2FE (H)
C3A1 (H) ~ C3FE (H)
C4A1 (H) ~ C4FE (H)
C5A1 (H) ~ C5FE (H)
C6A1 (H) ~ C6FE (H)
C7A1 (H) ~ C7FE (H)
C8A1 (H) ~ C8FE (H)
CAA1 (H) ~ CAFÉ (H)
CBA1 (H) ~ CBFE (H)
CCA1 (H) ~ CCFE (H)
CDA1 (H) ~ CDFE (H)
CEA1 (H) ~ CEFE (H)
CFA1 (H) ~ CFFE (H)
D0A1 (H) ~ D0FE (H)
D1A1 (H) ~ D1FE (H)
D2A1 (H) ~ D2FE (H)
D3A1 (H) ~ D3FE (H)
D4A1 (H) ~ D4FE (H)
D5A1 (H) ~ D5FE (H)
D6A1 (H) ~ D6FE (H)
D7A1 (H) ~ D7FE (H)
D8A1 (H) ~ D8FE (H)
D9A1 (H) ~ D9FE (H)
DAA1 (H) ~ DAFE (H)
DBA1 (H) ~ DBFE (H)
DCA1 (H) ~ DCFE (H)
DDA1 (H) ~ DDFE (H)
0380 (H) ~ 03DD (H)
03DE (H) ~ 043B (H)
043C (H) ~ 0499 (H)
049A (H) ~ 04F7 (H)
04F8 (H) ~ 0555 (H)
0556 (H) ~ 05B3 (H)
05B4 (H) ~ 0611 (H)
0612 (H) ~ 066F (H)
0670 (H) ~ 06CD (H)
06CE (H) ~ 072B (H)
072C (H) ~ 0789 (H)
078A (H) ~ 07E7 (H)
07E8 (H) ~ 0845 (H)
0846 (H) ~ 08A3 (H)
08A4 (H) ~ 0901 (H)
0902 (H) ~ 095F (H)
0960 (H) ~ 09BD (H)
09BC (H) ~ 0A1B (H)
0A1C (H) ~ 0A7C (H)
0A7D (H) ~ 0AD7 (H)
0AD8 (H) ~ 0B35 (H)
0B36 (H) ~ 0B93 (H)
0B94 (H) ~ 0BF1 (H)
0BF2 (H) ~ 0C4F (H)
0C50 (H) ~ 0CAD (H)
0CB0 (H) ~ 0D0D (H)
0D0E (H) ~ 0D6B (H)
0D6C (H) ~ 0DC9 (H)
0DCA (H) ~ 0E27 (H)
0E28 (H) ~ 0E85 (H)
0E86 (H) ~ 0EE3 (H)
0EE4 (H) ~ 0F41 (H)
0F42 (H) ~ 0F9F (H)
0FA0 (H) ~ 0FFD (H)
0FFE (H) ~ 105B (H)
105C (H) ~ 10B9 (H)
10BA (H) ~ 1117 (H)
1118 (H) ~ 1175 (H)
1176 (H) ~ 11D3 (H)
11D4 (H) ~ 1231 (H)
1232 (H) ~ 128F (H)
1290 (H) ~ 12FD (H)
12EE (H) ~ 134B (H)
134C (H) ~ 13A9 (H)
13AA (H) ~ 1407 (H)
65 COM / 132 SEG DRIVER & CONTROLLER FOR STN LCD
KS0040
Table 11. KS0040F00 Font (KSC5601 Code) Map (Continued)
KSC5601 code
KS0040 FCGROM code
DEA1 (H) ~ DEFE (H)
DFA1 (H) ~ DFFE (H)
E0A1 (H) ~ E0FE (H)
E1A1 (H) ~ E1FE (H)
E2A1 (H) ~ E2FE (H)
E3A1 (H) ~ E3FE (H)
E4A1 (H) ~ E4FE (H)
E5A1 (H) ~ E5FE (H)
E6A1 (H) ~ E6FE (H)
E7A1 (H) ~ E7FE (H)
E8A1 (H) ~ E8FE (H)
E9A1 (H) ~ E9FE (H)
EAA1 (H) ~ EAFE (H)
EBA1 (H) ~ EBFE (H)
ECA1 (H) ~ ECFE (H)
EDA1 (H) ~ EDFE (H)
EEA1 (H) ~ EEFE (H)
EEA1 (H) ~ EFFE (H)
F0A1 (H) ~ F0FE (H)
F1A1 (H) ~ F1FE (H)
F2A1 (H) ~ F2FE (H)
F3A1 (H) ~ F3FE (H)
F4A1 (H) ~ F4FE (H)
F5A1 (H) ~ F5FE (H)
F6A1 (H) ~ F6FE (H)
F7A1 (H) ~ F7FE (H)
F8A1 (H) ~ F8FE (H)
F9A1 (H) ~ F9FE (H)
FAA1 (H) ~ FAFE (H)
FBA1 (H) ~ FBFE (H)
FCA1 (H) ~ FCFE (H)
FDA1 (H) ~ FDFE (H)
1408 (H) ~ 1465 (H)
1466 (H) ~ 14C3 (H)
14C4 (H) ~ 1521 (H)
1522 (H) ~ 157F (H)
1580 (H) ~ 15DD (H)
15DE (H) ~ 163B (H)
163C (H) ~ 1699 (H)
169A (H) ~ 16F7 (H)
16F8 (H) ~ 1755 (H)
1756 (H) ~ 17B3 (H)
17B4 (H) ~ 1811 (H)
1812 (H) ~ 186F (H)
1870 (H) ~ 18CD (H)
18CE (H) ~ 192B (H)
192C (H) ~ 1989 (H)
198A (H) ~ 19E7 (H)
19E8 (H) ~ 1A45 (H)
1A46 (H) ~ 1AA3 (H)
1AA4 (H) ~ 1B01 (H)
1B02 (H) ~ 1B5F (H)
1B60 (H) ~ 1BBD (H)
1BBE (H) ~ 1C1B (H)
1C1C (H) ~ 1C79 (H)
1C7A (H) ~ 1CD7 (H)
1CD8 (H) ~ 1D35 (H)
1D36 (H) ~ 1D93 (H)
1D94 (H) ~ 1DF1 (H)
1DF2 (H) ~ 1E4F (H)
1E50 (H) ~ 1EAD (H)
1EAE (H) ~ 1F0B (H)
1F0C (H) ~ 1F69 (H)
1F6A (H) ~ 1FC7 (H)
Font data
25
KS0040
65 COM / 132 SEG DRIVER & CONTROLLER FOR STN LCD
LOW POWER CONSUMPTION MODE
KS0040 has sleep mode for saving power consumption during standby period. (refer to "INITIALIZING & POWER
SAVE MODE SETUP")
Sleep Mode
In the Sleep Mode, the power circuit and the oscillation circuit are turned OFF. This mode helps to save power
consumption by reducing current to almost resting current level.
1. Liquid Crystal Display Output
COM1 to COM64, COMI1, 2: VSS level
SEG1 to SEG128, SEGI1, 2, 3, 4: VSS level
2. DDRAM, CGRAM, ICONRAM and register written information are saved.
3. Operation mode is retained the same as it was prior to execution of the sleep mode.
All internal circuits are stopped.
4. Power Circuit and Oscillation Circuit
The built-in supply circuit and the oscillation circuit are turned OFF automatically by using the sleep command.
LCD DRIVING CIRCUIT
LCD Driver circuit has 65 common and 132 segment signals for LCD driving. The data from CGROM / CGRAM /
ICONRAM is transferred to 128-bit segment latch serially by 8-bits unit, and then it is stored to 128-bit shift latch.
The data from ICONRAM is stored to 4-bit latch. When each common line is selected by 65-bit common register,
segment data and segment icon data also output through segment driver from 128-bit segment latch and 4-bit
segment icon latch. KS0040 has common and segment bi-directional function to help various panel applications.
(refer to table 12 and table 13)
Table 12. SEG Data Shift Direction
DIRS
SEG data shift direction
→ - - - - - - - → SEG128, SEGI3, SEGI4
Low
SEGI1, SEGI2, SEG1
High
SEGI4, SEGI3, SEG128 → - - - - - - - → SEG1, SEGI2, SEGI1
Table 13. COM Data Shift Direction
26
Duty
DIRC
COM data shift direction
1/17
Low
COM1 → - - - - - - - → COM16, COMI1 (COMI2)
(1-line mode)
High
COM16 → - - - - - - - → COM1, COMI1 (COMI2)
1/33
Low
COM1 → - - - - - - - → COM32, COMI1 (COMI2)
(2-line mode)
High
COM32 → - - - - - - - → COM1, COMI1 (COMI2)
1/49
Low
COM1 → - - - - - - - → COM48, COMI1 (COMI2)
(3-line mode)
High
COM48 → - - - - - - - → COM1, COMI1 (COMI2)
1/65
Low
COM1 → - - - - - - - → COM64, COMI1 (COMI2)
(4-line mode)
High
COM64 → - - - - - - - → COM1, COMI1 (COMI2)
65 COM / 132 SEG DRIVER & CONTROLLER FOR STN LCD
KS0040
DISPLAY SHIFT CONTROL
KS0040 has vertical dot-by-dot or character-by-character shift function, which are usable when display panel size
is less than 4-line display and want to display the hidden-line data, or when extended DDRAM is set and want to
display extended DDRAM data
Display Home State
After 1st Dot-By-Dot
Shift-up
After 2nd Dot-By-Dot
Shift-up
After 4th Dot-By-Dot
Shift-up
After 16th Dot-By-Dot
Shift-up
Figure 14. Vertical Dot-by-Dot Shift-up (down) Example
27
KS0040
65 COM / 132 SEG DRIVER & CONTROLLER FOR STN LCD
INSTRUCTION DESCRIPTION
Outline
To overcome the speed difference between internal clock of KS0040 and MPU clock, KS0040 performs internal
operation by storing control information to IR or DR. The internal operation is determined according to the signal
from MPU, composed of read / write and data bus.
Instruction can be divided four kinds,
(1) System register set instructions (power control, contrast value set, etc.)
(2) Internal RAM access instructions (RAM select, RAM address set, data read / write, etc.)
(3) Display control instructions (vertical shift, double height character, etc.)
(4) Others
The address of internal RAM is automatically increased or decreased by 1.
NOTE: Every instruction takes one cycle execution time, so to execute the next instruction, minimum E cycle time (tc) must
be kept.
28
65 COM / 132 SEG DRIVER & CONTROLLER FOR STN LCD
KS0040
Table 14. Instruction table
Instruction code
Instruction
Description
RS DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
NOP
0
0 (Hex)
0
0
0
0
No operation
Return home
0
1 (Hex)
-
-
-
-
Set DDRAM address to "00H" from AC and
return cursor to its original position if shifted.
The contents of DDRAM are not changed
Display control
0
2 (Hex)
D
CC
Display (D), character cursor (CC), line
LC REV cursor (LC), B/W reverse display (REV)
ON / OFF control
Power save mode
0
3 (Hex)
-
-
-
SLP Sleep mode (SLP) ON / OFF control
Contrast increment
/ decrement
0
4 (Hex)
-
-
-
CID
Contrast increment (CID = 1) or
decrement (CID = 0)
Vertical shift
0
5 (Hex)
-
-
CD
UD
Vertical character (CD = 1), dot (CD = 0)
shift -up (UD = 1), down (UD = 0)
Double height
character
0
6 (Hex)
-
EN DH1 DH0
Double height character enable (EN) at
selected line (DH1, DH0).
R3 R2 R1 R0 Selected RAM / register
RAM select /
system register set
0
7 (Hex)
R3
R2
R1
R0
0 0 0 0
0 0 0 1
1 0 0 0
1 1 1 1
DDRAM
ICONRAM
CGRAM page 0
CGRAM page 7
0
0
0
0
Power control register
Contrast control register
Environment control register
Function control register
1
1
1
1
0
0
1
1
0
1
0
1
DD / CG / ICON RAM address setting, one
RAM address set
0
1
AC6 AC5 AC4 AC3 AC2 AC1 AC0 of 3 RAM is selected by RAM select
instruction.
Write data
1
D7
D6
D5
D4
D3
D2
D1
D0
DD / CG / ICON RAM and system register
data write
Read data
1
D7
D6
D5
D4
D3
D2
D1
D0
DD / CG / ICON RAM and system register
data read
NOTE: "-" - Don’t care
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65 COM / 132 SEG DRIVER & CONTROLLER FOR STN LCD
Table 15. System Register Values
Register select bit
Selected system register
R3
R2
R1
R0
0
1
0
0
*1) Power control register
0
1
0
1
0
1
1
0
1
1
Register value map
DB7
DB6
DB5
DB4
OSC
VC
VR
VF
*2) Contrast control register
-
-
C5
C4
0
*3) Environment control register
-
-
DT1
1
*4) Function control register
-
-
-
DB3
DB2
DB1
DB0
INTR RR2
RR1
RR0
C1
C0
C3
C2
DT0 DIRC DIRS EXT
ID
FG
B0
CM
FL1
B1
NOTE: "-" - Don’t care
*1) OSC: internal oscillator ON (OSC = 1), OFF (OSC = 0) control bit
VC: voltage converter ON (VC = 1), OFF (VF = 1) control bit
VR: voltage regulator ON (VR = 1), OFF (VR = 0) control bit
VF: voltage follower ON (VF = 1), OFF (VF = 0) control bit
INTR: use the internal voltage regulating resisters ON (INTR = 1), OFF (INTR = 0) control bit
RR2 to RR0: internal voltage adjusting resisters set control register bits (refer to table 18)
*2) C5 to C0: electronic contrast control register bits. (refer to figure 21)
*3) DT1, DT0: duty select bits (refer to table 15)
DIRC, DIRS: common data direction (DIRC), segment data direction (DIRS) select bit (refer to table 12 and table 13)
EXT: DDRAM extended mode ON (EXT = 1), OFF (EXT = 0) control bit
ID: DDRAM / CGRAM / ICONRAM address increment (ID = 1), decrement (ID = 0) control bit
*4) FG: CGRAM full graphic mode ON (FG = 1), OFF (FG = 0) control bit
CM: center display mode ON (CM = 1), OFF (CM = 0) control bit
FL1: first line fix mode ON (FL1 = 1), OFF (FL1 = 0) control, during vertical shift
B1, B0: cursor attribute control bit
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65 COM / 132 SEG DRIVER & CONTROLLER FOR STN LCD
KS0040
Return Home
RS
DB7
DB6
DB5
DB4
DB3
DB2
DB1
DB0
0
0
0
0
1
Set DDRAM address to "00h" into the address counter. If the display position has shifted, it return to the original
positions. When cursor or blinking is displayed on, bring the cursor to the left edge on first line of the display. The
data in DDRAM does not change.
Display Control
RS
DB7
DB6
0
0
0
Display control bit ON / OFF instruction
DB5
DB4
DB3
DB2
DB1
DB0
1
0
D
CC
LC
REV
D: Display ON / OFF Control
When D = "High", entire display is turned ON
When D = "Low", entire display is turned OFF, but display data is remained in DDRAM (default)
CC: Character Cursor ON / OFF Control Bit
When CC = "High", character cursor is turned ON.
When CC = "Low", character cursor is disappeared in current display (default).
LC: Line Cursor ON / OFF Control Bit
When LC = "High", line cursor is turned on according to the most significant 2-bits (ADDR[6], ADDR[5]) of current
DDRAM address (ADDR [6:0]). When LC = "Low", line cursor is disappeared in current display (default)
REV: Black / White Reverse Display ON / OFF Control Bit
When REV= "High", all the display area except icon area are black / white reversed.
When REV= "Low", normal display status (default)
Power Save Mode
RS
DB7
DB6
DB5
DB4
0
0
0
1
1
Power Save mode is used to making KS0040 sleep mode.
DB3
DB2
DB1
DB0
-
-
-
SLP
SLP: Sleep Mode ON / OFF Control Bit
When SLP = "High", sleep mode is set (default).
When SLP = "Low", sleep mode is reset.
(refer to "LOW POWER CONSUMPTION MODE" and "INITIALIZING & POWER SAVE MODE SETUP")
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65 COM / 132 SEG DRIVER & CONTROLLER FOR STN LCD
Contrast Increment / Decrement
RS
DB7
DB6
DB5
DB4
0
0
1
0
0
Contrast control register value increment / decrement instruction
DB3
DB2
DB1
DB0
-
-
-
CID
DB3
DB2
DB1
DB0
-
CD
UD
CID: Contrast Increment / Decrement Enable Bit
When CID = “High”: contrast register value increased by 1 until 63.
When CID = “Low”: contrast register value decreased by 1 until 0.
Vertical Shift-up / down
RS
DB7
DB6
DB5
DB4
0
0
1
0
1
Vertical dot-by-dot display shift-up / down instruction (refer to figure 14, 16)
CD: Character / Dot Shift Select Bit
When CD = "High": display shift-up / down by character is selected (It’s the same as 16-time dot shift).
When CD = "Low": display shift-up / down by dot is selected.
UD: Vertical Display Shift Direction Select
When UD = "High": display shift-up is performed.
When UD = "Low": display shift-down is performed.
Double Height Character
RS
DB7
DB6
DB5
0
0
1
1
Double height character instruction (refer to figure 15)
DB4
DB3
DB2
DB1
DB0
0
-
EN
DH1
DH0
EN: Double Height Character Mode Enable Bit
When EN = "High": double height character mode is enabled.
When EN = "Low": double height character mode is disabled (default).
DH1, DH0: Double Height Character Line Select
When [DH1, DH0] = [Low, Low]: 1, 2-line becomes double height character
= [Low, High]: 2, 3-line becomes double height character
= [High, Low]: 3, 4-line becomes double height character
= [High, High]: 1 to 4-line becomes double height character
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65 COM / 132 SEG DRIVER & CONTROLLER FOR STN LCD
KS0040
RAM Select / System Register Set
RS
DB7
DB6
DB5
DB4
DB3
DB2
DB1
DB0
0
0
1
1
1
R3
R2
R1
R0
RAM selection (DDRAM / CGRAM / ICONRAM) or system register set instruction. R3 / R2 / R1 / R0: RAM or
system register selection bits
Select bits
Data length / value map
Selected RAM or registers
R3 R2 R1 R0
DB7
DB6
DB5
DB4
DB3
DB2
DB1
DB0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
DDRAM
ICONRAM
CGRAM page0
CGRAM page1
CGRAM page2
CGRAM page3
CGRAM page4
CGRAM page5
CGRAM page6
CGRAM page7
Power control register
Contrast control register
Environment control register
Function control register
1-byte (half-size font) 2-byte (full-size font)
1-byte
2-byte
2-byte
2-byte
2-byte
2-byte
2-byte
2-byte
2-byte
OSC VC
VR
VF
INTR RR2
C5
C4
C3
C2
DT1
DT0
DIRC DIRS
FG
CM
FL1
RR1
C1
EXT
B1
RR0
C0
ID
B0
NOTE: "-" - Don’t care
For writing 2-byte data into RAM, data write instruction must be performed twice.
OSC: oscillator circuit ON (OSC = "High"), OFF (OSC = "Low": default) control
VC / VR / VF: voltage converter / regulator / follower circuit ON (VC / VR / VF = "High"), OFF (VC / VR / VF =
"Low": default) control
INTR: Use the internal voltage regulating resistors on (INTR = "High"), off (INTR = "Low": default) control bit
RR2~RR0: internal voltage adjusting resistors set control register bits ([0,0,0]: default). (refer to table 18)
C5 to C0: electronic contrast control register ([0, 0, 0, 0, 0, 0]: default) (refer to figure 21)
DT1, DT0: duty select register ([1, 1]: default) (refer to table 18)
DIRC, DIRS: common data shift direction (DIRC), segment data shift direction (DIRS) flag register ([0, 0]: default)
(refer to table 12 and table 13)
EXT: DDRAM extended mode ON (EXT = "High"), OFF (EXT = "Low": default) control
ID: RAM address increment (ID = "High": default), decrement (ID = "Low") mode set
FG: CGRAM full graphic mode ON / OFF control register (FG = "Low": default). (refer to figure 18)
CM: center display mode ON / OFF control register (CM = "Low": default). (refer to figure 17)
FL1: first line fix mode, during vertical scroll instruction, ON / OFF control register (FL1 = "Low": default).
(refer to figure 16)
B1, B0: character / line cursor attribute select register ([0, 0]: default) (refer to table 17)
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65 COM / 132 SEG DRIVER & CONTROLLER FOR STN LCD
RAM Address Set
RS
DB7
DB6
DB5
DB4
DB3
DB2
DB1
DB0
0
1
AC6
AC5
AC4
AC3
AC2
AC1
AC0
DDRAM / CGRAM / ICONRAM address set instruction. Each RAM is selected by RAM select instruction.
Write Data
RS
DB7
DB6
DB5
DB4
DB3
DB2
DB1
DB0
1
D7
D6
D5
D4
D3
D2
D1
D0
DDRAM / CGRAM / ICONRAM data or system register value write instruction. Each RAM and system register is
selected by RAM select / system register set instruction. After write operation, the address is increased/decreased
by 1 automatically, according to function control register set. When writing full-size character address in FCGROM
to DDRAM, RAM data write instruction must be written twice, because the FCGROM address is 13-bits long.
(refer to figure 15)
Read Data (8-bit Bus Mode MPU Interface only)
RS
DB7
DB6
DB5
DB4
DB3
DB2
DB1
DB0
1
D7
D6
D5
D4
D3
D2
D1
D0
DDRAM / CGRAM / ICONRAM data or system register value read instruction. Each RAM and system register is
selected by RAM select / system register set instruction. If you read RAM data after RAM address set instruction,
you can get correct RAM data from the second. The first data would be incorrect, because there is no timing
margin for transfer RAM data to output register. After write or read operation, the address is increased/decreased
by 1 automatically, according to function control register set. When reading full size character address in
FCGROM from DDRAM, RAM data read instruction must be executed twice, because the FCGROM address is
13-bits long. (refer to figure 15)
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65 COM / 132 SEG DRIVER & CONTROLLER FOR STN LCD
KS0040
Full-size Character Code (FCGROM / CGRAM Address + Attribute)
0
[A1]
[A0]
C12
Full-size
Display
Character Attribute Code
C7
C6
C5
C11
C10
C9
C8
Upper Character Code
C4
C3
C2
C1
C0
C1
C0
Lower Character Code
Half-size Character Code (HCGROM Address)
1
C6
C5
C4
C3
C2
Character Code
Half-size
Character
Figure 15. DDRAM Data (FCGROM / HCGROM / CGRAM Address) Format
Table 16. Display Attributes
[A1] [A0]
Display state (when cursor / blink OFF)
0
0
Normal display
0
1
B/W reversed display
1
0
Character blink mode 1
1
1
Character blink mode 2
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65 COM / 132 SEG DRIVER & CONTROLLER FOR STN LCD
Table 17 Cursor Attributes
[B1] [B0]
Display state (at cursor position)
0
0
Underline cursor
0
1
B/W reverse cursor
1
0
Blink cursor 1
1
1
Blink cursor 2
Table 18. The Relationship between Duty and Environment Set
DT1 DT0
36
Duty
Bias
fosc (kHz)
Display line number
0
0
1/17
1/5
24.5
1-line display
0
1
1/33
1/7
47.6
2-line display
1
0
1/49
1/8
68.3
3-line display
1
1
1/65
1/9
93.7
4-line display
65 COM / 132 SEG DRIVER & CONTROLLER FOR STN LCD
KS0040
Normal Display
l Line Cursor (LC) OFF
l First Line Fix Mode (FL1) OFF
l Vertical Shift OFF
Normal Display & Line Cursor
l Line Cursor (LC) ON (B1, B0 = [0, 1])
l First Line Fix Mode (FL1) OFF
l Vertical Shift OFF
Vertical Shifted Display
(in First Line Fix Mode)
Line Cursor (LC) ON (B1, B0 = [0, 1])
l First Line Fix Mode (FL1) ON
l Vertical Shift-up by Dot 6 times
Vertical Shifted Display
(in First Line Fix Mode )
l Line Cursor (LC) ON (B1,B0 = [0, 1])
l First Line Fix Mode (FL1) ON
l Vertical Shift Up by Dot 16 times
or Vertical Shift-up by Character once
Figure 16. The Examples of Vertical Shift and First Line Fix Mode
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65 COM / 132 SEG DRIVER & CONTROLLER FOR STN LCD
(a) DH1, DH0 = [0, 0]
(b) DH1, DH0 = [0, 1]
(c) DH1, DH0 = [1, 0]
(d) DH1, DH0 = [1, 1]
(e) DH1, DH0 = [0, 0] and Center Mode ON (CM = 1), When 3-line Display
Figure 17. The Examples of Double Height Character Display
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65 COM / 132 SEG DRIVER & CONTROLLER FOR STN LCD
KS0040
Figure 18. The Examples of Full Graphic Mode Display (FG = 1)
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65 COM / 132 SEG DRIVER & CONTROLLER FOR STN LCD
INITIALIZING & POWER SAVE MODE SETUP
HARDWARE RESET
When RESET pin = "Active (rising or falling)", KS0040 can be initialized the following state.
Return Home
Address counter = 00H
Control Display ON / OFF Instruction
D = 0: display OFF
CC, LC = [0, 0]: character / line cursor OFF
REV = 0: reverse display OFF (normal display)
Power Save Mode Instruction
SLP = 1: sleep mode ON
RAM Select Instruction
R3 to R0 = [0, 0, 0, 0]: DDRAM is selected.
System Register Set Instruction
OSC = 0: oscillator OFF
VC, VR, VF = [0, 0, 0]: voltage converter / regulator / follower OFF
INTR = 0: internal voltage regulating resister OFF
RR2 to RR0 = [0, 0, 0]: Internal voltage adjusting resistors set control register value are set to 000.
C5 to C0= [0, 0, 0, 0, 0, 0]: Electronic contrast control register values are set to 00H.
DT1, DT0 = [1, 1]: 4-line display mode
DIRC = 0: normal direction of common outputs (COM1 to COM64, COMI1 (COMI2))
DIRS = 0: normal direction of segment outputs (SEGI1, SEGI2, SEG1 to SEG128, SEGI3, SEGI4)
EXT = 0: Normal DDRAM mode is selected.
ID = 1: RAM address increment condition
FG = 0: CGRAM full graphic mode OFF
CM = 0: center display mode OFF
FL1 = 0: first line fix mode OFF
B1, B0 = [0, 0]: under line cursor attribute is selected.
NOTE: If initialization is not done by RESET pin, unstable condition might result. So, for initializing the RESET input pin must
be active at first.
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65 COM / 132 SEG DRIVER & CONTROLLER FOR STN LCD
VDD
KS0040
VDD=2.4V
tRESETB
tRW
tR
RESET
Internal Reset Time
Reset Start Time
Reset Pulse Width
Reset Time
tRESETB
tRW
tR
50ns
1.0µs
1.0µs
Figure 19. Reset Timing
NOTE: tRW indicates the minimum RESET duration for activating internal reset signal.
tR indicates reset completion time of internal circuit from the edge of the internal reset signal.
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65 COM / 132 SEG DRIVER & CONTROLLER FOR STN LCD
INITIALIZING BY INSTRUCTION
VDD-VSS Power ON
Power Regulation
Input of Reset Signal
Command Status
Initializing by Hardware Reset Input
Status
Waiting for 10µ sec or more
Command Input
(1) Power Save Set Command
SLP = OFF (Sleep Mode OFF)
(2) System Register Set Command
a. Environment Register Value Set
(DT1, DT0, DIRC, DIRS, EXT, ID)
b. Function Control Register Value Set
(FG, CM, FL1, B1, B0)
c. Internal Voltage Adjusting Resistors
Set Control Register set (RR2~RR0)
d. Contrast Control Register Value Set
(C5 to C0)
e. Power Control Register Value Set
(OSC→VC→VR (INTR)→VF: ON)
(3) RAM Address Set Command
(4) Data Writing (RAM Clear)
(DDRAM = A0H, CG/ ICONRAM = 00H)
Waiting for 20msec or more
Command Input
(5) Display Control Commands
D: ON
End of Initialization
Input of RAM Address Setup Command
Input of RAM (Data) Write Command
Display of Written Data
42
NOTE: Commands (3) and (4) initialize the RAM.
The non-display area must satisfy the following conditions
(for RAM clear).
DDRAM: Write the A0H data. (Half character flag "1" and
space character code "20H": "1" "0100000")
CGRAM: Write the 00H data (blank data)
ICONRAM: Write the 00H data (off data)
As the RAM data is unstable during reset signal input (after
power ON), blank data must be written. If not, unexpected
display may result.
65 COM / 132 SEG DRIVER & CONTROLLER FOR STN LCD
KS0040
SLEEP MODE SET OR RELEASE BY INSTRUCTION
Sleep Mode Setting
End of Initialization
Command Status
Initializing by Instruction Setup Input
Status
Normal Operation Status
Internal voltage regulating resistor control bit (INTR)
and voltage adjusting resistors set control register
bits (RR2 - RR0) are not changed in sleep mode.
Command Input
(1) Display ON / OFF Control Command
D = OFF (Display OFF)
(2) Power Save Set Command
SLP = ON (Power Save ON)
*OSC, VC, VR, VF are automatically
OFF.
Enter the Sleep Mode
Sleep Mode Releasing
End of Initialization
Command Input
(1) Power Save Set Command
SLP = OFF (Sleep Mode OFF)
(2) System Register Set Command
(Power Control Register Set)
* OSC→VC→VR→VF: ON
Waiting for 20 ms or more
(3) Display Control Command
D = ON (Display ON)
Return to Normal Operation
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65 COM / 132 SEG DRIVER & CONTROLLER FOR STN LCD
RECOMMENDATION OF POWER ON / OFF SEQUENCE
Power ON Sequence (Power Control Register Set)
VDD - VSS Power ON
Oscillator ON
[OSC, VC, VR, VF = 1, 0, 0, 0]
Waiting for ≥ 1ms
Voltage Converter ON
[OSC, VC, VR, VF = 1, 1, 0, 0]
Waiting for ≥ 1ms
Voltage Regulator ON
[OSC, VC, VR, VF = 1, 1, 1, 0]
Waiting for ≥ 1ms
Voltage Follower ON
[OSC, VC, VR, VF = 1, 1, 1, 1]
Power OFF Sequence
Display OFF
Waiting for ≥ 50ms
Voltage Regulator OFF
[OSC, VC, VR, VF = 1, 1, 0, 1]
Waiting for ≥ 1ms
Voltage Follower OFF
[OSC, VC, VR, VF = 1, 1, 0, 0]
Waiting for ≥ 1ms
Voltage Converter OFF
[OSC, VC, VR, VF = 1, 0, 0, 0]
Waiting for ≥ 1ms
VDD-VSS Power OFF
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65 COM / 132 SEG DRIVER & CONTROLLER FOR STN LCD
KS0040
LCD DRIVING POWER SUPPLY CIRCUIT
This Power Supply circuit generating voltages to drive LCD consists of voltage converter, voltage regulator, and
voltage follower. Voltage converter boosts up logic voltage (VDD) 2, 3 and 4 times and this boosted voltage (VOUT)
is delivered to the voltage regulator. Voltage regulator adjusts V0 between VOUT and VSS and this adjusted
voltage is sent to the voltage follower. VLCD voltage (V0) is resistively divided into four voltage levels (V1, V2, V3
and V4) and those output impedance are converted by the voltage follower for increasing drive capability. Power
Supply circuit is controlled by the Power Control instruction. There can be eight combination states according to
instruction sets (VC, Vr and VF). Table 19 shows useful combinations which are recommended, and the
remaining combination states are impractical, not recommended to be used.
Table 19. Recommended Power Supply Combination
VC VR VF
Voltage
converter
Voltage
regulator
Voltage
follower
VOUT
VO,VR
V1, V2, V3, V4
1 1 1
Enable
Enable
Enable
Internal voltage
output
Used for voltage
adjustment
Internal voltage
output
0 1 1
Disable
Enable
Enable
External voltage
input
Used for voltage
adjustment
Internal voltage
output
0 0 1
Disable
Disable
Enable
Open
VO: External
voltage input
VR: open
Internal voltage
output
0 0 0
Disable
Disable
Disable
Open
VO: External
voltage input
VR: open
External voltage
input
NOTE: SEC recommendation is to use only the case listed above table.
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65 COM / 132 SEG DRIVER & CONTROLLER FOR STN LCD
VOLTAGE CONVERTER
This circuit boosts up the electric potential between VDD and VSS to 2, 3 or 4 times toward positive side and
boosted voltage come out through VOUT terminal.
VDD
VDD
C1
VOUT
CAP3+
CAP3CAP2+
CAP2C1
VOUT = 2 x VDD
CAP1+
VDD
CAP1-
VSS
VSS
GND
* Recommended Capacitance value is 1µF
Figure 20. Two Times Boosting
VDD
VDD
C1
VOUT
CAP3+
CAP3C1
C1
VOUT = 3 x VDD
CAP2+
CAP2CAP1+
VDD
CAP1VSS
VSS
GND
* Recommended Capacitance value is 1µF
Figure 21. Three Times Boosting
46
65 COM / 132 SEG DRIVER & CONTROLLER FOR STN LCD
KS0040
VDD
VDD
C1
VOUT
C1
C1
CAP3+
VOUT = 4 x VDD
CAP3CAP2+
CAP2-
C1
CAP1+
VDD
CAP1VSS
VSS
GND
* Recommended Capacitance value is 1µF
Figure 22. Four Times Boosting
47
KS0040
65 COM / 132 SEG DRIVER & CONTROLLER FOR STN LCD
VOLTAGE REGULATOR
The boosting voltage occurring at VOUT is sent to the voltage regulator. The Voltage Regulator determines V0
LCD driver voltage by adjusting resistor Ra and Rb within the range of |V0| < |VOUT|. This V0 is determined by
equation (1), where Ra and Rb are internal or external resistors and VREF is determined by equation (2) as the
voltage source of the IC. The electric potential of VREF is set to one of 64 levels by setting 6-bit reference voltage
register.
Rb
V0 = (1 +  ) x VEV [V]
Ra
------ (1)
(63 - α)
VEV = (1 -  ) x Vs [V]
300
------- (2)
where α = value of 6-bit reference voltage register (0 to 63)
when REF = "High", Vs = VDD
REF = "Low", Vs = VREF (internal reference voltage) = 2V
Rb
VDD
VOUT
VR
Ra
VS
REF
VEV +
VREF
+
Inside Chip
VSS
GND
Figure 23. Voltage Regulator Circuit
48
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65 COM / 132 SEG DRIVER & CONTROLLER FOR STN LCD
KS0040
When Using Internal Resistors, Ra and Rb (INTR = "High")
When INTR bit is set to "High", resistor Ra is connected internally between VR pin and VSS, and Rb is connected
between V0 and VR. We determine V0 by two instructions, "Regulator Resistor Select" and "Set Reference
Voltage".
Table 20. Internal Rb / Ra Ratio Depending on 3-bit Data (RR2 RR1 RR0)
3-bit data settings (RR2 RR1 RR0)
1+(Rb / Ra)
000
001
010
011
100
101
110
111
3.0
3.5
4.0
4.5
5.0
5.5
6.0
6.5
The following figure shows V0 voltage measured by adjusting internal regulator resistor ratio (Rb / Ra) and 6-bit
electronic volume registers at Ta = 25 °C (temperature coefficient = -0.05%/°C).
14.00
(1 1 1)
(1 1 0)
(1 0 1)
(1 0 0)
(0 1 1)
(0 1 0)
(0 0 1)
(0 0 0)
12.00
10.00
V0 8.00
[V] 6.00
4.00
2.00
0.00
0
8
16
24
32
40
48
56
Electronic Volume Level
Figure 24. Electronic Volume Level (Temperature Coefficient = -0.05% / ° C)
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65 COM / 132 SEG DRIVER & CONTROLLER FOR STN LCD
Table 21. The Relationship between Electronic Volume Constant, α , and 6-bit
Voltage Reference Register (C5, C4, C3, C2, C1, C0)
C5
C4
C3
C2
C1
C0
α
1
1
1
1
1
1
63
1
1
1
1
1
0
62
.
.
.
.
.
.
.
.
.
.
.
.
.
.
0
0
0
0
0
1
1
0
0
0
0
0
0
0
Table 22. The Change Ratio of VREF and V0 by α is as Following Table
(REF = L, [RR2, RR1, RR0] = [1, 0, 0], Ta = 25°C)
α
V0
50
0
1
---
30
31
32
---
62
63
7.90
7.93
-
8.90
8.93
8.97
-
9.97
10.00
65 COM / 132 SEG DRIVER & CONTROLLER FOR STN LCD
KS0040
When Using External Resistors, Ra and Rb (INTR = "Low")
When INTR bit is set to "Low", it is necessary to connect external regulator resistor Ra between VR and VSS, and
Rb between V0 and VR.
Example: For the following requirements
1. LCD driver voltage, V0 = 10V
2. 6-bit reference voltage register = (1, 1, 1, 1, 1, 1)
3. Maximum current flowing Ra, Rb = 1µA
From equation (1)
Rb
V0 = 10 [V] = (1 +  ) x VREF
Ra
------ (2)
From equation (2)
0
VREF = (1 -  ) x Vs = Vs = 2V or VDD
300
where α = 63
Vs = 2V or VDD
------ (3)
From requirement 3.
10
 = 1 [µA] ------ (4)
Ra + Rb
From equations (2), (3) and (4)
A. When Vs = 2V (REF = "Low")
Ra = 2 [MΩ]
Rb = 8 [MΩ]
B. When Vs = VDD = 3V (REF = "High")
Ra = 3 [MΩ]
Rb = 7 [MΩ]
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65 COM / 132 SEG DRIVER & CONTROLLER FOR STN LCD
LCD BIAS RESISTOR & FOLLOWER
VDD
VDD
VDD
C1
C1
C1
C1
VDD
CAP1+
CAP1CAP2+
CAP2CAP3+
CAP3VOUT
CAP1+
CAP1CAP2+
CAP2CAP3+
CAP3VOUT
C1
C1
C1
C1
VR
C1
C1
C1
C1
C1
VR
V0
C1
V1
C1
R1
V2
C1
R1
C1
R2
C1
R1
V3
V4
R1
VSS
V0
V1
V2
V3
V4
VSS
GND
GND
a) When use the internal bias circuit
(VC, VR, VF, INTR = [1, 1, 1, 1])
b) When use the external bias circuit
(VC, VR, VF, INTR = [1, 1, 0, 1])
* Recommended Capacitance value is 1µF
Figure 25. LCD Bias Circuit
Table 23. Duty Select Input & Internal Bias Circuit
52
DT1
DT0
Duty
Internal bias
Low
Low
1/17
1/5
Low
High
1/33
1/7
High
Low
1/49
1/8
High
High
1/65
1/9
65 COM / 132 SEG DRIVER & CONTROLLER FOR STN LCD
KS0040
USE THE EXTERNAL POWER SUPPLY
VDD
VDD
VDD
CAP1+
CAP1CAP2+
CAP2CAP3+
CAP3VOUT
External
Power
Supply
External
Power
Supply
VDD
CAP1+
CAP1CAP2+
CAP2CAP3+
CAP3VOUT
Ra
C1
Rb
C1
C1
C1
C1
VR
VR
V0
C1
V0
V1
C1
V1
C1
V2
C1
V3
C1
V4
VSS
V2
V3
V4
VSS
GND
GND
(VC, VR, VF, INTR = [0, 1, 1, 0])
(VC, VR, VF, INTR = [0, 1, 1, 1])
VDD
External
Power
Supply
C1
C1
C1
C1
VDD
VDD
CAP1+
CAP1CAP2+
CAP2CAP3+
CAP3VOUT
VDD
CAP1+
CAP1CAP2+
CAP2CAP3+
CAP3VOUT
VR
VR
V0
V0
V1
V2
External
Power
Supply
V1
V2
V3
V3
V4
V4
VSS
VSS
GND
(VC, VR, VF, INTR = [0, 0, 1, 0])
GND
(VC, VR, VF, INTR = [0, 0, 0, 0])
* Recommended Capacitance value is 1µF
Figure 26. When External Power Supply is used
53
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65 COM / 132 SEG DRIVER & CONTROLLER FOR STN LCD
APPLICATION INFORMATION
MPU INTERFACE METHOD
Parallel Interfacing with 8080-series Microprocessors
VCC
VCC
VCC
VDD
A0
A1~A7
IORQ
DECODER
RS
CSB
MPU
PS
MI
GND
KS0040
(8080-series) RD
WR
D0-D7
E_RD
RW_WR
DB0-DB7
RESET
RESET
GND
VSS
RESETB
GND
Figure 27. 8080-series MPU Interface
Parallel Interfacing with 6800-series Microprocessors
VCC
VCC
DECODER
MPU
RS
CSB
PS
MI
KS0040
(6800 -series)
E
R/W
D0-D7
E_RD
RW_WR
DB0-DB7
RESET
GND
RESET
RESETB
VSS
GND
Figure 28. 6800-series MPU Interface
54
VCC
VDD
A0
A1~A7
VMA
65 COM / 132 SEG DRIVER & CONTROLLER FOR STN LCD
KS0040
Clock Synchronized Serial Interfacing with any Microprocessors
VCC
VCC
VDD
PORT4
PORT3
RS
CSB
PS
GND
MPU
GND
KS0040
PORT1
PORT0
SCL(DB6)
SI(DB7)
RESET
RESET
RESETB
MI
IF
VCC
or
GND
VSS
GND
Figure 29. 4-Pin Serial Interface
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65 COM / 132 SEG DRIVER & CONTROLLER FOR STN LCD
LCD PANEL CONNECTION METHOD (1/65 DUTY CONFIGURATION)
Chip Bottom & Lower View (DIRS = 0, DIRC = 0)
SEG127
SEG126
SEG125
SEG124
SEG123
SEG122
SEG121
SEG120
SEG119
SEG118
SEG117
SEG116
SEG115
SEG14
SEG13
SEG12
SEG11
SEG10
SEG9
SEG8
SEG7
SEG6
SEG5
SEG4
SEG3
SEG2
SEG1
SEGI2
SEGI1
COM56
~
COM49
COM40
~
COM33
COM24
~
COM17
COM8
~
COM1
COMI1
BOTTOM VIEW
SEGI3
SEGI4
COMI2
COM64
~
COM57
COM48
~
COM41
COM32
~
COM25
COM16
~
COM9
Figure 30. Chip Bottom & Lower View (DIRS = 0, DIRC = 0)
56
65 COM / 132 SEG DRIVER & CONTROLLER FOR STN LCD
KS0040
Chip Bottom & Upper View (DIRS = 1, DIRC = 1)
BOTTOM VIEW
SEG2
SEG3
SEG4
SEG5
SEG6
SEG7
SEG8
SEG9
SEG10
SEG11
SEG12
SEG13
SEG14
SEG115
SEG116
SEG117
SEG118
SEG119
SEG120
SEG121
SEG122
SEG123
SEG124
SEG125
SEG126
SEG127
SEG128
COM9
~
COM16
COM25
~
COM32
COM41
~
COM48
COM57
~
COM64
COMI2
SEGI4
SEGI3
COMI1
COM1
~
COM8
COM17
~
COM24
COM33
~
COM40
COM49
~
COM56
SEGI1
SEGI2
Figure 31. Chip Bottom & Lower View (DIRS = 1, DIRC = 1)
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65 COM / 132 SEG DRIVER & CONTROLLER FOR STN LCD
Chip Top & Lower View (DIRS = 1, DIRC = 0)
SEG2
SEG3
SEG4
SEG5
SEG6
SEG7
SEG8
SEG9
SEG10
SEG11
SEG12
SEG13
SEG14
SEG115
SEG116
SEG117
SEG118
SEG119
SEG120
SEG121
SEG122
SEG123
SEG124
SEG125
SEG126
SEG127
SEG128
SEGI3
SEGI4
COMI2
COM64
COM57
COM48
COM41
COM32
COM25
COM16
COM9
TOP VIEW
SEGI2
SEGI1
COM56
COM49
COM40
COM33
COM24
COM17
COM8
COM1
COMI1
Figure 32. Chip Top & Lower View (DIRS = 1, DIRC = 0)
58
65 COM / 132 SEG DRIVER & CONTROLLER FOR STN LCD
KS0040
Chip Top & Upper View (DIRS = 0, DIRC = 1)
TOP VIEW
SEG127
SEG126
SEG125
SEG124
SEG123
SEG122
SEG121
SEG120
SEG119
SEG118
SEG117
SEG116
SEG115
SEG14
SEG13
SEG12
SEG11
SEG10
SEG9
SEG8
SEG7
SEG6
SEG5
SEG4
SEG3
SEG2
SEG1
COMI1
COM1
COM8
COM17
COM24
COM33
COM40
COM49
COM56
SEGI1
SEGI2
COM9
COM16
COM25
COM32
COM41
COM48
COM57
COM64
COMI2
SEGI4
SEGI3
Figure 33. Chip Top & Lower View (DIRS = 0, DIRC = 1)
59
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65 COM / 132 SEG DRIVER & CONTROLLER FOR STN LCD
FRAME FREQUENCY
1/17 Duty (DT1, DT0 = [0, 0])
1-line Selection Period
1 2
ŸŸŸ
16 17 1 2
ŸŸŸ
16 17 1 2
ŸŸŸ
16 17 1 2
ŸŸŸ
16 17
V0
V1
COM1
V4
VS
1 FRAME
1 FRAME
1-line Selection Period = 17 Clock Pulses
One Frame
= 17 x 17 x 40.8µs = 11.8ms (1 Clock=40.8µs at fosc=24.5kHz)
Frame Frequency
= 1 / 11.8ms = 85Hz
Figure 34. Frame Frequency (1/17 Duty)
1/33 Duty (DT1, DT0 = [0, 1])
1-line Selection Period
1 2 3 4
ŸŸŸ
ŸŸŸ
303132 33 1 2 3 4
303132 33
V0
V1
COM1
V4
VS
1 FRAME
1 FRAME
1-line Selection Period = 17 Clock Pulses
One Frame
= 17 x 33 x 21.0µs = 11.8ms (1 Clock=21.0µs at fosc=47.6kHz)
Frame Frequency
= 1 / 11.8ms = 85Hz
Figure 35. Frame Frequency (1/33 Duty)
60
65 COM / 132 SEG DRIVER & CONTROLLER FOR STN LCD
KS0040
1/49 Duty (DT1, DT0 = [1, 0])
1-line Selection Period
ŸŸŸ
1 2
48 49 1 2
ŸŸŸ
48 49 1 2
ŸŸŸ
48 49 1 2
ŸŸŸ
48 49
V0
V1
COM1
V4
VS
1 FRAME
1 FRAME
1-line Selection Period = 17 Clock Pulses
One Frame
= 17 x 49 x 14.2µs = 11.8ms (1 Clock=14.2µs at fosc=68.3kHz)
Frame Frequency
= 1 / 11.8ms = 85Hz
Figure 36. Frame Frequency (1/49 Duty)
1/65 Duty (DT1, DT0 = [1, 1])
1-line Selection Period
1 2 3 4
ŸŸŸ
ŸŸŸ
62636465 1 2 3 4
62636465
V0
V1
COM1
V4
VS
1 FRAME
1 FRAME
1-line Selection Period = 17 Clock Pulses
One Frame
= 17 x 65 x 10.7µs = 11.8ms (1 Clock=10.7µs at fosc=93.7kHz)
Frame Frequency
= 1 / 11.8ms = 85Hz
Figure 37. Frame Frequency (1/65 Duty)
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65 COM / 132 SEG DRIVER & CONTROLLER FOR STN LCD
Table 24. Duty Select Input & Display Window Size
62
DT1
DT0
Duty
Display window size
Low
Low
1/17
1-line x 8-character
Low
High
1/33
2-line x 8-character
High
Low
1/49
3-line x 8-character
High
High
1/65
4-line x 8-character
65 COM / 132 SEG DRIVER & CONTROLLER FOR STN LCD
KS0040
MAXIMUM ABSOLUTE RATE
Table 25. Absolute Maximum Ratings
Characteristics
Symbol
Value
Unit
Power supply voltage (1)
VDD
-0.3 to +7.0
V
Power supply voltage (2)
V0, VOUT
-0.3 to + 15
V
Input voltage
VIN
-0.3 to VDD +0.3
V
Operating temperature
TOPR
-30 to +85
°C
Storage temperature
TSTG
-55 to +125
°C
NOTE1: All the voltage levels are based on VSS = 0V
NOTE2: Voltage greater than above may damage to the circuit
Voltage level: VOUT ≥ V0 ≥ VSS. (VLCD = V0 - VSS)
Voltage level: V0 ≥ V1 ≥ V2 ≥ V3 ≥ V4 ≥ VSS
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65 COM / 132 SEG DRIVER & CONTROLLER FOR STN LCD
ELECTRICAL CHARACTERISTICS
DC CHARACTERISTICS
Table 26. DC Characteristics
(VDD = 2.4V to 3.6V, Ta = -30 to +85 °C)
Item
Symbol
Condition
Min.
Typ.
Max.
Unit
Operating voltage
VDD
-
2.4
-
3.6
V
IDD1
Display operation
(checker pattern)
V0 = 9V without load
No access from MPU
-
-
180
IDD2
Sleep operation without load
Oscillator OFF
-
-
5
IDD3
Access operation from MPU
fcyc = 200kHz
-
-
500
VIH
-
0.8VDD
-
VDD
VIL
-
VSS
-
0.2VDD
ILEAK
VIN = 0V to VDD
-1
-
1
RCOM
Io = ± 50µA
-
-
5
RSEG
Io = ± 50µA
-
-
10
fFR
VDD = 3V, Ta = 25°C
60
85
110
Display of 1-line mode
-
24.5
-
Display of 2-line mode
-
47.6
-
Display of 3-line mode
-
68.3
-
Display of 4-line mode
-
93.7
-
Supply current
(VDD = 3V, Ta = 25°C)
µA
Input voltage
Input leakage current
V
RON resistance
Frame frequency
External clock
frequency
64
fCK
µA
kΩ
Hz
kHz
Voltage converter
VDD 2 / 3 / 4 times
VOUT
Ta = 25°C, C = 1µF
without load
95
99
-
Voltage regulator
reference voltage
VREF
Ta = 25°C, REF = L, VR pad
EV value (α) = 63
without load
1.94
2.0
2.06
LCD driving voltage
VLCD
VLCD = V0 – VSS
4.0
%
V
-
13.0
65 COM / 132 SEG DRIVER & CONTROLLER FOR STN LCD
KS0040
Table 26. DC Characteristics (Continued)
(VDD = 3.6V to 5.5V, Ta = -30 to +85 °C)
Item
Symbol
Condition
Min
Typ
Max
Unit
Operating voltage
VDD
-
3.6
-
5.5
V
IDD1
Display operation
(checker pattern)
V0 = 9V without load
no access from MPU
-
-
280
IDD2
Sleep operation without load
oscillator OFF
-
-
10
IDD3
Access operation from MPU
fcyc = 200kHz
-
-
1000
VIH
-
0.8VDD
-
VDD
VIL
-
VSS
-
0.2VDD
ILEAK
VIN = 0V to VDD
-1
-
1
RCOM
Io = ± 50µA
-
-
5
RSEG
Io = ± 50µA
-
-
10
fFR
VDD = 5V, Ta = 25°C
60
85
110
Display of 1-line mode
-
24.5
-
Display of 2-line mode
-
47.6
-
Display of 3-line mode
-
68.3
-
Display of 4-line mode
-
93.7
-
Supply current
(VDD = 5V, Ta = 25°C)
Input voltage
Input leakage current
V
RON resistance
Frame frequency
External clock
frequency
µA
µA
KΩ
fCK
Hz
kHz
*Voltage converter
VDD 2 / 3 times
VOUT
Ta = 25°C, C = 1µF
without load
95
99
-
Voltage regulator
reference voltage
VREF
Ta = 25°C, REF = L, VR pad
EV value (α) = 63
without load
1.94
2.0
2.06
LCD driving voltage
VLCD
VLCD = V0 – VSS
4.0
%
V
-
13.0
NOTE: When power supply (VDD) range is 3.6V to 5.5V, the 4 times boosting is not allowed.
65
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65 COM / 132 SEG DRIVER & CONTROLLER FOR STN LCD
AC CHARACTERISTICS
6800-series MPU Interface & Write Instruction
Table 27. AC Characteristics (6800-series Write Instruction)
Condition
VDD = 2.4V to 3.6V,
Ta = -30 to +85 oC
VDD = 3.6V to 5.5V,
Ta = -30 to +85 oC
Characteristic
Symbol
Min.
E cycle time
tC
650
Pulse rise / fall time
tR, tF
-
-
25
E pulse width high
tWH
450
-
-
E pulse width low
tWL
150
-
-
RS and CSB setup time
tSU1
60
-
-
RS and CSB hold time
tH1
30
-
-
DB setup time
tSU2
100
-
-
DB hold time
tH2
50
-
-
E cycle time
tC
350
Pulse rise / fall time
tR, tF
-
-
25
E pulse width high
tWH
250
-
-
E pulse width low
tWL
100
-
-
RS and CSB setup time
tSU1
40
-
-
RS and CSB hold time
tH1
10
-
-
DB setup time
tSU2
40
-
-
DB hold time
tH2
10
-
-
Typ.
tH1
tWL
tF
E_RD
tR
tSU2
tH2
DB0 to DB7
tC
Figure 17. Write Bus Mode Timing (6800-series MPU Interface)
66
ns
-
RW_WR
tWH
Unit
-
RS, CSB
tSU1
Max.
ns
65 COM / 132 SEG DRIVER & CONTROLLER FOR STN LCD
KS0040
8080-series MPU Interface & Write Instruction
Table 28. AC Characteristics (8080-series Write Instruction)
Condition
VDD = 2.4V to 3.6V,
Ta = -30 to +85 oC
VDD = 3.6V to 5.5V,
Ta = -30 to +85 oC
Characteristic
Symbol
Min.
WR cycle time
tC
650
Pulse rise / fall time
tR, tF
-
-
25
WR pulse width high
tWH
150
-
-
WR pulse width low
tWL
450
-
-
RS and CSB setup time
tSU1
60
-
-
RS and CSB hold time
tH1
30
-
-
DB setup time
tSU2
100
-
-
DB hold time
tH2
50
-
-
WR cycle time
tC
350
Pulse rise / fall time
tR, tF
-
-
25
WR pulse width high
tWH
100
-
-
WR pulse width low
tWL
250
-
-
RS and CSB setup time
tSU1
40
-
-
RS and CSB hold time
tH1
10
-
-
DB setup time
tSU2
40
-
-
DB hold time
tH2
10
-
-
Typ.
Max.
Unit
-
ns
-
ns
RS, CSB
tSU1
t WL
tH1
tR
tWH
RW_WR
tF
tSU2
tH2
DB0 to DB7
tC
Figure 18. Write Bus Mode Timing (8080-series MPU Interface)
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65 COM / 132 SEG DRIVER & CONTROLLER FOR STN LCD
6800-series MPU Interface & Read Instruction
Table 29. AC Characteristics (6800-series Read Instruction)
Condition
VDD = 2.4V to 3.6V,
Ta = -30 to +85 oC
VDD = 3.6V to 5.5V,
Ta = -30 to +85 oC
Characteristic
Symbol
Min.
E cycle time
tC
650
Pulse rise / fall time
tR, tF
-
-
25
E pulse width high
tWH
450
-
-
E pulse width low
tWL
150
-
-
RS and CSB setup time
tSU
60
-
-
RS and CSB hold time
tH
30
-
-
DB output delay time
tD
-
-
360
DB output hold time
tDH
20
-
-
E cycle time
tC
350
Pulse rise / fall time
tR, tF
-
-
25
E pulse width high
tWH
250
-
-
E pulse width low
tWL
100
-
-
RS and CSB setup time
tSU
40
-
-
RS and CSB hold time
tH
10
-
-
DB output delay time
tD
-
-
120
DB output hold time
tDH
10
-
-
Typ.
RW_WR
tF
t WL
E_RD
tR
tD
tDH
DB0 toDB7
tC
Figure 19. Read Bus Mode Timing (6800-series MPU Interface)
68
ns
-
tH
tWH
Unit
-
RS, CSB
tSU
Max.
ns
65 COM / 132 SEG DRIVER & CONTROLLER FOR STN LCD
KS0040
8080-series MPU Interface & Read Instruction
Table 30. AC Characteristics (8080-series Read Instruction)
Condition
VDD = 2.4V to 3.6V,
Ta = -30 to +85 oC
VDD = 3.6V to 5.5V,
Ta = -30 to +85 oC
Characteristic
Symbol
Min.
RD cycle time
tC
650
Pulse rise / fall time
tR, tF
-
-
25
RD pulse width high
tWH
150
-
-
RD pulse width low
tWL
450
-
-
RS and CSB setup time
tSU
60
-
-
RS and CSB hold time
tH
30
-
-
DB output delay time
tD
-
360
DB output hold time
tDH
20
-
-
RD cycle time
tC
350
Pulse rise / fall time
tR, tF
-
-
25
RD pulse width high
tWH
100
-
-
RD pulse width low
tWL
250
-
-
RS and CSB setup time
tSU
40
-
-
RS and CSB hold time
tH
10
-
-
DB output delay time
tD
-
-
120
DB output hold time
tDH
10
-
-
Typ.
Max.
Unit
-
ns
-
ns
RS, CSB
tSU
tWL
tH
tR
tWH
E_RD
tF
tD
tDH
DB0 to DB7
tC
Figure 20. Read Bus Mode Timing (8080-series MPU Interface)
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65 COM / 132 SEG DRIVER & CONTROLLER FOR STN LCD
Clock Synchronized Serial Mode
Table 31. AC Characteristics (Serial Mode)
Characteristic
Symbol
Min.
SCL clock cycle time
tC
1000
Pulse rise / fall time
tR, tF
-
-
25
SCL clock width (H / L)
tW
300
-
-
CSB setup time
tSU1
150
-
-
CSB hold time
tH1
700
-
-
RS data setup time
tSU2
50
-
-
RS data hold time
tH2
300
-
-
SI data setup time
tSU3
50
-
-
SI data hold time
tH3
50
-
-
SCL clock cycle time
tC
600
Pulse rise / fall time
tR, tF
-
-
25
SCL clock width (H / L)
tW
200
-
-
CSB setup time
tSU1
100
-
-
CSB hold time
tH1
400
-
-
RS data setup time
tSU2
40
-
-
RS data hold time
tH2
200
-
-
SI data setup time
tSU3
40
-
-
SI data hold time
tH3
40
-
-
Condition
VDD = 2.4V to 3.6V,
Ta = -30 to +85 oC
VDD = 3.6V to 5.5V,
Ta = -30 to +85 oC
tSU1
CSB
tC
SCL(DB6)
tSU2
t H2
RS
tSU3
tH3
SI(DB7)
Figure 32. Clock Synchronized Serial Interface Mode Timing Diagram
70
Unit
ns
-
tW
tF
Max.
-
tH1
tW
tR
Typ.
ns