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User's Guide
SLAU211A – March 2007 – Revised November 2009
DAC8560 Evaluation Module
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This user’s guide describes the characteristics, operation, and the use of the DAC8560 evaluation module
(EVM). It covers all pertinent areas to properly use this EVM board along with the devices that it supports.
The physical PCB layout, schematic diagram, and circuit descriptions are included.
Contents
EVM Overview
...............................................................................................................
PCB Design and Performance
............................................................................................
EVM Operation
..............................................................................................................
Related Documentation from Texas Instruments
Using the DAC8560 EVM with DXP
.....................................................................
....................................................................................
Bill of Materials
.............................................................................................................
List of Figures
EVM Block Diagram
........................................................................................................
Top Silkscreen
...............................................................................................................
Layer 1 (Top Signal Plane)
................................................................................................
Layer 2 (Ground Plane)
....................................................................................................
Layer 3 (Power Plane)
.....................................................................................................
Layer 4 (Bottom Signal Plane)
............................................................................................
Bottom Silkscreen
...........................................................................................................
INL and DNL Characteristic Plot
..........................................................................................
DAC8560EVM Default Jumper Configuration
...........................................................................
DAC8560EVM Schematic
................................................................................................
MMB0 with DAC8560EVM Installed
....................................................................................
Loading a DAC8560EVM Configuration
................................................................................
DAC8560EVM: Frequency/Amplitude and Update Rate Adjustments
.............................................
DAC Output Update Options
.............................................................................................
List of Tables
Factory Default Jumper Settings
..........................................................................................
DAC Output Channel Mapping
..........................................................................................
Unity Gain Output Jumper Settings
.....................................................................................
Gain of Two Output Jumper Settings
...................................................................................
Capacitive Load Drive Output Jumper Settings
.......................................................................
Jumper Setting Functions
................................................................................................
Output Update Features
..................................................................................................
DAC8560EVM Parts List
.................................................................................................
Microsoft, Windows are registered trademarks of Microsoft Corporation.
LabVIEW is a registered trademark of National Instruments.
All other trademarks are the property of their respective owners.
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DAC8560 Evaluation Module 1
EVM Overview www.ti.com
1 EVM Overview
This section gives a general overview of the DAC8560 evaluation module (EVM), and describes some of the factors to consider when using this module.
1.1
Features
This EVM features the DAC8560 digital-to-analog converter (DAC). The DAC8560EVM is a simple evaluation module designed to quickly and easily evaluate the functionality and performance of the 16-bit high-resolution, single-channel, and serial input DAC with a built-in 2.5-V internal reference that is enabled by default. This EVM features a serial interface to communicate with any host microprocessor or TI DSP base system.
Although the DAC was designed for single-supply operation, a bipolar output range is also possible by configuring the output operational amplifier circuit properly. This is discussed in detail in section 3.2.3. In addition, the external operational amplifier is also installed as an option to provide output signal conditioning or boost capacitive load drive and for other output mode requirements desired.
A +5-V precision voltage reference is provided via U3 as well as a 4.096-V precision reference via U4.
These references are optional voltage reference provided externally in case the user needs to evaluate the DAC8560 with external reference circuits. The external +5-V and +4-V reference source can be selected via W8 and W4 jumper configuration.
There is also a provision for possibly experimenting with different circuit loads on the reference of the
DAC8560. These are available through R16, C6, and a small 4x4 through-hole grid.
1.2
Power Requirements
The following sections describe the power requirements of this EVM.
1.2.1
Supply Voltage
The dc power supply requirement for this DAC8560EVM (VDD) is selectable between +3.3 V and +5 V via the W1 jumper header. The +3.3 V comes from J6-8 and the +5 V comes from J6-3 terminal. These power-supply voltages are referenced to ground through the J6-6 terminal. The VSS and VCC are only used by the U2 operational amplifier and the U3 voltage reference, which ranges from -15 V to +15 V maximum and connects through J6-1 and J6-2 terminals, respectively. All the analog power supplies are referenced to analog ground through J6-6 terminal.
CAUTION
To avoid potential damage to the EVM board, ensure that the correct cables are connected to their respective terminals as labeled on the EVM board.
Stresses greater than the maximum listed voltage ratings may cause permanent damage to the device.
The negative rail of the output operational amplifier, U2, can be selected between V
SS and AGND via the
W5 jumper. The external operational amplifier is installed as an option to provide output signal conditioning or for other desired output mode requirements.
CAUTION
To avoid potential damage to the EVM board, ensure that the correct cables are connected to their respective terminals as labeled on the EVM board.
Stresses greater than the maximum listed voltage ratings may cause permanent damage to the device.
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EVM Overview
1.2.2
Reference Voltage
The DAC8560 comes with a +2.5-V internal reference that is enabled by default. The +2.5-V internal reference can be measured from its V
REF pin, which can be used to source other devices that requires
+2.5-V reference. Because the DAC8560’s internal reference is enabled by default, care should be taken to ensure that the W4 and W8 jumper headers are open. Otherwise, inaccurate performance or damage to the part can result. However, the DAC8560 should not be damaged, providing that the external voltage that is applied to the V
REF pin does not exceed the applied voltage in the V
DD pin, and it does not exceed
100 mA of sourcing current. It is not recommended to leave the external voltage applied on the V
REF pin if the internal reference is not disabled. The external reference source should be disconnected immediately, and the EVM power must be recycled to ensure correct performance of the device.
The +5-V and +4-V precision voltage references are provided as an optional reference source to supply the external voltage reference for the DAC through REF02 (U3) and REF3240 (U4). These reference voltages are selectable via the jumper W8. When shorting pins 1 and 2, the +5-V reference is selected whereas shorting pins 2 and 3 selects +4-V reference. The jumper W4 must be shorted between pins 1 and 2 in order for these reference sources to propagate through the DAC.
The +5-V reference voltage goes through an adjustable 100-k Ω potentiometer, R11, in series with 20-k Ω
R10, to allow the user to adjust the reference voltage to its desired settings. The voltage reference then is buffered through U5 as seen by the device under test. The REF02 precision reference is powered by V
CC
(+15 V) through J6-1 terminal.
The REF3240 precision reference is powered by +5 VA through J6-3 terminal.
The test point TP1 also is provided, as well as J4-20, to allow the user to connect other external reference source if the onboard reference circuit is not desired. The external voltage reference should not exceed the applied power supply, V
DD
, of the DAC under test.
CAUTION
When applying an external voltage reference through TP1 or J4-20, ensure that it does not exceed the applied V
DD
. Otherwise, this can permanently damage the DAC8560, U1, device under test.
1.3
EVM Basic Functions
This EVM is designed primarily as a functional evaluation platform to test certain functional characteristics of the DAC8560 digital-to-analog converter (DAC). Functional evaluation of the installed DAC device can be accomplished with the use of any microprocessor, TI DSP, or some sort of a signal/waveform generator.
The headers J2 (top side) and P2 (bottom side) are pass-through connectors provided to allow the control signals and data required to interface a host processor or waveform generator to the DAC8560EVM using a custom-built cable.
The DAC output can be monitored through the selected pins of J4 header connector. The output can be switched through its respective jumper W2 whereas the sense pin V
FB respective jumper W7 for the reason of stacking. The V
FB also can be switched through its pin is discussed further in section 3 of this user’s guide manual. Stacking allows a total of two (DAC8560) DAC channels to be used provided the frame synchronization signal, SYNC, is unique for each EVM board stacked.
In addition, the option of selecting the DAC output to be fed to the noninverting side of the output operational amplifier, U2, is also possible by using a jumper across the selected pins of J4. The output operational amplifier, U2, must be first configured correctly for the desired waveform characteristic (see
of this document).
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DAC8560 Evaluation Module 3
PCB Design and Performance
A block diagram of the EVM is shown in
VCC
VSS
TP 1
External
Reference
Module
+4 V
+5V
W 4
W8
+ 3 .3 VA
W1
+ 5VA
( J1 )
( J5 )
( J6 )
( P 6)
V
REF
H
DAC Out
TP 3 Output
Buffer
Module W 3
(J 4)
(P 4)
W2
W 7
VREF H
VOUT
VDD
DAC Module
SCLK
DIN
VFB
GND SYNC
TP 2
(J 2)
(P 2)
W15
W6
VSS
W 5
Figure 1. EVM Block Diagram www.ti.com
VCC
GND
VSS
GND
VDD
+5 VA
+3 .3 VA
SCLK
DIN
CS
FSX
2 PCB Design and Performance
This section discusses the layout design of the PCB, describes the physical and mechanical characteristics of the EVM, and provides a brief description of the EVM test performance procedure. Also included is the list of components used on this evaluation module.
2.1
PCB Layout
The DAC8560EVM is designed to preserve the performance quality of the DAC, device under test, as specified in the data sheet. To take full advantage of the EVM's capabilities, use care during the schematic design phase to properly select the right components and to build the circuit correctly. The circuit should include adequate bypassing, identifying and managing the analog and digital signals, and understanding the components' electrical and mechanical attributes.
The main design concern during the layout process is the optimal placement of components and the proper routing of signals. Place the bypass capacitors as close as possible to the pins; properly separate the analog and digital signals from each other. In the layout process, carefully consider the power and ground plane because of their importance. A solid plane is ideally preferred, but because of its greater cost, sometimes a split plane can be used satisfactorily. When considering a split plane design, analyze the component placement and carefully split the board into its analog and digital sections starting from the
DUT. The ground plane plays an important role in controlling the noise and other effects that otherwise contributes to the error of the DAC output. To ensure that the return currents are handled properly, route the appropriate signals only in their respective sections, meaning that the analog traces should only lay directly above or below the analog section and the digital traces in the digital section. Minimize the length of the traces but use the biggest possible trace width allowable in the design. These design practices are illustrated in
through
.
The DAC8560EVM board is constructed on a four-layer printed-circuit board using a copper-clad FR-4 laminate material. The printed-circuit board has a dimension of 43,1800 mm (1.7000 inch) × 82,5500 mm
(3.2500 inch), and the board thickness is 1,5748 mm (0.062 inch).
through
show the individual artwork layers.
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PCB Design and Performance
Figure 2. Top Silkscreen
Figure 3. Layer 1 (Top Signal Plane)
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Figure 4. Layer 2 (Ground Plane)
Figure 5. Layer 3 (Power Plane)
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PCB Design and Performance
Figure 6. Layer 4 (Bottom Signal Plane)
Figure 7. Bottom Silkscreen
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EVM Operation www.ti.com
2.2
EVM Performance
The EVM performance test is performed using a high-density DAC bench test board, an Agilent 3458A digital multimeter, and a PC running the LabVIEW ® software. The EVM board is tested for all codes of
65535 and the device under test (DUT) is allowed to settle for 1 ms before the meter is read. This process is repeated for all codes to generate the measurements for INL and DNL.
shows the characteristic INL and DNL plots.
Figure 8. INL and DNL Characteristic Plot
3 EVM Operation
This section covers in detail the operation of the EVM to provide guidance to the user in evaluating the onboard DAC and how to interface the EVM to a specific host processor.
See the DAC8560 data sheet, SLAS264 , for information about its serial interface and other related topics.
The EVM board is factory tested and configured to operate in the unipolar output mode.
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EVM Operation
3.1
Factory Default Settings
The EVM board is set to its default configuration from factory as described in
to operate in unipolar +2.5-V mode of operation.
shows the default jumper configuration as described in the table for the DAC8560.
Table 1. Factory Default Jumper Settings
Reference
W1
W2
W3
W4
W5
W6
W7
W8
W15
J4
Jumper
Position
1-2
1-2
OPEN
Function
Analog supply for the DAC8560 is +5 VA.
DAC output (V
OUT
) is routed to J4-2.
V
REF is not routed to the inverting input of the operational amplifier for voltage offset (for bipolar mode of operation).
OPEN Onboard external buffered reference U3 or U4 is not routed to V
REF
.
1-2
1-2
Negative supply rail of U2 operational amplifier is supplied with V
SS
.
CS signal from J2 is used for frame synchronization, SYNC, signal.
OPEN
OPEN
For DAC8560EVM, the V
FB is not routed out unless there is a need to minimize the output error. If using
W7, remove R1 and short W7, then connect V
FB and V
OUT as close as possible to the load.
Onboard external buffered reference U3 or U4 are not selected. Default is the +2.5-V internal reference of the DAC8560.
OPEN Output operational amplifier, U2, is configured as voltage follower.
1-2 DAC output (V
OUT
) is connected to the noninverting input of the output operational amplifier, U2.
Figure 9. DAC8560EVM Default Jumper Configuration
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3.2
Host Processor Interface
The host processor basically drives the DAC; so, the DAC's proper operation depends on the successful configuration between the host processor and the EVM board. In addition, a properly written code also is required to operate the DAC.
A custom cable can be made specific to the host interface platform. The EVM allows interface to the host processor through J2 header connector for the serial control signals and the serial data input. The output can be monitored through the J4 header connector.
An interface adapter board also is available for a specific TI DSP starter kit as well as an MSP430-based microprocessor as previously mentioned. Using the interface board alleviates the tedious task of building customized cables and allows easy configuration of a simple evaluation system.
The DAC8560 interfaces with any host processor capable of handling SPI protocols or the popular TI
DSP. For more information regarding the DAC8560 data interface, see the DAC8560 data sheet
( SLAS464 ).
3.3
EVM Stacking
The stacking of EVMs is possible if the user needs to evaluate two DAC8560 devices to yield a total of up to two (DAC8560) channel outputs. A maximum of two EVMs are allowed because the output terminal, J4, dictates the number of DAC channels that can be connected without output bus contention.
shows how the DAC output channels are mapped into the output terminal, J4, with respect to the jumper position of W2 and W7.
Table 2. DAC Output Channel Mapping
Reference
W2
W7
Jumper
Position
1-2
2-3
1-2
2-3
Function
DAC output (V
OUT
) is routed to J4-2.
DAC output (V
OUT
) is routed to J4-6.
DAC sense pin (V
FB
) is routed to J4-10, if R1 jumper resistor is disconnected.
DAC sense pin (V
FB
) is routed to J4-14, if R1 jumper resistor is disconnected.
In order to allow exclusive control of each EVM that is stacked together, the DAC8560 must have a separate SYNC signal. This is accomplished in hardware by routing the SYNC signal of the first EVM through CS (P2/J2 pin 1) by shorting pins 1-2 of jumper W6. The second EVM should use the FSX signal
(P2/J2 pin 7) to drive the SYNC signal by shorting pins 2-3 of the jumper W6. The output can be mapped as described in
for each of the EVM stacked.
3.4
The Output Operational Amplifier
The EVM includes an optional signal-conditioning circuit for the DAC output through an external operational amplifier, U2. During stacking of the EVMs, only one DAC output channel can be monitored at any given time for evaluation because the odd-numbered pins (J4-1 to J4-7) are tied together. If both outputs are needed to be buffered and monitored at the same time, the traces in the back of the EVM board are exposed for ease of cutting. When cutting a trace, make sure to cut through the trace adjacent to the appropriate J4 header pin and not at the curvy line. If the trace is cut through the curving line, the signal may not propagate through to the operational amplifier. See
and the schematic included in this manual.
The output operational amplifier is set to unity gain configuration by default but can be modified by simple jumper settings. Nevertheless, the raw output of the DAC can be probed through the specified pins of the
J4 output terminal, which also provides mechanical stability when stacking or plugging into any interface board. In addition, it provides easy access for monitoring up to two (DAC8560) DAC channels when stacking two EVMs together (see section 3.3).
The following sections describe the different configurations of the output amplifier, U2.
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EVM Operation
3.4.1
Unity Gain Output
The buffered output configuration can be used to prevent loading the DAC8560, although it may present some slight distortion because of the feedback resistor and capacitor. The user can tailor the feedback circuit to closely match the desired wave shape by simply desoldering R6 and C12 and replacing them with components of the desired values. Additionally, C12 can be eliminated and R6 can be replaced with a
0 Ω resistor to simplify the feedback circuit.
shows the jumper setting for the unity gain configuration of the DAC external output buffer in unipolar or bipolar mode.
Reference
W3
W5
W15
Table 3. Unity Gain Output Jumper Settings
Jumper Setting
Unipolar Bipolar
Open
2-3
Open
Open
1-2
Open
Function
Disconnect V
REF from the inverting input of the operational amplifier.
Supplies V
SS to the negative rail of operational amplifier or ties it to AGND.
Disconnect the negative input of the operational amplifier from the gain resistor, R12.
3.4.2
Output Gain of Two or Bipolar Operation
Two types of configurations yield a gain of two output, depending on the setup of the jumpers W3 and
W15. These configurations allow the user to choose a DAC output having V
REF as an offset or not.
shows the proper jumper settings of the EVM for the 2× gain output of the DAC.
Table 4. Gain of Two Output Jumper Settings
Reference
Jumper Setting
Unipolar Bipolar
Close Close
W3
Open Open
W5
W15
2-3
Close
Open
1-2
Close
Open
Function
Inverting input of the output operational amplifier, U2, is connected to V
REF voltage for bipolar operation. W15 jumper must be open.
for use as its offset
V
REF is disconnected from the inverting input of the output operational amplifier, U2. W15 jumper must be close to achieve gain of 2 output.
Supplies power, V
SS
, to the negative rail of operational amplifier, U2, for bipolar mode, or ties it to AGND for unipolar mode.
Configures operational amplifier, U2, for a gain of 2 output without a voltage offset. W3 jumper must be open.
Inverting input of the operational amplifier, U2, is disconnected from the gain resistor, R12. W3 jumper must be close.
3.4.3
Capacitive Load Drive
Another output configuration option is to drive a wide range of capacitive load requirement. However, all operational amplifiers under certain conditions may become unstable depending on the operational amplifier configuration, gain, and load value. These are just few factors that can affect operational amplifiers stability performance and should be considered when implementing.
In unity gain, the OPA627 operational amplifier, U2, performs well with large capacitive loads. Increasing the gain enhances the amplifier’s ability to drive even more capacitance, and by adding a load resistor even improves the capacitive load drive capability.
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EVM Operation
shows the jumper setting configuration for a capacitive load drive.
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Reference
W3
W5
W15
Table 5. Capacitive Load Drive Output Jumper Settings
Jumper Setting
Unipolar Bipolar
Open
2-3
Open
Function
Open V
REF is disconnected from the inverting input of the output operational amplifier, U2.
1-2
Supplies power, V
SS
, to the negative rail of operational amplifier, U2, for bipolar mode, or ties it to AGND for unipolar mode.
Open
Capacitive load drive output of DAC is routed to pin 1 of W15 jumper and can be used as the output terminal.
3.5
Jumper Settings
shows the function of each specific jumper setting of the EVM.
Reference
Jumper
Position
1 3
Table 6. Jumper Setting Functions
Function
+5-V analog supply is selected for AV
DD
.
W1
1 3
+3.3-V analog supply is selected for AV
DD
.
1 3
Routes V
OUT to J4-2.
W2
1 3
Routes V
OUT to J4-6.
W3
W4
1 3
1 3
1 3
Disconnects V
REF to the inverting input of the output operational amplifier, U2
Connects V
REF to the inverting input of the output operational amplifier, U2
Routes the adjustable, onboard +5-V reference or the fixed +4-V reference to the V
REF
DAC8560.
input of the
This is the default jumper position for DAC8560EVM because the +2.5-V internal reference is enabled by default.
Routes the user-supplied reference from TP1 or J4-20 to the V
REF input of the DAC8560.
1 3
Negative supply rail of the output operational amplifier, U2, is powered by V
SS for bipolar operation.
W5
1 3
Negative supply rail of the output operational amplifier, U2, is tied to AGND for unipolar operation.
1 3
CS signal from J2-1 is routed to drive the SYNC signal of the DAC8560.
W6
1 3
FSX signal from J2-7 is routed to drive the SYNC signal of the DAC8560.
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Reference
W7
W8
EVM Operation
Jumper
Position
1 3
1 3
1 3
1 3
1 3
Table 6. Jumper Setting Functions (continued)
Function
For DAC8560EVM, the V
FB shown; then connect V
FB
J4-10.
is routed out to minimize the output error. Remove R1 and short W7 as and V
OUT as close as possible to the load. The V
FB signal will be routed to
This is the default jumper position for DAC8560EVM when R1 is installed.
For DAC8560EVM, the V
FB shown then connect V
FB
J4-14.
is routed out to minimize the output error. Remove R1 and short W7 as and V
OUT as close as possible to the load. The V
FB signal will be routed to
This jumper position selects the adjustable +5-V reference to route to the V
REF input of the DAC8560.
This is the default jumper position for DAC8560EVM because the +2.5-V internal reference is enabled by default.
1 3
This jumper position selects the +4-V reference to route to the V
REF input of the DAC8560.
W15
Legend:
Disconnects the inverting input of the output operational amplifier, U2, from the gain resistor, R12.
Connects the inverting input of the output operational amplifier, U2, to the gain resistor, R12, for gain of 2 configuration.
Indicates the corresponding pins that are shorted or closed.
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3.6
Schematic
7
5
1
4 www.ti.com
7
8
4
1 3
3
D GN
4
1
Figure 10. DAC8560EVM Schematic
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4 Related Documentation from Texas Instruments
Related Documentation from Texas Instruments
To obtain a copy of any of the following TI documents, call the Texas Instruments Literature Response
Center at (800) 477-8924 or the Product Information Center (PIC) at (972) 644-5580. When ordering, identify this manual by its title and literature number. Updated documents also can be obtained through the TI Web site at www.ti.com
.
Related Documentation
Data Sheet
DAC8560
REF02
REF3240
OPA627
OPA227
Literature Number
SBAS254
SBVS003
SBVS058
SBOS165
SBOS110
5 Using the DAC8560 EVM with DXP
The DAC8560EVM is compatible with the DAC eXerciser Program (DXP) from Texas Instruments. DXP is a tool that can generate the necessary control signals required to output various signals and waveforms from the device installed on the DAC8560EVM. The DAC8560EVM-PDK kit combines the DAC8560EVM board with the DSP-based MMB0 modular motherboard. The kit includes the DXP software for evaluation using any available USB port on a Microsoft ® Windows ® XP-based computer.
DXP is a program that controls the digital input signals such as the clock, CS, and SDI. Wave tables are built into the DSP software to allow sine, ramp, triangle, and square wave signals to be generated by the
DAC8560. Straight dc outputs can also be obtained.
The DAC8560EVM-PDK uses the DSP-based MMB0 to control the DAC8560EVM using the DXP software. For complete information about installing and configuring DXP, see the DXP User's Guide , available for download from the TI web site . This section covers the specific operation of the
DAC8560EVM-PDK.
5.1
Hardware
The hardware consists of two primary components: the DAC8560EVM itself and a modular motherboard called the MMB0. The MMB0 board houses a TMS320VC5507 DSP that controls the serial interface to the device loaded on the EVM board.
The hardware must be configured such that the DAC8560EVM is plugged onto the MMB0, aligning female connectors J4, J2, and J6 (on the bottom side of the DAC8560EVM) with male connectors J7, J4, and J5 on the MMB0. The assembled hardware is shown in
CAUTION
Be sure to exercise caution when assembling the boards. It is possible to misalign the connectors and damage both the EVM and the motherboard.
CAUTION
DO NOT connect the MMB0 to your PC before installing the DXP software as described in the DXP User’s Guide. Installing the software first ensures that the necessary drivers are properly loaded to run the hardware.
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Figure 11. MMB0 with DAC8560EVM Installed
5.2
MMB0 Power Supplies
Several power connections are required for the hardware to work properly. For the MMB0, the supplied
6-V ac/dc converter is all that is necessary. Be sure that J12 on the MMB0 board is closed before connecting the ac/dc adapter to the DC In connector of the MMB0. This supply provides all power to the digital portion of the DAC8560EVM as well as all necessary power for the DSP. Clean, well-regulated analog power for the DAC8560EVM should be supplied externally via J14, a six-position screw terminal mounted in the lower left corner of the MMB0 board.
CAUTION
When using external power supplies applied to J14 on the MMB0, please ensure all shorting blocks from J13 are completely removed. Permanent damage to the MMB0 may occur otherwise
From left to right, the J14 screw terminal connections are –VA, +VA, +5VA, –5VA, +5VD, and GND. The
5V from the ac/dc adapter can be connected to the +VA or the +5VA by installing a jumper across JP13A or JP13B. If the jumpers are not installed, the analog V
SS
, V
CC
, +5VA, and –5VA may be applied directly to the –VA, +VA, +5VA, and –5VA screw terminals at J14 on the MMB0 (referenced to the GND terminal).
The DAC8581 board power requirements are described in
of this manual.
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Using the DAC8560 EVM with DXP
5.3
Software: Running DXP
Install DXP on a laptop or personal computer running Windows XP according to the detailed instruction in the DXP Users Guide (TI document SBAU146 ). Run the DXP program by clicking on the DXP icon on your desktop, or by browsing to your installation directory.
Before you can generate signals with DXP, a DAC EVM configuration file must be loaded. To load a configuration file, select the desired DAC from the configuration list under the DAC menu, as
illustrates. Choose the DAC configuration file for the device installed on the EVM.
Figure 12. Loading a DAC8560EVM Configuration
SLAU211A – March 2007 – Revised November 2009
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Using the DAC8560 EVM with DXP www.ti.com
The DXP software defaults to output a 1-kHz sine wave from the DAC. Other waveform options include square, sawtooth, triangle, and dc output options, as described in the DXP User's Guide . The frequency and amplitude of the output waveform are controlled by sliders on the DXP software interface. The DAC update rate can also be modified, as shown in
Figure 13. DAC8560EVM: Frequency/Amplitude and Update Rate Adjustments
18 DAC8560 Evaluation Module SLAU211A – March 2007 – Revised November 2009
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Bill of Materials
5.4
DAC Output Update Options
The DXP software also allows the user to choose several DAC output update options, as
shows.
Figure 14. DAC Output Update Options
lists the details on these options.
Options
Frame Sync
Latch with DSP Timer
Latch with External Timer
Update Rate
Table 7. Output Update Features
Detailed Description
The DXP software defaults to Frame Sync. The Frame Sync output of the MMB0 connects to the SYNC input of the DAC8560. The DAC output changes to the corresponding level when the DAC latch is updated via SDI. Ensure the shunt jumper on W6 is covering pins 2-3 (default is 1-2) to use this feature.
N/A
N/A
User Input - enter the desired DAC update rate, 1MSPS is the default
6 Bill of Materials
13
14
11
12
8
9
10
Item Qty Value
1
2
3 10k Ω
Designators
R6 R12 R14
1 20k Ω Trim Pot R9
3
4
5
1
0 Ω
100 Ω
R1–R4 R8
R13
5
6
7
1
1
3
20k
100k
0.1
Ω
μ
Ω
F
R10
Trim Pot R11
C1 C3 C7
15
16
2 1 μ F
1 1nF
1 0.47
μ F
2 10 μ F
C9 C10
C12
C2
1 100pF
1 Bipolar
Op-Amp
1 16-Bit String
DAC
1 4.096V
Reference
1 5V Reference
U4
U3
C5 C11
C4
U5
U1
Table 8. DAC8560EVM Parts List
Description
1/8W 1206 Thick Film Chip Resistor, ±1% Tol
5T Potentiometer, 4mm SMD, Cermet
1/4 W 1206 Thick Film Chip Resistor, ±5% Tol
1/4W 1206 Thick Film Chip Resistor, ±5% Tol
Vendor
Panasonic
Bourns
Panasonic
Panasonic
1/4W 1206 Thick Film Chip Resistor, ±5% Tol
Potentiometer, 4mm SMD, Cermet
Panasonic
Bourns
Multilayer Ceramic Chip Capacitor, 1206 SMD, 25V, ±15% TDK
TC, ±10% Tol
Multilayer Ceramic Chip Capacitor, 1210 SMD, 25V, ±15% TDK
TC, ±10% Tol
Multilayer Ceramic Chip Capacitor, 1206 SMD, 25V, ±15% TDK
TC, ±10% Tol
Multilayer Ceramic Chip Capacitor, 1206 SMD, 50V, ±15% TDK
TC, ±10% Tol
Multilayer Ceramic Chip Capacitor, 1210 SMD, 25V, ±15% TDK
TC, ±10% Tol
Multilayer Ceramic Chip Capacitor, 0603 SMD, 50V,
30ppm/°C, ±5% Tol
TDK
8-SOP(D) High Precision Low Noise Op-Amp
MSOP-8(DGK), 1-CH, SPI, Low Glitch, Voltage Output
DAC with Internal reference
Texas
Instruments
Texas
Instruments
4ppm/°C, 100µA, SOT23-6 VOLTAGE REFERENCE
15ppm/°C, ±0.2% Tol Output, SOIC-8, Voltage Reference
Texas
Instruments
Texas
Instruments
Vendor Part No.
ERJ-8ENF1002V
3214W-1-203E
ERJ-8GEY0R00V
ERJ-8GEYJ101V
ERJ-8GEYJ203V
3214W-1-104E
C3216X7R1E104KT
C3225X7R1E105KT
C3216X7R1H102KT
C3216X7R1H474KT
C3225X7R1E106KT
C1608COG1H101J
OPA227UA
DAC8560IDDGK
REF3240AIDBV
REF02AU
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DAC8560 Evaluation Module 19
Bill of Materials www.ti.com
(1)
Item Qty Value
17 1 Difet Op-Amp
18
19
20
21
22
23
24
25
26
27
28
29
Designators
U2
Table 8. DAC8560EVM Parts List (continued)
Description
8-SOP(D) Precision High-Speed, Difet Op-Amp
Vendor
Texas
Instruments
Samtec 2 10 × 2 × 0.1
SMT
1 5 × 2 × 0.1
SMT
2 10 × 2 × 0.1
SMT
1 5 × 2 × 0.1
SMT
J2 J4
J6
P2 P4
20-PIN Terminal Strip
10-PIN Terminal Strip
20-PIN Socket Strip
(1)
P6 10-PIN Socket Strip
(1)
5 1 × 1 × 0.061D
TP1–TP5
TH
2 3 × 1 × 0.7874
W2 W7
TH
2 2 × 1 × 0.1 TH W3 W15
Turret Terminal Pin
3-PIN Terminal Strip
Modified 0.025" Square Post Header
5 3 x 1 × 0.1 TH W1 W4–W6 W8 Modified 0.025" Square Post Header
0 N/A N/A Schematic Diagram
1 N/A
0 N/A
0 N/A
N/A
N/A
N/A
Printed Wiring Board
Printed Circuit Assembly
29 0 N/A N/A Kit Assembly
Samtec
Samtec
Samtec
Mill-Max
Samtec
Samtec
Samtec
Texas
Instruments
Texas
Instruments
Texas
Instruments
Texas
Instruments
30 Do not install these components
(1)
31
32
5 Do Not
Populate
1 2mm Shunt
C6 R5 R7 R16
R25
N/A
6 0.100 Shorting N/A
Blocks
Shorting Block for W2
Shorting Blocks
Samtec
Samtec
Vendor Part No.
OPA627AU
TSM-110-01-S-DV-M
TSM-105-01-T-DV
SSW-110-22-S-D-VS-P
SSW-105-22-F-D-VS-K
2348-2-00-01-00-00-07-0
TMM-103-01-T-S
MTSW-102-08-T-S-295
MTSW-103-08-T-S-295
6484156
6484155
6484157
6484158
2SN-BK-G
SNT-100-BK-G-H
P2, P4, and P6 parts are not shown in the schematic diagram. All the P-designated parts are installed in the bottom side of the PC board opposite the J-designated counterpart. Example, J2 is installed on the topside whereas P2 is installed in the bottom side opposite of J2.
Do NOT install the following: C6, R5, R7, R16, and R25.
20 DAC8560 Evaluation Module SLAU211A – March 2007 – Revised November 2009
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Exceeding the specified input range may cause unexpected operation and/or irreversible damage to the EVM. If there are questions concerning the input range, please contact a TI field representative prior to connecting the input power.
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