Fully Integrated GPS Module ORG1308 Data Sheet ORG1308 datasheet

ORG1308 datasheet

Fully Integrated GPS module

Fully Integrated GPS Module

ORG1308 Data Sheet

Document number: 31086 For technical questions contact: [email protected] www.origingps.com

Revision: A01

15-11-09 - 1 -



1. Introduction

ORG1308 GPS receiver module of ORG13XX Series has been designed to address applications where placement flexibility is very important along with stand alone operation, high level of integration and low power consumption.

The ORG13XX series are OriginGPS smallest, autonomous, fully featured GPS receivers, optimized for stand alone operation.

Featuring OriginGPS Noise-Free Zone System

TM

technology the ORG13XX series offer the ultimate in high sensitivity GPS performance in small size.

The ORG13XX series modules incorporate miniature multi-channel receiver that continuously tracks all satellites in view and provides accurate positioning data in industry’s standard NMEA-0183 format.

Internal ARM CPU core and sophisticated firmware keep GPS payload off the host and allow integration in low resources embedded solutions.

The ORG13XX series modules are complete SiP (System-in-Package) featuring advanced miniature packaging technology and an ultra small footprint designed to commit unique integration features for high volume, low cost and low power applications.

OriginGPS case study of the specifications of key components through involvement in R&D effort of major vendors derived in highest performance in industry’s smallest footprint parts available. These components placement using OriginGPS NFZ

TM

technology created hard-to-achieve laboratory performance in heavy-duty environment.


Revision: A01

15-11-09 - 2 -



2. Description

OriginGPS has revised and enhanced the architecture of classic GPS receivers.

Carefully selected key components including TCXO and LNA resulted in faster TTFF and operation stability under rapid environmental changes.

2.1. Features

 Fully integrated multi channel GPS receiver

 Stand alone operation

 50Ω passive antenna input through miniature coaxial connector

 Noise Free Zone System

TM

Technology

 SiRFstarIII GSC3LTf chipset

 L1 frequency, C/A code

 20 channels searching, 12 channels parallel tracking

 Acquisition sensitivity: -157dBm

 Tracking sensitivity: -159dBm

 Fast TTFF: <40s (typical) under Cold Start conditions

 Rapid TTFF by aiding information upload capability

 Multipath mitigation

 Indoor tracking

 SBAS (WAAS, MSAS, EGNOS) support

 Multi-Mode Assisted GPS (A-GPS) support

1

: Autonomous, MS Based, MS Assisted

 Extended Ephemeris for very fast TTFFs support through SiRF InstantFix

2

 Automatic and user programmable power saving scenarios

 Low power consumption: 100mW during acquisition

 ARM7 baseband CPU

 Selectable UART or SPI hardware interface

 Programmable UART protocol and message rate

 Selectable NMEA-0183 or SiRF Binary communication standards

 Single operating voltage: 3.3V to 5.5V

 Small footprint: 17mm x 17mm

 Surface Mount Device (SMD)

 Optimized for automatic pick–n-place and reflow equipment

 Industrial operating temperature range: -40

0

to 85

0

C

 Pb-Free RoHS compliant

Notes:

1. SiRFLoc® Client (SLC) LT A-

GPS Multimode Location Engine™ for GSM/3GPP or for CDMA IS-801A required

2. SiRF InstantFix service required


Revision: A01

15-11-09 - 3 -

2.2. Architecture



Figure 2-1: ORG1308 architecture

 Antenna input

Signals at 1575.42 MHz from the GPS satellites are being delivered from receiving antenna.

 LNA (Low Noise Amplifier)

The LNA amplifies the GPS signal to meet GSC3LT RF front-end signal chain input threshold.

Noise figure optimized design was implemented to provide maximum sensitivity.

 Band-pass SAW Filter

Band-pass SAW filter eliminates inter-modulated out-of-band signals that may corrupt receiver performance.

 TCXO (Temperature Compensated Crystal Oscillator)

This highly stable 16.369 MHz oscillator controls the down conversion process in RF block.

Highest characteristics of this component are key factors in fast TTFF.

 UART Buffers

UART interface is 1.8V/2.5V/3.3V compatible. Voltage level is defined externally by host.


Revision: A01

15-11-09 - 4 -

 GSC3LTf IC



Figure 2-2: GSC3LT functional block diagram

SiRF GSC3LT GPS Navigation Engine includes the following features:



RF Receiver



ARM7TDMI-S core



SiRFstarIII-LT GPS DSP core



ARM RAM with cache



DSP RAM



Interrupt Controller



RTC Block



Watchdog Timer



Battery Backed RAM



4 Mbit Program ROM



UART Block



SPI Block



4 Integrated Voltage Regulators



POR (Power-On-Reset) Circuitry


Revision: A01

15-11-09 - 5 -



3. Electrical Specifications

3.1. Absolute Maximum Ratings

Absolute Maximum Ratings are stress ratings only.

Stresses exceeding Absolute Maximum Ratings may damage the device.

Parameter

Power Supply Voltage

UART Input Voltage

UART Output Source/Sink Current

SPI/GPIO Input Voltage

SPI/GPIO Output Source/Sink Current

ON_OFF Input Voltage

RESET Input Voltage

1.8V Source Output Current

J1 RF Input Power

Storage Temperature

Lead Temperature (10 sec. @ 1mm from case)

I

Symbol Min

V

V

I

CC

RX

TX

0

-0.5

Max

5.5

7

Units

V

V

-10 +10 mA

V

V

IO_IN

IO_OUT

0

-2

ON_OFF

1.98

+2

3.78

V mA

V

V

RESET

I

IO_1V8

1.26

6

V mA

P

RF_IN

10

T

ST

-55 +125

T

LEAD

+260 dBm

0

C

0

C

Table 3-1: Absolute maximum ratings


Revision: A01

15-11-09 - 6 -



3.2. Recommended Operating Conditions

Functional operation above the Recommended Operating Conditions is not implied.

Extended exposure to stresses above the Recommended Operating Conditions may affect device reliability.

Parameter

Power supply voltage

Power Supply Current

1.8 Output Voltage

Input Voltage Low State

Input Voltage High State

Output Voltage Low State

Output Voltage High State

Input Capacitance

Input Impedance

Input Return Loss

Reverse Isolation

Input 1dB Compressed Power

Input 3-rd Order Intercept Point

Operating Temperature

1

Symbol

RL

IN

IP

1dB

T

V

C

Z

OH

IIP

IN

IN

ISL

3

AMB

Mode / Pin

V

CC

Acquisition

I

CC

V

IO_1V8

V

IO-1V8

V

IL

UART

SPI / GPIO

ON_OFF

UART

V

IH

Tracking

Hibernate

V

OL

SPI / GPIO

ON_OFF

UART

SPI / GPIO

Test Conditions

T

V

CC

AMB

= 3.3V

= 25

0

C

UART

SPI / GPIO

UART

SPI / GPIO

J1 (RF Input)

I

OL

= 8mA

I

OL

= 1mA

I

OH

= -50µA

I

OH

= -4mA

I

OH

= -1mA f

0

= 1575.5 MHz f

0

= 1575.5 MHz f

1,2

= f

0

± 1MHz

Pin = -30 dBm

Relative Humidity RH Oper. Temp.

Min

3.25

Typ

3.3

30

9

1.62

1.4

1.35

2.7

V

IO

– 0.1

V

IO

– 0.5

1.6

24

1.8

4

1.3

50

-12

-30

-15

-40

5

-3

+25 +85

95

Max

5.5

35

0.36

0.2

10

23

25

1.98

0.5

0.45

0.6

Units

V mA

V

V pF pF

Ω

V

V

V

V mA

µA

V

V

V

V

V

V dB dB dBm dBm

0

C

%

Table 3-2: Operating conditions

Note:

1. Operation below -20

0

C to -40

0

C and above +70

0

C to +85

0

C is accepted, but TTFF may increase


Revision: A01

15-11-09 - 7 -



4. Performance

4.1. Acquisition times

TTFF (Time To First Fix) – is the period of time from GPS power-up till position estimation.

Hot Start

A hot start results from software reset after a period of continuous navigation or a return from a short idle period that was preceded by a period of continuous navigation.

In this state, all of the critical data (position, velocity, time, and satellite ephemeris) is valid to the specified accuracy and available in SRAM.

Warm Start

A warm start typically results from user-supplied position and time initialization data or continuous RTC operation with an accurate last known position available in memory. In this state, position and time data are present and valid, but ephemeris data validity has expired.

Cold Start

A cold start acquisition results when either position or time data is unknown.

Almanac information is used to identify previously healthy satellites.

Aided Start

Aiding is a method of effectively reducing the TTFF by making every start Hot or Warm.

Hot Start

Warm Start

Cold Start

Signal Reacquisition

TTFF

< 1s

< 35s

< 40s

< 1s

Signal Level

-130 dBm (Outdoor)

-130 dBm (Outdoor)

-130 dBm (Outdoor)

-130 dBm (Outdoor)

Table 4-1: Acquisition times

4.2. Sensitivity

Signal Level

Acquisition

Tracking

Cold Start

-157 dBm (Deep Indoor)

-159 dBm (Deep Indoor)

-142 dBm

Table 4-2: Sensitivity

4.3. Received Signal Strength

Average C/N

0

1

ORG1308

45 dB-Hz

Table 4-3: Received signal strength

Note:

1.

Averaging of 5 SV’s with highest C/N0 @ -130dBm, HDOP <1.5

2. With 12mm x 12 mm x 2.6mm OriginGPS Antenna assembly

2


Revision: A01

15-11-09 - 8 -



4.4. Power Consumption

Operation Mode

Acquisition

Tracking

Hibernate

Table 4-4: Power consumption

Power

100mW

30-75mW

80µW

4.5. Accuracy

Position

Velocity Horizontal

Heading

Time

Horizontal

Vertical

Method

CEP (50%)

2dRMS (95%)

Accuracy

< 2.5

< 2

< 5

VEP (50%)

2dRMS (95%)

< 4

< 4

< 3

<7.5

< 6

50%

50%

1 PPS

< 0.01

< 0.01

< 1

Units

m m m m m m

Test Conditions

-130 dBm (Outdoor), Static

-130 dBm (Outdoor), SBAS, Static


-130 dBm (Outdoor), SBAS, Static


-130 dBm (Outdoor), SBAS, Static m m


-130 dBm (Outdoor), SBAS, Static m/s -130 dBm (Outdoor), 30 m/s

0

-130 dBm (Outdoor), 30 m/s

µs -130 dBm (Outdoor)

Table 4-5: Accuracy

4.6. Dynamic Constrains

1

Velocity < 515m/s

Acceleration < 4g

Altitude < 18,000m

Table 4-6: Dynamic constrains

Note:

1. Standard dynamic constrains according to regulatory limitations


Revision: A01

15-11-09 - 9 -



5. Power Management

The ORG13XX series modules have three main operating modes which are controlled by internal statemachine.

These modes provide different levels of power and performance.

5.1. Normal Mode

In Normal Mode the ORG13XX series are fully powered and will automatically acquire and track

GPS satellites.

5.2. Power Saving Modes

Adaptive Trickle Power

TM

Adaptive Trickle Power (ATP) is best suited for applications that require navigation solutions at a fixed rate as well as low power consumption and an ability to track weak signals.

In ATP mode the ORG13XX series module is intelligently cycled between three states to optimize low power operation:

Full Power State

This is the initial state of the ORG13XX series module.

The module stays in full power until a position solution is made and estimated to be reliable.

During the acquisition mode, processing is more intense, thus consuming more power.

CPU Only State

This is the state when the RF and DSP sections are partially powered off.

The state is entered when the satellites measurements have been acquired but the navigation solution still needs to be computed.

Standby State

This is the state when the RF and DSP sections are completely powered off and baseband clock is stopped.

Figure 5-1: ATP timing


Revision: A01

15-11-09 - 10 -



Push-to-Fix

TM

Push-to-Fix (PTF) is best suited for applications that require infrequent navigation solutions, optimizing battery life time.

In PTF mode the ORG13XX series module is mostly in Hibernate Mode, waked up for Ephemeris and Almanac refresh in fixed periods of time. The PTF period is 30 minutes by default but can be anywhere between 10 seconds and 2 hours. When the PTF mode is enabled the receiver well stay on full power until the good navigation solution is computed.

Figure 5-2: PTF timing

Hibernate State

In this state the RF, DSP and baseband sections are completely powered off leaving only the RTC and Battery-backed RAM running. When the application needs a position report it can toggle the

ON_OFF pin to wake up the module. In this case, a new PTF cycle with default settings begins.


Revision: A01

15-11-09 - 11 -



6. Interface

6.1. Pin Assignment

Pin Number

1

2

3

4

5

6

7

12

13

14

15

8

9

10

11

16

17

18

19

20

21

22

J1

Pin Name

RX

TX

V

IO-EXT

SCK nSE

SDO

GPIO

[1]

V

CC

V

IO-1V8

GND

GND

GND

GND

GND

TSYNC nRESET

ON_OFF

GPIO

[2]

ECLK

COMM_SEL

1PPS

SDI

RF

IN

Pin Description

UART Receive

UART Transmit

UART buffers power

SPI Clock

SPI Chip Select

SPI Data Out

Valid Fix Indicator

System Power

1.8V Voltage Output

System Ground

System Ground

System Ground

System Ground

System Ground

Time Aiding

Asynchronous Reset

Soft Power On/Hibernate

Valid Fix Indicator

External Clock Input

UART/SPI Select

1 Pulse Per Second

SPI Data In

50Ω RF Input

Direction

Input

Output

Power

Input

Input

Output

Output

Power

Power

Power

Power

Power

Power

Power

Input

Input

Input

Output

Input

Input

Output

Input

Input

Table 6-1: ORG13XX series pin-out

Default

High

Low

Low

High

High

High

Low

Low

High

Low

Low

Notes

1.8V/2.5V/3.3V compatible

1.8V/2.5V/3.3V compatible

Connect to V

CC

if powered 3.3V

1.8V compatible

1.8V compatible

1.8V compatible

1.8V compatible

Connect to V

IO-EXT

for 1.8V UART

Special ROM version required

3.3V compatible

1.8V compatible

Special ROM version required

1.8V compatible

1.8V compatible

Passive antenna compatible


Revision: A01

15-11-09 - 12 -



6.2. Connectivity

Power supply

The ORG13XX series module requires only one power supply V

CC

, which can be supplied directly from a battery since the module has internal regulators.

It is recommended to keep the power supply on all the time in order to maintain the non-volatile

RTC and RAM active for fastest possible TTFF. When the V

CC is powered off settings are reset to factory default and the receiver performs Cold Start on next power up.

Power supply current varies according to the processor load and satellite acquisition.

V

CC

range is 3.3 to 5.5V DC.

Typical I

CC

current is 30mA during acquisition. Peak I

CC

current is 50 mA.

Typical I

CC

current in Hibernate state is 30µA.

Voltage ripple below 300mV

PP

allowed for frequency under 10KHz.


PP

allowed for frequency between 10KHz and 100KHz.


PP

allowed for frequency between 100KHz and 1MHz.


PP

allowed for frequency above 1MHz.

High voltage ripple may compromise the ORG13XX series module performance.

In case of powering the ORG13XX from switching mode (DC-DC) power source carefully follow manufacturer’s application note and apply passive low pass filtering.

Ground

Single Ground pin should be connected to main Ground with shortest possible trace or via.

ON OFF Control Input

The ON_OFF control input can be used to switch the receiver between Normal or Hibernate modes and also to generate interrupt in Push-to-Fix operation.

The ON_OFF interrupt is generated by a low-high-low toggle, which should be longer than 62µs and less than 1s (100ms pulse length recommended).

ON_OFF interrupts with less than 1 sec intervals are not recommended. Multiple switch bounce pulses are recommended to be filtered out.

Input level is 3.3V compatible.

Figure 6-1: ON_OFF timing

nRESET Input

The Power-on-Reset (POR) is generated internally in the ORG13XX series module.Additionally, manual reset option is available through nRESET pin.

Resetting the ORG13XX clears the RTC block and configuration settings become default. nRESET pin is active low and has internal pull-up resistor. nRESET signal should be applied for at least 1µs.


Revision: A01

15-11-09 - 13 -



COMM_SEL

The ORG13XX is able to communicate via UART or SPI interface.

UART is default communication interface.

To select SPI communication 0Ω resistor to system Ground should be applied on this pin.

Do not connect if SPI communication is not used.

UART

The device supports full duplex 8-N-1 UART communication without flow control.

The default protocol is NMEA.

The default configuration for baud rates and respective protocols can be changed by commands via NMEA or SiRF binary protocols.

I/O levels in the serial port are CMOS 1.8V/2.5V/3.3V compatible.

I/O levels are defined by applying appropriate voltage to

V

IO-EXT pin.

Do not connect if UART communication is not used.

SPI

The Host Interface SPI is a slave mode SPI that can be used as an alternative to the UART interface. The four primary pins are SDI, SDO, nSE, SCK.

I/O levels are 1.8V compatible.

Do not connect if SPI communication is not used.

SCK clock frequency must not be higher than 48fo/7 (= 7 MHz approximately).

The primary Host Interface SPI features are

:



TX and RX each have independent 1024 byte FIFO buffers.



RX and TX have independent, software specified two byte idle patterns.



TX FIFO is disabled when empty and transmits its idle pattern until re-enabled.



RX FIFO detects a software specified number of idle pattern repeats and then disables FIFO input until the idle pattern is broken.



FIFO buffers can generate an interrupt at any fill level.



SPI detects synchronization errors and can be reset by software.

The HSPI performs bit-by-bit transmitting and receiving at the same time whenever nSE is asserted and SCK is active.

Receive operations do not require an enable.

When the system is first turned on, the master in the host system is able to send a message before software has set up the receiver's idle pattern filter. At the system level, protocols are established to specify how the host platform must verify that the GPS system and host SPI are prepared for operation.

In general, the GSC3LT loads a ‘power on’ message to the TX_FIFO to inform the host that operations can begin. The protocol specifies the delay and repeats intervals for host query of the slave SPI for this message. This limits the receive byte volume until idle pattern filters are established.

On the receive side, the host is expected to transmit idle pattern when it is querying the transmit buffer, unless it has traffic for the GSC3LT. In this way, the volume is discarded, bytes are kept nearly as low as in the UART application because the hardware does not place most idle pattern bytes in the RX FIFO. Most messaging can be serviced with polling.


Revision: A01

15-11-09 - 14 -



The FIFO threshold can be placed to detect large messages requiring interrupt driven servicing.

On the transmit side, the intent is to fill the FIFO only when it is disabled and empty. In this condition, the driver software loads as many queued up messages as can fit in the FIFO. Then the

FIFO is enabled. The host is required to poll messages until idle pattern bytes are detected. At this point the FIFO is empty and disabled, allowing the driver to once again respond to an empty FIFO interrupt and load the FIFO with messages, if any are queued up in buffers.

Figure 6-2: SPI timing

ECLK Input

The ECLK is available optionally for external clock input using SiRFLoc client firmware for A-GPS frequency aiding. Input level is CMOS 1.8V compatible. Pull low with 10kΩ when not used.

Do not connect when using standard firmware version.

TSYNC Input

Optional input TSYNC input is intended for external time aiding using SiRFLoc client firmware for

A-GPS. Input level is CMOS 1.8V compatible. Pull low with 10kΩ when not used.

Do not connect when using standard firmware version.

RF Input

J1 miniature coaxial connector is unbalanced RF input matched for 50Ω passive microstrip patch antenna.


Revision: A01

15-11-09 - 15 -



1PPS Output

The pulse-per-second (PPS) output provides a pulse signal for timing purposes.

Pulse length (high state) is about 1µs synchronized to full UTC second.

I/O level is CMOS 1.8V compatible.

Figure 6-3: 1PPS

GPIO1 Output

GPIO1 is available as a valid fix indicator. Prior navigation the output stays at high state. During valid fix the output sends 100ms high state pulses at 1Hz rate. The I/O level is CMOS 1.8V compatible.

GPIO2 Output

GPIO2 is available as a valid fix indicator. Prior navigation the output stays at low state. During valid fix the output sends 100ms high state pulses at 1Hz rate. The I/O level is CMOS 1.8V compatible.

Figure 6-4: GPIO2 output period Figure 6-5: GPIO2 output


Revision: A01

15-11-09 - 16 -



6.3. Typical Application Circuit

UART Communication

3V3

C1

100pF

R1

33R nRESET

(Option)

ON_OFF

TX_GPS nRESET

ON_OFF

R3

33R

RF IN

C3

100pF

TX_D

RX_D

9 3 8

19

15

VIO_1V8

ECLK

TSY NC

VIO_EXT VCC

1PPS

21

GPIO1

GPIO2

7

18

J1

16

17

RFIN

RESET

ON_OFF

2

1

TX

RX

U1

COMM_SEL

20

SE

SCK

SDO

SDI

GND1 GND2 GND3 GND4 GND5

5

4

6

22

10 11 12 13 14

1PPS

GPIO2

C2

100pF

R2

33R

RX_GPS

R4

33R

C4

100pF

Figure 6-6: UART communication circuit

SPI Communication

1V8 3V3

(Option)

1PPS_GPS

(Option)

GPIO2_GPS

C1

100pF

R1

33R

(Option)

1PPS_GPS nRESET

(Option)

ON_OFF nRESET

ON_OFF

RF IN

9 3 8

VIO_1V8 VIO_EXT VCC

1PPS

21

19

15

ECLK

TSY NC

GPIO1

GPIO2

7

18

J1

16

17

RFIN

RESET

ON_OFF

2

1

TX

RX

U2

COMM_SEL

20

SE

SCK

SDO

SDI

GND1 GND2 GND3 GND4 GND5

5

4

6

22

10 11 12 13 14

1PPS

GPIO2

R0

0R

C2

100pF

R2

33R

R3

33R

R4

33R

R5

33R

R6

33R

(Option)

GPIO2_GPS

SPI_CS

SPI_CLK

SPI_DO

SPI_DI

Figure 6-7: SPI communication circuit


Revision: A01

15-11-09 - 17 -

6.4. Recommended Land Pattern



TOP VIEW

629mil

12

50mil

11

Ø12 mil

490mil

33mil

669mil

22

1

33mil

41mil

669mil

Figure 6-8: Recommended PCB layout

All Ground pins should be connected to main Ground with shortest possible traces or vias.

Ground pad at the middle should be connected to main Ground plane by multiple vias.

Ground pad at the middle should be solder masked.


Revision: A01

15-11-09 - 18 -



7. Software Functions

The ORG13XX series modules support NMEA-0183 and SiRF Binary protocols.

7.1. NMEA

NMEA Output Messages

Message Description

GGA

GLL

GSA

GSV

RMC

VTG

Time, position and fix type data

Latitude, longitude, UTC time of position fix and status

GPS receiver operating mode, satellites used in the position solution and DOP values

The number of GPS satellites in view, satellite ID, elevation, azimuth and SNR values

Time, date, position, course and speed data

Course and speed information relative to the ground

NMEA Input Messages

Message

ID (MID)

100

101

103

104

105

106

Message

Set Serial Port

Navigation Initialization

Query/Rate Control

LLA Navigation Initialization

Development Data On/Off

Select Datum

Description

Set PORT A parameters and protocol

Parameters required for start using X/Y/Z

Query standard NMEA message and/or set output rate

Parameters required for start using Lat/Lon/Alt

Development Data messages On/Off

Selection of an alternative map datum


Revision: A01

15-11-09 - 19 -



7.2. SiRF Binary

SiRF Binary Output Messages

0 x 02

0 x 03

0 x 04

0 x 06

0 x 07

0 x 08

0 x 09

0 x 0A

0 x 0B

0 x 0C

0 x 0D

0 x 0E

0 x 0F

0 x 10

0 x 12

0 x 13

0 x 14

0 x 1C

0 x 1E

0 x 1F

0 x FF

Hex Message ASCII Message Name

11

12

13

14

15

16

18

19

2

3

4

6

7

8

9

10

20

28

30

31

255

Description

Measured Navigation Data

True Tracker Data

Measured Tracking Data

SW Version

Clock Status

50 BPS Subframe Data

Throughput

Error ID

Position, velocity and time

Not implemented

Satellite and C/No information

Receiver software

Current clock status

Standard ICD format

Navigation complete data

Error coding for message failure

Command Acknowledgement Successful request

Command No Acknowledgement Unsuccessful request

Visible List

Almanac Data

Auto Output

Response to Poll

Ephemeris Data

Test Mode 1

Ok To Send

Navigation Parameters

Response to Poll

For use with SiRFtest (Test Mode 1)

CPU ON/OFF (Trickle Power)

Response to Poll

Test Mode 2

Nav. Lib. Measurement Data

Nav. Lib. SV State Data

Nav. Lib. Initialization Data

Development Data

Additional test data (Test Mode 2)

Measurement Data

Satellite State Data

Initialization Data

Various status messages


Revision: A01

15-11-09 - 20 -



SiRF Binary Input Messages

Hex ASCII Name

0 x 55 85

0 x 80 128

0 x 81 129

0 x 82 130

0 x 84 132

0 x 86 134

0 x 87 135

0 x 88 136

0 x 89 137

0 x 8B 139

0 x 8C 140

0 x 8D 141

0 x 8E 142

0 x 8F 143

0 x 90 144

0 x 92 146

0 x 93 147

0 x 94 148

0 x 95 149

0 x 96 150

0 x 97 151

0 x 98 152

0 x A5 165

0 x A6 166

0 x A7 167

Description

Transmit Serial Message

Initialize Data Source

Switch to NMEA Protocol

Set Almanac (upload)

Software Version (Poll)

Set Main Serial Port

Switch Protocol

Mode Control

DOP Mask

Elevation Mask

Power Mask

Editing Residual

Steady-State Detection

Static Navigation

Poll Clock Status

Poll Almanac

User definable message

Receiver initialization and associated parameters

Enable NMEA message, output rate and baud rate

Sends an existing almanac file to the receiver

Polls for the loaded software version

Baud rate, data bits, stop bits and parity

Obsolete

Navigation mode configuration

Control DOP mask selection and parameters

Elevation tracking and navigation masks

Power tracking and navigation masks

Not implemented

Configuration for static operation

For use with SiRFtest (Test Mode 1)

Polls the clock status

Polls for almanac data

Poll Ephemeris

Flash Update

Set Ephemeris (upload)

Switch Operating Mode

Polls for ephemeris data

On the fly software update

Sends an existing ephemeris to the receiver

Test mode selection, SV ID and period

Set Trickle Power Parameters

Poll Navigation Parameters

Set UART Configuration

Set Message Rate

Push to fix mode, duty cycle and on time

Polls for the current navigation parameters

Protocol selection, baud rate, data bits, stop bits and parity

SiRF binary message output rate

Low Power Acquisition Parameters Low power configuration parameters


Revision: A01

15-11-09 - 21 -

8. Handling Information

8.1. Product Packaging and Delivery

Plastic Reel



TOP VIEW

Feed direction

Position of Pin1

Figure 8-1: Carrier

A

0

B

0

K

0

F

P

1

S

0

W

ORG1308

18.00 ± 0.1

18.00 ± 0.1

03.60 ± 0.1

14.20 ± 0.1

24.00 ± 0.1

28.40 ± 0.1

32.00 ± 0.3

Carrier material: Conductive Polystyrene

Table 8-1: Carrier dimensions [mm]

Feed direction

Figure 8-2: Module position


Revision: A01

15-11-09 - 22 -



ØA

ØN

W

1

W

2

Figure 8-3: Reel

330.00 ± 0.85

60.00 ± 0.5

33.00 ± 0.5

39.00 ± 0.5

Table 8-2: Reel dimensions [mm]

Reel material: Antistatic Plastic

Each reel contains 200 or 500 modules.

Tube

18.42

Figure 8-4: Tube

Tube length: 515mm

Tube material: Antistatic Plastic

Each tube contains up to 27 modules.


Revision: A01

15-11-09 - 23 -



8.2. Moisture Sensitivity

The devices are moisture sensitive at MSL 3 according to standard IPC/JEDEC J-STD-033B.

The recommended drying process for samples and bulk components is to be done at 125°C for 48 hours.

8.3. Assembly

The ORG13XX series module support automatic assembly and reflow soldering processes on the component side of the motherboard PCB according to standard IPC/JEDEC J-STD-020D for LGA

SMD. Suggested solder paste stencil is 5 mil to ensure sufficient solder volume.

Figure 8-4: Recommended soldering profile

Suggested peak reflow temperature is 250°C for 10 sec. for Pb-Free solder paste.

Absolute Maximum reflow temperature is 260°C for 10 sec.

8.4. Rework

If localized heating is required to rework or repair the ORG13XX series module, precautionary methods are required to avoid exposure to solder reflow temperatures that can result in permanent damage to the device.

8.5. ESD Sensitivity

The ORG13XX series modules are ESD sensitive devices and should be handled with care.

8.6. Compliances

The ORG13XX series modules comply with the following standards:

 Pb-Free/RoHS (Directive 2002/95/EC on the restriction of the use of certain hazardous substances in electrical and electronic equipment)

 ISO 9001:2000 accredited manufacturing facility


Revision: A01

15-11-09 - 24 -



8.7. Safety Information

Improper handling and use can cause permanent damage to the device.

There is also the possible risk of personal injury from mechanical trauma or shocking hazard.

8.8. Disposal Information

The product should not be treated as household waste.

For more detailed information about recycling electronic components, please contact your local waste management authority.


Revision: A01

15-11-09 - 25 -



9. Mechanical Specifications

 The ORG13XX series modules have advanced miniature packaging and a LGA footprint.

 The ORG13XX series modules PCB footprint size is 17mm x 17mm

 The ORG1308 module is surface mount device packaged on a miniature printed circuit board with a metallic RF enclosure featuring miniature RF connector.

 There are 22 surface mount connection pads with a base metal of copper and an Electroless

Nickel / Immersion Gold (ENIG) finish.

 The ORG13XX series modules have been designed for automated pick and place assembly and reflow soldering processes.

9.1. ORG1308

TOP VIEW

SIDE VIEW

BOTTOM VIEW

16.2 ± 0.2

17 ± 0.2

11

12

Ø4.2 ± 0.2

1 22

Pin 1

17 ± 0.2

Dimensions mm inch

Length

17 ± 0.2

0.7 ± 0.008

All dimensions are in millimeters

Figure 9-1: ORG1308 mechanical drawing

Width

17 ± 0.2

0.7 ± 0.008

Height

2.2 ± 0.1

0.088 ± 0.004

Table 9-1: ORG1308 mechanical information

9.2. Plug

Mating plug for J1 connector is Hirose W.FL or Sunridge MCD series.

Figure 9-2: J1 mating plug mechanical drawing gr oz

Weight

1.4

0.1


Revision: A01

15-11-09 - 26 -

9.3. Antenna assembly



Figure 9-3: Antenna assembly mechanical drawing


Revision: A01

15-11-09 - 27 -



10. Ordering Information

ORG1308 - R01

– TR

XXX XX

Packaging

TR = Tape & Reel

UAR = Demo Board

Program configuration (table 10-1)

The table below indicates ORG13xx series modules program configuration options.

Configuration 1 and 2 are standard ordering options.

Configuration 3 is user defined application specific firmware version.

Ordering code

Configuration 1 Configuration 2 Configuration 3

ORG13xx-R01 ORG13xx-R02 ORG13xx-Fxx

Power On State Full Power Hibernate Full Power

UART data format

UART settings

SPI data format

Pin Functions

NMEA NMEA NMEA

4,800 bps 8-N-1 57,600 bps 8-N-1 9,600 bps 8-N-1

NMEA NMEA N/A

ON OFF

1 PPS

GPIO1

Direction

Next Toggle

Direction

No Nav

Nav

Direction

No Nav

Nav

Direction

No Nav GPIO2

Nav

Direction

COMM_SEL UART

SPI

Extended Features

Navigation

SBAS

Static Filter

Track

Smoothing

Internal DR

Input

Hibernate

Output

OFF

Input

Full Power

Output

OFF

1µs ON @ 1Hz

Output

1µs ON @ 1Hz

Output

ON ON

100ms ON @ 1Hz 100ms ON @ 1Hz

Output

OFF

Output

OFF

100ms ON @ 1Hz 100ms ON @ 1Hz

Input Input

No Connect

GND

No Connect

GND

OFF

OFF

OFF

OFF

ON

ON

OFF

ON

N/A

Output

OFF

1µs ON @ 1Hz

Application specific


N/A





Table 10-1: Program configuration


Revision: A01

15-11-09 - 28 -

Fully Integrated GPS Module ORG1308 Data Sheet ORG1308 datasheet

Fully Integrated GPS Module

ORG1308 Data Sheet

TOP VIEW

SIDE VIEW

BOTTOM VIEW

Related manuals

Table of contents

Fully Integrated GPS Module ORG1308 Data Sheet ORG1308 datasheet

Fully Integrated GPS Module

ORG1308 Data Sheet

TOP VIEW

SIDE VIEW

BOTTOM VIEW

Related manuals

Deluo

31-919-1

AmbiCom

GPS-USB

Table of contents