NXP PCF8534AU Universal LCD driver Product data

PCF8534A

Universal LCD driver for low multiplex rates

Rev. 6 — 25 July 2011 Product data sheet

The PCF8534A is a peripheral device which interfaces to almost any Liquid Crystal

Display (LCD) 1 with low multiplex rates. It generates the drive signals for any static or multiplexed LCD containing up to four backplanes and up to 60 segments. It can be easily cascaded for larger LCD applications. The PCF8534A is compatible with most microcontrollers and communicates via the two-line bidirectional I 2 C-bus. Communication overheads are minimized by a display RAM with auto-incremented addressing, by hardware subaddressing, and by display memory switching (static and duplex drive modes).

• PCF8534AHL/1 should not be used for new design-ins. Replacement part is

PCF85134HL/1

2. Features and benefits

 AEC-Q100 compliant (PCF8534AH/1) for automotive applications

 Single-chip LCD controller and driver

 Selectable backplane drive configurations: static or 2, 3, or 4 backplane multiplexing

 60 segment outputs allowing to drive:

 30 7-segment numeric characters

 15 14-segment alphanumeric characters

 Any graphics of up to 240 elements

 Cascading supported for larger applications

 60

 4-bit display data storage RAM

 Wide LCD supply range: from 2.5 V for low threshold LCDs up to 6.5 V for high threshold twisted nematic LCDs

 Internal LCD bias generation with voltage follower buffers

 Selectable display bias configurations: static, 1 ⁄

2

, or 1 ⁄

3

 Wide logic power supply range: from 1.8 V to 5.5 V

 LCD and logic supplies may be separated

 Low power consumption

 400 kHz I 2 C-bus interface

 No external components required

 Display memory bank switching in static and duplex drive modes

 Versatile blinking modes

 Silicon gate CMOS process

1.

The definition of the abbreviations and acronyms used in this data sheet can be found in

Section 19

.

NXP Semiconductors

PCF8534A


Table 1.

Ordering information

Type number Package

Name Description

PCF8534AHL/1

[1]

LQFP80 plastic low profile quad flat package; 80 leads; body 12

 12  1.4 mm

PCF8534AU/DA/1 wire bond die 76 bonding pads;

2.91

 2.62  0.38 mm

[1] Not to be used for new designs. Replacement part is PCF85134HL/1.

Delivery form Version tape and reel SOT315-1 chip in tray PCF8534AU

4. Marking

Table 2.

Marking codes

Type number

PCF8534AHL/1

PCF8534AU/DA/1

Marking code

PCF8534AHL

PC8534A-1

PCF8534A

Product data sheet

All information provided in this document is subject to legal disclaimers.

Rev. 6 — 25 July 2011

© NXP B.V. 2011. All rights reserved.

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PCF8534A


5.

Block diagram

BP0 BP1 BP2 BP3 S0 to S59

60

DISPLAY SEGMENT OUTPUTS

V

LCD BACKPLANE

OUTPUTS

LCD

VOLTAGE

SELECTOR

LCD BIAS

GENERATOR

V

SS

CLK

SYNC

CLOCK SELECT

AND TIMING

BLINKER

TIMEBASE

OSC OSCILLATOR

POWER-ON

RESET

SCL

SDA

INPUT

FILTERS

I

2

C-BUS

CONTROLLER

Fig 1.

Block diagram of PCF8534A

SA0

DISPLAY

CONTROL

PCF8534A

COMMAND

DECODE

V

DD

WRITE DATA

CONTROL

DISPLAY REGISTER

OUTPUT BANK SELECT

AND BLINK CONTROL

DISPLAY

RAM

DATA POINTER AND

AUTO INCREMENT

SUBADDRESS

COUNTER

A0 A1 A2

001aah614

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6.1 Pinning

S43

S44

S45

S46

S39

S40

S41

S42

S35

S36

S37

S38

S31

S32

S33

S34

S47

S48

S49

S50

17

18

19

20

13

14

15

16

9

10

11

12

7

8

5

6

3

4

1

2

PCF8534AHL

Top view. For mechanical details, see

Figure 25 .

Fig 2.

Pin configuration for SOT315-1 (PCF8534AHL)

56

55

54

53

60

59

58

57

S6

S5

S4

S3

S10

S9

S8

S7

52

51

S2

S1

50 S0

49

48

V

LCD

V

SS

SA0 47

46

45

44

43

42

A2

A1

A0

OSC

SYNC

41 V

DD

013aaa158

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C1

64

65

66

67

68

69

70

71

72

73

74

75

76

1

S51

S52

S53

S54

S55

S56

S57

S58

S59

BP0

BP1

BP2

BP3

SDA

PCF8534A-1

SCL 2

CLK 3

F

Top view

Viewed from active side. For mechanical details, see Figure 26

.

Fig 3.

Pin configuration for the wire bond die (PCF8534AU)

C2

43

42

41

40

39

38

37

S30

S29

S28

S27

S26

S25

S24

36

35

34

33

32

31

30

29

28

27

26

25

24

S16

S15

S14

S13

S12

S11

S23

S22

S21

S20

S19

S18

S17

001aai648

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6.2 Pin description

Table 3.

Pin description

Symbol Pin

SOT315-1 Wire bond die

S31 to S59 1 to 29

BP0 to BP3 30 to 33 n.c.

34 to 37

SDA

SCL

CLK

V

DD

SYNC

38

39

40

41

42

OSC

A0 to A2

SA0

43

44 to 46

47

V

SS

V

LCD

48

49

S0 to S30 50 to 80

-

44 to 72

73 to 76

1

2

3

4

5

6

7 to 9

10

11 [1]

12

13 to 43

-

Type output output input/output input input/output supply input/output input input input supply supply output

Description

LCD segment output 31 to 59

LCD backplane output 0 to 3 not connected; do not connect and do not use as feed through

I 2 C-bus serial data input and output

I 2 C-bus serial clock input external clock input and internal clock output supply voltage cascade synchronization input and output (active LOW) enable input for internal oscillator subaddress counter input 0 to 2

I 2 C-bus slave address input 0 ground input of LCD supply voltage

LCD segment output 0 to 30

[1] The substrate (rear side of the die) is connected to V

SS

and should be electrically isolated.

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The PCF8534A is a versatile peripheral device designed to interface between any microcontroller to a wide variety of LCD segment or dot matrix displays (see

Figure 4 ). It

can directly drive any static or multiplexed LCD containing up to four backplanes and up to

60 segments.

The display configurations possible with the PCF8534A depend on the required number of active backplane outputs. A selection of display configurations is given in

Table 4 .

All of the display configurations given in

Table 4

can be implemented in a typical system

as shown in Figure 5

.

dot matrix

7-segment with dot 14-segment with dot and accent

013aaa312

Fig 4.

Example of displays suitable for PCF8534A

2

1

4

3

Table 4.

Selection of possible display configurations

Number of

Backplanes Icons

240

180

120

60

Digits/Characters

7-segment

[1]

14-segment

[2]

30

22

15

11

15

7

7

3

[1] 7-segment display has eight elements including the decimal point.

[2] 14-segment display has 16 elements including decimal point and accent dot.

Dot matrix/

Elements

240 (4

 60)

180 (3

 60)

120 (2

 60)

60 (1

 60)

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V

DD

R

≤ t r

2C b

V

DD

V

LCD

HOST

MICRO-

PROCESSOR/

MICRO-

CONTROLLER

SDA

SCL

OSC

PCF8534A

60 segment drives

4 backplanes

LCD PANEL

(up to 240 elements)

A0 A1 A2 SA0 V

SS

V

SS

001aah616

Fig 5.

Typical system configuration

The host microcontroller maintains the 2-line I 2 C-bus communication channel with the

PCF8534A.

Biasing voltages for the multiplexed LCD waveforms are generated internally, removing the need for an external bias generator. The internal oscillator is selected by connecting pin OSC to V

SS

. The only other connections required to complete the system are the power supplies (pins V

DD

, V

SS

, and V

LCD

) and the LCD panel selected for the application.

7.1 Power-On Reset (POR)

At power-on the PCF8534A resets to the following starting conditions:

• All backplane and segment outputs are set to V

LCD

• The selected drive mode is: 1:4 multiplex with 1 ⁄

3

bias

• Blinking is switched off

• Input and output bank selectors are reset

• The I 2 C-bus interface is initialized

• The data pointer and the subaddress counter are cleared (set to logic 0)

• Display is disabled

Remark: Do not transfer data on the I 2 C-bus for at least 1 ms after a power-on to allow the reset action to complete.

7.2 LCD bias generator

Fractional LCD biasing voltages are obtained from an internal voltage divider consisting of three impedances connected in series between V

LCD

and V

SS

. If the 1 ⁄

2

bias voltage level for the 1:2 multiplex drive mode configuration is selected, the center impedance is bypassed by switch. The LCD voltage can be temperature compensated externally, using the supply to pin V

LCD

.

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7.3 LCD voltage selector

The LCD voltage selector coordinates the multiplexing of the LCD in accordance with the selected LCD drive configuration. The operation of the voltage selector is controlled by the mode-set command from the command decoder. The biasing configurations that apply to the preferred modes of operation, together with the biasing characteristics as functions of

V

LCD

and the resulting discrimination ratios (D) are given in

Table 5

.

Discrimination is a term which is defined as the ratio of the on and off RMS voltage across a segment. It can be thought of as a measurement of contrast.

Table 5.

Biasing characteristics

LCD drive mode

Number of:

Backplanes Levels

LCD bias configuration static 1

1:2 multiplex 2

1:2 multiplex 2

1:3 multiplex 3

1:4 multiplex 4

4

4

2

3

4 static

1 ⁄

2

1 ⁄

3

1 ⁄

3

1 ⁄

3

V

-------------------------



V

LCD

0

0.354

0.333

0.333

0.333

V

------------------------



D

V

LCD

=

V

-------------------------

V off RMS





1



0.791

2.236

0.745

0.638

0.577

2.236

1.915

1.732

A practical value for V

LCD

is determined by equating V off(RMS)

with a defined LCD threshold voltage (V th(off)

), typically when the LCD exhibits approximately 10 % contrast. In the static drive mode a suitable choice is V

LCD

> 3V th(off)

.

Multiplex drive modes of 1:3 and 1:4 with 1 ⁄

2

bias are possible but the discrimination and hence the contrast ratios are smaller.

Bias is calculated by

1 + a

, where the values for a are a = 1 for 1 ⁄

2

bias a = 2 for 1 ⁄

3

bias

The RMS on-state voltage (V on(RMS)

) for the LCD is calculated with Equation 1

:

V



=

V

LCD

2 + 2a + n n

 

1 + a

 2 where the values for n are n = 1 for static drive mode n = 2 for 1:2 multiplex drive mode n = 3 for 1:3 multiplex drive mode n = 4 for 1:4 multiplex drive mode

The RMS off-state voltage (V off(RMS)

) for the LCD is calculated with

Equation 2 :

(1)

V



=

V

LCD

2 – 2a + n n

 

1 + a

 2

Discrimination is the ratio of V on(RMS)

to V off(RMS)

and is determined from

Equation 3

:

(2)


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D =

V

-----------------------

V off RMS



=

2

+ 2a + n a

2

– 2a + n

(3)

Using

Equation 3

, the discrimination for an LCD drive mode of 1:3 multiplex with

1 ⁄

2 bias is 3 = 1.732

and the discrimination for an LCD drive mode of 1:4 multiplex with

1 ⁄

2 bias is

21

1.528

3

= .

The advantage of these LCD drive modes is a reduction of the LCD full scale voltage V

LCD as follows:

• 1:3 multiplex ( 1 ⁄

2

bias): V

LCD

=

• 1:4 multiplex ( 1 ⁄

2

bias): V

LCD

=

6



V



= 2.449V

 

3

3



= 2.309V

off RMS





These compare with V

LCD

= 3V off RMS



when 1 ⁄

3

bias is used.

V

LCD

is sometimes referred as the LCD operating voltage.

7.3.1 Electro-optical performance

Suitable values for V on(RMS)

and V off(RMS)

are dependent on the LCD liquid used. The

RMS voltage, at which a pixel is switched on or off, determines the transmissibility of the pixel.

For any given liquid, there are two threshold values defined. One point is at 10 % relative transmission (at V th(off)

) and the other at 90 % relative transmission (at V th(on)

), see

Figure 6

. For a good contrast performance, the following rules should be followed:

V

V





V





V th off



(4)

(5)

V on(RMS)

and V off(RMS)

are properties of the display driver and are affected by the selection

of a, n (see Equation 1

to

Equation 3 ) and the V

LCD

voltage.

V th(off)

and V th(on)

are properties of the LCD liquid and can be provided by the module manufacturer.

It is important to match the module properties to those of the driver in order to achieve optimum performance.

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100 %

90 %

10 %

OFF

SEGMENT

V th(off)

V

GREY

SEGMENT th(on)

V

RMS

[V]

ON

SEGMENT

013aaa494

Fig 6.

Electro-optical characteristic: relative transmission curve of the liquid

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7.4 LCD drive mode waveforms

7.4.1 Static drive mode

The static LCD drive mode is used when a single backplane is provided in the LCD.

Backplane and segment drive waveforms for this mode are shown in Figure 7

.

T fr

V

LCD

LCD segments

BP0

V

SS

V

LCD state 1

(on) state 2

(off)

Sn

V

SS

V

LCD

Sn+1

V

SS

(a) Waveforms at driver.

V

LCD state 1 0 V

− V

LCD

V

LCD state 2 0 V

− V

LCD

(b) Resultant waveforms at LCD segment.

V state1

(t) = V

Sn

(t)

 V

BP0

(t).

V on(RMS)

= V

LCD

.

V state2

(t) = V

(Sn + 1)

(t)

 V

BP0

(t).

V off(RMS)

= 0 V.

Fig 7.

Static drive mode waveforms

013aaa207

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7.4.2 1:2 Multiplex drive mode

When two backplanes are provided in the LCD, the 1:2 multiplex mode applies. The

PCF8534A allows the use of 1 ⁄

2

bias or 1 ⁄

3

bias in this mode as shown in

Figure 8 and

Figure 9

.

T fr

BP0

BP1

V

LCD

V

LCD

/2

V

SS

V

LCD

V

LCD

/2

V

SS

V

LCD

LCD segments state 1 state 2

Sn

V

SS

V

LCD

Sn+1

V

SS


state 1 state 2

V

LCD

V

LCD

/2

0 V

− V

LCD

/2

−

V

LCD

V

LCD

V

LCD

/2

0 V

− V

LCD

/2

− V

LCD


013aaa208

V state1

(t) = V

Sn

(t)

 V

BP0

(t).

V on(RMS)

= 0.791V

LCD

.

V state2

(t) = V

Sn

(t)

 V

BP1

(t).

V off(RMS)

= 0.354V

LCD

.

Fig 8.

Waveforms for the 1:2 multiplex drive mode with 1 ⁄

2

bias

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T fr

BP0

BP1

S n

S n+1

V

LCD

2V

LCD

/3

V

LCD

/3

V

SS

V

LCD

2V

LCD

/3

V

LCD

/3

V

SS

V

LCD

2V

LCD

/3

V

LCD

/3

V

SS

V

LCD

2V

LCD

/3

V

LCD

/3

V

SS



state 1 state 2

V

LCD

2V

LCD

/3

V

LCD

/3

0 V

−

V

LCD

/3

− 2V

LCD

/3

− V

LCD

V

LCD

2V

LCD

/3

V

LCD

/3

0 V

− V

LCD

/3

−

2V

LCD

− V

LCD

/3


V state1

(t) = V

Sn

(t)

 V

BP0

(t).

V on(RMS)

= 0.745V

LCD

.

V state2

(t) = V

Sn

(t)

 V

BP1

(t).

V off(RMS)

= 0.333V

LCD

.

Fig 9.

Waveforms for the 1:2 multiplex drive mode with 1 ⁄

3

bias

013aaa209

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When three backplanes are provided in the LCD, the 1:3 multiplex drive mode applies, as

shown in Figure 10 .

T fr

BP0

BP1

BP2

Sn

Sn+1

Sn+2

V

LCD

2V

LCD

/3

V

LCD

/3

V

SS

V

LCD

2V

LCD

/3

V

LCD

/3

V

SS

V

LCD

2V

LCD

/3

V

LCD

/3

V

SS

V

LCD

2V

LCD

/3

V

LCD

/3

V

SS

V

LCD

2V

LCD

/3

V

LCD

/3

V

SS

V

LCD

2V

LCD

/3

V

LCD

/3

V

SS


state 1 state 2

V

LCD

2V

LCD

/3

V

LCD

/3

0 V

− V

LCD

/3

− 2V

LCD

/3

−

V

LCD

V

LCD

2V

LCD

/3

V

LCD

/3

0 V

−

V

LCD

/3

− 2V

LCD

/3

−

V

LCD


V state1

(t) = V

Sn

(t)

 V

BP0

(t).

V on(RMS)

= 0.638V

LCD

.

V state2

(t) = V

Sn

(t)

 V

BP1

(t).

V off(RMS)

= 0.333V

LCD

.

Fig 10. Waveforms for the 1:3 multiplex drive mode with 1 ⁄

3

bias


013aaa210

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When four backplanes are provided in the LCD, the 1:4 multiplex drive mode applies, as

shown in Figure 11 .

T fr

BP0

BP1

BP2

BP3

Sn

Sn+1

Sn+2

Sn+3

V

LCD

2V

LCD

/3

V

LCD

/3

V

SS

V

LCD

2V

LCD

/3

V

LCD

/3

V

SS

V

LCD

2V

LCD

/3

V

LCD

/3

V

SS

V

LCD

2V

LCD

/3

V

LCD

/3

V

SS

V

LCD

2V

LCD

/3

V

LCD

/3

V

SS

V

LCD

2V

LCD

/3

V

LCD

/3

V

SS

V

LCD

2V

LCD

/3

V

LCD

/3

V

SS

V

LCD

2V

LCD

/3

V

LCD

/3

V

SS


state 1 state 2

V

LCD

2V

LCD

/3

V

LCD

/3

0 V

-V

LCD

/3

-2V

LCD

/3

-V

LCD

V

LCD

2V

LCD

/3

V

LCD

/3

0 V

-V

LCD

/3

-2V

LCD

/3

-V

LCD


V state1

(t) = V

Sn

(t)

 V

BP0

(t).

V on(RMS)

= 0.577V

LCD

.

V state2

(t) = V

Sn

(t)

 V

BP1

(t).

V off(RMS)

= 0.333V

LCD

.

Fig 11. Waveforms for the 1:4 multiplex drive mode with 1 ⁄

3

bias state 1 state 2

LCD segments

013aaa211

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7.5 Oscillator

The internal logic and the LCD drive signals of the PCF8534A are timed by the frequency f clk

. It equals either the built-in oscillator frequency f osc

or the external clock frequency f clk(ext)

. The clock frequency f clk

determines the LCD frame frequency (f fr

).

7.5.1 Internal clock

The internal oscillator is enabled by connecting pin OSC to pin V

SS

. In this case, the output from pin CLK is the clock signal for any cascaded PCF8534A in the system.

7.5.2 External clock

Pin CLK is enabled as an external clock input by connecting pin OSC to V

DD

.

Remark: A clock signal must always be supplied to the device. Removing the clock may freeze the LCD in a DC state, which is not suitable for the liquid crystal.

7.6 Timing

The PCF8534A timing controls the internal data flow of the device. This includes the transfer of display data from the display RAM to the display segment outputs. In cascaded applications, the correct timing relationship between each PCF8534A in the system is maintained by the synchronization signal at pin SYNC. The timing also generates the LCD frame signal whose frequency is derived from the clock frequency. The frame signal frequency is a fixed division of the clock frequency from either the internal or an external clock.

Table 6.

LCD frame frequencies

Operating mode ratio Frame frequency with respect to f

f clk

= 1536 Hz clk

(typical) f fr

= f

--------

24

64

Unit

Hz

7.7 Display register

The display register holds the display data while the corresponding multiplex signals are generated.

7.8 Segment outputs

The LCD drive section includes 60 segment outputs (S0 to S59) which should be connected directly to the LCD. The segment output signals are generated based on the multiplexed backplane signals and with data resident in the display register. When less than 60 segment outputs are required, the unused segment outputs must be left open-circuit.

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7.9 Backplane outputs

The LCD drive section includes four backplane outputs BP0 to BP3 which must be connected directly to the LCD. The backplane output signals are generated in accordance with the selected LCD drive mode.

• In 1:4 multiplex drive mode: BP0 to BP3 must be connected directly to the LCD.

If less than four backplane outputs are required, the unused outputs can be left open-circuit.

• In 1:3 multiplex drive mode BP3 carries the same signal as BP1, therefore these two adjacent outputs can be tied together to give enhanced drive capabilities.

• In 1:2 multiplex drive mode BP0 and BP2, respectively, BP1 and BP3 carry the same signals and can also be paired to increase the drive capabilities.

• In static drive mode, the same signal is carried by all four backplane outputs and they can be connected in parallel for very high drive requirements.

7.10 Display RAM

The display RAM is a static 60

 4-bit RAM which stores LCD data. A logic 1 in the RAM bit map indicates the on-state (V on(RMS)

) of the corresponding LCD element. Similarly, a logic 0 indicates the off-state (V off(RMS)

). For more information on V on(RMS)

and V off(RMS)

,

see Section 7.3

.

There is a one-to-one correspondence between

• the bits in the RAM bitmap and the LCD elements

• the RAM columns and the segment outputs

• the RAM rows and the backplane outputs.

The display RAM bit map,

Figure 12

, shows row 0 to row 3 which correspond with the backplane outputs BP0 to BP3, and column 0 to column 59 which correspond with the segment outputs S0 to S59. In multiplexed LCD applications, the data of each row of the display RAM is time-multiplexed with the corresponding backplane (row 0 with BP0, row 1 with BP1, and so on).

rows

0 display RAM rows/ backplane outputs

(BP)

1

2

0

3

1 2 columns

3 display RAM addresses/segment outputs (S)

4 55 56 57 58 59

013aaa212

The display RAM bit map shows the direct relationship between the display RAM addresses and the segment outputs and between the bits in a RAM word and the backplane outputs.

Fig 12. Display RAM bit map

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xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x x xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx drive mode static

LCD segments

S n+2

S n+3

S n+4

S n+5

S n+6 e f d g a c b

S n+1

BP0

S n

S n+7

DP

LCD backplanes rows display RAM rows/backplane outputs (BP)

0

1

2

3 n x x c x b x x x display RAM filling order columns display RAM address/segment outputs (s) byte1 n + 1 n + 2 n + 3 n + 4 n + 5 n + 6 n + 7 a x x x f x x x g x x x e x x x d x x x

DP x x x

1:2 multiplex

S n

S n+1 f a g

S n+2

S n+3 e d c b

DP

BP0

BP1 rows display RAM rows/backplane outputs (BP)

0

1

2

3 n x x a b x x f g columns display RAM address/segment outputs (s) byte1 byte2 n + 1 n + 2 n + 3 x x e c d

DP x x

1:3 multiplex

1:4 multiplex

S n+1

S n+2 f a g e c b

S n d DP

BP0

BP1

S n a f

S n+1 e d g c b

BP0

DP

BP1

BP2 columns byte1 display RAM address/segment outputs (s) byte2 byte3 rows display RAM rows/backplane outputs (BP)

0

1

2

3 n b

DP c x n + 1 n + 2 a d g x x x f e

BP2

BP3 rows display RAM rows/backplane outputs (BP)

0

1

2

3 n a c b

DP byte1 columns display RAM address/segment outputs (s) byte2 byte3 byte4 byte5 n + 1 f e g d transmitted display byte

MSB LSB c b a f g e d DP

MSB LSB a b f g e c d DP

MSB LSB b DP c a d g f e

MSB LSB a c b DP f e g d

001aaj646 x = data bit unchanged.

Fig 13. Relationship between LCD layout, drive mode, display RAM filling order and display data transmitted over the I 2 C-bus


PCF8534A


When display data is transmitted to the PCF8534A, the display bytes received are stored in the display RAM in accordance with the selected LCD multiplex drive mode. The data is stored as it arrives and depending on the current multiplex drive mode, data is stored singularly, in pairs, triples, or quadruples. To illustrate the filling order, an example of a

7-segment display showing all drive modes is given in

Figure 13

. The RAM filling organization depicted applies equally to other LCD types.

The following applies to

Figure 13

:

• In static drive mode the eight transmitted data bits are placed into row 0 as one byte.

• In 1:2 multiplex drive mode the eight transmitted data bits are placed in pairs into row 0 and row 1 as two successive 4-bit RAM words.

• In 1:3 multiplex drive mode the eight bits are placed in triples into row 0, row

1, and row 2 as three successive 3-bit RAM words, with bit 3 of the third address left unchanged. It is not recommended to use this bit in a display because of the difficult addressing. This last bit may, if necessary, be controlled by an additional transfer to this address. But care should be taken to avoid overwriting adjacent data because always full bytes are transmitted (see

Section 7.10.3

).

• In 1:4 multiplex drive mode, the eight transmitted data bits are placed in quadruples into row 0, row 1, row 2, and row 3 as two successive 4-bit RAM words.

7.10.1 Data pointer

The addressing mechanism for the display RAM is realized using the data pointer. This allows the loading of an individual display data byte, or a series of display data bytes, into any location of the display RAM. The sequence commences with the initialization of the data pointer by the load-data-pointer command (see

Table 12 ). Following this command,

an arriving data byte is stored at the display RAM address indicated by the data pointer.

The filling order is shown in Figure 13

. After each byte is stored, the content of the data pointer is automatically incremented by a value dependent on the selected LCD drive mode:

• In static drive mode by eight.

• In 1:2 multiplex drive mode by four.

• In 1:3 multiplex drive mode by three.

• In 1:4 multiplex drive mode by two.

If an I 2 C-bus data access terminates early, then the state of the data pointer is unknown.

Consequently, the data pointer must be rewritten before further RAM accesses.

7.10.2 Subaddress counter

The storage of display data is determined by the content of the subaddress counter.

Storage is allowed only when the content of the subaddress counter matches with the hardware subaddress applied to A0, A1, and A2. The subaddress counter value is defined

by the device-select command (see Table 13 ). If the content of the subaddress counter

and the hardware subaddress do not match, then data storage is inhibited but the data pointer is incremented as if data storage had taken place. The subaddress counter is also incremented when the data pointer overflows.

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In cascaded applications each PCF8534A in the cascade must be addressed separately.

Initially, the first PCF8534A is selected by sending the device-select command matching the first hardware subaddress. Then the data pointer is set to the preferred display RAM address by sending the load-data-pointer command.

Once the display RAM of the first PCF8534A has been written, the second PCF8534A is selected by sending the device-select command again. This time however the command matches the hardware subaddress of the second device. Next the load-data-pointer command is sent to select the preferred display RAM address of the second PCF8534A.

This last step is very important because during writing data to the first PCF8534A, the data pointer of the second PCF8534A is incremented. In addition, the hardware subaddress should not be changed while the device is being accessed on the I 2 C-bus interface.

7.10.3 RAM writing in 1:3 multiplex drive mode

In 1:3 multiplex drive mode, the RAM is written as shown in

Table 7

(see

Figure 13 as

well).

1

2

3

Table 7.

Standard RAM filling in 1:3 multiplex drive mode

Assumption: BP2/S2, BP2/S5, BP2/S8 etc. are not connected to any elements on the display.

Display RAM addresses (columns)/segment outputs (Sn) Display RAM bits (rows)/ backplane outputs (BPn)

0 1 2 3 4 5 6 7 8 9 :

0 a7 a4 a1 b7 b4 b1 c7 c4 c1 d7 :

a6 a5

a3 a2 -

a0

b6 b5

b3 b2 -

b0

c6 c5

c3 c2 -

c0

d6 d5 :

:

:

If the bit at position BP2/S2 would be written by a second byte transmitted, then the

mapping of the segment bits would change as illustrated in Table 8 .

1

2

3

Table 8.

Entire RAM filling by rewriting in 1:3 multiplex drive mode

Assumption: BP2/S2, BP2/S5, BP2/S8 etc. are connected to elements on the display.

Display RAM addresses (columns)/segment outputs (Sn) Display RAM bits (rows)/ backplane outputs (BPn)

0 1 2 3 4 5 6 7 8 9

0 a7 a4 a1/b7 b4 b1/c7 c4 c1/d7 d4 d1/e7 e4

a6 a5

a3 a2

a0/b6 b3 b5

b2

b0/c6 c3 c5

c2

c0/d6 d3 d5

d2

d0/e6 e3 e5

e2

:

:

:

:

:

In the case described in

Table 8 the RAM has to be written entirely and BP2/S2, BP2/S5,

BP2/S8, and so on, have to be connected to elements on the display. This can be achieved by a combination of writing and rewriting the RAM like follows:

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• In the first write to the RAM, bits a7 to a0 are written.

• In the second write, bits b7 to b0 are written, overwriting bits a1 and a0 with bits b7 and b6.

• In the third write, bits c7 to c0 are written, overwriting bits b1 and b0 with bits c7 and c6.

Depending on the method of writing to the RAM (standard or entire filling by rewriting), some elements remain unused or can be used. But it has to be considered in the module layout process as well as in the driver software design.

7.10.4 Bank selector

7.10.4.1

Output bank selector

The output bank selector (see

Table 14

) selects one of the four rows per display RAM address for transfer to the display register. The actual row selected depends on the particular LCD drive mode in operation and on the instant in the multiplex sequence.

• In 1:4 multiplex mode, all RAM addresses of row 0 are selected, these are followed by the contents of row 1, 2, and then 3

• In 1:3 multiplex mode, rows 0, 1, and 2 are selected sequentially

• In 1:2 multiplex mode, rows 0 and 1 are selected

• In static mode, row 0 is selected

The SYNC signal resets these sequences to the following starting points:

• row 3 for 1:4 multiplex



• row 0 for static mode

The PCF8534A includes a RAM bank switching feature in the static and 1:2 multiplex drive modes. In the static drive mode, the bank-select command may request the contents of row 2 to be selected for display instead of the contents of row 0. In the 1:2 multiplex mode, the contents of rows 2 and 3 may be selected instead of rows 0 and 1. This gives the provision for preparing display information in an alternative bank and to be able to switch to it once it is assembled.

7.10.4.2

Input bank selector

The input bank selector loads display data into the display data in accordance with the selected LCD drive configuration. Display data can be loaded in row 2 in static drive mode or in rows 2 and 3 in 1:2 multiplex drive mode by using the bank-select command (see

Table 14 ). The input bank selector functions independently to the output bank selector.

7.11 Blinking

The display blinking capabilities of the PCF8534A are very versatile. The whole display

can blink at frequencies selected by the blink-select command (see Table 15 ). The blink

frequencies are derived from the clock frequency. The ratio between the clock and blink frequency depends on the blink mode selected (see

Table 9

).

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Table 9.

Blink frequencies

Blink mode Operating mode ratio Blink frequency with respect to f clk

(typical) off -

f clk

= 1536 Hz blinking off

1 f blink

= f

---------

768

2

2

3 f blink

= f

------------

1536 f blink

= f

------------

3072

1

0.5

Unit

Hz

Hz

Hz

Hz

An additional feature is for an arbitrary selection of LCD segments to blink. This applies to the static and 1:2 multiplex drive modes and can be implemented without any communication overheads. With the output bank selector, the displayed RAM banks are exchanged with alternate RAM banks at the blink frequency. This mode can also be specified by the blink-select command.

In the 1:3 and 1:4 multiplex modes, where no alternate RAM bank is available, groups of

LCD elements can blink by selectively changing the display RAM data at fixed time intervals.

The entire display can blink at a frequency other than the nominal blink frequency. This can be effectively performed by resetting and setting the display enable bit E at the

required rate using the mode-set command (see Table 11 ).

7.12 Command decoder

The command decoder identifies command bytes that arrive on the I 2 C-bus. The

commands available to the PCF8534A are defined in Table 10 .

Table 10.

Definition of commands

Command Operation code

7 6 5 mode set load data pointer device select bank select blink select

1

0

1

1

1

1

P[6:0]

1

1

1

0

1

1

1

0

1

1

4

0

0

1

0

3

E

2

B

1

M[1:0]

0

A[2:0]

0 I

AB BF[1:0]

O

Reference

Table 11

Table 12

Table 13

Table 14

Table 15

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Table 11.

Mode-set command bit description

Bit Symbol Value Description

7 to 4 -

3 E

2

1 to 0

B

M[1:0]

1100

0

1

0

1

[1]

[1]

fixed value display status disabled (blank)

[2]

enable

LCD bias configuration [3]

1 ⁄

3

bias

1 ⁄

2

bias

LCD drive mode selection

01

10

11

00

[1]

static; one backplane

1:2 multiplex; two backplanes

1:3 multiplex; three backplanes

1:4 multiplex; four backplanes

[1] Default value.

[2] The possibility to disable the display allows implementation of blinking under external control.

[3] Not applicable for static drive mode.

Table 12.

Load data pointer command bit description

See

Section 7.10.1 on page 20

.

Bit

7 -

Symbol

6 to 0 P[6:0]

Value

0

0000000 [1]

to

0111011

Description fixed value

7-bit binary value, 0 to 59; transferred to the data pointer to define one of 60 display RAM addresses

[1] Default value.

Table 13.

Device select command bit description

See


.


7 to 3 -

2 to 0 A[2:0]

11100

000 [1]

to 111 fixed value

3-bit binary value, 0 to 7; transferred to the subaddress counter to define one of eight hardware subaddresses

[1] Default value.

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Table 14.

Bank select command bit description

See


.


Static

7 to 2

1

-

I

111110

0

1

[2]

1:2 multiplex [1]

fixed value

input bank selection: storage of arriving display data

RAM row 0 RAM rows 0 and 1

0 O

0

1

[2]


output bank selection: retrieval of LCD display data



[1] The bank select command has no effect in 1:3 or 1:4 multiplex drive modes.

[2] Default value.

Table 15.

Blink select command bit description

Section 7.11 on page 22

.


7 to 3 -

2 AB

1 to 0 BF[1:0]

11110

0

1

[1]

fixed value blink mode selection

normal blinking [2] alternate RAM bank blinking [3]

blink frequency selection

[4]

off 00

[1]

01

10

11

1

2

3

[1] Default value.

[2] Normal blinking is assumed when the LCD multiplex drive modes 1:3 or 1:4 are selected.

[3] Alternate RAM bank blinking does not apply in 1:3 and 1:4 multiplex drive modes.

[4] For the blink frequencies, see

Table 9

.

7.13 Display controller

The display controller executes the commands identified by the command decoder. It contains the status registers of the PCF8534A and coordinates their effects. The display controller is also responsible for loading display data into the display RAM in the correct filling order.

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8. Characteristics of the I

2

C-bus

The I 2 C-bus is for bidirectional, two-line communication between different ICs or modules.

The two lines are a Serial DAta Line (SDA) and a Serial CLock line (SCL). Both lines must be connected to a positive supply via a pull-up resistor when connected to the output stages of a device. Data transfer may be initiated only when the bus is not busy.

8.1 Bit transfer

One data bit is transferred during each clock pulse. The data on the SDA line must remain stable during the HIGH period of the clock pulse as changes in the data line at this time

will be interpreted as a control signal (see Figure 14

).

SDA

SCL data line stable; data valid change of data allowed mba607

Fig 14. Bit transfer

8.2 START and STOP conditions

Both data and clock lines remain HIGH when the bus is not busy.

A HIGH-to-LOW change of the data line, while the clock is HIGH, is defined as the START condition (S).

A LOW-to-HIGH change of the data line, while the clock is HIGH, is defined as the STOP condition (P).

The START and STOP conditions are illustrated in

Figure 15 .

SDA SDA

SCL

S

START condition

Fig 15. Definition of START and STOP conditions

SCL

P

STOP condition mbc622

8.3 System configuration

A device generating a message is a transmitter, a device receiving a message is the receiver. The device that controls the message is the master; and the devices which are controlled by the master are the slaves. The system configuration is shown in

Figure 16

.

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SDA

SCL

MASTER

TRANSMITTER/

RECEIVER

SLAVE

RECEIVER

SLAVE

TRANSMITTER/

RECEIVER

MASTER

TRANSMITTER

MASTER

TRANSMITTER/

RECEIVER mga807

Fig 16. System configuration

8.4 Acknowledge

The number of data bytes transferred between the START and STOP conditions from transmitter to receiver is unlimited. Each byte of 8 bits is followed by an acknowledge cycle.

• A slave receiver, which is addressed, must generate an acknowledge after the reception of each byte.

• A master receiver must generate an acknowledge after the reception of each byte that has been clocked out of the slave transmitter.

• The device that acknowledges must pull-down the SDA line during the acknowledge clock pulse, so that the SDA line is stable LOW during the HIGH period of the acknowledge related clock pulse (set-up and hold times must be considered).

• A master receiver must signal an end of data to the transmitter by not generating an acknowledge on the last byte that has been clocked out of the slave. In this event, the transmitter must leave the data line HIGH to enable the master to generate a STOP condition.

Acknowledgement on the I 2

C-bus is illustrated in Figure 17 .

data output by transmitter data output by receiver

SCL from master

1

S

START condition

Fig 17. Acknowledgement of the I 2 C-bus

2 not acknowledge acknowledge

8 9 clock pulse for acknowledgement mbc602

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8.5 I 2 C-bus controller

The PCF8534A acts as an I 2 C-bus slave receiver. It does not initiate I 2 C-bus transfers or transmit data to an I 2 C-bus master receiver. The only data output from the PCF8534A are the acknowledge signals of the selected devices. Device selection depends on the

I 2 C-bus slave address, on the transferred command data and on the hardware subaddress.

In single device applications, the hardware subaddress inputs A0, A1, and A2 are normally tied to V

SS

which defines the hardware subaddress 0. In multiple device applications A0, A1, and A2 are tied to V

SS

or V

DD

using a binary coding scheme, so that no two devices with a common I 2 C-bus slave address have the same hardware subaddress.

8.6 Input filters

To enhance noise immunity in electrically adverse environments, RC low-pass filters are provided on the SDA and SCL lines.

8.7 I 2 C-bus protocol

Two I 2 C-bus slave addresses (0111 000 and 0111 001) are used to address the

PCF8534A. The entire I 2 C-bus slave address byte is shown in

Table 16

.

Table 16.

I 2 C slave address byte

Slave address

Bit 6 5 7

MSB

0 1 1

4

1

3

0

2

0

1

SA0

0

LSB

R/W

The PCF8534A is a write-only device and does not respond to a read access, therefore bit 0 should always be logic 0. Bit 1 of the slave address byte, that a PCF8534A will respond to, is defined by the level tied to its SA0 input (V

SS

for logic 0 and V

DD

for logic 1).

Having two reserved slave addresses allows the following on the same I 2 C-bus:

• Up to 16 PCF8534A for large LCD applications

• The use of two types of LCD multiplex drive

The I 2 C-bus protocol is shown in

Figure 18 . The sequence is initiated with a START

condition (S) from the I 2 C-bus master which is followed by one of the available PCF8534A slave addresses. All PCF8534A with the same SA0 level acknowledge in parallel to the slave address. All PCF8534A with the alternative SA0 level ignore the whole I 2 C-bus transfer.

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R/W = 0 slave address

S 0 1 1 1 0 0

S

A

0

0 A

C

O

R

S control byte

A

M

S

B

RAM/command byte

L

S

B

P

EXAMPLES a) transmit two bytes of RAM data

S 0 1 1 1 0 0

S

A

0

0 A 0 1 A RAM DATA A RAM DATA A P b) transmit two command bytes

S 0 1 1 1 0 0

S

A

0

0 A 1 0 A COMMAND A 0 0 A COMMAND A P c) transmit one command byte and two RAM date bytes

S 0 1 1 1 0 0

S

A

0

0 A 1 0 A COMMAND A 0 1 A RAM DATA A RAM DATA A P mgl752

Fig 18. I 2 C-bus protocol

After acknowledgement, the control byte is sent defining if the next byte is a RAM or command information. The control byte also defines if the next byte is a control byte or

further RAM or command data (see Figure 19

and

Table 17

). In this way it is possible to configure the device and then fill the display RAM with little overhead.

MSB

7

CO

6

RS

5 4 3 2 not relevant

1 0

LSB mgl753

Fig 19. Control byte format

PCF8534A


Table 17.

Control byte description

Bit

7

Symbol

CO

Value Description continue bit

6

5 to 0 -

RS

0

1

0

1 last control byte control bytes continue register selection command register data register unused

The command bytes and control bytes are also acknowledged by all addressed

PCF8534A connected to the bus.

The display bytes are stored in the display RAM at the address specified by the data pointer and the subaddress counter. Both data pointer and subaddress counter are automatically updated.


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The acknowledgement after each byte is made only by the (A0, A1 and A2) addressed

PCF8534A. After the last display byte, the I 2 C-bus master issues a STOP condition (P).

Alternatively a START may be issued to RESTART I 2 C-bus access.

V

DD

SA0

V

SS

V

DD

CLK

V

SS

V

DD

OSC

V

SS

V

DD

SYNC

V

SS

V

DD

A0, A1, A2

V

SS

V

LCD

BP0, BP1,

BP2, BP3

V

SS

V

LCD

S0 to S59

Fig 20. Device protection diagram

V

SS

V

SS

V

SS

V

SS

V

DD

V

SS

SCL

SDA

V

LCD

001aah615

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10. Limiting values

CAUTION

Static voltages across the liquid crystal display can build up when the LCD supply voltage

(V

LCD

) is on while the IC supply voltage (V

DD

) is off, or vice versa. This may cause unwanted display artifacts. To avoid such artifacts, V

LCD

and V

DD

must be applied or removed together.

Table 18.

Limiting values

In accordance with the Absolute Maximum Rating System (IEC 60134).

Symbol Parameter Conditions

I

I

SS

V

I

I

I

V

O

V

DD

I

DD

V

LCD

I

DD(LCD)

O

P tot

P/out supply voltage supply current

LCD supply voltage

LCD supply current ground supply current input voltage input current output voltage output current total power dissipation power dissipation per output

[1]

[1]

[1]

[2]

[1][2]

Min

0.5

50

0.5

50

50

0.5

10

0.5

0.5

10

-

-

I

V

T

T lu

ESD stg amb electrostatic discharge voltage latch-up current storage temperature ambient temperature

HBM

CDM operating device

[3]

-

[4]

-

[5]

[6]

-

65

40

Max

+6.5

+50

+7.5

+50

+50

+6.5

+10

+6.5

+7.5

+10

400

100

3000

1000

200

+150

+85

V

V mA

C

C

[1] Pins SDA, SCL, CLK, SYNC, SA0, OSC, and A0 to A2.

[2] Pins S0 to S59 and BP0 to BP3.

[3]

Pass level; Human Body Model (HBM), according to Ref. 5 “JESD22-A114” .

[4]

Pass level; Charged-Device Model (CDM), according to Ref. 6 “JESD22-C101”

.

[5] Pass level; latch-up testing according to

Ref. 7 “JESD78”

at maximum ambient temperature (T amb(max)

).

[6] According to the NXP store and transport requirements (see

Ref. 9 “NX3-00092” ) the devices have to be

stored at a temperature of +8

C to +45 C and a humidity of 25 % to 75 %. For long-term storage products deviant conditions are described in that document.

mA

V

V mA mW mW

Unit

V mA

V mA mA

V

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11. Static characteristics

V

IH

I

OL

I

L

C i

Table 19.

Static characteristics

V

DD

= 1.8 V to 5.5 V; V

SS

= 0 V; V

LCD

= 2.5 V to 6.5 V; T amb

=



40



C to +85



C; unless otherwise specified.

Symbol Parameter Conditions Min Typ Max

Supplies

V

DD

V

LCD supply voltage

LCD supply voltage

I

DD supply current

I

DD(LCD)

LCD supply current

Logic

V

I

V

IL input voltage

LOW-level input voltage f clk

= 1536 Hz f clk

= 1536 Hz

1.8

[1]

-

2.5

[1]

-

-

-

-

8

24

5.5

6.5

20

60

Unit

V

DD

+ 0.5 V

0.3V

DD

V

V

V

A

A

V

IH

V

POR

I

OL

I

OH

I

L

HIGH-level input voltage power-on reset voltage

LOW-level output current

HIGH-level output current leakage current on pins CLK, SYNC, OSC, A0 to A2 and SA0 on pins CLK, SYNC, OSC, A0 to A2 and SA0

V

SS

 0.5

V

SS

0.7V

V

OL

= 0.4 V; V

DD

= 5 V; on pins CLK and SYNC

V

OH

= 4.6 V; V

DD

= 5 V; on pin CLK

V

I

= V

DD

or V

SS

; on pins SA0, A0 to

A2 and CLK

V

I

= V

DD

; on pin OSC

1.0

1

1

1

[2]

-

1

DD

-

-

-

-

-

-

1.3

V

DD

-

1.6

-

+1

+1

7

V

V mA mA

A

A pF C

I input capacitance

I 2

C-bus; pins SDA and SCL [3]

V

I

V

IL input voltage

LOW-level input voltage

HIGH-level input voltage

LOW-level output current leakage current input capacitance pin SCL pin SDA

V

OL

= 0.4 V; V

DD

= 5 V; on pin SDA

V

I

= V

DD

or V

SS

[2]

-

3

1

V

SS

 0.5

-

V

SS

-

V

SS

0.7V

DD

-

-

-

-

-

-

+1

7

5.5

0.3V

DD

0.2V

DD

5.5

V

V

V

V mA

A pF

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PCF8534A


Table 19.

Static characteristics …continued

V

DD

= 1.8 V to 5.5 V; V

SS

= 0 V; V

LCD

= 2.5 V to 6.5 V; T amb

=



40



C to +85





LCD outputs

Output pins BP0, BP1, BP2 and BP3

V

BP voltage on pin BP

R

BP resistance on pin BP

Output pins S0 to S59

V

S

R

S voltage on pin S resistance on pin S

C bpl

= 35 nF

V

LCD

= 5 V

C sgm

= 35 nF

V

LCD

= 5 V

[4]

100

[5]

-

[6]

100

[5]

-

-

1.5

-

6.0

+100

10

+100

13.5

[1] LCD outputs are open circuit; inputs at V

SS

or V

DD

; external clock with 50 % duty factor; I

2

C-bus inactive.

[2] Not tested, design specification only.

[3] The I

2

C-bus interface of PCF8534A is 5 V tolerant.

[4] C bpl

= backplane capacitance.

[5] Outputs measured individually and sequentially.

[6] C sgm

= segment capacitance.

Unit mV k

 mV k



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PCF8534A


12. Dynamic characteristics

Table 20.

Dynamic characteristics

V

DD

= 1.8 V to 5.5 V; V

SS

= 0 V; V

LCD

= 2.5 V to 6.5 V; T amb

=



40



C to +85





Clock

Internal: output pin CLK f osc oscillator frequency

External: input pin CLK f clk(ext) external clock frequency t clk(H)

HIGH-level clock time t clk(L)

LOW-level clock time

Synchronization: input pin SYNC t

PD(SYNC_N) t

SYNC_NL

SYNC propagation delay

SYNC LOW time

Outputs: pins BP0 to BP3 and S0 to S59 t

PD(drv) driver propagation delay

I 2

C-bus: timing [2]

Pin SCL

SCL frequency f

SCL t

LOW t

HIGH

Pin SDA

LOW period of the SCL clock

HIGH period of the SCL clock t

SU;DAT t

HD;DAT data set-up time data hold time

Pins SCL and SDA t

BUF bus free time between a STOP and

START condition set-up time for STOP condition t

SU;STO t

HD;STA t

SU;STA hold time (repeated) START condition set-up time for a repeated START condition rise time of both SDA and SCL signals t r t f

C b t w(spike) fall time of both SDA and SCL signals capacitive load for each bus line spike pulse width

V

DD

= 5 V

V

DD

= 5 V

V

LCD

= 5 V

[1]

960

-

-

-

-

-

-

1

797

130

130

-

1.3

0.6

100

0

1.3

0.6

0.6

0.6

-

-

-

-

-

-

-

-

-

-

-

-

-

-

1536

-

-

1536

-

30

-

-

-

-

-

-

-

-

3046

-

-

3046

30

-

-

400

0.3

0.3

400

50

Unit

Hz

s

s pF ns

Hz

s

s ns

s

s kHz

s

s ns ns

s

s

s

s

[1] Typical output (duty cycle

 = 50 %).

[2] All timing values are valid within the operating supply voltage and ambient temperature range and are referenced to V

IL

and V

IH

with an input voltage swing of V

SS

to V

DD

.

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CLK

PCF8534A

Universal LCD driver for low multiplex rates t clk(H)

1 / f clk t clk(L)

0.7V

DD

0.3V

DD

SYNC

BP0 to BP3, and S0 to S59 t

PD(SYNC_N)

Fig 21. Driver timing waveforms

SDA t

BUF t

LOW

SCL t

HD;STA t r

SDA t

SU;STA t

HD;DAT t t

SYNC_NL

PD(drv)

0.7V

DD

0.3V

DD t

PD(SYNC_N)

001aah618

0.5 V

(V

DD

= 5 V)

0.5 V t

HIGH t f t

SU;DAT t

SU;STO mga728

Fig 22. I 2 C-bus timing waveforms

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PCF8534A


13. Application information

13.1 Cascaded operation

Large display configurations of up to 16 PCF8534As can be recognized on the same

I 2 C-bus by using the 3-bit hardware subaddress (A0, A1 and A2) and the programmable

I 2 C-bus slave address (SA0).

Table 21.

Addressing cascaded PCF8534A

Cluster

1

Bit SA0

0

Pin A2

0

0

1

0

0

2 1

0

1

0

0

1

0

1

1

1

1

1

0

1

1

0

1

0

1

1

0

0

1

1

0

0

1

Pin A1

0

1

0

1

0

1

1

0

1

0

1

0

1

0

1

0

Pin A0

0

When cascaded PCF8534A are synchronized, they can share the backplane signals from one of the devices in the cascade. Such an arrangement is cost-effective in large LCD applications since the backplane outputs of only one device need to be through-plated to the backplane electrodes of the display. The other PCF8534A of the cascade contribute additional segment outputs, but their backplane outputs are left open-circuit

(see

Figure 23 ).

11

12

13

14

15

7

8

9

10

5

6

3

4

1

2

Device

0

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PCF8534A


PCF8534A


V

DD

V

LCD

SDA

SCL

SYNC

CLK

OSC

PCF8534A

(2)

60 segment drives

BP0 to BP3

(open-circuit)

A0 A1 A2 SA0 V

SS

LCD PANEL

V

LCD

V

DD t r

R ≤

2C b

HOST

MICRO-

PROCESSOR/

MICRO-

CONTROLLER

SDA

SCL

SYNC

CLK

OSC

VDD VLCD

60 segment drives

PCF8534A

(1)

4 backplanes

BP0 to BP3

A0 A1 A2 SA0 V

SS

V

SS

013aaa513

(1) Is master (OSC connected to V

SS

).

(2) Is slave (OSC connected to V

DD

).

Fig 23. Cascaded PCF8534A configuration

The SYNC line is provided to maintain the correct synchronization between all cascaded

PCF8534A. Synchronization is guaranteed after a power-on reset. The only time that

SYNC is likely to be needed is if synchronization is accidentally lost (for example, by noise in adverse electrical environments or by defining a multiplex drive mode when PCF8534A with different SA0 levels are cascaded).

SYNC is organized as an input/output pin. The output selection is realized as an open-drain driver with an internal pull-up resistor. A PCF8534A asserts the SYNC line at the onset of its last active backplane signal and monitors the SYNC line at all other times.

If synchronization in the cascade is lost, it is restored by the first PCF8534A to assert

SYNC. The timing relationship between the backplane waveforms and the SYNC signal

for the various drive modes of the PCF8534A are shown in Figure 24 .

The contact resistance between the SYNC on each cascaded device must be controlled.

If the resistance is too high, the device is not able to synchronize properly; this is applicable to chip-on-glass applications. The maximum SYNC contact resistance allowed

for the number of devices in cascade is given in Table 22 .


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PCF8534A


Table 22.

SYNC contact resistance

Number of devices

2

3 to 5

6 to 10

11 to 16

Maximum contact resistance

6000



2200



1200



700



The PCF8534A can always be cascaded with other devices of the same type or conditionally with other devices of the same family. This allows optimal drive selection for

a given number of pixels to display. Figure 22 and

Figure 24

show the timing of the synchronization signals.

T fr

=

1 f fr

BP0

SYNC

(a) static drive mode.

BP0

(1/2 bias)

BP0

(1/3 bias)

SYNC

(b) 1:2 multiplex drive mode.

BP0

(1/3 bias)

SYNC

(c) 1:3 multiplex drive mode.

BP0

(1/3 bias)

SYNC

(d) 1:4 multiplex drive mode.

mgl755

Fig 24. Synchronization of the cascade for various PCF8534A drive modes

In a cascaded configuration, only one PCF8534A master must be used as clock source.

All other PCF8534A in the cascade must be configured as slave such that they receive the clock from the master.

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PCF8534A


If an external clock source is used, all PCF8534A in the cascade must be configured such as to receive the clock from that external source (pin OSC connected to V

DD

). It must be ensured that the clock tree is designed such that on all PCF8534A the clock propagation delay from the clock source to all PCF8534A in the cascade is as equal as possible since otherwise synchronization artifacts may occur.

In mixed cascading configurations, care has to be taken that the specifications of the individual cascaded devices are met at all times.

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PCF8534A


14. Package outline

LQFP80: plastic low profile quad flat package; 80 leads; body 12 x 12 x 1.4 mm SOT315-1 c y

X

A

61

60 41

40 Z E

80

1 e pin 1 index b p

D

H

D w M e

E

H

E w

M b p

20

Z D

21 v

M A

B v

M B

A

A

2

A

1 detail X

L

L p

θ

0 5 scale

10 mm

DIMENSIONS (mm are the original dimensions)

UNIT

A max.

A

1

A

2

A

3 b p c mm 1.6

0.16

0.04

1.5

1.3

0.25

0.27

0.13

0.18

0.12

D

(1)

E

(1)

12.1

11.9

12.1

11.9

e H

D

H

E

0.5

14.15

13.85

14.15

13.85

L

1

Note

1. Plastic or metal protrusions of 0.25 mm maximum per side are not included.

L p

0.75

0.30

v

0.2

w y

0.15

0.1

Z

D

(1)

Z

E

(1)

1.45

1.05

1.45

1.05

θ

7 o o

0

OUTLINE

VERSION

SOT315-1

IEC

136E15

REFERENCES

JEDEC JEITA

MS-026

EUROPEAN

PROJECTION

ISSUE DATE

00-01-19

03-02-25

Fig 25. Package outline SOT315-1 (LQFP80)

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15. Bare die outline

Wire bond die; 76 bonding pads; 2.91 x 2.62 x 0.38 mm

D

64

C1

63 e

PC8534A-1

(3)

44

C2

43 e

PCF8534A


A

PCF8534AU

76

1 x

0

0 y

E

3

F

4

X

0 0.5

scale

DIMENSIONS (mm are the original dimensions) mm

UNIT max nom min

A

0.38

D

2.91

E

2.62

e

0.08

P

1

(1)

P

2

(2)

P

3

(1)

P

4

(2)

0.06

0.05

0.10

0.09

Notes

1. Pad size

2. Passivation opening

3. Marking code

OUTLINE

VERSION IEC

REFERENCES

JEDEC JEITA

PCF8534AU

Fig 26. PCF8534AU die outline

PCF8534A


23

1 mm


Rev. 6 — 25 July 2011

24

EUROPEAN

PROJECTION

P

2

P

1 detail X

P

4

P

3

ISSUE DATE

08-08-06


41 of 52


PCF8534A


PCF8534A


Table 23.

Bonding pad locations

Symbol

SDA

SCL

CLK

V

SYNC

OSC

A0

A1

A2

SA0

V

V

DD

SS

LCD

S0

S1

S2

S3

S4

S5

S6

S7

S8

S9

S10

S11

S12

S13

S14

S15

S16

S17

S18

S19

S20

S21

Pad Coordinates

[1]

1

2

3

4

5

6

7

8

9

10

11

X (

m)

1384.4

1384.4

1384.4

978.7

829.3

714.3

584.3

454.3

324.3

194.3

64.3

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

28

29

30

31

32

33

34

68.7

173.7

253.7

333.7

413.7

493.7

573.7

653.7

733.7

813.7

893.7

973.7

1384.4

1384.4

1384.4

1384.4

1384.4

1384.4

1384.4

1384.4

1384.4

1384.4

1384.4

841

761

681

601

521

441

361

281

1238

1238

1238

1238

1238

1238

1238

1238

201

121

41

1238

1238

1238

1238

1238

1238

1238

1238

Y (

m)

280

760.5

945

1238

1238

1238

1238

S22 35 1384.4

39

S23

S24

36

37

1384.4

1384.4

119

301.6

S25

S26

S27

38

39

40

1384.4

1384.4

1384.4

381.6

461.6

541.6

I

Description

I 2

I 2

2

C-bus serial data input and output

C-bus serial clock input external clock input and output supply voltage cascade synchronization input and output enable input for internal oscillator subaddress counter input

C-bus slave address input 0 ground input of LCD supply voltage

LCD segment output


Rev. 6 — 25 July 2011


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PCF8534A


S51

S52

S53

S54

S55

S56

S57

S58

S43

S44

S45

S46

S47

S48

S49

S50

S35

S36

S37

S38

S39

S40

S41

S42

S59

BP0

BP1

BP2

BP3

Table 23.

Bonding pad locations …continued

Symbol Pad Coordinates [1]

X (

m)

Y (

m)

Description

S28 41 1384.4

621.6

LCD segment output

S29

S30

42

43

1384.4

1384.4

701.6

781.6

S31

S32

S33

S34

44

45

46

47

896.5

816.5

736.5

576.5

1239.4

1239.4

1239.4

1239.4

48

49

50

51

52

53

54

55

56

57

58

59

60

61

62

63

64

65

66

67

68

69

70

71

72

73

74

75

76

496.5

416.5

336.5

256.5

176.5

96.5

16.5

63.5

143.5

223.5

303.5

463.5

543.5

623.5

703.5

783.5

1384.4

1384.4

1384.4

1384.4

1384.4

1384.4

1384.4

1384.4

1384.4

1384.4

1384.4

1384.4

1384.4

1239.4

1239.4

1239.4

1239.4

1239.4

1239.4

1239.4

1239.4

1239.4

1239.4

1239.4

1239.4

1239.4

1239.4

1239.4

1239.4

935

855

775

695

615

535

375

295

215

125

45

35

115

LCD backplane output

[1] All coordinates are referenced in

m to the center of the die (see

Figure 26

).

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PCF8534A


REF

REF

C1

REF

C2

F 001aai649

Fig 27. Alignment marks

Table 24.

Alignment mark locations

[1]

Symbol

C1

X (

m)

1387

C2

F

1335

1345

Y (

m)

1190

1242

1173

[1] All coordinates are referenced in

m to the center of the die (see

Figure 26

).

16. Handling information

All input and output pins are protected against ElectroStatic Discharge (ESD) under normal handling. When handling Metal-Oxide Semiconductor (MOS) devices ensure that all normal precautions are taken as described in JESD625-A, IEC 61340-5 or equivalent standards.

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17. Packing information

1.1

1.2

1.3

2.1

2.2

3.1

PCF8534A


A C x.1

D

F

1.y

y x

Fig 28. Tray details for PCF8534AU/DA/1

E

B

001aai625

PC8534A-1

PCF8534A


Fig 29. Tray alignment for PCF8534AU/DA/1


Rev. 6 — 25 July 2011

001aai650


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PCF8534A


E

F

N

M

Table 25.

Tray dimensions

Symbol Description

C

D

A

B pocket pitch in x direction pocket pitch in y direction pocket width in x direction pocket width in y direction tray width in x direction tray width in y direction number of pockets, x direction number of pockets, y direction

8

9

Value

5.5 mm

4.9 mm

3.08 mm

2.79 mm

50.8 mm

50.8 mm

18. Soldering of SMD packages

This text provides a very brief insight into a complex technology. A more in-depth account of soldering ICs can be found in Application Note AN10365 “Surface mount reflow

soldering description”.

18.1 Introduction to soldering

Soldering is one of the most common methods through which packages are attached to

Printed Circuit Boards (PCBs), to form electrical circuits. The soldered joint provides both the mechanical and the electrical connection. There is no single soldering method that is ideal for all IC packages. Wave soldering is often preferred when through-hole and

Surface Mount Devices (SMDs) are mixed on one printed wiring board; however, it is not suitable for fine pitch SMDs. Reflow soldering is ideal for the small pitches and high densities that come with increased miniaturization.

18.2 Wave and reflow soldering

Wave soldering is a joining technology in which the joints are made by solder coming from a standing wave of liquid solder. The wave soldering process is suitable for the following:

• Through-hole components

• Leaded or leadless SMDs, which are glued to the surface of the printed circuit board

Not all SMDs can be wave soldered. Packages with solder balls, and some leadless packages which have solder lands underneath the body, cannot be wave soldered. Also, leaded SMDs with leads having a pitch smaller than ~0.6 mm cannot be wave soldered, due to an increased probability of bridging.

The reflow soldering process involves applying solder paste to a board, followed by component placement and exposure to a temperature profile. Leaded packages, packages with solder balls, and leadless packages are all reflow solderable.

Key characteristics in both wave and reflow soldering are:

• Board specifications, including the board finish, solder masks and vias

• Package footprints, including solder thieves and orientation

• The moisture sensitivity level of the packages

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PCF8534A


• Package placement

• Inspection and repair

• Lead-free soldering versus SnPb soldering

18.3 Wave soldering

Key characteristics in wave soldering are:

• Process issues, such as application of adhesive and flux, clinching of leads, board transport, the solder wave parameters, and the time during which components are exposed to the wave

• Solder bath specifications, including temperature and impurities

PCF8534A


18.4 Reflow soldering

Key characteristics in reflow soldering are:

• Lead-free versus SnPb soldering; note that a lead-free reflow process usually leads to higher minimum peak temperatures (see Figure 30 ) than a SnPb process, thus reducing the process window

• Solder paste printing issues including smearing, release, and adjusting the process window for a mix of large and small components on one board

• Reflow temperature profile; this profile includes preheat, reflow (in which the board is heated to the peak temperature) and cooling down. It is imperative that the peak temperature is high enough for the solder to make reliable solder joints (a solder paste characteristic). In addition, the peak temperature must be low enough that the packages and/or boards are not damaged. The peak temperature of the package depends on package thickness and volume and is classified in accordance with

Table 26 and 27

Table 26.

SnPb eutectic process (from J-STD-020C)

Package thickness (mm) Package reflow temperature (

C)

Volume (mm 3 )

< 350

 350

< 2.5

 2.5

235

220

220

220

Table 27.

Lead-free process (from J-STD-020C)

Package thickness (mm) Package reflow temperature (

C)

Volume (mm 3 )

< 350 350 to 2000

< 1.6

1.6 to 2.5

> 2.5

260

260

250

260

250

245

> 2000

260

245

245

Moisture sensitivity precautions, as indicated on the packing, must be respected at all times.

Studies have shown that small packages reach higher temperatures during reflow soldering, see Figure 30 .


Rev. 6 — 25 July 2011


47 of 52


PCF8534A

Universal LCD driver for low multiplex rates temperature maximum peak temperature

= MSL limit, damage level minimum peak temperature

= minimum soldering temperature peak

temperature time

001aac844

MSL: Moisture Sensitivity Level

Fig 30. Temperature profiles for large and small components

For further information on temperature profiles, refer to Application Note AN10365

“Surface mount reflow soldering description”.

19. Abbreviations

Table 28.

Abbreviations

Acronym Description

CMOS

ESD

HBM

IC

Complementary Metal-Oxide Semiconductor

ElectroStatic Discharge

Human Body Model

Integrated Circuit

LCD

MM

RAM

Liquid Crystal Display

Machine Model

Random Access Memory

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PCF8534A


20. References

[1] AN10365 — Surface mount reflow soldering description

[2] IEC 60134 — Rating systems for electronic tubes and valves and analogous semiconductor devices

[3] IEC 61340-5 — Protection of electronic devices from electrostatic phenomena

[4] IPC/JEDEC J-STD-020D — Moisture/Reflow Sensitivity Classification for

Nonhermetic Solid-State Surface Mount Devices

[5] JESD22-A114 — Electrostatic Discharge (ESD) Sensitivity Testing Human Body

Model (HBM)

[6] JESD22-C101 — Field-Induced Charged-Device Model Test Method for

Electrostatic-Discharge-Withstand Thresholds of Microelectronic Components

[7] JESD78 — IC Latch-Up Test

[8] JESD625-A — Requirements for Handling Electrostatic-Discharge-Sensitive

(ESDS) Devices

[9] NX3-00092 — NXP store and transport requirements

[10] SNV-FA-01-02 — Marking Formats Integrated Circuits

[11] UM10204 — I 2 C-bus specification and user manual

21. Revision history

Table 29.

Revision history

Document ID

PCF8534A v.6

Modifications:

PCF8534A_5

Release date Data sheet status Change notice

20110725 Product data sheet -

•

Added design-in and replacement part information

•

Changed description of

Table 17

•

Added

Section 7.10.3

20090806 Product data sheet -

PCF8534A_4

PCF8534A_3

PCF8534A_2

PCF8534A_1

20090716

20081110

20080604

20080423

Product data sheet

Product data sheet

Product data sheet

Product data sheet -

-

-

-

Supersedes

PCF8534A_5

PCF8534A_4

PCF8534A_3

PCF8534A_2

-

PCF8534A_1

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22. Legal information

Document status

[1][2]

Objective [short] data sheet

Product status

[3]

Development

Preliminary [short] data sheet Qualification

Product [short] data sheet Production

Definition

This document contains data from the objective specification for product development.

This document contains data from the preliminary specification.

This document contains the product specification.

[1] Please consult the most recently issued document before initiating or completing a design.

[2] The term ‘short data sheet’ is explained in section “Definitions”.

[3] The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status information is available on the Internet at URL http://www.nxp.com

.

22.2 Definitions

Draft — The document is a draft version only. The content is still under internal review and subject to formal approval, which may result in modifications or additions. NXP Semiconductors does not give any representations or warranties as to the accuracy or completeness of information included herein and shall have no liability for the consequences of use of such information.

Short data sheet — A short data sheet is an extract from a full data sheet with the same product type number(s) and title. A short data sheet is intended for quick reference only and should not be relied upon to contain detailed and full information. For detailed and full information see the relevant full data sheet, which is available on request via the local NXP Semiconductors sales office. In case of any inconsistency or conflict with the short data sheet, the full data sheet shall prevail.

Product specification — The information and data provided in a Product data sheet shall define the specification of the product as agreed between

NXP Semiconductors and its customer, unless NXP Semiconductors and customer have explicitly agreed otherwise in writing. In no event however, shall an agreement be valid in which the NXP Semiconductors product is deemed to offer functions and qualities beyond those described in the

Product data sheet.

22.3 Disclaimers

Limited warranty and liability — Information in this document is believed to be accurate and reliable. However, NXP Semiconductors does not give any representations or warranties, expressed or implied, as to the accuracy or completeness of such information and shall have no liability for the consequences of use of such information.

In no event shall NXP Semiconductors be liable for any indirect, incidental, punitive, special or consequential damages (including - without limitation - lost profits, lost savings, business interruption, costs related to the removal or replacement of any products or rework charges) whether or not such damages are based on tort (including negligence), warranty, breach of contract or any other legal theory.

Notwithstanding any damages that customer might incur for any reason whatsoever, NXP Semiconductors’ aggregate and cumulative liability towards customer for the products described herein shall be limited in accordance with the Terms and conditions of commercial sale of NXP Semiconductors.

Right to make changes — NXP Semiconductors reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice. This document supersedes and replaces all information supplied prior to the publication hereof.

Suitability for use in automotive applications — This NXP

Semiconductors product has been qualified for use in automotive applications. The product is not designed, authorized or warranted to be

PCF8534A



Rev. 6 — 25 July 2011 suitable for use in medical, military, aircraft, space or life support equipment, nor in applications where failure or malfunction of an NXP Semiconductors product can reasonably be expected to result in personal injury, death or severe property or environmental damage. NXP Semiconductors accepts no liability for inclusion and/or use of NXP Semiconductors products in such equipment or applications and therefore such inclusion and/or use is at the customer’s own risk.

Applications — Applications that are described herein for any of these products are for illustrative purposes only. NXP Semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification.

Customers are responsible for the design and operation of their applications and products using NXP Semiconductors products, and NXP Semiconductors accepts no liability for any assistance with applications or customer product design. It is customer’s sole responsibility to determine whether the NXP

Semiconductors product is suitable and fit for the customer’s applications and products planned, as well as for the planned application and use of customer’s third party customer(s). Customers should provide appropriate design and operating safeguards to minimize the risks associated with their applications and products.

NXP Semiconductors does not accept any liability related to any default, damage, costs or problem which is based on any weakness or default in the customer’s applications or products, or the application or use by customer’s third party customer(s). Customer is responsible for doing all necessary testing for the customer’s applications and products using NXP

Semiconductors products in order to avoid a default of the applications and the products or of the application or use by customer’s third party customer(s). NXP does not accept any liability in this respect.

Limiting values — Stress above one or more limiting values (as defined in the Absolute Maximum Ratings System of IEC 60134) will cause permanent damage to the device. Limiting values are stress ratings only and (proper) operation of the device at these or any other conditions above those given in the Recommended operating conditions section (if present) or the

Characteristics sections of this document is not warranted. Constant or repeated exposure to limiting values will permanently and irreversibly affect the quality and reliability of the device.

Terms and conditions of commercial sale — NXP Semiconductors products are sold subject to the general terms and conditions of commercial sale, as published at http://www.nxp.com/profile/terms , unless otherwise agreed in a valid written individual agreement. In case an individual agreement is concluded only the terms and conditions of the respective agreement shall apply. NXP Semiconductors hereby expressly objects to applying the customer’s general terms and conditions with regard to the purchase of NXP Semiconductors products by customer.

No offer to sell or license — Nothing in this document may be interpreted or construed as an offer to sell products that is open for acceptance or the grant, conveyance or implication of any license under any copyrights, patents or other industrial or intellectual property rights.


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Export control — This document as well as the item(s) described herein may be subject to export control regulations. Export might require a prior authorization from national authorities.

Bare die — All die are tested on compliance with their related technical specifications as stated in this data sheet up to the point of wafer sawing and are handled in accordance with the NXP Semiconductors storage and transportation conditions. If there are data sheet limits not guaranteed, these will be separately indicated in the data sheet. There are no post-packing tests performed on individual die or wafers.

NXP Semiconductors has no control of third party procedures in the sawing, handling, packing or assembly of the die. Accordingly, NXP Semiconductors assumes no liability for device functionality or performance of the die or systems after third party sawing, handling, packing or assembly of the die. It is the responsibility of the customer to test and qualify their application in which the die is used.

All die sales are conditioned upon and subject to the customer entering into a written die sale agreement with NXP Semiconductors through its legal department.

22.4 Trademarks

Notice: All referenced brands, product names, service names and trademarks are the property of their respective owners.

I

2

C-bus — logo is a trademark of NXP B.V.

23. Contact information

For more information, please visit: http://www.nxp.com

For sales office addresses, please send an email to: [email protected]

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24. Contents

1

2

3

4

5

6

6.1

6.2

General description . . . . . . . . . . . . . . . . . . . . . . 1

Features and benefits . . . . . . . . . . . . . . . . . . . . 1

Ordering information . . . . . . . . . . . . . . . . . . . . . 2

Marking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2

Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 3

Pinning information . . . . . . . . . . . . . . . . . . . . . . 4

Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4

Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 6

7 Functional description . . . . . . . . . . . . . . . . . . . 7

7.4.4

7.5

7.5.1

7.5.2

7.6

7.7

7.8

7.9

7.1

7.2

7.3

7.3.1

7.4

7.4.1

7.4.2

7.4.3

Power-On Reset (POR) . . . . . . . . . . . . . . . . . . 8

LCD bias generator . . . . . . . . . . . . . . . . . . . . . 8

LCD voltage selector . . . . . . . . . . . . . . . . . . . . 9

Electro-optical performance . . . . . . . . . . . . . . 10

LCD drive mode waveforms . . . . . . . . . . . . . . 12

Static drive mode . . . . . . . . . . . . . . . . . . . . . . 12

1:2 Multiplex drive mode. . . . . . . . . . . . . . . . . 13



Oscillator. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

Internal clock . . . . . . . . . . . . . . . . . . . . . . . . . 17

External clock . . . . . . . . . . . . . . . . . . . . . . . . . 17

Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

Display register . . . . . . . . . . . . . . . . . . . . . . . . 17

Segment outputs. . . . . . . . . . . . . . . . . . . . . . . 17

Backplane outputs . . . . . . . . . . . . . . . . . . . . . 18

7.10 Display RAM . . . . . . . . . . . . . . . . . . . . . . . . . . 18

7.10.1 Data pointer . . . . . . . . . . . . . . . . . . . . . . . . . . 20

7.10.2 Subaddress counter . . . . . . . . . . . . . . . . . . . . 20

7.10.3 RAM writing in 1:3 multiplex drive mode. . . . . 21

7.10.4 Bank selector . . . . . . . . . . . . . . . . . . . . . . . . . 22

7.10.4.1 Output bank selector . . . . . . . . . . . . . . . . . . . 22

7.10.4.2 Input bank selector . . . . . . . . . . . . . . . . . . . . . 22

7.11 Blinking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

7.12

7.13

Command decoder . . . . . . . . . . . . . . . . . . . . . 23

Display controller . . . . . . . . . . . . . . . . . . . . . . 25

8 Characteristics of the I

2 C-bus . . . . . . . . . . . . 26

8.1

8.2

Bit transfer . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

START and STOP conditions . . . . . . . . . . . . . 26

8.3 System configuration . . . . . . . . . . . . . . . . . . . 26

8.4 Acknowledge . . . . . . . . . . . . . . . . . . . . . . . . . 27

8.5 I 2

C-bus controller . . . . . . . . . . . . . . . . . . . . . . 28

8.6 Input filters . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

8.7 I 2

C-bus protocol . . . . . . . . . . . . . . . . . . . . . . . 28

9 Internal circuitry. . . . . . . . . . . . . . . . . . . . . . . . 30

10

11

Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . 31

Static characteristics . . . . . . . . . . . . . . . . . . . . 32

20

21

22

22.1

22.2

22.3

22.4

17

18

18.1

18.2

18.3

18.4

19

23

24

12

13

13.1

14

15

16

Dynamic characteristics. . . . . . . . . . . . . . . . . 34

Application information . . . . . . . . . . . . . . . . . 36

Cascaded operation. . . . . . . . . . . . . . . . . . . . 36

Package outline. . . . . . . . . . . . . . . . . . . . . . . . 40

Bare die outline . . . . . . . . . . . . . . . . . . . . . . . . 41

Handling information . . . . . . . . . . . . . . . . . . . 44

Packing information . . . . . . . . . . . . . . . . . . . . 45

Soldering of SMD packages . . . . . . . . . . . . . . 46

Introduction to soldering. . . . . . . . . . . . . . . . . 46

Wave and reflow soldering. . . . . . . . . . . . . . . 46

Wave soldering . . . . . . . . . . . . . . . . . . . . . . . 47

Reflow soldering . . . . . . . . . . . . . . . . . . . . . . 47

Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . 48

References. . . . . . . . . . . . . . . . . . . . . . . . . . . . 49

Revision history . . . . . . . . . . . . . . . . . . . . . . . 49

Legal information . . . . . . . . . . . . . . . . . . . . . . 50

Data sheet status . . . . . . . . . . . . . . . . . . . . . . 50

Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . 50

Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . 50

Trademarks . . . . . . . . . . . . . . . . . . . . . . . . . . 51

Contact information . . . . . . . . . . . . . . . . . . . . 51

Contents. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52

Please be aware that important notices concerning this document and the product(s) described herein, have been included in section ‘Legal information’.

© NXP B.V. 2011.

All rights reserved.

For more information, please visit: http://www.nxp.com

For sales office addresses, please send an email to: [email protected]

Date of release: 25 July 2011

Document identifier: PCF8534A

NXP PCF8534AU Universal LCD driver Product data

Universal LCD driver for low multiplex rates

2. Features and benefits

4. Marking

5.

Block diagram

8. Characteristics of the I

C-bus

10. Limiting values

11. Static characteristics

12. Dynamic characteristics

13. Application information

14. Package outline

15. Bare die outline

16. Handling information

17. Packing information

18. Soldering of SMD packages

19. Abbreviations

20. References

21. Revision history

22. Legal information

23. Contact information

24. Contents

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