i.MX25 Applications Processor for Consumer and Industrial Products

Freescale Semiconductor

Data Sheet: Technical Data

Document Number: IMX25CEC

Rev. 10, 07/2013

MCIMX25

i.MX25 Applications

Processor for

Consumer and

Industrial Products

Silicon Version 1.2

Package Information

Plastic package

Case 5284 17 x 17 mm, 0.8 mm Pitch

Case 2107 12 x 12 mm, 0.5 mm Pitch

Ordering Information

See

Table 1 on page 3 for ordering information.

1 Introduction

The i.MX25 multimedia applications processor has the right mix of high performance, low power, and integration to support the growing needs of the industrial and general embedded markets.

At the core of the i.MX25 is Freescale's fast, proven, power-efficient implementation of the

ARM® 926EJ-S™ core, with speeds of up to

400 MHz. The i.MX25 includes support for up to

133 MHz DDR2 memory, integrated 10/100

Ethernet MAC, and two on-chip USB PHYs. The device is suitable for a wide range of applications, including the following:

• Graphical remote controls

• Human Machine Interface (HMI)

• Residential and commercial control panels

• Residential gateway (smart metering)

• Handheld scanners and printers

• Electronic point-of-sale terminals

• Patient-monitoring devices

1. Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

1.1. Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . 3

1.2. Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

2. Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

2.1. Special Signal Considerations . . . . . . . . . . . . . . . . 9

3. Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . 11

3.1. i.MX25 Chip-Level Conditions . . . . . . . . . . . . . . . . 11

3.2. Supply Power-Up/Power-Down Requirements and

Restrictions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

3.3. Power Characteristics . . . . . . . . . . . . . . . . . . . . . . 18

3.4. Thermal Characteristics . . . . . . . . . . . . . . . . . . . . 20

3.5. I/O DC Parameters . . . . . . . . . . . . . . . . . . . . . . . . 20

3.6. AC Electrical Characteristics . . . . . . . . . . . . . . . . 24

3.7. Module Timing and Electrical Parameters . . . . . . 41

4. Package Information and Contact Assignment . . . . . . 124

4.1. 400 MAPBGA—Case 17x17 mm, 0.8 mm Pitch . 124

4.2. Ground, Power, Sense, and Reference Contact

Assignments Case 17x17 mm, 0.8 mm Pitch . . . 125

4.3. Signal Contact Assignments—17 x 17 mm, 0.8 mm

Pitch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127

4.4. i.MX25 17x17 Package Ball Map . . . . . . . . . . . . 135

4.5. 347 MAPBGA—Case 12 x 12 mm, 0.5 mm Pitch 138

4.6. Ground, Power, Sense, and Reference Contact

Assignments Case 12x12 mm, 0.5 mm Pitch . . . 139

4.7. Signal Contact Assignments—12 x 12 mm, 0.5 mm

Pitch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 140

4.8. i.MX25 12x12 Package Ball Map . . . . . . . . . . . . 148

5. Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 151

© 2009-2013 Freescale Semiconductor, Inc. All rights reserved.

Features of the i.MX25 processor include the following:

• Advanced power management—The heart of the device is a level of power management throughout the IC that enables the multimedia features and peripherals to achieve minimum system power consumption in active and various low-power modes. Power management techniques allow the designer to deliver a feature-rich product that requires levels of power far lower than typical industry expectations.

• Multimedia powerhouse—The multimedia performance of the i.MX25 processor is boosted by a

16 KB L1 instruction and data cache system and further enhanced by an LCD controller (with alpha blending), a CMOS image sensor interface, an A/D controller (integrated touchscreen controller), and a programmable Smart DMA (SDMA) controller.

• 128 Kbytes on-chip SRAM—The additional 128 Kbyte on-chip SRAM makes the device ideal for eliminating external RAM in applications with small footprint RTOS. The on-chip SRAM allows the designer to enable an ultra low power LCD refresh.

• Interface flexibility—The device interface supports connection to all common types of external memories: MobileDDR, DDR, DDR2, NOR Flash, PSRAM, SDRAM and SRAM, NAND Flash, and managed NAND.

• Increased security—Because the need for advanced security for tethered and untethered devices continues to increase, the i.MX25 processor delivers hardware-enabled security features that enable secure e-commerce, Digital Rights Management (DRM), information encryption, robust tamper detection, secure boot, and secure software downloads.

• On-chip PHY—The device includes an HS USB OTG PHY and FS USB HOST PHY.

• Fast Ethernet—For rapid external communication, a Fast Ethernet Controller (FEC) is included.

• i.MX25 only supports Little Endian mode.

2

i.MX25 Applications Processor for Consumer and Industrial Products, Rev. 10

Freescale Semiconductor

1.1

Ordering Information

Table 1

provides ordering information for the i.MX25.

Table 1. Ordering Information

Description

i.MX253

Part Number

MCIMX253DVM4

Silicon

Version

1.1

Projected

Temperature

Range (

°C)

–20 to +70 i.MX257

i.MX253

i.MX257

i.MX258

i.MX253

i.MX257

i.MX253

i.MX257

i.MX258

i.MX253

i.MX257

i.MX257

i.MX253

i.MX257

i.MX258

i.MX257

MCIMX257DVM4

MCIMX253CVM4

MCIMX257CVM4

MCIMX258CVM4

MCIMX253DJM4

MCIMX257DJM4

MCIMX253CJM4

MCIMX257CJM4

MCIMX258CJM4

MCIMX253DJM4A

MCIMX257DJM4A

MCIMX257DJM4AR2

MCIMX253CJM4A

MCIMX257CJM4A

MCIMX258CJM4A

MCIMX257CJN4A

1.1

1.1

1.1

1.1

1.1

1.1

1.1

1.1

1.1

1.2

1.2

1.2

1.2

1.2

1.2

1.2

–20 to +70

–40 to +85

–40 to +85

–40 to +85

–20 to +70

–20 to +70

–40 to +85

–40 to +85

–40 to +85

–20 to +70

–20 to +70

–20 to +70

–40 to +85

–40 to +85

–40 to +85

–40 to +85

Package

17 x 17 mm, 0.8 mm pitch,

MAPBGA-400


MAPBGA-400


MAPBGA-400


MAPBGA-400


MAPBGA-400


MAPBGA-400


MAPBGA-400


MAPBGA-400


MAPBGA-400


MAPBGA-400


MAPBGA-400


MAPBGA-400


MAPBGA-400


MAPBGA-400


MAPBGA-400


MAPBGA-400

12 x 12mm, 0.5mm pitch,

MAPBGA-347

Ballmap

Table 103

Table 103

Table 103

Table 103

Table 103

Table 103

Table 103

Table 107

Table 103

Table 103

Table 103

Table 103

Table 103

Table 103

Table 103

Table 103

Table 103


Freescale Semiconductor 3

Table 2 shows the functional differences between the different parts in the i.MX25 family.

Table 2. i.MX25 Parts Functional Differences

Features MCIMX253

Core

CPU Speed

L1 I/D Cache

On-chip SRAM

PATA/CE-ATA

LCD Controller

Touchscreen

CSI

FlexCAN (2)

ESAI

—

—

SIM (2) —

Security —

10/100 Ethernet

HS USB 2.0 OTG + PHY

HS USB 2.0 Host + PHY

12-bit ADC

Yes

Yes

Yes

Yes

SD/SDIO/MMC (2)

External Memory Controller

I

2

C (3)

SSI/I2S (2)

CSPI (2)

UART (5)

ARM 926EJ-S

400 MHz

16K I/D

128 KB

Yes

Yes

—

—

Yes

Yes

Yes

Yes

Yes

Yes

MCIMX257

Yes

Yes

Yes

Yes

Yes

Yes

Yes

—

ARM 926EJ-S

400 MHz

16K I/D

128 KB

Yes

Yes

Yes

Yes

Yes

Yes

Yes

Yes

Yes

Yes

MCIMX258

Yes

Yes

Yes

Yes

Yes

Yes

Yes

Yes

ARM 926EJ-S

400 MHz

16K I/D

128 KB

Yes

Yes

Yes

Yes

Yes

Yes

Yes

Yes

Yes

Yes

4



1.2

Block Diagram

Figure 1

shows the simplified interface block diagram.

DDR2 /

MDDR

NOR

Flash/

PSRAM

NAND

Flash

Ext. Graphics

Accelerator

Camera

Sensor

External Memory

Interface (EMI)

LCD Display 1

ARM Processor Domain (AP)

LCDC /

SLCDC

Smart

DMA

SPBA

Shared

Domain

SDMA Peripherals

UART(3)

CSPI(2)

ADC/TSC

SSI(1)

ESAI

SIM(2)

ATA

FEC

Fusebox

ARM9

Platform

ARM926EJ-S

L1 I/D cache

AVIC

MAX

AIPS(2)

ETM

Internal

Memory

ARM Peripherals

SSI

AUDMUX

HS USB OTG

HS USB OTG PHY

HS USB Host

FS USB Host PHY I

2

C(3)

UART(2)

CSPI eSDHC(2)

FlexCAN(2)

IOMUX

GPIO(3)

IIM

RTICv3

RNGB

SCC

DRYICE

KPP

PWM(4)

1-WIRE

EPIT(2)

Timers

RTC

WDOG

GPT(4)

Audio/Power

Management

JTAG

Bluetooth

MMC/SDIO or WLAN

Keypad

Access.

Conn.

Figure 1. i.MX25 Simplified Interface Block Diagram i.MX25 Applications Processor for Consumer and Industrial Products, Rev. 10


6

2 Features

Table 3

describes the digital and analog modules of the device.

Table 3. i.MX25 Digital and Analog Modules

Block

Mnemonic

1-WIRE

Block Name Subsystem Brief Description

ARM9 or

ARM926

ATA

AUDMUX

CCM

CSPI(3)

DRYICE

EMI

1-Wire

Interface

ARM926 platform and memory

Connectivity peripherals

ARM

ATA module Connectivity peripherals

Digital audio mux

Multimedia peripherals

Clock control module

Clocks

Configurable serial peripheral interface


DryIce module Security

External memory interface


1-Wire support provided for interfacing with an on-board EEPROM, and smart battery interfaces, for example: Dallas DS2502.

The ARM926 Platform consists of the ARM 926EJ-S core, the ETM real-time debug modules, a 5x5 Multi-Layer AHB crossbar switch, and a “primary

AHB” complex. It contains the 16 Kbyte L1 instruction cache, 16 Kbyte L1 data cache, 32 Kbyte ROM and 128 Kbyte RAM.

The ATA module is an AT attachment host interface. Its main use is to interface with IDE hard disc drives and ATAPI optical disc drives. It interfaces with the ATA device over a number of ATA signals.

The AUDMUX is a programmable interconnect for voice, audio, and synchronous data routing between host serial interfaces (SSIs) and peripheral serial interfaces (audio codecs). The AUDMUX has two sets of interfaces: internal ports to on-chip peripherals, and external ports to off-chip audio devices. Data is routed by configuring the appropriate internal and external ports.

This block generates all clocks for the iMX25 system. The CCM also manages the ARM926 Platform's low-power modes (wait, stop, and doze) by disabling peripheral clocks appropriately for power conservation.

This module is a serial interface equipped with data FIFOs. Each master/slave-configurable SPI module is capable of interfacing to both serial port interface master and slave devices. The CSPI ready (SPI_RDY) and

Slave Select (SS) control signals enable fast data communication with fewer software interrupts.

DryIce provides volatile key storage for Point-of-Sale (POS) terminals, and a trusted time source for Digital Rights Management (DRM) schemes. Several tamper-detect circuits are also provided to support key erasure and time invalidation in the event of tampering. Alarms and/or interrupts can also assert if tampering is detected. DryIce also includes a Real Time clock (RTC) that can be used in secure and non-secure applications.

The External Memory Interface (EMI) module provides access to external memory for the ARM and other masters. It is composed of four main submodules:

• M3IF provides arbitration between multiple masters requesting access to the external memory.

• Enhanced SDRAM/LPDDR memory controller (ESDCTL) interfaces to

DDR2 and SDR interfaces.

• NAND Flash controller (NFC) provides an interface to NAND Flash memories.

• Wireless External Interface Memory controller (WEIM) interfaces to NOR

Flash and PSRAM.



Table 3. i.MX25 Digital and Analog Modules (continued)

Block

Mnemonic


EPIT(2)

ESAI eSDHC(2)

FEC

Enhanced periodic interrupt timer

Enhanced serial audio interface

Enhanced multimedia card/ secure digital host controller

Fast ethernet controller

Timer peripherals




Each Enhanced Periodic Interrupt Timer (EPIT) is a 32-bit set-and-forget timer that starts counting after the EPIT is enabled by software. It is capable of providing precise interrupts at regular intervals with minimal processor intervention. It has a 12-bit prescaler to adjust the input clock frequency to the required time setting for the interrupts, and the counter value can be programmed on the fly.

ESAI provides a full-duplex serial port for serial communication with a variety of serial devices, including industry-standard codecs, SPDIF transceivers, and other DSPs. The ESAI consists of independent transmitter and receiver sections, each section with its own clock generator.

The features of the eSDHC module, when serving as host, include the following:

• Conforms to the SD host controller standard specification version 2.0

• Compatible with the JEDEC MMC system specification version 4.2

• Compatible with the SD memory card specification version 2.0

• Compatible with the SDIO specification version 1.2

• Designed to work with SD memory, miniSD memory, SDIO, miniSDIO, SD combo, MMC and MMC RS cards

• Configurable to work in one of the following modes:

—SD/SDIO 1-bit, 4-bit

—MMC 1-bit, 4-bit, 8-bit

• Full-/high-speed mode

• Host clock frequency variable between 32 kHz and 52 MHz

• Up to 200-Mbps data transfer for SD/SDIO cards using four parallel data lines

• Up to 416-Mbps data transfer for MMC cards using eight parallel data lines

The Ethernet Media Access Controller (MAC) is designed to support both 10- and 100-Mbps Ethernet networks compliant with IEEE 802.3® standard. An external transceiver interface and transceiver function are required to complete the interface to the media

FlexCAN(2) Controller area network module


GPIO(4)

GPT(4)

General purpose I/O modules

General purpose timers

System control peripherals

Used for general purpose input/output to external ICs. Each GPIO module supports 32 bits of I/O.

Timer peripherals

The Controller Area Network (CAN) protocol is primarily designed to be used as a vehicle serial data bus running at 1 MBps.

Each GPT is a 32-bit free-running or set-and-forget mode timer with programmable prescaler and compare and capture register. A timer counter value can be captured using an external event and can be configured to trigger a capture event on either the leading or trailing edges of an input pulse. When the timer is configured to operate in set-and-forget mode, it is capable of providing precise interrupts at regular intervals with minimal processor intervention. The counter has output compare logic to provide the status and interrupt at comparison. This timer can be configured to run either on an external clock or on an internal clock.



8


Block

Mnemonic

I

2

C(3)

IIM

IOMUX

KPP

LCDC

MAX

PWM(4)

SDMA

SIM(2)

SJC


I

2

C module

IC

Identification

Module


Security

I/O multiplexer Pins

Inter-IC Communication (I

2

C) is an industry-standard, bidirectional serial bus that provides a simple, efficient method of data exchange, minimizing the interconnection between devices. I

2

C is suitable for applications requiring occasional communications over a short distance between many devices.

The interface operates up to 100 kbps with maximum bus loading and timing.

The I

2

C system is a true multiple-master bus, including arbitration and collision detection that prevents data corruption if multiple devices attempt to control the bus simultaneously. This feature supports complex applications with multiprocessor control and can be used for rapid testing and alignment of end products through external connections to an assembly-line computer.

The IIM provides the primary user-visible mechanism for interfacing with on-chip fuse elements. Among the uses for the fuses are unique chip identifiers, mask revision numbers, cryptographic keys, and various control signals requiring a fixed value.

Each I/O multiplexer provides a flexible, scalable multiplexing solution:

• Up to eight output sources multiplexed per pin

• Up to four destinations for each input pin

• Unselected input paths are held at constant level for reduced power consumption

Keypad port Connectivity peripherals

LCD

Controller


KPP can be used for either keypad matrix scanning or general purpose I/O.

ARM platform multilayer

AHB crossbar switch

ARM platform MAX concurrently supports up to five simultaneous connections between master ports and slave ports. MAX allows for concurrent transactions to occur from any master port to any slave port.

Pulse width modulation


LCDC provides display data for external gray-scale or color LCD panels.

LCDC is capable of supporting black-and-white, gray-scale, passive-matrix color (passive color or CSTN), and active-matrix color (active color or TFT)

LCD panels.

The Pulse-Width Modulator (PWM) has a 16-bit counter and is optimized to generate sound from stored sample audio images. It can also generate tones. The PWM uses 16-bit resolution and a 4x16 data FIFO to generate sound.

Smart DMA engine

Subscriber identity module interface

System control The SDMA provides DMA capabilities inside the processor. It is a shared module that implements 32 DMA channels.


The SIM is an asynchronous interface designed to facilitate communication with SIM cards or pre-paid phone cards. This module was designed based on the ISO7816 standard; however, the module does require an external companion controller to allow communication to certain smart cards or to pass certain certifications, such as EMV.

The SIM supports only 11 and 12ETU cards and can communicate at the default rate, which is obtained at Fi/Di=372/1. An external companion controller is required to support cards aligned on 10.8 or 11.8ETU and to support other rates, such as those obtained at Fi/Di=372/2 and Fi/Di=372/4.

Secure JTAG interface

System control peripherals

The System JTAG Controller (SJC) provides debug and test control with maximum security.




Block

Mnemonic


SLCD

SPBA

SSI(2)

Smart LCD controller


The SLCDC module transfers data from the display memory buffer to the external display device.

Shared peripheral bus arbiter

System control The SPBA controls access to the shared peripherals. It supports shared peripheral ownership and access rights to an owned peripheral.

I2S/SSI/AC97 interface


TSC (and ADC) Touchscreen controller (and

A/D converter)


The SSI is a full-duplex serial port that allows the processor to communicate with a variety of serial protocols, including the Freescale Semiconductor SPI standard and the inter-IC sound bus standard (I2S). The SSIs interface to the AUDMUX for flexible audio routing.

The touchscreen controller and associated Analog-to-Digital Converter

(ADC) together provide a resistive touchscreen solution. The module implements simultaneous touchscreen control and auxiliary ADC operation for temperature, voltage, and other measurement functions.

UART(5)

USBOTG

USBHOST

UART interface

High-speed

USB on-the-go



Each of the UART modules supports the following serial data transmit/receive protocols and configurations:

• 7- or 8-bit data words, one or two stop bits, programmable parity (even, odd, or none)

• Programmable baud rates up to 4 MHz. This is a higher maximum baud rate than the 1.875 MHz specified by the TIA/EIA-232-F standard and previous Freescale UART modules. 32-byte FIFO on Tx and 32 half-word

FIFO on Rx supporting auto-baud

• IrDA-1.0 support (up to SIR speed of 115200 bps)

• Option to operate as 8-pins full UART, DCE, or DTE

The USB module provides high-performance USB On-The-Go (OTG) and host functionality (up to 480 Mbps), compliant with the USB 2.0 specification, the OTG supplement, and the ULPI 1.0 Low Pin Count specification. The module has DMA capabilities for handling data transfer between internal buffers and system memory. An OTG HS PHY and HOST FS PHY are also integrated.

2.1

Special Signal Considerations

Special signal considerations are listed in Table 4 . The package contact assignment is found in

Section 4,

“Package Information and Contact Assignment .”

Signal descriptions are provided in the reference manual.

.

Table 4. Signal Considerations

Signal Description

BAT_VDD

CLK0

DryIce backup power supply input.

Clock-out pin; renders the internal clock visible to users for debugging. The clock source is controllable through CRM registers. This pin can also be configured (through muxing) to work as a normal GPIO.

CLK_SEL Used to select the ARM clock source from MPLL out or from external EXT_ARMCLK. In normal operation,

CLK_SEL should be connected to GND.

EXT_ARMCLK Primarily for Freescale factory use. There is no internal on-chip pull-up/down on this pin, so it must be externally connected to GND or VDD. Aside from factory use, this pin can also be configured (through muxing) to work as a normal GPIO.



Table 4. Signal Considerations (continued)


MESH_C, MESH_D Wire-mesh tamper detect pins that can be routed at the PCB board to detect attempted tampering of a protected wire. When security measures are implemented, MESH_C should be pulled-up or connected to

NVCC_DRYICE and triggers a tamper event when floating or when connected to MESH_D. MESH_D should be pulled-down or connected to GND and triggers an event when floating or connected to

MESH_C. These pins can be left unconnected if the DryIce security features are not being used.

NVCC_DRYICE This is the DryIce power supply output. The supply source is QVDD when the i.MX25 is in run mode. When i.MX25 is in reduced power mode, the DryIce supply source is the BATT_VDD supply. This pin can be used to power external DryIce components (external tamper detect, wire-mesh tamper detect). In order to guarantee the power-loss protection feature which guarantees that RTC and/or secure keys be maintained after power-off an external capacitor no less than 4 µF must be connected to this supply output pin. A 4.7 µF capacitor is recommended.

OSC_BYP

OSC32K_EXTAL

OSC32K_XTAL

The 32 kHz oscillator bypass-control pin. If this signal is pulled down, then OSC32K_EXTAL and

OSC32K_XTAL analog pins should be tied to the external 32.768 kHz crystal circuit. If on the other hand the signal is pulled up, then the external 32 kHz oscillator output clock must be connected to

OSC32K_EXTAL analog pin, and OSC32K_XTAL can be no connect (NC).

These analog pins are connected to an external 32 kHz CLK circuit depending on the state of OSC_BYP pin (see the description of OSC_BYP under the preceding bullet). The 32 kHz reference CLK is required for normal operation.

POWER_FAIL

REF

An interrupt from PMIC, which should be connected to a low-battery detection circuit. This signal is internally connected to an on-chip 100 k

Ω pull-down device. If there is no low-battery detection, then users can tie this pin to GND through a pull-down resistor, or leave the signal as NC. This pin can also be configured to work as a normal GPIO.

External ADC reference voltage. REF may be tied to GND if the user plans to only use the internally generated 2.5 V reference supply.

SJC_MOD

TAMPER_A,

TAMPER _B

TEST_MODE

Must be externally connected to GND for normal operation. Termination to GND through an external pull-down resistor (such as 1 k

Ω) is allowed, but the value should be much smaller than the on-chip 100 k

Ω pull-up.

DryIce external tamper detect pins, active high. If TAMPER_A or TAMPER_B is connected to

NVCC_DRYICE, then external tampering is detected. These pins can be left unconnected if the DryIce security features are not being used.

For Freescale factory use only. This signal is internally connected to an on-chip pull-down device. Users must either float this signal or tie it to GND.

UPLL_BYPCLK Primarily for Freescale factory use. There is no internal on-chip pull-up/down on this pin, so it must be externally connected to GND or VDD. Aside from factory use, this pin can also be configured (through muxing) to work as a normal GPIO.

USBPHY1_RREF Determines the reference current for the USB PHY1 bandgap reference. An external 10 k

Ω 1% resistor to

GND is required.

USBPHY2_DM

USBPHY2_DP

The output impedance of these signals is expected at 10

Ω. It is recommended to also have on-board 33 Ω series resistors (close to the pins).

10



3 Electrical Characteristics

This section provides the device-level and module-level electrical characteristics for the i.MX25.

3.1

i.MX25 Chip-Level Conditions

This section provides the chip-level electrical characteristics for the IC.

3.1.1

DC Absolute Maximum Ratings

Table 5

provides the DC absolute maximum operating conditions.

CAUTION

• Stresses beyond those listed under

Table 5

may cause permanent damage to the device.

• Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

•

Table 5

gives stress ratings only—functional operation of the device is

not implied beyond the conditions indicated in Table 6

.

Table 5. DC Absolute Maximum Ratings

Supply voltage

Parameter Symbol

Supply voltage (level shift i/o)

ESD damage immunity:

Human body model (HBM)

Charge device model (CDM)

Machine model (MM)

Input voltage range

Storage temperature range

QV

DD

V

DDIOmax

V esd

T

V

Imax storage

Min.

–0.5

–0.5

—

—

—

–0.5

–40

Max.

1.52

3.6

2500

400

200

NV

DD

+ 0.3

105

3.1.2

DC Operating Conditions

Table 6

provides the DC recommended operating conditions.

Table 6. DC Operating Conditions

Parameter

Core supply voltage (at 266 MHz)

Core supply voltage (at 400 MHz)

Coin battery

1

BAT_VDD

I/O supply voltage, GPIO

NFC,CSI,SDIO

Symbol

QV

DD

QV

DD

V

DD_BAT

NV

DD_GPIO1

Units

V

V

V

V o

C

Min.

1.15

1.38

1.15

Typ.

1.34

1.45

—

Max.

Units

1.52

1.52

1.55

V

V

V

1.75

— 3.6

V



Table 6. DC Operating Conditions (continued)

Parameter Symbol Min.

Typ.

Max.

Units

I/O supply voltage, GPIO

CRM,LCDC,JTAG,MISC

I/O supply voltage DDR (Mobile DDR mode)

EMI1, EMI2

I/O supply voltage DDR (DDR2 mode)

EMI1,EMI2

I/O supply voltage DDR (SDRAM mode)

EMI1,EMI2

Supply of USBPHY1 (HS)

USBPHY1_VDDA_BIAS, USBPHY1_UPLL_VDD,USBPHY1_VDDA

Supply of USBPHY2 (FS)

USBPHY2_VDD

Supply of OSC24M

OSC24M_VDD

Supply of PLL

MPLL_VDD,UPLL_VDD

NV

NV

NV

NV

V

V

V

DD_SDRAM

DD_usbphy1

DD_usbphy2

DD_OSC24M

V

DD_GPIO2

DD_MDDR

DD_DDR2

DD_PLL

3.0

1.75

1.75

1.75

3.17

3.0

1.4

3.3

—

—

—

3.3

3.3

3.0 3.3

—

3.6

1.95

1.9

3.6

3.43

3.6

3.6

1.65

—

V

V

V

V

V

V

V

Supply of touchscreen ADC

NVCC_ADC

External reference of touchscreen ADC

Ref

V

DD_tsc

Vref

3.0

2.5

V

3.3

DD_tsc

V

3.6

DD_tsc

V

V

Fusebox program supply voltage

FUSE_VDD

2

Supply output

3

NVCC_DRYICE

FUSEV

V

DD_

DD

(program mode)

3.3 ± 5%

1.0

—

—

3.6

1.55

V

V

Operating ambient temperature T

A

–40 — 85 o

C

1

2

3

V

DD_BAT

must always be powered by battery in security application. In non-security case, V

DD_BAT can be connected to

QV

DD

.

The fusebox read supply is connected to supply of the full speed USBPHY2_VDD. FUSE_VDD is only used for programming.

It is recommended that FUSE_VDD be connected to ground when not being used for programming. See Table 7 for current

parameters.

NVCC_DRYICE is a supply output. An external capacitor no less than 4 µF must be connected to it. A 4.7 µF capacitor is recommended.

12



3.1.3

Fusebox Supply Current Parameters

Table 7

lists the fusebox supply current parameters.

Table 7. Fusebox Supply Current Parameters

Parameter Symbol Min.

eFuse program current

1

Current to program one eFuse bit

The associated VDD_FUSE supply = 3.6 V eFuse read current

2

Current to read an 8-bit eFuse word

I program

I read

1

2

The current I program

is during program time (t program

).

The current I read

is present for approximately 50 ns of the read access to the 8-bit word.

26

—

Typ.

35

Max.

62

12.5

15

Units

mA mA

3.1.4

Interface Frequency Limits

Table 8 provides information for interface frequency limits.

Table 8. Interface Frequency Limits

Parameter

JTAG: TCK Frequency of Operation

OSC24M_XTAL Oscillator

OSC32K_XTAL Oscillator

Min.

DC

—

—

Typ.

5

24

32.768

Max.

10

—

—

Units

MHz

MHz kHz

Table 9 provides the recommended external crystal specifications.

Table 9. Recommended External Crystal Specifications

Frequency Tolerance

ESR

Load Capacitor

Shunt Capacitor

Drive Level

24 MHz

<=

±

30 ppm

< 80

Ω

8 pF–12 pF

< 7 pF

> 150 µW

32.768 kHz

<=

±

30 ppm

50 K~60 K

6 pF–8 pF (12 pF–16 pF on each pin)

1 pF

> 1 µW

Table 10 provides the recommended external reference clock oscillator specifications (when reference is used from an external clock source).

Table 10. Recommended External Reference Clock Specifications

V

OH

V

OL

Frequency Tolerance

24 MHz

min = 0.7* VDD max = 0.3* VDD

= 30 ppm

32.768 kHz

min = 0.7* VDD max = 0.3* VDD

= 30 ppm



T

RISE

T

FALL

Duty Cycle

Table 10. Recommended External Reference Clock Specifications (continued)

1% T

CLOCK

1% T

CLOCK

50%

1% T

CLOCK

1% T

CLOCK

50%

3.1.5

USB_PHY Current Consumption

Table 11 provides information for USB_PHY current consumption.

Table 11. USB PHY Current Consumption

1

Analog supply

USBPHY1_VDDA_BIAS, USBPHY1_UPLL_VDD,

USBPHY1_VDDA (3.3 V)

Analog supply

USBPHY2_VDD (3.3 V)

All supplies

1

Values must be verified

Parameter Conditions

Full speed

High speed

Suspend

Full Speed

Low Speed

Suspend

—

Rx

Tx

Rx

Tx

Rx

Tx

Rx

Tx

Typ.

(@Typ. Temp)

Max.

(@Max. Temp)

Unit

11.4

22,6

21.5

33.8

0.6

120

25

252

5.5

50

—

—

—

—

—

—

—

—

100 mA

μA

μA mA

μA mA

μA

3.1.6

Power Modes

Table 12

describes the core, clock, and module settings for the different power modes of the processor.

Table 12. i.MX25 Power Mode Settings

Core/Clock/Module

ARM core

Doze

Platform clock is off

Wait

Power Mode

In wait-for-interrupt mode

Stop/Sleep

1

—

Well bias

MCU PLL

USB PLL

OSC24M

OSC32K

Other modules

On

On

Off

On

On

Off

On

On

Off

Off

On

Off

Off

On

Off

On

Off

Off

Run (266 MHz) Run (400 MHz)

Active @

266 MHz

Off

On

On

On

On

On

Active @

400 MHz

Off

On

On

On

On

On

14



1

Sleep mode differs from stop mode in that the core voltage is reduced to 1 V.

Table 13

shows typical current consumption for the various power supplies under the various power modes.

Table 13. i.MX25 Power Mode Current Consumption

Current Consumption for Power Modes

1

Power Group Power Supplies

Voltage

Setting

Doze

5

μA

Wait

3.15

μA

Stop

3.51

μA

Sleep

3.61

μA

NVCC_EMI

NVCC_CRM

NVCC_

OTHER

NVCC_ADC

OSC24M

PLL_VDD

QVDD

USBPHY1_

VDDA

USBPHY1_

VDDA_VBIAS

NVCC_EMI1

NVCC_EMI2

NVCC_CRM

NVCC_SDIO

NVCC_CSI

NVCC_NFC

NVCC_JTAG

NVCC_LCDC

NVCC_MISC

NVCC_ADC

OSC24M_

VDD

MPLL_VDD

UPLL_VDD

QVDD

3.0 V

3.0 V

3.0 V

3.0 V

3.0 V

1.4 V

USBPHY1_

VDDA

USBPHY1_

VDDA_VBIAS

1.15 V

3.17 V

3.17 V

USBPHY1_

UPLL_VDD

USBPHY1_

UPLL_VDD

3.17 V

USBPHY2 USBPHY2_

VDD

3.0 V

1

Values are typical, under typical use conditions.

1.15

μA

31.2

μA

163

μA

906

μA

6.83 mA

8.79 mA

240

μA

0.6

μΑ

201

μΑ

158

μA

4.31

μΑ

29.5

μΑ

3.25

μΑ

903

μΑ

6.83 m

Α

11.28 mA

240

μΑ

1.46

μΑ

201

μΑ

0158

μΑ

0.267

μΑ

31.7

μA

1.14

μΑ

10.2

μΑ mA

38.9

μΑ

842

μA

241

μΑ

0.328

μΑ

191

μΑ

164

μΑ

0.32

μΑ

32.1

μΑ

0.871

μΑ

10.5

μΑ

39.1

μΑ

665

μA

242

μΑ

0.231

μΑ

191

μΑ

164

μΑ

In the reduced power mode, shown in

Table 14

, the i.MX25 is powered down, while the RTC clock and the secure keys (in secure-use case), remain operational. BAT_VDD is tied to a battery while all other supplies are turned off.

NOTE

In this low-power mode, i.MX25 cannot be woken up with an interrupt; it must be powered back up before it can detect any events.



Power Group

BAT_VDD

Table 14. iMX25 Reduced Power Mode Current Consumption

Power Supply

BAT_VDD

Voltage Setting

1.15 V

1.55 V

Typical Current Consumption

9.95

μA

12.6

μA

3.2

Supply Power-Up/Power-Down Requirements and Restrictions

Any i.MX25 board design must comply with the power-up and power-down sequence guidelines given in this section to ensure reliable operation of the device. Recommended power-up and power-down sequences are given in the following subsections.

CAUTION

Deviations from the guidelines in this section may result in the following situations:

• Excessive current during power-up phase

• Prevention of the device from booting

• Irreversible damage to the i.MX25 (worst-case scenario)

NOTE

For security applications, the coin battery must be connected during both power-up and power-down sequences to ensure that security keys are not unintentionally erased.

3.2.1

Power-Up Sequence

For those users that are not using DryIce/SRTC, the following power-up sequence is recommended:

1. Assert power on reset (POR).

2. Turn on QVDD digital logic domain supplies.

3. Turn on NVCCx digital I/O power supplies after QVDD is stable.

4. Turn on all other analog power supplies, including USBPHY1_VDDA_BIAS,

USBPHY1_UPLL_VDD, USBPHY1_VDDA, USBPHY2_VDD, OSC24M_VDD,

MPPLL_VDD, UPLL_VDD, NVCC_ADC, and FUSEVDD (FUSEVDD is tied to GND if fuses are not programmed), after all NVCCx digital I/O supplies are stable.

5. Negate the POR signal.

16



NOTE

• The user is advised to connect FUSEVDD to GND except when fuses are programmed, to prevent unintentional blowing of fuses.

• Other power-up sequences may be possible; however, the above sequence has been verified and is recommended.

• There is a 1 ms minimum time between supplies coming up, and a 1 ms minimum time between POR_B assert and de-assert.

• The dV/dT should be no faster than 0.25 V/

μs for all power supplies, to

avoid triggering ESD circuit.

Figure 2

shows the power-up sequence diagram. After POR_B is asserted, Core VDD and NVDDx can be powered up. After Core VDD and NVDDx are stable, the analog supplies can be powered up.

Figure 2. Power-Up Sequence Diagram

3.2.2

Power-Down Sequence

There are no special requirements for the power-down sequence. All power supplies can be shut down at the same time.

3.2.3

SRTC DryIce Power-Up/Down Sequence

In order to guarantee DryIce power-loss protection, including retention of SRTC time data during power down, users must do the following:

• Place a proper capacitor on the NVCC_DRYICE output pin, and

• Implement the below power-up/down sequence

1. Assert power on reset (POR).

2. Turn on NVCC_CRM.

3. Turn on QVDD digital logic domain supplies for not less than 1 ms and not more than 32 ms, after

NVCC_CRM reaches 90% of 3.3 V.



NOTE

This is to guarantee that POR is stable already at NVCC_CRM/QVDD power domain interface before QVDD is turned on, and POR instantly propagates to QVDD domain after QVDD is turned on.

4. Turn on other NVCCx digital I/O power supplies for not less than 1 ms and not more than 32 ms, after QVDD reaches 90% of 1.2 V.

5. Turn on all other analog power supplies, including USBPHY1_VDDA_BIAS,

USBPHY1_UPLL_VDD, USBPHY1_VDDA, USBPHY2_VDD, NVCC_ADC,

OSC24M_VDD, MPPLL_VDD, UPLL_VDD, and FUSEVDD (FUSEVDD is tied to GND if fuses are not programmed) for not less than 1 ms and not more than 32 ms, after NVCCx reaches

90% of 3.3 V.

NOTE

This is to guarantee that analog peripherals can get properly initialized

(reset) values from QVDD domain and NVCCx domain.

6. Negate the POR signal for at least 90

μs after all previous steps.

NOTE

• This is to guarantee that both POR logic and clocks are stable inside the i.MX25 chip, before POR is removed.

• The dV/dT should be no faster than 0.25 V/us for all power supplies, to avoid triggering ESD circuit.

In addition, the following power-down sequence is recommended:

1. Turn off power for analog parts, including USBPHY1_VDDA_BIAS, USBPHY1_UPLL_VDD,

USBPHY1_VDDA, USBPHY2_VDD, NVCC_ADC, and FUSEVDD (FUSEVDD is tied to GND if fuses are not programmed).

2. Turn off QVDD.

3. Turn off NVCCx, PLL, OSC, and other powers.

NOTE

The power-down steps can be executed simultaneously, or very shortly one after another.

3.3

Power Characteristics

Table 15

shows values representing maximum current numbers for the i.MX25 under worst case voltage and temperature conditions. These values are derived from the i.MX25 with core clock speed up to

400 MHz. Additionally, no power saving techniques such as clock gating were implemented when measuring these values. Common supplies are bundled according to the i.MX25 power-up sequence requirements. Peak numbers are provided for system designers so that the i.MX25 power supply requirements are satisfied during startup and transient conditions. Freescale recommends that system

18



current measurements are taken with customer-specific use-cases to reflect the normal operating conditions in the end system.

Table 15. Power Consumption

Power Supply Voltage (V) Max Current (mA)

QVDD

NVCC_EMI1, NVCC_EMI2

1.52

1.9

360

30

NVCC_CRM, NVCC_SDIO, NVCC_CSI,

NVCC_NFC, NVCC_JTAG, NVCC_LCDC,

NVCC_MISC

MPLL_VDD, UPLL_VDD

3.6

110

USBPHY1_VDDA_BIAS, USBPHY1_UPLL_VDD,

USBPHY1_VDDA, USBPHY2_VDD,

OSC24M_VDD, NVCC_ADC

FUSE_VDD

1

1.65

3.3

3.6

20

40

62

BATT_VDD 1.55

0.030

1

The FUSE_VDD rail is connected to ground. it only needs a voltage if the system fuse burning is needed.

The method for obtaining the maximum current is as follows:

1. Measure the worst case power consumption on individual rails using directed test on i.MX25.

2. Correlate the worst case power consumption power measurements with the worst case power consumption simulations.

3. Combine common voltage rails based on the power supply sequencing requirements (add the worst case power consumption on each rail within some test cases from several test cases run, to maximize different rails in the power group).

4. Guard the worst case numbers for temperature and process variation.

5. The sum of individual rails is greater than the real world power consumption, since a real system does not typically maximize the power consumption on all peripherals simultaneously.

6. BATT_VDD current is measured when the system is in reduced power mode maintaining the

RTC. When the system is in run mode, QVDD is used to supply the DryIce, so this current becomes negligible. See

Table 12

, for more details on the power modes.

NOTE

The values mentioned above should not be taken as a typical max run data for specific use cases. These values are Absolute MAX data. Freescale recommends that the system current measurements are taken with customer-specific use-cases to reflect normal operating conditions in the end system.



3.4

Thermal Characteristics

The thermal resistance characteristics for the device are given in

Table 16 . These values are measured

under the following conditions:

• Two-layer substrate

• Substrate solder mask thickness: 0.025 mm

• Substrate metal thicknesses: 0.016 mm

• Substrate core thickness: 0.200 mm

• Core through I.D: 0.118 mm, Core through plating 0.016 mm.

• Flag: Trace style with ground balls under the die connected to the flag

• Die Attach: 0.033 mm non-conductive die attach, k = 0.3 W/m K

• Mold compound: Generic mold compound; k = 0.9 W/m K

Table 16. Thermal Resistance Data

Rating Condition Symbol Value Unit

Junction to ambient

1

natural convection Single layer board (1s) R eJA

55 °C/W

Junction to ambient

1

natural convection Four layer board (2s2p) R eJA

33 °C/W

Junction to ambient

1

(@200 ft/min) Single layer board (1s) R eJMA

46 °C/W

Junction to ambient

1

(@200 ft/min) Four layer board (2s2p) R eJMA

29 °C/W

Junction to boards

2

— R eJB

22 °C/W

Junction to case (top)

3

Junction to package top

4

—

Natural convection

R eJCtop

Ψ

JT

13

2

°C/W

°C/W

1

2

3

4

Junction-to-ambient thermal resistance determined per JEDC JESD51-3 and JESD51-6. Thermal test board meets JEDEC specification for this package.

Junction-to-board thermal resistance determined per JEDC JESD51-8. Thermal test board meets JEDEC specification for this package.

Junction-to-case at the top of the package determined using MIL-STD 883 Method 1012.1. The cold plate temperature is used for the case temperature. Reported value includes the thermal resistance of the interface layer.

Thermal characterization parameter indicating the temperature difference between the package top and the junction temperature per JEDEC JESD51-2. When Greek letters are not available, this thermal characterization parameter is written as Psi-JT.

3.5

I/O DC Parameters

This section includes the DC parameters of the following I/O types:

• DDR I/O: Mobile DDR (mDDR), double data rate (DDR2), or synchronous dynamic random access memory (SDRAM)

• General purpose I/O (GPIO)

20



NOTE

The term ‘OVDD’ in this section refers to the associated supply rail of an input or output. The association is shown in the “Signal Multiplexing” chapter of the reference manual.

3.5.1

DDR I/O DC Parameters

The DDR pad type is configured by the IOMUXC_SW_PAD_CTL_GRP_DDRTYPE register (see the

External Signals and Pin Multiplexing chapter of the i.MX25 Reference Manual for details).

3.5.1.1

DDR_TYPE = 00 Standard Setting DDR I/O DC Parameters

Table 17 shows the I/O parameters for mobile DDR. These settings are suitable for mDDR and DDR2

1.8V (

± 5%) applications.

Table 17. Mobile DDR I/O DC Electrical Characteristics

DC Electrical Characteristics

High-level output voltage

Max.

—

Units

V

Low-level output voltage

High-level output current

Low-level output current

High-level DC CMOS input voltage

Low-level DC CMOS input voltage

Differential receiver VTH+

Differential receiver VTH-

Input current (no pull-up/down)

High-impedance I/O supply current

High-impedance core supply current

Symbol Test Conditions

Voh

Vol

Ioh

I

I

Iol

VIH

VIL

I

OH

= –1mA

I

OH

= Specified Drive

I

OL

= 1mA

I

OL

= Specified Drive

Voh = 0.8

× OVDDV

Standard Drive

High Drive

Max. Drive

Vol = 0.2

× OVDDV

Standard Drive

High Drive

Max. Drive

—

—

VTH+

VTH-

—

IIN VI = 0

VI = OVDD

Icc-ovdd VI = OVDD or 0

Icc-vddi VI = VDD or 0

Min.

OVDD – 0.08

0.8

× OVDD

—

—

—

Typ.

—

—

—

–3.6

–7.2

–10.8

—

3.6

7.2

10.8

0.7

× OVDD

OVDD

–0.3

0

–100

—

—

—

—

—

—

0.08

0.2

× OVDD

—

—

OVDD+0.3

0.3

× OVDD

100

—

110

60

990

1220

V mA mA nA nA

V

V mV mV nA



3.5.1.2

DDR_TYPE = 01 SDRAM I/O DC Parameters

Table 18 shows the DC I/O parameters for SDRAM.

Table 18. SDRAM DC Electrical Characteristics



Min.

2.4


High-level output current

Low-level output current

High-level DC input voltage

Low-level DC input voltage





Voh

Vol

I

Ioh

I

Iol

VIH

VIL

IIN

Icc-ovdd

Icc-vddi

Ioh = Specified Drive

(Ioh = –4, –8, –12, –16mA)


(Ioh = 4, 8, 12, 16mA)

Standard Drive

High Drive

Max. Drive

Standard Drive

High Drive

Max. Drive

—

—

VI = 0

VI = OVDD

VI = OVDD or 0

VI = VDD or 0

—

—

—

–4.0

–8.0

–12.0

4.0

8.0

12.0

2.0

–0.3 V

—

Typ.

—

—

—

—

—

—

—

—

—

Max.

—

0.4

—

Units

V

V mA

—

3.6

0.8

150

80

1180

1220 mA

3.5.1.3

DDR_TYPE = 10 Max Setting DDR I/O DC Parameters

Table 19 shows the I/O parameters for DDR2 (SSTL_18).

Table 19. DDR2 (SSTL_18) I/O DC Electrical Characteristics




Output min. source current

1

Output min. sink current

2

DC input logic high

DC input logic low

DC input signal voltage

3

(for differential signal)

DC differential input voltage

4


Voh

Vol

IIoh

IIol

VIH(dc)

VIL(dc)

Vin(dc)

Vid(dc)

—

—

—

—

—

—

—

—

Min.

OVDD – 0.28

—

–13.4

13.4

OVDD/2 + 0.125

–0.3 V

–0.3

0.25

—

Typ.

—

—

—

—

—

—

—

Max.

—

0.28

—

—

OVDD + 0.3

OVDD/2 – 0.125

OVDD + 0.3

Units

V

V mA mA

V

V

V

OVDD+0.6

V

V

V nA nA nA

22



Table 19. DDR2 (SSTL_18) I/O DC Electrical Characteristics (continued)

DC Electrical Characteristics Symbol Test Conditions Min.

Typ.

Max.

Units

Termination voltage

5

Input current

6

(no pull-up/down)

Vtt — OVDD/2 – 0.04

OVDD/2 OVDD/2 + 0.04

IIN VI = 0

VI = OVDD

— — 110

60 nA


6


6

Icc-ovdd VI = OVDD or 0

Icc-vddi VI = VDD or 0

—

—

—

—

980

1210 nA nA

3

4

5

6

1

2

OVDD = 1.7 V; V out

= 1.42 V. (V out

-OVDD)/IOH must be less than 21 W for values of V out

between OVDD and OVDD-0.28 V.

OVDD = 1.7 V; V out

= 280 mV. V out

/IOL must be less than 21 W for values of V out

between 0 V and 280 mV. Simulation circuit for parameters V oh

and V ol

for I/O cells is below.

Vin(dc) specifies the allowable DC excursion of each differential input.

Vid(dc) specifies the input differential voltage required for switching. The minimum value is equal to Vih(dc) - Vil(dc).

Vtt is expected to track OVDD/2.

Minimum condition: BCS model, 1.95 V, and –40 °C. Typical condition: typical model, 1.8 V, and 25 °C. Maximum condition: wcs model, 1.65 V, and 105 °C.

3.5.2

GPIO I/O DC Parameters

Table 20 shows the I/O parameters for GPIO.

Table 20. GPIO DC Electrical Characteristics



1


1

High-level output current for slow mode

High-level output current for fast mode

Low-level output current for slow mode

Low-level output current for fast mode

High-level DC input voltage

Low-level DC input voltage

Symbol

Voh

Vol

I

Ioh

I

Ioh

I

Iol

I

Iol

VIH

VIL

Test Conditions

Ioh=–1mA


Iol=1mA

Iol=Specified Drive

Voh=0.8

× OVDD

Standard Drive

High Drive

Max. Drive

Voh=0.8

× OVDD

Standard Drive

High Drive

Max. Drive

Voh=0.2

× OVDD

Standard Drive

High Drive

Max. Drive

Voh=0.2

× OVDD

Standard Drive

High Drive

Max. Drive

—

—

Min.

OVDD – 0.15

0.8

× OVDD

—

–2.0

–4.0

–8.0

–4.0

–6.0

–8.0

2.0

4.0

8.0

4.0

6.0

8.0

0.7

× OVDD

–0.3 V

Typ.

—

—

—

—

—

—

—

—

Max.

—

0.15

0.2

× OVDD

—

—

—

—

OVDD

0.3

× OVDD

Units

V

V mA mA mA mA

V

V



Table 20. GPIO DC Electrical Characteristics (continued)

DC Electrical Characteristics Symbol Test Conditions Min.

Typ.

Input hysteresis

Schmitt trigger VT+

1

Schmitt trigger VT–

1

Pull-up resistor (22 k

Ω PU)


Ω PU)


Ω PU)

Pull-down resistor (100 k

Ω PD)


VHYS

VT+

VT–

Rpu

Rpu

Rpu

Rpd

IIN

OVDD = 3.3 V

OVDD = 1.8V

—

—

Vi=0

Vi=0

Vi=0

VI = OVDD

VI = 0, OVDD = 3.3 V

VI = OVDD = 3.3 V

VI = 0, OVDD = 1.8 V

VI = OVDD = 1.8 V

VI = 0, OVDD = 3.3 V

VI = OVDD = 3.3 V

VI = 0, OVDD = 1.8 V

VI = OVDD = 1.8 V

370

290

0.5

× OVDD

—

18.5

41

85

85

—

—

Input current (22 k

Input current (47 k

Ω PU)

Ω PU)

Input current (100 k

Input current (100 k

Ω PU)

Ω PD)

IIN

IIN

IIN

IIN

VI = 0, OVDD = 3.3 V

VI = OVDD = 3.3 V

VI = 0, OVDD = 1.8 V

VI = OVDD = 1.8 V

VI = 0, OVDD = 3.3 V

VI = OVDD = 3.3 V

VI = 0, OVDD = 1.8 V

VI = OVDD = 1.8 V

VI = 0, OVDD = 3.3 V

VI = OVDD = 3.3 V

VI = 0, OVDD = 1.8 V

VI = OVDD = 1.8 V

117

0.0001

64

0.0001

54

0.0001

30

0.0001

25

0.0001

14

0.0001

25

0.0001

14

0.0001

—

—

—

—

High-impedance I/O supply current Icc–ovdd VI = 0, OVDD = 3.3 V

VI = OVDD = 3.3 V

VI = 0, OVDD = 1.8 V

VI = OVDD = 1.8 V

—

High-impedance core supply current Icc–vddi VI = 0, OVDD = 3.3 V

VI = OVDD = 3.3 V

VI = 0, OVDD = 1.8 V

VI = OVDD = 1.8 V

—

1

Hysteresis of 250 mV is guaranteed over all operating conditions when hysteresis is enabled.

—

—

—

—

22

47

100

100

—

Max.

420

320

—

0.5

× OVDD

25.6

55

120

120

100

60

77

50

184

0.0001

104

0.0001

88

0.0001

49

0.0001

42

0.0001

23

0.0001

42

0.001

23

0.0001

688

688

560

560

490

490

410

410

Units

mV

μA

μA

μA

μA nA nA

V

V k

Ω k

Ω k

Ω k

Ω nA

3.6

AC Electrical Characteristics

This section provides the AC parameters for slow and fast I/O.

24



Figure 3

shows the load circuit for output.

Figure 4 through Figure 6 show the output transition time and

propagation waveforms.

From Output

Under Test

Test Point

CL

CL includes package, probe and jig capacitance

Figure 3. Load Circuit for Output

Output (at pad)

80%

20%

PA1

PA1

Figure 4. Output Pad Transition Time Waveform

80%

OVDD

20%

0V

VDD

50% 50%

Input from core

(1 ns transition times)

0V tPLH tPHL

Output (at pad)

80%

50%

20% tTLH tTHL

Figure 5. Output Pad Propagation and Transition Time Waveform

OVDD

80%

50%

20%

0V signal “1” pdat from core

VDD signal “0” pdat from core

0

VDD

50% signal open from core tpv

50%

OVDD

Output (at pad)

Figure 6. Output Enable to Output Valid i.MX25 Applications Processor for Consumer and Industrial Products, Rev. 10


3.6.1

Slow I/O AC Parameters

Table 21 shows the slow I/O AC parameters.

Table 21. Slow I/O AC Parameters

Parameter

Duty cycle

Output pad transition times

1

(max. drive)


1

(high drive)


(standard drive)

1

Output pad propagation delay

(max. drive), 50%–50%


(high drive), 50%–50%


(standard drive), 50%–50%


(max. drive), 40%–60%





1

1

1

1

1

1

Symbol Test Voltage

Test

Capacitance

Fduty tpr tpr tpr tpo tpo tpo tpo tpo tpo

—

3.0–3.6 V

3.0–3.6 V

1.65–1.95 V

1.65–1.95 V

3.0–3.6 V

3.0–3.6 V

1.65–1.95 V

1.65–1.95 V

3.0–3.6 V

3.0–3.6 V

1.65–1.95 V

1.65–1.95 V

3.0–3.6 V

3.0–3.6 V

1.65–1.95 V

1.65–1.95 V

3.0–3.6 V

3.0–3.6 V

1.65–1.95 V

1.65–1.95 V

3.0–3.6 V

3.0–3.6 V

1.65–1.95 V

1.65–1.95 V

3.0–3.6 V

3.0–3.6 V

1.65–1.95 V

1.65–1.95 V

3.0–3.6 V

3.0–3.6 V

1.65–1.95 V

1.65–1.95 V

3.0–3.6 V

3.0–3.6 V

1.65–1.95 V

1.65–1.95 V

25 pF

50 pF

25 pF

50 pF

25 pF

50 pF

25 pF

50 pF

25 pF

50 pF

25 pF

50 pF

25 pF

50 pF

25 pF

50 pF

—

25 pF

50 pF

25 pF

50 pF

25 pF

50 pF

25 pF

50 pF

25 pF

50 pF

25 pF

50 pF

25 pF

50 pF

25 pF

50 pF

25 pF

50 pF

25 pF

50 pF

Min.

Rise/Fall

1.92/2.1

2.44/2.53

2.05/2.27

2.71/2.84

2.35/2.49

3.31/3.43

2.58/2.69

3.62/3.60

3.39/3.51

5.28/5.35

3.71/3.68

5.52/5.32

1.942/2.04

2.378/2.48

2.03/2.28

2.59/2.73

40

0.95/0.84

1.58/1.37

2.70/2.50

3.40/3.20

1.60/1.39

2.94/2.51

1.85/1.48

2.93/2.37

3.07/2.62

5.82/4.95

3.04/2.47

5.37/4.40

2.29/2.44

3.05/3.20

2.45/2.62

3.36/3.39

3.12/3.26

4.60/4.73

3.43/3.46

4.89/4.79

Max.

Rise/Fall

4.47/4.38

5.54/5.31

5.27/5.85

7.00/7.15

5.35/5.24

7.19/6.8

6.64/6.74

9.34/8.76

7.39/6.95

10.97/9.45

9.64/8.97

13.9/11.3

4.33/4.3

5.29/5.09

4.97/5.64

6.43/6.77

60

2.06/1.60

3.20/2.47

3.01/2.37

4.63/3.38

3.26/2.50

5.72/4.27

4.75/3.43

7.33/5.26

6.03/4.48

11.28/8.28

3.01/2.36

4.63/3.38

5.05/5.02

6.53/6.3

6.02/6.35

8.40/8.08

6.69/6.42

9.5/8.32

8.65/8.26

12.2/9.97

Units

% ns ns ns

Typ.

Rise/Fall

2.96/2.96

3.7/3.64

3.32/3.67

4.39/4.51

3.58/3.61

4.9/4.786

4.17/4.27

5.86/5.61

5.03/4.89

7.6/7.14

6.03/5.75

8.80/7.96

2.923/2.95

3.541/3.53

3.19/3.59

4.10/4.33

—

1.36/1.11

2.19/1.77

1.80/1.40

2.80/2.14

2.23/1.79

4.05/3.17

2.90/2.17

4.56/3.40

4.22/3.30

7.94/6.19

4.73/3.50

7.70/8.10

3.42/3.49

4.46/4.45

3.86/4.07

5.34/5.22

4.58/4.53

6.61/6.32

5.48/5.34

7.75/7.16

26



Table 21. Slow I/O AC Parameters (continued)

Output enable to output valid delay

1 delay

1

(max. drive), 50%–50%


1


1



1

Parameter


(max. drive), 40%–60%

Output enable to output valid



1


Output pad slew rate

2

(max. drive)


Output pad slew rate drive)

2

2

(high drive)

(standard

Symbol Test Voltage

Test

Capacitance

tpv tpv tpv tpv tpv tpv tps tps tps

3.0–3.6 V

3.0–3.6 V

1.65–1.95 V

1.65–1.95 V

3.0–3.6 V

3.0–3.6 V

1.65–1.95 V

1.65–1.95 V

3.0–3.6 V

3.0–3.6 V

1.65–1.95 V

1.65–1.95 V

3.0–3.6 V

3.0–3.6 V

1.65–1.95 V

1.65–1.95 V

3.0–3.6 V

3.0–3.6 V

1.65–1.95 V

1.65–1.95 V

3.0–3.6 V

3.0–3.6 V

1.65–1.95 V

1.65–1.95 V

3.0–3.6 V

3.0–3.6 V

1.65–1.95 V

1.65–1.95 V

3.0–3.6 V

3.0–3.6 V

1.65–1.95 V

1.65–1.95 V

3.0–3.6 V

3.0–3.6 V

1.65–1.95 V

1.65–1.95 V

25 pF

50 pF

25 pF

50 pF

25 pF

50 pF

25 pF

50 pF

25 pF

50 pF

25 pF

50 pF

25 pF

50 pF

25 pF

50 pF

25 pF

50 pF

25 pF

50 pF

25 pF

50 pF

25 pF

50 pF

25 pF

50 pF

25 pF

50 pF

25 pF

50 pF

25 pF

50 pF

25 pF

50 pF

25 pF

50 pF

Min.

Rise/Fall

Typ.

Rise/Fall

Max.

Rise/Fall

2.13/2.01

2.65/2.46

2.31/2.45

2.95/3.01

2.56/2.43

3.55/3.21

2.85/2.90

3.87/3.78

3.60/3.28

5.50/4.81

4.04/3.94

5.85/5.56

2.152/1.7

2.6/2.07

2.28/2.46

2.83/2.93

2.497/2.036

3.254/2.647

2.71/2.81

3.59/3.56

3.326/2.7

4.81/3.85

3.73/3.69

5.16/4.99

0.79/1.12

0.49/0.73

0.30/0.42

0.20/0.29

3.3/3.045

4.038/3.639

3.76/4.00

4.81/4.82

5.072/4.609

6.142/5.423

6.11/6.47

7.81/7.73

3.91/3.604

5.21/4.598

4.65/4.64

6.31/5.95

5.35/4.70

7.93/6.603

6.65/6.21

9.47/8.49

5.937/5.36

7.776/6.694

7.58/7.44

10.3/9.43

7.97/6.836

11.58/9.338

10.9/9.22

15.5/13.3

3.25/2.68

3.88/3.17

3.62/3.92

4.50/4.62

3.75/3.135

4.8/3.9

4.31/4.23

5.75/5.54

4.9/3.9

6.9/5.4

6.04/5.77

8.28/7.61

1.30/1.77

0.84/1.23

0.54/0.73

0.35/0.50

4.93/4.162

5.842/4.846

5.77/6.24

7.20/7.32

5.633/4.782

7.117/5.84

6.89/7.01

9.23/8.71

7.269/5.95

10.12/7.86

9.81/9.11

13.4/11.8

2.02/2.58

1.19/1.58

0.91/1.20

0.60/0.80

0.48/0.72

0.27/0.42

0.19/0.28

0.12/0.18

0.25/0.40

0.14/0.21

0.12/0.18

0.07/0.11

0.76/1.10

0.41/0.62

0.34/0.49

0.34/0.49

0.40/0.59

0.21/0.32

0.20/0.30

0.11/0.17

1.17/1.56

0.63/0.86

0.58/0/79

0.36/0.49

0.60/0.83

0.32/0.44

0.34/0.47

0.20/0.27

Units

ns ns

V/ns



Table 21. Slow I/O AC Parameters (continued)

Parameter Symbol Test Voltage

Test

Capacitance

Min.

Rise/Fall

Typ.

Rise/Fall

Max.

Rise/Fall

Units

Output pad dI/dt

Output pad dI/dt

Output pad dI/dt drive)

3

3

3

(max. drive)

(high drive)

(standard

Input pad propagation delay without hysteresis, 50%–50%

4

Input pad propagation delay with hysteresis, 50%–50%

4 tdit tdit tdit tpi tpi

3.0–3.6 V

3.0–3.6 V

1.65–1.95 V

1.65–1.95 V

3.0–3.6 V

3.0–3.6 V

1.65–1.95 V

1.65–1.95 V

3.0–3.6 V

3.0–3.6 V

1.65–1.95 V

1.65–1.95 V

—

—

25 pF

50 pF

25 pF

50 pF

25 pF

50 pF

25 pF

50 pF

25 pF

50 pF

25 pF

50 pF

1.6 pF

1.6 pF

15

16

7

7

8

9

5

5

4

4

2

2

0.82/0.47

0.74/1

1.1/1.3

1.75/1.63

36

38

21

22

20

21

14

15

10

10

7

7

1.1/0.76

1.1/1.5

1.43/1.6

2.67/2.22

76

80

56

58

45

47

38

40

22

23

18

19

1.6/1.04

1.75/2.16

2/2

2.92/3 mA

/ns ns

Input pad propagation delay without hysteresis, 40%–60%

4

Input pad propagation delay with hysteresis, 40%–60%

4 tpi tpi

—

—

1.6 pF

1.6 pF

1.62/1.28

1.82/1.55

1.88/2.1

2.4/2.6

0.16/0.12

1.9/1.56

2.28/1.87

2.2/2.4

3/3.07

0.23/0.18

2.38/1.82

2.95/2.54

2.7/2.75

3.77/3.71

0.33/0.29

Input pad transition times without hysteresis

4 trfi — 1.6 pF

Input pad transition times with hysteresis

4

Maximum input transition times

5 trfi 1.6 pF 0.16/0.13

0.22/0.18

0.33/0.29

trm — — — — 25 ns

3

4

1

2

5

Maximum condition for tpr, tpo, and tpv: wcs model, 1.1 V, I/O 3.0 V (3.0–3.6 V range) or 1.65 V (1.65–1.95 V range), and 105

°C. Minimum condition for tpr, tpo, and tpv: bcs model, 1.3 V, I/O 3.6 V (3.0–3.6 V range) or 1.95 V (1.65–1.95 V range), and

–40 °C. Input transition time from core is 1 ns (20%–80%).

Minimum condition for tps: wcs model, 1.1 V, I/O 3.0 V (3.0–3.6 V range) or 1.65 V (1.65–1.95 V range), and 105 °C. tps is measured between VIL to VIH for rising edge and between VIH to VIL for falling edge.

Maximum condition for tdit: bcs model, 1.3 V, I/O 3.6 V (3.0–3.6 V range) or 1.95 V (1.65–1.95 V range), and –40 °C.

Maximum condition for tpi and trfi: wcs model, 1.1 V, I/O 3.0 V (3.0–3.6 V range) or 1.65 V (1.65–1.95 V range), and 105 °C.

Minimum condition for tpi and trfi: bcs model, 1.3 V, I/O 3.6 V or 1.95 V (1.65–1.95 V range), and –40 °C. Input transition time from pad is 5 ns (20%–80%).

Hysteresis mode is recommended for input with transition time greater than 25 ns.

28



3.6.2

Fast I/O AC Parameters

Table 22 shows the fast I/O AC parameters for OVDD = 1.65–1.95 V.

Table 22. Fast I/O AC Parameters for OVDD = 1.65

–

1.95 V

Parameter

Duty cycle


1

(max. drive)


1

(high drive)


1

(standard drive)


1

(max. drive),

50%–50%


1

(high drive),

50%–50%


1

(standard drive),

50%–50%


1

(max. drive),

40%–60%


1

(high drive),

40%–60%


1

(standard drive),

40%–60%


1

(max. drive),

50%–50%


1

(high drive),

50%–50%


1



1

(max. drive),

40%–60%


1

(high drive),

40%–60%


1



2

(max. drive)


2

(high drive)


2

(standard drive)

Symbol

Fduty tpr tpr tpr tpo tpo tpo tpo tpo tpo tpv tpv tpv tpv tpv tpv tps tps tps

Test

Condition

25 pF

50 pF

25 pF

50 pF

25 pF

50 pF

25 pF

50 pF

25 pF

50 pF

25 pF

50 pF

25 pF

50 pF

25 pF

50 pF

25 pF

50 pF

25 pF

50 pF

25 pF

50 pF

—

25 pF

50 pF

25 pF

50 pF

25 pF

50 pF

25 pF

50 pF

25 pF

50 pF

25 pF

50 pF

25 pF

50 pF

Typ.

4.06/3.50

5.50/4.73

3.00/2.69

3.65/3.24

3.28/2.33

4.04/3.59

3.80/3.18

5.03/4.37

0.72/0.97

0.43/0.61

0.59/0.81

0.34/0.50

0.40/0.55

0.23/0.34

—

1.36/1.10

2.20/1.80

1.65/1.33

2.80/2.20

2.47/1.95

4.20/3.20

2.68/2.41

3.47/3.08

2.98/2.66

3.96/3.49

3.63/3.15

5.09/4.41

2.63/2.38

3.30/2.97

2.89/2.61

3.69/3.30

3.39/2.99

4.65/4.07

3.06/2.71

3.83/3.37

3.67/2.98

4.32/3.78

Min.

Rise/Fall

2.49/2.25

3.40/3.08

1.90/1.74

2.30/2.13

2.06/1.90

2.56/2.37

2.39/2.18

3.16/2.89

0.40/0.57

0.25/0.36

0.38/0.48

0.20/0.30

0.23/0.32

0.13/0.20

40

0.88/0.77

1.45/1.24

1.10/0.92

1.84/1.54

1.60/1.35

2.74/2.26

1.64/1.53

2.15/2.01

1.82/1.71

2.46/2.29

2.24/2.06

3.17/2.92

1.67/1.58

2.09/1.98

1.94/1.73

2.34/2.22

2.15/1.99

2.94/2.74

1.87/1.70

2.36/2.16

2.05/1.88

2.68/2.45

Max.

Rise/Fall

6.57/5.49

8.88/7.37

4.76/4.18

5.79/5.02

5.21/4.54

6.43/5.54

6.05/5.14

8.02/6.72

1.2/1.5

0.72/0.95

0.98/1.27

0.56/0.72

0.66/0.87

0.38/0.52

60

2.10/1.70

3.50/2.70

2.64/2.10

4.40/3.30

3.99/3.10

6.56/4.86

4.25/3.74

5.50/4.77

4.74/4.13

6.27/5.37

5.73/4.84

8.06/6.75

4.06/3.63

5.14/4.51

4.49/3.97

5.76/5.01

5.28/4.53

7.28/6.13

4.97/4.30

6.18/5.30

5.46/4.72

6.98/5.92

Units

% ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns

V/ns

V/ns

V/ns




–

1.95 V (continued)


Test

Condition

Min.

Rise/Fall

Typ.

Max.

Rise/Fall

Units

Output pad dI/dt

Output pad dI/dt

3

3

(max. drive)

(high drive) tdit tdit

25 pF

50 pF

25 pF

50 pF

25 pF

50 pF

7

7

11

12

9

10

43

46

31

33

27

28

112

118

81

85

71

74 mA/ns mA/ns

Output pad dI/dt

3

(standard drive)

Input pad propagation delay without hysteresis,

50%–50%

4

Input pad propagation delay with hysteresis,

50%–50%

4 tdit tpi tpi

1.6 pF

1.6 pF

0.74/1

1.75/1.63

1.1/1.5

2.67/2.22

1.75/2.16

2.92/3 mA/ns ns ns

Input pad propagation delay without hysteresis,

40%–60%

4 tpi 1.6 pF 1.82/1.55

2.28/1.87

2.95/2.54

ns

Input pad propagation delay with hysteresis,

40%–60%

4

Input pad transition times without hysteresis

4

Input pad transition times with hysteresis

4

Maximum input transition times

5 tpi trfi trfi

1.6 pF

1.6 pF

1.6 pF

2.4/2.6

0.16/0.12

0.16/0.13

3/3.07

0.30/0.18

0.30/0.18

3.77/3.71

0.33/0.29

0.33/0.29

ns ns ns trm — — — 25 ns

1

2

3

4

5

Maximum condition for tpr, tpo, and tpv: wcs model, 1.1 V, I/O 1.65 V, and 105 °C. Minimum condition for tpr, tpo, and tpv: bcs model, 1.3 V, I/O 1.95 V, and –40 °C. Input transition time from core is 1 ns (20%–80%).

Minimum condition for tps: wcs model, 1.1 V, I/O 1.65 V and 105 °C. tps is measured between VIL to VIH for rising edge and between VIH to VIL for falling edge.

Maximum condition for tdit: bcs model, 1.3 V, I/O 1.95 V and –40 °C.

Maximum condition for tpi and trfi: wcs model, 1.1 V, I/O 1.65 V and 105 °C. Minimum condition for tpi and trfi: bcs model, 1.3 V,

I/O 1.95 V and –40 °C. Input transition time from pad is 5 ns (20%–80%).


Table 23 shows the fast I/O AC parameters for OVDD = 3.0–3.6 V.


–

3.6 V

Parameter

Duty Cycle

Output Pad Transition Times

1

(Max Drive)


1

(High Drive)


1

(Standard Drive)

Output Pad Propagation Delay

1

(Max Drive),

50%–50%

Symbol

Test

Condition

Fduty tpr tpr tpr tpo

25 pF

50 pF

25 pF

50 pF

25 pF

50 pF

25 pF

50 pF

Min.

Rise/Fall

40

0.80/0.70

1.40/1.60

1.00/0.90

1.95/1.66

1.50/1.30

2.90/2.50

1.20/1.28

1.67/1.75

Typ.

1.12/2.51

1.60/2.39

1.43/1.16

2.66/2.09

2.09/1.67

3.40/3.09

1.74/1.73

2.39/2.32

Max.

Rise/Fall

60

1.64/1.32

2.84/2.10

2.05/1.60

3.70/2.80

3.00/2.30

5.56/4.12

2.67/2.52

3.58/3.33

Units

% ns ns ns ns

30




–



1

(High Drive),

50%–50%


1

(Standard Drive),

50%–50%


1

(Max Drive),

40%–60%


1

(High Drive),

40%–60%


1

(Standard Drive),

40%–60%

Output Enable to Output Valid Delay

1

(Max Drive),

50%–50%


1

(High Drive),

50%–50%


1

(Standard

Drive), 50%–50%


1

(Max Drive),

40%–60%


1

(High Drive),

40%–60%


1

(Standard

Drive), 40%–60%

Output Pad Slew Rate

2

(Max Drive)


2

(High Drive) tpo tpo tpo tpo tpo tpv tpv tpv tpv tpv tpv tps tps

25 pF

50 pF

25 pF

50 pF

25 pF

50 pF

25 pF

50 pF

25 pF

50 pF

25 pF

50 pF

25 pF

50 pF

25 pF

50 pF

25 pF

50 pF

25 pF

50 pF

25 pF

50 pF

25 pF

50 pF

25 pF

50 pF

1.35/1.42

1.98/2.04

1.77/1.85

2.70/2.78

1.37/1.50

1.74/1.88

1.48/1.61

1.98/2.10

1.84/1.97

2.58/2.71

1.34/1.32

1.81/1.79

1.48/1.47

2.12/2.1

1.90/1.90

2.85/2.83

1.55/1.42

1.93/1.81

1.67/1.54

2.16/2.03

2.02/1.90

2.76/2.63

0.96/1.40

0.54/0.83

0.76/1.10

0.41/0.64

1.95/1.91

2.81/2.68

2.54/2.48

3.82/3.62

1.94/2.05

2.46/2.55

2.11/2.19

2.78/2.81

2.61/2.67

3.62/3.58

1.91/1.81

2.56/2.40

2.12/2.00

2.98/2.76

2.70/2.60

4.00/3.70

2.25/2.08

2.77/2.58

2.41/2.23

3.08/2.86

2.91/2.71

3.91/3.62

1.54/2.10

0.85/1.24

1.19/1.71

0.63/0.95


2

(Standard Drive) tps

Output Pad di/dt

3

(Max Drive)

Output Pad di/dt

3

(High Drive) didt didt

25 pF

50 pF

25 pF

50 pF

25 pF

50 pF

0.52/0.78

0.28/0.44

46

49

35

37

0.80/1.19

0.43/0.64

108

113

82

86

Output Pad di/dt

3

(Standard Drive) didt tpi

25 pF

50 pF

1.6pF

22

23

52

55

Input Pad Propagation Delay without Hysteresis,

50%–50%

4

Input Pad Propagation Delay with Hysteresis,

50%–50%

4 tpi 1.6pF

1.20/1.60

0.63/0.87

250

262

197

207

116

121

0.729/0.458

0.97/0.0649

1.404/0.97

1.203/0.938

1.172/1.187

1.713/1.535

2.96/2.76

4.16/3.78

3.80/3.60

5.62/5.10

2.95/3.07

3.71/3.75

3.19/3.26

4.14/4.09

3.95/3.95

5.36/5.15

2.92/2.67

3.83/3.47

3.21/2.92

4.41/3.94

4.07/3.74

5.86/5.24

3.50/3.31

4.24/3.99

3.74/3.51

4.66/4.34

4.48/4.21

5.85/5.39

2.30/3.00

1.26/1.70

1.78/2.39

0.95/1.30

Input Pad Propagation Delay without Hysteresis,

40%–60%

4 tpi 1.6pF

0.879/0.977

1.434/1.12

1.854/1.427

ns ns ns ns ns ns ns ns ns ns ns

V/ns

V/ns

V/ns mA/ns mA/ns mA/ns ns ns ns




–


Input Pad Propagation Delay with Hysteresis,

40%–60%

4

Input Pad Transition Times without Hysteresis

4

Input Pad Transition Times with Hysteresis

4

Maximum Input Transition Times

5 tpi trfi trfi

1.6pF

1.6pF

1.6pF

1.353/1.457

0.16/0.12

0.16/0.13

1.637/1.659

0.23/0.18

0.22/0.18

2.163/1.991

0.33/0.29

0.33/0.29

ns ns ns trm — — — — ns

3

4

1

2

5

Maximum condition for tpr, tpo, and tpv: wcs model, 1.1 V, IO 3.0 V and 105 °C. Minimum condition for tpr, tpo, and tpv: bcs model, 1.3 V, IO 3.6 V and –40 °C. Input transition time from core is 1ns (20%–80%).

Minimum condition for tps: wcs model, 1.1 V, IO 3.0 V and 105 °C. tps is measured between VIL to VIH for rising edge and between VIH to VIL for falling edge.

Maximum condition for tdit: bcs model, 1.3 V, IO 3.6 V and –40 °C.

Maximum condition for tpi and trfi: wcs model, 1.1 V, IO 3.0 V and 105 °C. Minimum condition for tpi and trfi: bcs model, 1.3 V,

IO 3.6 V and –40 °C. Input transition time from pad is 5 ns (20%–80%).


3.6.3

DDR I/O AC Parameters

The DDR pad type is configured by the IOMUXC_SW_PAD_CTL_GRP_DDRTYPE register (see

Chapter 4, “External Signals and Pin Multiplexing,” in the i.MX25 Multimedia Applications Processor

Reference Manual).

3.6.3.1

DDR_TYPE = 00 Standard Setting I/O AC Parameters and Requirements

Table 24 shows AC parameters for mobile DDR I/O. These settings are suitable for mDDR and DDR2

1.8V (

± 5%) applications.

Table 24. AC Parameters for Mobile DDR I/O

Parameter

Duty cycle

Clock frequency

1


1

(max. drive)


1

(high drive)


1

(standard drive)


1

(max. drive),

50%–50%


1

(high drive),

50%–50%


1

(standard drive),

50%–50%


1

(max. drive),

40%–60%

Symbol

Fduty f tpr tpr tpr tpo tpo tpo tpo

Load

Condition

15 pF

35 pF

15 pF

35 pF

15 pF

35 pF

15 pF

35 pF

—

—

25 pF

50 pF

25 pF

50 pF

25 pF

50 pF

Min.

Rise/Fall

40

—

0.52/0.51

0.98/0.96

1.13/1.10

2.15/2.10

2.26/2.19

4.30/4.18

0.80/1.03

1.06/1.32

1.04/1.27

1.63/1.90

1.55/1.80

2.72/3.06

0.80/0.91

1.06/1.12

Typ.

Max.

Rise/Fall

50

—

0.79/0.72

1.49/1.34

1.74/1.55

3.28/2.92

60

133

1.25/1.09

2.31/1.98

2.71/2.30

5.11/4.31

3.46/3.07

6.59/5.79

5.39/4.56

10.13/8.55

1.36/1.50

1.76/1.90

1.74/1.83

2.63/2.69

2.21/2.40

2.83/2.82

2.79/2.70

4.18/3.86

2.53/2.57

4.31/4.29

1.44/1.59

1.76/1.91

4.03/3.76

6.80/6.19

2.24/2.29

2.74/2.75

Units

%

MHz ns ns ns ns ns ns ns

32



Table 24. AC Parameters for Mobile DDR I/O (continued)


Load

Condition

Min.

Rise/Fall

Typ.

Max.

Rise/Fall

Units


1

(high drive),

40%–60%


1

(standard drive),

40%–60%


1

(max. drive),

50%–50%


1

(high drive),

50%–50%


1



1

(max. drive),

40%–60%


1

(high drive),

40%–60%


1



2

(max. drive) tpo tpo tpv tpv tpv tpv tpv tpv

15 pF

35 pF

15 pF

35 pF

15 pF

35 pF

15 pF

35 pF

15 pF

35 pF

15 pF

35 pF

15 pF

35 pF

15 pF

35 pF

1.04/1.09

1.63/1.56

1.50/1.74

2.73/2.42

1.17/1.01

1.43/1.30

1.38/1.28

1.97/1.92

1.92/1.57

3.12/3.16

1.28/1.12

1.49/1.36

1.43/1.33

1.90/1.84

1.85/1.78

2.80/2.81

1.73/1.83

2.43/2.52

2.36/2.41

3.77/3.78

1.93/1.61

2.33/2.00

2.25/1.99

3.16/2.86

3.11/2.79

4.97/4.59

2.01/1.70

2.33/2.01

2.24/1.99

2.96/2.68

2.91/2.62

4.37/4.53

2.69/2.62

3.79/3.62

3.67/3.46

5.86/5.37

3.06/2.55

3.69/3.13

3.58/3.10

5.01/4.39

4.98/4.13

7.97/6.98

3.09/2.60

3.60/3.06

3.47/3.02

4.59/4.03

4.54/3.96

6.88/6.05

ns ns ns ns ns ns ns ns tps 25 pF

50 pF

0.80/0.92

0.43/0.50

1.35/1.50

0.72/0.81

2.23/2.27

1.66/1.68

V/ns


2

(high drive) tps 25 pF

50 pF

0.37/0.43

0.19/0.23

0.62/0.70

0.33/0.37

1.03/1.05

0.75/0.77

V/ns


2

(standard drive) tps 25 pF

50 pF

0.18/0.22

0.10/0.12

0.31/0.35

0.16/0.18

0.51/0.53

0.38/0.39

V/ns

Output pad dI/dt

3

(max. drive) tdit 25 pF

50 pF

64

69

171

183

407

432 mA/ns

Output pad dI/dt

3

(high drive) tdit 25 pF

50 pF

37

39

100

106

232

246 mA/ns

Output pad di/dt

3

(standard drive) tdit 25 pF

50 pF

18

20

50

52

116

123 mA/ns

Input pad transition times

4

Input pad propagation delay, 50%–50%

4


4 trfi tpi

1.0 pF

1.0 pF

0.07/0.08

0.77/1.00

0.11/0.13

1.22/1.45

0.16/0.20

1.89/2.21

ns ns tpi 1.0 pF 1.59/1.82

2.04/2.27

2.69/3.01

ns

3

4

1

2

Maximum condition for tpr, tpo, tpi, and tpv: wcs model, 1.1 V, I/O 1.65 V, and 105 °C. Minimum condition for tpr, tpo, and tpv: bcs model, 1.3 V, I/O 1.95 V and –40 °C. Input transition time from core is 1 ns (20%–80%).

Minimum condition for tps: wcs model, 1.1 V, I/O 1.65 V, and 105 °C. tps is measured between VIL to VIH for rising edge and between VIH to VIL for falling edge.

Maximum condition for tdit: bcs model, 1.3 V, I/O 1.95 V, and –40 °C.





Table 25 shows the AC parameters for mobile DDR pbijtov18_33_ddr_clk I/O.

Table 25. AC Parameters for Mobile DDR pbijtov18_33_ddr_clk I/O

Parameter

Duty cycle

Clock frequency

1


1

(max. drive)


1

(high drive)


1

(standard drive)


1

(max. drive),

50%–50% input signals and crossing of output signals


1

(high drive),



1

(standard drive),



1

(max. drive),



1

(high drive),



1

(standard drive),



1

(max. drive),

50%–50%


1

(high drive),

50%–50%


1



1

(max. drive),

40%–60%


1

(high drive),

40%–60%


1



2

(max. drive)

Symbol

Fduty f tpr tpr tpr tpo tpo tpo tpo tpo tpo tpv tpv tpv tpv tpv tpv tps

Load

Condition

—

—

25 pF

50 pF

25 pF

50 pF

25 pF

50 pF

15 pF

35 pF

15 pF

35 pF

15 pF

35 pF

15 pF

35 pF

15 pF

35 pF

15 pF

35 pF

15 pF

35 pF

15 pF

35 pF

15 pF

35 pF

15 pF

35 pF

15 pF

35 pF

15 pF

35 pF

25 pF

50 pF

Min.

Rise/Fall

40

—

0.52/0.51

0.98/0.96

1.13/1.10

2.15/2.10

2.26/2.19

4.30/4.18

1.28/1.19

1.56/1.47

1.54/1.43

2.14/2.04

2.05/1.94

3.27/3.16

1.45/1.36

1.73/1.64

1.70/1.60

2.31/2.21

2.22/2.11

3.43/3.32

1.16/1.12

1.42/1.41

1.39/1.39

1.98/2.02

1.90/1.94

3.07/3.20

1.28/1.24

1.49/1.47

1.45/1.44

1.92/1.95

1.85/1.88

2.78/2.88

0.37/0.45

0.30/0.36

Typ.

Max.

Rise/Fall

50

—

0.79/0.72

1.49/1.34

1.74/1.55

3.28/2.92

3.46/3.07

6.59/5.79

1.97/1.83

2.37/2.23

60

133

1.25/1.09

2.31/1.98

2.71/2.30

5.11/4.31

5.39/4.56

10.13/8.55

2.98/2.78

3.57/3.37

2.34/2.20

3.22/3.08

3.54/3.33

4.85/4.65

3.11/2.96

4.86/4.72

4.70/4.50

7.33/7.12

2.13/2.00

2.53/2.40

3.14/2.94

3.74/3.54

2.51/2.37

3.38/3.24

3.70/3.50

5.02/4.82

3.27/3.13

5.02/4.88

4.87/4.66

7.49/7.29

1.91/1.81

2.31/2.20

2.28/2.18

3.18/3.04

3.09/2.94

4.88/4.66

2.00/1.90

2.32/2.21

2.28/2.19

2.99/2.87

2.92/2.79

4.34/4.16

0.64/0.79

0.52/0.61

3.10/2.89

3.72/3.47

3.69/3.43

5.08/4.69

4.95/4.55

7.73/7.05

3.14/2.93

3.64/3.41

3.60/3.36

4.69/4.36

4.5894.25

6.79/6.24

1.14/1.36

0.90/1.02

Units

%

MHz ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns

V/ns

34



Table 25. AC Parameters for Mobile DDR pbijtov18_33_ddr_clk I/O (continued)


Load

Condition

Min.

Rise/Fall

Typ.

Max.

Rise/Fall

Units


2


50 pF

0.30/0.37

0.21/0.25

0.51/0.63

0.36/0.42

091/1.06

0.63/0.67

V/ns


2


50 pF

0.22/0.26

0.13/0.16

0.37/0.44

0.23/0.26

0.65/0.72

0.39/0.40

V/ns

Output pad dI/dt

3


50 pF

65

70

171

183

426

450 mA/ns

Output pad dI/dt

3


50 pF

31

33

82

87

233

245 mA/ns

Output pad dI/dt

3


50 pF

16

17

43

46

115

120 mA/ns


4


4


4 trfi tpi

1.0 pF

1.0 pF

0.07/0.08

0.84/0.84

0.11/0.13

1.40/1.34

0.16/0.20

2.25/2.16

ns ns tpi 1.0 pF 1.66/1.66

2.22/2.16

3.06/2.97

ns

3

4

1

2






Table 26

shows the AC requirements for mobile DDR I/O.

Table 26. AC Requirements for Mobile DDR I/O

Parameter

AC input logic high

AC input logic low

AC differential input voltage

AC differential cross point voltage for input

Symbol

VIH(ac)

VIL(ac)

Vid(ac)

Vix(ac)

Min.

0.8

× OVDD

–0.3

0.6

× OVDD

0.4

× OVDD

Max.

OVDD+0.3

0.2

× OVDD

OVDD+0.6

OVDD+0.6

Units

V

V

V

V



3.6.3.2

DDR_TYPE = 01 SDRAM I/O AC Parameters and Requirements

Table 27 shows AC parameters for SDRAM I/O.

Table 27. AC Parameters for SDRAM I/O

Parameter

Duty cycle

Clock frequency

1


1

(max. drive)


1

(high drive)


1

(standard drive)


1

(max. drive),

50%–50%


1

(high drive),

50%–50%


1

(standard drive),

50%–50%


1

(max. drive),

40%–60%


1

(high drive),

40%–60%


1

(standard drive),

40%–60%


1

(max. drive),

50%–50%


1

(high drive),

50%–50%


1

(standard drive),

50%–50%


1

(max. drive),

40%–60%


1

(high drive),

40%–60%


1

(standard drive),

40%–60%


2

(max. drive)


2

(high drive)

Symbol

Fduty f tpr tpr tpr tpo tpo tpo tpo tpo tpo tpv tpv tpv tpv tpv tpv tps tps

Load

Condition

—

—

25 pF

50 pF

15 pF

35 pF

15 pF

35 pF

15 pF

35 pF

15 pF

35 pF

25 pF

50 pF

25 pF

50 pF

15 pF

35 pF

15 pF

35 pF

15 pF

35 pF

15 pF

35 pF

15 pF

35 pF

15 pF

35 pF

15 pF

35 pF

15 pF

35 pF

25 pF

50 pF

25 pF

50 pF

Min.

Rise/Fall

Typ.

Max.

Rise/Fall

1.71/1.68

3.22/3.12

3.38/3.27

6.38/6.23

1.69/0.75

2.02/2.30

1.72/1.93

2.54/2.85

2.45/2.69

4.10/4.51

1.53/1.73

1.96/2.23

1.72/1.93

2.37/2.66

2.30/2.52

3.59/3.97

1.44/1.89

1.66/2.51

1.58/2.16

2.06/3.09

2.02/3.00

3.00/4.91

1.54/1.94

1.74/2.44

1.65/2.15

2.03/2.89

1.99/2.83

2.76/4.30

1.74/1.75

0.92/0.94

1.16/1.19

0.61/0.63

1.23/1.31

2.31/2.47

2.44/2.60

4.65/4.99

0.97/1.19

2.85/3.21

1.15/1.39

3.57/3.91

2.01/1.57

5.73/6.05

1.06/1.26

1.38/1.38

1.15/1.20

1.75/1.67

1.91/2.01

2.88/2.56

0.90/1.27

1.07/1.77

1.01/1.48

1.37/2.33

1.32/2.14

2.04/3.67

1.03/1.34

1.16/1.74

1.11/1.51

1.39/2.10

1.35/2.03

1.91/3.23

1.11/1.20

0.97/0.65

0.76/0.80

0.40/0.43

40

—

0.82/0.87

1.56/1.67

50

—

1.14/1.13

2.13/2.09

3.54/3.77

5.84/6.13

2.18/2.47

2.78/3.12

2.45/2.71

3.35/3.67

3.26/3.50

5.06/5.36

2.19/2.87

2.51/3.69

2.38/3.23

3.06/4.46

3.01/4.36

4.40/6.90

2.26/2.88

2.55/3.54

2.43/3.16

2.95/4.13

2.89/4.03

3.98/6.01

2.42/2.46

1.39/1.30

1.76/1.66

0.93/0.87

60

133

1.62/1.50

3.015/2.7

7

2.39/2.22

4.53/4.16

4.73/4.38

9.05/8.23

2.17/2.46

2.93/3.27

2.51/2.77

3.66/3.97

Units

%

MHz ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns

V/ns

V/ns

36



Table 27. AC Parameters for SDRAM I/O (continued)


Load

Condition

Min.

Rise/Fall

Typ.

Max.

Rise/Fall

Units


2


50 pF

0.38/0.41

0.20/0.22

0.59/0.60

0.31/0.32

0.89/0.82

0.47/0.43

V/ns

Output pad dI/dt

3


50 pF

89

94

198

209

398

421 mA/ns

Output pad dI/dt

3


50 pF

59

62

132

139

265

279 mA/ns

Output pad dI/dt

3


50 pF

29

31

65

69

132

139 mA/ns


4


4


4 trfi tpi

1.0 pF

1.0 pF

0.07/0.08

0.35/1.17

0.11/0.12

0.63/1.53

0.16/0.20

1.16/2.04

ns ns tpi — 1.18/1.99

1.45/2.35

1.97/2.85

—

1

2

3

4






Table 28 shows AC parameters for SDRAM pbijtov18_33_ddr_clk I/O.

Table 28. AC Parameters for SDRAM pbijtov18_33_ddr_clk I/O

Parameter

Duty cycle

Clock frequency

1


1

(max. drive)


1

(high drive)


1

(standard drive)


1

(max. drive),



1

(high drive),



1

(standard drive),



1

(max. drive),


Symbol

Fduty f tpr tpr tpr tpo tpo tpo tpo

Load

Condition

—

—

25 pF

50 pF

25 pF

50 pF

25 pF

50 pF

15 pF

35 pF

15 pF

35 pF

15 pF

35 pF

15 pF

35 pF

Min.

Rise/Fall

Typ.

Max.

Rise/Fall

40

—

0.82/0.87

1.56/1.67

1.23/1.31

2.31/2.47

2.44/2.60

4.65/4.99

1.50/1.40

1.95/1.85

1.69/1.59

2.35/2.25

2.26/2.15

3.59/3.49

1.67/1.57

2.11/2.02

50

—

60

133

1.14/1.13

2.13/2.09

1.62/1.50

3.015/2.7

7

1.71/1.68

3.22/3.12

3.38/3.27

6.38/6.23

2.39/2.22

4.53/4.16

4.73/4.38

9.05/8.23

2.23/2.07

2.81/2.66

3.28/3.04

4.06/3.82

2.48/2.32

3.35/3.19

3.24/3.08

4.98/4.82

3.63/3.38

4.80/4.56

4.66/4.42

7.00/6.75

2.39/2.24

2.97/2.82

3.45/3.21

4.23/3.99

Units

%

MHz ns ns ns ns ns ns ns



Table 28. AC Parameters for SDRAM pbijtov18_33_ddr_clk I/O (continued)


Load

Condition

Min.

Rise/Fall

Typ.

Max.

Rise/Fall

Units


1

(high drive),



1

(standard drive),



1

(max. drive),

50%–50%


1

(high drive),

50%–50%


1

(standard drive),

50%–50%


1

(max. drive),

40%–60%


1

(high drive),

40%–60%


1

(standard drive),

40%–60%


2

(max. drive) tpo tpo tpv tpv tpv tpv tpv tpv

15 pF

35 pF

15 pF

35 pF

15 pF

35 pF

15 pF

35 pF

15 pF

35 pF

15 pF

35 pF

15 pF

35 pF

15 pF

35 pF

1.85/1.75

2.52/2.42

2.42/2.32

3.76/3.66

1.37/1.34

1.77/1.83

1.55/1.56

2.15/2.29

2.07/2.18

3.28/3.65

1.46/1.42

1.77/1.81

1.60/1.59

2.07/2.18

2.01/2.09

2.96/3.26

2.65/2.49

3.51/3.36

3.40/3.25

5.15/4.99

2.22/2.02

2.77/2.63

2.46/2.30

3.28/3.21

3.20/3.08

4.84/4.90

2.28/2.07

2.71/2.56

2.47/2.30

3.12/3.02

3.05/2.91

4.34/4.37

3.79/3.55

4.97/4.72

4.83/4.59

7.17/6.92

3.53/3.12

4.30/3.92

3.87/3.47

5.02/4.67

4.92/4.50

7.21/6.89

3.54/3.13

4.15/3.78

3.82/3.41

4.72/4.37

4.64/4.23

6.45/6.13

ns ns ns ns ns ns ns ns tps 25 pF

50 pF

1.11/1.20

0.60/0.65

1.74/1.75

0.93/0.95

2.63/2.48

1.39/1.29

V/ns


2


50 pF

0.75/0.81

0.40/0.43

1.16/1.18

0.62/0.64

1.76/1.65

094/0.87

V/ns


2


50 pF

0.38/0.41

0.20/0.22

0.59/0.61

0.31/0.32

0.89/0.83

0.47/0.43

V/ns

Output pad dI/dt

3


50 pF

89

95

202

213

435

456 mA/ns

Output pad dI/dt

3


50 pF

60

63

135

142

288

302 mA/ns

Output pad dI/dt

3


50 pF

29

31

67

70

144

150 mA/ns


4


4


4 trfi tpi

1.0 pF

1.0 pF

0.07/0.08

0.56/0.69

0.11/0.12

0.87/1.08

0.16/0.20

1.37/1.62

ns ns tpi 1.38/1.51

1.68/1.89

2.18/2.42

3

4

1

2






38



3.6.3.3

DDR_TYPE = 10 Max Setting I/O AC Parameters and Requirements

Table 29 shows AC parameters for DDR2 I/O.

Table 29. AC Parameters for DDR2 I/O


Load

Condition

Min.

Rise/Fall

Typ.

Max.

Rise/Fall

Units

Duty cycle Fduty — 40 50 60 %

Clock frequency


1 f tpr

—

25 pF

50 pF

—

0.53/0.52

1.01/0.98

—

0.80/0.72

1.49/1.34

133

1.19/1.04

2.21/1.90

MHz ns

Output pad propagation delay, 50%–50%

1 tpo 25 pF

50 pF

0.93/1.25

1.26/1.54

1.56/1.70

2.07/2.19

2.52/2.53

3.29/3.24

ns

Output pad propagation delay, 40%–60%

1 tpo 25 pF

50 pF

1.01/1.17

1.27/1.53

1.60/1.75

2.00/2.14

2.49/2.52

3.11/3.10

ns

Output enable to output valid delay, 50%–50%

1 tpv 25 pF

50 pF

1.30/1.19

1.62/1.54

2.17/1.81

2.56/2.29

3.35/2.84

3.35/2.54

ns


1 tpv 25 pF

50 pF

1.39/1.27

1.64/1.55

2.13/1.86

2.62/2.23

3.38/2.83

4.14/2.38

ns


2 tps 25 pF

50 pF

0.86/0.98

0.46/054

1.35/1.5

0.72/0.81

2.15/2.19

1.12/1.16

V/ns

Output pad dI/dt

3 tdit 25 pF

50 pF

65

70

157

167

373

396 mA/ns


4


4


4 trfi tpi

1.0 pF

1.0 pF

0.07/0.08

0.83/0.99

0.10/0.12

1.23/1.49

0.17/0.20

1.79/2.04

ns ns tpi 1.0 pF 1.65/1.81

2.05/2.31

2.60/2.84

ns

3

4

1

2

Maximum condition for tpr, tpo, tpi, and tpv: wcs model, 1.1 V, I/O 1. V, and 105 °C. Minimum condition for tpr, tpo, and tpv: bcs model, 1.3 V, I/O 1.9 V and –40 °C. Input transition time from core is 1 ns (20%–80%).





Table 30 shows AC parameters for DDR2 pbijtov18_33_ddr_clk I/O.

Table 30. AC Parameters for DDR2 pbijtov18_33_ddr_clk I/O

Parameter

Duty cycle

Clock frequency


1


1

, 50%–50% input signals and crossing of output signals

Symbol

Fduty f tpr tpo

Load

Condition

—

—

25 pF

50 pF

25 pF

50 pF

Min.

Rise/Fall

Typ.

40

—

0.53/0.52

1.01/0.98

1.3/1.21

1.59/1.5

50

—

0.80/0.72

1.49/1.34

1.97/1.84

2.37/2.24

Max.

Rise/Fall

60

133

1.19/1.04

2.21/1.90

2.91/2.71

3.48/3.28

Units

%

MHz ns ns



Table 30. AC Parameters for DDR2 pbijtov18_33_ddr_clk I/O (continued)


Load

Condition

Min.

Rise/Fall

Typ.

Max.

Rise/Fall

Units


1

, 40%–60% input signals and crossing of output signals


1 tpo 25 pF

50 pF

1.47/1.38

1.75/1.67

2.13/2.00

2.54/2.40

3.072/2.87

3.65/3.45

ns tpv 25 pF

50 pF

1.32/1.28

1.66/1.65

2.11/2.00

2.61/2.50

3.31/3.12

4.06/3.81

ns


1 tpv 25 pF

50 pF

1.40/1.37

1.67/1.66

2.16/2.06

2.56/2.45

3.30/3.13

3.89/3.67

ns


2 tps 25 pF

50 pF

0.86/0.98

0.46/054

1.35/1.5

0.72/0.81

2.15/2.19

1.12/1.16

V/ns

Output pad dI/dt

3 tdit 25 pF

50 pF

72

77

172

183

400

422 mA/ns


4


4


4 trfi tpi

1.0 pF

1.0 pF

0.07/0.08

0.89/0.87

0.10/0.12

1.41/1.37

0.17/0.20

2.16/2.07

ns ns tpi 1.0 pF 1.71/1.69

2.22/2.18

2.98/2.88

ns

3

4

1

2

Maximum condition for tpr, tpo, tpi, and tpv: wcs model, 1.1 V, I/O 1. V, and 105 °C. Minimum condition for tpr, tpo, and tpv: bcs model, 1.3 V, I/O 1.9 V and –40 °C. Input transition time from core is 1 ns (20%–80%).





Table 31

shows the AC requirements for DDR2 I/O.

Table 31. AC Requirements for DDR2 I/O

Parameter

1

Symbol Min.

Max.

Units

AC input logic high VIH(ac) OVDD/2 + 0.25

OVDD + 0.3

V

AC input logic low

AC differential input voltage

2

VIL(ac)

Vid(ac)

–0.3

0.5

OVDD/2 – 0.25

OVDD + 0.6

V

V

AC differential cross point voltage for input

3

AC differential cross point voltage for output

4

Vix(ac) OVDD/2–0.175

OVDD/2 + 0.175

V

Vox(ac) OVDD/2–0.125

OVDD/2 + 0.125

V

1

2

3

4

The Jedec SSTL_18 specification (JESD8-15a) for an SSTL interface for class II operation supersedes any specification in this document.

Vid(ac) specifies the input differential voltage |Vtr–Vcp| required for switching, where Vtr is the “true” input signal and Vcp is the “complementary” input signal. The minimum value is equal to Vih(ac)–Vil(ac)

The typical value of Vix(ac) is expected to be about 0.5

× OVDD. and Vix(ac) is expected to track variation of OVDD. Vix(ac) indicates the voltage at which differential input signal must cross.

The typical value of Vox(ac) is expected to be about 0.5

× OVDD and Vox(ac) is expected to track variation in OVDD. Vox(ac) indicates the voltage at which differential output signal must cross. Cload = 25 pF.

40



3.7

Module Timing and Electrical Parameters

This section contains the timing and electrical parameters for i.MX25 modules.

3.7.1

1-Wire Timing Parameters

Figure 7

shows the reset and presence pulses (RPP) timing for 1-Wire.

1-Wire bus

(OWIRE_LINE)

1-Wire Tx

“Reset Pulse”

1-Wire Memory Device

“Presence Pulse”

OW2

OW1

OW3

OW4

Figure 7. 1-Wire RPP Timing Diagram

Table 32

lists the RPP timing parameters.

Table 32. RPP Sequence Delay Comparisons Timing Parameters

ID

OW1

OW2

OW3

OW4

Parameters

Reset Time Low

Presence Detect High

Presence Detect Low

Reset Time High

Symbol

t

RSTL t

PDH t

PDL t

RSTH

Min.

480

15

60

480

Typ.

511

—

—

512

Max.

—

60

240

—

Units

μs

μs

μs

μs

Figure 8

shows write 0 sequence timing, and

Table 33

describes the timing parameters (OW5–OW6) that are shown in the figure.

OW6

1-Wire bus

(OWIRE_LINE)

OW5

Figure 8. Write 0 Sequence Timing Diagram

Table 33. WR0 Sequence Timing Parameters

ID Parameter

OW5 Write 0 Low Time

OW6 Transmission Time Slot

Symbol

t

WR0_low t

SLOT

Min.

60

OW5

Typ.

100

117

Max.

120

120

Units

μs

μs



Figure 9

and

Figure 10

show write 1 and read sequence timing, respectively.

Table 34 describes the timing

parameters (OW7–OW8) that are shown in the figure.

OW8

1-Wire bus

(OWIRE_LINE)

OW7

Figure 9. Write 1 Sequence Timing Diagram

OW8

1-Wire bus

(OWIRE_LINE)

ID

OW7

OW8

OW9

OW7

OW9

Figure 10. Read Sequence Timing Diagram

Parameter

Write 1 / read low time

Transmission time slot

Release time

Table 34. WR1 /RD Timing Parameters

Symbol

t

LOW1 t

SLOT t

RELEASE

Min.

1

60

15

Typ.

5

117

—

Max.

15

120

45

Units

μs

μs

μs

42



3.7.2

ATA Timing Parameters

Table 35

shows parameters used to specify the ATA timing. These parameters depend on the implementation of the ATA interface on silicon, the bus buffer used, the cable delay and cable skew.

Table 35. Timing Parameters

Name

T ti_ds ti_dh tco tsu tsui thi tskew1 tskew2 tskew3 tbuf tcable1 tcable2 tskew4 tskew5 tskew6

Description

Bus clock period

Set-up time ata_data to ata_iordy edge (UDMA-in only)

UDMA0

UDMA1

UDMA2,UDMA3

UDMA4

UDMA5

Hold time ata_iordy edge to ata_data (UDMA-in only)

UDMA0,UDMA1,UDMA2,UDMA3,UDMA4

UDMA5

Propagation delay bus clock L-to-H to ata_cs0, ata_cs1, ata_da2, ata_da1, ata_da0, ata_dior, ata_diow, ata_dmack, ata_data, ata_buffer_en

Set-up time ata_data to bus clock L-to-H

Set-up time ata_iordy to bus clock H-to-L

Hold time ata_iordy to bus clock H-to-L

Maximum difference in propagation delay bus clock L-to-H to any of the following signals

ata_cs0, ata_cs1, ata_da2, ata_da1, ata_da0, ata_dior, ata_diow,

ata_dmack, ata_data (write), ata_buffer_en

Maximum difference in buffer propagation delay for any of the following signals

ata_cs0, ata_cs1, ata_da2, ata_da1, ata_da0, ata_dior, ata_diow,

ata_dmack, ata_data (write), ata_buffer_en

Maximum difference in buffer propagation delay for any of the following signals

ata_iordy, ata_data (read)

Maximum buffer propagation delay cable propagation delay for ata_data cable propagation delay for control signals ata_dior, ata_diow, ata_iordy,

ata_dmack

Maximum difference in cable propagation delay between ata_iordy and

ata_data (read)

Maximum difference in cable propagation delay between (ata_dior, ata_diow,

ata_dmack) and ata_cs0, ata_cs1, ata_da2, ata_da1, ata_da0,

ata_data(write)

Maximum difference in cable propagation delay without accounting for ground bounce

Value/Contributing Factor

Peripheral clock frequency

15 ns

10 ns

7 ns

5 ns

4 ns

5.0 ns

4.6 ns

12.0 ns

8.5 ns

8.5 ns

2.5 ns

7 ns

Transceiver

Transceiver

Transceiver

Cable

Cable

Cable

Cable

Cable



3.7.2.1

PIO Mode Timing Parameters

Figure 11 shows a timing diagram for PIO read mode.

t1 t2r t9

ADDR

(See note 1) t5

DIOR

READ Data(15:0)

IORDY

IORDY tA t6 trd1

Figure 11. PIO Read Mode Timing

To meet PIO read mode timing requirements, a number of timing parameters must be controlled. Table 36

shows timing parameters and their determining relations, and indicates parameters that can be adjusted to meet required conditions.

Table 36. Timing Parameters for PIO Read Mode

ATA

Parameter

PIO Read

Mode Timing

Parameter

1

t5 t6 tA trd t1 t2 t9 t1 t2r t9 t5 t6 tA trd1 t0

1

See

Figure 11 .

—

Relation Adjustable Parameter

t1(min.) = time_1

× T – (tskew1 + tskew2 + tskew5) t2(min.) = time_2r

× T – (tskew1 + tskew2 + tskew5) t9(min.) = time_9

× T – (tskew1 + tskew2 + tskew6) t5(min.) = tco + tsu + tbuf + tbuf + tcable1 + tcable2

time_1 time_2r time_9

0 tA(min.) = (1.5 + time_ax)

× T – (tco + tsui + tcable2 + tcable2 + 2 × tbuf) trd1(max.) = (–trd) + (tskew3 + tskew4) trd1(min.) = (time_pio_rdx – 0.5)

× T – (tsu + thi)

(time_pio_rdx – 0.5)

× T > tsu + thi + tskew3 + tskew4 t0(min.) = (time_1 + time_2 + time_9)

× T

If not met, increase time_2

— time_ax time_pio_rdx time_1, time_2r, time_9

44



Figure 12

gives timing waveforms for PIO write mode.

t1 t2w t9

ADDR

(See note 1)

DIOR

DIOW buffer_en

Write Data(15:0) ton tA tB t4 toff t1

IORDY

IORDY

Figure 12. PIO Write Mode Timing

To meet PIO write mode timing requirements, a number of timing parameters must be controlled. Table 37

shows timing parameters and their determining relations, and indicates parameters that can be adjusted to meet required conditions.

Table 37. Timing Parameters for PIO Write Mode

ATA

Parameter

PIO Write

Mode Timing

Parameter

1

t3 t4 tA t0

— t1 t2 t9

— t4 tA

—

— t1 t2w t9

— —

Relation Adjustable Parameter(s)

t1(min.) = time_1

× T – (tskew1 + tskew2 + tskew5) t2(min.) = time_2w

× T – (tskew1 + tskew2 + tskew5) t9(min.) = time_9

× T – (tskew1 + tskew2 + tskew6)

time_1 time_2w time_9 t3(min.) = (time_2w – time_on)

× T – (tskew1 + tskew2 +tskew5) if not met, increase time_2w t4(min.) = time_4

× T – tskew1 time_4 tA = (1.5 + time_ax)

× T – (tco + tsui + tcable2 + tcable2 + 2 × tbuf) t0(min.) = (time_1 + time_2 + time_9)

× T time_ax time_1, time_2r, time_9

Avoid bus contention when switching buffer on by making ton long enough

—

Avoid bus contention when switching buffer off by making toff long enough

—

1

See

Figure 12 .



3.7.2.2

Multiword DMA (MDMA) Mode Timing

Figure 13 and Figure 14 show the timing for MDMA read and write modes, respectively.

tk1

DMARQ

ADDR

(See note 1)

DMACK

DIOR tm td tk

READ Data(15:0) te tgr tfr

Figure 13. MDMA Read Mode Timing

tkjn tk1

DMARQ

ADDR

(See note 1)

DMACK buffer_en

DIOW tm ton td1 tk td

Write Data(15:0)

Figure 14. MDMA Write Mode Timing

tkjn toff

46



To meet timing requirements, a number of timing parameters must be controlled. See Table 38

for details on timing parameters for MDMA read and write modes.

Table 38. Timing Parameters for MDMA Read and Write Modes

ATA

Parameter

MDMA Read

1 and Write

2

Timing

Parameters

Relation

tm, ti td tk t0 tg(read) tm td, td1 tk

— tgr tm(min.) = ti(min.) = time_m

× T – (tskew1 + tskew2 + tskew5) td1(min.) = td(min.) = time_d

× T – (tskew1 + tskew2 + tskew6) tk(min.) = time_k

× T – (tskew1 + tskew2 + tskew6) t0(min.) = (time_d + time_k)

× T tgr(min.–read) = tco + tsu + tbuf + tbuf + tcable1 + tcable2 tgr(min.–drive) = td – te(drive) tf(read) tfr tfr(min.–drive) =0 k tg(write) tf(write) tL tn, tj

—

—

—

— tkjn ton toff tg(min.–write) = time_d

× T –(tskew1 + tskew2 + tskew5) tf(min.–write) = time_k

× T – (tskew1 + tskew2 + tskew6) tL(max.) = (time_d + time_k–2)

× T – (tsu + tco + 2 × tbuf + 2 × tcable2) tn= tj= tkjn = (max.(time_k,. time_jn)

× T – (tskew1 + tskew2 + tskew6) ton = time_on

× T – tskew1 toff = time_off

× T – tskew1

2

3

1

See

Figure 13 .

See

Figure 14 .

tk1 in the UDMA figures equals (tk –2

× T).

Adjustable

Parameter(s)

time_m time_d time_k time_d, time_k time_d

— time_d time_k time_d, time_k

3 time_jn

—

3.7.2.3

Ultra DMA (UDMA) Mode Timing

UDMA mode timing is more complicated than PIO mode or MDMA mode. In this section, timing diagrams for UDMA in- and out-transfers are provided.



3.7.2.3.1

UDMA In-Transfer Timing

Figure 15

shows the timing for UDMA in-transfer start.

tack

ADDR

DMARQ

DMACK tenv

DIOR

DIOW tc1 tc1

IORDY

DATA READ tds tdh

Figure 15. Timing for UDMA In-Transfer Start

Figure 16

shows the timing for host-terminated UDMA in-transfer.

ADDR

DMARQ

DMACK

DIOR

DIOW trp tack tc1 tc1 tx1 tmli

IORDY

DATA READ tds tdh tmli tzah tzah ton tdzfs tcvh toff

DATA WRITE buffer_en

Figure 16. Timing for Host-Terminated UDMA In-Transfer

48



Figure 17

shows timing for device-terminated UDMA in-transfer.

ADDR

DMARQ

DMACK

DIOR

DIOW tack tmli tc1 tc1 tss1 tli5

IORDY

DATA READ tds tdh tmli tzah tzah ton tdzfs tcvh toff

DATA WRITE buffer_en

Figure 17. Timing for Device-Terminated UDMA Transfer

Timing parameters for UDMA in-burst are listed in

Table 39

.

Table 39. Timing Parameters for UDMA In-Burst

ATA

Parameter

Spec.

Parameter

Value Required Conditions

tack tenv tds tdh tack tenv tds1 tdh1 tack(min.) = (time_ack

× T) – (tskew1 + tskew2) tenv(min.) = (time_env

× T) – (tskew1 + tskew2) tenv(max.) = (time_env

× T) + (tskew1 + tskew2) tds – (tskew3) – ti_ds > 0 tdh – (tskew3) –ti_dh > 0 time_ack time_env tskew3, ti_ds, ti_dh should be low enough tcyc tc1 (tcyc – tskew) > T T big enough trp

— tmli tzah tdzfs trp tx1

1 tmli1 tzah tdzfs trp(min.) = time_rp

× T – (tskew1 + tskew2 + tskew6)

(time_rp

× T) – (tco + tsu + 3T + 2 × tbuf + 2 × tcable2) > trfs (drive) tmli1(min.) = (time_mlix + 0.4)

× T tzah(min.) = (time_zah + 0.4)

× T tdzfs = (time_dzfs

× T) – (tskew1 + tskew2) time_rp time_rp time_mlix time_zah time_dzfs tcvh

— tcvh ton toff tcvh = (time_cvh

× T) – (tskew1 + tskew2) ton = time_on


× T – tskew1 time_cvh

—

1

There is a special timing requirement in the ATA host that requires the internal DIOW to go only high three clocks after the last active edge on the DSTROBE signal. The equation given on this line tries to capture this constraint.

Make t on

and t off

big enough to avoid bus contention.



3.7.2.4

UDMA Out-Transfer Timing

Figure 18

shows the timing for start of UDMA out-transfer.

tack

ADDR

DMARQ

DMACK tenv

DIOW

DIOR buffer_en tcyc tcyc ton tdzfs tdvs tdvh tdvs

DATA WRITE

IORDY tli1 trfs1

Figure 18. Timing for UDMA Out-Transfer Start

Figure 19

shows timing for host-terminated UDMA out-transfer.

ADDR

DMARQ

DMACK

DIOW

DIOR tss tack tcyc tli2 tcyc1 tdzfs_mli tcvh toff

DATA WRITE

IORDY buffer_en tli3

Figure 19. Timing for Host-Terminated UDMA Out-Transfer

50



ATA

Parameter

tack tenv tdvs tdvh tcyc t2cyc trfs1

— tss tmli tli tli tli tcvh

—

Timing parameters for UDMA out-bursts are listed in

Table 40

.

Table 40. Timing Parameters UDMA Out-Bursts

Spec

Parameter

Value

tack tenv tdvs tdvh tcyc

— tack(min.) = (time_ack

× T) – (tskew1 + tskew2) tenv(min.) = (time_env

× T) – (tskew1 + tskew2) tenv(max.) = (time_env

× T) + (tskew1 + tskew2) tdvs = (time_dvs

× T) – (tskew1 + tskew2) tdvs = (time_dvh

× T) – (tskew1 + tskew2) tcyc = time_cyc

× T – (tskew1 + tskew2) t2cyc = time_cyc

× 2 × T trfs tdzfs trfs = 1.6

× T + tsui + tco + tbuf + tbuf tdzfs = time_dzfs

× T – (tskew1) tss tss = time_ss

× T – (tskew1 + tskew2) tdzfs_mli tdzfs_mli =max.(time_dzfs, time_mli)

× T – (tskew1 + tskew2) tli1 tli1 > 0 tli2 tli2 > 0 tli3 tcvh ton toff tli3 > 0 tcvh = (time_cvh

× T) – (tskew1 + tskew2) ton = time_on


× T – tskew1

3.7.3

Digital Audio Mux (AUDMUX) Timing

The AUDMUX provides a programmable interconnect logic for voice, audio, and data routing between internal serial interfaces (SSI and SAP) and external serial interfaces (audio and voice codecs). The AC timing of AUDMUX external pins is governed by the SSI modules. For more information, see

Section 3.7.17, “Synchronous Serial Interface (SSI) Timing

.”

3.7.4

CMOS Sensor Interface (CSI) Timing

The CSI enables the chip to connect directly to external CMOS image sensors, which are classified as dumb or smart as follows:

• Dumb sensors only support traditional sensor timing (vertical sync (VSYNC) and horizontal sync

(HSYNC)) and output-only Bayer and statistics data.

• Smart sensors support CCIR656 video decoder formats and perform additional processing of the image (for example, image compression, image pre-filtering, and various data output formats).

The following subsections describe the CSI timing in gated and ungated clock modes.

How to Meet?

time_ack time_env time_dvs time_dvh time_cyc time_cyc

— time_dzfs time_ss

—

—

—

— time_cvh

—



3.7.4.1

Gated Clock Mode Timing

Figure 20 and Figure 21 shows the gated clock mode timings for CSI, and

Table 41

describes the timing parameters (P1–P7) shown in the figures. A frame starts with a rising/falling edge on VSYNC, then

HSYNC is asserted and holds for the entire line. The pixel clock is valid as long as HSYNC is asserted.

VSYNC

P1

HSYNC

P2

P5

P7

P6

PIXCLK

P3

P4

DATA[15:0]

Figure 20. CSI Gated Clock Mode—Sensor Data at Falling Edge, Latch Data at Rising Edge

VSYNC

P1

HSYNC

P2

P6

P7

P5

PIXCLK

P3

P4

DATA[15:0]

Figure 21. CSI Gated Clock Mode—Sensor Data at Rising Edge, Latch Data at Falling Edge

52



ID

P5

P6

P7

P1

P2

P3

P4

Table 41. CSI Gated Clock Mode Timing Parameters

Parameter

CSI VSYNC to HSYNC time

CSI HSYNC setup time

CSI DATA setup time

CSI DATA hold time

CSI pixel clock high time

CSI pixel clock low time

CSI pixel clock frequency

Symbol

tV2H tHsu tDsu tDh tCLKh tCLKl fCLK

Min.

67.5

1

1

1.2

10

10

—

Max.

—

—

—

—

—

—

48

±

10%

3.7.4.2

Ungated Clock Mode Timing

Figure 22

shows the ungated clock mode timings of CSI, and

Table 42 describes the timing parameters

(P1–P6) that are shown in the figure. In ungated mode the VSYNC and PIXCLK signals are used, and the

HSYNC signal is ignored.

VSYNC

P1

P4

P6

P5

PIXCLK

P2

P3

Units

ns ns ns ns ns ns

MHz

DATA[15:0]

ID

P4

P5

P6

P1

P2

P3

Figure 22. CSI Ungated Clock Mode—Sensor Data at Falling Edge, Latch Data at Rising Edge

Table 42. CSI Ungated Clock Mode Timing Parameters

Parameter

CSI VSYNC to pixel clock time

CSI DATA setup time

CSI DATA hold time

CSI pixel clock high time

CSI pixel clock low time

CSI pixel clock frequency

Symbol

tVSYNC tDsu tDh tCLKh tCLKl fCLK

Min.

67.5

1

1.2

10

10

—

Max.

—

—

—

—

—

48

±

10%

Units

ns ns ns ns ns

MHz



3.7.5

Configurable Serial Peripheral Interface (CSPI) Timing

Figure 23 and Figure 24

provide CSPI master and slave mode timing diagrams, respectively. Table 43

describes the timing parameters (t1–t14) that are shown in the figures. The values shown in timing diagrams were tested using a worst-case core voltage of 1.1 V, slow pad voltage of 2.68 V, and fast pad voltage of 1.65 V.

t7 t5

SSn

(output) t8 t9 t6

RDY

(input) t1 t2 t3

SCLK

(output) t10 t11 t4 t4

MOSI t12 t13

MISO

Figure 23. CSPI Master Mode Timing Diagram

t7’ t5’

SS n

(input) t6’ t1’ t2’ t3’

SCLK

(input)

MISO t10 t11 t4 t4 t14 t12 t13 t14

MOSI

Figure 24. CSPI Slave Mode Timing Diagram

54



Table 43. CSPI Interface Timing Parameters

ID

t2’ t3’ t4 t5 t1 t2 t3 t1’ t5’ t6 t6’ t7 t7’ t8 t9 t10 t11 t12 t13

Parameter Description

CSPI master SCLK cycle time

CSPI master SCLK high time

CSPI master SCLK low time

CSPI slave SCLK cycle time

CSPI slave SCLK high time

CSPI slave SCLK low time

CSPI SCLK transition time

SS n output pulse width

SS n input pulse width

SS n output asserted to first SCLK edge (SS output setup time)

SS n input asserted to first SCLK edge (SS input setup time)

CSPI master: Last SCLK edge to SS n negated (SS output hold time)

CSPI slave: Last SCLK edge to SS n negated (SS input hold time)

CSPI master: CSPI1_RDY low to SS n asserted

(CSPI1_RDY setup time)

CSPI master: SS n negated to CSPI1_RDY low

Output data setup time

Symbol

t clko t clkoH t clkoL t clki t clkiH t clkiL t pr

1 t

Wsso t

Wssi t

Ssso t t t t t t

Sssi

Hsso

Hssi

Srdy

Hrdy

Sdatao

Output data hold time

Input data setup time

Input data hold time t14 Pause between data word

1

2

4

5

3

The output SCLK transition time is tested with 25 pF drive.

T sclk

= CSPI clock period

T wait

= Wait time, as specified in the sample period control register

T per

= CSPI reference baud rate clock period (PERCLK2)

T ipg

= CSPI main clock IPG_CLOCK period t t t t

Hdatao

Sdatai

Hdatai pause

Minimum

60.2

22.65

22.47

60.2

30.1

30.1

2.6

2T sclk

2

+T

wait

3

T per

4

3T sclk

T

2T

30

2T per sclk per

0

(t t clkoL

or t clkoH

or clkiL

or t

T clkiH ipg

5

) – t clkoL

or t clkoH

or t clkiL

or t clkiH

T ipg

+ 0.5

0

0

Maximum

—

—

8.5

—

—

—

—

—

—

—

—

—

—

5T per

—

—

—

—

—

—

Units

ns ns ns

— ns ns ns ns

—

—

—

— ns

— ns

—

— ns ns ns

3.7.6

External Memory Interface (EMI) Timing

The EMI module includes the enhanced SDRAM/LPDDR memory controller (ESDCTL), NAND Flash controller (NFC), and wireless external interface module (WEIM). The following subsections give timing information for these submodules.



3.7.6.1

ESDCTL Electrical Specifications

3.7.6.1.1

SDRAM Memory Controller

The following diagrams and tables specify the timings related to the SDRAMC module which interfaces

SDRAM.

SD1

SDCLK

SDCLK

SD4

SD2

SD3

CS

SD5

RAS

SD4

SD5

SD4

CAS

SD4

SD5

SD5

WE

ADDR

SD6

ROW/BA

SD7

COL/BA

SD10

DQ

SD8

SD9

Data

56

ID

SD1

SD2

SD3

SD4

SD5

SD4

DQM

Note: CKE is high during the read/write cycle.

SD5

Figure 25. SDRAM Read Cycle Timing Diagram

Table 44. DDR/SDR SDRAM Read Cycle Timing Parameters

Parameter

SDRAM clock high-level width

1

SDRAM clock low-level width

1

SDRAM clock cycle time

CS, RAS, CAS, WE, DQM, CKE setup time

CS, RAS, CAS, WE, DQM, CKE hold time

Symbol

tCH tCL tCK tCMS tCMH

Min.

3.4

3.4

7.5

2.0

1.8

Max.

4.1

4.1

—

—

—

Unit

ns ns ns ns ns



Table 44. DDR/SDR SDRAM Read Cycle Timing Parameters (continued)

ID Parameter Symbol Min.

Max.

Unit

SD6

SD7

Address setup time

Address hold time tAS tAH

2.0

1.8

—

— ns ns

SD8

SD9

SDRAM access time

Data out hold time

2 tAC tOH

—

1.2

6.47

— ns ns

SD10 Active to read/write command period tRC 10 — clock

1

2

SD1 + SD2 does not exceed 7.5 ns for 133 MHz.

Timing parameters are relevant only to SDR SDRAM. For the specific DDR SDRAM data related timing parameters, see

Table 48 and

Table 49

.

SD1

SDCLK

SDCLK

SD3

SD2

SD4

CS

SD5

RAS

SD11

SD4

CAS

SD5

SD4 SD4

WE

SD5

SD5

SD7

SD12

ADDR

SD6

BA

ROW / BA

COL/BA

SD13

SD14

DQ

DATA

DQM

Figure 26. SDR SDRAM Write Cycle Timing Diagram i.MX25 Applications Processor for Consumer and Industrial Products, Rev. 10


Table 45. SDR SDRAM Write Timing Parameters

ID Parameter

SD1

SD2

SD3

SD4




CS, RAS, CAS, WE, DQM, CKE setup time

SD5

SD6

SD7

SD11

SD12

SD13

CS, RAS, CAS, WE, DQM, CKE hold time

Address setup time

Address hold time

Precharge cycle period

1

Active to read/write command delay

1

Data setup time

SD14 Data hold time

1

SD11 and SD12 are determined by SDRAM controller register settings.

Symbol

tCH tCL tCK tCMS tCMH tAS tAH tRP tRCD tDS tDH

Min.

1.8

2.0

1.8

1

3.4

3.4

7.5

2.0

1

2.0

1.3

SD1

SDCLK

SDCLK

SD3

SD2

CS

Max.

—

—

—

4

4.1

4.1

—

—

8

—

—

Unit

ns ns ns clock ns ns ns ns clock ns ns

RAS

SD11

CAS

SD10

WE

ADDR

SD6

BA

SD7

Figure 27. SDRAM Refresh Timing Diagram

SD10

ROW/BA

58



Table 46. SDRAM Refresh Timing Parameters

ID Parameter Symbol

SD1

SD2

SD3

SD6


SDRAM clock low-level width tCL


Address setup time tCH tCK tAS

SD7

SD10

SD11

Address hold time

Precharge cycle period

1

Auto precharge command period

1

1

SD10 and SD11 are determined by SDRAM controller register settings.

tAH tRP tRC

Min.

3.4

3.4

7.5

1.8

1.8

1

2

Max.

—

4

20

4.1

4.1

—

—

Unit

ns ns ns ns ns clock clock

SDCLK

CS

RAS

CAS

WE

ADDR

CKE

BA

SD16

SD16

Don’t care

Figure 28. SDRAM Self-Refresh Cycle Timing Diagram

NOTE

The clock continues to run unless CKE is low. Then the clock is stopped in low state.



ID

SD16

Table 47. SDRAM Self-Refresh Cycle Timing Parameters

Parameter

CKE output delay time

Symbol

tCKS

Min.

1.8

Max.

—

Unit

ns

3.7.6.1.2

Mobile DDR SDRAM–Specific Parameters

The following diagrams and tables specify the timings related to the SDRAMC module which interfaces with the mobile DDR SDRAM.

SDCLK

SDCLK

DQS (output)

DQ (output)

SD19 SD20

SD17

Data

SD18

Data

SD17

Data Data

SD18

Data Data Data Data

DQM (output)

DM

DM

DM

SD17

DM DM DM

SD17

SD18

SD18

Figure 29. Mobile DDR SDRAM Write Cycle Timing Diagram

Table 48. Mobile DDR SDRAM Write Cycle Timing Parameters

1


SD17 DQ and DQM setup time to DQS

SD18 DQ and DQM hold time to DQS tDS tDH

SD19 Write cycle DQS falling edge to SDCLK output delay time tDSS

SD20 Write cycle DQS falling edge to SDCLK output hold time tDSH

1

Test condition: Measured using delay line 5 programmed as follows: ESDCDLY5[15:0] = 0x0703.

DM

DM

Min.

Max.

Unit

0.95

0.95

1.8

1.8

—

—

—

— ns ns ns ns

60



SDCLK

SDCLK

SD23

DQS (input)

SD22

DQ (input)

SD21

Data Data

Data

Data

Data Data

Data

Data

Figure 30. Mobile DDR SDRAM DQ versus DQS and SDCLK Read Cycle Timing Diagram

Table 49. Mobile DDR SDRAM Read Cycle Timing Parameters

ID Parameter

SD21 DQS – DQ Skew (defines the data valid window in read cycles related to DQS)

SD22 DQS DQ HOLD time from DQS

SD23 DQS output access time from SDCLK posedge

Symbol Min. Max. Unit

tDQSQ tQH

—

2.3

0.85

— ns ns tDQSCK — 6.7

ns



3.7.6.1.3

DDR2 SDRAM–Specific Parameters

The following diagrams and tables specify timing related to the SDRAMC module, which interfaces with

DDR2 SDRAM.

DDR1

SDCLK

SDCLK

CS

RAS

DDR4

DDR4

DDR5

DDR3

DDR2

DDR5

DDR4

CAS

DDR4

DDR5

DDR5

WE

CKE

DDR6

ADDR

ROW/BA

DDR7

COL/BA

DDR4

Figure 31. DDR2 SDRAM Basic Timing Parameters

Table 50

provides values for a command/address slew rate of 1 V/ns and an SDCLK, SDCLK_B differential slew rate of 2 V/ns. For additional values, use

Table 51 , “tlS, tlH Derating Values for

DDR2-400, DDR2-533.”

Table 50. DDR2 SDRAM Timing Parameter Table

DDR2-400


DDR1

DDR2

DDR3



SDRAM clock cycle time t

CH t

CL t

CK

Min.

0.45

0.45

7.5

Max.

0.55

0.55

8

Unit

t

CK t

CK ns

62



ID

DDR4

DDR5

DDR6

DDR7

Table 50. DDR2 SDRAM Timing Parameter Table (continued)

DDR2-400


CS, RAS, CAS, CKE, WE setup time

CS, RAS, CAS, CKE, WE hold time

Address output setup time

Address output hold time t

IS t

IH t

IS t

IH

Min.

1.2

1.2

1.2

0.475

Max.

—

—

—

—

Unit

ns ns ns ns

0.4

0.3

0.25

0.2

0.8

0.7

0.6

0.5

0.15

0.1

2.0

1.5

1.0

0.9

4.0

3.5

3.0

2.5

Table 50

shows values for a command/address slew rate of 1 V/ns and an SDCLK, SDCLK_B differential slew rate of 2 V/ns.

Table 51 shows additional values for DDR2-400 and DDR2-533.

Table 51. tlS, tlH Derating Values for DDR2-400, DDR2-533

Command/

Address

Slew Rate (V/Ns)

ΔtlS

–25

–43

–67

–110

–175

–285

–350

–525

–800

–1450

+187

+179

+167

+150

+125

+83

0

–11

2.0 V/ns

ΔtlH

–31

–54

–83

–125

–188

–292

–375

–500

–708

–1125

+45

+21

0

–14

+94

+89

+83

+75

CK, CK Differential Slew Rate

1.5 V/ns

ΔtlS

–145

–255

–320

–495

+5

–13

–37

–80

–770

–1420

+217

+209

+197

+180

+155

+113

+30

+19

ΔtlH

–158

–262

–345

–470

–1

–24

–53

–95

–678

–1095

+75

+51

+30

+16

+124

+119

+113

+105

ΔtlS

–115

–225

–290

–465

+35

+17

–7

–50

–740

–1390

+247

+239

+227

+210

+185

+143

+60

+49

1.0 V/ns

ΔtlH

–128

–232

–315

–440

+29

+6

–23

–65

–648

–1065

+154

+149

+143

+135

+105

+81

+60

+46

Units

ps ps ps ps ps ps ps ps ps ps ps ps ps ps ps ps ps ps



SDCLK

SDCLK_B

DQS (output)

DQ (output)

DDR21

DDR17

DDR22

DDR23

Data

DDR18

Data

DDR17

Data Data

DDR18

Data

DDR19

Data Data

DDR20

Data

DQM (output)

DM

DM

DM

DM DM DM

DDR17

DDR18

DDR17

DDR18

Figure 32. DDR2 SDRAM Write Cycle Timing Diagram

DM

DM

Table 52. DDR2 SDRAM Write Cycle Parameter Table

DDR2-400

ID Parameter Symbol Unit

Min.

Max.

DDR17 DQ & DQM setup time to DQS (single-ended strobe)

1

DDR18 DQ & DQM hold time to DQS (single-ended strobe)

1

DDR19 Write cycle DQS falling edge to SDCLK output setup time t

DS1(base) t

DH1(base) t

DSS

0.6

0.6

0.3

—

—

— ns ns tCK

DDR20

DDR21

Write cycle DQS falling edge to SDCLK output hold time

DQS latching rising transitions to associated clock edges t

DSH t

DQSS t

DQSH

0.3

-0.2

—

0.2

tCK tCK

DDR22 DQS high-level width 0.35

— tCK

DDR23 DQS low-level width t

DQSL

0.35

— tCK

1

These values are for a DQ/DM slew rate of 1 V/ns and a DQS slew rate of 1 V/ns. For additional values use

Table 53 , “DtDS1,

DtDH1 Derating Values for DDR2-400, DDR2-533.”

Table 53.

ΔtDS1, ΔtDH1 Derating Values for DDR2-400, DDR2-533

1,2,3

DQS Single-Ended Slew Rate

2.0 V/ns 1.5 V/ns 1.0 V/ns 0.9 V/ns 0.8 V/ns 0.7 V/ns 0.6 V/ns 0.5 Vns 0.4 V/ns

ΔtD

S1

ΔtD

H1

ΔtD

S1

ΔtD

H1

ΔtD

S1

ΔtD

H1

ΔtD

S1

ΔtD

H1

ΔtD

S1

ΔtD

H1

ΔtD

S1

ΔtD

H1

ΔtD

S1

ΔtD

H1

ΔtD

S1

ΔtD

H1

ΔtD

S1

ΔtD

H1

64



Table 53.

ΔtDS1, ΔtDH1 Derating Values for DDR2-400, DDR2-533

1,2,3

(continued)

DQS Single-Ended Slew Rate

2.0 188 188 167 146 125 63 — — — — — — — — — — — —

1.5 146 167 125 125 83 42 81 43 — — — — — — — — — —

1.0 63 125 42 83 0 0 –2 1 –7 –13 — — — — — — — —

0.9

— — 31 69 –11 –14 –13 –13 –18 –27 –29 –45 — — — — — —

DQ Slew Rate

V/ns

0.8

— — — — –25 –31 –27 –30 –32 –44 –43 –62 –60 –86 — — — —

0.7

— — — — — — –45 –53 –50 –67 –61 –85 –78 –109 –108 –152 — —

0.6

— — — — — — — — –74 –96 –85 –114 –102 –138 –132 –181 –183 –246

0.5

— — — — — — — — — — –128 –156 –145 –180 –175 –223 –226 –288

0.4

— — — — — — — — — — — — –210 –243 –240 –286 –291 –351

1

2

3

All units in ‘ps’.

Test conditions are at capacitance=15pF for DDR PADS. Recommended drive strengths are medium for SDCLK and high for address and controls.

SDRAM CLK and DQS related parameters are measured from the 50% point. That is, high is defined as 50% of the signal value, and low is defined as 50% of the signal value. DDR SDRAM CLK parameters are measured at the crossing point of

SDCLK and SDCLK (inverted clock).

SDCLK

SDCLK_B

DQS (input)

DDR26

DDR25

DDR24

DATA DATA DATA DATA DATA

DATA

DATA DATA

DQ (input)

Figure 33. DDR2 SDRAM DQ vs. DQS and SDCLK READ Cycle Timing Diagram

Table 54. DDR2 SDRAM Read Cycle Parameter Table

1,2


DDR2-400

Min.

Max.

Unit

DDR24 DQS - DQ Skew (defines the Data valid window in read cycles related to DQS)

DDR25 DQS DQ in HOLD time from DQS

3 t

DQSQ t

QH

—

2.5

0.6

— ns ns

DDR26 DQS output access time from SDCLK posedge t

DQSCK

–0.5

0.5

ns

1

Test conditions are at capacitance=15 pF for DDR PADS. Recommended drive strengths are medium for SDCLK and high for address and controls.



2

3

SDRAM CLK and DQS-related parameters are measured from the 50% point. That is, high is defined as 50% of the signal value, and low is defined as 50% of the signal value. DDR SDRAM CLK parameters are measured at the crossing point of

SDCLK and SDCLK (inverted clock).

The value was calculated for an SDCLK frequency of 133 MHz, by the formula tQH = tHP – tQHS = min. (tCL,tCH) – tQHS =

0.45*tCK – tQHS = 0.45 * 7.5 – 0.45 = 2.925 ns

3.7.6.2

NAND Flash Controller (NFC) Timing

The i.MX25 NFC supports normal timing mode, using two Flash clock cycles for one access of RE and

WE. AC timings are provided as multiplications of the clock cycle and fixed delay. Figure 34 through

Figure 37

depicts the relative timing between NFC signals at the module level for different operations under normal mode.

Table 55

describes the timing parameters (NF1–NF17) that are shown in the figures.

NFCLE

NF2

NF1

NF3

NF4

NFCE

NF5

NFWE

NF6 NF7

NFALE

NFIO[7:0]

NF8

NF9

Command

Figure 34. Command Latch Cycle Timing Diagram

NFCLE

NF1

NF3

NF4

NFCE

NF5

NF10

NF11

NFWE

NF6 NF7

NFALE

NFIO[7:0]

NF8

NF9

Address

Figure 35. Address Latch Cycle Timing Diagram

66



NFCLE

NF1

NF3

NFCE

NF5

NF10

NF11

NFWE

NF6

NF7

NFALE

NFIO[15:0]

NF8

NF9

Data to NF

Figure 36. Write Data Latch Cycle Timing Diagram

NFCLE

NFCE

NF14

NF13

NF15

NFRE

NF16 NF17

ID

NF1

NF2

NF3

NF4

NFRB

NF12

NFIO[15:0]

Data from NF

Parameter

NFCLE setup time

NFCLE hold time

NFCE setup time

NFCE hold time

Figure 37. Read Data Latch Cycle Timing Diagram

Table 55. NFC Timing Parameters

1

Symbol

tCLS tCLH tCS tCH

Timing

T = NFC Clock Cycle

Min.

T–1.0 ns

T–2.0 ns

2T–5.0 ns

7T–5.0 ns

Max.

—

—

—

—

Example Timing for

NFC Clock

≈

33 MHz

T = 30 ns

Min.

29

28

55

205

Max.

—

—

—

—

Unit

ns ns ns ns



ID Parameter

Table 55. NFC Timing Parameters

1

(continued)

Symbol

NF5

NF6

NF7

NF8

NF_WP pulse width

NFALE setup time

NFALE hold time

Data setup time

NF9 Data hold time

NF10 Write cycle time

NF11 NFWE hold time

NF12 Ready to NFRE low

NF13 NFRE pulse width

NF14 READ cycle time

NF15 NFRE high hold time

NF16 Data setup on read tRP tRC tREH tDSR

NF17 Data hold on read tDHR

1

The Flash clock maximum frequency is 50 MHz.

tWP tALS tALH tDS tDH tWC tWH tRR

Timing

T = NFC Clock Cycle

Min.

Max.

T

T–3.0 ns

T–1.5 ns

2T ns

T–5.0 ns

2T

T–2.5 ns

21T–10 ns

1.5T

2T

0.5T–2.5 ns

N/A

N/A

—

—

—

—

—

—

—

620

45

60

12.5

10

0

Example Timing for

NFC Clock

≈

33 MHz

T = 30 ns

Min.

Max.

28.5

30

27

60

25

—

—

—

—

60

27.5

—

—

—

—

—

—

NOTE

For timing purposes, transition to signal high is defined as 80% of signal value; while signal low is defined as 20% of signal value.

Timing for HCLK is 133 MHz. The internal NFC clock (Flash clock) is approximately 33 MHz (30 ns). All timings are listed according to this NFC clock frequency (multiples of NFC clock phases), except NF16 and NF17, which are not related to the NFC clock.

Unit

3.7.6.3

Wireless External Interface Module (WEIM) Timing

Figure 38 depicts the timing of the WEIM module, and Table 56

describes the timing parameters

(WE1–WE27) shown in the figure.

All WEIM output control signals may be asserted and negated by internal clock relative to BCLK rising edge or falling edge according to corresponding assertion/negation control fields. Address always begins relative to BCLK falling edge, but may be ended on rising or falling edge in muxed mode according to the control register configuration. Output data begins relative to BCLK rising edge except in muxed mode, where rising or falling edge may be used according to the control register configuration. Input data, ECB and DTACK are all captured relative to BCLK rising edge. ns ns ns ns ns ns ns ns ns ns ns ns ns

68



BCLK

Address

CS[x]

WE4

WE6

WE8

RW

OE

WE10

WE12

EB[y]

LBA WE14

WE16

Output Data

WEIM Output Timing

WE1

WE2 WE3

...

WE5

WE7

WE9

WE11

WE13

WE15

WE17

WEIM Input Timing

BCLK

WE18, WE19

Input Data

WE20, WE21

WE22, WE23

ECB

WE24, WE25

WE26

DTACK

WE27

Figure 38. WEIM Bus Timing Diagram

Table 56. WEIM Bus Timing Parameters

1

ID

WE1 BCLK cycle time

2

WE2 BCLK low-level width

2

WE3 BCLK high-level width

2

WE4 Clock fall to address valid

WE5 Clock rise/fall to address invalid

WE6 Clock rise/fall to CS[x] valid

WE7 Clock rise/fall to CS[x] invalid

Parameter Min.

14.5

7

7

15

22

15

3.3



Max.

21

25

19

5

—

—

—

Unit

ns ns ns ns ns ns ns

69

Table 56. WEIM Bus Timing Parameters

1

(continued)

ID Parameter Min.

Max.

Unit

WE8 Clock rise/fall to RW valid

WE9 Clock rise/fall to RW invalid

WE10 Clock rise/fall to OE valid

WE11 Clock rise/fall to OE invalid

WE12 Clock rise/fall to EB[y] valid

WE13 Clock rise/fall to EB[y] invalid

WE14 Clock rise/fall to LBA valid

WE15 Clock rise/fall to LBA invalid

6

6

17.5

0

8

3

7

3.6

11.5

10

20

1

12

8

12

5.5

WE16 Clock rise/fall to output data valid

WE17 Clock rise to output data invalid

5

0

WE18 Input data valid to clock rise, FCE=1

WE19 Input Data Valid to Clock rise, FCE=0 (in the case there is ECB asserted during access)

1

1/2 BCLK

+2.63

6.9

Input Data Valid to Clock rise, FCE=0 (in the case there is NO ECB asserted during access)

WE20 Clock rise to input data invalid, FCE=1 1

10

2.5

—

—

— ns ns ns ns ns

WE21 Clock rise to input data invalid, FCE=0

WE22 ECB setup time, FCE=1

WE23 ECB setup time, FCE=0

WE24 ECB hold time, FCE=1

2.4

5

7.2

5

—

—

—

—

—

WE25 ECB hold time, FCE=0

WE26 DTACK setup time

0

5.4

—

— ns ns

WE27 DTACK hold time –3.2

— ns

1

2

High is defined as 80% of signal value; low is defined as 20% of signal value.

BCLK parameters are being measured from the 50% point. For example, high is defined as 50% of signal value and low is defined as 50% as signal value.

ns ns ns ns ns ns ns ns ns ns ns ns ns

NOTE

The test condition load capacitance was 25 pF. Recommended drive strength for all controls, address, and BCLK is maximum drive.

Recommended drive strength for all controls, address and BCLK is maximum drive.

70



Figure 39

through Figure 44 give examples of basic WEIM accesses to external memory devices with the

timing parameters described in

Table 56

for specific control parameter settings.

BCLK

ADDR

CS[x]

Last Valid Address

WE4

WE6

V1

WE5

Next Address

WE7

RW

WE14

WE15

LBA

WE10 WE11

OE

WE12

WE13

EB[y]

DATA

WE21

V1

WE19

Figure 39. Synchronous Memory Timing Diagram for Read Access—WSC=1

BCLK

ADDR

CS[x]

Last Valid Address

WE4

WE6

V1

WE5

WE7

Next Address

WE8

WE9

RW

WE14

WE15

LBA

OE

WE12

WE13

EB[y]

DATA

WE17

V1

WE16

Figure 40. Synchronous Memory Timing Diagram for Write Access—

WSC=1, EBWA=1, EBWN=1, LBN=1 i.MX25 Applications Processor for Consumer and Industrial Products, Rev. 10


BCLK

WE4

ADDR

Last Valid Addr

WE6

CS[x]

Address V1

WE5

Address V2

WE7

RW

WE14 WE15

LBA

WE10

WE11

OE

EB[y]

WE12

WE13

WE24

WE24

ECB

DATA

WE22 WE22

WE19

V1

Halfword

V1+2

Halfword

WE19

V2

Halfword

V2+2

Halfword

WE18

WE18

Figure 41. Synchronous Memory Timing Diagram for Two Non-Sequential Read Accesses—

WSC=2, SYNC=1, DOL=0

72



BCLK

ADDR

WE4

Last Valid Addr

CS[x]

WE6

RW

WE8

WE14

LBA

WE15

Address V1

WE5

WE7

WE9

OE

EB[y]

WE12 WE13

WE24

ECB

WE22

WE17

WE17

V1+4 V1+8 V1+12

DATA

V1

WE16

WE16

Figure 42. Synchronous Memory TIming Diagram for Burst Write Access—

BCS=1, WSC=4, SYNC=1, DOL=0, PSR=1

BCLK

WE4

ADDR/

M_DATA

Last Valid Addr

CS[x]

WE6

RW

WE8

WE14

LBA

OE

EB[y]

WE12

Address V1

WE15

WE5

WE16

Write Data

Write

WE17

WE7

WE9

WE13

Figure 43. Muxed A/D Mode Timing Diagram for Synchronous Write Access—

WSC=7, LBA=1, LBN=1, LAH=1 i.MX25 Applications Processor for Consumer and Industrial Products, Rev. 10


BCLK

ADDR/

M_DATA

CS[x]

WE4

Last Valid Addr

WE6

RW

LBA

OE

EB[y]

WE12

Address V1

WE14

WE5

WE15

WE10

WE20

Read Data

WE18

WE7

WE11

WE13

Figure 44. Muxed A/D Mode Timing Diagram for Synchronous Read Access—

WSC=7, LBA=1, LBN=1, LAH=1, OEA=7

Figure 45

through Figure 49 , and Table 57

help to determine timing parameters relative to chip select (CS) state for asynchronous and DTACK WEIM accesses with corresponding WEIM bit fields and the timing parameters mentioned above.

CS [x]

ADDR

RW

LBA

OE

EB[y]

DATA

Last Valid Address

WE31

WE39

WE35

WE37

Address V1

WE32

WE40

WE36

WE38

V1

WE43

Figure 45. Asynchronous Memory Read Access

WE44

Next Address

74



CS[x]

ADDR/

M_DATA

WE

LBA

OE

EB[y]

WE31

Addr. V1

WE32A

MAXDI

D(V1)

WE44

WE40

WE39

WE35A

WE37

WE36

WE38

MAXCO

Figure 46. Asynchronous A/D Muxed Read Access (RWSC = 5)

CS[x]

ADDR

RW

LBA

OE

EB[y]

DATA

WE31

Last Valid Address

WE33

WE39

Address V1

WE32

WE34

WE40

WE45 WE46

WE42

D(V1)

WE41

Figure 47. Asynchronous Memory Write Access

Next Address



CS[x]

ADDR/

M_DATA

RW

LBA

OE

EB[y]

WE31

WE33

WE39

Addr. V1

WE32A

WE40A

WE41

D(V1)

WE34

WE42

WE45 WE46

WE42

Figure 48. Asynchronous A/D Mux Write Access

CS [x]

ADDR

Last Valid Address

WE31

Address V1

WE32

Next Address

RW

WE39 WE40

LBA

WE35

WE36

OE

WE37

WE38

EB[y]

WE44

DATA

V1

WE43

WE48

DATA

WE47

Figure 49. DTACK Read Access

Ref No.

Table 57. WEIM Asynchronous Timing Parameters Relative to Chip Select Table

Parameter

WE31 CS[x] valid to Address Valid

WE32 Address Invalid to CS[x] invalid

Determination By

Synchronous Measured

Parameters

1

WE4 – WE6 – CSA

2

WE7 – WE5 – CSN

3

Min

—

—

Max

(If 133 MHz is supported by SoC)

Unit

3 – CSA

3 – CSN ns ns

76



Table 57. WEIM Asynchronous Timing Parameters Relative to Chip Select Table (continued)

Ref No.

Parameter

Determination By

Synchronous Measured

Parameters

1

Min

Max

(If 133 MHz is supported by SoC)

Unit

WE32A( muxed

A/D

CS[x] valid to Address Invalid WE4 – WE7 + (LBN + LBA + 1

– CSA

2

)

–3 + (LBN + LBA +

1 – CSA)

WE33

WE34

CS[x] Valid to RW Valid

RW Invalid to CS[x] Invalid

WE8 – WE6 + (RWA – CSA)

WE7 – WE9 + (RWN – CSN)

—

—

WE35

WE35A

(muxed

A/D)

WE36

CS[x] Valid to OE Valid

CS[x] Valid to OE Valid

WE10 – WE6 + (OEA – CSA)

WE10 – WE6 + (OEA + LBN +

LBA + LAH + 1 – CSA)

OE Invalid to CS[x] Invalid WE7 – WE11 + (OEN – CSN)

WE37 CS[x] Valid to EB[y] Valid (Read access)

WE12 – WE6 + (EBRA – CSA)

—

–3 + (OEA + LBN

+ LBA + LAH + 1 –

CSA)

—

—

—

3 + (RWA – CSA)

3 – (RWN_CSN)

3 + (OEA – CSA)

3 + (OEA + LBN +

LBA + LAH + 1 –

CSA)

3 – (OEN – CSN)

3 + (EBRA

4

– CSA)

WE38 EB[y] Invalid to CS[x] Invalid

(Read access)

WE7 – WE13 + (EBRN – CSN)

WE39

WE40

—

—

3 – (EBRN

5

– CSN)

WE40A

(muxed

A/D)

CS[x] Valid to LBA Invalid

WE41 CS[x] Valid to Output Data Valid

WE14 – WE6 + (LBN + LBA + 1

– CSA)

–3 + (LBN + LBA +

1 – CSA)

3 + (LBN + LBA + 1 –

CSA)

WE16 – WE6 – CSA —

— WE41A

(muxed

A/D)

CS[x] Valid to Output Data Valid WE16 – WE6 + (LBN + LBA +

LAH + 1 – CSA)

3 – CSA

3 + (LBN + LBA +

LAH + 1 – CSA)

WE42

WE43

WE44

WE45

CS[x] Valid to LBA Valid

LBA Invalid to CS[x] Invalid

Output Data Invalid to CS[x]

Invalid

Input Data Valid to CS[x]

Invalid

CS[x] Invalid to Input Data invalid

CS[x] Valid to EB[y] Valid

(Write access)

WE14 – WE6 + (LBA – CSA)

WE7 – WE15 – CSN

WE17 – WE7 – CSN

MAXCO – MAXCSO + MAXDI

0

WE12 – WE6 + (EBWA – CSA)

—

—

MAXCO

MAXCSO

MAXDI

8

0

—

6 –

7

+

3 + (LBA – CSA)

3 – CSN

3 – CSN

—

—

3 + (EBWA – CSA)

WE46

WE47

EB[y] Invalid to CS[x] Invalid

(Write access)

WE7 – WE13 + (EBWN – CSN)

DTACK Valid to CS[x] Invalid MAXCO – MAXCSO + MAXDTI

— ns ns ns ns

–3 + (EBWN – CSN) ns

— ns ns ns ns ns ns ns

WE48 CS[x] Invalid to DTACK invalid 0

MAXCO

6

–

MAXCSO

7

+

MAXDTI

9

0 — ns ns ns ns ns ns ns ns



3

4

5

6

7

1

2

8

9

For the value of parameters WE4–WE21, see column BCD = 0 in

Table 56 .

CS Assertion. This bit field determines when the CS signal is asserted during read/write cycles.

CS Negation. This bit field determines when the CS signal is negated during read/write cycles.

BE Assertion. This bit field determines when the BE signal is asserted during read cycles.

BE Negation. This bit field determines when the BE signal is negated during read cycles.

Output maximum delay from internal driving ADDR/control FFs to chip outputs.

Output maximum delay from CS[x] internal driving FFs to CS[x] out.

DATA maximum delay from chip input data to its internal FF.

DTACK maximum delay from chip dtack input to its internal FF.

NOTE

All configuration parameters (CSA, CSN, EBWA, EBWN, LBA, LBN,

LAH, OEN, OEA, EBRA, and EBRN) are in cycle units.

78



3.7.7

Enhanced Serial Audio Interface (ESAI) Timing

This section describes general timing requirements for ESAI, as well as the ESAI transmit and receive timing.

Figure 50

shows the ESAI transmit timing diagram.

62

SCKT

(Input/Output)

63 64

78 79

FST (bit) out

82 83

FST (word) out

84

86 86

87 first bit last bit

Data out

93

Transmitter #0 drive enable

(internal signal) 89 85 88

91

FST (bit) in

92

90

91

FST (word) in

94

See Note

Flags out

Note:

In network mode, output flag transitions can occur at the start of each time slot within the frame. In normal mode, the output flag state is asserted for the entire frame period.

Figure 50. ESAI Transmit Timing i.MX25 Applications Processor for Consumer and Industrial Products, Rev. 10


Figure 51

shows the ESAI receive timing diagram.

62

63

64

SCKR

(input/output)

65 66

FSR (bit) out

69

FSR (word) out

72

71

Data in first bit last bit

73

75

FSR (bit) in

74 75

FSR (word) in

76

77

Flags in

Figure 51. ESAI Receive Timing Diagram

Figure 52

shows the ESAI HCKT timing diagram.

HCKT

SCKT (output)

95

96

Figure 52. ESAI HCKT Timing

70

80



Figure 53

shows the ESAI HCKR timing diagram.

HCKR

95

SCKR (output)

97

Figure 53. ESAI HCKR Timing

Table 60

describes the general timing requirements for the ESAI module.

Table 58 and Table 59 describe respectively the conditions and signals cited in Table 60

.

Table 58. ESAI Timing Conditions

Symbol

i ck x ck i ck a i ck s

Significance Comments

Internal clock In the i.MX25, the internal clock frequency is equal to the IP bus frequency

(133 MHz)

External clock The external clock may be derived from the CRM module or other external clock sources

Internal clock, asynchronous mode In asynchronous mode, SCKT and SCKR are different clocks

Internal clock, synchronous mode In synchronous mode, SCKT and SCKR are the same clock

SCKT

SCKR

FST

HCKT

HCKR

Signal Name

Table 59. ESAI Signals

Significance

Transmit clock

Receive clock

Transmit frame sync

Transmit high-frequency clock

Receive high-frequency clock

No.

62 Clock cycle

4

Characteristics

1 2

63 Clock high period

For internal clock

For external clock

64 Clock low period

For internal clock

For external clock

Table 60. ESAI General Timing Requirements

Symbol

t

SSICC

—

—

—

—

—

Expression

3

4

× T c

4

× T c

2

× T

— c

− 9.0

2

× T c

2

× T c

− 9.0

2

× T c

Min.

Max.

30.0

30.0

—

6

15

6

15

—

—

—

—

—

—

—

Condition

i ck i ck

—

—

—

—

Unit

ns ns ns



Table 60. ESAI General Timing Requirements (continued)

Characteristics

1 2

Symbol Expression

3

Min.

Max.

No.

65 SCKR rising edge to FSR out (bl) high — —

66 SCKR rising edge to FSR out (bl) low

67 SCKR rising edge to FSR out (wr) high

5

68 SCKR rising edge to FSR out (wr) low

5

69 SCKR rising edge to FSR out (wl) high

70 SCKR rising edge to FSR out (wl) low

71 Data in setup time before SCKR (SCK in synchronous mode) falling edge

72 Data in hold time after SCKR falling edge

73 FSR input (bl, wr) high before SCKR falling edge

5

74 FSR input (wl) high before SCKR falling edge

75 FSR input hold time after SCKR falling edge

76 Flags input setup before SCKR falling edge

77 Flags input hold time after SCKR falling edge

78 SCKT rising edge to FST out (bl) high

79 SCKT rising edge to FST out (bl) low

80 SCKT rising edge to FST out (wr) high

5

81 SCKT rising edge to FST out (wr) low

5

82 SCKT rising edge to FST out (wl) high

83 SCKT rising edge to FST out (wl) low

84 SCKT rising edge to data out enable from high impedance

85 SCKT rising edge to transmitter #0 drive enable assertion

—

—

—

—

—

—

—

—

—

—

—

—

—

—

—

—

—

—

—

—

—

—

—

—

—

—

—

—

—

—

—

—

—

—

—

—

—

—

—

—

—

—

—

—

6.0

0.0

—

—

2.0

12.0

2.0

12.0

2.5

8.5

0.0

19.0

—

—

—

—

—

—

—

—

—

—

12.0

19.0

3.5

9.0

—

—

—

—

—

—

—

—

—

—

—

—

—

—

18.0

8.0

20.0

10.0

20.0

10.0

—

—

—

—

—

—

—

—

22.0

12.0

19.0

9.0

20.0

10.0

22.0

17.0

17.0

11.0

—

—

—

—

16.0

6.0

17.0

7.0

17.0

7.0

17.0

7.0

19.0

9.0

19.0

9.0

ns ns ns ns ns ns ns ns ns ns ns ns

Unit

ns ns ns ns ns ns ns ns ns

Condition

x ck i ck s x ck i ck x ck i ck x ck i ck x ck i ck a x ck i ck a x ck i ck a x ck i ck s x ck i ck x ck i ck x ck i ck x ck i ck x ck i ck x ck i ck a x ck i ck a x ck i ck x ck i ck x ck i ck a x ck i ck a x ck i ck a x ck i ck a

82



Table 60. ESAI General Timing Requirements (continued)

Characteristics

1 2

Symbol Expression

3

Min.

Max.

No.

Condition Unit

86 SCKT rising edge to data out valid

87 SCKT rising edge to data out high impedance

6

88 SCKT rising edge to transmitter #0 drive enable negation

6

89 FST input (bl, wr) setup time before SCKT falling edge

5

90 FST input (wl) setup time before SCKT falling edge

91 FST input hold time after SCKT falling edge

—

—

—

—

—

—

—

—

—

—

—

—

—

—

2.0

18.0

18.0

13.0

21.0

16.0

14.0

9.0

—

— x ck i ck x ck i ck x ck i ck x ck i ck ns ns ns ns

—

—

—

—

2.0

18.0

4.0

5.0

—

—

—

—

—

21.0

x ck i ck x ck i ck

— ns ns

92 FST input (wl) to data out enable from high impedance

93 FST input (wl) to transmitter #0 drive enable assertion

94 Flag output valid after SCKT rising edge

—

—

—

— — 14.0

— ns ns

— — —

—

14.0

9.0

x ck i ck ns

95

96

HCKR/HCKT clock cycle

HCKT input rising edge to SCKT output

—

—

2 x T

C

—

15

—

—

18.0

—

— ns ns

97 HCKR input rising edge to SCKR output — — — 18.0

— ns

1

2

3

4

5

6

V

CORE_VDD

= 1.00

± 0.10 V; T

J

= –40 °C to 125 °C, C

L

= 50 pF

In the “Characteristics” column, bl = bit length, wl = word length, wr = word length relative

In the “Expression” column, T

C

= 7.5 ns.

For the internal clock, the external clock cycle is defined by Icyc and the ESAI control register.

The word-relative frame sync signal waveform relative to the clock operates in the same manner as the bit-length frame sync signal waveform, but spreads starting from one serial clock before the first bit clock (same as the bit length frame sync signal), until the second-to-last bit-clock of the first word in the frame.

Periodically sampled and not 100% tested.

3.7.8

Enhanced Secured Digital Host Controller (eSDHCv2) Timing

Figure 54

shows eSDHCv2 timing, and

Table 61

describes the timing parameters (SD1–SD8) used in the figure. The following definitions apply to values and signals described in

Table 61 :

• LS: low-speed mode. Low-speed card can tolerate clocks up to 400 kHz

• FS: full-speed mode. Full-speed MMC card’s clock can reach 20 MHz; full speed SD/SDIO card clock can reach 25 MHz

• HS: high-speed mode. High-speed MMC card’s clock can reach 52 MHz; SD/SDIO card clock can reach 50 MHz



SD4

SD2

SD5

SD1 output from eSDHCv2 to card input from card to eSDHCv2

CLK

SD3

CMD

DAT0

DAT1

......

DAT7

SD6

SD7 SD8

CMD

DAT0

DAT1

......

DAT3

Figure 54. eSDHCv2 Timing

Table 61. eSDHCv2 Interface Timing Specification

ID Parameter Symbols Min.

Max.

Unit

Card Input Clock

SD1

SD2

SD3

SD4

Clock frequency (low speed)

Clock frequency (SD/SDIO full speed/high speed)

Clock frequency (MMC full speed/high speed)

Clock frequency (identification mode)

Clock low time

Clock high time

Clock rise time f

PP

1 f

PP

2 f

PP

3 f

OD t

WL t

WH t

TLH t

THL

0

0

0

100

6.5

6.5

—

—

400

25/50

20/52

400

—

—

3

3 kHz

MHz

MHz kHz ns ns ns ns SD5 Clock fall time

eSDHC Output / Card Inputs CMD, DAT (Reference to CLK)

SD6 eSDHC output delay

eSDHC Input / Card Outputs CMD, DAT (Reference to CLK)

t

OD

–3 3 ns

SD7

SD8 eSDHC input setup time eSDHC input hold time t

ISU t

IH

4

2.5

2.5

—

— ns ns

1

2

3

4

In low-speed mode, card clock must be lower than 400 kHz, voltage ranges from 2.7 to 3.6 V.

In normal-speed mode for SD/SDIO card, clock frequency can be any value between 0 ~ 25 MHz. In high speed mode, clock frequency can be any value between 0 ~ 50 MHz.

In normal-speed mode for MMC card, clock frequency can be any value between 0 ~ 20 MHz. In high speed mode, clock frequency can be any value between 0 ~ 52 MHz.

To satisfy hold timing, the delay difference between clock input and cmd/data input must not exceed 2 ns.

84



3.7.9

Fast Ethernet Controller (FEC) Timing

The FEC is designed to support both 10- and 100-Mbps Ethernet networks compliant with the IEEE 802.3 standard. An external transceiver interface and transceiver function are required to complete the interface to the media. The FEC supports 10/100 Mbps MII (18 pins altogether), 10/100 Mbps RMII (ten pins, including serial management interface) and the 10-Mbps-only 7-Wire interface (which uses seven of the

MII pins), for connection to an external Ethernet transceiver. All signals are compatible with transceivers operating at a voltage of 3.3 V.

The following subsections describe the timing for MII and RMII modes.

3.7.9.1

FEC MII Mode Timing

The following subsections describe MII receive, transmit, asynchronous inputs, and serial management signal timings.

3.7.9.1.4

MII Receive Signal Timing (FEC_RXD[3:0], FEC_RX_DV, FEC_RX_ER, and

FEC_RX_CLK)

The receiver functions correctly up to an FEC_RX_CLK maximum frequency of 25 MHz + 1%. There is no minimum frequency requirement. Additionally, the processor clock frequency must exceed twice the

FEC_RX_CLK frequency.

Figure 55

shows MII receive signal timings.

Table 62 describes the timing parameters (M1–M4) shown in

the figure.

M3

FEC_RX_CLK (input)

M4

FEC_RXD[3:0] (inputs)

FEC_RX_DV

FEC_RX_ER

M1 M2

Figure 55. MII Receive Signal Timing Diagram

M1

M2

M3

M4

ID

Table 62. MII Receive Signal Timing

Characteristic

1

FEC_RXD[3:0], FEC_RX_DV, FEC_RX_ER to FEC_RX_CLK setup

FEC_RX_CLK to FEC_RXD[3:0], FEC_RX_DV, FEC_RX_ER hold

FEC_RX_CLK pulse width high

FEC_RX_CLK pulse width low

Min.

5

5

35%

35%

Max.

—

—

65%

65%

Unit

ns ns

FEC_RX_CLK period

FEC_RX_CLK period

1

FEC_RX_DV, FEC_RX_CLK, and FEC_RXD0 have the same timing in 10 Mbps 7-wire interface mode.



3.7.9.1.5

MII Transmit Signal Timing (FEC_TXD[3:0], FEC_TX_EN, FEC_TX_ER, and

FEC_TX_CLK)

The transmitter functions correctly up to an FEC_TX_CLK maximum frequency of 25 MHz + 1%. There is no minimum frequency requirement. Additionally, the processor clock frequency must exceed twice the

FEC_TX_CLK frequency.

Figure 56

shows MII transmit signal timings.

Table 63

describes the timing parameters (M5–M8) shown in the figure.

M7

FEC_TX_CLK (input)

M5

M8

FEC_TXD[3:0] (outputs)

FEC_TX_EN

FEC_TX_ER

M6

Figure 56. MII Transmit Signal Timing Diagram

M5

M6

M7

M8

ID

Table 63. MII Transmit Signal Timing

Characteristic

1

FEC_TX_CLK to FEC_TXD[3:0], FEC_TX_EN, FEC_TX_ER invalid

FEC_TX_CLK to FEC_TXD[3:0], FEC_TX_EN, FEC_TX_ER valid

FEC_TX_CLK pulse width high

FEC_TX_CLK pulse width low

Min.

5

—

35%

35%

Max.

Unit

—

20 ns ns

65% FEC_TX_CLK period

65% FEC_TX_CLK period

1

FEC_TX_EN, FEC_TX_CLK, and FEC_TXD0 have the same timing in 10-Mbps 7-wire interface mode.

3.7.9.1.6

MII Asynchronous Inputs Signal Timing (FEC_CRS and FEC_COL)

Figure 57

shows MII asynchronous input timings.

Table 64 describes the timing parameter (M9) shown in

the figure.

FEC_CRS, FEC_COL

M9

Figure 57. MII Async Inputs Timing Diagram

86



M9

1

ID

Table 64. MII Asynchronous Inputs Signal Timing

Characteristic

FEC_CRS to FEC_COL minimum pulse width

1

FEC_COL has the same timing in 10-Mbit 7-wire interface mode.

Min.

1.5

Max.

—

Unit

FEC_TX_CLK period

3.7.9.2

MII Serial Management Channel Timing (FEC_MDIO and FEC_MDC)

The MDC frequency is designed to be equal to or less than 2.5 MHz to comply with the IEEE 802.3 standard MII specification. However the FEC can function correctly with a maximum MDC frequency of

15 MHz.

Figure 58

shows MII asynchronous input timings.

Table 65

describes the timing parameters (M10—M15) shown in the figure.

M14

M15

FEC_MDC (output)

M10

FEC_MDIO (output)

M11

FEC_MDIO (input)

M10

ID

M11

M12

M13

M14

M15

M12

M13

Figure 58. MII Serial Management Channel Timing Diagram

Table 65. MII Serial Management Channel Timing

Characteristic

FEC_MDC falling edge to FEC_MDIO output invalid (min. propagation delay)

FEC_MDC falling edge to FEC_MDIO output valid (max. propagation delay)

FEC_MDIO (input) to FEC_MDC rising edge setup

FEC_MDIO (input) to FEC_MDC rising edge hold

FEC_MDC pulse width high

FEC_MDC pulse width low

Min.

0

—

18

0

40%

40%

Max.

—

5

—

—

60%

60%

Unit

ns ns ns ns

FEC_MDC period

FEC_MDC period



3.7.9.3

RMII Mode Timing

In RMII mode, FEC_TX_CLK is used as the REF_CLK, which is a 50 MHz ± 50 ppm continuous reference clock. FEC_RX_DV is used as the CRS_DV in RMII. Other signals under RMII mode include

FEC_TX_EN, FEC_TXD[1:0], FEC_RXD[1:0] and FEC_RX_ER.

Figure 59 shows RMII mode timings. Table 66

describes the timing parameters (M16–M21) shown in the figure.

M16

M17

REF_CLK (input)

M18

FEC_TXD[1:0] (output)

FEC_TX_EN

M19

ID

M16

M17

M18

M19

M20

M21

CRS_DV (input)

FEC_RXD[1:0]

FEC_RX_ER

M20

M21

Figure 59. RMII Mode Signal Timing Diagram

Table 66. RMII Signal Timing

Characteristic

REF_CLK(FEC_TX_CLK) pulse width high

REF_CLK(FEC_TX_CLK) pulse width low

REF_CLK to FEC_TXD[1:0], FEC_TX_EN invalid

REF_CLK to FEC_TXD[1:0], FEC_TX_EN valid

FEC_RXD[1:0], CRS_DV(FEC_RX_DV), FEC_RX_ER to REF_CLK setup

REF_CLK to FEC_RXD[1:0], FEC_RX_DV, FEC_RX_ER hold

Min.

35%

35%

3

—

2

2

Max.

65%

65%

—

12

—

—

Unit

REF_CLK period

REF_CLK period ns ns ns ns

88



3.7.10

Controller Area Network (FlexCAN) Transceiver Parameters and

Timing

Table 67

and

Table 68

show voltage requirements for the FlexCAN transceiver Tx and Rx pins.

Table 67. Tx Pin Characteristics

Parameter



1

Vcc = +3.3 V ± 5%

Symbol

V

OH

V

OL

Min.

2

—

Typ.

—

0.8

Max.

Vcc

1

+ 0.3

—

Units

V

V

Parameter

High-level input voltage

Low-level input voltage

1

Vcc = +3.3 V ± 5%

Table 68. Rx Pin Characteristics

Symbol

V

IH

V

IL

Min.

0.8

× Vcc 1

—

Typ.

—

0.4

Max.

Vcc

1

—

Units

V

V

Figure 60

through Figure 63 show the FlexCAN timing, including timing of the standby and shutdown

signals.

TXD t

ONTXD

V

DIFF

RXD

V

CC

/2

0.9V

V

CC

/2 t

OFFTXD t

ONRXD

V

CC

/2 t

OFFRXD

0.5V

V

CC

/2

Figure 60. FlexCAN Timing Diagram i.MX25 Applications Processor for Consumer and Industrial Products, Rev. 10


V

CC x 0.75

RS

Bus Externally

Driven

1.1V

V

DIFF t

SBRXDL t

DRXDL

V

CC

/2 RXD V

CC

/2

Figure 61. Timing Diagram for FlexCAN Standby Signal

SHDN

V

DIFF

V

CC

/2 t

OFFSHDN

V

CC

/2 t

ONSHDN

0.5V

Bus Externally

Driven

RXD

V

CC

/2

Figure 62. Timing Diagram for FlexCAN Shutdown Signal

SHDN V

CC

/2 t

SHDNSB

0.75 x V

CC

RS

Figure 63. Timing Diagram for FlexCAN Shutdown-to-Standby Signal

Because integer multiples are not possible, taking into account the range of frequencies at which the SoC has to operate, DPLLs work in FOL mode only.

90



3.7.11

Inter IC Communication (I

2

C) Timing

The I

2

C communication protocol consists of the following seven elements:

• Start

• Data source/recipient

• Data direction

• Slave acknowledge

• Data

• Data acknowledge

• Stop

Figure 64

shows the timing of the I

2

C module.

Table 69

and Table 70

describe the I

2

C module timing parameters (IC1–IC6) shown in the figure.

IC11

IC10

IC9

I2DAT

IC2

IC8

IC4 IC7

IC3

I2CLK

ID

IC1

IC2

IC3

IC4

IC5

IC6

IC7

IC8

IC9

IC10

IC11

IC12

START

IC10

IC6

IC11

START

IC5

IC1

Figure 64. I

2

C Module Timing Diagram

STOP START

Table 69. I2C Module Timing Parameters: 3.0 V +/–0.30 V

Standard Mode

Parameter

I2CLK cycle time

Hold time (repeated) START condition

Set-up time for STOP condition

Data hold time

HIGH Period of I2CLK Clock

LOW Period of the I2CLK Clock

Set-up time for a repeated START condition

Data set-up time

Bus free time between a STOP and START condition

Rise time of both I2DAT and I2CLK signals

Fall time of both I2DAT and I2CLK signals

Capacitive load for each bus line (C b

)

Min.

10

4.0

4.0

0

1

4.0

4.7

4.7

250

4.7

-

-

-

Fast Mode

Max.

Min.

-

-

-

3.45

2

-

2.5

0.6

0.6

0

1

0.6

-

-

1.3

0.6

100

3

-

1.3

1000 20+0.1C

b

4

300 20+0.1C

b

4

400 -

Max.

-

-

-

-

-

0.9

2

-

-

300

300

400

Unit

ns

μs ns

μs

μs

μs

μs

μs

μs

μs ns pF



1

A device must internally provide a hold time of at least 300 ns for I2DAT signal in order to bridge the undefined region of the falling edge of I2CLK.

2

3

The maximum hold time has only to be met if the device does not stretch the LOW period (ID no IC5) of the I2CLK signal

A Fast-mode I2C-bus device can be used in a Standard-mode I2C-bus system, but the requirement of Set-up time (ID No IC7) of 250 ns must then be met. This is automatically the case if the device does not stretch the LOW period of the I2CLK signal.

If such a device does stretch the LOW period of the I2CLK signal, it must output the next data bit to the I2DAT line max_rise_time(ID No IC9) + data_setup_time(ID No IC7) = 1000 + 250 = 1250 ns (according to the Standard-mode I2C-bus specification) before the I2CLK line is released.

4

C b

= total capacitance of one bus line in pF.

Table 70. I2C Module Timing Parameters: 1.8 V +/– 0.10 V

Standard Mode

ID Parameter Unit

Min.

Max.

IC1

IC2

IC3

IC4

IC5

IC6

IC7

IC8

IC9

IC10

IC11

I2CLK cycle time

Hold time (repeated) START condition

Set-up time for STOP condition

Data hold time

HIGH Period of I2CLK Clock

LOW Period of the I2CLK Clock

Set-up time for a repeated START condition

Data set-up time

Bus free time between a STOP and START condition

Rise time of both I2DAT and I2CLK signals

Fall time of both I2DAT and I2CLK signals

10

4.0

4.0

0

1

4.0

4.7

4.7

250

4.7

-

-

-

-

-

-

-

3.45

-

-

-

1000

300

2

μs

μs

μs

μs

μs

μs

μs ns

μs ns ns

IC12 Capacitive load for each bus line (C b

) 400 pF

1

2

A device must internally provide a hold time of at least 300 ns for I2DAT signal in order to bridge the undefined region of the falling edge of I2CLK.

The maximum hold time has only to be met if the device does not stretch the LOW period (ID no IC5) of the I2CLK signal

92



3.7.12

Liquid Crystal Display Controller (LCDC) Timing

Figure 65

and Figure 66

show LCDC timing in non-TFT and TFT mode respectively, and Table 71 and

Table 72

list the timing parameters used in the associated figures.

T5

VSYNC

Line n Line 1

HSYNC

Line 1 Line 2

T2

HSYNC

T1

LSCLK

T3 T4

LD

Figure 65. LCDC Non-TFT Mode Timing Diagram

Table 71. LCDC Non-TFT Mode Timing Parameters

ID Description

T1

T2

T3

Pixel clock period

HSYNC width

LD setup time

T4

T5

LD hold time

Wait between HSYNC and VSYNC rising edge

T6 Wait between last data and HSYNC rising edge

1

T is pixel clock period

Min.

5

2

1

22.5

1

5

Max.

1000

—

—

—

—

—

T6

Unit

ns

T

1 ns ns

T

1

T

1



VSYNC

HSYNC

Line 1 Line 2

Line n Line 1

HSYNC

T2

T5

OE

T1

LSCLK

T3 T4

LD

Figure 66. LCDC TFT Mode Timing Diagram

Table 72. LCDC TFT Mode Timing Parameters

ID Description

T1

T2

T3

T4

Pixel clock period

HSYNC width

LD setup time

LD hold time

T5 Delay from the end of HSYNC to the beginning of the OE pulse

T6 Delay from end of OE to the beginning of the HSYNC pulse

1

T is pixel clock period

Min.

22.5

1

5

5

3

1

T6

Ma

1000

—

—

—

—

—

Unit

ns

T

1 ns ns

T

1

T

1

3.7.13

Pulse Width Modulator (PWM) Timing Parameters

Figure 67

depicts the timing of the PWM, and

Table 73

lists the PWM timing characteristics.

The PWM can be programmed to select one of three clock signals as its source frequency. The selected clock signal is passed through a prescaler before being input to the counter. The output is available at the pulse width modulator output (PWMO) external pin.

94



1

2a

PWM Source Clock

2b

3a

4a

PWM Output

Figure 67. PWM Timing

Table 73. PWM Output Timing Parameter

Ref No.

1

2a

2b

3a

3b

4a

4b

1

CL of PWMO = 30 pF

Parameter

System CLK frequency

1

Clock high time

Clock low time

Clock fall time

Clock rise time

Output delay time

Output setup time

Minimum

0

12.29

9.91

—

—

—

8.71

3b

4b

Maximum

ipg_clk

—

—

0.5

0.5

9.37

—

3.7.14

Subscriber Identity Module (SIM) Timing

Each SIM module interface consists of a total of 12 pins (two separate ports, each containing six signals).

Typically a port uses five signals.

The interface is designed to be used with synchronous SIM cards, meaning the SIM module provides the clock used by the SIM card. The clock frequency is typically 372 times the Tx/Rx data rate; however, the

SIM module can also work with CLK frequencies of 16 times the Tx/Rx data rate.

There is no timing relationship between the clock and the data. The clock that the SIM module provides to the SIM card is used by the SIM card to recover the clock from the data in the same manner as standard

UART data exchanges. All six signals (five for bidirectional Tx/Rx) of the SIM module are asynchronous with each other.

There are no required timing relationships between signals in normal mode. The SIM card is initiated by the interface device; the SIM card responds with Answer to Reset. Although the SIM interface has no defined requirements, the ISO/IEC 7816 defines reset and power-down sequences (for detailed information see ISO/IEC 7816).

Unit

MHz ns ns ns ns ns ns



1

/SI1

SIMx_CLKy

SI3

SI2

SIMx_DATAy_TX_RX

SIMx_SIMPDy

SI4 SI4

SIMx_DATAy_TX_RX

SI5 SI5

SIMx_RSTy

SI6 SI6

Figure 68. SIM Clock Timing Diagram

Table 74

defines the general timing requirements for the SIM interface.

Table 74. Timing Specifications, High Drive Strength


SI1 SIM clock frequency (SIMx_CLKy)

SI2 SIM clock rise time (SIMx_CLKy)

SI3 SIM clock fall time (SIMx_CLKy)

3

2

1

S freq

S rise

S fall

SI4 SIM input transition time (SIMx_DATAy_RX_TX, SIMx_SIMPDy) S trans

SI5 SIM I/O rise time / fall time (SIMx_DATAy_RX_TX)

4

Tr/Tf

SI6 SIM RST rise time / fall time (SIMx_RSTy)

5

Tr/Tf

1

2

3

4

5

50% duty cycle clock,

With C = 50 pF

With C = 50 pF

With Cin = 30 pF, Cout = 30 pF,

With Cin = 30 pF,

Min.

0.01

—

—

10

—

—

Max.

25

0.09

× (1/S freq

)

0.09

× (1/S freq

)

25

1

1

Unit

MHz ns ns ns

μs

μs

96



3.7.14.1

SIM Reset Sequences

SIM cards may have internal reset, or active low reset. The following subset describes the reset sequences in these two cases.

3.7.14.1.1

SIM Cards with Internal Reset

Figure 69

shows the reset sequence for SIM cards with internal reset. The reset sequence comprises the following steps:

• After power-up, the clock signal is enabled on SIMx_CLKy (time T0)

• After 200 clock cycles, SIMx_DATAy_RX_TX must be asserted.

• The card must send a response on SIMx_DATAy_RX_TX acknowledging the reset between

400–40000 clock cycles after T0.

SIMn_SVENm

SIMx_CLKy

SIMx_DATAy_RX_TX

RESPONSE

1

2

T0

Figure 69. Internal Reset Card Reset Sequence

Table 75


Table 75. Timing Specifications, Internal Reset Card Reset Sequence

Ref No.

1

2

Min.

—

400

Max.

200

40,000

Units

clk cycles clk cycles

3.7.14.1.2

SIM Cards with Active Low Reset

Figure 70

shows the reset sequence for SIM cards with active low reset. The reset sequence comprises the following steps:

• After power-up, the clock signal is enabled on SIMx_CLKy (time T0)

• After 200 clock cycles, SIMx_DATAy_RX_TX must be asserted.

• SIMx_RSTy must remain low for at least 40,000 clock cycles after T0 (no response is to be received on RX during those 40,000 clock cycles)

• SIMx_RSTy is asserted (at time T1)

• SIMx_RSTy must remain asserted for at least 40,000 clock cycles after T1, and a response must be received on SIMx_DATAy_RX_TX between 400 and 40,000 clock cycles after T1.



SIMx_SVENy

SIMx_RSTy

SIMx_CLKy

SIMx_DATAy_RX_TX

RESPONSE

1

2

3

3

T0

T1

Figure 70. Active-Low-Reset SIM Card Reset Sequence

Table 76


Table 76. Timing Specifications, Active-Low-Reset SIM Card Reset Sequence

Ref No.

1

2

3

Min.

—

400

40,000

Max.

200

40,000

—

Unit

clk cycles clk cycles clk cycles

3.7.14.2

SIM Power-Down Sequence

Figure 71 shows the SIM interface power-down AC timing diagram. Table 77 shows the timing

requirements for parameters (SI7–SI10) shown in the figure.

The power-down sequence for the SIM interface is as follows:

• SIMx_SIMPDy port detects the removal of the SIM Card

• SIMx_RSTy is negated

• SIMx_CLKy is negated

• SIMx_DATAy_RX_TX is negated

• SIMx_SVENy is negated

Each of the above steps requires one CKIL period (usually 32 kHz). Power-down may be initiated by a

SIM card removal detection; or it may be launched by the processor.

98



SI10

SIMx_SIMPDy

SIMx_RSTy

SIMx_CLKy

SIMx_RXy & SIMx_TXy

SIMx_VENy

SI7

SI8

SI9

Figure 71. SmartCard Interface Power Down AC Timing

Table 77. Timing Requirements for Power-down Sequence

ID PARAMETER

SI7 SIM reset to SIM clock stop

SI8 SIM reset to SIM Tx data low

SI9 SIM reset to SIM voltage enable low

SI10 SIM presence detect to SIM reset low

SYMBOL

S rst2clk

S rst2dat

S rst2ven

S pd2rst

Min.

0.9

× 1/Fckil

1.8

× 1/Fckil

2.7

× 1/Fckil

0.9

× 1/Fckil

Max.

1.1

× 1/Fckil

2.2

× 1/Fckil

3.3

× 1/Fckil

1.1

× 1/Fckil

Unit

ns ns ns ns

3.7.15

System JTAG Controller (SJC) Timing

Figure 72

through Figure 75 show respectively the test clock input, boundary scan, test access port, and

TRST timings for the SJC.

Table 78

describes the SJC timing parameters (SJ1–SJ13) indicated in the figures.

TCK

(Input)

SJ1

SJ3

VIH

SJ2

VM

SJ2

VM

VIL

SJ3

Figure 72. Test Clock Input Timing Diagram i.MX25 Applications Processor for Consumer and Industrial Products, Rev. 10


TCK

(Input)

VIL

VIH

SJ4

Input Data Valid

SJ5

Data

Inputs

SJ6

Data

Outputs

Data

Outputs

SJ7

Output Data Valid

Data

Outputs

TDI

TMS

(Input)

TDO

(Output)

TDO

(Output)

TDO

(Output)

TCK

(Input)

SJ6

Output Data Valid

Figure 73. Boundary Scan (JTAG) Timing Diagram

VIL

SJ8

Input Data Valid

VIH

SJ9

SJ10

Output Data Valid

SJ11

SJ10

Output Data Valid

Figure 74. Test Access Port Timing Diagram

100



TCK

(Input)

SJ13

TRST

(Input)

SJ12

Figure 75. TRST Timing Diagram

Table 78. SJC Timing Parameters

All Frequencies

ID Parameter Unit

SJ1 TCK cycle time

SJ2 TCK clock pulse width measured at

V

M

2

SJ3 TCK rise and fall times

SJ4

SJ5

SJ6 TCK low to output data valid

SJ7 TCK low to output high impedance

SJ8

SJ9

Boundary scan input data set-up time

Boundary scan input data hold time

TMS, TDI data set-up time

TMS, TDI data hold time

SJ10 TCK low to TDO data valid

SJ11 TCK low to TDO high impedance

Min. Max.

100

1

—

40

—

10

50

—

—

10

50

—

—

—

3

—

—

50

50

—

—

44

44 ns ns ns ns ns ns ns ns ns ns ns

SJ12 TRST assert time 100 — ns

SJ13 TRST set-up time to TCK low 40 — ns

1

2

In cases where SDMA TAP is put in the chain, the maximum TCK frequency is limited by the maximum ratio of 1:8 of SDMA core frequency to TCK. This implies a maximum frequency of 8.25 MHz (or 121.2 ns) for a 66 MHz IPG clock.

V

M – mid point voltage



3.7.16

Smart Liquid Crystal Display Controller (SLCDC)

Figure 76

and Figure 77 show SLCDC timing for serial and parallel transfers respectively. Table 79

and

Table 80

describe the timing parameters shown in the respective figures.

tcss tcsh tcyc

LCD_CS tcl tch

LCD_CLK (LCD_DATA[6])

SDATA (LCD_DATA[7])

RS tds tdh

MSB trss

RS=0 => command data, RS=1=> display data trsh

LSB

(This diagram shows the case SCKPOL = 1, CSPOL = 0) tcss tcsh tcyc

LCD_CS tcl tch


SDATA (LCD_DATA[7]) tds tdh

MSB trss


LSB

RS

LCD_CS tcss

(This diagram shows the case SCKPOL = 0, CSPOL = 0) tcsh tcyc tcl tch

LCD_CLK (LCD_DATA[6]) tds tdh

SDATA (LCD_DATA[7])

MSB

RS trss


LSB

(This diagram shows the case SCKPOL = 1, CSPOL = 1) tcss tcsh

LCD_CS tcyc tcl tch


SDATA (LCD_DATA[7])

MSB tds tdh trsh

LSB trss

RS=0 => command data, RS=1=> display data

RS

(This diagram shows the case SCKPOL = 0, CSPOL = 1)

Figure 76. SLCDC Timing Diagram—Serial Transfers to LCD Device

102



Symbol

t ch t ds t dh t rss t rsh t css t csh t cyc t cl

Table 79. SLCDC Serial Interface Timing Parameters

Parameter

Chip select setup time

Chip select hold time

Serial clock cycle time

Serial clock low pulse

Serial clock high pulse

Data setup time

Data hold time

Register select setup time

Register select hold time

Min.

(t cyc

/ 2) (

±

) t prop

(t cyc

/ 2) (

±

) t prop

39 (

±

) t prop

18 (

±) t prop

18 (

±) t prop

(t cyc

/ 2) (

±) t prop

(t cyc

/ 2) (

±) t prop

(15

× t cyc

/ 2) (

±) t prop

(t cyc

/ 2) (

±) t prop

Typ.

—

—

—

—

—

—

—

—

—

LCD_CLK trss trsh

LCD_RS tcyc

LCD_CS

LCD_DATA[15:0] tds tdh command data display data

(This diagram shows the case CSPOL=0)

LCD_CLK trss trsh

LCD_RS tcyc

LCD_CS tds tdh command data

LCD_DATA[15:0] display data

(This diagram shows the case CSPOL=1)

Figure 77. SLCDC Timing Diagram—Parallel Transfers to LCD Device

Max.

—

—

—

—

—

—

—

2641

—

Units

ns ns ns ns ns ns ns ns ns



Symbol

t cyc t ds t dh t rss t rsh

Table 80. SLCDC Parallel Interface Timing Parameters

Parameter

Parallel clock cycle time

Data setup time

Data hold time

Register select setup time

Register select hold time

Min.

78 (

±) t prop

(t cyc

/ 2) (

±) t prop

(t cyc

/ 2) (

±) t prop

(t cyc

/ 2) (

±) t prop

(t cyc

/ 2) (

±) t prop

Typ.

—

—

—

—

—

3.7.17

Synchronous Serial Interface (SSI) Timing

The following subsections describe SSI timing in four cases:

• Transmitter with external clock

• Receiver with external clock

• Transmitter with internal clock

• Receiver with internal clock

Max.

4923

—

—

—

—

3.7.17.1

SSI Transmitter Timing with Internal Clock

Figure 78

shows the timing for SSI transmitter with internal clock, and Table 81

describes the timing parameters (SS1–SS52).

SS1

SS2

SS5

SS4

SS3

AUDn_TXC

(Output)

SS6

SS8

AUDn_TXFS (bl)

(Output)

SS10

AUDn_TXFS (wl)

(Output)

SS14

SS15

SS16

SS17

SS18

AUDn_TXD

(Output)

SS43

SS42

SS19

AUDn_RXD

(Input)

Note: SRXD Input in Synchronous mode only

Figure 78. SSI Transmitter with Internal Clock Timing Diagram

SS12

Units

ns

—

—

—

—

104



Table 81. SSI Transmitter Timing with Internal Clock

Parameter Min.

ID

Internal Clock Operation

SS1

SS2

SS3

SS4

SS5

SS6

SS8

(Tx/Rx) CK clock period

(Tx/Rx) CK clock high period

(Tx/Rx) CK clock rise time

(Tx/Rx) CK clock low period

(Tx/Rx) CK clock fall time

(Tx) CK high to FS (bl) high

(Tx) CK high to FS (bl) low

SS10 (Tx) CK high to FS (wl) high

SS12 (Tx) CK high to FS (wl) low

SS14 (Tx/Rx) internal FS rise time

SS15 (Tx/Rx) internal FS fall time

SS16 (Tx) CK high to STXD valid from high impedance

SS17 (Tx) CK high to STXD high/low

SS18 (Tx) CK high to STXD high impedance

SS19 STXD rise/fall time

Synchronous Internal Clock Operation

SS42 SRXD setup before (Tx) CK falling

SS43 SRXD hold after (Tx) CK falling

SS52 Loading

—

—

—

—

—

—

—

—

81.4

36.0

—

36.0

—

—

—

10.0

0.0

—

Max.

15.0

15.0

15.0

6.0

15.0

15.0

6.0

6.0

—

—

6.0

—

6.0

15.0

15.0

Unit

—

—

25.0

ns ns pf

Note:

• All the timings for the SSI are given for a non-inverted serial clock polarity (TSCKP/RSCKP = 0) and a non-inverted frame sync

(TFSI/RFSI = 0). If the polarity of the clock and/or the frame sync have been inverted, all the timing remains valid by inverting the clock signal STCK/SRCK and/or the frame sync STFS/SRFS shown in the tables and in the figures.

• All timings are on pads when SSI is being used for a data transfer.

• ”Tx” and “Rx” refer, respectively, to the transmit and receive sections of the SSI.

• For internal frame sync operation using external clock, the FS timing is the same as that of Tx data (for example, during AC97 mode of operation).

ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns



3.7.17.2

SSI Receiver Timing with Internal Clock

Figure 79

shows the timing for the SSI receiver with internal clock.

Table 82

describes the timing parameters (SS1–SS51) shown in the figure.

SS1

SS2

SS5

SS4

SS3

AUDn_TXC

(Output)

SS7

SS9

AUDn_TXFS (bl)

(Output)

SS11

SS13

AUDn_TXFS (wl)

(Output)

SS20

SS21

AUDn_RXD

(Input)

SS48

SS47

SS51

SS50

SS49

ID

SS1

SS2

SS3

SS4

SS5

SS7

SS9

SS11

SS13

SS20

SS21

SS47

AUDn_RXC

(Output)

Figure 79. SSI Receiver Internal Clock Timing Diagram

Table 82. SSI Receiver Timing with Internal Clock

Min.

Parameter

Internal Clock Operation






(Rx) CK high to FS (bl) high

(Rx) CK high to FS (bl) low

(Rx) CK high to FS (wl) high

(Rx) CK high to FS (wl) low

SRXD setup time before (Rx) CK low

SRXD hold time after (Rx) CK low

Oversampling Clock Operation

Oversampling clock period 15.04

—

—

—

—

81.4

36.0

—

36.0

—

10.0

0.0

Max.

6.0

15.0

15.0

15.0

—

—

6.0

—

15.0

—

—

—

Unit


106



ID

SS48

SS49

SS50

SS51

Table 82. SSI Receiver Timing with Internal Clock (continued)

Parameter

Oversampling clock high period

Oversampling clock rise time

Oversampling clock low period

Oversampling clock fall time

Min.

6.0

—

6.0

—

Max.

—

3.0

—

3.0

Unit

ns ns ns ns

Note:



• All timings are on pads when SSI is being used for a data transfer.

• ”Tx” and “Rx” refer to the transmit and receive sections of the SSI.

• For internal frame sync operation using external clock, the FS timing is the same as that of Tx Data (for example, during AC97 mode of operation).

3.7.17.3

SSI Transmitter Timing with External Clock

Figure 80

shows the timing for the SSI transmitter with external clock. Table 83

describes the timing parameters (SS22-SS46) shown in the figure.

SS22

SS23

SS25

SS26

SS24

AUDn_TXC

(Input)

SS27

SS29

AUDn_TXFS (bl)

(Input)

SS31

SS33

AUDn_TXFS (wl)

(Input)

SS37

SS38

AUDn_TXD

(Output)

SS45

SS44

AUDn_RXD

(Input)

Note: SRXD Input in Synchronous mode only

SS46

Figure 80. SSI Transmitter with External Clock Timing Diagram

SS39



Table 83. SSI Transmitter Timing with External Clock

Min.

ID Parameter

External Clock Operation

SS22 (Tx/Rx) CK clock period

SS23 (Tx/Rx) CK clock high period

SS24 (Tx/Rx) CK clock rise time

SS25 (Tx/Rx) CK clock low period

SS26 (Tx/Rx) CK clock fall time

SS27 FS (bl) low/ high setup before (Tx) CK falling

SS29 FS (bl) low/ high setup before (Tx) CK falling

SS31 FS (wl) low/ high setup before (Tx) CK falling

SS33 FS (wl) low/ high setup before (Tx) CK falling

SS37 (Tx) CK high to STXD valid from high impedance

SS38 (Tx) CK high to STXD high/low

SS39 (Tx) CK high to STXD high impedance

Synchronous External Clock Operation

SS44 SRXD setup before (Tx) CK falling

SS45 SRXD hold after (Tx) CK falling

SS46 SRXD rise/fall time

10.0

2.0

—

81.4

36.0

—

36.0

—

–10.0

10.0

–10.0

10.0

—

—

—

Max.

—

—

6.0

—

6.0

15.0

—

15.0

—

15.0

15.0

15.0

Unit

—

—

6.0

ns ns ns

Note:


(TFSI/RFSI = 0). If the polarity of the clock and/or the frame sync have been inverted, all the timing remains valid by inverting the clock signal STCK/SRCK and/or the frame sync STFS/SRFS shown in the tables figures.

• All timings are on pads when SSI is being used for data transfer.




108



3.7.17.4

SSI Receiver Timing with External Clock

Figure 81 shows the timing for SSI receiver with external clock. Table 84 describes the timing parameters

(SS22–SS41) used in the figure.

SS22

SS23

SS26

SS25

SS24

ID

SS22

SS23

SS24

SS25

SS26

SS28

SS30

SS32

SS34

SS35

SS36

SS40

SS41

AUDn_TXC

(Input)

SS28

SS30

AUDn_TXFS (bl)

(Input)

AUDn_TXFS (wl)

(Input)

SS32

SS35

SS41

SS34

SS36

SS40

AUDn_RXD

(Input)

Figure 81. SSI Receiver with External Clock Timing Diagram

Table 84. SSI Receiver Timing with External Clock

Parameter Min.





External Clock Operation


FS (bl) low/high setup before (Tx) CK falling

FS (bl) low/high setup before (Tx) CK falling

FS (wl) low/high setup before (Tx) CK falling

FS (wl) low/high setup before (Tx) CK falling

(Tx/Rx) External FS rise time

(Tx/Rx) External FS fall time

SRXD setup time before (Rx) CK low

SRXD hold time after (Rx) CK low

81.4

36.0

—

36.0

—

–10.0

10.0

–10.0

10.0

—

—

10.0

2.0

Max.

—

—

6.0

—

6.0

15.0

—

15.0

—

6.0

6.0

—

—

Unit

ns ns ns ns ns ns ns ns ns ns ns ns ns

Note:



• All timings are on pads when SSI is being used for data transfer.





3.7.18

Touchscreen ADC Electrical Specifications and Timing

This section describes the electrical specifications, operation modes, and timing of the touchscreen ADC.

3.7.18.1

ADC Electrical Specifications

Table 85

shows the electrical specifications for the touchscreen ADC.

Table 85. Touchscreen ADC Electrical Specifications

Min.

Parameter Conditions

Input sampling capacitance ( C

Resolution

S

)

Resistance value between ref and agndref

ADC

No pin/pad capacitance included

—

Analog Bias

—

Sampling rate (fs)

Internal ADC/TSC clock frequency

Multiplexed inputs

Data latency

Timing Characteristics

—

—

—

—

—

—

—

—

Typ.

2

12

1.6

—

—

8

12.5

Power-up time

1

— 14 clk falling edge to sampling delay

(tsd) soc input setup time before clk rising edge (tsocst) soc input hold time after clk rising edge (tsochld) eoc delay after clk rise edge (teoc) With a 250 pF load

Valid data out delay after eoc rise edge (tdata)

With a 250 pF load

—

—

—

Current consumption

QV

DD

2

NVCC_ADC

Power Supply Requirements

—

2

2

5

2

0.5

— —

3

7

8

5

1

Max.

—

—

6

10

13

8

3

125

1.75

kHz

MHz

— clk cycles clk cycles ns ns ns ns ns

2.1

0.5

Unit

pF bits k

Ω mA mA

110



Table 85. Touchscreen ADC Electrical Specifications (continued)

Parameter Conditions Min.

Typ.

Max.

Unit

Power-down current

NVCC_ADC

QV

DD

— — — 1

10 uA uA

Touchscreen Interface

Expected plate resistance

Switch drivers on resistance

—

GND and VDD switches

Conversion Characteristics

3

100

—

—

—

1500

10

Ω

Ω

DNL

4

INL

4 fin = 1 kHz fin = 1 kHz

—

—

+/–0.75

+/–2.0

—

—

LSB

LSB

Gain + Offset Error — — — +/–2 %FS

1

2

3

4

This comprises only the required initial dummy conversion cycle. Additional power-up time depends on the enadc, reset and soc signals applied to the touchscreen controller.

This value only includes the ADC and the driver switches, but it does not take into account the current consumption in the touchscreen plate. For example, if the plate resistance is 100 W, the total current consumption is about 33 mA.

At avdd = 3.3 V, dvdd = 1.2 V, Tjunction = 50 °C, fclk = 1.75 MHz, any process corner, unless otherwise noted.

Value measured with a –0.5 dBFS sinusoidal input signal and computed with the code density test.

3.7.18.2

ADC Timing Diagrams

Figure 82

represents the synchronization between the signals clk, soc, eoc, and the output bits in the usage of the internal ADC. After a conversion cycle eoc is asserted, a new conversion begins only when the



assertion of soc is detected. Thus, if the soc signal is continuously asserted, the ADC undergoes successive conversion cycles and achieves the maximum sampling rate. If soc is negated, no conversion is initiated.

Figure 82. Start-up Sequence

The output data can be read from adcout11...adcout0, and is available tdata nanoseconds after the rising edge of eoc. The reset signal and the digital signals controlling the analog switches (ypsw, xpsw, ynsw,

xnsw) are totally asynchronous.

The following conditions are necessary to guarantee the correct operation of the ADC:

• The input multiplexer selection (selin11…selin0) is stable during both the last clock cycle (14 th

) and the first clock cycle (1 st

). The best way to guarantee this is to make the input multiplexer selection during clock cycles 2 to 13.

• The references are stable during clock cycle 1 to 13. The best way to guarantee this is to make the reference multiplexer selection (selrefp and selrefn) before issuing an soc pulse and changing it only after an eoc pulse has been acquired, during the last clock cycle (14).

112



Figure 83

shows the timing for ADC normal operation.

Figure 83. Timing for ADC Normal Operation

When the ADC is used so that the idle clock cycles occur between conversions (due to the negation of soc), the selin inputs must be stable at least 1 clock cycle before the clock's rising edge where the soc signal is latched. Also, selrefp and selrefn must be stable by the time the soc signal is latched. These conditions are met if enadc=1 and reset=0 throughout ADC operation, including the idle cycles. If the conditions are not met, or if power is lost during ADC operation, then a new start-up sequence is required for ADC to become operational again.



Figure 84

represents the usage of the ADC with idle cycles between conversions. This diagram is valid for any value of N equal or greater than 1.

Figure 84. ADC Usage with Idle Cycles Between Conversions

3.7.19

UART Timing

This section describes the timing of the UART module in serial and parallel mode.

114



3.7.19.1

UART RS-232 Serial Mode Timing

3.7.19.1.1

UART Transmit Timing in RS-232 Serial Mode

Figure 85

shows the UART transmit timing in RS-232 serial mode, showing only 8 data bits and 1 stop bit.

Table 86

describes the timing parameter (UA1) shown in the figure.

UA1 UA1

Possible

Parity

Bit

TXD

(output)

Start

Bit

Bit 0 Bit 1 Bit 2 Bit 3 Bit 4 Bit 5 Bit 6 Bit 7 Par Bit

STOP

BIT

Next

Start

Bit

UA1 UA1

Figure 85. UART RS-232 Serial Mode Transmit Timing Diagram

Table 86. UART RS-232 Serial Mode Transmit Timing Parameters


Max.

UA1 Transmit Bit Time t

Tbit

1/F baud_rate

1

– T ref_clk

2

1/F baud_rate

+ T ref_clk

1

2

F baud_rate

: Baud rate frequency. The maximum baud rate the UART can support is ( ipg_perclk frequency)/16.

T ref_clk

: The period of UART reference clock ref_clk (ipg_perclk after RFDIV divider).

Units

—

3.7.19.1.2

UART Receive Timing in RS-232 Serial Mode

Figure 86

shows the UART receive timing in RS-232 serial mode, showing only 8 data bits and 1 stop bit.

Table 87

describes the timing parameter (UA2) shown in the figure.

–

UA2

UA2

Possible

Parity

Bit

RXD

(input)

Start

Bit

Bit 0 Bit 1 Bit 2 Bit 3 Bit 4 Bit 5 Bit 6

Bit 7

Par Bit

STOP

BIT

Next

Start

Bit

UA2 UA2

Figure 86. UART RS-232 Serial Mode Receive Timing Diagram

Table 87. UART RS-232 Serial Mode Receive Timing Parameters


Max.

Units

1

2

UA2 Receive bit time

1 t

Rbit

1/F baud_rate

× F

2

– 1/(16 baud_rate

)

1/F baud_rate

+ 1/(16

× F baud_rate

)

—

The UART receiver can tolerate 1/(16

× F baud_rate exceed 3/(16

× F baud_rate

).

) tolerance in each bit. But accumulation tolerance in one frame must not

F baud_rate




3.7.19.2

UART Infrared (IrDA) Mode Timing

The following subsections describe the UART transmit and receive timing in IrDA mode.

3.7.19.2.3

UART IrDA Mode Transmit Timing

Figure 87

depicts the UART transmit timing in IrDA mode, showing only 8 data bits and 1 stop bit.

Table 88

describes the timing parameters (UA3–UA4) shown in the figure.

UA3

UA3

UA4

UA3

UA3

TXD

(output)

Start

Bit

Bit 0 Bit 1

Bit 2 Bit 3 Bit 4 Bit 5 Bit 6 Bit 7

Possible

Parity

Bit

STOP

BIT

Figure 87. UART IrDA Mode Transmit Timing Diagram

Table 88. UART IrDA Mode Transmit Timing Parameters


Max.

UA3

UA4

Transmit bit time in IrDA mode

Transmit IR pulse duration t

TIRbit t

TIRpulse

1/F baud_rate

1

– T ref_clk

2

(3/16)

× (1/F baud_rate

) – T ref_clk

1/F baud_rate

+ T ref_clk

(3/16)

× (1/F baud_rate

) + T ref_clk

1

2

F baud_rate


T ref_clk

: The period of UART reference clock ref_clk (ipg_perclk after RFDIV divider).

Units

—

—

3.7.19.2.4

UART IrDA Mode Receive Timing

Figure 88

shows the UART receive timing for IrDA mode, for a format of 8 data bits and 1 stop bit.

Table 89

describes the timing parameters (UA5–UA6) shown in the figure.

UA5

UA5

UA6

UA5 UA5

RXD

(input)

Start

Bit

Bit 0 Bit 1

Bit 2 Bit 3 Bit 4 Bit 5 Bit 6 Bit 7

Possible

Parity

Bit

STOP

BIT

Figure 88. UART IrDA Mode Receive Timing Diagram

Table 89. UART IrDA Mode Receive Timing Parameters


Max.

Units

UA5 Receive bit time

1

in IrDA mode t

RIRbit

1/F baud_rate

2

– 1/(16

× F baud_rate

) 1/F baud_rate

+ 1/(16

× F baud_rate

) —

1

UA6 Receive IR pulse duration t

RIRpulse

1.41

μs

(5/16)

× (1/F baud_rate

) —

The UART receiver can tolerate 1/(16

× F baud_rate exceed 3/(16

× F baud_rate

).

) tolerance in each bit. But accumulation tolerance in one frame must not

116



2

F baud_rate


3.7.20

USBOTG Timing

This section describes timing for the USB OTG port and host ports. Both serial and parallel interfaces are described.

3.7.20.1

USB Serial Interface Timing

The USB serial transceiver is configurable to four modes supporting four different serial interfaces:

• DAT_SE0 bidirectional, 3-wire mode

• DAT_SE0 unidirectional, 6-wire mode

• VP_VM bidirectional, 4-wire mode

• VP_VM unidirectional, 6-wire mode

The following subsections describe the timings for these four modes.

3.7.20.1.1

DAT_SE0 Bidirectional Mode Timing

Table 90

defines the DAT_SE0 bidirectional mode signals.

Table 90. Signal Definitions—DAT_SE0 Bidirectional Mode

Name

USB_TXOE_B

USB_DAT_VP

USB_SE0_VM

Direction

Out

Out

In

Out

In


Transmit enable, active low

Tx data when USB_TXOE_B is low

Differential Rx data when USB_TXOE_B is high

SE0 drive when USB_TXOE_B is low

SE0 Rx indicator when USB_TXOE_B is high

Figure 89

shows the USB transmit waveform in DAT_SE0 bidirectional mode diagram.

Transmit

USB_DAT_VP

USB_SE0_VM

US1

US4 US2

Figure 89. USB Transmit Waveform in DAT_SE0 Bidirectional Mode i.MX25 Applications Processor for Consumer and Industrial Products, Rev. 10


Figure 90

shows the USB receive waveform in DAT_SE0 bidirectional mode diagram.

Receive

USB_TXOE_B

USB_DAT_VP

USB_SE0_VM

US5

US7/US8

US6

Figure 90. USB Receive Waveform in DAT_SE0 Bidirectional Mode

Table 91

shows the OTG port timing specification in DAT_SE0 bidirectional mode.

Table 91. OTG Port Timing Specification in DAT_SE0 Bidirectional Mode

No.

US1

US2

US3

US4

US5

US6

Parameter

Tx rise/fall time

Tx rise/fall time

Tx rise/fall time

Tx duty cycle

Enable Delay

Disable Delay

Signal Name

USB_DAT_VP

USB_SE0_VM

USB_TXOE_B

USB_DAT_VP

USB_DAT_VP

USB_SE0_VM

USB_DAT_VP

USB_SE0_VM

USB_DAT_VP

USB_SE0_VM

Direction

Out

Out

Out

Out

In

In

Min.

—

—

—

49.0

—

—

Max.

5.0

5.0

5.0

51.0

8.0

10.0

ns

US7

US8

Rx rise/fall time

Rx rise/fall time

In

In

—

—

3.0

3.0

ns ns

3.7.20.1.2

DAT_SE0 Unidirectional Mode Timing

Table 92

defines the DAT_SE0 unidirectional mode signals.

Table 92. Signal Definitions—DAT_SE0 Unidirectional Mode

Name

USB_TXOE_B

USB_DAT_VP

USB_SE0_VM

USB_VP1

USB_VM1

USB_RCV

Direction

In

In

In

Out

Out

Out



Tx data when USB_TXOE_B is low

SE0 drive when USB_TXOE_B is low

Buffered data on DP when USB_TXOE_B is high

Buffered data on DM when USB_TXOE_B is high

Differential Rx data when USB_TXOE_B is high

Unit

ns ns ns

% ns

Conditions/

Reference Signal

50 pF

50 pF

50 pF

—

USB_TXOE_B

USB_TXOE_B

35 pF

35 pF

118



Figure 91

shows the USB transmit waveform in DAT_SE0 unidirectional mode diagram.

Transmit

USB_DAT_VP

USB_SE0_VM

US9

US12

Figure 91. USB Transmit Waveform in DAT_SE0 Unidirectional Mode

Figure 92

shows the USB receive waveform in DAT_SE0 unidirectional mode diagram.

Receive

USB_DAT_VP

USB_SE0_VM

RCV

US10

US13

US17

US14

Figure 92. USB Receive Waveform in DAT_SE0 Unidirectional Mode

Table 93

shows the USB port timing specification in DAT_SE0 unidirectional mode.

Table 93. USB Port Timing Specification in DAT_SE0 Unidirectional Mode

No.

US9

US10

US11

US12

US13

US14

US15

US16

US17

Parameter

Tx rise/fall time

Tx rise/fall time

Tx rise/fall time

Tx duty cycle

Enable Delay

Disable Delay

Rx rise/fall time

Rx rise/fall time

Rx rise/fall time

Signal Name

USB_DAT_VP

USB_SE0_VM

USB_TXOE_B

USB_DAT_VP

USB_DAT_VP

USB_SE0_VM

USB_DAT_VP

USB_SE0_VM

USB_VP1

USB_VM1

USB_RCV

Signal

Source

Out

Out

Out

Out

In

In

In

In

In

Min.

—

—

—

49.0

—

—

—

—

—

Max.

5.0

5.0

5.0

51.0

8.0

10.0

3.0

3.0

3.0

Unit

ns ns ns ns ns ns

% ns ns

Condition/


50 pF

50 pF

50 pF

—

USB_TXOE_B

USB_TXOE_B

35 pF

35 pF

35 pF



3.7.20.1.3

VP_VM Bidirectional Mode Timing

Table 94

defines the VP_VM bidirectional mode signals.

Table 94. Signal Definitions—VP_VM Bidirectional Mode

Name

USB_TXOE_B

USB_DAT_VP

USB_SE0_VM

USB_RCV

Direction

Out

Out (Tx)

In (Rx)

Out (Tx)

In (Rx)

In


• Transmit enable, active low

• Tx VP data when USB_TXOE_B is low

• Rx VP data when USB_TXOE_B is high

• Tx VM data when USB_TXOE_B low

• Rx VM data when USB_TXOE_B high

• Differential Rx data

Figure 93

shows the USB transmit waveform in VP_VM bidirectional mode diagram.

Transmit

US1

USB_TXENB

USB_VPOUT

US4

US2

USB_VMOUT

US3

Figure 93. USB Transmit Waveform in VP_VM Bidirectional Mode

Figure 94

shows the USB receive waveform in VP_VM bidirectional mode diagram.

Receive

US5

USB_VPIN

USB_VMIN

US6

Figure 94. USB Receive Waveform in VP_VM Bidirectional Mode

120



Table 95

shows the USB port timing specification in VP_VM bidirectional mode.

Table 95. USB Port Timing Specifications in VP_VM Bidirectional Mode

No.

US18

US19

US20

US21

US22

US23

US24

US25

US26

US27

US28

US29

Parameter

Tx rise/fall time

Tx rise/fall time

Tx rise/fall time

Tx duty cycle

Tx high overlap

Tx low overlap

Enable delay

Disable delay

Rx rise/fall time

Rx rise/fall time

Rx skew

Rx skew

Signal Name Direction

USB_DAT_VP

USB_SE0_VM

USB_TXOE_B

USB_DAT_VP

USB_SE0_VM

USB_SE0_VM

USB_DAT_VP

USB_SE0_VM

USB_DAT_VP

USB_SE0_VM

USB_DAT_VP

USB_SE0_VM

USB_DAT_VP

USB_RCV

Out

Out

Out

Out

Out

Out

In

In

In

In

Out

Out

—

—

–4.0

–6.0

Min.

—

—

—

49.0

0.0

—

—

—

Max.

5.0

5.0

5.0

51.0

—

0.0

8.0

10.0

3.0

3.0

+4.0

+2.0

ns ns ns ns ns

Unit

% ns ns ns ns ns ns

Condition/


50 pF

50 pF

50 pF

—

USB_DAT_VP

USB_DAT_VP

USB_TXOE_B

USB_TXOE_B

35 pF

35 pF

USB_SE0_VM

USB_DAT_VP

3.7.20.1.4

VP_VM Unidirectional Mode Timing

Table 96

defines the signals for USB in VP_VM unidirectional mode.

Table 96. Signal Definitions for USB VP_VM Unidirectional Mode

Name

USB_TXOE_B

USB_DAT_VP

USB_SE0_VM

USB_VP1

USB_VM1

USB_RCV

Direction

Out

Out

Out

In

In

In



Tx VP data when USB_TXOE_B is low

Tx VM data when USB_TXOE_B is low

Rx VP data when USB_TXOE_B is high

Rx VM data when USB_TXOE_B is high

Differential Rx data



Figure 95

shows the USB transmit waveform in VP_VM unidirectional mode diagram.

Transmit

US32

USB_TXOE_B

USB_DAT_VP

USB_SE0_VM

US30

US33 US31

US34

Figure 95. USB Transmit Waveform in VP_VM Unidirectional Mode

Figure 96

shows the USB receive waveform in VP_VM unidirectional mode diagram.

Receive

USB_TXOE_B

USB_VP1

US36

US38

US37

USB_VM1

US40

US39

USB_RCV

US41

Figure 96. USB Receive Waveform in VP_VM Unidirectional Mode

122



Table 97

shows the timing specifications for USB in VP_VM unidirectional mode.

Table 97. USB Timing Specifications in VP_VM Unidirectional Mode

No.

US30

US31

US32

US33

US34

US35

US36

US37

US38

US39

US40

US41

Parameter

Tx rise/fall time

Tx rise/fall time

Tx rise/fall time

Tx duty cycle

Tx high overlap

Tx low overlap

Enable delay

Disable delay

Rx rise/fall time

Rx rise/fall time

Rx skew

Rx skew

Signal

USB_DAT_VP

USB_SE0_VM

USB_TXOE_B

USB_DAT_VP

USB_SE0_VM

USB_SE0_VM

USB_DAT_VP

USB_SE0_VM

USB_DAT_VP

USB_SE0_VM

USB_VP1

USB_VM1

USB_VP1

USB_RCV

Direction

Out

Out

Out

Out

Out

Out

In

In

In

In

Out

Out

Min.

—

—

—

49.0

0.0

—

—

—

—

—

–4.0

–6.0

Max.

5.0

5.0

5.0

51.0

—

0.0

8.0

10.0

3.0

3.0

+4.0

+2.0

ns ns ns ns ns

% ns ns ns ns ns ns

Unit

Conditions/


50 pF

50 pF

50 pF

—

USB_DAT_VP

USB_DAT_VP

USB_TXOE_B

USB_TXOE_B

35 pF

35 pF

USB_SE0_VM

USB_DAT_VP

3.7.20.2

USB Parallel Interface Timing

Table 98

defines the USB parallel interface signals.

Table 98. Signal Definitions for USB Parallel Interface

Name

USB_Clk

USB_Data[7:0]

Direction

In

I/O

USB_Dir

USB_Stp

USB_Nxt

In

Out

In


Interface clock—All interface signals are synchronous to USB_Clk

Bidirectional data bus, driven low by the link during idle—Bus ownership is determined by the direction

Direction—Control the direction of the data bus

Stop—The link asserts this signal for one clock cycle to stop the data stream currently on the bus

Next—The PHY asserts this signal to throttle the data



Figure 97

shows the USB parallel mode transmit/receive waveform.

Table 99 describes the timing

parameters (USB15–USB17) shown in the figure.

USB_Clk

US15

US16

USB_Stp

US15

US16

USB_Data

US17

US17

USB_Dir/Nxt

Figure 97. USB Parallel Mode Transmit/Receive Waveform

Table 99. USB Timing Specification in Parallel Mode

ID Parameter

US15 Setup time (Dir&Nxt in, Data in)

US16 Hold time (Dir&Nxt in, Data in)

US17 Output delay time (Stp out, Data out

Min.

6.0

0.0

—

Max.

—

—

9.0

Unit

ns ns ns

Conditions/Reference Signal

10 pF

10 pF

10 pF

4 Package Information and Contact Assignment

4.1

400 MAPBGA—Case 17x17 mm, 0.8 mm Pitch

Figure 98

shows the 17

×17 mm i.MX25 production package. The following notes apply to

Figure 98

:

• All dimensions in millimeters.

• Dimensioning and tolerancing per ASME Y14.5M-1994.

• Maximum solder bump diameter measured parallel to datum A.

• Datum A, the seating plane, is determined by the spherical crowns of the solder bumps.

• Parallelism measurement shall exclude any effect of mark on top surface of package.

124



Figure 98.

zzxz

17

×17 i.MX25 Production Package

4.2

Ground, Power, Sense, and Reference Contact Assignments

Case 17x17 mm, 0.8 mm Pitch

Table 100

shows the 17

×17 mm package ground, power, sense, and reference contact assignments.

Table 100. 17

×17 mm Package Ground, Power Sense, and Reference Contact Assignments

Contact Assignment Contact Name

BATT_VDD

FUSE_VDD

MPLL_GND

MPLL_VDD

NGND_ADC

NVCC_ADC

NVCC_CRM

NVCC_CSI

P10

T17

U17

U18

Y13

W13

N14

J13, J14



Table 100. 17

×17 mm Package Ground, Power Sense, and Reference Contact Assignments (continued)

Contact Name

NVCC_DRYICE

NVCC_EMI1

NVCC_EMI2

NVCC_JTAG

NVCC_LCDC

NVCC_MISC

1

W11

G6, G7, G8, G9, H6, H7, H8, J6, J7

G12, G13, G14, G15, H12, H13, H14

U10

P6, P7, R6, R7

N5, N6, N7

L6, L7, L8

R17

Contact Assignment

NVCC_NFC

NVCC_SDIO

OSC24M_GND

OSC24M_VDD

QGND

QVDD

REF

UPLL_GND

UPLL_VDD

USBPHY1_UPLLVDD

USBPHY1_UPLLVSS

M17

N17

USBPHY1_VDDA K16

USBPHY1_VDDA_BIAS K19

W15

W16

A1, A11, A20, B11, C11, D11, E5, E6, E7, E8, E9, E10, E11, E12, E13, E14, E15, E16, F5, F6,

F7, F8, F9, F10, F11, F12, F13, F14, F15, F16, G5, G10, G16, H5, H9, H10, H11, H15, H16, J5,

J9, J10, J11, J15, J16, K1, K2, K3, K4, K5, K8, K9, K10, K11, K13, K14, K15, L5, L9, L10, L11,

L12, L13, L14, L15, M8, M9, M10, M11, M12, M13, M14, M15, N9, N12, N13, N15, N16, P5, P13,

P14, P15, P16, R5, R8, R9, R10, R11, R12, R13, R14, R15, R16, T5, T6, T7, T8, T9, T10, T11,

T12, T13, T14, T15, T16, Y1, Y20

G11, J8, J12, K6, K7, K12, M5, M6, M7, N8, P8, P9

V11

M16

L16

USBPHY1_VSSA L19

USBPHY1_VSSA_BIAS J17

USBPHY2_VDD W18

USBPHY2_VSS W17

1


126



4.3

Signal Contact Assignments—17 x 17 mm, 0.8 mm Pitch

Table 101

lists the 17

×17 mm package i.MX25 signal contact assignments.

Table 101. 17×17 mm Package i.MX25 Signal Contact Assignment

Contact Name

A23

A24

A25

SD0

SD1

SD2

A19

A20

A21

A22

A15

A16

A17

A18

A8

A9

A10

MA10

A11

A12

A13

A14

A4

A5

A6

A7

A0

A1

A2

A3

DDR

DDR

DDR

DDR

DDR

DDR

DDR

DDR

DDR

DDR

DDR

DDR

DDR

DDR

DDR

DDR

DDR

DDR

DDR

DDR

DDR

DDR

DDR

DDR

DDR

DDR

DDR

DDR

DDR

DDR

EMI1

EMI1

EMI1

EMI1

EMI1

EMI1

EMI1

EMI1

EMI1

EMI1

EMI1

EMI1

EMI1

EMI1

EMI2

EMI2

EMI1

EMI2

EMI2

EMI2

EMI2

EMI1

EMI2

EMI2

EMI2

EMI2

EMI2

EMI2

EMI2

EMI2

Contact

Assignment

A6

B7

A7

A12

C13

B13

A4

B6

C7

A5

B4

C6

B5

D7

D20

D17

D19

A3

D18

C18

A2

D16

C20

A19

C19

B19

A18

B17

C17

B18

Power Rail I/O Buffer Type

Direction after

Reset

1

OUTPUT

OUTPUT

OUTPUT

OUTPUT

OUTPUT

OUTPUT

OUTPUT

OUTPUT

OUTPUT

OUTPUT

OUTPUT

INPUT

INPUT

INPUT

OUTPUT

OUTPUT

OUTPUT

OUTPUT

OUTPUT

OUTPUT

OUTPUT

OUTPUT

OUTPUT

OUTPUT

OUTPUT

OUTPUT

OUTPUT

OUTPUT

OUTPUT

OUTPUT

Configuration after Reset

1

Low

Low

Low

Keeper

Keeper

Keeper

Low

Low

Low

Low

Low

Low

Low

Low

Low

Low

Low

Low

Low

Low

Low

Low

Low

Low

Low

Low

Low

Low

Low

Low



Contact Name

SDQS0

SDQS1

EB0

EB1

OE

CS0

CS1

CS2

DQM1

RAS

CAS

SDWE

SDCKE0

SDCKE1

SDCLK

SDCLK_B

SD11

SD12

SD13

SD14

SD15

SDBA1

SDBA0

DQM0

SD3

SD4

SD5

SD6

SD7

SD8

SD9

SD10

Table 101. 17×17 mm Package i.MX25 Signal Contact Assignment (continued)

EMI2

EMI2

EMI1

EMI1

EMI1

EMI1

EMI1

EMI2

EMI1

EMI2

EMI2

EMI2

EMI2

EMI2

EMI2

EMI2

EMI1

EMI1

EMI1

EMI1

EMI1

EMI2

EMI2

EMI1

EMI1

EMI1

EMI1

EMI1

EMI1

EMI1

EMI1

EMI1

Contact

Assignment

D6

C3

D3

B16

B12

B8

B3

C5

D15

C15

B14

A14

C8

C14

C16

A15

A8

A16

B15

C12

C10

C9

A9

D9

A10

B9

D10

B10

D14

D13

A13

D12


DDR

DDR

DDR

DDR

DDR

DDR

DDR

DDR

DDR

DDR

DDR

DDR

DDR

DDR

DDR

DDR

DDR

DDR

DDR

DDR

DDR

DDR

DDR

DDR

DDR

DDR

DDR

DDR

DDR

DDR

DDR

DDR

Direction after

Reset

1

INPUT

INPUT

OUTPUT

OUTPUT

OUTPUT

OUTPUT

OUTPUT

OUTPUT

OUTPUT

OUTPUT

OUTPUT

OUTPUT

OUTPUT

OUTPUT

OUTPUT

OUTPUT

INPUT

INPUT

INPUT

INPUT

INPUT

OUTPUT

OUTPUT

OUTPUT

INPUT

INPUT

INPUT

INPUT

INPUT

INPUT

INPUT

INPUT


1

Keeper

Keeper

High

High

High

High

High

High

High

High

High

High

High

High

Low

High

Keeper

Keeper

Keeper

Keeper

Keeper

Low

Low

High

Keeper

Keeper

Keeper

Keeper

Keeper

Keeper

Keeper

Keeper

128



Contact Name

D5

D4

D3

D2

D1

D0

LD0

2

LD1

2

D9

D8

D7

D6

D13

D12

D11

D10

NFWE_B

NFRE_B

NFALE

NFCLE

NFWP_B

NFRB

D15

D14

CS3

CS4

CS5

NF_CE0

ECB

LBA

BCLK

RW


NFC

NFC

NFC

NFC

NFC

NFC

LCDC

LCDC

NFC

NFC

NFC

NFC

NFC

NFC

NFC

NFC

NFC

NFC

NFC

NFC

NFC

NFC

NFC

NFC

EMI2

EMI1

EMI1

NFC

EMI1

EMI1

EMI1

EMI1

Contact

Assignment

F3

E3

Y7

V8

G1

G2

G3

E1

D1

E2

J3

H1

H2

H3

F1

F2

H4

C2

J2

J1

G4

C1

F4

E4

B2

B1

D8

C4

A17

D5

D4

D2


GPIO

GPIO

GPIO

GPIO

GPIO

GPIO

GPIO

GPIO

GPIO

GPIO

GPIO

GPIO

GPIO

GPIO

GPIO

GPIO

GPIO

GPIO

GPIO

GPIO

GPIO

GPIO

GPIO

GPIO

DDR

GPIO

GPIO

GPIO

GPIO

DDR

DDR

DDR

Direction after

Reset

1

INPUT

INPUT

INPUT

INPUT

INPUT

INPUT

OUTPUT

OUTPUT

INPUT

INPUT

INPUT

INPUT

INPUT

INPUT

INPUT

INPUT

OUTPUT

OUTPUT

OUTPUT

OUTPUT

OUTPUT

INPUT

INPUT

INPUT

OUTPUT

OUTPUT

OUTPUT

OUTPUT

INPUT

OUTPUT

OUTPUT

OUTPUT


1

Keeper

Keeper

Keeper

100 K

Ω Pull-Up

Keeper

Keeper

Keeper

Keeper

Keeper

Keeper

Keeper

Keeper

Keeper

Keeper

Keeper

Low

Low

High

High

High

High

100 K

Ω Pull-Up

High

Low

High

High

High

Low

Low

High

100 K

Ω Pull-Up

Keeper



Contact

Assignment

H18

G20

H19

H20

E20

E18

G19

F20

F18

E19

F19

G18

U5

V3

U4

W2

V4

W3

U7

U6

Y4

Y3

V5

W4

W6

Y5

V6

W5

W7

U8

Y6

V7

Contact Name

LD10

2

LD11

2

LD12

2

LD13

2

LD14

2

LD15

2

HSYNC

2

LD2

2

LD3

2

LD4

2

LD5

2

LD6

2

LD7

2

LD8

2

LD9

2

VSYNC

2

LSCLK

2

OE_ACD

2

CONTRAST

PWM

2

CSI_D2

CSI_D3

CSI_D4

CSI_D5

CSI_D6

CSI_D7

CSI_D8

CSI_D9

CSI_MCLK

2

CSI_VSYNC

2

CSI_HSYNC

2

CSI_PIXCLK

2


Power Rail

GPIO

GPIO

GPIO

GPIO

GPIO

GPIO

GPIO

GPIO

GPIO

GPIO

GPIO

GPIO

GPIO

GPIO

GPIO

GPIO

GPIO

GPIO

GPIO

GPIO

GPIO

GPIO

GPIO

GPIO

GPIO

GPIO

GPIO

GPIO

GPIO

GPIO

GPIO

GPIO

CSI

CSI

CSI

CSI

CSI

CSI

CSI

CSI

LCDC

LCDC

LCDC

LCDC

CSI

CSI

CSI

CSI

LCDC

LCDC

LCDC

LCDC

LCDC

LCDC

LCDC

LCDC

LCDC

LCDC

LCDC

LCDC

LCDC

LCDC

LCDC

LCDC

I/O Buffer Type


1

Low

Low

Low

100 K

Ω Pull-Down

Keeper

Keeper

Keeper

Keeper

Keeper

Keeper

Keeper

Keeper

Low

Keeper

Keeper

Keeper

Low

Low

Low

Low

Low

Low

Low

Low

Low

Low

Low

Low

Low

Low

Low

Low

Direction after

Reset

1

INPUT

INPUT

INPUT

INPUT

OUTPUT

INPUT

INPUT

INPUT

OUTPUT

OUTPUT

OUTPUT

INPUT

INPUT

INPUT

INPUT

INPUT

OUTPUT

OUTPUT

OUTPUT

OUTPUT

OUTPUT

OUTPUT

OUTPUT

OUTPUT

OUTPUT

OUTPUT

OUTPUT

OUTPUT

OUTPUT

OUTPUT

OUTPUT

OUTPUT

130



Contact

Assignment

N2

N1

L1

L2

P3

P2

P1

N3

M19

J20

N4

R1

K20

M20

L20

N20

P4

T1

R3

R2

U2

U1

T3

T2

R4

V2

U3

V1

F17

G17

T4

W1

Contact Name

SD1_CMD

SD1_CLK

SD1_DATA0

SD1_DATA1

SD1_DATA2

SD1_DATA3

KPP_ROW0

KPP_ROW1

KPP_ROW2

KPP_ROW3

KPP_COL0

KPP_COL1

KPP_COL2

KPP_COL3

FEC_MDC

FEC_MDIO

I2C1_CLK

I2C1_DAT

CSPI1_MOSI

CSPI1_MISO

CSPI1_SS0

CSPI1_SS1

CSPI1_SCLK

CSPI1_RDY

UART1_RXD

UART1_TXD

UART1_RTS

UART1_CTS

UART2_RXD

UART2_TXD

UART2_RTS

UART2_CTS


Power Rail

GPIO

GPIO

GPIO

GPIO

GPIO

GPIO

GPIO

GPIO

GPIO

GPIO

GPIO

GPIO

GPIO

GPIO

GPIO

GPIO

GPIO

GPIO

GPIO

GPIO

GPIO

GPIO

GPIO

GPIO

GPIO

GPIO

GPIO

GPIO

GPIO

GPIO

GPIO

GPIO

MISC

MISC

MISC

MISC

MISC

MISC

MISC

MISC

SDIO

SDIO

SDIO

SDIO

SDIO

SDIO

MISC

MISC

MISC

MISC

MISC

MISC

MISC

MISC

MISC

MISC

CSI

CSI

MISC

MISC

MISC

MISC

MISC

MISC

I/O Buffer Type


1

100 K

Ω Pull-Up

100 K

Ω Pull-Up

100 K

Ω Pull-Up

Low

100 K

Ω Pull-Up

100 K

Ω Pull-Up

100 K

Ω Pull-Up

100 K

Ω Pull-Up

100 K

Ω Pull-Up

High

100 K

Ω Pull-Up

High

100 K

Ω Pull-Up

High

100 K

Ω Pull-Up

-

47 K

Ω Pull-Up

High

47 K

Ω Pull-Up

47 K

Ω Pull-Up

47 K

Ω Pull-Up

47 K

Ω Pull-Up

100 K

Ω Pull-Up

100 K

Ω Pull-Up

100 K

Ω Pull-Up

100 K

Ω Pull-Up

100 K

Ω Pull-Up

100 K

Ω Pull-Up

100 K

Ω Pull-Up

100 K

Ω Pull-Up

Low

22 K

Ω Pull-Up

Direction after

Reset

1

INPUT

INPUT

INPUT

INPUT

INPUT

INPUT

OUTPUT

INPUT

INPUT

OUTPUT

INPUT

INPUT

INPUT

INPUT

INPUT

INPUT

INPUT

OUTPUT

INPUT

OUTPUT

INPUT

OUTPUT

INPUT

INPUT

INPUT

INPUT

INPUT

OUTPUT

INPUT

INPUT

INPUT

INPUT



Contact

Assignment

R20

U20

R18

T20

P17

P19

P18

R19

Y19

Y18

N19

N18

L18

K18

J18

L17

V9

W8

U9

K17

V10

Y9

W9

Y8

M4

M3

L4

W10

L3

J4

M2

M1

Contact Name


USBPHY1_DP

USBPHY1_DM

USBPHY1_UID

USBPHY1_RREF

USBPHY2_DM

USBPHY2_DP

GPIO_A

GPIO_B

GPIO_C

GPIO_D

GPIO_E

GPIO_F

EXT_ARMCLK

UPLL_BYPCLK

VSTBY_REQ

VSTBY_ACK

3

FEC_TDATA0

FEC_TDATA1

FEC_TX_EN

FEC_RDATA0

FEC_RDATA1

FEC_RX_DV

FEC_TX_CLK

RTCK

TCK

TMS

TDI

TDO

TRSTB

DE_B

SJC_MOD

USBPHY1_VBUS

Power Rail

GPIO

GPIO

GPIO

GPIO

GPIO

GPIO

GPIO

GPIO

ANALOG

ANALOG

ANALOG

ANALOG

ANALOG

ANALOG

GPIO

GPIO

GPIO

GPIO

GPIO

GPIO

GPIO

GPIO

GPIO

ANALOG

GPIO

GPIO

GPIO

GPIO

GPIO

GPIO

GPIO

GPIO

USBPHY1

USBPHY1

USBPHY1

USBPHY1_BIAS

USBPHY2

USBPHY2

CRM

CRM

CRM

CRM

CRM

CRM

CRM

CRM

CRM

CRM

JTAG

JTAG

JTAG

JTAG

JTAG

JTAG

JTAG

USBPHY1

MISC

MISC

MISC

MISC

MISC

MISC

MISC

JTAG

I/O Buffer Type


1

High

High

Low

100 K

Ω Pull-Down

100 K

Ω Pull-Down

100 K

Ω Pull-Down

100 K

Ω Pull-Down

Low

100 K

Ω Pull-Down

47 K

Ω Pull-Up

47 K

Ω Pull-Up

-

47 K

Ω Pull-Up

47 K

Ω Pull-Up

100 K

Ω Pull-Up

-

-

-

-

-

-

-

-

100 K

Ω Pull-Down

100 K

Ω Pull-Down

-

100 K

Ω Pull-Up

-

-

-

Low

Low

Direction after

Reset

1

INPUT

INPUT

INPUT

INPUT

INPUT

INPUT

OUTPUT

OUTPUT

ANALOG

ANALOG

ANALOG

ANALOG

ANALOG

ANALOG

INPUT

INPUT

INPUT

INPUT

INPUT

INPUT

INPUT

INPUT

INPUT

ANALOG

OUTPUT

OUTPUT

OUTPUT

INPUT

INPUT

INPUT

INPUT

OUTPUT

132




Contact Name

Contact

Assignment


Direction after

Reset

1

POWER_FAIL

RESET_B

POR_B

CLKO

BOOT_MODE0

2

BOOT_MODE1

2

CLK_SEL

TEST_MODE

OSC24M_EXTAL

OSC24M_XTAL

OSC32K_EXTAL

OSC32K_XTAL

TAMPER_A

TAMPER_B

N10

N11

P11

P12

Y15

Y16

Y11

Y10

V19

W20

W19

V18

T19

T18

U19

V20

OSC24M

OSC24M

DRYICE

DRYICE

DRYICE

DRYICE

DRYICE

DRYICE

CRM

CRM

CRM

CRM

CRM

CRM

CRM

CRM

ANALOG

ANALOG

ANALOG

ANALOG

ANALOG

ANALOG

ANALOG

ANALOG

GPIO

GPIO

GPIO

GPIO

GPIO

GPIO

GPIO

GPIO

MESH_C

MESH_D

OSC_BYP

XP

XN

YP

YN

WIPER

Y12

V14

U13

V13

W12

U14

DRYICE

ADC

ADC

ADC

ADC

ADC

ANALOG

ANALOG

ANALOG

ANALOG

ANALOG

ANALOG

ANALOG

ANALOG

ANALOG

ANALOG

ANALOG

ANALOG

INAUX0

INAUX1

U11

V12

ADC

ADC

ANALOG

ANALOG

ANALOG

ANALOG

INAUX2 U12 ADC ANALOG

2

3

1

The state immediately after reset and before ROM firmware or software has executed.

During power-on reset this port acts as input for fuse override signal.

During power-on reset this port acts as output for diagnostic signal.

ANALOG

ANALOG

ANALOG

ANALOG

ANALOG

ANALOG

ANALOG

ANALOG

ANALOG

INPUT

INPUT

INPUT

OUTPUT

INPUT

INPUT

INPUT

INPUT

-

-

-

-

-

-

-

-


1

100 K

Ω Pull-Down

100 K

Ω Pull-Up

100 K

Ω Pull-Up

Low

100 K

Ω Pull-Down

100 K

Ω Pull-Down

100 K

Ω Pull-Down

100 K

Ω Pull-Down

-

-

-

-

-

-

-

-

-



Table 102

lists the 17

×17 mm package i.MX25 no connect contact assignments.

Table 102. 17

×17 mm Package i.MX25 No Connect Contact Assignments

Contact Assignment Signal Name

NC_BGA_B20

NC_BGA_E17

NC_BGA_H17

NC_BGA_J19

NC_BGA_M18

NC_BGA_P20

NC_BGA_U15

NC_BGA_U16

NC_BGA_V15

NC_BGA_V16

NC_BGA_V17

NC_BGA_W14

NC_BGA_Y2

NC_BGA_Y14

NC_BGA_Y17

V15

V16

V17

W14

Y2

Y14

Y17

M18

P20

U15

U16

B20

E17

H17

J19

134



4.4

i.MX25 17x17 Package Ball Map

Table 103

shows the i.MX25 17

×17 package ball map.

Table 103. i.MX25 17

×17 Package Ball Map



Table 103. i.MX25 17

×17 Package Ball Map (continued)

136



Table 103. i.MX25 17




4.5

347 MAPBGA—Case 12 x 12 mm, 0.5 mm Pitch

Figure 99 shows the 12

×12 mm i.MX25 production package. The following notes apply to

Figure 99 :

• All dimensions in millimeters.Dimensioning and tolerancing per ASME Y14.5M-1994.

• Maximum solder ball diameter measured parallel to datum A.

• Datum A, the seating plane, is determined by the spherical crowns of the solder balls.

• Parallelism measurement shall exclude any effect of mark on package’s top surface.

Figure 99. 12

×12 mm i.MX25 Production Package

138



4.6

Ground, Power, Sense, and Reference Contact Assignments

Case 12x12 mm, 0.5 mm Pitch

Table 104 shows the 12

×12 mm package ground, power, sense, and reference contact assignment.

Table 104. 12x12 mm Package Ground, Power Sense, and Reference Contact Assignments

Contact Name Contact Assignment

BATT_VDD

FUSE_VDD

MPLL_GND

MPLL_VDD

NGND_ADC

NVCC_ADC

NVCC_CRM

NVCC_CSI

NVCC_DRYICE

1

AA10

P18

V17

W19

N15

P15

P16

J15, J16

NVCC_EMI1

NVCC_EMI2

NVCC_JTAG

NVCC_LCDC

NVCC_MISC

NVCC_NFC

NVCC_SDIO

OSC24M_GND

OSC24M_VDD

QGND

R14

G8, G9, G10, H8, H9, H10

E15, F15, G15, G16, H15, H16

W10

R8, R9, T8

P7, P8, R7, T7

J7, J8, K7, K8

N19

QVDD

REF

UPLL_GND

UPLL_VDD

USBPHY1_UPLLVDD L21

USBPHY1_UPLLVSS M19

USBPHY1_VDDA K15, K16

USBPHY1_VDDA_BIAS L22

T15

V15

A1, A22, B2, B14, B21, E18, F13, F14, F18, G6, G11, G12, G14, H11, H12, H14, J12, K10, K11, K12,

K13, L7, L8, L9, L10, L11, L12, L13, L14, L15, L16, M7, M8, M9, M10, M11, M12, M13, M14, M15,

M16, N10, N11, N12, N13, P11, P12, R11, R12, R18, T5, T6, T11, T12, T18, V18, V19, W2, W9, Y21,

AA2, AA21, AB1, AB18, AB21, AB22, J11

G7, G13, H7, H13, H18, J18, N7, N8, R10, R15, R16, T9, T10, V10,

AA14

N16

M18



Table 104. 12x12 mm Package Ground, Power Sense, and Reference Contact Assignments (continued)

Contact Name Contact Assignment

USBPHY1_VSSA K19

USBPHY1_VSSA_BIAS K18

USBPHY2_VDD T16

USBPHY2_VSS W16

1


4.7

Signal Contact Assignments—12 x 12 mm, 0.5 mm Pitch

Table 105 lists the 12

×12 mm package i.MX25 signal contact assignments.

Table 105. 12x12 mm Package i.MX25 Signal Contact Assignment

Contact Name

A8

A9

A10

MA10

A11

A12

A13

A14

A15

A16

A17

A18

A19

A4

A5

A6

A7

A0

A1

A2

A3

Contact

Assignment

C21

B22

D21

A4

E19

D19

B5

E17

D6

A5

E6

A6

E7

A21

B19

D18

B20

A20

A19

B18

D17

Power Rail

DDR

DDR

DDR

DDR

DDR

DDR

DDR

DDR

DDR

DDR

DDR

DDR

DDR

DDR

DDR

DDR

DDR

DDR

DDR

DDR

DDR

EMI2

EMI2

EMI1

EMI2

EMI2

EMI2

EMI2

EMI1

EMI1

EMI1

EMI1

EMI1

EMI1

EMI2

EMI2

EMI2

EMI2

EMI2

EMI2

EMI2

EMI2

I/O Buffer Type

Direction after

Reset

1

OUTPUT

OUTPUT

OUTPUT

OUTPUT

OUTPUT

OUTPUT

OUTPUT

OUTPUT

OUTPUT

OUTPUT

OUTPUT

OUTPUT

OUTPUT

OUTPUT

OUTPUT

OUTPUT

OUTPUT

OUTPUT

OUTPUT

OUTPUT

OUTPUT


1

Low

Low

Low

Low

Low

Low

Low

Low

Low

Low

Low

Low

Low

Low

Low

Low

Low

Low

Low

Low

Low

140



Contact Name

DQM0

DQM1

RAS

CAS

SDWE

SDCKE0

SDCKE1

SDCLK

SD10

SD11

SD12

SD13

SD14

SD15

SDBA1

SDBA0

SD6

SD7

SD8

SD9

SD2

SD3

SD4

SD5

A24

A25

SD0

SD1

A20

A21

A22

A23

Table 105. 12x12 mm Package i.MX25 Signal Contact Assignment (continued)

EMI1

EMI1

EMI2

EMI2

EMI2

EMI2

EMI2

EMI2

EMI1

EMI1

EMI1

EMI1

EMI1

EMI1

EMI2

EMI2

EMI1

EMI1

EMI1

EMI1

EMI1

EMI1

EMI1

EMI1

EMI1

EMI1

EMI1

EMI1

EMI1

EMI1

EMI1

EMI1

Contact

Assignment

B15

A16

F16

D13

D11

A9

D15

B16

B8

D9

D16

A17

A11

B10

B9

E11

B11

A12

D10

A10

B12

A14

B13

A15

B7

D8

A13

D12

B6

D7

A7

E9


DDR

DDR

DDR

DDR

DDR

DDR

DDR

DDR

DDR

DDR

DDR

DDR

DDR

DDR

DDR

DDR

DDR

DDR

DDR

DDR

DDR

DDR

DDR

DDR

DDR

DDR

DDR

DDR

DDR

DDR

DDR

DDR

Direction after

Reset

1

OUTPUT

OUTPUT

OUTPUT

OUTPUT

OUTPUT

OUTPUT

OUTPUT

OUTPUT

INPUT

INPUT

INPUT

INPUT

INPUT

INPUT

OUTPUT

OUTPUT

INPUT

INPUT

INPUT

INPUT

INPUT

INPUT

INPUT

INPUT

OUTPUT

OUTPUT

OUTPUT

OUTPUT

OUTPUT

OUTPUT

INPUT

INPUT


1

High

High

High

High

High

High

High

Low

Keeper

Keeper

Keeper

Keeper

Keeper

Keeper

Low

Low

Keeper

Keeper

Keeper

Keeper

Keeper

Keeper

Keeper

Keeper

Low

Low

Low

Low

Low

Low

Keeper

Keeper



142

D11

D10

D9

D8

D15

D14

D13

D12

Contact Name

SDCLK_B

SDQS0

SDQS1

EB0

EB1

OE

CS0

CS1

CS2

CS3

CS4

CS5

NF_CE0

ECB


Contact

Assignment

B17

A18

E5

D2

F4

B1

B4

A3

C2

D4

D14

E14

E12

A2

Power Rail

EMI2

EMI2

EMI1

EMI1

NFC

EMI1

EMI2

EMI2

EMI2

EMI1

EMI1

EMI1

EMI1

EMI1

I/O Buffer Type

DDR

DDR

GPIO

GPIO

GPIO

GPIO

DDR

DDR

DDR

DDR

DDR

DDR

DDR

DDR

Direction after

Reset

1

OUTPUT

INPUT

INPUT

OUTPUT

OUTPUT

OUTPUT

OUTPUT

OUTPUT

OUTPUT

OUTPUT

OUTPUT

OUTPUT

OUTPUT

INPUT


1

High

Keeper

Keeper

High

High

High

High

High

High

High

High

High

High

100 K

Ω Pull-Up

LBA

BCLK

RW

NFWE_B

NFRE_B

NFALE

NFCLE

NFWP_B

NFRB

C1

E2

D1

G4

G5

B3

A8

D5

E1

EMI1

EMI1

EMI1

NFC

NFC

NFC

NFC

NFC

NFC

DDR

DDR

DDR

GPIO

GPIO

GPIO

GPIO

GPIO

GPIO

OUTPUT

OUTPUT

OUTPUT

OUTPUT

OUTPUT

OUTPUT

OUTPUT

OUTPUT

INPUT

K5

H4

H5

G2

K2

K4

J2

J4

NFC

NFC

NFC

NFC

NFC

NFC

NFC

NFC

GPIO

GPIO

GPIO

GPIO

GPIO

GPIO

GPIO

GPIO

INPUT

INPUT

INPUT

INPUT

INPUT

INPUT

INPUT

INPUT

High

Low

High

High

High

Low

Low

High

100 K

Ω Pull-Up

Keeper

Keeper

Keeper

Keeper

-

Keeper

Keeper

Keeper



Contact Name

D7

D6

D5

D4

D3

D2

D1

LD7

2

LD8

2

LD9

2

LD10

2

LD11

2

LD12

2

LD13

2

LD14

2

LD15

2

HSYNC

2

D0

LD0

2

LD1

2

LD2

2

LD3

2

LD4

2

LD5

2

LD6

2

VSYNC

2

LSCLK

2

OE_ACD

2

CONTRAST

PWM

2


LCDC

LCDC

LCDC

LCDC

LCDC

LCDC

LCDC

LCDC

LCDC

LCDC

LCDC

LCDC

LCDC

LCDC

LCDC

LCDC

LCDC

LCDC

LCDC

LCDC

LCDC

LCDC

NFC

NFC

NFC

NFC

NFC

NFC

NFC

NFC

Contact

Assignment

AA4

W5

AB2

AA3

Y2

W4

AB4

W6

AB3

AA5

AB6

AA6

AB5

W7

AB10

W8

AB9

AA9

AB8

AA8

AB7

AA7

H1

G1

F1

F2

L1

K1

J1

H2


GPIO

GPIO

GPIO

GPIO

GPIO

GPIO

GPIO

GPIO

GPIO

GPIO

GPIO

GPIO

GPIO

GPIO

GPIO

GPIO

GPIO

GPIO

GPIO

GPIO

GPIO

GPIO

GPIO

GPIO

GPIO

GPIO

GPIO

GPIO

GPIO

GPIO

Direction after

Reset

1

OUTPUT

OUTPUT

OUTPUT

OUTPUT

OUTPUT

OUTPUT

OUTPUT

OUTPUT

OUTPUT

OUTPUT

OUTPUT

OUTPUT

OUTPUT

INPUT

OUTPUT

OUTPUT

OUTPUT

OUTPUT

OUTPUT

OUTPUT

OUTPUT

OUTPUT

INPUT

INPUT

INPUT

INPUT

INPUT

INPUT

INPUT

INPUT


1

Low

Low

Low

Low

Low

Low

Low

Low

Low

Low

Low

Low

Low

100 K

Ω Pull-Down

Low

Low

Low

Low

Low

Low

Low

Low

Keeper

Keeper

Keeper

Keeper

Keeper

Keeper

Keeper

Keeper

CSI_D2 C22 CSI GPIO INPUT Keeper



144


Contact Name

CSI_D3

CSI_D4

CSI_D5

CSI_D6

CSI_D7

CSI_D8

CSI_D9

CSI_MCLK

2

CSI_VSYNC

2

CSI_HSYNC

2

CSI_PIXCLK

2

I2C1_CLK

Contact

Assignment

F21

E22

H19

F22

F19

E21

G19

D22

G21

G22

J19

H22

Power Rail

CSI

CSI

CSI

CSI

CSI

CSI

CSI

CSI

CSI

CSI

CSI

CSI

I/O Buffer Type

GPIO

GPIO

GPIO

GPIO

GPIO

GPIO

GPIO

GPIO

GPIO

GPIO

GPIO

GPIO

Direction after

Reset

1

INPUT

INPUT

INPUT

INPUT

INPUT

INPUT

INPUT

OUTPUT

INPUT

INPUT

INPUT

INPUT


1

Keeper

Keeper

Keeper

Keeper

Keeper

Keeper

Keeper

Low

Keeper

Keeper

Keeper

100 K

Ω Pull-Up

I2C1_DAT

CSPI1_MOSI

H21

AA1

CSI

MISC

GPIO

GPIO

INPUT

INPUT

100 K

Ω Pull-Up

100 K

Ω Pull-Up

CSPI1_MISO

CSPI1_SS0

V4

V2

MISC

MISC

GPIO

GPIO

OUTPUT

INPUT

CSPI1_SS1

CSPI1_SCLK

CSPI1_RDY

UART1_RXD

UART1_TXD

UART1_RTS

UART1_CTS

UART2_RXD

UART2_TXD

U4

Y1

U5

U2

V6

W1

R5

V1

T4

MISC

MISC

MISC

MISC

MISC

MISC

MISC

MISC

MISC

GPIO

GPIO

GPIO

GPIO

GPIO

GPIO

GPIO

GPIO

GPIO

INPUT

INPUT

INPUT

INPUT

OUTPUT

INPUT

OUTPUT

INPUT

OUTPUT

Low

100 K

Ω Pull-Up

100 K

Ω Pull-Up

100 K

Ω Pull-Up

100 K

Ω Pull-Up

100 K

Ω Pull-Up

High

100 K

Ω Pull-Up

High

100 K

Ω Pull-Up

High




Contact Name

UART2_RTS

Contact

Assignment

T2

Power Rail

MISC

I/O Buffer Type

GPIO

Direction after

Reset

1

INPUT


1

100 K

Ω Pull-Up

UART2_CTS

SD1_CMD

P5

N22

MISC

SDIO

GPIO

GPIO

INPUT

INPUT

SD1_CLK

SD1_DATA0

SD1_DATA1

SD1_DATA2

SD1_DATA3

KPP_ROW0

KPP_ROW1

KPP_ROW2

KPP_ROW3

KPP_COL0

KPP_COL1

KPP_COL2

KPP_COL3

FEC_MDC

FEC_MDIO

FEC_TDATA0

FEC_TDATA1

FEC_TX_EN

N21

P22

R22

M22

M21

R2

R4

U1

P4

T1

N5

P2

N4

P1

M2

L2

M1

R1

SDIO

SDIO

SDIO

SDIO

SDIO

MISC

MISC

MISC

MISC

MISC

MISC

MISC

MISC

MISC

MISC

MISC

MISC

MISC

GPIO

GPIO

GPIO

GPIO

GPIO

GPIO

GPIO

GPIO

GPIO

GPIO

GPIO

GPIO

GPIO

GPIO

GPIO

GPIO

GPIO

GPIO

OUTPUT

INPUT

INPUT

INPUT

INPUT

INPUT

INPUT

INPUT

INPUT

INPUT

INPUT

INPUT

INPUT

OUTPUT

INPUT

OUTPUT

OUTPUT

OUTPUT

-

47 K

Ω Pull-Up

High

47 K

Ω Pull-Up

47 K

Ω Pull-Up

47 K

Ω Pull-Up

47 K

Ω Pull-Up

100 K

Ω Pull-Up

100 K

Ω Pull-Up

100 K

Ω Pull-Up

100 K

Ω Pull-Up

100 K

Ω Pull-Up

100 K

Ω Pull-Up

100 K

Ω Pull-Up

100 K

Ω Pull-Up

Low

22 K

Ω Pull-Up

High

High

Low




Contact Name

FEC_RDATA0

Contact

Assignment

M4

Power Rail

MISC

I/O Buffer Type

GPIO

Direction after

Reset

1

INPUT


1

100 K

Ω Pull-Down

FEC_RDATA1

FEC_RX_DV

FEC_TX_CLK

N2

L5

N1

MISC

MISC

MISC

GPIO

GPIO

GPIO

INPUT

INPUT

INPUT

100 K

Ω Pull-Down

100 K

Ω Pull-Down

100 K

Ω Pull-Down

RTCK

TCK

W13

AA13

JTAG

JTAG

GPIO

GPIO

OUTPUT

INPUT

TMS

TDI

TDO

TRSTB

DE_B

SJC_MOD

USBPHY1_VBUS

USBPHY1_DP

USBPHY1_DM

USBPHY1_UID

USBPHY1_RREF

USBPHY2_DM

USBPHY2_DP

GPIO_A

GPIO_B

GPIO_C

GPIO_D

AA12

W12

AA11

AB14

W11

AB11

L19

W18

W17

T22

P21

K22

K21

J21

J22

U22

P19

JTAG

JTAG

JTAG

JTAG

JTAG

JTAG

USBPHY1

USBPHY1

USBPHY1

USBPHY1

USBPHY1_BIAS

USBPHY2

USBPHY2

CRM

CRM

CRM

CRM

GPIO

GPIO

GPIO

GPIO

GPIO

GPIO

ANALOG

ANALOG

ANALOG

ANALOG

ANALOG

ANALOG

ANALOG

GPIO

GPIO

GPIO

GPIO

INPUT

INPUT

INPUT

INPUT

INPUT

INPUT

ANALOG

ANALOG

ANALOG

ANALOG

ANALOG

ANALOG

ANALOG

INPUT

INPUT

INPUT

INPUT

Low

100 K

Ω Pull-Down

47 K

Ω Pull-Up

47 K

Ω Pull-Up

-

47 K

Ω Pull-Up

47 K

Ω Pull-Up

100 K

Ω Pull-Up

-

-

-

-

-

-

-

-

100 K

Ω Pull-Down

100 K

Ω Pull-Down

-

146



Contact Name

GPIO_E


Contact

Assignment

R21

Power Rail

CRM

I/O Buffer Type

GPIO

Direction after

Reset

1

INPUT


1

100 K

Ω Pull-Up

GPIO_F

EXT_ARMCLK

UPLL_BYPCLK

VSTBY_REQ

VSTBY_ACK

3

POWER_FAIL

RESET_B

POR_B

CLKO

BOOT_MODE0

2

BOOT_MODE1

2

CLK_SEL

TEST_MODE

OSC24M_EXTAL

OSC24M_XTAL

OSC32K_EXTAL

OSC32K_XTAL

TAMPER_A

TAMPER_B

MESH_C

MESH_D

OSC_BYP

XP

XN

YP

YN

R19

V22

U21

T21

W22

T19

U19

V21

Y22

AA22

W21

AA20

AA19

AB19

AB20

AB13

AB12

V11

V13

T13

R13

AB15

AA18

AA16

AB17

W15

CRM

CRM

CRM

CRM

CRM

CRM

CRM

CRM

CRM

CRM

CRM

CRM

CRM

OSC24M

OSC24M

DRYICE

DRYICE

DRYICE

DRYICE

DRYICE

DRYICE

DRYICE

ADC

ADC

ADC

ADC

GPIO

GPIO

GPIO

GPIO

GPIO

GPIO

GPIO

GPIO

GPIO

GPIO

GPIO

GPIO

GPIO

ANALOG

ANALOG

ANALOG

ANALOG

ANALOG

ANALOG

ANALOG

ANALOG

ANALOG

ANALOG

ANALOG

ANALOG

ANALOG

INPUT

INPUT

INPUT

OUTPUT

OUTPUT

INPUT

INPUT

INPUT

OUTPUT

INPUT

INPUT

INPUT

INPUT

ANALOG

ANALOG

ANALOG

ANALOG

ANALOG

ANALOG

ANALOG

ANALOG

ANALOG

ANALOG

ANALOG

ANALOG

ANALOG

Low

100 K

Ω Pull-Down

100 K

Ω Pull-Down

100 K

Ω Pull-Down

100 K

Ω Pull-Down

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

Low

Low

100 K

Ω Pull-Down

100 K

Ω Pull-Up

100 K

Ω Pull-Up




Contact Name

Contact

Assignment


Direction after

Reset

1

WIPER

INAUX0

AA17

AA15

ADC

ADC

ANALOG

ANALOG

ANALOG

ANALOG

INAUX1 W14 ADC ANALOG ANALOG

INAUX2 AB16 ADC ANALOG

2

3

1

The state immediately after reset and before ROM firmware or software has executed.

During power-on reset this port acts as input for fuse override signal.

During power-on reset this port acts as output for diagnostic signal.

ANALOG


1

-

-

-

-

Table 106 lists the 12

×12 mm package i.MX25 no connect contact assignments.

Table 106. 12

×12 mm Package i.MX25 No Connect Contact Assignments

Contact Assignment Signal Name

NC_BGA_E4

NC_BGA_L4

E4

L4

4.8

i.MX25 12x12 Package Ball Map

Table 107 shows the i.MX25 12

×12 package ball map.

Table 107. i.MX25 12

×12 Package Ball Map

148



Table 107. i.MX25 12




Table 107. i.MX25 12


150



5 Revision History

Table 108 summarizes revisions to this document.

Table 108. Revision History

Rev.

Number

Date Substantive Change(s)

Rev. 10 05/2013 • Updated DDR timing parameters in

– Table 47, “SDRAM Self-Refresh Cycle Timing Parameters”

–

Table 49, “Mobile DDR SDRAM Read Cycle Timing Parameters”

–

Table 51, “tlS, tlH Derating Values for DDR2-400, DDR2-533”

•

Table 101 , “17×17 mm Package i.MX25 Signal Contact Assignment”

: Updated configuration after reset for contact D11 to “100 K

Ω Pull-Up”

Rev. 9 06/2012 • In

Table 1, "Ordering Information," on page 3

, removed exclamation marks from table rows and also removed table footnote.

• In

Table 3, "i.MX25 Digital and Analog Modules," on page 6 , modified description of block mnemonic,

SIM.

• Updated

Section 3.2.1, “Power-Up Sequence.”

• Updated

Section 3.2.3, “SRTC DryIce Power-Up/Down Sequence.”

• In

Figure 38 and Table 56

:

—Removed “_B” and added an overbar to signal names, CSx_B, RW_B, OE_B, EBy_B, LBA_B,

ECB_B, and DTACK_B

—Changed CSx and CSy to CS[x] and CS[y], respectively

• In

Table 57, "WEIM Asynchronous Timing Parameters Relative to Chip Select Table," on page 76

:

—Changed WE and WEA to RW and RWA, respectively, for reference number, WE33

—Changed WE and WEN to RW and RWN, respectively, for reference number, WE34

—Changed RLBA, RLBN, and ADH to LBA, LBN, and LAH, respectively, for reference number, WE35A

—Changed RBEA to EBRA for reference number, WE37

—Changed RBEN to EBRN for reference number, WE38

—Changed WCSA to CSA for reference numbers, WE41 and WE41A

—Changed WLBA, WLBN, and ADH to LBA, LBN, and LAH, respectively, for reference number, WE41A

—Changed WBEA and WBEN to EBWA and EBWN, respectively, for reference numbers, WE45 and

WE46

• Updated the note after

Table 57

.

• In

Table 99, "USB Timing Specification in Parallel Mode," on page 124 , swapped the values of Min and

Max columns for IDs, US15 and US16.

Rev. 8 01/2011 • In Table 27, "AC Parameters for SDRAM I/O," on page 36 , the frequency specification has been updated to 133 MHz.

• In Table 28, "AC Parameters for SDRAM pbijtov18_33_ddr_clk I/O," on page 37 , the frequency

specification has been updated to 133 MHz.



Table 108. Revision History (continued)

Rev.

Number

Date Substantive Change(s)

Rev. 7 12/2010 • Updated the first paragraph of

Section 3.2.3, “SRTC DryIce Power-Up/Down Sequence.”

• Updated

Table 4, "Signal Considerations," on page 9 for NVCC_DRYICE signal.

• Updated the third note for

Table 6, "DC Operating Conditions," on page 11.

• Added Table 9, "Recommended External Crystal Specifications," on page 13 .

• Added Table 10, "Recommended External Reference Clock Specifications," on page 13 .

• Added a note for the line NVCC_DRYICE in

Table 100, "17

×17 mm Package Ground, Power Sense, and

Reference Contact Assignments," on page 125 .

• Updated

Table 101, "17×17 mm Package i.MX25 Signal Contact Assignment," on page 127 .

• Added a note for the line NVCC_DRYICE in Table 104, "12x12 mm Package Ground, Power Sense, and

Reference Contact Assignments," on page 139 .

• Removed records for UPLL_BYPCLK, USBPHY2_DP, USBPHY1RREF, USBPHY1_DM,

USBPHY1_DP, USBPHY1_UID, USBPHY1_VBUS, and USBPHY2_DM contacts from Table 104,

"12x12 mm Package Ground, Power Sense, and Reference Contact Assignments," on page 139 .

• Updated Table 105, "12x12 mm Package i.MX25 Signal Contact Assignment," on page 140 .

Rev. 6

09/2010 • Added Section 3.2.3, “SRTC DryIce Power-Up/Down Sequence.”

Rev. 5 08/2010 • Updated

Table 56, "WEIM Bus Timing Parameters," on page 69

to include new row for WE19.

• Updated

Table 6, "DC Operating Conditions," on page 11 to include Min and Max values of FUSE_VDD.


Table 1 , “Ordering Information,”

to include new part numbers.




• Added Table 2 , “ i.MX25 Parts Functional Differences.”

• Added Section 3.3, “Power Characteristics.”

• Added Section 4.5, “347 MAPBGA—Case 12 x 12 mm, 0.5 mm Pitch.”

• Added Section 4.6, “Ground, Power, Sense, and Reference Contact Assignments Case 12x12 mm, 0.5 mm Pitch.”

• Added Section 4.7, “Signal Contact Assignments—12 x 12 mm, 0.5 mm Pitch

.

• Added Section 4.8, “i.MX25 12x12 Package Ball Map.”





Table 1, “Ordering Information,”


• Updated DRYICE description in

Table 3 , “i.MX25 Digital and Analog Modules.”

• Updated REF signal description in Table 4 , “Signal Considerations.”

• Updated ESD damage immunity values in Table 5 , “DC Absolute Maximum Ratings.”

• Updated values in Table 13 , “i.MX25 Power Mode Current Consumption.”

• Added a note on timing in Section 3.2.1, “Power-Up Sequence.”

• Added Table 14 , “iMX25 Reduced Power Mode Current Consumption.”

• Updated

Table 55 , “NFC Timing Parameters.”

• Updated values in Table 56 , “WEIM Bus Timing Parameters.

• Updated

Table 85 , “Touchscreen ADC Electrical Specifications.”

Rev. 0 6/2009 Initial release.

152



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