Toshiba T3200 - Maintenance Manual

1.1
GENERAL
Toshiba Personal Computer T3200 (hereinafter referred to as
T3200) is a portable personal computer which is compatible with
IBM PC/AT si tuated at higher rank of portable computer than
Toshiba T3l00. Hardware of the T3200, a lot of IC chips are
C-MOS type so that the power consumption is very little and Gate
Array chips are applied so that it is very compact and light
weight.
The T3200 is composed of as follows:
System PCB (Printed curcuit board)
Hard disk control PCB
3.5-inch floppy disk drive
3.5-inch hard disk drive
Plasma display
Keyboard
Power supply unit
FIGURE 1-1 T3200 Personal Computer
1-1
A
3.5-inch
Floppy
disk
drive
(FDD)
is
double-sided,
double-density,
double-track with storage capacity of 720
kilobytes (formatted). A 3.5-inch hard disk drive (HDD) with
storage capacity of 40 megabytes (formatted) is the second
external storage device. The plasma display with pixels of 720
in columns and 400 in rows.
The keyboard has 85 keys. For most applications it can be used
exactly like a standard typewriter keyboard.
The power supply unit provides +5 Vdc and +12 Vdc power to every
component in the system unit, including the option cards. For
the plasma display, this unit regulates +205 Vdc power. This
unit has a ventilation fan, driven by +12 Vdc. The fan enhances
the reliability and durability of the T3200 system unit.
The T3200 provided connecting to the optional devices at the
rear panel of the system. There are three connectors such as a
parallel printer (or an external floppy disk drive), an RGB
direct drive CRT display and an RS-232C device.
The connector for a parallel printer can be used to connect an
external FDD unit by changing the A-B-PRT switch setting.
1-2
1.2 SYSTEM PCB
System PCB is composed of the following devices:
o
Central processor: CPU (80286-12)
o
Numeric data processor: NPU (80287, optional)
o
Memory
RAM
ROM (Main BIOS)
.... .
(AGS BIOS)
..... .
Video RAM ..........•
(12 MHz/6 MHz»
1 Mbyte standard
3 Mbytes (option card)
--- "LIM" standard
64 Kbytes (16 bits)
32 Kbytes (8 bits)
256 Kbytes
o
System suP?ort elements
Direct memory access: DMA (82C37)
Programmable interrupt controller: PIC (82C59)
Programmable interval timer: PIT (82C54)
Real time clock: RTC (MC1468l8)
o
Floppy disk controller: FDC (TC8565F)
o
Keyboard controller: KBC (u8042) x 2
o
Display controller: PEGA2, AGS G.A.
o
Gate array
Bus driver
Memory mapper
DMA driver
I/O controller
LIM
AGS (Advanced graphics subsystem)
1-3
1.2.1 DIP switches
The system has DIP switches which are located at the rear panel.
The following table shows function of the DIP switches.
TABLE 1-1 DIP Switch Functions
DIP
Switch
1
Setting
Description
ON
Auto-Switched display mode
OFF
IBM EGA full compatible
ON
PRT port used both for input and output
OFF
PRT port only for output
ON
Communications port as CH2
OFF
Communications port as CH 1
ON
Double font in plasma for TEXT
OFF
Single font in plasma for TEXT
ON
Disable CRTC for EXT.CRTC
OFF
Enable internal CRTC (normal)
ON
North European Font to display
OFF
Other Fonts (Normal)
2
3
4
5
6
7to 10
(Defined as follows)
Monitor in use
7
8
9
10
Monochrome
OFF
OFF
OFF
OFF
Standard RGB
(40 column mode is default)
ON
OFF
OFF
ON
Standard RGB
(80 column mode is default)
OFF
OFF
OFF
ON
Enhanced RGB
(200 line or emulation of standard RGB is
default)
ON
ON
ON
OFF
OFF
ON
ON
OFF
Enhanced RGB
(350 line, true enhanced operation is default)
1-4
1.2.2 Jumper straps
The system has six jumper straps (PJ 2) which are located on the
keyboard control PCB.
Usually the six jumper straps are all open.
The following figure shows location of the jumper straps.
MiwtfU
I
PJ 2
I
FIGURE 1-2 Jumper Strap Locations
The following table shows function of the jumper straps.
TABLE 1-2 Jumper Strap Functions
Function
Name
1-2
Not used
3-4
2HD FDD type
Open ... 1.6 Mbytes
Short ... 2.0 Mbytes
5-6
Internal FDD numbers
Open ... OneFDD
Short ... Two FDD/s
7-8
FDD type
Open ... 2DD
Short ... 2HD (1.6 Mbytes/2.0 Mbytes)
9-10
Standard memory size
Open ... 640 kbytes
Short ... 512 kbytes
11-12 Used 3M B memory card
mode (Option)
Open ... Used as the extended memory and
the expanded memory.
Short ... Used as the only expanded
memory.
1-5
1.3 3.5-INCB FLOPPY DISK DRIVE
The
floppy disk drive
(FDD)
used
in
the T3200
is
high
performance, high reliable, slim sized FDD for 3.5-inch floppy
disks with recording capacity of 720 kbytes (formatted) in
double-sided, double density and 135 tracks per inch operation.
The specifications are as following table.
FIGURE 1-3 3.5-inch FDD
TABLE 1-3 3.5-inch Floppy Disk Drive Specifications
Item
Specifications
Storage Capacity (kilobytes)
Number of Heads
Number of Track per Side
Track to Track Access (milliseconds)
Head Settling Time (milliseconds)
Track Density (tracks per inch)
Motor Start-up Time (milliseconds)
Data Transfer Rate (kilobits per second)
Rotational Speed (revolutions per minute)
Recording Method
1-6
1000 (unformatted)
720 (formatted)
2
80
3
15
135
500
250
300
MFM (Modified frequency
modulation)
1.4 3.5-IRCH HARD DISK DRIVE
The hard disk drive (HDD) is random access storage, having
recording capacity of 40 Mbytes (formatted). This is equipped
with the storage media of non-removable 3.5-inch magnetic disks
and mini-winchester type magnetic heads.
The specifications are as following table.
FIGURE 1-4 3.5-inch Hard Disk Drive
TABLE 1-4 3.5-inch Hard Disk Drive Specifications
Item
Specifications
Storage Capacity (megabytes)
Number of Heads
Number of Cylinders
Number of Tracks (tracks per cylinder)
(minimum)
Access Time (milliseconds)
(average)
(maximum)
Recording Density (bits per inch)
Track Density (tracks per inch)
Rotational Speed (revolutions per minute)
Recording Method
1-7
51.24 (unformatted)
40.30 (formatted)
8
615
8
8
38
85
14845
834
3600
MFM (Modefied Frequency
Modulation)
1.5 HARD DISK CONTROL PCB
Hard disk control PCB (HOC) is accompanied by hard disk drive
(HOD) and connects to the system PCB through a cable. This HOC
can interface the HDD to the system PCB.
The specifications are as following table.
FIGURE 1-5 Hard Disk Control PCB
TABLE 1-5 Hard Disk Control PCB Specifications
Item
Specifications
MFM (Modefied Frequency
Modulation)
Encoding method
Data Transfer Rate (megabits per second) maximum
Write Precompensation time (nanoseconds)
Sectoring
1-8
5
12
Soft
1.5.1 Jumper straps
The Hard disk control PCB has jumper straps which are PJ 3, PJ 4
and PJ 5.
Functions of the jumper straps are as follows.
(1)
PJ 3
Not used.
(2) PJ 4
This jumper straps select recording method of the hard
disk control PCB.
The following table shows function.
TABLE 1-6 PJ 4 Jumper Strap Functions
No.
1-2
3-4
( 3)
Function
Status
Short
Open
MFM method
PJ 5
This jumper straps select the delay time of the hard
disk control PCB.
Usually delay time is selected as 20 ns.
The following table shows function of the jumper
straps.
TABLE 1-7 PJ 5 Jumper Strap Functions
No.
Delay time select
1-2
10 ns
3-4
15 ns
5-6
20 ns
7-8
25 ns
9-10
30 ns
1-9
1 .6 KEYBOARD
The keyboard is mounted on the system and has 85 keys. These
consist of 54 standard keys, 10 function keys, 17 cursor keys,
14 functional keypads, and Fn key.
The keyboard is just a key matrix built up by the above keys.
The keyboard is connected to the keyboard controller on the
system PCB through a 22-pin flat cable.
FIGURE 1-6 Keyboard
1-10
1. 7 PLASMA DISPLAY
The plasma display is a graphics type display unit composed of
the display panel and driver circui ts. This receives vertical
and horizontal sync signals, four bit data signals, and shift
clock for data transmission. All these signals are TTL level
compatible. The specifications are as following table.
The plasma display has 4-level of gray display.
The plasma display be adjusted by contrast/brightness
volume.
FIGURE 1-7 Plasma Display
TABLE 1-8 Plasma Display Specifications
Item
Dot Number (dots)
Dot Dimension (mm)
Dot Pitch (mm)
Display Area (mm)
Contrast
Color
Power Requirement
MTBF
Specification
720 x 400
0.18 (V) x 0.16 (H)
0.36 (V) x 0.30 (H)
144(V)x216(H)
1 : 10
Neon - orange
+ 5V ± 0.5V, 0.6A
+ 205 ± 5V, 170mA
+ SV ± O.SV, 60mA
20000 hours
1-11
control
1.8 POWER SUPPLY UNIT
The power supply unit supplies dc 5, 12, -12 and 205 volts to
all the components in the system.
The power supply unit is housed in the system and is designed to
support the following:
1)
2)
3)
4)
5)
6)
7)
System PCB
3.5-inch Floppy disk drive
3.5-inch Hard disk drive
Hard disk control PCB
Keyboard unit
Plasma display
Option PCB's
The power supply unit includes the input line filter, line fuse,
cooling fan, power conversion circuitry and connectors.
Input rating is as follows.
AC 100, 115/220, 240 Volts, 60W (lOOW max.)
Output rating is as following table.
FIGURE 1-8 Power Supply Unit
TABLE 1-9 Power Supply Unit Output Rating
FUNCTION
SYSTEM PCB
SYSTEM PCB
SYSTEM PCB
PLASMA DISPLAY
PLASMA DISPLAY
DC VOLTAGE
5V
12 V
-12 V
205 V
SV
1-12
REGULATION
TOLERANCE
:t5%
±5%
+ 10 %, - 20 %
200 to 210 V
±10%
MAX.
CURRENT
6.5A
2.6A
0.3A
170mA
60mA
2.1 GENERAL
These problem isolation procedures are used to isolate defective
FRUs (field replaceable units) to be replaced.
FRUs consist of
the following:
1.
2.
3.
4.
5.
6.
Power supply unit
System PCB
FDD
HDD and HOC
Keyboard
Plasma display
See PART 4 for detailed replacement procedures
Test program operations are described in PART 3.
instructions.
The following items are necessary for carrying out the problem
isolation procedures.
1.
2.
3.
4.
5.
6.
T3200 Diagnostics disk
Flatbladed screwdriver
Work disk (for FDD testing)
Cleaning disk kit (for FDD testing)
Multimeter
Printer port LED
The problem isolation flowchart described in part 2.2 can
used to determine the necessary isolation procedures to
followed when there is a problem with the T3200.
be
be
2.2 PROBLEM ISOLATION FLOWCHART
This flowchart is used as a guide for determining which FRU is
defecti ve.
Please conf irm the following before performing the
flowchart procedures.
1.
2.
No disk is in the FDD.
All optional equipment is disconnected.
See next page.
2-1
Turn the POWER switch off.
Perform power supply problem
">-;,.;.No"--___ I isolation procedures in part 2.3.
Yes
=>-----l.1
No
Perform Plasma Display problem
isolation procedures in part 2.8.
No
Perform system PCB problem
isolation procedures in part 2.4.
~_ _. I
:>-.:..;.::....---1.1
Is the C> displayed
on the screen ?
Perform system PCB problem
isolation procedures in part 2.4.
No
~":':'="'---l.1
Perform HOD problem isolation
procedures 1n part 2.4.
FIGURE 2-1 Problem Isolation Flowchart
2-2
Insert the diagnostics disk into the FDD.
Perform FDD problem isolation
in part 2.5.
~_N...,;.o_..., procedures
After confirming which diagnostic
test caused an error to be
Yes
--:>-----l., genera ted. Perform the re 1evant
problem isolation procedures, as
indicated below.
System normal
1.
If an error is generated on the system test, memory test,
display test and real timer test, go to system PCB isolation
procedures in part 2.4.
2.
If an error is generated on the hard disk test,
isolation procedures in part 2.6.
3.
If an error is generated on the keyboard
keyboard isolation procedures in part 2.8.
4.
If an error is generated on the floppy disk test, go to FDD
isolation procedures in part 2.5.
2-3
go to HDD
test,
go
to
2.3 POWER SUPPLY UNIT ISOLATION PROCEDURES
This section describes how to determine whether the power supply
PCB is defective or not.
The procedures below are outlined in
the following pages.
They should be performed in the order
indicated.
PROCEDURE 1:
Power Indicator Check
PROCEDURE 2:
Connector Check
PROCEDURE 3:
Output Voltage Check
PROCEDURE 4:
Power Supply Unit Voltage Adjustment
PROCEDURE 5:
Power Supply Unit Replacement
2-4
PROCEDURE 1
Power Indicator Check
1.
Turn the POWER switch on.
2.
If the POWER indicator lights, go to PROCEDURE 3.
If the indicator doesn't light, replace the ac cord; if it
lights, the previous ac cord was defective. If the indicator
doesn't light yet, go to PROCEDURE 2.
Disk in Use
FIGURE 2-2
DO
0
DOD
Left Right
CRT
Caps Num Scroll
Lock Lock Lock
POWER Indicator Check
2-5
PROCEDURE 2
Connector Check
1.
Turn the POWER switch off and unplug the ac cord.
2.
Remove the top cover.
3.
If the two system PCB connectors (PJ 7 and 8) are connected
properly, go to PROCEDURE 3; if they are not connected
properly, reconnect them.
(Refer to part 4.2.)
FIGURE 2-3 Power Supply Unit Connectors
2-6
PROCEDURE 3
Output Voltage Check
1.
Disconnect the three power cables
system PCB) from the system PCB.
(for
plasma
display and
2.
Plug the ac cord, then turn the POWER switch on.
3.
Use a multimeter to confirm that the output voltages for the
three power supply PCB connectors conform to the values
given in the following table.
4.
If the voltages conform to the values given in the table,
the power supply PCB is normal. System PCB is probably
defecti ve, go to system PCB isolation procedures in part
2.4.
5.
If the voltages do not conform to those given in the table,
ao to PROCEDURE 4.
TABLE 2-1 Power Supply Unit Output Voltages
CONNECTOR
PJ 003
PJ 004
PJ 005
VOLTAGE (Vdc)
PIN NUMBER
+ lead
-lead
Normal
Min
Max
1
3,4
+ 5
+ 4.75
+ 5.25
2
3,4
+ 5
+ 4.75
+ 5.25
1
2,4
+ 12
+ 11.4
+ 12.6
3
2,4
- 12
- 13.2
- 9.6
1
2
+ 205
+ 200
+ 210
3
2
+ 5
+ 4.5
+ 5.5
2-7
PROCEDURE 4
Power Supply Unit Voltage Adjustment
1.
Turn the POWER switch off and unplug the ac cord.
2.
Remove the power supply unit.
3.
Remove
unit.
4.
Set the dummy load resister (1.3 kiloohm, 35
plasma display power connector (l-pin to 2-pin).
5.
Plug the ac cord
POWER switch on.
6.
Use a multimeter to confirm that the output voltages for the
plasma display power connector conform to the volues given
in the following table.
the
power
supply uni t
(Refer to part 4.9.)
cover
from
the
to the power supply uni t,
power
W)
then
supply
to
the
turn
the
TABLE 2-2 VRl Adjustment
CONNECTOR
PJ 005
PIN NUMBER
VOLTAGE (Vdc)
+ lead
-lead
Min
Max
1
2
+ 201
+ 202
7.
If the voltage does not conform to that given in the table,
after turn the VR2 to the right, then adjust the VRl on the
power supply PCB by Phillips screwdriver.
8.
Turn the POWER switch off,
resister (1.3 kiloohm, 35 W).
9.
Set the dummy load resister (21 kiloohm, 2.5
prasma display power connector (l-pin to 2-pin).
then
remove
the
dummy
W)
to
load
the
10. Adjust the VR2 on the systen PCB that the output voltages
for the plasma display power connector conform to the values
given in the following table.
TABLE 2-3 VR2 Adjustment
CONNECTOR
PJ 005
PIN NUMBER
VOLTAGE (Vdc)
+ lead
-lead
Min
Max
1
2
+ 208
+ 209
2-8
PROCEDURE 5
Power Supply unit Replacement
1.
Turn the POWER switch off and unplug the ac cord.
2.
Replace the power supply unit.
3.
If normal operation is restored after replacing the power
supply unit, the previous power supply unit was defective.
4.
If normal operation is not restored, another FRU is probably
defective.
The defective unit must be
isolated and
replaced.
2-9
(Refer to part 4.9.)
2.4 SYSTEM PCB ISOLATION PROCEDURES
This section describes how to determine whether the system PCB
is defective or not.
The procedures below are outlined in the
fol1owinq pages.
They should be performed in the order
indicated.
PROCEDURE 1:
Message Check
PROCEDURE 2:
Printer Port LED Check
PROCEDURE 3:
Test Program Execution
PROCEDURE 4:
System PCB Replacement
NOTE: Before ca rrying out any of these procedures,
that there is not a floppy disk in the FDD.
2-10
make
sure
PROCEDURE 1
Message Check
1.
Turn the POWER switch on.
2.
If the system is loaded, go to PROCEDURE 3.
3.
If the following message is displayed on the screen, press
the Fl key. Execute the setup. (Refer to OWNER'S MANUAL in
PART 6.)
*** Error in CMOS. Bad battery ***
Check system Then. press [Fl] key ......
*** Error in CMOS. Bad check sum ***
Check system Then. press [Fl] key .•••.•
** Error in CMOS. Bad configuration **
Check system Then. press [Fl] key ..•.•
a
*** Error in CMOS. Bad memory size ***
Check system Then. press [Fl] key .•••••
** Error in CMOS. Bad time function **
Check system Then. press [Fl] key ......
4.
If the following message is displayed on the screen, go to
HOD isolation procedures in part 2.6.
** HOD Load error or Bad system disk **
Insert system disk in drive
Press any key when ready ..•..
5.
If none of the messages are displayed and you have a printer
port LED, go to PROCEDURE 3.
If none the messages are displayed and you don't have a
printer port LED, go to PROCEDURE 2.
2-11
PROCEDURE 2
Beep Sound Check
1.
Turn the POWER switch off.
2.
Turn the POWER switch on.
3.
If the system occurs an error, the system informs you of an
error code with the beep sound. (That is the bit information
of DL register.)
The system repeats the buzzer message three times. A
hexadecimal number is configured by the combination of two
groups of the beep sounds, each of which is composed of
either short sounds or long sounds.
The status of an error code is as following table.
4.
If the error code conforms to the values given in the table,
go to PROCEDURE 5.
5.
If the error code doesn't conform to the values given in the
table, another FRU is probably defective.
TABLE 2-4 Beep Sound Error Code
OH
lH
2H
3H
4H
5H
6H
7H
BH
9H
AH
BH
CH
DH
EH
FH
2-12
PROCEDURE 3
Printer Port LED Check
1.
Turn the POWER switch off.
2.
Plug the printer port LED into the PRT/FDD connector on the
back of the unit.
3.
Turn the POWER switch on while watching the printer port
LED.
The printer port LED will light at the same time that the
POWER switch is turned on.
4.
Read the final LED status as a hexadecimal value from left
to right.
5.
If the final LED status matches any of the error code values
1n the table 2-6 (See the next page.), go to PROCEDURE 5.
6.
If the final
continue.
LED
status
is
19B,
go
to
PROCEDURE
TABLE 2-5 Printer Port LED Normal Status
Status
01 (H)
02 (H)
03 (H)
04 (H)
05(H)
06 (H)
07 (H)
08 (H)
09 (H)
OA (H)
OB (H)
OC (H)
OD (H)
OE(H)
OF (H)
10 (H)
11 (H)
12 (H)
13 (H)
14 (H)
15 (H)
16(H)
17 (H)
18 (H)
19 (H)
Messages
Initial setup of LSI start
Initial setup of RTC end
Initial setup of PIT end
Initial setup of DMAC(#1) end
Initial setup of DMAC(#2) end
Initial setup of PIC (#1) end
Initial setup of PIC (#2) end
Initial setup of DMA page register end
Initial setup of KB controller end
Initial setup of memory (0 - 64 KB) end
Initial setup of memory (64 - 640 KB) end
Initial setup of memory (more than 1 MB) Protect mode end
Initial setup of memory (more than 1 MB) Real mode end
Check a checksum of CMOS end
Check ciassfication of CRT end
Check item of CMOS end
Initial setup of CRT end
Initial setup of keyboard end
Initial setup of Timer end
Initial setup of FDD end
Initial setup of HDD end
Initial setup of option ROM end
Initial setup of printer end
Initial setup of RS232C end
Prepare the boot end
2-13
4
and
TABLE 2-6 Printer Port LED Error Status
Status
Error Messages
Process
81 (H)
Exception (size proc)
82 (H)
Faded PM (size proc)
HALT
83 (H)
ADR 20 failed (size proc)
HALT
84(H)
KBC Self test error
HALT
HALT
85(H)
KBC not ready
I (KBC init)
HALT
86 (H)
KBC not ready
o (KBC init)
HALT
87(H)
KBC not ready
I (size ret)
HALT
88(H)
KBC not ready
I (ex. ret size)
HALT
89 (H)
KBC not ready
I (mono set)
HALT
8A(H)
KBC not ready
I (KB init)
HALT
8B (H)
KBC not ready
I (PRT init)
HALT
8C(H)
KBC not ready
o (PRT init)
HALT
91 (H)
PE
HALT
93 (H)
=1 (start)
PE =0 (size proc)
PE =0 (mem test)
94(H)
ROM check sum error
HALT
A1 (H)
RTC data bus error
HALT
A2(H)
92 (H)
HALT
HALT
RTC into error
HALT
A3 (H)
RTC clock error
HALT
A4(H)
PIT data bus error
HALT
A5(H)
PIT ch.2 output error
HALT
A6(H)
PIT clock error
HALT
A7 (H)
PIT ch. 1 output error
HALT
A8(H)
PIT ch.O output error
HALT
A9 (H)
DMAC # 1 data bus error
HALT
AA(H)
DMAC #2 data bus error
HALT
AB (H)
PIC # 1 data bus error
HALT
AC(H)
PIC #1 data bus error
HALT
AD(H)
PIC #2 data bus error
HALT
AE (H)
PIC #2 data bus error
HALT
AF (H)
MAPPER data bus error
HALT
B1 (H)
MAPPER address error
HALT
B2 (H)
Word/byte error (110)
HALT
B3 (H)
Exception (mem test)
HALT
B4 (H)
Failed PM (mem test)
HALT
I (ex. ret mem test)
B5(H)
KBC not ready
B6(H)
ADR 20 failed (mem test)
B7(H)
KBC NOT ready
I (mem test)
2-14
HALT
HALT
HALT
Status
Error Messages
o (FDD int)
Process
B8(H)
KBC not ready
C1 (H)
Mem (base 64KB) data bus error
HALT
C2 (H)
Mem (base 64KB) word/byte error
HALT
HALT
C3 (H)
Mem (base 64KB) fixed data error
HALT
C4(H)
Mem (base 64KB) address error
HALT
C8(H)
Mem (base 64KB) parity circuit error
HALT
C9(H)
Mem (base 64KB) parity circuit error
HALT
CA(H)
i Mem (base 64KB) parity circuit error
HALT
CB (H)
Mem (base 64KB) parity circuit error
HALT
CC(H)
Mem (base 64KB) parity circuit error
HALT
01 (H)
Mem (64 KB-
) data bus error
HALT
D2 (H)
Mem (64 KB-
) word/byte error
HALT
D3 (H)
Mem (64 KB-
) fixed error
HALT
04 (H)
Mem (64 KB-
) address error
HALT
DS (H)
Mem address error
D8(H)
Mem (64 KB-
) parity circuit error
HALT
09 (H)
Mem (64 KB-
) parity circuit error
HALT
OA(H)
Mem (64 KB-
) parity circuit error
HALT
DO(H)
HALT
DB (H)
Mem (64 KB-
) parity circuit error
HALT
DC(H)
Mem (64 KB-
) parity circuit error
HALT
E1 (H)
Video RAM error (mono)
HALT
E2 (H)
Video RAM error (plasma/color)
HALT
E3 (H)
Video RAM error (plasma)
HALT
E4(H)
CRTC error (mono)
HALT
ES(H)
CRTC error (plasma/color)
HALT
E6(H)
FDC error
HALT
2-15
PROCEDURE 4
Test Program Execution
1.
Execute the following
DIAGNOSTICS. )
1.
2.
3.
4.
S.
6.
7.
test program.
(See PART
3 TEST AND
System test
Memory test
Keyboard test
Display test
Floppy disk test
Hard disk test
Real timer test
2.
If an error is generated on the system test, memory test,
display test and real timer test, go to PROCEDURE S.
3.
If an error is generated on the floppy disk test, go to FDD
isolation procedures in part 2.S.
4.
If an error is generated on the hard disk test, go to HDD
isolation procedures in part 2.6.
S.
If an er.ror is generated on the keyboard
keyboard isolation procedures in part 2.7.
2-16
test,
go
to
PROCEDURE 5
System PCB Replacement
1.
Replace the system PCB.
(Refer to part 4.14)
2.
If normal operation is restored after replacing the PCB, the
previous PCB was defective.
3.
If normal operation is not restored, another FRU is probably
defective.
The defective unit must be isolated and
replaced.
2-17
2.5 FLOPPY DISK DRIVE ISOLATION PROCEDURES
This section describes how to determine whether the floppy disk
drive is defective or not.
The procedures below are outlined in
the following pages.
They should be performed in the order
indicated.
PROCEDURE 1: Test and Diagnostic Program Loading Check
PROCEDURE 2 : Message Check
PROCEDURE 3 : Head Cleaning
PROCEDURE 4 : FDD Test Execution
PROCEDURE 5 : FDD Connector Check
PROCEDURE 6 : New FDD connection
2-18
PROCEDURE 1
Test and Diagnostic Programs Loading Check
1.
Turn the POWER switch off.
2.
Insert the diagnostics disk into the FDD.
3.
Turn the POWER switch on.
4.
If loading occurs normally, go to PROCEDURE 3.
to determine if loading has occurred normally.)
5.
If loading has not occurred normally, go to PROCEDURE 2.
2-19
(See PART 3
PROCEDURE 2
Messaqe Check
1.
When the diagnostics disk is inserted into the FDD and the
POWER switch is turned on, message (a), message (b), message
(c) or message (d) should appear.
(a) (**** FDD A in not installed ****
(b)
)
Non-System disk or disk error
Replace and press any key when ready
** FDD load error or Bad system disk **
(c)
Insert system disk in drive
Press any key when ready •.•••
** HOD Load error or Bad system disk **
(d)
Insert system disk in drive
Press any key when ready •••••
2.
If (a) of the above message is displayed, confirm that the
A-B-PRT switch is set to the PRT side. If it is not seted to
the PRT side, set the PRT side; if it is seted to the PRT
side, go to PROCEDURE 5.
3.
If (b), (c) or (d) of the above messages is displayed, the
contents of the floppy disk are damaged, or some other disk
than the diagnostics disk has been inserted into the FDD.
Change the diagnostics disk.
If loading then occurs, go to
PROCEDURE 4; if loading does not occur, go to PROCEDURE 3.
4.
If none of the above messages appears, go to PROCEDURE 5.
2-20
PROCEDURE 3
Head Cleaning
1.
Turn the POWER switch off.
2.
Insert the cleaning disk to the FDD.
3.
Turn the POWER switch on.
4.
If normal operation is restored after cleaning the head, go
to PROCEDURE 4.
5.
If normal operation is not restored, go to PROCEDURE 5.
2-21
PROCEDURE 4
FDD Test Execution
1.
Run
the floppy disk
Diagnostic Test Menu.
test
which
is
2.
If an error is generated during the floppy disk test, an
error code and status will be displayed as indicated in the
following table.
Follow the directions provided in the
table.
3.
If no error is generated, the FDD is normal.
TABLE 2-7 FDD Error Status
CODE
STATUS
01
Bad Command
02
Address Mark Not Found
03
Write Protected
04
Recod Not Found
06
Media removed on dual attach card
08
DMA Overrun Error
09
DMA Boundary Error
10
CRC Error
20
FDC Error
40
SEEK ERROR
60
FDD not drive
80
Time Out Error (Not Ready)
EE
Write buffer error
2-22
indicated
in
the
PROCEDURE 5
FDD Connector Check
1.
Turn the POWER switch off and disconnect the ac cord.
2.
Remove the top cover.
3.
If the FDD cable is connected to the system PCB securely, go
to PROCEDURE 6.
4.
If the above connections are not secure, reconnect them.
(Refer to part 4.2.>
FIGURE 2-4 FDD Connector Check
2-23
PROCEDURE 6
New FDD Connection
1.
Turn the POWER switch off.
2.
Remove the FDD. (Refer to part 4.10.>
3.
Connect the new
connectors too.
4.
Turn the POWER switch on.
5.
If normal operation is restored after connect the new FDD,
the previous FDD was defective. Assemble the system.
6.
If normal operation is not restored, system PCB is probably
defective. Refer to part 2.4.
FDD
to
the
2-24
FDD
connector,
then
other
2.6 BARD DISK DRIVE ISOLATION PROCEDURES
This section describes how to determine whether the Hard Disk
Drive is defective or not.
The procedures below are outlined in
the following pages.
They should be performed in the order
indicated.
PROCEDURE 1: HDD Indicator Check
PROCEDURE 2: Message Check
PROCEDURE 3: Format Execution
PROCEDURE 4: Hard Disk Test Execution
PROCEDURE 5: Connector Check
PROCEDURE 6 : New HDC Connection
PROCEDURE 7: New HDD Connection
2-25
PROCEDURE 1
HOD Indicator Check
1.
Turn the POWER switch off.
2.
If there is a floppy disk in the FDD, take it out.
3.
Turn the POWER switch on.
4.
If the HDD indicator (Disk In Use - Left) blinks briefly and
goes out, go to PROCEDURE 2: if it continues blinking, go to
PROCEDURE 4.
5.
If the indicator does not light at all, go to PROCEDURE 5.
Disk in Use
_0
0
000
Left Right
CRT
Caps Num Scroll
.----~---., Lock Lock Lock
FIGURE 2-5 HDD Indicator Check
2-26
PROCEDURE 2
Message Check
1.
If the system is loaded, go to PROCEDURE 4.
2.
If the following message is displayed on the screen, go to
PROCEDURE 3.
**
HOD Load error or Bad system disk
Insert system disk in drive
Press any key when ready ..•••
2-27
**
PROCEDURE 3
Format Execution
CAUTION: The contents of the hard disk will be erased when the
FORMAT command is
run.
Before running
the
test,
transfer the contents of the hard disk on the floppy
disk. This can be done with the MS-DOS BACKUP command.
(See the MS-DOS manual for details.)
1.
Remove the diagnostics
system disk to the FDD.
disk,
2.
To set the parti tion of the hard disk, enter
command. (See the MS-DOS manual for details.)
3.
To format the hard disk, enter the FORMAT command.
MS-DOS manual for details.)
4.
If normal operation is restored, the HDD is normal.
5.
If normal operation is not restored, go to PROCEDURE 6.
2-28
and
then
insert
the
MS-DOS
the
FDISK
(See the
PROCEDURE 4
Hard Disk Test Execution
CAUTION: The contents of the hard disk will be erased when the
test program is run. Before running the test, transfer
the contents of the hard disk on the floppy disk. This
can be done wi th the MS -DOS BACKUP command. (See the
MS-DOS manual for details.>
1.
Insert the diagnostics disk into the FDD and load the test
and diagnostic programs.
2.
Run the hard disk test which is indicated in the diagnostics
test menu.
3.
If an error is generated during the hard disk test, an error
code and status will be displayed as indicated in the
following table. Go to PROCEDURE 6.
4.
If no error is generated, the HDD is normal. Enter the
MS-DOS FDISK command which will set the parti tion. Then
enter the MS-DOS FORMAT command. (See the MS-DOS manual for
details. )
TABLE 2-8 HDD Error Status
STATUS
CODE
01
02
04
05
07
09
OA
OB
10
11
20
40
80
AA
BB
CC
EO
FO
Bad command error
Bad address mark
Record not found
HDC NOT RESET
Drive not initialize
DMA Boundary error
Bad sector error
Bad track error
ECC error
ECC recover enable
HDC error
Seek error
Time out error
Drive not ready
Undefined
Write fault
Status error
Not sense error (HW.code =FF)
2-29
PROCEDURE 5
Connector Check
1.
Turn the POWER switch off and disconnect the ac cord.
2.
Remove the top cover. (Refer to part 4.2>
J.
If the HDD, HDC, and system PCB are connected securely, go
to PROCEDURE 6.
4.
If they are not connected securely, reconnect them.
FIGURE 2-6 HDC and HDD Connector Check
2-30
PROCEDURE 6
New HOC Connection
1.
Turn the POWER switch off and disconnect the ac cord.
2.
Remove the HDC.
3.
Connect the new HOC to the system PCB and HDO,
connectors too.
4.
If normal operation is restored,
defective. Assemble the system.
5.
If normal operation is not
defective. Go to PROCEDURE 7.
(Refer to part 4.13.>
2-31
the
restored,
then other
previous
HOD
is
HOC
was
probably
PROCEDURE 7
New HOD Connection
1.
Turn the POWER switch off.
2.
Remove the HOD.
3.
Connect the new HDD to the HDC, then other connectors too.
4.
If normal operation is restored,
defective. Assemble the system.
5.
If normal operation is not restored, system PCB is probably
defective. System PCB is probably defective. Refer to part
2.4.
(Refer to part 4.11.)
2-32
the
previous
HDD
was
2.7 KEYBOARD ISOLATION PROCEDURES
This section describes how to determine whether the keyboard is
defective or not.
The procedures below are outlined in the
following pages.
They should be performed in the order
indicated.
PROCEDURE 1: Input Check
PROCEDURE 2: Keyboard Test Execution
PROCEDURE 3: Connector Check
PROCEDURE 4: New Keyboared Connection
2-33
PROCEDURE 1
Input Check
1.
Load either the diagnostics disk or the MS-DOS system disk.
2.
When a prompt (A, B, C, etc.) appears on the screen, hit any
of the whi te keys on the keyboard (any character or the
space bar).
If the character you hit appears on the screen,
go to PROCEDURE 2.
3.
If the character does not appear,
go to PROCEDURE 3.
Toshiba Personal Computer MS-DOS Version 3.20 / (RXXXXX)
(C) Copyright Toshiba
(C) Copyright Microsoft
Corporation 1983,1986
Corporation 1981,1986
Current date is XXX X-XX-19XX
Enter new date (mm-dd-yy) :
Current time is X:XX:XX,XX
Enter new time :
COMMAND Version 3.20
A> abcdefghijklmnopqrst ••••••••••••••••
2-34
PROCEDURE 2
Keyboard Test Execution
1.
Insert the diagnostics disk into the PDD and load the test
and diagnostics programs. (Refer to PART 3.>
2.
Run the keyboard test which is indicated in the diagnostics
test menu.
3.
If an error is generated during the test, go to PROCEDURE 3.
4.
If no error is generated during
normal.
2-35
the test,
the keyboard
is
PROCBDURE 3
Connector Check
1.
Turn the POWER switch off and disconnect the ac cord.
2.
Remove the top cover. (Refer to part 4.2)
3.
Lift the keyboard up and check that the keyboard cable is
connected securely to the system PCB.
If it is connected
securely, go to PROCEDURE 4.
4.
If it is not connected securely, reconnect it.
FIGURE 2-7 Keyboard Connector Check
2-36
PROCEDURE 4
New Keyboard Connection
1.
Turn the POWER switch off and unplug the ac cord.
2.
Remove the keyboard unit.
3.
Connect the new keyboard to the system PCB.
4.
If normal operation is restored after connect the keyboard,
the previous keyboard was defective. Assemble the system.
5.
If normal operation is not restored, system PCB is probably
defective. Refer to part 2.4.
(Refer to part 4.7.>
2-37
2.8
PLASMA DISPLAY ISOLATION PROCBDURES
This section describes how to determine whether the PLASMA
DISPLAY is defective or not. The procedures below are outlined
in the following pages.
They should be performed in the order
indicated.
PROCEDURE 1: Display Check
PROCEDURE 2: Plasma Display Contrast and
Brightness Check
PROCEDURE 3 : Display Test Execution
PROCEDURE 4: Plasma Display Connector Check
PROCEDURE 5: New PDP Connection
2-38
PROCEDURE 1
Display Check
1.
Turn the POWER switch off.
2.
After turning the POWER switch on again, the following
message should appear in the upper left-hand corner of the
screen:
MEMORY TEST XXXKB
3.
If the message appears, go to PROCEDURE 2.
4.
If the message does not appear, first do the following:
(a) Confirm that the contrast
adjusted correctly.
and
brightness
volume
is
(b) Confirm that the display is not on an external CRT.
(The CRT indicator lamp will be lit if the display is
on an external CRT.)
(C) Confirm that the DIP switch is OFF.
After confirming (a), (b) and (c) above, perform steps 1 and
2 again. If the message still fails to appear, go to
PROCEDURE 3.
2-39
PROCEDURE 2
Plasma Display Contrast and Brightness Check
1.
Turn the contrast and brightness volume, then confirm that
the screen becomes changed darker or brighter.
2.
If the screen is changed darker or brighter,
inputs voltage to the PDP. Go to PROCEDURE 7.
3.
If the screen is not changed, go to PROCEDURE 4.
power supply
FIGURE 2-8 Plasma Display Contrast and Brightness Check
2-40
PROCEDURE 3
Display Test Execution
1.
Insert the diagnostics disk into the FDD and run the test
and diagnostics programs.
2.
If an error is generated dur ing the display test from the
diagnostics test menu, the system PCB is probably defective.
Refer to part 2.4.
3.
If no error is generated, the plasma display is normal.
2-41
PROCEDURE 4
PDP Connector Check
1.
Turn the POWER switch off and unplug the ac cord.
2.
Take out the PDP (Refer to part 4.4.) and confirm that the
plasma display cable is connected securely to the module.
3.
If the cable is connected securely, go to PROCEDURE 6.
4.
If the cable is not connected securely, reconnect it.
FIGURE 2-9 PDP Connector Check
2-42
PROCEDURE 5
New PDP Connection
1.
Connect a new PDP and plasma display cable to the PDP.
2.
If normal operation is restored after replacing the PDP, the
previous PDP was defective. Assemble the system.
3.
If normal operation is not restored, system PCB is probably
defective.
System PCB is probably defective. Refer to part
2.4.
2-43
3.1 GENERAL
This part explains test and diagnostic programs. The purpose of
the test and diagnostic programs is to check the functions of
all hardware modules of the T3200 Personal Computer.
There are 19 programs ~ they are composed of two modules: the
service program module (DIAGNOSTICS MENU) and test program
module (DIAGNOSTIC TEST MENU).
The service program module is composed of 8 tasks:
1.
2.
3.
4.
5.
6.
7.
8.
HARD DISK FORMAT
SEEK TO LANDING ZONE (HOD)
HEAD CLEANING
LOG UTILITIES
RUNNING TEST
FDD UTILITIES
SYSTEM CONFIGURATION
SETUP
The test program module is composed of 11 tests as follows:
1.
2.
3.
4.
5.
6.
7.
8.
9.
10.
11.
SYSTEM TEST
MEMORY TEST
KEYBOARD TEST
DISPLAY TEST
FLOPPY DISK TEST
PRINTER TEST
ASYNC TEST
HARD DISK TEST
REAL TIMER TEST
NDP TEST
EXPANSION TEST
The following items are necessary for carrying out the test and
diagnostic programs.
1.
2.
3.
4.
5.
6.
T3200 Diagnostics disk
MS-DOS system disk
Work disk (formatted)
Cleaning disk kit
Printer wraparound connector
RS232C wraparound connector
The service engineer utilizes these programs to isolate problems
by selecting the appropriate program and operation procedures
described in the part 3.2 OPERATIONS.
3-1
3.2 OPERATIONS
1.
Insert the diagnostics disk in
turn the POWER switch on.
the floppy disk drive
2.
Input TESTCB3 for the A> prompt and press Enter.
3.
The following display will appear.
and
TOSHIBA personal computer T3200 DIAGNOSTICS
Version X.XX (C) copyright TOSHIBA Corp. 1987
DIAGNOSTIC MENU:
1
2
3
4
5
6
7
8
9
-
o-
DIAGNOSTIC TEST
HARD DISK FORMAT
SEEK TO LANDING ZONE (HOD)
HEAD CLEANING
LOG UTILITIES
RUNNING TEST
FDD UTILITIES
SYSTEM CONFIGURATION
EXIT TO MS-DOS
SETUP
PRESS [0] - [9] KEY
Detailed explanations of the service programs
operations are given in parts 3.16 to 3.23.
4.
and
the
Press 1 key then Enter. The following display will appear.
TOSHIBA personal computer T3200 DIAGNOSTICS
version X.XX (C) copyright TOSHIBA Corp. 1987
DIAGNOSTIC TEST MENU :
1
2
3
4
5
6
7
8
9
10
11
88
99
-
SYSTEM TEST
MEMORY TEST
KEYBOARD TEST
DISPLAY TEST
FLOPPY DISK TEST
PRINTER TEST
ASYNC TEST
HARD DISK TEST
REAL TIME TEST
NDP TEST
EXPANSION TEST
FDD & HOD ERROR RETRY COUNT SET
EXIT TO DIAGNOSTICS MENU
PRESS [1] - [9] KEY
3-2
If you want to set the FDD and HDD retry count, type 88 then
press Enter. The following message will appear.
When don't operate, error retry count number is onece.
FOO & HOD Error retry count ?
You can set the error retry count of the floppy disk test
and hard disk test.
Type 99 then press Enter. Return to the DIAGNOSTICS MENU.
When select the
will appear.
FLOPPY DISK
TEST,
the
following
messages
Test drive number select (1:F001.2:FOD2.0:F001&2) ?
Media in drivell mode (l:360k.2:360k-l.2M/720k.3:1.2M.4:720k) ?
Test start track (Enter:0/dd:OO-79) ?
In the case of type the test start track, test start track
number of the floppy disk is one digit or two digits.
When press Enter only, test start track number is zero
track.
When select the HARD DISK TEST,
appear.
the following message will
Test drive number select (I:H001.2:H002.0:H001&2) ?
5.
After pressing the test number (1 to 11) of the DIAGNOSTIC
TEST MENU, the following display (sample) will appear.
XXXXXXX
TEST NAME
SUB TEST
PASS COUNT
WRITE DATA
ADDRESS
xx
XXXXX
XX
XXX XX
ERROR COUNT
READ DATA
STATUS
SUB-TEST MENU :
01 - ROM CHECKSUM
99 - Exit to DIAGNOSTIC TEST MENU
SELECT SUB-TEST NUMBER?
TEST LOOP (1:YES/2:NO) ?
ERRR STOP (1:YES/2:NO) ?
3-3
XXXXX
XX
xxx
6.
Select the subtest number. Type the subtest number then
press the Enter. The following message will appear.
When select the KEYBOARD TEST, the following message will
not appear.
TEST LOOP (1:YES/2:NO) ?
When select the (YES)1
Each time a test cycle ends, it increments the pass counter
by one and repeats the test cycle ••
When select the (NO)1
At the end of a test cycle, it terminares the test execution
and exits to the subtest menu.
7.
Type the 1 or 2 then press Enter. The following message will
appear.
ERROR STOP (1:YES/2:NO) ?
When select the (YES)1
When an error occurs, it displays the error status and stops
the execution of the test program. The operation guide
displays on the right side of the display screen.
When select the (NO)1
When an error occurs, it displays the error status then it
increments the error counter by one and goes to the next
test.
8.
Type the 1 or 2 then press the Enter. The test program will
run. Each subtest names described in the part 3.3.
9.
When stop the test program, press Ctrl + Break keys
return to the DIAGNOSTICS MENU.
then
10. When error occurs on the test program, the following message
will appear.
(( HALT OPERATION ]]
1: Test End
2: Continue
3: Retry
ERROR STATUS NAME
1: Terminates the test program execution and exits
subtest menu.
2: Continues the test.
3: Retry the test.
The error
3.15.
code and
error
status
3-4
names
described
to the
in
part
3.3 SUBTEST NAMES
The following table shows subtest name of the test program.
TABLE 3-1 Subtest Names
#
TEST NAME
1
SYSTEM
2
MEMORY
3
KEYBOARD
4
DISPLAY
5
FDD
SUBTEST#
01
02
01
02
03
ROM checksum
HW status
RAM constant data
RAM address pattern data
RAM refresh
Protected mode
Protected mode (3MB)
LIM (Expansion memory)
Pressed key display
Pressed key code display
VRAM read/write
Character attributes
Character set
80*25 Character display
Graphics display (color set 0/1)
640*200 Graphics display
640*200 Graphics display
Display page
·W pattern display
Special attribute test
Sequential read
Sequential read/write
Random address/data
Write specified address
Read specified address
Ripple pattern
Function
Wrapa around
Wrap around (channel· 1)
Wrap around (channel - 2)
Point to point (send)
Point to point (receive)
Card modem loopback
Card modem on-line test
Dial tester test
Sequential read
Address uniquence
Random address/data
Cross talk & peek shift
Write/read/compare(CE)
Write specified address
Read specified address
ECC circuit (CE cylinder)
Sequential write
Real time test
Backup memory test
Real ti me carry test
NDPtest
Box wrap around test
Box mono video ram test
Wrap around test ( 16bit bus)
04
05
06
01
02
01
02
03
04
05
06
07
08
09
10
01
02
03
04
OS
6
PRINTER
7
ASYNC
01
02
03
01
02
03
04
OS
06
07
01
02
03
04
HOD
OS
9
REAL TIMER
10
NDP
11
EXPANSION
UNIT
06
07
08
09
01
02
03
01
01
02
03
8
TEST ITEMS
3-5
3.4
SYSTEM TEST
Subtest 01
ROM checksum (Execution time: 1 second)
This test performs the ROM checksum
system PCB.
(Test extent : FOOOOH - FFFFFH 64KB)
Subtest 02
test
on
the
H/W status
This test reads hardware status of the system, then
displays the status as shown below.
76543210
H/W status = 10011101
Bit7
Bit6
BitS
Bit4
Bit3
Bit2
Bit1
BitO
-----------------
[DIP]
SW1
SW4
SW6
SW7-10
Display mode
CPU clock
Ten key PAD
2MB FDD
Internal FDDs
Drive A/B
External FDD
Internal FDD
---------
= Plasma
= 12MHz
= OFF
= 1.6MB
=1
= Normal
= OFF
= 2DD type
Auto SW
= Disable
Font Mode
= Single
European Font= Other
Monitor Type = RGB 350
3-6
3.5
MEMORY TEST
Subtest 01
RAM constant data (Execution time: 30 seconds)
This test writes constant data to Memory, and then
reads and compares them with the original data.
The constant data are "FFFFH", "AAAAH", "5555H",
"OlOlH" and "OOOOH".
Subtest 02
RAM
address
seconds)
pattern
data
<Execution
time:
10
This test makes the segment address and offset
address by XORing, and then writes the address
pat tern data and reads and compares them wi th the
original data.
Subtest 03
RAM refresh (Execution time: 20 seconds)
This test wr i tes constant data in 256 bytes length
to Memory, and then reads and compares it with the
original data.
The constant data are "AAAAH" and
"5555H".
A certain interval time will be taken
between the write and the read operations.
Subtest 04
Protected mode (Execution time: 78 seconds)
This test writes fixed data and address data to
memory (256 kbytes to MAX 640 kbytes or 1 Mbytes to
MAX. Mbytes ) in protect mode, and then reads and
compares it with the original data.
Subtest 05
Protected mode (3MB)
(Execution time: 74 seconds)
This test writes fixed data and address data to
memory (1 Mbytes to 4 Mbyts) in protect mode, and
then reads and compares it with the original data.
Subtest 06
LIM (Expansion memory)
(Execution time: 84 seconds)
Run the same test as subtest 04 for the expansion
memory page' frame address (DO OOOH) and the block
select register (208H/2l8H) and memory size (3
Mbytes + 384 kbytes). This performed for every 64
kbytes.
3-7
3.6
KEYBOARD TEST
Subtest 01
Pressed
key display
Hote: Execute the test when Num-lock key is off.
key is on, the test cannot be carried out.
If this
When the keyboard layout (as shown below) is drawn
on the display, press a certain key and check
whether the corresponding key on the screen is
changed to the character "*".
When the same key again, it becomes to be the
original state so that it is able to confirm the
self-repeat function.
The following three keys are exceptions, and each
key is changed to the character "*" only when it is
pressed, and if released, it gets back to the
original state.
Ctrl key, Shift key, Alt key
KEYBOARD TEST
IN PROGRESS
30100
IF TEST OK, PRESS [DEL] THEN [ENTER] KEY
3-8
Subtest 02
Pressed key code display
Scan code, character code, and key top name are
displayed on the screen by pressing a certain key as
shown below.
Some keys such as Ins, Caps lock, Num lock, Scroll
lock, Alt, Ctrl, and shift key blink on the screen
when each one is pressed.
Each scan code, character code and key top name
described in the TABLE 3-2.(Next page)
KEYBOARD TEST
IN PROGRESS
302000
Scan code
= XX
Character code = XX
Key top
= XXXX
Ins Lock
Alt
Caps Lock
Ctrl
PRESS [ENTER] KEY
3-9
Num Lock
Scroll Lock
Left Shift Right Shift
TABLE 3-2 Scan Code, Character Code, and Key Top Names
KEY TOP
,
1
2
3
4
5
6
7
8
9
0
-
=
\
~-~
q
w
e
r
t
Y
u
i
0
P
[
1
a
s
d
f
9
h
J
k
I
SCAN CODE
29
02
03
04
05
06
07
08
09
OA
OB
OC
00
2B
OE
OF
10
11
12
13
14
15
16
17
18
19
1A
18
1E
1F
20
21
22
23
24
25
26
27
3-10
CHARACTER
CODE
60
31
32
33
34
35
36
37
38
39
30
20
3D
5C
08
09
71
77
65
72
74
79
75
69
6F
70
58
50
61
73
64
66
67
68
6A
68
6C
3B
TABLE 3-2 Scan Code, Character Code, and Key Top Name
KEY TOP
SCAN CODE
,
z
2C
x
c
v
b
n
m
,
/
Space
F2
F4
F6
F8
FlO
Fl
F3
F5
F7
F9
Esc
Home
E-
End
Uper
Lower
Pg Up
~
Pg Dn
Del
Sys Req
Prt Sc
-
+
28
2D
2E
2F
30
31
32
33
34
35
39
3C
3E
40
42
44
3B
3D
3F
41
43
01
47
4B
4F
48
50
49
4D
51
53
85
37
4A
4E
3-11
CHARACTER
CODE
27
7A
78
63
76
62
6E
6D
2C
2E
2F
20
00
00
00
00
00
00
00
00
00
00
lB
00
00
00
00
00
00
00
00
00
00
2A
2D
2B
3.7
DISPLAY TEST
Subtest 01
VRAM read/write (Execution time: 1 second)
This test writes constant data (FFFFH, AAAAH, 5555H,
OOOOH) and address data to the video RAM (256
kbytes) and SRAM (2 kbytes); it then reads the data
out and compares it the original data.
Subtest 02
Character attributes (Execution time: 1 second)
This test
displays:
is
for
checking
the
various
types
of
Normal Display
Intensified Display
Reverse Display
Blinking Display
In the case of color displays, all seven colors used
(blue, red, magenta, green, cyan, yellow, white) are
displayed. The background and foreground colors can
then be checked for br ightness. The display below
appears on the screen when this test is run.
CHARACTER ATTRIBUTES
NEXT LINE SHOWS NORMAL DISPLAY.
NNNNNNNNNNNNNNNNNNNNNNNN
NEXT LINE SHOWS INTENSIFIED DISPLAY.
I I I I I I I I I I I I I I I I
NEXT LINE SHOWS REVERSE DISPLAY.
RRRRRRRRRRRRRRRRRRRRRRRRRRRRRRR
NEXT LINE SHOWS BRINKING DISPLAY.
BBBBBBBBBBBBBBBBBBBBBBBBBBBBBBB
BLUE
RED
MAGENTA
GREEN
CYAN
YELLOW
WHITE
PRESS [ENTER] KEY
3-12
Subtest 03
Character set (Execution time: 1 second)
In this test the character code (OOH to FFH)
characters are displayed in the 40 x 25 pixel mode
as shown below.
CHARACTER SET IN 40X25
I
J. ~ , - .
/0123456 T B' :
J "_' •
PO R STU V W x Y Z ' "
I
J
I : J~
•
A ~
.i i 4 ,; ;; H 9 !
a ,
, r
aa
5.
rJ
+
•
~
-. I,~ I.~ i ...
I.•_Il.. . :-~...I.---'YT'·
.. ± ?:
~
b. f'
=:: • • , . . A I
~
:
< - > !@lA a C 0 E F 0 HI J i l L " NO
c _ • , , • I I k I.
aI
, i f 1
ill
I i i .j -8 -.. "'3 I,.J J
.;i
.--a +J
llE.~;
I ........
•
~ r n 1:
~
A.
,
~
r
I
I •••
G • YO 0 C ~k~
d , ~-
II ..
r
1--1
r
r II
I • n , _ • E n
•
PRESS [ENTER] KEY
Subtest 04
80*25 Character display (Execution time: 1 second)
In this test the shift caracters are displayed
the 80 x 25 pixel mode as shown below.
80*25 CHARACTER DISPLAY
012345678901234567890123u
!U;$~Lj()*~,-,/01234S67
!u=S~&j()*+,-./01234567f
678901234567890123456789
JXYZC¥]A_"abcdet9hij~lmno
XYZC¥]A
"abcdet9hijklmno~
.. !;$:".&. ' ( ) *+, -,/012345678' {YZC¥]" _ -: abcde t 9h i jk I mncpq
~$~~I()*+,-,/01234Sb787 YZC.JA_"abcdeT9hijkimncpq~
$~&.' ()*+,-./0123456789
ZC.]"_ "abcdet9hijklmncpqrs
~L' ()*+,-./0123456789:
:C¥]A_ "abcdet9hijklmno~~~st
& J ( ) T" , - , 10 123456789 : j . • ] A _ "a bed e t 9 h i j kim n 0 ~ '1 ~ 5 t u
'()*+,-./0123456789:j(: ]A_"abcdet9hijklmnc~~rstuv
()*+,-,/012345b789:j(=> \_"abcdet9hijklmnc~~rStuvw
)*+,-./012345b789: j(=>?Q "abc~et9hijklmnop~r5tuvwx
*+.-,10123456789: j(=>?CiA ~ocdet9hijklmnop~r5tuvwxy
*
T,
-.10 :23456789: j (=> ?CiA8C.
PRESS [ENTER] KEY
3-13
cde t 9h i jk I mnOpqr s t:..:vwxy::
in
Subtest 05
320*200 Graphics display (Execution time: 3 seconds)
This test displays two sets of color blocks for the
color display in the 320 x 200 dots graphics mode
(Mode 4 and D) as shown below.
Color set 0: Green, red, yellow
Color set 1: Cyan, Magenta, White
320*200 GRAPHICS DISPLAY
[X]
PRESS [ENTER] KEY
Subtest 06
640*200 Graphics display (Execution time: 3 seconds)
This test displays the color blocks for the black
and white display in the 640 x 200 dot graphics mode
(Mode 6 and E) as shown below.
640*200 GRAPHICS DISPLAY [X]
EVEN DOTS
ODD DOTS
DRIVEN
DRIVEN
PRESS [ENTER] KEY
3-14
ALL DOTS
DRIVEN
Subtest 07
640 x 400 Graphics display (Execution time: 5
seconds)
This test displays the color
and white display in the 640 x
graphics mode (Mode 10/ 74) as
Note: Mode 74 is not applicable when
is selected.
640*XXX GRAPHICS DISPLAY : [XX]
EVEN DOTS
ODD DOTS
DRIVEN
DRIVEN
blocks for the black
350 and 640 x 400 dot
shown below.
the external display
ALL DOTS
DRIVEN
PRESS [ENTER] KEY
Subtest 08
Display page (Execution time: 15 seconds)
This test confirms that the pages can be changed in
order (page 0 to page 7) in the 40 x 25 pixel mode.
a
aaaaaaaaaaaaaaaaaaaaaaaaa
a
a
a
a
a
a
a
a
a
a
a
a
a
a
a
a
a
a
a
a
a
a
a
a
aaaaaaaaaaaaaaaaaaaaaaaaa
DISPLAY PAGE
3-15
Subtest 09
"H" pattern display
This test displays H
screen, as shown below.
characters
on
the
entire
HHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHH
HHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHH
HHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHH
HHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHH
HHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHH
HHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHH
HHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHH
HHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHH
HHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHH
HHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHH
HHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHH
HHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHH
HHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHH
HHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHH
~HHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHH
Subtest 10
Special attribute test
This test displays the following display.
CRT/Caps/Num/Scroll LED test 1
(1)
(2)
(3)
(4)
(5)
Press
Press
Press
Press
Press
[ Caps Lock 1 key!
[ Num lock] key!
[Scroll lock 1 key!
[ Fn + End] key!
[ Fn + Home] key!
Press [ENTER] KEY
3-16
••• Caps (on/off)
•.. Num (on/off)
•.• Scroll (on/off)
.•. CRT (on)
••. CRT (off)
3.8
FLOPPY DISK TEST
CAUTION: Before running the floppy disk test prepare a formatted
work disk and remove the diagnostics disk then insert
the work disk to the FDD.
Subtest 01
Sequential read (Execution time: 50 seconds)
This test performs a cyclic redundancy check with a
continuous read operation of all track on a floppy
disk.
2D (Double-sided, double density): Track 0 to 39
2DD (Double-sided, double density, double track):
Track 0 to 79
Subtest 02
Sequential read/write (Execution time: 115 seconds)
This test writes data to all tracks (as defined
above) continuously and then reads the data out and
compares it to original data.
(The data pattern is B5ADADH repeated.)
Subtest 03
Random address/data (Execution time: 12 seconds)
This test writes random data to random address on
all tracks (as defined in subtest 01) and then reads
the data out and compares it with the original data.
Subtest 04
Write specified address (Execution time: 1 second)
This test writes data specified by keyboard to
tracks,
heads,
and
address
specified
by
the
keyboard.
Subtest 05
Read specified address (Execution time: 1 second)
This test reads data from tracks, heads, and address
specified by keyboard.
3-17
3.9
PRINTER TEST
CAUTION: A printer
(IBM compatible) must be
system in order to execute the test.
Subtest 01
looked
up
to
the
Ripple pattern (Execution time: 110 seconds)
This test prints character for code 20H through 7EH
line by line while shifting one character to the
right at the beginning of each new line.
! "#$%&' ( ) '"+, -. /0123456789: ; <=>?~ABCDEFGHIJKLMNOPQRSTUVWXYZ l ¥] - _' abcde
!"#$%&' ('''+,-./01234:;ti'jd~:;''=>'?ICIIABl:DEI!'GHIJKLMNOPQRSTUVWXYZl'tj_·abcder
"#$%&' ( ) "+, - ./0123456789: ; <=>?:glABCDEFGHIJKLMNOPQRSTUVWXYZ [¥ J -_ - abcdefg.
#$%&' ( ) *+, - ./0123456789: ; <=>?:~ABCDEFGHIJKLMNOPQRSTUVWXYZ [¥] - _' abcdefgh
$%&' ()*+,-./012345678 Q · '<=>?@ABCDEFGHIJKLMNOPQRSTUVWXYZ[¥]-_'abcdef%&' ()*+,-./Ol?~·
-or,HIJKLMNOPQRSTUVWXYZ[¥]-_-abc~
&'()*+
-··..,OPQRSTUVWXYZ(¥)-_·""
,
Subtest 02
'
Function (Execution time: 15 seconds)
This test
below.
prints
out
various
Normal Print
Compressed Print
Double Strike Print
print
Subtest 03
as
shown
Double Width Print
Emphasized Print
All Characters Print
PRINTER TEST
1. THIS LINES SHOWS NORMAL PRINT.
2.
THIS LINE SHOWS DOUBLE
3. THIS LINE SHOWS COMPRESSED PRINT.
4.
THIS LINE SHOWS EMPASIZED PRINT.
5. THIS LINE SHOWS DOUBLE STRIKE PRINT.
ALL CHARACTERS PRINT
!"#S%&' ()0+,-./0123456789:
opqrstuvwxyz{j )-
type
WIDTH
PRINT.
;<=>?~ABCDEFGHIJKLMNOPQRSTUVWXYZ(Yl'_ abcdefgn~J~lmn
Wrap around (Execution time: 1 second)
Note: A printer wraparound connector is necessary for
executing this test. Wiring diagram of the printer
wrap around connector described in the part 3.24.
Checks the data, control, and status lines with the
printer wrap around connector.
Operations for the test is as follows.
1. After type the channel
message will appear.
[[[ Change DIPSW-2
number,
the
following
ON JJJ ?
2. Turn the DIP switch-2 on, then press Enter.
3. After f innished the test,
off.
3-18
turn
the DIP swi tch-2
3.10 ASYNC TEST
For subtest 01 to subtest 05, transmission is done as follows in
the communication.
Speed: 9600 BPS
Data:
8 bits + parity (EVEN)
1 stop bit
20H to 7EH
Subtest 01
Wrap around (channell)
(Execution time: 1 second)
Note: An RS232C wrap around connector must be connected to
channell to execute this test. RS232C wrap around
connector wiring diagram described in part 3.24.
Performs a data send/receive test
around connector for the channell.
Subtest 02
Wrap around (channel 2)
with
the
wrap
(Execution time: 1 second)
Performs the same test as subtest 01 for the channel
2.
Subtest 03
Point to point (send)
(Execution time: 1 second)
Note: This test can be executed on condition that the both
send
and
receive
sides
are
set
in
the
same
condition, and also connected together by RS232C
direct cable
(Wiring diagram described in part
3.22. ). Subtest 03 must be executed together wi th
subtest 04 and vice versa.
In this test, the data (20H to 7EH) are sent as one
block from one side to the other, and then returned
from the later one to the first side again.
This test is used to check wheter the returned data
are same as the original ones.
Subtest 04
Point to point (receive)
(Execution time: 1 second)
This test is exactly the same as subtest 03 except
that the data flow is completely opposite.
3-19
Subtest 05
300/1200 BPS card modem loopback (Execution time:
seconds)
Note: If there is no modem card in the system,
can not be executed.
5
this test
This test is used to check whether the data, which
is from the modem to the RS232C inside the system,
is same as the original data which had first been
sent to the modem card.
Subtest 06
Card modem on-line test (Execution time: 10 seconds)
Note: After the system is connected to the PBX, unless the
receive side is in the same status as the send side,
the test cannot be executed.
In this test, first some data are sent to the modem
card from the RS232C inside the system, then the
data is again sent to the other system through the
PBX (Private Branch Exchange).
This test is used whether the returned data from the
other system are same as the original data.
Subtest 07
Dial tester test (Execution time: 60 seconds)
Note: To execute this test,
connected to the system.
a
dial
tester
must
be
This test is carried out by sending the pulse dial
and tone dial twice automatically.
[Pulse dial]: "1-2-3-4-5-6-7-8-9-0-1-2"
[Tone dial]:
"1-2-3-4-5-6-7-8-9-*-0-#"
3-20
3.11 BARD DISK TEST
CAUTION: The contents of the hard disk will be erased when
subtest 02, 03, 04, 06, 08 and 09 is run. Before
running the test, transfer the contents of the hard
disk on the floppy disk. This can be done with the
MS-DOS BACKUP command. After the test, enter the MS-DOS
FDISK command, which will set the partition. Then enter
the MS-DOS FORMAT command. (See the MS-DOS manual for
details.)
Subtest 01
Sequential
read
(CYL.0-614,CYL.614-0)
time: 8.5 minutes)
(Execution
This test performs forward reading of contents from
track 0 to track 610 and then performs reverse
reading of the contents from track 610 to track O.
Subtest 02
Address uniquence (Execution time: 13 minutes)
This test writes the address data(sector by sector)
track by track, then reads the data and compares it
to the original data.
Following
three
kinds
of
read
operations
are
performed.
(Forward sequential, Reverse sequential, Random)
Subtest 03
Random address/data (Execution time 30 seconds)
This test write random data in random units to
random address (cylinder, head, sector) and then
reads the data out and compares it to the original
data.
Subtest 04
Cross talk & peak shift (Execution time: 13 minutes)
This test writes the eight types of worst pattern
data (shown below) to cylinders then reads the data
while shifting cylinder by cylinder.
Worst pattern data
1. B5ADAD ...... .
2. 4A5252 ...... .
3. EB6DB6 ...... .
4. 149249 ...... .
5. 63B63B ...... .
6. 9C49C4 ...... .
7. 2DB6DB ..•....
8. D24924 ....•..
3-21
Subtest 05
Write/Read/Compare (CE)
(Execution time: 2 seconds)
This test writes B5ADAD worst pattern data to the CE
cylinder and then reads the data out and compares it
to the original data.
Subtest 06
Write specified address (Execution time: I second)
This test writes
cylinder and head.
Subtest 07
specified
data
a
specified
Read specified address (Execution time: I second)
This test reads data which has
specified cylinder and head.
Subtest 08
to
ECC
circuit
seconds)
(CE
cyl inder)
been
written
(Execution
to
time:
a
2
This
(Error
test
checks
check
and
the
ECC
specified
correction)
circuit
functions
to
a
cylinder and head.
Subtest 09
Sequential write
This test writes specified data of the two bytes to
all cylinder.
3-22
3.12 REAL TIMER TEST
Subtest 01
Real time
A new data and time can be input during this
when the current data and time are displayed.
Operations for the test is as follows.
1. After executing the
will appear.
test,
test
the following message
REAL TIME TEST
901000
Current date: xx-xx-xxxx
Current time: XX:XX:XX
Enter new date:
PRESS [ENTER] KEY TO EXIT TEST
2. If current date is not correct, input the current
new date. Press the Enter, the Enter new tiae:
message will appear.
3. If current time is not correct, input the current
new time. Press the Enter, return to the subtest
menu of the REAL TIME TEST.
Subtest 02
Backup memory (Execution time: 1 second)
This test writes data (FFH, AAH, 55H, OOH) to 64
bytes of the backup memory, and then reads and
compares it with the original data.
Subtest 03
Real time carry
CAUTION: When
this test
time is erased.
is
executed,
the
current data
and
This
test
checks
whether
the
real-time
clock
increments the time displayed correctly (month, day,
year, hour, minute, second).
3-23
3.13 NDP TEST
Note: This test cannot be run if there is no NDP mounted on the
system PCB.
Subtest 01
NDP test (Execution time: 1 second)
This test checks the control word, status word, bus,
and addition/multiplication functions.
3.14 EXPARSION UNIT TEST
Note: If there is no expansion box connected to the system, this
test cannot be executed.
Subtest 01
Box wrap around
seconds)
(8
bits
bus)
(Execution
time:
3
Note: As this test required a special tool to be executed,
it can not be carried out here.
Subtest 02
Box mono video ram (Execution time: 1 second)
Note: If there is no monochrome display card in
expansion box, this test cannot be executed.
the
This test writes data (FF, AA, 55, OOH) into the
monochrome display memory (BOOOOH to BOF9FH), then
reads the data out and compares it to the original
data.
Subtest 03
Wrap around test (16 bit bus)
Note: As this test required a special tool to be executed,
it can not be carried out here.
3-24
3.15 ERROR CODE AND ERROR STATUS HAMES
The following table shows the error code and error status names.
TABLE 3-3 Error Code and Error Status Names
DEVICE NAME
ERROR CODE
EVERYTHING
FF
Compare error
SYSTEM
01
ROM Checksum Error
MEMORY
01
02
Parity Error
PROTECTED MODE NOT CHANGE ERROR
FDD
01
02
03
04
06
08
09
10
20
40
60
80
EE
Bad Command
Address Mark Not Found
Write Protected
Record Not Found
Media removed on dual attach card
DMA Overrun Error
DMA Boundary Error
CRC Error
FDC Error
SEEK ERROR
FDD not drive
Time Out Error (Not Ready)
Write buffer error
RS232C
01
02
04
08
10
20
40
80
88
33
34
36
DSR Off Time Out
CTS Off Time Out
RX EMPTY Time Out
TX BUFFER FULL Time Out
Parity Error
Framing Error
Overrun Error
Line Status Error
Modem Status Error
NO CARRIER (CARD MODEM)
ERROR (CARD MODEM)
NO DIAL TONE (CARD MODEM)
PRINTER
01
08
10
20
40
80
Time Out
Fault
Select Line
Out Of Paper
Power off
Busy Line
ERROR STATUS NAME
3-25
TABLE 3-3 Error Code and Error Status Names
DEVICE NAME
ERROR CODE
HDD
01
02
04
05
07
09
AA
BB
CC
EO
FO
Bad command error
Bad address mark
Record not found
HDC NOT RESET
Drive not initialize
DMA Boundary error
Bad sector error
Bad track error
ECC error
ECC recover enable
HDC error
Seek error
Ti me out error
Drive not ready
Undefined
Write fault
Status error
Not sense error (HW.code
01
02
03
04
05
06
No NDP
Control word error
Status word error
Bus error
Addition error
Multiplication error
OA
OB
10
11
20
40
80
NDP
ERROR STATUS NAME
3-26
=FF)
3.16 HARD DISK FORMAT
There are two types of hard disk formatting:
1. Physical formatting
2. Logical formatting
This orogram is for physical formatting of the hard disk; it can
execute the following items.
1.
2.
3.
4.
All track FORMAT
Good track FORMAT
Bad track FORMAT
Bad track CHECK
Note: Execution of the program cannot be performed unless the
HDD switch is on.
CAUTION: The contents of the hard disk will be erased when this
program is run. Before running the program, transfer
the contents of the hard disk on to a floppy disk. This
can be done with the MS-DOS BACKUP command. (See the
MS-DOS manual for details.)
3.16.1 proqram description
1. All track FORMAT
Performs physical
shown below.
(Execution time: 15 minutes)
formatting of hard disk in
Sector sequences:
Cylinders:
Heads:
Sectors:
Sector length:
Bad track:
the
manner
3
o
o
to 614
to 7
1 to 17
512 bytes per sector
MAX. 51 tracks
2. Good track FORMAT
(Execution time: 1 second)
Executes the formatting of a specified cylinder and track as
a good track.
3. Bad track FORMAT
(Execution time: 1 second)
Executes the formatting of a specified cylinder and track as
a bad track.
4. Bad track CHECK
(Execution time: 1 and 1/2 minutes)
Checks for bad tracks by performing a read operation for all
tracks on the hard disk; a list of bad tracks is then
displayed.
3-27
3.16.2 Operations
CAUTION: After physical formatting is finished, enter the MS-DOS
FDISK command, which will set the partition. Then enter
the MS-DOS FORMAT command. (See the MS-DOS manual for
details.)
1.
After pressing 2 and Enter to select from the DIAGNOSTICS
MENU, the following display will appear.
DIAGNOSTIC - HARD DISK FORMAT: VI.O
I - All track FORMAT
2 Good track FORMAT
3 Bad track FORMAT
4 Bad track CHECK
9 Exit to DIAGNOSTICS MENU
Press [NUMBER] key?
2.
All track FORMAT Selection
(1) When All track FORMAT (1) is selected, the following
message will appear.
Interleave number (3/1-9) ?
(2) Select an interleave number. (Usually select 3.) Type the
number and press Enter.
The following message will
appear.
Drive number select (1:11. 2:12) ?
(3) Select a drive number. Type the drive number and press
Enter. The following display will appear.
[HOD TYPE]
[HOD TYPE]
[HOD TYPE]
CYLINDER
HEAD
SECTOR
= XXX
=
X
= XX
[WARNING: Current DISK data will be
completely destroyed]
[[cylinder,head
3-28
= XXX X]]
(4) After checking all cylinders of
following message will appear. If
the following message will appear.
the hard disk, the
found the bad track,
Press [Bad track number (CCCH) key ?
(5) If the hard disk has the bad track except the displayed
number, type a bad-track number (four digits) and press
Enter. (The first three digits are the cylinder number
and the last digit is the head number.) If there is a bad
track on the hard disk, press the Enter only. This
executes the formatting of all tracks.
formatting the hard disk, the [[cylinder r
message wi 11 appear; then all cyl inders
hard disk are checked. If there is a bad track
hard disk, the bad track number will be displayed
screen.
(6) After
xxx
X))
head =
of the
on the
on the
(7) Format complete message will then appear.
(8) Press the Enter to return to the HARD DISK FORMAT menu.
3-29
3. Good track FORMAT or Bad track FORMAT Selection
(1) When Good track FORMAT or Bad track
the following message will appear.
FO~
is selected,
Interleave number (3/1-9) ?
(2) Select an interleave number. (Usually select 3.) Type the
number and press Enter. The following message will
appear.
Drive number select (1:11, 2:12) ?
(3) Select a drive number. Type the drive number and press
Enter. The following message will appear.
[HOD TYPE]
[HOD TYPE]
[HOD TYPE]
CYLINDER
HEAD
SECTOR
= XXX
=X
= XX
Press [Track Number (CCCH)] key?
(4) Type a track number (four digits) and press Enter.
(The first three digits are the cylinder number and the
last digit is the head number.) This executes the
formatting of good tracks or bad tracks.
Rote: This program can format only one track per operation. If
it is desired to format several good tracks or bad
tracks, repeat the operation as many times as nessary.
(5) After formatting the track of the hard disk,
complete message will appear.
the Format
(6) Press the Enter to return to the HARD DISK FORMAT menu.
3-30
4. Bad track CHECK Selection
(l) When Bad track CHECK is selected, the following message
will appear.
Drive number select (l:ll, 2:12) ?
( 2) Sel ect a dr i ve number. Type the dr i ve number and press
Enter. When the following message appears, and bad tracks
of the hard disk are checked.
[HOD TYPE]
[HOD TYPE]
[HOD TYPE]
CYLINDER
HEAD
SECTOR
= XXX
=X
= XX
[[cylinder,head
=
XXX X]]
(3) After checking the bad tracks of the hard disk
checked, the Format complete message will appear.
are
(4) Press the Enter to return to the HARD DISK FORMAT menu.
3-31
3. 17 SEEK TO LANDIRG ZONE (BDD)
3.17.1 Program description
When moving the uni t, if an HDD head touches a da ta area, the
data wi 11 be lost. In order to protect the data, this program
moves HDD heads to safe areas. Theese areas called .. landing
zones."
Note: When the built-in T3200 hard disk does not issue a command
to the HDD for an interval of 5 seconds, the HDD heads
move to a landing zone automatically.
3.17.2 Operations
1.
After pressing .. 3" and Enter to select from the DIAGNOSTICS
MENU. The program is then automatically executed and the
following message will appear.
Landing seek completed. (HOO#!)
Press [enter] key.
2.
After pressing Enter, return to the DIAGNOSTICS MENU.
3-32
3.18 BEAD CLEANING
3.18.1 Program description
This program executes head loading and seek/read operations for
head cleaning. A cleaning kit is necessary for cleaning the FDD
head.
3.18.2 Operations
1.
After pressing 4 and Enter to select from the DIAGNOSTICS
MENU, the following message will appear.
HEAD CLEANING
Mount cleaning disk(s) on drive(s).
Press any key when ready.
2.
After above message appears, remove the Diagnostics
insert the cleaning disk, and press any key.
3.
When the following message appears,
begin.
disk,
FDD head cleaning will
HEAD CLEANING
Mount cleaning disk(s) on drive(s).
Press any key when ready.
Cleaning start
4.
When cleaning is finished, the display automatically returns
to the DIAGNOSTICS MENU.
3-33
3.19 LOG UTILITIES
3.18.1 Program description
This program logs error information generated, while a test is
in progress; the information is stored in the RAM.
However if the POWER switch is turned off the error information
will be lost. The error information itself is displayed as the
following.
1.
2.
3.
4G
5.
6.
7.
8.
9.
Error count (eNT)
Test name (TEST)
Subtest number (NAME)
Pass count (PASS)
Error status (STS)
Address (FDD, HDD 1 or memory; ADDR)
Write data (WD)
Read data (RD)
Error status name
This program can store
information to a printer.
data
3-34
on
a
floppy
disk
or
output
3.19.2 Operations
1.
After pressing 5 and Enter to select from the DIAGNOSTICS
MENU, the error information logged in the RAM or on the
floppy disk is displayed as shown below.
XXXXX ERRORS
CNT TEST NAME PASS STS ADDR WD RD ERROR STATUS NAME
001
FDD 02 0000 103 00001 00 00 FDD - WRITE PROTECTED
001
FDD 01 0000 180 00001 00 00 FDD - TIME OUT ERROR
1AdJ...
1
Read data
Error status
Pass count
Write data
Error status name
Sub test number
Test name
Error count
[[1:Next,2:Prev,3:Exit,4:Clear,5:Print,6:FD LogRead,7:FD LogWrite II
2.
Error information to be displayed on the screen
manupulated with the following key operation.
The
The
The
The
The
The
The
1
2
3
4
5
6
7
key
key
key
key
key
key
key
scrolls the display to the next page.
scrolls the display to the previous page.
returns the display to the DIAGNOSTIC MENU.
erases all error log information in RAM.
outputs error log information to a printer.
reads log information from a floppy disk.
writes log information to a floppy disk.
3-35
can
be
3.20 RUNNING TEST
3.20.1 Program
descripti~n
This program automatically runs the following tests in sequence.
1.
2.
3.
4.
S.
6.
7.
8.
System test (subtest number 01)
Memory test (subtest number 01, 02, 03, 04, 06)
Display test (subtest number 01 to 08)
FDD test (subtest number 02)
Printer test (subtest number 03)
Async test (subtest number 01)
HDD test (subtest number 01, OS)
Real timer (subtest number 02)
When running an FDD test, this system
whether there are one or two FDDs.
automatically
decides
3.20.2 Operations
CAUTION: Do not
forget to load a work disk. If a work disk is
not loaded, an error will be generated during FDD
testing.
1.
Remove the diagnostics disk and
the floppy disk drive.
insert the work disk into
2.
After pressing 6 and Enter to select from
MENU, the following message will appear.
the
DIAGNOSTIC
Printer wrap around test (YIN) 1
3.
Select whether to execute the printer wraparound test (Yes)
or not (No). Type the desired Y or N and press Enter key.
(If Y is selected, a wraparound connector must be connected
to the pr inter connector on the back of the unit.) The
following message will appear.
Async wrap around test (YIN) 1
4.
Select whether to execute the test (Yes) or not (No). Type
the desired Y or N and press Enter Key. (If Y is selected,
an RS232C wraparound connector must be connected to the
COMMS connector on the back of the unit.)
5.
This program is repeated continuously. To stop the program,
press Ctrl + Break key.
3-36
3.21 FDD UTILITIES
3.21.1 Program description
These programs format and copy floppy disks,
list for both the FDD and the HDD.
and display dump
1. FORMAT
This program can format floppy disk (5.25"/3.5") as follows.
(a) 20: Two-sided, double-density, 48 TPI, MFM mode, 512 bytes,
9 sectors/track.
(b) 200: Two-sided, double-density, double-track, 96 TPI, MFM
mode, 512 bytes, 15 sectors/track.
(c) 2HD: Two-sided,high-density, double-track, 96/135 TPI, MFM
mode, 512 bytes, 15 sectors/track.
2. COpy
This program copies floppy disks.
Copy with one FDD (Drive A)
Copy with two FDDs (Drive A to Drive B)
3. DUMP
This program display the contents of floppy disks (both 3.5" and
5.25") and hard disks (designated sectors).
3.21.2 Operations
1.
After
pressing
7 and
Enter
key
to
select
from
the
DIAGNOSTICS MENU, the following display will appear before
program execution.
[FDD UTILITIES]
1
2
3
9
FORMAT
COPY
DUMP
EXIT TO DIAGNOSTICS MENU
PRESS [I] - [9] KEY
3-37
2. FORMAT
Selection
(1) When FORMAT is selected, the following message appears.
DIAGNOSTICS - FORMAT
Drive number select (l:A, 2:8) ?
(2) Select a drive number. Type the number and the following
message will then appear.
Type select (O:2DD-2DD,1:2D-04DE,2:2D-08DE,3:2HD-08DE)
(3) Select a media-drive type number. Type the number and the
following message will appear.
Warning: Disk data will be destroyed.
Insert work disk in to drive A :
Press any key when ready.
( 4 ) Remove the diagnostics disk from the FDD and insert the
work disk; press any key.
The Format start message will appear; formatting is then
the
executed. After the floppy disk
is
formatted,
following message will appear.
Format complete
Another format (1:Yes/2:No) ?
(5) If you type 1 and press Enter key, the display will
return to the message in (3) above. If you type 2 the
display will return to the DIAGNOSTICS MENU.
3-38
3. COpy Selection
(1) When COpy is selected, the following message will appear.
DIAGNOSTICS - COPY
Type select (O:2DD-2DD,1:2D-04D,2:2D-08DE,3:2HD-08DE) ?
(2) Select a media/dr i ve type number. Type the number.
following message will then appear.
The
Insert source disk into drive A
Press any key when ready.
(3) Remove the diagnostics disk from the FDD and insert the
source disk; press any key. The Copy started message will
then appear. After that, the following message will
appear.
Insert target disk into drive A
Press any key when ready.
(4) Remove the source disk from the FDD and insert the work
disk (formatted); press any key. When coping can not be
done with one operation, message (2) is displayed again.
Repeat the operation. After the floppy disk has been
copied, the following message will appear.
Copy complete
Another copy (1:Yes/2:No) ?
(5) If you type 1 the display will return to the message in
(1) above. If you type 2 the display will return to the
DIAGNOSTICS MENU.
3-39
4. DUMP Selection
(1) When DUMP is selected, the following message will appear.
[HDD&FLOPPY DISK DATA DUMP]
format type select (O:2DD,1:2D,2:2HD,3:HDD) ?
(2) Select a format type number. Type the number. If 3 is
selected, the dump lists for the hard disk are displayed
automatically.
0:
1:
2:
3:
Display a dump list for a floppy disk (2DD)
Display a dump list for a floppy disk (2D).
Display a dump list for a floppy disk (2HD).
Displays a dump list for a hard disk.
(3) If 0, 1,
appear.
or
2 is
selected,
the
following
message will
following
message wi 11
Select FDD number (1:A/2:B) ?
( 4) Select an FDD drive number;
then appear.
the
Insert source disk into drive A
Press any key when ready.
(5) Remove the diagnostics disk from the FDD and insert a
source disk; press any key. The Track number 11 message
will then appear. Type the track number and press Enter.
(6) The Head number? message will then appear. Type the head
number and press Enter.
(7) The sector number ?1 message will then appear. Type the
sector number and press Enter. The dump list for the
floppy disk will be displayed.
(8) After a dump list appears on the screen, the Press number
key (1:up,2:down,3:end) 1 message will appear.
1. Displays the next sector dump.
2. Displays a previous sector dump.
3. Displays the following message.
Another dump (1:Yes/2:No) ?
(9) If you type 1 the display will return to the message
shown after (4) above. If you type 2 the display will
return to the DIAGNOSTICS MENU.
3-40
3.22 SYSTEM CONFIGURATION
3.22.1 Program description
This program displays the following system configuration.
1.
2.
3.
4.
5.
6.
7.
8.
Memory size
Display type
Floppy disk drive number
Async port number
Hard disk drive number
Printer port number
Co-processor number
Extended memory size
3.22.2 Operations
After pressing 8 and Enter key to select from the DIAGNOSTICS
MENU, the following display will appear.
SYSTEM CONFIGURATION
*
*
*
*
*
*
*
*
-
-
640KB MEMORY
PLASMA DISPLAY
1 FLOPPY DISK DRIVE(S)
1 ASYNC ADAPTOR
1 HARD DISK DRIVE(S)
1 PRINTER ADAPTOR
0 MATH CO-PROCESSOR
XXXXKB EXTENDED MEMORY
PRESS [ENTER] KEY
Press Enter key to return to the DIAGNOSTICS MENU.
3-41
3.23 SETUP
3.23.1 Program description
This program displays the following items, and then can change
it by automatically or manual.
1.
2.
3.
4.
5.
6.
Floppy disk drive number and type
Hard disk drive number and type
System memory size
Extended memory size
Expanded memory size
External display card status
3.23.2 Operations
1.
After pressing a and Enter to select the DIAGNOSTICS MENU,
the following display will appear.
[[ System setup ]]
1. Floppy disk drives
drive#! type
driveN2 type
=1
=2
=0
720KB/l.2MB
No drive
2. Hard disk drives
driveNl type
=1
= 4- Cyl=614,h=8,S/T=17
3. Memory size
System memory
Extended memory
Expanded memory
= 640KB
= OMB
= 384KB +
4. External display card
= None
OMB
Select setup change (l:no/2:yes) ?
2.
Select the (yes) or (no). Type the number and press Enter.
If select (yes), the following message will appear.
If select (no), load the system again.
3-42
3.
Select the (auto) or (manual). Type the number and press
En ter. If select the (manual), the following message wi 11
appear.
Floppy disk setup
0: No drive
1: 360KB
2: 720KB/1. 2MB
(1) Floppy disk driveR1 type = 2 ?
4.
Select the floppy disk drive#l type. Type the number and
press Enter. (In the case of the floppy disk drivr type is
720KB or 1.2MB, press Enter only.)
The following message will appear.
0: No drive
1: 360KB
2: 720KB/1. 2MB
(2) Floppy disk driveR1 type
5.
=
0 ?
Select the floppy disk drive#2 type. Type the number and
press Enter. (In the case of the floppy disk drive#2 is no
drive, press Enter only.) The following message will appear.
Hard disk setup 1
(3) Is hard disk available? (YIN)
3-43
6.
Select the (YES) or (NO). Type "Y" or
Enter. Return to the SETUP menu.
Note: If the system has a optional
following message will appear.
"N"
and
memory
press
card,
the
the
Extended memory setup ]
0:
1:
2:
3:
4:
5:
6:
No memory
0.5MB
1MB
1.5MB
2MB
2.5MB
3MB
(4) Extended memory size = 06 ? [
(Expanded memory size
7.
3MB]
[384KB+ OMB])
Select the expanded memory size. Type the number and press
the Enter. Return to the SETUP menu.
Note: If the DIP switch 5 is ON and the system has a
optional display board to the expansion slot, the
following message will appear.
[External display card type setup]
1:
2:
3:
0:
Color display card (40*25 column)
Color display card (80*25 column)
Monochrome display card
Others
(5) External display type = 0 ?
8.
Select the external display card type. Type the number and
press the Enter. Return to the SETUP menu.
3-44
3 • 24 WIRING DIAGRAM
1 . Printer wrap around connector
(9) + PD7
- ERROR
( 15)
(8) + PD6
- AUTFD
( 14)
(7) + PD5
+ SELECT
(13)
(6) + PD4
- PINIT
(16)
(5) + PD3
- STROBE
(1)
-ACK
(10)
(4) + PD2
+ PE
(12)
(3) + PD1
- SLiN
(17)
(2) + PD~
+ BUSY
(11 )
FIGURE 3-1 Printer Wrap Around Connector
2 . RS232C Wrap around connector
(3) TRANSMIT DATA
RECEIVE DATA
(2)
(7) REQU EST TO SEN D
CLEAR TO SEND
(8)
CARRIER DETECT
(1)
DATA SET READY
(6)
RING INDICATE
(9)
L
L
(4) DATA TERMINAL
READY
FIGURE 3-2 RS232C Wrap Around Connector
3-45
3 . RS232C direct cable (9-pin to 9-pin)
(3) TO
.-
(4) OTR
:
(7) RTS
RO
(2)
OSR
(6)
CTS
(8)
RI
(9)
CO
(1)
GNO
(5)
.-
(5) GNO
(2) RO
I(
TO
(3)
(1) CO
I(
RTS
(7)
OTR
(4)
(6) OSR
(8) CTS
(9) RI
:
FIGURE 3-3 RS232C Direct Cable (9-pin to 9-pin)
4. RS232C direct cable (9-pin to 25-pin)
(1) CO
...
RTS
(4)
(2) RO
...
TO
(2)
RO
(3)
CTS
(5)
OSR
(6)
RI
(22)
GNO
(7)
CO
(8)
OTR
(20)
(3) TO
.-
(4) OTR
:
(5) GNO
(7) RTS
(6) OSR
(8) CTS
(9) RI
.-
:
FIGURE 3-4 RS232C Direct Cable (9-pin to 25-pin)
3-46
4.1 GENERAL
This section gives a detailed description of the procedures used
to replace FRUs (field replaceable units).
FRUs consist of the following:
1.
2.
3.
4.
5.
6.
7.
8.
9.
10.
11.
12.
13.
14.
15.
16.
Top Cover
PDP (Plasma Display Panel) Mask
PDP
Indicator PCB
Cable Guide
PDP Cover Assembly
Keyboard Unit
Speaker
Lithium Battery
Power Supply Unit
FDD (Floppy Disk Drive)
HDD (Hard Disk Drive)
Expansion Bus PCB
Fan
HDC (Hard Disk Control PCB)
Syatem PCB
The following points must be kept in mind:
1. The system should never be disassembled unless there is a
problem (abnormal operation, etc.)
2. Only approved tools may be used.
3. After deciding the purpose of replacing the unit, and the
procedures required, do not carry out any other
procedures which are not absolutely necessary.
4. Be sure to turn the POWER switch off before beginning.
5. Be sure to disconnect the ac cord and all external cables
from the system.
6. Follow only the fixed, standard procedures.
7. After replacing a unit, confirm that the system is
operating normally.
Tools needed for unit replacement:
1. Phillips Screwdriver
2. Bladehead Screwdriver
3. Tweezers
4-1
4. 2 REMOVING/REPLACING THE TOP COVER
1.
Confirm that the POWER switch is off and unplug the ac cord.
2.
Turn the unit upside down and pull the handle (A) forward.
3.
Remove the five screws (B) from the base assembly (C).
(B)
(A)
FIGURE 4-1 Removing the Screws from the Base Assembly
4-2
6.
Open the plasma display, then remove the PDP, the indicator
PCB and cable guide as directed in part 4.3, 4.4 and 4.5.
7.
Remove the keyboard unit as directed in part 4.7.
8.
To remove the top cover (H), pass the four cable (1) through
a slit (J) of the top cover.
At this time, remove the connector panel (K) from the top
cover.
(K)
~
(J)
FIGURE 4-3 Removing the Top Cover
9.
To install a top cover, follow the above procedures in
reverse.
4-4
4.3 REMOVING/REPLACING THE PDP MASK
1.
Confirm that the POWER switch is off and unplug the ac cord.
2.
Open the plasma display.
3.
Using tweezers or fine-pointed instruments, peel off the
function label (A) and keep it in a clean place.
4.
Remove the two screws (B) from the PDP mask (C), then remove
the PDP mask pulling it up.
([»)
(E)
FIGURE 4-4 Removing the PDP Mask
5.
To install a new PDP mask, follow the above procedures in
reverse.
Note: Confirm that the eight latches (D) of the PDP cover
assembly (E) are inserted into the PDP mask.
4-5
4.4 REMOVING/REPLACING THE PDP
1.
Confirm that the POWER switch is off and unplug the ac cord.
2.
Remove the PDP mask as directed in part 4.3.
3.
Remove the four screws (A) on the PDP (B).
4.
Lift up the PDP, then put it on the keyboard (C).
5.
Disconnect the three cable (D) from the rear of the PDP.
FIGURE 4-5 Removing the PDP
6.
To install a PDP, follow the above procedures in reverse.
4-6
4.5 REMOVING/REPLACING THE INDICATOR PCB, THE CABLE GUIDE AND
THE PLASMA PCB
1.
Confirm that the POWER switch is off and unplug the ac cord.
2.
Remove the PDP as directed in part 4.4.
3.
Pull the ground cable (A) from the PDP cover assembly (B).
4.
Lift the indicator PCB (C), then disconnect an indicator
cable (D) from the indicator PCB.
4.
Take off the indicator cable, ground cable, plasma display
power cable (E) and plasma display signal cable (F) from the
cable guide (G), then remove the cable guide.
5.
To remove the volume PCB (H), remove the single screw (I)
from the PDP cover assembly.
(8)
-I.-J'--II'f--- (H)
(G)
(F) - - - , t . , . ,
FIGURE 4-6 Removing the Indicator PCB and the Cable Guide
4-7
6.
To install an indicator PCB and cable guide, follow the
previous page procedures in reverse.
Note: When put the four cables through cable guide, be
careful as following items.
(1)
Put plasma display power cable (J) to your right, and
plasma ground cable (K), indicator cable (L) and plasma
display signal cable (M) to your left as shown in the
figure 4-7.
(2)
position the cable guide so that thicker part (N) comes
to the upper side as shown in the figure 4-8.
(3)
Put the cable guide in the top cover, then place each
cable in the two ditches (0) of the PDP cover assembly
as shown in the figure 4-7.
«(»
(~)
(K)
(U
FIGURE 4-7 Cable position
FIGURE 4-8 Cable Guide
4-8
4. 6 REMOVING/REPLACING THE PDP COVER ASSEMBLY
1.
Confirm that the POWER switch is off and unplug the ac coad.
2.
Remove the indicator PCB and cable guide as directed in part
4•5•
3.
Remove the two screws (A) from the two hinges (B).
4.
To remove the PDP cover assembly (C), shift the two hinges
to inside, then turn the PDP cover assembly down and lift it
up.
FIGURE 4-9 Removing the PDP Cover Assembly
5.
To install a new PDP cover assembly, follow the above
procedures in reverse.
4-9
4. 7 REMOVING/REPLACING THE KEYBOARD UNIT
1.
Confirm that the POWER switch is off and unplug the ac cord.
2.
Open the plasma display, then remove the two mask panels (A)
by using bladehead screwdriver.
3.
Remove the two screws (B) located beneath the two mask
panels and lift up the keyboard unit (C).
4.
Release the pressure plate (0) of connector PJ 3 to
disconnect the keyboard cable (E) from the system PCB (F).
FIGURE 4-10 Removing the Keyboard unit
5.
To install a keyboard unit, follow the above procedures in
reverse.
4-10
4.8 REMOVING/REPLACING THE SPEAKER AND THE LITHIUM BATTERY
1.
Confirm that the POWER switch is off and unplug the ac cord.
2.
Remove the top cover as directed in part 4.2.
3.
To remove the lithium battery (A), disconnect the lithium
battery cable (B) from the system PCB (C) and lift it up.
4.
Disconnect the speaker cable (D) from the system PCB.
5.
Remove the speaker (E) by pushing the plastic latch (F)
outward until the speaker can be pulled out.
\.1ir--+-- (8)
(C)
FIGURE 4-11 Removing the Lithium Battery and the Speaker
6.
To install a new lithium battery and speaker, follow the
above procedures in reverse.
4-11
4.9 REMOVDIG/RBPLACIHG THE POWER SUPPLY UNIT
1.
Confirm that the POWER switch is off and unplug the ac cord.
2.
Remove the top cover as directed in part 4.2.
3.
Disconnect the two power supply cable (A) from the system
PCB
4.
(B).
To remove the power supply unit (C), remove the three screws
(D) from the power supply unit.
FIGURE 4-12 Removing the Power Supply Unit
5.
To install a power supply unit, follow the above procedures
in reverse.
4-12
4.10 REMOVING/REPLACING THE POD
1.
Confirm that the POWER switch is off and unplug the ac cord.
2.
Remove the top cover as directed in part 4.2.
3.
Remove the lithum battery (A) from the FDD base (B).
4.
Disconnect the FDD cable (C) from the system PCB (D).
5.
Remove the five screws (E) and ground cable (F) from the FDD
base.
(A)
FIGURE 4-13 Removing the FDD Base
4-13
6.
Remove the three screws (G) from the bottom of the FDD base.
(G)
FIGURE 4-14 Removing the FDD
7.
To install a new FDD, follow the above procedures in
reverse.
4-14
4.11 REMOVING/REPLACING THE BOD
CAUTION: The hard disk contents will remain in the old hard
disk. If desired, transfer the contents of the old hard
disk onto a floppy disk before replacing the hard disk.
This can be done with the MS-DOS BACKUP command. (See
the MS-DOS manual for details.)
1.
Confirm that the POWER switch is off and unplug the ac cord.
2.
Remove the top cover and FDD base as directed in part 4.2
and 4.10.
3.
Disconnect the HOD power cable (A) and HOC cable (B) from
the HOD (C).
4.
To remove the HOD, hold the HOD and remove the four screws
(D) from the bottom of the base assembly (E).
(E)
(8)
FIGURE 4-15 Removing the HOD
5.
To install a new HOD, follow the above procedures in
reverse.
6.
Enter the MS-DOS FDISK command, which will set the
partition. Then enter the MS-DOS FORMAT command. (See the
MS-DOS manual for details.)
4-15
4.12 RBMOVING/RBPLACING THE EXPANSION BUS PCB AND THE FAN
1.
Confirm that the POWER switch is off and unplug the ac cord.
2.
Remove the top cover and the FDD base as directed in part
4.2 and 4.10.
3.
Disconnect the fan and HOD power cable (A) from the HOD (B)
and the system PCB (C).
4.
Remove the two screws (D), then lift it up.
5.
To remove the fan on the expansion bus PCB (E), remove the
two screws (F).
(C)
(8)
FIGURE 4-16 Removing the Expansion Bus PCB and the Fan
6.
To install a new expansion bus PCB and a new fan, follow the
above procedures in reverse.
4-16
4.13 REMOVING/REPLACING THE BARD DISK CONTROL PCB
1.
Confirm that the POWER switch is off and unplug the ac cord.
2.
Remove the expansion bus PCB as directed in part 4.12.
3.
Disconnect the HDC cable (A) from the HDD (B), then remove
the two screws (C) from the HDC (D).
4.
To remove the HDC from the system PCB (E) lift it up.
(C)
(8) -
_ _ _-.::.
(E)
FIGURE 4-17 Removing the HDC
5.
To install a new HDC, follow the above procedures in
reverse.
4-17
4.14 REMOVING/REPLACING THE SYSTEM PCB
1.
Confirm that the POWER switch is off and unplug the ac cord.
2.
Remove the power supply unit, the FOO base and the expansion
bus PCB as directed in part 4.9, 4.10 and 4.12.
3.
Disconnect the speaker cable (A) from the system PCB (B).
4.
Remove the thirteen screws (C) and three spacer (D) on the
system PCB.
If the system has optional memory card, remove the optional
memory card from the system PCB after removing the system
PCB. (Refer to part 4.15.)
(D)
FIGURE 4-18 Removing the System PCB
5.
To install a new system PCB, follow the above procedures in
reverse.
4-18
4.15 REMOVING/REPLACING THE OPTIONAL MEMORY CARD
1.
Confirm that the POWER switch is off and unplug the ac cord.
2.
Remove the keyboard unit as directed in part 4.7.
3.
Remove the single screw (A) from the optional memory card
(B).
4.
To remove the optional memory card, lift up a part of the
system PCB and optional memory card, then disconnect the
optional memory card connector (C) from the system PCB.
(8)
FIGURE 4-19 Removing the Optional Memory Card
5.
To install a new optional memory card, follow the above
procedures in reverse.
4-19
5.1
PCB LAYOUT
N
:
~ 11.~~~ ~
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(L)
I
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a~
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D,
(D)
t~J':.
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••
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i
D•
••
(J)
;
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i
..
(F)
(N)
(A)
(C)
FIGURE
5 -1 System PCB Connectors
5-1
(A)
PJ 1
CRT connector
( B)
PJ 2
PRT/FDD connector
(C)
PJ 3
COMMS connector
(D)
PJ 4
Expansion connector
(E)
PJ 5
Speaker connector
(F)
PJ 6
HDD power connector
(G)
PJ 7
Power supply connector (+ 12 V)
(H)
PJ 8
Power supply connector (+ 5 V)
(1)
PJ 9
HDC connector
(J)
PJ 10 PDP connector
(K)
PJ 11 FDD connector
(L)
PJ 12 Lithium battery connector
(M)
PJ 14 Sensor connector
(N)
PJ 15 External keyboard connector
5-2
5.1. 2 System PCB ICs
(G)
(B)
~ b~
-c:J;
,0,itY
.. - :::cJ.
Cl~
(F) - - - r l
~
CJ-
(A)
EJi
~
c
EJ~
(E)
•
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0
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I
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(M)
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+
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:r=J
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,. P..J2
(R)
~I---·
.I"
FIGURE 5-2 Sy stem PCB ICs
5-3
I
j
1, •
(A)
CPU: Central processing unit (80286-12)
(B)
NDP: Numeric data processor socket (option)
(C)
FDC: Floppy disk controller (TC8565)
(D)
PIC: Programmable interrupt controller (82C59)
(E)
DMA: Direct memory access controller (82C37)
(F)
PIT: Programmable interval timer (82C54)
(G)
RTC: Rial time clock (46818)
(H)
SIO: Serial input/output controller (T8570)
(I)
VFO: Variable frequency oscillator (4108A)
(J)
AGS ROM
(K)
AGS RAM
(L)
V-RAM (256 kbytes)
(M)
Gate array (bus driver)
(N)
Gate array (memory mapper)
(0)
Gate array (DMA)
(P)
Gate array (AGS)
(Q)
Gate array (I/O controller)
(R)
PEGA2
5-4
5.1.3 Keyboard control PCB
(A)
...
I., I
.~
De
a
,~
I
. ..
I.' [
112
I
•
eq
!
(E)
+
(G)
...... . .
., II
(F)
(D)
(C)
..
~[j
+ :
~
N
M
u..
-
c:J:
l:J;
FIGURE 5-3 Keyboard Control PCB
5-5
(A)
PJ 1 Memory card connector
(B)
PJ 2 Jumper straps
(C)
PJ 3 Keyboard connector
(D)
Keyboard controller (8742)
(E)
System RAM
(F)
BIOS ROM
(G)
Gate array (EMS)
5-6
5.2
CONNECTORS
5.2.1
PRT/EXT FDD connector
13
o
0000000000000
o
000000000000
14
25
FIGURE 5-4 PRT/EXT FDD Connector
TABLE 5-1 PRT/EXT FDD Connector Signal Names
PIN
(FOR EXT FDD)
(FOR PRT)
SIGNAL
DESCRIPTION
I/O
SIGNAL
1/0
1
STROBE;OOO
0
- STROBE
READY;OOO
I
2
3
4
5
6
7
8
PD~; 110
PD1; 11 0
PD2; 110
PD3;110
PD4;110
PD5;110
PD6; 110
PD7;110
ACK;OOO
BUSY; 100
PE; 100
SELECT; 100
AUTFD;OOO
ERROR;OOO
PINIT;OOO
SLlN;OOO
0
0
0
0
0
0
0
0
+
+
+
+
+
+
+
+
INDEX;OOO
TRACKO;OOO
WPROTC;OOO
RDDA;OOO
DSKCHG;OOO
I
I
I
I
I
9
10
11
12
13
14
15
16
17
1825
GND
I
I
I
I
0
I
0
0
DATA BIT 0
DATA BIT 1
DATA BIT 2
DATA BIT 3
DATA BIT 4
DATA BIT 5
DATA BIT 6
DATA BIT 7
- ACKNOWLEDGE
+ BUSY
+ PAPER END
+ SELECT
-AUTO FEED
- ERROR (FAULT)
- PRINTER INITIALIZE
- SELECT INPUT
SWFDP;100
SWMONB;OOO
WRDATA;100
EXFWE; 100
XRATEO;100
SIDE;100
FDCDRC; 100
STEP;100
GROUND (0 V)
GND
5-7
0
0
0
0
0
0
0
0
DESCRIPTION
- EXTERNAL DRIVE
READY
-INDEX
- TRACK ZERO
- WRITE PROTECTED
- READ DATA
- DISK CHANGE
(NOT USED)
(NOT USED)
(NOT USED)
+ DRIVE SELECT
+ MOTOR ON
+ WRITE DATA
+ WRITE ENABLE
+ LOW DENSITY
+ SIDE SELECT
+ DIRECTION
+ STEP
GROUND (0 V)
5.2.2 RGB connector
5
o
o
0000
9
6
FIGURE 5-5 RGB Connector
TABLE 5-2 RGB Connector Signal Names
PIN
1
2
3
4
5
6
7
8
9
5.2.3
1/0
0
0
0
0
0
0
0
0
SIGNAL
MONOCHROME
STANDARD RGB
GND
Ground
Ground
Ground
PESR; 100
Ground
Ground
S.Red
ENHANCED RGB
PERE; 100
Not connected
Red
Red
PEGR; 100
Not connected
Green
Green
PEBL;100
Not connected
Blue
Blue
PESG;100
Intensity
Intensity
Intensity/ S.Green
PESB; 100
Video
Not connected
S.Blue
PEHS; 100
H.Sync
H.Sync
H.Sync
PEVS'100
V.Svnc
V.Svnc
V.Svnc
COMMS connector
5
o
0000
o
6
9
FIGURE 5-6 COMMS Connector
TABLE 5-3 COMMS Connector Signal Names
PIN
1
2
3
4
5
6
7
8
9
SIGNAL
MDCD; 100
MDRD; 100
MDTD; 100
MDDTR; 100
GND
MDDSR;100
MDRTS;100
MDCTS; 100
MDRI'100
1/0
DESCRIPTION
+ DATA CARRIER DETECT
+ RECEIVE DATA
+ SEND DATA
+ DATA TERMINAL READY
GROUND (OV)
+ DATA SET READY
+ REQUEST TO SEND
+ CLEAR TO SEND
+ RING INDICATOR
I
I
0
0
I
0
I
I
5-8
5.2.4
Expansion bus connector (in the system unit)
There are two typs of expansion bus connectors: one is 8-bit bus
type, and the other is l6-bi t bus type. 8 bi t bus-type has
signal names only at A side and B side.
TABLE 5-4 Expansion Bus Connector (A side/B side)
Signal Names
PIN
SIGNAL
I/O
PIN
SIGNAL
I/O
Al
A2
A3
A4
AS
A6
A7
A8
A9
Ala
All
A12
An
A14
A15
A16
A17
A18
A19
A20
A21
A22
A23
A24
A25
A26
A27
A28
A29
A30
A31
10CHCK; 000
507; 100
506; 100
505; 100
5D4; 100
503;100
,SD2; 100
501;100
500; 100
10RDY; 100
AEN;100
5A19;100
SA 18; 100
SA17; 100
SA 16; 100
SA 15; 100
SA 14; 100
SA 13; 100
SA12;100
SA 11; 100
SA10;100
SA9; 100
SA8; 100
SA7; 100
SA6; 100
5A5; 100
SA4; 100
5A3; 100
SA2; 100
SA 1; 100
SAO; 100
I
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I
0
/0
/0
/0
/0
/0
/0
/0
/0
/0
/0
/0
/0
/0
/0
/0
/0
/0
/0
/0
/0
Bl
B2
B3
B4
85
B6
B7
B8
B9
Bl0
B 11
B12
B13
B14
B15
B16
B17
B18
B19
B20
B21
B22
B23
B24
B25
B26
B27
B28
B29
B30
B31
GNO
RE5ET;100
0
5-9
vee
IRQ9; 100
M5V
OREQ2;100
M12V
OWAIT;OOO
P12V
GND
SMEMW;OOO
5MEMR;000
10W;000
10R;000
DACK3; 000
OREQ3; 100
OACK1;000
OREQ1;100
REFR5H;000
CLK;100
IRQ7;100
IRQ6; 100
IRQ5;100
IRQ4; 100
IRQ3;100
OACK2;000
TC; 100
ALE;100
vce
CLKCRT; 100
GND
I
I
I
0
0
I/O
I/O
0
I
0
I
I/O
0
I
I
I
I
I
0
0
0
0
TABLE 5-5 Expansion Bus Connector (C side/D side)
Signal Names
PIN
SIGNAL
I/O
PIN
SIGNAL
I/O
Cl
C2
(3
C4
(5
(6
C7
(8
(9
(10
Cll
(12
(13
(14
C1S
(16
C17
(18
5BHE;000
A23; 100
A22; 100
A21;100
A20; 100
A19;100
A 18; 100
A 17; 100
MEMR;OOO
MEMW;OOO
5D8; 100
509; 100
5Dl0;100
5Dl1;100
5D12; 100
5D13;100
5D14;100
5Dls'100
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
Dl
D2
D3
D4
Ds
D6
D7
D8
D9
Dl0
Dl1
012
013
D14
Dls
D16
D17
D18
MEM16;000
1016;000
IRQ10;100
IRQll;100
IRQ12; 100
IRQls;100
IRQ14;100
DA(KO;OOO
DREQO; 100
DA(KS;OOO
DREQS; 100
OA(K6;OOO
DREQ6; 100
DACK7;000
DREQ7; 100
V((
MA5TER;000
GND
I
I
I
I
I
I
I
0
I
0
I
5.2.5 External keyboard connector
3
2
FIGURE 5-7 External Keyboard Connector
TABLE 5-6 External Keyboard Connector Signal Names
Pin
1/0
Signal Name
1
1/0
KBCLK (clock)
2
3
I/O
KBDAT (data)
N.C.
4
Vee
5
GND
5-10
0
I
0
I
I
5.3
5.3.1
KEYBOARD LAYOUT
USA version
FIGURE 5-8 USA Version
5-11
5.3.2
England version
FIGURE 5-9 England Version
5-12
5.3.3 German version
FIGURE 5-10 German Version
5-13
5.3.4
France version
FIGURE 5-11 France Version
5-14
5.3.5 Spain version
FIGURE 5-12 Spain Version
5-15
5.3.6
Italy version
FIGURE 5-13 Italy Version
5-16
5.3.7 Scandinavia version
FIGURE 5-14 Scandinavia Version
5-17
5.3.8 Switzerland version
FIGURE 5-15 Switzerland Version
5-18
5.3.9 Keycap number
FIGURE 5-16 Keycap Number
5-19
5.4
DISPLAY CODE
TABLE 5-7 Display Code
~
0
I
2
3
4
5
6
7
0
I(~
A
B
C
0
E
F
2
3
4
5
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! " 2 B R
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I~I
APPENDIX A
BUS DRIVER GA (Gate Array)
A.l GENERAL
The
100
and
The
Bus Driver
lead pins,
Memory, or
Bus Driver
Gate Array is a flat package typed chip with
and it controls the busses between the CPU
the CPU and I/O devices.
Gate Array has the following functions.
- Input/ Output control of the 16-bit data bus
- Generation of the system address
- Generation of the Memory refresh address
51
80
50
31
100
30
1
A-l
A. 2 BLOCK DIAGRTAM
<
XCVR
n1" nil
<;D1S-C;DR
DIRC
DBHEN
I
V
BCHGE~I
XCVR
BCHGD~
(
I
LCH
CNVAO
LATDEN
<-r)7-nn
DIRC
SDl-SDD
-:> XVCR K
;>
DBlEN
r A16-A9
LCH
ALE
SEL
~16.:-:~'>
CPHLDA
AENl +AEN2
I
>
-:>
xn7-XD
ADSTB?,
LCH
r--
..
..
AENl
r--
SADREN
f--
r-->
AENl
AEN2 ~
ADSTBl
SEL
t
-
LCH
XA8
DRVR
CTR
..
REFADO
C;A8-SAO
>
REFQ1..,
PGA16
>
I Alq-A 1
I
LCH
ALE
~
CPHlD~
='.J REFAD~
SEL
SA19· ·SAiL />
CPHlDA
+DMACK
XCVR:
DRVR:
SEL:
LCH;
CTR :
FIGURE A-I
Transceiver
Driver
Selector
Latch
Counter
Bus Driver GA Block Diagram
A-2
A.3 SIGNAL DESCRIPTION AND PIN ASSIGNMENT
TABLE A-I
Pin
liD
Signal Name
1
I
CPHLDA
2
I
ALE
3
Vcc
4
I
PGA16
5
I
DIRC
6
I
BUSEN
7
I
XDO
8
I
I
I
I
I
I
I
XD1
XD2
XD3
XD4
XD5
XD6
XD7
GND
16
I
AEN1
17
I
AEN2
18
I
A9
19
20
21
I
I
I
A10
A 11
A15
9
10
11
12
13
14
15
Pin Description
Description
CPU hold acknowledge signal.
When this signal is high, the system bus is used by
anyother controller than the CPU.
CPU address latch signal.
This signal is active high.
+ 5V
This signal is a part of DMA address from the
page register of the Memory Mapper GA.
Data transfer direction signal in the CPU access
mode. When this signal is low, the data goes to
the CPU (read cycle), and when it is high, the data
comes from the CPU (write cycle).
Data bus enable signal.
This signal controls data enable timing during
the CPU readl write operation.
This signal is active high.
XD7-XDO are data bus from the liD controllers.
The DMAC outputs DMA address on the data bus
during the DMA operation.
Data bus bit o.
Data bus bit 1.
Data bus bit 2.
Data bus bit 3.
Data bus bit 4.
Data bus bit 5.
Data bus bit 6.
Data bus bit 7.
Ground
Address enable signal for the slave DMA.
This signal is active low.
Address enable signal for the master DMA.
This signal is active low.
A 19-A9 are the CPU address lines. These lines
also come from the Memory Mapper GA for the
DMA address transfer.
CPU address line bit 9.
CPU address line bit 10.
CPU address line bit 11.
CPU address line bit 15.
A-3
Pin
I/O
Signal Name
22
23
24
25
26
27
28
29
I
I
I
I
I
I
I
A12
A13
A17
A19
A14
A16
Vcc
A18
30
I
DMACK
31
0
XA8
32
I/O
SD15
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
SD14
SD13
SD12
SD11
SD10
SD9
SD8
GND
SD7
SD6
SD5
SD4
SD3
SD2
SD1
SDO
49
I
BCHGEN
50
I
BCHGDR
Descri ption
CPU address line bit 12.
CPU address line bit 13.
CPU address line bit 17.
CPU address line bit 19.
CPU address line bit 14.
CPU address line bit 16.
+5V
CPU address line bit 18.
This signal is generated by CPHLDA signal.
When this signal is low, CPU mode is activated,
and when it is high, DMA mode is activated.
DMA address
Each of SD15-SDO is the system data bus.
The lines SD15-SD8 are in the high bank, while
SD7-SDO are in the low bank.
System data bus bit 15.
System data bus bit 14.
System data bus bit 13.
System data bus bit 12.
System data bus bit 11.
System data bus bit 10.
System data bus bit 9.
System data bus bit 8.
Ground
System data bus bit 7.
System data bus bit 6.
System data bus bit 5.
System data bus bit 4.
System data bus bit 3.
System data bus bit 2.
System data bus bit 1.
System data bus bit o.
This is an enable signal to transfer the 2nd byte
during 16/8 bit conversion.
It is also enabled while DMA byte is transferred.
This signal is active low.
This signal controls the direction of the 2nd byte
transfer during 16/8 bit conversion or DMA byte
transfer.
A-4
Pin
51
1/0
0
Signal Name
SA6
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
0
0
0
0
0
0
0
0
Vcc
SA9
SA7
SA8
SA10
SAB
SA 11
SA 12
SA5
SA3
SA4
SA2
GND
SA1
SA14
SA15
SA16
SA17
SA18
SAO
SA19
74
I
DBHEN
75
I
DBLEN
76
I
LATDEN
77
I
CNVAO
78
0
0
0
0
0
0
0
0
0
0
0
Vcc
Description
System address lines.
SA8-SAO are used during the memory refresh
cycle, and SA 15-SA9 are used during the
CPU/DMA mode as a part of the system address.
System address line bit 6.
Not used
+ 5V
System address line bit 9.
System address line bit 7.
System address line bit 8.
System address line bit 10.
System address line bit 13.
System address line bit 11.
System address line bit 12.
System address line bit 5.
System address line bit 3.
System address line bit 4.
System address line bit 2.
Ground
System address line bit 1.
System address line bit 14.
System address line bit 15.
System address ne bit 16.
System address nebit17.
System address ne bit 18.
System address ne bit o.
System address I ne bit 19.
High bank data bus (SD15-SD8) enable signal.
This is active high.
Low bank data bus (SD7-SDO) enable signal.
This signal is active high.
This signal is to read the 1st byte stored in the
internal buffer during 16/8 bit conversion.
The 1st byte is read out when starting the 2nd
byte reading if this signal is active.
This signal is dummy address for the 2nd byte
during 16/8 bit conversion.
This signal stores the 1st byte in the internal
buffrer while read operation is being executed.
+ 5V
A-5
Pin
I/O
Signal Name
79
I
REFADO
80
I
REFQ1
81
I
ADSTB1
82
I/O
D15
83
84
85
86
87
88
89
90
I/O
I/O
I/O
I/O
I/O
I/O
I/O
D14
D13
D12
D11
D10
D9
D8
GND
91
I
ADSTB2
92
93
94
95
96
97
98
99
100
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
D7
D6
D5
D4
D3
D2
D1
DO
Description
This signal is a refresh address (the lowest bit).
It is output as SAO.
This signal is also used as a clock signal for the
internal refresh address counter.
This signal is to output the refresh address to the
system bus.
This signal outputs the content of the refresh
address counter, when it is low.
Slave DMAC address strobe signal.
This signal is used to latch the DMA address
which has been output on the data bus,.
CPU data bus from Ito the CPU.
(D15-D8 are in the high bank, and D7-DO are in
the low bank)
CPU data bus bit 15.
CPU data bus bit 14.
CPU data bus bit 13.
CPU data bus bit 12.
CPU data bus bit 11.
CPU data bus bit 10.
CPU data bus bit 9.
CPU data bus bit 8.
Ground
Master DMAC address strobe signal.
This signal generates DMA address.
It is active high.
CPU data bus bit 7.
CPU data bus bit 6.
CPU data bus bit 5.
CPU data bus bit 4.
CPU data bus bit 3.
CPU data bus bit 2.
CPU data bus bit 1.
CPU data bus bit o.
Not used.
A-6
A.4 DATA BUS CONTROL
This circuit controls the data bus between the CPU and I/O
port or the CPU and Memory.
8/16 bit conversion is
performed by this circuit.
<
D
2
B
> XCVR
[)lS -08
<;[) 1S-SDR
DIRC
DBHEN
BCHGO~'I
BCHGEN..
LCH r<
lJ
XCVR
r
J 4
CNVAO
3
lATDEN..
A
< [)7-00
DIRC
<;[)7-
> XVCR r<
.<:.nn
1
DBlEN
FIGURE A-2
C
Data Flow among the CPU, I/O Port, and Memory
A.4.1 Word access
When the I/O port connected to the data bus is word
oriented, no data conversion is performed.
Low bank
High bank
B
l1li(
(refer to Figure A-2)
In this case, read/ write cycle is completed in three CPU
cycles. (No wait cycle request is included.)
A-7
A.4.2 Byte access
Following are the cases of byte access.
The I/O port is connected to the low bank of the data bus.
- Word Read Operation
The 1st data byte (even address data) transferred from C is
latched in the buffer 3 temporarily.
The following second byte data (odd address data) is
transferred to the DIS-D8 ( B ) through the trsansceiver 4.
At this time, the 1st data byte in the buffer 3 is enabled
to be output to the data bus D7-DO ( A ), thus, l6-bit data
is transferred to the cpu. The transceiver 1 is disabled
while the 2nd data byte is being transferred.
1st data byte
2nd data byte
C--~-'~3
-.A
C
.. B
-4
(refer to Figure A-2)
- Word Write Operation
l6-bit write data from the cpu is output to A and B through
the data bus DIS-DO.
The low bank data D8-DO is transferred to C through the
transceiver 1 as the 1st data byte.
The high bank data DlS-19 is transferred to C through the
transceiver 2 and trnasceiver 4 as the 2nd byte.
1st data byte
2nd data byte
A--~-~1
"C
B
-'4
-'2
-.C
(refer to Figure A-2)
The transceiver 1 is disabled during the 2nd byte transfer.
The buffer 3 is disabled while write operation is being
executed.
This word/ byte conversion occupies 12 system clock cycle
time.
A-8
A.4.3 DMA operation
- Byte DMA operation
DMA data transfer between I/O port connected to the low bank
data bus and memory location of odd address is as follows.
Case of I/O to Memory
"D
Case of Memory to I/O
.. c
(refer to Figure A-2)
- Word DMA operation
The GA is not concerned with the word DMA operation.
~.5
Address Generation
System address busses SA19-SAO are generated in this GA,
and each of these lines are used for the following purposes.
- CPU address output
SA19 - SA9
- DMA address output
SA19 - SA9, XA8
- Refresh address output : SA8 - SAO
To generate the system address, following three functional
blocks are applied.
A.5.1 SA19 -SA17
SA19 - 17 come from the CPU and from the Memory Mapper GA.
They are wired ORed.
I
Alq-A17
I
r
;:;
ALE
L.CH
.-
CPHLD~
FIGURE A-3
\=:J
>
>
SEL
REFADO
CPHLDA
+DMACK
System Address Bus 19 - 17
A-9
<:lI.1Q"':'<;A17
">
A.S.2 SA16 - SA9, XA8
These lines are used to output the CPU address A16-A9 to
SA16 - SA9 or output the DMA address PGA16, XD7 - XDO to
SA16 - SA9, XA8.
LA 16
A9
LCH
ALE
SEL
SAlfi-SAQ
(PHLDA
AEN1 +AEN2
>
I XD7-XDI
ADSTB?.
>
LCH
SEL
r---
t
SADREN
f---
->
AEN2 •
-
AEN1
---ADSTBl
•
XA8
LCH
AENl •
PGA16
FIGURE A-4
System Address Bus SA16 - 9, XA8
A.S.3 SA8 - SAO
These address lines are used to output memory refresh
address. The address is generated by refresh address
counter and it is output at every 15 micro seconds.
DRVR
CTR
,..
REFADO
S~B
s~o
>
REFQ1,..
FIGURE A-5 System Address Bus SA8 - 0
A-IO
>
APPENDIX B
MEMORY MAPPER GA (Gate Array)
B.l GENERAL
The Memory Mapper Gate Array is a flat package typed chip
with 100 lead pins, and it contains the following functions.
- Generation of the DMA memory address.
- I/O address decoding.
- Other various functions such as;
* ROM control signal
*
*
*
Timer clock
Parity error detection control
NMI (Non Maskable Interrupt) signal
51
80
..w._ _ _ _.-Y""'- 50
31
100
30
1
B-1
B • 2 BLOCK DIAGRAM
>
CPU
Xn7-Xnn
Interface
CPU commands
8bitx 16
<---
Latch
A23-A16
>
Register
I
(SA9)
XA8 XAO
>
Address
I--I---
>
Select
I
DACK7-DACKO
10CONT
>
1/0
Command
10CS
1/0 control Lines
Decoder
FIGURE B-1
Memory Mapper GA Block Diagram
B-2
/
B.3 SIGNAL DESCRIPTION AND PIN ASSIGNMENT
TABLE B-1
Pin
1/0
Pin Description
Signal Name
1
I
CPHLDA
2
I
MIO
3
4
0
VCC
SPK
S
0
KBCCS
6
0
LROMCS
7
0
ROMOE
8
0
SBHE
9
I
MEMR
10
I
LATAO
11
I
CNVALE
12
0
PGA16
Description
CPU hold acknowledge signal.
When this signal is high, the system bus is used by
any other controller than the CPU.
If this signal is low, the system bus is used by the
CPU.
Memory I/O select signal.
When this signal is high, memory cycle is being
executed, and when low, I/O cycle.
+SV
Buzzer signal from the external circuit.
Keyboard controller select signal.
This signal becomes low when the I/O port
address is 062H/ 068H and also KBSEL = 0, or
when the address is 8062"H/ 8068H.
Chip select signal to the BIOS ROM.
This signal is active low.
The address ranges are:
OEOOOOH-OFFFFFH
FEOOOOH-FFFFFFH
Output enable signal to the BIOS ROM.
This signal is generated by the ROM chip select
signal and memory read command.
This signal is active high.
System bus high enable signal.
This signal generates the data bus high enable
signal. This signal is active low.
Memory read command.
This signal comes from the DMA controller GA
and it is generated by SAO.
When this signal is high, the low bank of the
data bus is selected.
Dummy address latch enable signal for the 2nd
byte transfer in 16/8 bit conversion.
This signal also generates output enable signal of
the 1st byte which has been latched.
Address line from the Memory Mapper register
during the DMA cycle or memory refresh cycle.
This signal is used as the system address SA 16
durinQ the slave DMA oQeration.
B-3
Pin
I/O
Signal Name
13
0
NDPCS
14
I
DIRC
15
16
I
GND
HCS1
17
0
DBlEN
18
0
DBHEN
19
0
lATDEN
20
0
NMI
21
0
BSYCPU
22
0
10RDY
23
0
ROMCS
24
I
RAM16
25
0
PPICS
Description
This signal defines that the NDP (80287) has been
selected. If this signal is low, the system data bus
is disabled. When OF8H*SMI0*INTA 1 is made,
this signal is activated.
Direction signal for CPU data transfer.
When this signal is low, read data is on the data
bus, and when it is high, write data is on the data
bus.
Ground
HDD address decode signal 1 (not used).
Data (low bank) enable signal.
This signal is generated from lATAO signal. This
signal is active high.
Data bus (high bank) enable signal.
This signal is generated from SHBE signal.
This signal is active high. each data bus is
controlled inside the GA.
This signal is read enable signal for the 1st byte
transfer in 16/8 bit conversion.
The 1st byte has been stored in a buffer of the
Bus Controller GA during the 1st read cycle.
NMI interrupt signal. It is active high.
This signal is output when memory parity error or
any error from the expansion unit occurs.
CPU busy signal to NDP.
This signal is active low.
I/O channel ready signal:
This signal is used to expand the NDP reset signal
in order to meet the timing specification of the
NDP.
ROM chip select signal. This signal is active low.
The address ranges are:
OFOOOOH-OFFFFFH
FEOOOOH-FFFFFFH
This signal becomes low when the system
memory (0-640 Kbytes) is accessed. This signal
enables internal parity error detection flag.
PeripheralI/O select signal.
This signal becomes active when the I/O port
address is 06*H-07*H.
This signal is active low.
B-4
Pin
1/0
Signal Name
26
I
PUCLR
27
I
10CHK
28
Vcc
29
I
INTA
30
I
REFRSH
31
I
TM20UT
32
I
RESET
33
I
lOR
34
I
lOW
35
I
ALE
36
0
TMCLK
37
0
TMGATE
38
0
PITCS
39
0
PIC1CS
40
GND
Description
Power on reset signal. This signal is active low.
This signal inhibits real timer write command
during the reset period.
Error signal from an external expansion unit. If
this signal is low, the NMI flag becomes effective.
+5V
This signal is to read the interrupt vector address.
This signal comes from the interrupt controller
(U8259A).
DMA refresh enable signal. This signal is active
high. The Memory Mapper address A23-A 17
and PGA 16 are output during the memory
refresh operation.
Buzzer sound signal used in the system.
This signal comes from the timer (U8254).
System reset signal.
This signal is active high.
1/0 read command. This signal is active low.
It is used to write memory address register in the
GA, system status, and also to generate
command.
1/0 write command. This signal is active low.
It is used to write memory address sregister in the
GA, or to generate various commands.
Address latch enable signal from the cpu.
This signal is active high.
Clock signal (1.19 MHz) to the timer (U8254).
Count control signal to the timer.
When this signal is low, it disables from counting,
and when it is high, counting is enabled.
Timer (U8254) chip select signal.
This signal is active low, and becomes active
when the 1/0 port address is 04*H-05*H.
Chip select signal to the master interrupt
controller (U8259A). This signal is active low, and
becomes active when 1/0 port address is
02*H-03*H.
Ground
B-5
Pin
110
Signal Name
41
0
DSTRB
42
43
44
45
46
47
48
49
50
I
I
I
I
I
I
I
I
0
SA14
SA15
DACK6
DACK2
DACK4
DACKO
DACK7
DACK3
IRQ13
51
I
MASTER
52
KBCCS2
53
54
55
I
I
Vcc
NDPER
NDPBS
56
0
KBSEL2
Description
Data read strobe signal to the real timer.
This signal becomes active when read operation
to the 1/0 port address 071 H is executed.
This signal is active low.
Address line bit 14.
Address line bit 15.
DMA acknowledge signal from channel 6.
DMA acknowledge signal from channel 2.
DMA acknowledge signal from channel4.
DMA acknowledge signal from channel O.
DMA acknowledge signal from channel7.
DMA acknowledge signal from channel 3.
Interrup_t request signal when NDP error occurs.
System occupation request signal from the
external processor.
This signal is active low.
Chip select signal forthe external 101 keyboard
controller.
+5V
NDP error signal.
NDP busy signal.
This signal indicates which of the two keyboard
controllers (the internal one or excternal one) is
selected.
When this signal is "1" it shows that the external
controller is selected.
Address line bit 9.
This signal is ORed signal of CPHLDA and
MASTER signals. This signal is low except in the
DMA mode.
Reset command to the NDP.
This signal is active high.
Chip select signal to the slave interrupt controller
(U8259A). This signal is active when the 1/0 port
address is OA*H-OB*H.
This is active low.
Chip select signal to the master DMAC (U8237).
This signal is active when the 1/0 port address is
OC*H-OD*H. This is active low.
HDD address decode signal 0 (not used).
Buzzer sound siqnal from the MODEM card.
I
57
I
SA9
58
0
DMACK
59
0
NDPRST
60
0
PIC2CS
61
0
DMA2CS
62
63
0
HCS0
MDSPK
I
B-6
Pin
I/O
Signal Name
64
I
PDINL
65
GND
66
I
PDINH
67
0
RETIMW
68
0
STEP
69
I
RWSEK
70
I
FDSTEP
71
0
DMA1CS
72
0
A23
73
74
75
76
77
78
79
80
0
0
0
0
0
0
0
I
A22
A21
A20
A19
A18
Vcc
A17
$14MHZ
81
I
XAO
Description
Parity error signal from the system memory (low
bank).
Ground
Parity error signal from the system memory (high
bank). This signal is active low.
It makes an NMI interrupt signal at the rising
edge of the memory read if an error occurs.
Data write command to the real timer.
This signal becomes active when write operation
to the 1/0 port address 071 H is executed. This
signal is active low.
Step signal to the FDD.
This signal is active high.
Seek enable signal to the FDD.
When this signal is low, FD seek operation is
enabled, and when it is high, FDD read orwrite
operation is enabled.
Step signal from the FDC.
This signal is active high.
Chip select signal to the DMAC (U8237A).
This signal becomes active when the 1/0 port
address is OO*H. This signal is active low.
A23--A 17 are used as page address during the
DMA operation. The page address from the
internal register is output when the DMA
acknowledge signal is low.
Address line bit 23.
Address line bit 22.
Address line bit 21.
Address line bit 20.
Address line bit 19.
Address line bit 18.
+5V
Address line bit 17.
Clock signal (14.31818 MHz) to the timer (U8254).
Each of XA9--XAO is X address which is same as
the system address. They are used to decode the
1/0 port address or to specify the DMA page
register for readl write operation to the page
address reqister
B-7
Pin
I/O
Signal Name
82
83
84
85
86
87
88
89
90
I
I
I
I
I
I
I
I
XA7
XA6
XA5
XA4
XA3
XA2
XA1
XA8
GND
91
0
XDREAD
92
I/O
XDO
93
94
95
96
97
98
99
I/O
I/O
I/O
I/O
I/O
I/O
I/O
XD1
XD2
XD3
XD4
XD5
XD6
XD7
100
I
PDPEN
Description
X address line bit 7.
X address line bit 6.
X address line bit 5.
X address line bit 4.
X address line bit 3.
X address line bit 2.
X address line bit 1.
X address line bit 8.
Ground
Read enable signal to the peripheralI/O which is
connected to the X data bus.
This signal is active low.
Each of XD7 - XDO is X data bus. Read or write
operation to the DMA page register and read
operation to the system status are performed
through this bus.
X data bus bit O.
X data bus bit 1.
X data bus bit 2.
X data bus bit 3.
X data bus bit 4.
X data bus bit 5.
X data bus bit 6.
X data bus bit 7.
This signal indicates whether the plasma display
panel is open or closed.
When this signal is" 1", it means that the panel is
open, and therefore the plasma display can be
used.
B-8
B • 4 DNA MEMORY ADDRESS
DMA page address is stored in the DMA page address register
in the Memory Mapper GA before it is used in the DMA cycle.
The DMA page address register has 8 bit length and it is
output to the address lines A23 - Al7 and PGAl6 during the
DMA cycle.
Each DMA channel has a DMA page address register and address
is assigned as follows.
TABLE B-2 Address Assignment of DMA Address Register
Adress
Channel
DMA
081H
082H
087H
089H
08AH
08FH
Channel 2
Channel 3
Channel 0
Channel 6
Channel7
* Refresh
Slave DMA
II
II
Master DMA
II
II
To store the DMA page address, the address lines XA are
decoded and the data on the XD lines are stored in the
selected register.
<
>
CPU
XD7 .l(nn
Interface
CPu commands
Latch
8bit x 16
I<=-
Register
(SA9)
I
XA8 XAO
>
Address
I--f--
>
Select
I
DACK7 DACKO
>
FIGURE B-2 DMA Page Address Register
B-9
A23 A16
>
B.5 I/O Decode Control
Address lines SA9 and SA8-SAS are used to generate the I/O
port select signal.
Address on the XA lines are decoded for I/O port chip select
if it is not in the DMA cycle.
The following table shows the address assignment to each I/O
port chip.
TABLE B-3 Address Assignment to the I/O Port
Address
OO*H-01*H
02*H-03*H
04*H-05*H
06*H-07*H
08*H-09*H
OA*H-OB*H
OC*H-OD*H
OE*H-OF*H
Signal Name
DMA1CS
PIC1CS
PITCS
PPICS
PREGCS
PIC2CS
DMA2CS
C287
Descri ption
Slave DMAC select
Master Interrupt Controller Select
Timer Chip Select
Peripheral 1/0 Select
Reqister Select within the GA
Slave Interrupt Controller Select
Master DMAC Select
NDP reset
B-10
APPENDIX C
OMA GA (Gate Array)
C.l GENERAL
The DMA Gate Array is a flat package typed chip with 100
lead pins.
The DMA Controller Gate Array has the following functions.
- Clock generator
- CPU clock
- DMA clock
- Keyboard clock
- System timing control
- Memory control (ROM, RAM)
- DMA control
- Memory refresh control
- DMA ready control
- Command generation
51
80
~--------~~-50
100
~m-________~~-~31
30
1
C-l
C. 2 BLOCK DIAGRAM
>
Command
~
CPUCLK
Counter
&
Latch
16MHz
SYSCLK
DMACLCK
CPRDY
Generator
Commands
(MEMRIW, IORIW, etc.)
DMAMRD
51,50
R5T CMD
MIO
IDMA
Ready
.. Gen.
..
•
..
Shutdown
Gen .
I
~
--:..A:.::E.:.:.N_ _ _ _ _ _ _ _....
DMHRQ
FREQ2
CPHLDA
~,3-AlZ
FIGURE C-I
I
..
•..
>
BUS
Control
DMAI
Refresh
&
Latch
Memory
Decoder
DMARDY
SHUTDOWN
BCHGEN
BCHGDR
BCHFEN
DMAACK
REFQ1
REFAQO
RASH, L
CASO, 1,2
VRAMCS
Latch
ROM~~
C-2
:
BCHGDR
&
DMA GA Block Diagram
•
.
•
•
•
C.3 SIGNAL DESCRIPTION AND PIN ASSIGNMENT
TABLE C-l
Pin
1/0
Signal Name
1
I
CPHLDA
2
0
ALE
3
Pin Description
VCC
4
I
AEN1
S
1/0
lOR
6
1/0
lOW
7
I
MIO
8
0
CLK4
9
1/0
MEMR*
10
I/O
MEMW*
11
I
SEL4M
Descri ption
CPU hold acknowledge signal.
When this signal is high, the system bus is used by
any other controller than the CPU.
If this signal is low, the system is used by the CPU.
CPU address latch signal.
The address data is latched at falling edge of this
signal.
+5V
Address enable signal during the slave DMA
operation. The DMA address is enabled when
this signal is low.
1/0 read command.
1/0 read operation is executed when this signal is
low. In the master mode, this becomes an input
signal.
1/0 write command.
1/0 write operation is executed when this signal is
low. This signal is output from the DMAC
(U8237) during the DMA operation. In the
master mode, this becomes an input signal.
Memory I/O select signal.
When this Signal is high, memory cycle is being
executed, and when this signal is low, it is 1/0
cycle.
12MHz clock (not used).
Memory read command. This signal is also
output during the memory refresh operation.
Memory read operation is done when this signal
is low. In the master mode, this becomes an
input signal.
Memory write command. The write operation is
done when this signal is low. In the master
mode, this becomes an input signal.
Clock rate select sig nal.
This signal is generated by the keyboard
controller to select CPU clock rate.
When this signal is low, the CPU clock rate is 12
MHz, and when it is high, the CPU clock rate is 6
MHz.
C-3
Pin
I/O
Signal Name
12
I
CPUA20
13
I
RSTCMD
14
I
AO
15
GND
16
0
DIR
17
0
FREQ
18
0
BALE
19
0
NPCK
20
I
A01
21
I
A17
22
23
I
I
A18
A19
24
liD
A20
25
26
27
28
29
I
I
I
I
I
A21
A22
A23
Vcc
PAKI
Description
Output address line from the CPU.
This signal is controlled inside the GA, depending
on the CPU mode {Reali Protect}.
In the real mode, A20 is fixed to low, and in the
protect mode, CPUA2 is output to A20.
CPU reset command.
This signal is effective when it is low, and it
outputs the CPU reset signal.
CPU address line bit O.
This signal generates SAO inside the GA.
Ground
This signal shows the direction of data transfer.
When reading, this becomes low.
Refresh timing signal {not used}.
In the CPU mode, this signal functions exactly like
ALE. Apart from the CPU mode, it is always high.
Clock signal8MHz forthe NDP {80287}.
CPU address line bit 1:
This signal is used to generate the "shut down"
signal.
CPUI Memory mapper address.
Memory Mapper address is input during the
DMA operation. This signal is used to decode
each memory size.
CPUI Memory Mapper Address line bit 17.
Address line bit 18.
Address line bit 19.
Address line bit 20.
This signal is output during the CPU operation,
and when used in the real mode, it is fixed to
low, while in the protect mode, CPUA2 signal is
output. When the CPU is inactivated, this
becomes an input signal.
Address line bit 21.
Address line bit 22.
Address line bit 23.
+ 5V
Input PEACK siqnal from the CPU.
C-4
Pin
I/O
Signal Name
30
I
REAL
31
0
CLK42
32
0
AS18
33
I
$24MHz
34
0
CPRDY
35
0
CPUCLK
36
37
38
39
40
41
I
I
I
I
I
S1
SO
NDPCS
TMIOUT
GND
TEST
42
I
PPICS
43
44
I
0
PUCLR
DMACLK
45
0
DMARDY
46
0
DMHLDA
47
I
DMHRQ
48
I
DMAMRD
49
I
DACK4
50
I
XA4
Description
RealI Protect mode select signal.
When this signal is low, the CPU is in the real
mode, and when it is high, the CPU is in the
protect mode.
Keyboard controller clock signal (6MHz).
Address strobe signal to the real timer
(MC146818). This signal is active low.
System clock signal (24 MHz)
CPU ready signal.
This signal is active low, and is sampled by the
CPU at the leading edge of the Tc cycle.
CPU clock signal.
Either 24 MHz or 12 MHz is output by the clock
selection control.
CPU bus status bit 1.
CPU bus status bit o.
NDP(80287) chip select signal.
Memory refresh request signal
Ground
Test signal for the GA. This signal is active high.
Peripheral 1/0 select signal. This signal generates
real timer address strobe signal. When 1/0
address is 06*h/07*h, this signal becomes low.
Power on reset signal. This signal is acitive low.
DMA clock signal.(4MHz or 2MHz)
Ready signal to the DMAC One wait cycle is
given in the DMA operation.
When this signal is low, it gives the wait cycle,
and when it is high, DMA operation is is enabled.
Ack hold signal to the external DMAC
When this signal is high, it allows the DMA
operation.
CPU hold request signal from the external DMAC
This signal is acitve high.
Memory read command from the DMAC
This signal is active low.
Slave DMAC cycle signal. This signal is active low.
The master DMAC can not output addressl
command signal while this signal is active.
Address sianal. CPUI DMA address bit 4.
C-5
Pin
1/0
Signal Name
51
1/0
XAO
52
0
BUSE N
53
Vcc
54
I
PAKO
55
0
SMEMR*
56
0
SMEMW *
57
I
10RDY
58
0
DMAAEN
59
I/O
SBHE
60
I
1016
61
I
MEM16
62
0
SYSCLK
63
0
DM1HLD
64
65
I
TEST2
GND
66
0
AMEMR
67
I
TEST1
Description
Address signal. This signal is from SAO.
It is input during the slave DMAC operation.
Data Enable Signal:
This signal is used to enable data bus.
+5V
PEAK output signal to the NDP:
The expanded PAKI (29 pins) signal with one
more CPU clock in order to meet the timing
specifications of the NDP.
Memory read command. This signal is output to
the 8-bit expansion bus.
It is not output to any address of more than 1 M
byte. This signal is active low.
Memory write command. The output condition
of this signal is same as that of the SMEMR signal.
CPU ready control signal from outside the GA.
When this signal is low, a wait cycle can be qiven.
Address enable signal during the DMA
operation. This signal is acive low.
System bus high enable signal.
This signal enables the high bank of the data
when it is active. In the master mode, this signal
becomes an input signal.
This signal defines that 16-bit type of I/O device is
serviced in 110 command execution.
16-bit memory access signal.
This signal is to indicate that 16-bit type memory
is accessed.
System clock.
One-third of the CPU clock frequency is output.
This signal is output when DMA request signal
comes from the slave DMAC. When DACK4 is
low, this signal becomes active (high).
The slave DMAC starts DMA operation by this.
GA test signal: This signal is active high.
Ground
Memory read signal to the T3200 system memory
(including expansion memory).
GA test sianal: This sianal is active low.
C-6
Pin
I/O
Signal Name
68
I
REFRSH
69
0
INTA
70
0
XMEMW
71
I/O
SAO
72
I/O
XIOW
73
I/O
XIOR
74
I
SA16
75
76
77
78
I
SA15
CHK1
OWAIT
Vcc
0
I
79
0
CPURST
80
I
AEN2
81
I
AMEMW
82
I
RAMOP
83
0
CRTMCS
84
0
RST
85
0
REFIN
86
0
REFQ1
87
0
REFADO
Description
Refersh enable signal.
When this signal is high, it enbales internal
memory refresh circuit.
Interrupt vector read signal.
When this signal is low, system address (SAO)
becomes low.
Memory write signal output from the DMA.
When not in the DMA mode, MEMW signal is
output.
System address. (The lowest bit)
I/O write command from the DMA.
Active low when CPU mode lOW signal is output.
I/O read command from the DMA.
Active low when CPU mode lOR signal is output.
System address line bit 16.
SA 16 and SA 15 are used to select the video
memory chips.
System address line bit 15.
Internal monitor signal in the GA. (not used).
It gives 0 wait during the CPU cycle.
+5V
CPU reset signal. This signal is active high.
When switching the power on or off, this signal
becomes active.
Address enable signal during the master DMAC
operation. This signal is active low.
Memroy write signal to the T3200 system
memory (including eXJ~anion memory)
This signal enables or disables to access sytem
memory (512 K-640 Kbytes).
When this is "0", access is enabled, and it is
always set to "0" in this system.
Color graphic video memory select signal.
(OB8000H-OBBFFFH)
System reset. This signal becomes active when
the power is switched on.
Memory refresh enable signal.
This signal is active high.
This signal is from the memory refresh control
counter. When this signal is low, the refresh
address is output.
Memory refresh address. (The lowest bit)
C-7
Pin
I/O
88
0
CNVAO
89
0
BCHGDR
GND
90
91
--
Signal Name
O~
.... BC-HG-EN·
92
_0
C:PVHRO
93
0
CHK2
94
0
RAM16
95
0
CNVALE
96
0
LlMSL
97
0
ROMCS
98
0
LATAO
-- --.-------= ---- ---
...
Description
This signal is dummy address for 2nd byte
transfer in 16/8 bit conversion.
The 1st byte is latched at raising point of this
signal while read operation is being executed.
This signal specifies the direction of the 2nd byte
transfer in 16/8 bit conversion.
When this signal is low;
High bank ~ Low bank
When this signal is high;
Low bank ~ High bank
Ground
This signal is an enable signal for the 2nd byte
tr.;:n~'fer- in·~1£/3 hih:-oniieG~oj')·.--·- ..... - -.--.-.- .~--.--This signal is active low.
CPU hold request signal. This signal is generated
when the DfVIHRQ signai ishlcih. ~
Internal monitor signal inside the GA.
System memory (0-640 Kbytes) access signal.
This signal is active low. It enables the parity
error detection.
This signal is to latch the dummy address of the
2nd byte transfer in 16/8 bit conversion. This
siqnal is active high.
Output signal from the EMS GA:
This signal indicates that the memory to be
accessed is the system memory, and that neither
VRAM nor the memory connected to the
extended bus is accessed.
BIOS ROM chip select signal. This signal is active
low. The decode ranges of the address are:
OEOOOOH-OFFFFH
FEOOOOH-FFFFFH
System address inverted signal during the CPU
cycle. When this signal is high (SAO is low), low
data bus enable sianal is aenerated.
- -
C-8
- - - -
~-
Pin
I/O
Signal Name
99
I
BHE
100
0
SMMW
Description
High data bus enable signal.
When this signal is low, high bank of the data
bus is accessed.
Memory write signal supplied to the EGA GA:
This signal is active when write access to the
memory space between 0-1 Megabyte is
executed.
In the CPU mode, signals with the mark * are output, only when VRAM or the
memory connected to the expanded bus is accessed.
C-9
C • 3 CLOCK GENERATOR
This circuitry is to generate the following cloks.
The original clock signal is a 24 MHz clock.
Fast
24 MHz
8 MHz
4 MHz
CPU Clock
System clock
DMA clock
Slow
12 MHz
4 MHz
2 MHz
Following are the timing chart of the clocks.
$24MHZ; 100
CPUCLK; 100
6 min.--.
SYSCLK; 100
13min.~
DMACLK; 100
16min.~
~
FIGURE C-2
Clock Timing Chart
C-IO
C • 4 DNA CONTROL
"
/\
/\
\,
"
<:r1.l5.-
0
Memory
>
·<;AI
<:1\ l'
ODD
~
C; A P.
<;D7-SD
~
XA7-XAO
XD7-XDO
DCHGEN
lIE
CPU
CPUHRQ
CPHLDA
t
DCHGDF
DMA
GA
EVEN
/I
DMHRO
DMHLDA
lIE
~
lOR
lOW
DMAC
t
DRQX
I/O
DACKX
Port
I
t
FIGURE C-3 DMA Controller
This circuitry controls the DMA operation.
The DMA GA receives DMHRQ signal from the DMAC, then the GA
responds to the CPU with CPUHRQ signal.
After receiving CPHLDA signal from the CPU, the GA responds
to the DMAC with DMHLDA signal.
The DMAC starts DMA operation when it receives the DMHLDA.
The DMAC prepares the DMA address on the system address bus
and lOR/lOW signal to the DMA GA for the bus control.
If
the I/O port is byte oriented device, the bus controller GA
is used for data bus switching (low bank to high bank or
vice versa).
C-ll
APPENDIX 0
I/O CONTROLLER GA (Gate Array)
D.l GENERAL
The I/O Controller Gate Array is a flat package type chip
with 100 lead pins.
This Gate Array has the following functions.
- FDD control
- Printer control
51
80
50
31
100
30
1
D-l
D.2 BLOCK DIAGGRAM
r
.> FDD
;; CPU
SD7-SDO
SA1 SAO
~
I lOR lOW
~
FDD Command
>
nn
>
Command
Register
Interface
>
FDD
Command
Register
PRT Inmm ..
Printer
"> Bus
Pf)7_Pf)(l
>
Driver
SIOCS
SA9-SAO
>
1110
Decoder
I
--,-~S:"';L~-'-'
p;. :S;. : .O_ _ _ _--.!:: Pre- Compo
FDCWD
~D~RQ~F~D~(
____
$16MHz
$19MHz
HDDCS
CRTCS
I
I-_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _W_R_D_A_TA_ _...
~.~ID_el_a_Y__~----------------D-L-D-RQ--'-_~.~
.1
~~.!..!.!...W=--_ _ _-...
$HIFRQ
FOC
Clock
Switch
FIGURE D-l
#CKFDC
I/O Controller GA Block Diagram
D-2
:
D.3 SIGNAL DESCRIPTION ADN PIN ASSIGNMENT
TABLE D-l
Pin
liD
Pin Description
Signal Name
1
liD
SDO
2
3
liD
4
5
6
7
8
9
liD
liD
liD
liD
liD
liD
SD1
Vcc
SD2
SD3
SD4
SD5
SD6
SD7
10
0
CRTCS
11
I
SA2
12
13
14
15
16
17
18
19
20
I
I
I
I
I
I
I
I
SA3
SA4
SAS
GND
SA6
SA7
SA8
SA9
SA1
21
I
PDSOO
22
0
DRQ2
Description
Each of SD7-SDO is system data bus.
For printer control, this signal is used;
- to output printer data.
- to read pri nter status.
- to decode printer command.
For FDD control, it is used;
- to decode FDD control command.
System data bus bit o.
System data bus bit 1.
+ 5v
System data bus bit 2
System data bus bit 3
System data bus bit 4
System data bus bit 5
System data bus bit 6
System data bus bit 7
liD port select signal to the color graphics
controller. This signal is active (low) when the liD
~ort address is 3D*H.
*=O-F
SA9-SAO is system address. They are used to
decode the liD port addresses such as;
Printer/ FDDI Color Graphics port!
HDD port! RS232C
System address line bit 2.
System address line bit 3.
System address line bit 4.
System address line bit 5.
Ground
System address line bit 6.
System address line bit 7.
System address line bit 8.
System address line bit 9.
System address line bit 1.
Write precompensation control.
This signal is fixed to low in this system.
DMA cycle request signal from the FDe.
This siqnal is active hiqh.
D-3
Pin
I/O
Signal Name
23
I
TC
24
0
FDAKTC
25
0
FDACK
26
I
DRQFDC
27
I
PDS01
28
Vec
29
0
IRQ6
30
I
DMACK
31
I
DACK2
32
I
EXTFDD
33
I
$16MHZ
34
I
$19MHZ
35
0
$CKFDC
Description
This signal is a terminal count signal that
indicates the end of the DMA data transfer.
This signal is active high.
It comes from the DMAC (U8237).
Terminal count signal to the FDC
This signal is active high. It is generated from the
TC signal.
DMA acknowledge signal to the FDC
This signal is active low.
DMA cycle request signal from the FDC
This signal generates DRQ2 to be sent to the
DMAC This signal is active high.
Write precompensation ON/ OFF signal.
This signal is fixed to high in this system.
+ 5V
Interrupt request signal which the FDC outputs at
the end of command execution.
This signal is active high, and goes to the
U8259A.
This signal inhibits output of the I/O port address
during the DMA operation.
When this signal is low, decoding the address is
enabled, and when high, it is disabled.
This is acknowledge signal to DRQ2 which is DMA
data transfer request signal.
This signal is active low.
This signal is to switch the printer port connector
to the external FDD.
When this signal is low, the connector is for the
printer port, and when it is high, the connector is
for FDD port.
Basic clock to the FDC and VFO.
16 M Hz (cycle time is 62.5 ns.)
Basic clock to the FDC and VFO.
19.2 MHz (cycle time is 52.08 ns.)
FDC clock. Frequency of the clock depends on
the data transfer rate.
250 kbps; 8 MHz, 16 MHz
300 kbps; 4.8 MHz, 19.2 MHz
500 kbps' 4 MHz 16 MHz
D-4
Pin
1/0
Signal Name
36
0
$HIFRQ
37
0
WINDOW
38
0
WCLK
39
0
FDCCS
40
GND
41
I
lOR
42
I
lOW
43
0
FDSRST
44
I
FDCWD
45
I
FDCINT
46
0
XF7RD
47
I
PS1
48
I
PSO
49
I
SYNC
Description
VFO clock. The clock frequency depends on the
data transfer rate.
250 kbps; 8 MHz
300 kbps; 9.6 MHz
500 kbps; 8 MHz
Window signal generated from the internal
circuit. This signal is active high.
FDD data write clock to the FDC
The cycle time of this signal is one-eighth of
CKFDC
Chip select signal to the FDC (U765).
This signal is active (low) when the 1/0 port
address is 3F4HI 3F5H.
Ground
1/0 read command.
This signal is active low.
1/0 write command.
This signal is active low.
FDC reset command. This signal is active high,
and is issued by the command to 3F2H (data is
D2).
Write data from the FDC
This signal is active high.
Interrupt signal from the FDC
This signal is active high, and generates IRQ6
signal.
This signal is to read the status of FDD disk
change. This signal is active (low) when read
address is 3F7H.
PS 1 and PSO are precompensation control signals.
These signals are output from the FDC
PS1
PSO
Time
No delay
Low
Low
225-250 nsdelayed
High
Low
225-250 nsquickened
High
Low
Precompensation control siqnal.
This signal is to control the VFO operation mode.
When this signal is low, it inhibits the read
operation, and when it is high, the read
operation isenabled.
D-5
Pin
I/O
Signal Name
50
I
FDCWE
51
0
IRQEN
52
0
CCMICS
Vcc
53
54
0
SWMONA
55
0
SWMONB
56
0
INDRVB
57
0
SWFDA
58
0
59
I
SELECT
60
I
BUSY
61
0
CBDIR
62
I
STROBE
63
I
AUTFD
XRATEO
Description
Data write enable signal to the FDD.
This signal is active high.
Printer interrupt enable signal.
This signal is active low. This signal is issued by
the command to 372H.
RS232C (Primary) select signal.
This signal is active (low) when the I/O port
address is 3F8H-3FFH.
+5V
FDD motor on signal to the 1st FDD.
This signal is active high. ON/OFF is controlled by
the command to 3F2H.
FDD motor on signal to the 2nd FDD.
This signal is active high. ON/OFF is controlled by
the command to 3F2H.
Internal FDD (2nd FD) select signal.
This siqnal is active hiqh.
Internal FDD (1st FDD) select signal.
This signal is active high.
This signal defines the FDD transfer rate.
When this signal is low;
500 kbps-250 kbps
When this signal is high;
300 kbps
This signal is issued by the command to 3F7H.
Printer select command. This signal is active low.
It can be read from address 3F7H. This signal
becomes write gate signal when it is in the
external FFD mode.
Printer busy status. This signal is active high.
It can be read from the address 371 H.
This signal becomes motor ON/OFF signal when it
is in the external FDD mode.
Read enable signal to the I/O peripheral which is
connected to the external bus. This type of bus
does not exist in this system.
Printer strobe signal. This signal is active high.
It can be read from address 371 H.
Printer auto-feed command. This signal becomes
low density signal when it is in the external FDD
mode.
D-6
Pin
I/O
Signal Name
64
I
PDS10
65
GND
66
0
CCM2CS
67
I
PE
68
I
PINIT
69
I
SUN
70
I
ACK
71
I
EROR
72
0
EXFDWE
73
0
SWFDB
74
0
DTAREA
75
0
EN96M
76
0
WN
Description
FDD precompensation ON/OFF signal.
This signal is not used in this system.
Ground
RS232C (Secondary) select signal.
This signal is active (low) when the 1/0 port
address is 2F7H-2FFH.
Paper end status from the printer.
This signal is active high. It can be read from the
address 371 H. This signal becomes write data
signal when it is in the external FDD mode.
Printer initial command. This signal is active high.
It can be read from address 372H. This signal
becomes direction signal when It is in the
external FDD mode.
Printer select command. This signal is active
high. It can be read from address 372H.
This signal becomes step signal when it is in the
external FDD mode.
Printer ACK status. This signal is active high.
It can be read from address 371 H.
Select signal is input when it is in the external
FDD mode,.
Printer error status. This signal is active high.
It can be read from the address 371 H. This signal
becomes SIDE signal when it is in the external
FDD mode.
Write gate signal in the external FDD mode.
System FDD (2nd FDD) select signal.
This signal is active high ..
Read control signal to the VFO.
When this signal is low, read operation is
disabled, and when high, it is enabled.
This signal is to change the value of resistance in
the VFO circuit when the data transfer rate is 300
kbps.
This signal is active high.
Window signal from the VFO.
This sianal is active hiah.
D-7
Pin
77
I/O
0
78
Signal Name
MINI
Vcc
79
0
WRDATA
80
0
HDDCS
81
0
PRTDIR
82
I/O
PD7
83
84
85
86
87
88
89
90
I/O
I/O
I/O
I/O
I/O
I/O
I/O
PD6
PDS
PD4
PD3
PD2
PD1
PDO
GND
91
0
SLCTIN
92
0
AUTFD
Description
This signal defines the formatting mode of the
disk.
When this signal is low;
9 sectors/ track
When this signal is high;
15 sectors/ track
+ 5V
Write data to the FDD. This signal is active high.
The precompensation is given to this write data.
Select signal to the external HDC.
This signal is active (low) when the I/O address is
170H-177H.
This signal controls the direction of printer data
port.
When this signal is low;
External ~ Internal.
When this signal is high;
Internal ~ External.
This function is ignored when it is in the external
FDD mode.
Each of PD7-PDO is a printer or parallel data IN
bus. When it is in the external FDD mode, each
bus is in the high impedance state.
When printer is connected, they are in the
output mode.
Printer data bus bit 7.
Printer data bus bit 6.
Printer data bus bit s.
Printer data bus bit 4.
Printer data bus bit 3.
Printer data bus bit 2.
Printer data bus bit 1.
Printer data bus bit o.
Ground
Printer select command. This signal is active
high. This signal is issued by the command to
address 372H.
Printer auto-feed command. This signal is active
high, and is issued by the command to address
372H.
D-8
Pin
1/0
Signal Name
93
0
INIT
94
0
STROBE
95
I
DIREN
96
0
FDSLSEN
97
I
SAO
98
I
RST
99
I
FSELSW
100
GND
Description
Printer initial command. This signal is active low,
and is issued bythe command to address 372H.
Printer strobe command. This signal is active
high, and is issued by the command to address
372H.
This signal is to control the direction of the
printer data bus.
When this signal is low, it is in the parallel IN
mode, and when it is high, it is in the printer
output mode.
This signal is to read the FDD interface signal as
below, when it is in the external FDD mode.
INDEX/TRAWCK O/WRITE PROTECTI
READ DATAl DISK CHANGEI READY
This signal is active low.
Address line. This signal is used to generate
printerl FDD control command.
Initial reset signal. This signal is active low.
Internal counters and F/Fs are reset by this signal.
This signal is to change the drive number of the
internal FDD. When this signal is low, the drive
number is changed to B, and when high, it is
changed to A (Normal).
Ground.
D-9
APPENDIX E
EMS GA (Gate Array)
E.l GENERAL
This chip allows application programs to access a vast
memory space by the bank switching operation, through a
certain memory address which is used as a window .
This Gate Array is used for address conversion, and it
stores page control registers, map registers, CPU/ DMA
address decoder and so on.
The EMS Gate Array is a flat package typed chip, and is
composed of 80 lead pins.
56
......................... -
41
40
57
80
17
......................... -
16
1
E-l
rv
I
f:Ij
"Ij
S
~
1'1
lQ
~
POIHl
IALE
RHR
R4-4(N
C!'HO
M51l
E.TN
0
.....
AH- 14
OMCK
S016-00
lOW, lOR
()
~
0
f-'
tJj
;:x:oo
G)
:s::
CIl
tI:I
f-'
tI:I
I
tI:I
~
C
H
G)
SOO -1
--
r
1
"---
24H
K
~
L..
,
MA
ME
J
MA
ME
"-d"'r
MA
REG
ME
J
28H
II
MA
ME
j5J
512
K
lET 1
!
MEM DEC
OIH
AH
K
512
~
•
SET 0
rt
~"00EC ~
-{>~:".
-b
.,
I-
~
f-----f)
r:
In
I-
--
RASOEC
Lb:f)
r
r--
ISHE
LA
LA
MfMW,R
IAOQ
~
,.
LA
~l
r-
JI
liJ!
ff
~
-t>=PfU_~
rrD
lOCK
DROM
CASL
(ASH
RAIA -0
ME 16
EA20
EA2'
ERAI
MA20-1.
I
1-4
o
~
N
tI:I
E.3 SIGNAL DESCRIPTION AND PIN ASSIGNMENT
TABLE E-1
Pin
I/O
Signal Name
1
2
3
I
I
RSET
GND
EXTND
4
I
M512K
5
6
7
8
9
10
11
12
I
I
I
I
I
I
I
13
0
0
SBHE
BALE
REFRSH
DMACK
MEMR
XIOR
XIOW
GND
EA20
EA21
SA16
SA15
SA14
SA13
SA12
SA 11
SA10
SA09
GND
SA08
SA07
SA06
SAOs
SA04
SA03
SA02
SA01
SAOO
Vcc
SDO
SD1
SD2
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
33
34
35
36
I/O
liD
liD
Pin Description
Descri pti 0 n
Reset signal. This signal is active high.
Ground
Extended memory access disable select.
Conventional memory 512 Kbytes/640 kbytes
select
Bus hiqh enable siqnal.
Address latch enable signal.
Refresh signal.
DMA acknowledge signal.
Memory read command
I/O read command
liD write command
Ground
Unlatched MA20
Unlatched MA21
Address bus 16
Address bus 15
Address bus 14
Address bus 13
Address bus 12
Address bus 11
Address bus 10
Address bus 09
Ground
Address bus 08
Address bus 07
Address bus 06
Address bus 05
Address bus 04
Address bus 03
Address bus 02
Address bus 01
Address bus 00
+5v
Data bus 0
Data bus 1
Data bus 2
E-3
Pin
I/O
Signal Name
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
I/O
I/O
I/O
I/O
I/O
SD3
SD4
SD5
SD6
SD7
GND
MA20
MA19
MA18
MA17
MA16
MA15
MA14
PDINH
PDINL
GND
CASLSL
CASHSL
RAS4SL
RAS3SL
RAS2SL
RAS1SL
RASOSL
RAS4EN
RAS3EN
RAS2EN
GND
MEMWE
A23
A22
A21
A20
A19
A18
A17
0
0
0
0
0
0
0
I
I
0
0
0
0
0
0
0
I
I
I
I
I
I
I
I
I
I
I
Description
Data bus 3
Data bus 4
Data bus 5
Data bus 6
Data bus 7
Ground
RAM address 20
RAM address 19
RAM address 18
RAM address 17
RAM address 16
RAM address 15
RAM address 14
RAM parity set H
RAM parity set L
Ground
RAM CAS enable L
RAM CAS enable H
RAM RAS enable signal4
RAM RAS enable signal 3
RAM RAS enable signal 2
RAM RAS enable signal 1
RAM RAS enable signal 0
RAS4 enable signal
RAS3 enable signal
RAS2 enable signal
Ground
Memory write command
Unlatched address bus 23
Unlatched address bus 22
Unlatched address bus 21
Unlatched address bus 20
Unlatched address bus 19
Unlatched address bus 18
Unlatched address bus 17
E-4
Pin
1/0
Signal Name
72
73
74
75
76
77
78
79
80
I
A16
Vcc
A15
A14
ERAS
MEM16
DRMRD
10CHK
CPHLDA
I
I
0
0
0
0
I
Description
Unlatched address bus 16
+ Sv
Unlatched address bus 15
Unlatched address bus 14
Unlatched OR of MA22, 23
Memory word transfer signal
RAM data enable
RAM parity error
CPU hold siQnal
E-5
APPENDIX F
AGS.GA (Gate Array)
F.I GENERAL
AGS stands for Advanced Graphics Subsystem, and is used
together with the PEGA2 chip to realize the function of 640
x 400 mode graphics in the CRT or Plasma display.
AGS Gate Array is a flat package typed chip with 100 lead
pins in total.
51
80
50
31
100
30
1
F-l
F.2 BLOCK DIAGRAM
PD2,3,4
--::,
SYSTEM BUS
(PDP (n(K P'HW
MXA
(iOCHi<)
DRV
;:-
~PE**
r--_V"'----.-_V~_, MXB
Sl TZ
SEl
I
SEl
J;
I SDO
TRPZ~~~~-L~___~Le_e_R_T-LS_W_/T~I~LL~
<
SDO-7
>
1----"[:]
'---
r--
--::, DRV
~----~~
TEST
FT2Z
FT1Z
AUT
PDP
DISZ
~-2
I--
AGS - GA
SDOO-19
I-I--
REF, DMA,IORZ,
MERZ,IOWZ,
MEWZ,RESZ
PO* {\
UNlZ
MIO MESZ
BlK
IOSZ
RDP
elK
ESAZ
IRO
~
I--
ROMZ
RWEZ
l=l
ROM
32 Kbytes
">.r
L...-_ _ _ _
L-wE
es
PEGA- 2
fI
" 1\
(M1BO
(M2BO-7)
DRV
t--
L..--~EN
1\
(MOBO
-7)
~
-7)
DRAM
~ ~
'-------' (M3B3 -7) L--_ _ _ _ _ _ _---J
-
FIGURE F-I
AGS.GA Block Diagram
F-2
SRAM
F.3 SIGNAL DESCRIPTION AND PIN ASSIGNMENT
TABLE F-l
Pin
I/O
Signal Name
1
0
MUXB
2
0
MUXA
3
4
5
6
7
8
9
10
I
I
I
I
I
Vcc
RAMCS
RAMWE
DMACK
SMEMW
SMEMR
lOW
lOR
11
I
AUTOSW
12
I
FONT
13
I
DSPDIS
14
I
CGFONT
0
0
15
GND
16
I
REFRSH
17
I
SWTCH
18
I
RESET
19
I
IRQ9
20
I
BLANK
21
22
23
24
25
26
27
I
I
I
I
I
I
I
MIOSl
POVS
POHS
POSB
POSG
POBl
POGR
Pin Description
Description
Multiplex Select A
External Clock/ Dip switch select signal
Multiplex Select B
External Clock/ Dip switch select signal
+5V
SRAM chiQselect signal
SRAM write enable signal
System bus address enable signal
Memory write command
Memory read command
I/O write command
I/O read commad
This signal is ued to power on the Auto-switch
(DIP-SW1) concernig bit 70f the PEGA2 status
read port.
This signal is used to select double or single FONT
(DIP-SW4) concernig bit 5 of the PEGA2 status
read port.
This signal is used to disable the system
This signal is used to select Sacandinavian or
Normal FONT (DIP-SW6) concernig bit 4 of the
PEGA2 status read port.
Ground
System bus memory refresh signal. When this is
low, memory access is enabled.
Status signal from the external4-bit Display type
select switch.
System bus reset signal
CRT interrupt signal. This signal is output from
the PEGA2, and can be read at the bit 7 of 3C2
port.
This is the signal to indicate that blanking is
being executed.
This is the si9nal to select Memory or I/O.
CRT display signal from the PEGA2.
CRT display signal from the PEGA2.
CRT disglay signal from the PEGA2.
CRT display signal from the PEGA2.
CRT display signal from the PEGA2.
CRT displav siqnal from the PEGA2.
F-3
Pin
1/0
Signal Name
28
29
30
31
32
33
34
35
36
I
I
0
0
0
0
I
I
Vcc
PORE
POSR
READ
10SEl
MEMSl
ROMSl
ClKMUX
PDPSl
37
I
UNl
38
39
40
41
0
I
ClK
ClKPDP
GND
GND
42
0
SRON
43
0
SlT
44
0
M3DA2
45
46
0
0
M3DA1
M3DAO
47
I
XA8
48
I
ESA
49
50
0
0
TRP
PEPD4
51
0
PEGR
Description
+ 5V
CRT display signal from the PEGA2.
CRT display signal from the PEGA2.
PEGA read I write select signal
I/O select signal
PEGA memory select signal
ROM chip select signal
Basic clock for CRT display
Plasmal CRT select signal
This signal is to indicate that the content of the
port 3D8 has already been read twice.
This is cleared by the next read or write signal.
Basic clock for display. This is output to the PEGA.
Basic clock for Plasma display
Ground
Ground
This signal is to enable the SR signal.
When this is high, CRT output pin No.2 is
grounded.
NMI generate timing signal
Address data bit 2 of the DRAM plane 3. In this
GA, system address bus is output to the PEGA.
Address data bit 1 of the DRAM plane 3.
Address data bit 0 of the DRAM plane 3.
I/O port address bit 8 for display
When XA8 = SA8, the port 3XX is accessed.
" XA8 = SA8, the port 2XX is accessed.
PEGA system address input enable signal.
When this is low, system address is output to M3
bus.
Trap (NMI) generate signal
Plasma display signal. This signal is active low.
Pins 51,54,55,57,58,59,60,61 are used for
selection of CRT or Plasma display as follows,
depending on their combinations.
PDP
CRT
VS
9Pin
PEVS (Pin 58)
HS
8pin
PEHS (Pin 59)
PD1
PESB (Pin 54)
7pin
PS4
6pin
PESG (pin 55)
PS3
Spin
PEBl (pin 61)
PS2
4pin
PEGR (pin 51)
PS1
PERE (pin 57)
3pin
2pin
PESR (pin 60)
SCK
F-4
Pin
I/O
Signal Name
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
0
PEPD2
Vcc
PESB
PESG
PEPD3
PERE
PEVS
PEHS
PESR
PEBL
SA8
SA7
SA6
GND
SA5
SA4
SA3
SA2
SA1
SAO
SDO
SD1
SD2
SD3
SD4
SD5
Vee
SD6
SD7
SA19
SA18
SA17
SA16
SA15
SA14
SA 13
SA12
SA 11
GND
0
0
0
0
0
0
0
0
I
I
I
I
I
I
I
I
I
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I
I
I
I
I
I
I
I
I
Description
Plasma display signal. This siBnal is active low.
+ 5V
Refer to the descriQtion of the Qin 51.
Refer to the description of the pin 51.
Plasma display signal. This signal is active low.
Refer to the description of the pin 51.
Refer to the description of the ~in 51.
Refer to the descriQtion of the ~in 51.
Refer to the description of theQin 51.
Refer to the descrif>tion of the pin 51.
system address bus bit 8.
system address bus bit 7.
system address bus bit 6.
Ground
system address bus bit 5.
system address bus bit 4.
system address bus bit 3.
system address bus bit 2.
system address bus bit 1.
system address bus bit o.
System data bus bit o.
System data bus bit 1.
System data bus bit 2.
System data bus bit 3.
System data bus bit 4.
System data bus bit 5.
+ 5V
System data bus bit 6.
System data bus bit 7.
system address bus bit 19.
system add ress bus bit 18.
system address bus bit 17.
system address bus bit 16.
system address bus bit 15.
system address bus bit 14.
system address bus bit 13.
system address bus bit 12.
system address bus bit 11.
Ground
F-5
Pin
I/O
Signal Name
91
92
93
94
95
96
97
98
99
100
I
I
liD
liD
liD
liD
liD
liD
liD
liD
SA10
SA9
LD7
LD6
LD5
LD4
LD3
LD2
LD1
LDO
Description
system address bus bit 10.
system address bus bit 9.
Local data bus 7 among PEGA, ROM, and SRAM.
Local data bus 6 amonq PEGA, ROM, and SRAM.
Local data bus 5 amonq PEGA, ROM, and SRAM.
Local data bus 4 among PEGA, ROM, and SRAM.
Local data bus 3 among PEGA, ROM, and SRAM.
Local data bus 2 among PEGA, ROM, and SRAM.
Local data bus 1 among PEGA, ROM, and SRAM.
Local data bus 0 amona PEGA ROM. and SRAM.
F-6
APPENDIX G
PEGA2
G.l GENERAL
The PEGA2 is a single solution for design of a video
controller.
This chip is composed of 84 pins with 40 multiplexed
bidirectional signals for handling RAM address and data, CPU
address and data, as well as various I/O bits.
Four busses of 8 bits each connect to the four banks of
DRAM, and the fifth 8 bits is used for CPU address and data.
54
74
75
53
84
1
32
12
G-l
G. 2 BLOCK DIAGRAM
RAM PLAN EO
POVS
RAM PLAN El
POHS
VIDEO OUT
RAM PLAN E2
~
PEGA 2
~
RAM PLAN E3
CPU
ADDRES S
,..
VDISP
(VIDEO DISPLAY
ENABLE)
AGS-GA
CPUINTFC
SEQUENCER
CRT CONTROL
CPU DATA
~
VIDEO CONTROL
IRQ
(INTERRUPT
REQUEST)
CPU
ADDRESS MUX
CONTROL
RAM CONTROL
10RDY
RD/W R
CLOC K
RES ET
-.-
lOS EL
MEM SL
FIGURE G-I
PEGA2 Block Diagram
G-2
The PEGA2 uses 64Kx4 DRAMs with one RAM bank consisting of 2
chips. Within a bank, one chip connects 4 data lines to the
low 4 bus signals and the other chip connects 5 data lines
to the high 4 bus signals.
The RAS, CAS, and OE signals are common to all 4 banks, but
each bank uses a separate WE signal.
The signals required for controlling the external bus
multiplexers are generated with a minimum of additional
logic. External logic as also required for PC bus interface
functions, including address decoding, bus direction control
and interrupt handling.
The eight video outputs of the PEGA2 are designed to drive
a 9-pin monitor cable directly. Switching logic inside the
PEGA 2 correctly configures the video data signals (RrGgBb,
IRGB or Video/ Intensity) for the particular monitor being
driven.
A TTG-compatib1e clock, up to 26 MHz drives the PEGA2.
A reset pin initializes the chip and a total of 12 pins are
used for power and ground connections.
G-3
F.3 SIGNAL DESCRIPTION AND PIN ASSIGNMENT
TABLE G-l
Pin
I/O
Signal Name
GND
1
2
I/O
M3DA-4
3
I/O
M3DA-5
4
I/O
M3DA-6
5
I/O
M3DA-7
6
I/O
M2DA-0
7
I/O
M2DA-l
8
9
I/O
I/O
M2DA-2
M2DA-3
10
11
0
FCVO
FCV1
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
I/O
I/O
I/O
I/O
M2DA-4
M2DA-5
M2DA-6
GND
M2DA-7
SDO
SD1
SD2
SD3
Vcc
GND
SD4
SDS
SD6
SD7
I/O
IRQ9
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
Pin Description
Description
Ground
Memory data and address bit 4, plane 3.
CPU add ress bit 10 at ESAN.
Memory data and address bit 5, plane 3.
CPU address bit 11 at ESAN.
Memory data and address bit 6, plane 3.
CPU add ress bit 12 at ESAN.
Memory data and address bit 7, plane 3.
CPU address bit 13 at ESAN.
Memory data and address bit 0, plane 2.
CPU address bit 14 at ESAN.
Memory data and address bit 1, plane 2.
LIGHT PEN Switch at ESAN.
Memory data and address bit 2, plane 2.
Memory data and address bit 3, plane 2.
Active low, bits DO and Dlof Figure Control
Register at I/O port 3XA; supplied to Feature
Connector.
Memory data and address bit 4, plane 2.
Memory data and address bit 5, plane 2.
Memory data and address bit 6, plane 2.
Ground
Memory data and address bit 7, plane 2.
CPU data bit 1
CPU data bit 2
CPU data bit 3
CPU data bit 4
+5V
Ground
CPU data bit S
CPU data bit 6
CPU data bit 7
CPU data bit 8
Active high, indicates that an interrupt has been
generated. Can be set to high impedance under
program control (3XS-11 H, bitS).
Gets read as STATUS 0 bit 7.
G-4
Pin
I/O
Signal Name
0
10RDY
29
30
0
GND
COE
31
0
ESA
32
0
CCAS
33
0
MIOSL
34
0
GRAPH
35
36
37
38
39
0
RAS
CWO
CW1
CW2
CW3
40
I
RESET
41
I
CLOCK
42
I
READ
28
43
44
GND
Vcc
45
I
10SEL
46
I
MEMSL
47
48
0
Vcc
POHS
49
0
POVS
50
51
0
0
POSR
POSG
52
0
BLANK
53
0
ATRSLN
Description
Active high, indicates that memory access has
been completed. When it is low,it is used to cause
wait states to be inserted into the memory access
cycles. It is high impedance when memory is not
selected.
Ground
Active low, output enable for video planes
Active low enable for system address bits
(6-13, 14) and LPSW multiplexed with memory
datal address bits (see above).
Active low, column address strobe
Active high, Memory or I/O selected. Controls
external data bus driver.
Active high, indicates that a graphics mode is
active; low indicates alphanumeric mode.
Active low, row address strobe.
Active low, write signal for video plane 0
Active low, write signal for video plane 1
Active low, write signal for video plane 2
Active low, write signal for video plane 3
Active low, master reset supplied by external
power on circuitry.
26.0 MHz max.
Active high while reading PEGA I/O port or video
memory.
Gound
+5V
Active low. I/O select indicates accessing any
PEGA I/O port.
Active low. memory select indicates accessing
video memory.
+ 5V
Horizontal Sync Signal
Vertical Sync Signal (active low for monochrome
monitors and IBM Enhanced Color Display).
Secondary Red Output
Secondary green output or intensity
Active high, Horizontal or Vertical blanking for
use with feature connector.
Active low, Attribute/ shift load for use with
feature connector.
G-S
Pin
I/O
Signal Name
54
0
VDISP
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
0
POSB
PORE
POGR
POBL
M1DAO
M1DAl
M1DA2
M1DA3
M1DA4
GND
Vcc
M1DA5
M1DA6
M1DA7
MODAO
MODAl
GND
MODA2
MODA3
MODA4
Vcc
0
0
0
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
76
0
UNLOCK
77
78
79
I/O
I/O
I/O
MODA5
MODA6
MODA7
80
I/O
M3DAO
81
I/O
M3DAl
82
I/O
M3DA2
83
I/O
M3DA3
84
Vcc
Description
Active high, Video display enable, indicates
active video (un blanked, not border).
Secondary blue output or monochrome video.
Primary red output
Primary green output
Primary blue output
Memory data and address bit 0, plane 1.
Memory data and address bit " plane 1.
Memory data and address bit 2, plane 1.
Memory data and address bit 3, plane 1.
Memory data and add ress bit 4, plane 1.
Ground
+5V
Memorydata and address bit 5, plane 1.
Memory data and address bit 6, plane 1.
Memory data and address bit 7, planel.
Memory data and add ress bit 0, plane O.
Memory data and address bit 1, plane O.
Ground
Memory data and address bit 2, plane o.
Memory data and add ress bit 3, plane O.
Memory data and address bit 4, plane O.
Active low, goes active after two successive reads
of the old mode register(3D8 or 3B8). Goes
inactive at the end of of the next /0 read or write
cycle.
Memory data and address bit 5, plane O.
Memory data and address bit 6, plane O.
Memory data and address bit 7, plane o.
Memory data and address bit 0, plane 3.
CPU address bit 6 at ESAN
Memory data and address bit 1, plane 3.
CPU address bit 7 at ESAN
Memory data and address bit 2, plane 3.
CPU address bit 8 at ESAN
Memory data and address bit 3, plane 3.
CPU address bit 9 at ESAN
+ 5V
G-6
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