Transcend 64MB SDRAM PC100 Unbuffer Non-ECC Memory Datasheet

168PIN PC100 Unbuffered DIMM
64MB With 8Mx16 CL2
TS8MLS64V8C2
Description
Placement
The TS8MLS64V8C2 is a 8M x 64 bits Synchronous
Dynamic
RAM
high-density
for
PC-100.
The
TS8MLS64V8C2 consists of 4pcs CMOS 8Mx16 bits
Synchronous DRAMs in TSOP-II 400mil packages and
a 2048 bits serial EEPROM on a 168-pin printed circuit
board. The TS8MLS64V8C2 is a Dual In-Line Memory
Module and is intended for mounting into 168-pin edge
connector sockets.
Synchronous design allows precise cycle control with
A
the use of system clock. I/O transactions are possible
on every clock cycle. Range of operation frequencies,
programmable latencies allow the same device to be
useful for a variety of high bandwidth, high performance
memory system applications.
B
D
Features
E
• Performance Range: PC-100.
C
• Conformed to JEDEC Standard spec.
• Burst Mode Operation.
• Auto and Self Refresh.
E
• CKE Power Down Mode.
H
• DQM Byte Masking (Read/Write)
G
F
• Serial Presence Detect (SPD) with serial EEPROM
• LVTTL compatible inputs and outputs.
• Single 3.3V ± 0.3V power supply.
PCB: 09-7130
• MRS cycle with address key programs.
Latency (Access from column address)
Burst Length (1,2,4,8 & Full Page)
Data Sequence (Sequential & Interleave)
• All inputs are sampled at the positive going edge of
the system clock.
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1
I
168PIN PC100 Unbuffered DIMM
64MB With 8Mx16 CL2
TS8MLS64V8C2
Dimensions
Pin Identification
Side
Millimeters
Inches
A
133.35±0.40
5.250±0.016
B
65.67000
2.585000
C
23.49000
0.925000
D
8.89000
0.350000
E
3.00000
0.118000
F
31.75±0.2000
1.250±0.00800
G
19.80000
0.788000
H
15.80
0.622
I
1.27±0.10
0.050±0.004
Symbol
Function
A0~A11,BA0,BA1 Address input
DQ0~DQ63
Data Input/Output.
CLK0, CLK2
Clock Input..
CKE0
Clock Enable Input.
/CS0, /CS2
Chip Select Input.
/RAS
Row Address Strobe
/CAS
Column Address Strobe
/WE
Write Enable
DQM0~DQM7
Data (DQ) Mask
SA0~SA2
Address in EEPROM
SCL
Serial PD Clock
SDA
Serial PD Add/Data input/output
Vcc
+3.3 Voltage Power Supply
Vss
Ground
NC
No Connection
(Refer Placement)
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2
168PIN PC100 Unbuffered DIMM
64MB With 8Mx16 CL2
TS8MLS64V8C2
Pinouts:
Pin
Pin
Pin
No
Name
No
01
Vss
43
02
DQ0
44
03
DQ1
45
04
DQ2
46
05
DQ3
47
06
Vcc
48
07
DQ4
49
08
DQ5
50
09
DQ6
51
10
DQ7
52
11
DQ8
53
12
Vss
54
13
DQ9
55
14
DQ10
56
15
DQ11
57
16
DQ12
58
17
DQ13
59
18
Vcc
60
19
DQ14
61
20
DQ15
62
21
*C0
63
22
*C1
64
23
Vss
65
24
NC
66
25
NC
67
26
Vcc
68
27
/WE
69
28
DQM0
70
29
DQM1
71
30
/CS0
72
31
NC
73
32
Vss
74
33
A0
75
34
A2
76
35
A4
77
36
A6
78
37
A8
79
38
A10/AP
80
39
BA1
81
40
Vcc
82
41
Vcc
83
42
CLK0
84
*Please refer Block Diagram
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Pin
Name
Vss
NC
/CS2
DQM2
DQM3
NC
Vcc
NC
NC
*C2
*C3
Vss
DQ16
DQ17
DQ18
DQ19
Vcc
DQ20
NC
*Vref
*CKE1
Vss
DQ21
DQ22
DQ23
Vss
DQ24
DQ25
DQ26
DQ27
Vcc
DQ28
DQ29
DQ30
DQ31
Vss
*CLK2
NC
NC
SDA
SCL
Vcc
Pin
No
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
3
Pin
Name
Vss
DQ32
DQ33
DQ34
DQ35
Vcc
DQ36
DQ37
DQ38
DQ39
DQ40
Vss
DQ41
DQ42
DQ43
DQ44
DQ45
Vcc
DQ46
DQ47
*C4
*C5
Vss
NC
NC
Vcc
/CAS
DQM4
DQM5
*/CS1
/RAS
Vss
A1
A3
A5
A7
A9
BA0
A11
Vcc
*CLK1
*A12
Pin
No
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
Pin
Name
Vss
CKE0
*/CS3
DQM6
DQM7
*A13
Vcc
NC
NC
*C6
*C7
Vss
DQ48
DQ49
DQ50
DQ51
Vcc
DQ52
NC
*Vref
*REGE
Vss
DQ53
DQ54
DQ55
Vss
DQ56
DQ57
DQ58
DQ59
Vcc
DQ60
DQ61
DQ62
DQ63
Vss
*CLK3
NC
SA0
SA1
SA2
Vcc
168PIN PC100 Unbuffered DIMM
64MB With 8Mx16 CL2
TS8MLS64V8C2
Block Diagram
DQ0~DQ63
A0~A11,
BA0,BA1
DQ0~DQ15
A0~A11,
BA0,BA1
DQ0~DQ15
A0~A11,
BA0,BA1
DQ0~DQ15
A0~A11,
BA0,BA1
DQ0~DQ15
/RAS
/RAS
/RAS
/RAS
/RAS
/CS
/CS
CLK0
CLK
CKE0
CKE
CLK
CKE
DQM4
DQM0
DQM5
DQM1
CLK
CKE
DQM6
DQM2
/CAS
CLK
CKE
8Mx16
SDRAM
UDQM
/CS
UDQM
/CS
LDQM
/CS0
UDQM
/WE
/CAS
LDQM
8Mx16
/CAS
SDRAM
/WE
UDQM
8Mx16
/CAS
SDRAM
/WE
LDQM
/WE
8Mx16
/CAS
SDRAM
/WE
LDQM
A0~A11,BA0,BA1
DQM7
DQM3
/CS2
CLK2
Serial EEPROM
SCL
SCL
A0
SDA
SDA
A1 A2
SA0 SA1 SA2
This technical information is based on industry standard data and tests believed to be reliable. However , Transcend makes no warranties, either expressed
or implied, as to its accuracy and assumes no liability in connection with the use of this product. Transcend reserves the right to make changes in
specifications at any time without prior notice.
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4
168PIN PC100 Unbuffered DIMM
64MB With 8Mx16 CL2
TS8MLS64V8C2
ABSOLUTE MAXIMUM RATINGS
Parameter
Symbol
Value
Unit
Voltage on any pin relative to Vss
VIN, VOUT
-1.0~4.6
V
Voltage on VDD supply to Vss
VDD, VDDQ
-1.0~4.6
V
TSTG
-55~+150
°C
Power dissipation
PD
4
W
Short circuit current
IOS
50
mA
MTBF
50
year
THB
85°C/85%, Static Stress
°C-%
TC
0°C ~ 125°C Cycling
°C
Storage temperature
Mean time between failure
Temperature Humidity Burning
Temperature Cycling Test
Note:
Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are exceeded.
Functional operation should be restricted to recommended operating condition.
Exposure to higher than recommended voltage for extended periods of time could affect device
reliability.
DC OPERATING CONDITIONS AND CHARACTERISTICS
Recommended operating conditions (Voltage referenced to Vss = 0V, TA = 0 to 70°C)
Parameter
Symbol
Min
Typ
Max
Unit
VDD, VDDQ
3.0
3.3
3.6
V
Input high voltage
VIH
2.0
3.0
VDD+0.3
V
1
Input low voltage
VIL
-0.3
0
0.8
V
2
Output high voltage
VOH
2.4
-
-
V
IOH=-2mA
Output low voltage
VOL
-
-
0.4
V
IOL=2mA
IIL
-10
-
10
uA
3
Supply voltage
Input leakage current
Note
Note: 1. VIH (max) = 5.6V AC. The overshoot voltage duration is ≤ 3ns.
2. VIL (min) = -1.5V AC. The undershoot voltage duration is ≤ 3ns.
3. Any input 0V ≤ VIN ≤ VDDQ,
Input leakage currents include Hi-Z output leakage for all bi-directional buffers with Tri-State outputs.
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5
168PIN PC100 Unbuffered DIMM
64MB With 8Mx16 CL2
TS8MLS64V8C2
CAPACITANCE (TA = 23°C, f = 1MHz)
Parameter
Input capacitance (A0~A11, BA0~ BA1)
Input capacitance (/RAS, /CAS, /WE)
Input capacitance (CKE0)
Input capacitance (CLK0, CLK2)
Input capacitance (/CS0, /CS2)
Input capacitance (DQM0~DQM7)
Data input/output capacitance (DQ0~DQ63)
Symbol
Min
Max
Unit
CIN1
CIN2
CIN3
CIN4
CIN5
CIN6
COUT
25
25
25
15
15
8
8
30
30
30
20
20
10
10
pF
pF
pF
pF
pF
pF
pF
AC OPERATING TEST CONDITIONS (VDD = 3.3V±0.3V, TA = 0 to 70°C)
Parameter
AC Input levels (VIH/VIL)
Input timing measurement reference level
Input rise and fall time
Output timing measurement reference level
Output load condition
Value
Unit
2.4/0.4
V
1.4
V
tr/tf=1/1
ns
1.4
V
See Fig. 2
Vtt=1.4V
3.3V
50 Ohm
1200 Ohm
Output
VOH (DC)=2.4V, IOH=-2mA
VOL (DC)=0.4V, I OL=2mA
Output
50pF
50pF
870 Ohm
(Fig. 2) AC Output Load Circuit
(Fig. 1) DC Output Load Circuit
Transcend information Inc
Z0=50 Ohm
6
168PIN PC100 Unbuffered DIMM
64MB With 8Mx16 CL2
TS8MLS64V8C2
DC CHARACTERISTICS
(Recommended operating condition unless otherwise noted, TA = 0 to 70°C)
Parameter
Operating Current
(One Bank Active)
Symbol
Test Condition
Value
Unit
Note
ICC1
Burst Length =1
tRC≥tRC(min)
IOL=0mA
560
mA
1
Precharge Standby Current ICC2P
in power-down mode
ICC2PS
ICC2N
Precharge Standby Current
in non power-down mode
Active Standby Current
in power-down mode
Active Standby Current
in non power-down mode
(One Bank Active)
ICC2NS
CKE≤VIL(max), tCC=10ns
4
CKE & CLK≤VIL(max), tCC=∞
4
CKE≥VIH(min), /CS≥VIH(min), tCC=10ns
Input signals are changed one time during 20ns
CKE≥VIH(min), CLK≤VIL(max), tCC=∞
Input signals are stable
mA
28
CKE≤VIL(max), tCC=10ns
20
ICC3PS
CKE & CLK≤VIL(max), tCC=∞
20
ICC3N
CKE≥VIH(min), /CS≥VIH(min), tCC=15ns
ICC3NS CKE≥VIH(min), CLK≤VIL(max), tCC=∞
Input signals are stable
Operating Current
(Bust Mode)
80
ICC3P
Input signals are changed one time during 30ns
ICC4
IOL= 0 mA
Page Burst
4Banks activated
mA
mA
120
mA
80
720
mA
1
840
mA
2
6
mA
tccD = 2CLKs
Refresh Current
ICC5
tRC ≥ tRC(min)
Self Refresh Current
ICC6
CKE ≤ 0.2V
Note:
1. Measured with outputs open.
2. Refresh period is 64ms.
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7
168PIN PC100 Unbuffered DIMM
64MB With 8Mx16 CL2
TS8MLS64V8C2
OPERATING AC PARAMETER (AC operating conditions unless otherwise noted)
Parameter
Symbol
Value
Unit
Note
tRRD(min)
tRCD(min)
tRP(min)
tRAS(min)
tRAS(max)
20
20
20
50
100
ns
ns
ns
ns
us
1
1
1
1
Row cycle time
tRC(min)
70
ns
1
Last data in to new col. address delay
Last data in to row precharge
Last data in to burst stop
Col. address to col. address delay
tCDL(min)
tRDL(min)
tBDL(min)
tCCD(min)
1
2
1
1
CLK
CLK
CLK
CLK
2
2
2
3
Number of valid output data
CAS latency=2
1
ea
4
Row active to row active delay
/RAS to /CAS delay
Row precharge time
Row active time
Note:
1. The minimum number of clock cycles is determined by dividing the minimum time required with
clock cycle time, and then rounding off to the next higher integer.
2. Minimum delay is required to complete write.
3. All parts allow every cycle column address change.
4. In case of row precharge interrupt, auto precharge and read burst stop.
5. A new command may be given tRFC after self refresh exit.
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8
168PIN PC100 Unbuffered DIMM
64MB With 8Mx16 CL2
TS8MLS64V8C2
AC CHARACTERISTICS (AC operating conditions unless otherwise noted)
Refer to the individual component, not the whole module.
Parameter
Symbol
CLK cycle time
tCC
Value
Unit
Note
Min
Max
10
1000
ns
1
6
ns
1, 2
CLK to valid output delay
tSAC
Output data hold time
tOH
3
ns
2
CLK high pulse width
tCH
3
ns
3
CLK low pulse width
tCL
3
ns
3
Input setup time
tSS
2
ns
3
Input hold time
tSH
1
ns
3
CLK to output in Low-Z
tSLZ
1
ns
2
CLK to output in Hi-Z
tSHZ
Note:
6
ns
1. Parameters depend on programmed CAS latency.
2. If clock rising time is longer than 1ns, (tr/2-0.5)ns should be added to the parameter.
3. Assumed input rise and fall time (tr & tf)= 1ns.
If tr & tf is longer than 1ns, transient time compensation should be considered,
i.e., [(tr + tf)/2-1]ns should be added to the parameter.
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9
168PIN PC100 Unbuffered DIMM
64MB With 8Mx16 CL2
TS8MLS64V8C2
SIMPLIFIED TRUTH TABLE
COMMAND
Register
Mode Register Set
Refresh
Auto Refresh
Entry
Self
Refresh
Exit
Bank Active & Row Addr.
Read &
Column Address
Auto Precharge Disable
Write &
Column Address
Auto Precharge Disable
Auto Precharge Enable
CKEn-1 CKEn
/CS
/RAS
/CAS
/WE
DQM
X
L
L
L
L
X
OP CODE
H
H
L
L
L
L
H
X
X
L
H
L
H
H
X
H
X
H
X
X
X
H
X
L
L
H
H
X
V
H
X
L
H
L
H
X
V
X
L
H
L
L
X
H
X
L
H
H
L
X
H
X
L
L
H
L
X
Clock Suspend or Entry
Active
Power
Down
Exit
H
L
H
X
X
X
L
V
V
V
L
H
X
X
X
X
H
X
X
X
Entry
H
L
L
H
H
H
H
X
X
X
L
V
V
V
H
X
X
X
L
H
H
H
Auto Precharge Enable
Bank Selection
Both Banks
Precharge
Precharge Power
Down Mode
V
1,2
3
3
3
3
Row Address
L
Column
Address
(A0~A8)
H
L
Column
Address
(A0~A8)
H
X
V
X
L
H
4
4, 5
4
4, 5
6
X
X
X
X
X
X
Exit
DQM
L
H
X
H
No Operation Command
Note:
A10/AP A11, A0~A9 Note
H
H
Burst Stop
BA0,1
H
X
X
V
X
X
X
(V=Valid, X=Don’t Care, H=Logic High, L=Logic Low)
1. OP Code : Operand Code
A0~A11, BA0~BA1 : Program keys. (@MRS)
2. MRS can be issued only at both banks precharge state.
A new command can be issued after 2 CLK cycles of MRS.
3. Auto refresh functions are as same as CBR refresh of DRAM.
The automatically precharge without row precharge command is meant by “Auto”.
Auto/self refresh can be issued only at both banks precharge state.
4. BA0~BA1: Bank select address.
If both BA0 and BA1 are “Low” at read, write, row active and precharge, bank A is selected.
If both BA0 is “Low” and BA1 is “High” at read, write, row active and precharge, bank B is selected.
If both BA0 is “High” and BA1 is “Low” at read, write, row active and precharge, bank C is selected.
If both BA0 and BA1 are “High” at read, write, row active and precharge, bank D is selected.
If A10/AP is “High” at row precharge, BA0 and BA1 is ignored and both banks are selected.
5. During burst read or write with auto precharge, new read/write command can not be issued.
Another bank read/write command can be issued after the end of burst.
New row active of the associated bank can be issued at tRP after the end of burst.
6. Burst stop command is valid at every burst length.
7. DQM sampled at positive going edged of a CLK masks the data-in at the very CLK (Write DQM latency is 0),
but makes Hi-Z state the data-out of 2 CLK cycles after. (Read DQM latency is 2)
Transcend information Inc
10
7
168PIN PC100 Unbuffered DIMM
64MB With 8Mx16 CL2
TS8MLS64V8C2
Serial Presence Detect Specification
Serial Presence Detect
Byte No.
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36-61
62
63
64-71
Function Described
# of Bytes Written into Serial Memory
Total # of Bytes of S.P.D Memory
Fundamental Memory Type
# of Row Addresses on this Assembly
# of Column Addresses on this Assembly
# of Module Banks on this Assembly
Data Width of this Assembly
Data Width Continuation
Voltage Interface Standard of this Assembly
SDRAM Cycle Time (highest CAS latency)
SDRAM Access from Clock (highest CL)
DIMM configuration type (non-parity, ECC)
Refresh Rate Type
Primary SDRAM Width
Error Checking SDRAM Width
Min Clock Delay Back to Back Random Address
Burst Lengths Supported
Number of banks on each SDRAM device
CAS # Latency
CS # Latency
Write Latency
SDRAM Module Attributes
SDRAM Device Attributes : General
nd
SDRAM Cycle Time (2 highest CL)
SDRAM Access from Clock (2nd highest CL)
SDRAM Cycle Time (3rd highest CL)
SDRAM Access from Clock (3rd highest CL)
Minimum Row Precharge Time
Minimum Row Active to Row Activate
Minimum RAS to CAS Delay
Minimum RAS Pulse Width
Density of Each Bank on Module
Command/Address Setup Time
Command/Address Hold Time
Data Signal Setup Time
Data Signal Hold Time
Superset Information
SPD Data Revision Code
Checksum for Bytes 0-62
Manufacturers JEDEC ID Code per JEP-108E
Transcend information Inc
11
Standard Specification
128bytes
256bytes
SDRAM
12
9
1 bank
64bits
0
LVTTL3.3V
10ns
6ns
None
15.625us/Self Refresh
x16
64bit
1 clock
1,2,4,8 & Full page
4 bank
3,2
0 clock
0 clock
Non Buffer
Prec All, Auto Prec,
R/W Burst
10ns
6ns
0
0
20
20
20
50
64MB
2ns
1ns
2ns
1ns
Version 1.2
34
Transcend
Vendor Part
80
08
04
0C
09
01
40
00
01
A0
60
00
80
10
00
01
8F
04
06
01
01
00
0E
A0
60
00
00
14
14
14
32
10
20
10
20
10
00
12
0D
7F, 4F
168PIN PC100 Unbuffered DIMM
64MB With 8Mx16 CL2
TS8MLS64V8C2
72
Manufacturing Location
T
73-90
Manufacturers Part Number
TS8MLS64V8C2
91-92
93-94
95-98
99-125
126
127
128~
Revision Code
Manufacturing Date
Assembly Serial Number
Manufacturer Specific Data
Intel Specification Frequency
Intel Specification CAS# Latency/Clock Signal Support
Unused Storage Locations
By Manufacturer
By Manufacturer
100MHz
CL=2 Clock=0,2
Open
Transcend information Inc
12
54
54 53 38 4D 4C 53
36 34 56 38 43 32
20 20 20 20 20 20
0
Variable
Variable
0
64
A6
FF