TDHBG2500P100 User Guide

User Guide
TDHBG2500P100: 2.5kW Half-bridge Evaluation Board
Introduction
The TDHBG2500P100 half-bridge evaluation board provides the elements of a simple buck or boost converter for basic study of
switching characteristics and efficiency achievable with Transphorm’s 650V GaN FETs. In either buck or boost mode the circuit
can be configured for synchronous rectification. Jumpers allow use of a single logic input or separate hi/lo inputs. The highvoltage input and output can operate at up to 400Vdc, with a power output of up to 2.5kW. The inductor provided is intended for
efficient operation at 100kHz, although other inductors and other frequencies may be easily used.
Figure 1. Half-bridge evaluation board
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TDHBG2500P100 User Guide
TDHGB2500P100 input/output specifications
High-voltage input/output: 400Vdc max
Auxiliary supply (J1): 10V min, 18V max
Logic inputs: nominal 0V-5V
Pulse-generation circuit: Vlo < 1.5V, Vhi > 3.0V
Direct connection to gate driver: Vlo < 0.8V, Vhi > 2.0V
SMA coaxial connectors
Switching frequency: configuration-dependent
Lower limit determined by peak inductor current
Upper limit determined by desired dead-time and power dissipation
Power dissipation in the GaN FET is limited by the maximum junction temperature. Refer to the TPH3212PS datasheet.
Circuit description
The circuit comprises a simple half-bridge featuring two TPH3212PS GaN FETs, as indicated in the block diagram of Figure 2.
Two high-voltage ports are provided which can serve as either input or output, depending on the configuration—boost or buck. In
either case one FET acts as the active power switch while the other carries the freewheeling current. The latter device may be
enhanced, as a synchronous rectifier, or not. With GaN FETs the reverse recovery charge is low and there is no need for
additional freewheeling diodes. Two input connectors are provided which can be connected to sources of logic-level command
signals for the hi/lo gate driver. Both inputs may be driven by off-board signal sources; or alternatively, a single signal source
may be connected to an on-board pulse-generator circuit which generates the two non-overlapping pulses. Jumpers determine
how the input signals are used.
An inductor is provided as a starting point for investigation. This is a 440µH toroid intended to demonstrate a reasonable
compromise between size and efficiency for power up to 2.5kW at a switching frequency of 100kHz.
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TPH3212PS
TPH3212PS
Figure 2. Functional block diagram
Using the board
The board can be used for evaluation of basic switching functionality in a variety of circuit configurations. It is not a complete
circuit, but rather a building block. It can be used in steady-state DC/DC converter mode with output power up to 2.5kW.
Configurations
Figure 3 shows the basic power connections for buck and boost modes. For buck mode, the HVdc input (terminals J2, J3) is
connected to the high-voltage supply and the output is taken from terminals J5 and J7. For boost mode, the connections are
reversed.
Note that in boost mode a load must be connected. The load current affects the output voltage up to the transition from DCM to
CCM. In buck mode the load may be an open circuit.
TPH3212PS
TPH3212PS
(a) Buck mode
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TPH3212PS
TPH3212PS
(b) Boost mode
Figure 3. Supply and load connections for buck (a) and boost (b) configurations
Figure 4 shows possible configurations for the gate-drive signals. In Figure 4(a), a single input from an external signal source is
used together with the on-board pulse generation circuit. J4 is used, J6 is left open circuit. Jumpers JP1 and JP2 are in the top
position, as shown. If the high-side transistor is to be the active switch (e.g. buck mode), then the duty cycle of the input source
should simply be set to the desired duty cycle (D). If the low-side transistor is to be the active switch (e.g. boost mode) the duty
cycle of the input source should be set to (1-D), where D is the desired duty cycle of the low-side switch. This configuration
results in synchronous rectification. If it is desired to let the device carrying the freewheeling current act as a diode, then the
appropriate jumper should be placed so that the pull-down resistor is connected to the driver. Figure 4(b) shows a buck-mode
configuration where the low-side device is not enhanced. Finally, Figure 4(c) shows use of two external signal sources as inputs
to the gate driver.
For any configuration, an auxiliary supply voltage of 10V-18V must be supplied at connector J1.
Pull-down resistors R5 and R6 have a value of 4.99k. If a 50Ω signal source is used and 50Ω termination is desired, then R5
and R6 may be replaced (or paralleled) with 1206 size 50Ω resistors.
Boost mode/buck mode operation
For buck mode operation, with input voltage of 400V and output voltage of 48V; 50A max output current is achievable at
2500W with duty cycle of 12%. A typical 400Vin - 200Vout buck operation with 50% duty cycle, 6.5A max output current is seen
at 2500W. On the other hand, for 200Vin - 400Vout boost mode operation at 2.5kW, 12.5A max output current can be reached
with a duty cycle of 50%. Thermal cooling must be enforced for high current switching at all times.
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TPH3212PS
TPH3212PS
(a)
TPH3212PS
TPH3212PS
(b)
TPH3212PS
TPH3212PS
(c)
Figure 4. Input configurations
(a) using a single source for either buck or boost mode
(b) buck mode without synchronous rectification
(c) using two signal sources
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Dead time control
The required form of the gate-drive signals is shown in Figure 5. The times marked A are the dead times when neither transistor
is driven on. The dead time must be greater than zero to avoid shoot-through currents. The Si8230BB gate drive chip ensures a
minimum dead time based on the value of resistor R7, connected to the DT input. The dead time in ns is equal to the resistance
in kΩ x 10, so the default value of 12k corresponds to 120ns. This will add to any dead time already present in the input signals.
The on-board pulse generator circuit; for example, creates dead times of about 60ns. The resulting dead time at the gate pins of
Q1 and Q2 is about 240ns. Either shorting or removing R7 will reduce the dead time to 60ns.
Figure 5. Non-overlapping gate pulses
Design details
See Figure 6 for a detailed circuit schematic and Figure 7 for the PCB layers (also included in the design files). The parts list can
be found in Table 1.
Table 1. TDHBpG2500P100 half-bridge evaluation board bill of materials (BOM)
Designator
Qty
U3
1
D1, D4, D5
FB1, FB2
FB3, FB4,
FB5, FB6
JP1, JP2
J2, J3, J5,
J7
LED1,
LED2, LED3
U1
3
2
2
J1
LDS, LGS
C7
C10, C11,
C12, C14,
C20, C21,
C22
C8, C16,
C17
R15
R9, R12
R4
R14
C19, C23
R3
R7, R11
C13, C15
R8, R10
Description
Package
Part Number
Manufacturer
74LVC1G17DBV
SOT23-5
SN74LVC1G17DBVR
DIODE-DO-214AC
FB0603
FB0805
DO-214AC
603
805
ES1J
MMZ1608S301ATA00
BLM21SN300SZ1D
Texas
Instruments
Fairchild
TDK
Murata
2
4
JP2E
KEYSTONE_7691
JP2
KEYSTONE_7691
68001-403HLF
7691
FCI
Keystone
3
LEDCHIP-LED0805
CHIP-LED0805
SML-211UTT86
Rohm
1
LT3082
SOT223-3
LT3082EST#PBF
1
2
1
7
0.1µF
0.1µF
PJ-002AH
TEKTRONIX-PCB
C-EUC1812
C-USC0603
PJ-002AH
TEKTRONIX-PCB
C1812
C0603
PJ-002AH
131-4353-00
C1812V104KDRACTU
06033C104JAT2A
Linear
Technology
CUI
Tektronix
Kemet
AVX
3
0.1µF
C-USC2225K
C2225K
VJ2225Y104KXGAT
Vishay
1
2
1
1
2
1
2
2
2
0Ω
0Ω
10Ω
100kΩ
100pF
10MΩ
10kΩ
10µF
1kΩ
R-US_R0603
R-US_R1206
R-US_R0805
R-US_R0603
C-USC0603
R-US_R1206
R-US_R0603
C-EUC0805
R-US_R0603
R0603
R1206
R0805
R0603
C0603
R1206
R0603
C0805
R0603
RC0603FR-070RL
ERJ-8GEY0R00V
ERJ-P06J100V
ESR03EZPJ104
06035A101FAT2A
HVC1206T1005JET
ERJ-3GEYJ103V
C0805C106M4PACTU
RC0603FR-071KL
Yageo
Panasonic
Panasonic
Rohm
AVX
Stackpole
Panasonic
Kemet
Yageo
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Value
300Ω
30Ω
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TDHBG2500P100 User Guide
Designator
Qty
Value
Description
Package
Part Number
Manufacturer
C2
C3
C1
R13
C4, C5, C6,
C24
R1, R5, R6
R17, R18,
R19, R20,
R21, R22
R2
C9, C18
U4, U5
1
1
1
1
4
1µF
2.2µF
22µF
2kΩ
4.7nF
C-EUC0805
C-EUC0805
C-USC1206
R-US_R0805
C-EUC1206
C0805
C0805
C1206
R0805
C1206
CC0805ZRY5V8BB105
C2012X5R1E225K125AC
CL31A226MOCLNNC
RC0805FR-072KL
C1206C472KDRACTU
Yageo
TDK
Samsung
Yageo
Kemet
6
6
4.99kΩ
560kΩ
R-US_R1206
R-US_R0805
R1206
R0805
RMCF1206FT4K99
ESR10EZPJ564
Stackpole
Rohm
1
2
2
499kΩ
10µH
R-US_R1206
10uH
74AHC1G86DBV
R1206
EPCOS_B32674
SOT23-5
RMCF1206FT499K
B32794D2106K
SN74AHC1G86DBVR
D2, D3
J4, J6
2
2
BAT54
BU-SMA-G
SOT23
BU-SMA-G
BAT54W
5-1814832-1
U$3
HS1
1
1
CWS-1MP-12640
C220-050-2AE
Stackpole
Epcos
Texas
Instruments
NXP
TE
Connectivity
CWS
Ohmite
U2
Q1, Q2
1
2
2
SI8230BB-D-IS
TPH3212PS
SP2000-0.015-00-54
SiLabs
Transphorm
Bergquist
9900
3049
TRG10R120-11E03Level-VI
SJ61A1
Keystone
Keystone
Cincon
2
2
1
4
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460µH
72mΩ
12V
Inductor
HEATSINKC220-0502AE
SI8230
TPH_TO220VERT_TRI
Thermal pad between
TPH3212 and
heatsink
4-40 screw
Nylon washer shoulder
Adaptor
Bumper cylin 0.312"
dia blk
SOIC16N
TO-220
3M
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Figure 6. Detailed circuit schematic
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(a) PCB top layer
(b) PCB bottom layer
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(c) PCB inner layer 2 (ground plane) + inner layer 3 (power plane)
Figure 7. PCB layers
Probing
Plated through-holes labeled test points (LGS and LDS) are provided for probing the low-side gate pulse and half-bridge
switching node waveform. In order to minimize inductance during measurement, the tip and the ground of the probe should be
directly attached to the sensing points to minimize the sensing loop. For safe, reliable and accurate measurement, a scope
probe tip may be directly soldered to the low-side FET drain and a short ground wire soldered to the low-side FET source. See
Figure 8 for an alternative that does not require soldering the probe tip.
WARNINGS:
There is no specific protection against over-current or over-voltage on this board.
If the on-board pulse generation circuit is used in boost mode, a zero input corresponds to 100% duty cycle for the active lowside switch.
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TDHBG2500P100 User Guide
Figure 8. Low-inductance probing of fast, high-voltage signals
Efficiency has been measured for this circuit in boost mode with 200Vdc in and 400Vdc out, switching at 50kHz and 100kHz
(Figure 9).
Figure 9. Efficiency for a boost 200V:400V converter
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