SAF7741HV - Component Sense

SAF7741HV
Dual IF car radio and audio DSP (N1F)
Rev. 07 — 28 April 2010
Product data sheet
1. General description
The SAF7741HV is a combined Intermediate-Frequency (IF) car radio and audio Digital
Signal Processor (DSP) with several powerful cores integrated onto a single device. It
combines analog IF input, digital radio and audio processing, sample-rate converters and
digital and analog audio output to enhance listening clarity and noise suppression while
reducing multipath channel effect.
The SAF7741 offers user-specific functions which can be configured to match the
software platform required by the systems of individual car-radio manufacturers, thus
providing a high level of product differentiation. It is equipped to work with the TEF7000
and TEF6730 integrated tuners for analog and digital AM/FM decoding and sound
processing
The SAF7741HV consists of two main processing blocks; one for radio and the other for
audio. These blocks demodulate either the IF or the low-IF tuner output, delivering digital
audio to internal Digital-to-Analog Converters (DACs). In addition to the main blocks there
are a number of interfaces and dedicated sub-circuits.
1.1 Radio processing
The IF radio block interfaces to the front-end tuner chips and supports either a so-called
low-IF frequency (of 60 kHz or 300 kHz ) or an IF frequency of 10.7 MHz. Two tuner
interfaces are supported, each of which is suitable for analog FrequencyModulated/Amplitude-Modulated and Weatherband (FM/AM/WX) radio reception as well
as reception of encoded digital signals such as HD Radio and Digital Radio Mondiale
(DRM).
Signals received from the tuner front-end chips are digitized with integrated IntermediateFrequency Analog-to-Digital Converters (IFADCs). The resulting digital signals are then
down-sampled, error-corrected and filtered in the digital domain to be suitable for further
radio and audio processing by the DSPs.
The low-IF interface to the tuner chip combined with the high level of integration allows
cost-effective implementation of the entire tuner/DSP application on a main radio Printed
Circuit Board (PCB).
1.2 Audio processing
The audio processing block receives either external digital signals, or analog signals
which are then digitized by the integrated ADCs. Together with the internal radio audio
signals these inputs are available for further audio processing such as equalization, tone
control and volume control. The output signals of the audio processing block are provided
in digital format on the Host IIS outputs and in analog format on the DAC outputs.
SAF7741HV
NXP Semiconductors
Dual IF car radio and audio DSP (N1F)
2. Features
2.1 Hardware features
SAF7741HV hardware is configured by firmware and host software to meet specific
customer requirements. The firmware is defined by the Read-Only Memory (ROM) code
associated with each DSP.
Remark: The list below describes the maximum hardware configuration. Customers
should consult with NXP to identify the best method of supporting their own particular
requirements.
„ Two IF data-paths of either 2 × IF 10.7 MHz or 2 × low IF 300 kHz input
Remark: The combination of 1 x IF and 1 x low IF is not supported.
„ Two 5th order Sigma-Delta (ΣΔ) IF ADCs for FM/AM/WB (Weather-band) and digital
radio at either IF = 10.7 MHz or low IF = 300 kHz
„ IF signal quadrature-mixing and down-sampling with signal level generation
„ Automatic Gain Control (AGC) of the radio front-end chip in three steps (6 dB for each
step) for the TEF6730 tuner and seven steps (6 dB for each step) for the TEF7000
tuner
„ AGC control of the TEF6730 tuner front-end PIN diodes, with an analog signal via the
Radio General-Purpose DAC (RGP DAC) output: one DAC for each radio data path
„ Integrated IF filter with bandwidth of 100 kHz or 400 kHz
„ Two wideband outputs for external digital radio decoding; one output for each
data-path
„ Two Radio Data System (RDS) decoders
„ Five bit-stream, 3rd order audio, ΣΔ ADCs with an anti-aliasing broadband input-filter
„ Eight configurable analog inputs (differential/stereo/mono) connected to any of the five
ADCs using an analog switchbox
„ Dedicated DSP for the Sample Rate Converter (SRC)
„ Audio Host Inter-IC Sound (IIS) Input/Output (I/O) port, with eight/ten outputs and eight
inputs with an option for slaving the DSP to an external master sample-rate
„ Audio Host IIS Bit-Clock (BCK) and Word-Size (WS) available simultaneously at
full-rate and half-rate
„ Four independent IIS inputs and two independent digital Sony/Philips Digital Interface
Format (SPDIF) inputs also configurable for Digital Versatile Disc/Digital Video Device
(DVD) multi-channel data inputs
„ Radio Host IIS master with separate data in and out lines
„ IIS output with buffer for eight samples for radio applications
„ WatchDog (WDOG) to monitor execution of the DSP main software loop
„ Phase-Lock Loop (PLL) to generate the DSP clock from the oscillator crystal
„ PLL to generate the audio reference sample-rate clock
„ Internal voltage regulator for the 1.8 V supply
„ I2C (Inter-IC Communication) bus-controlled
„ Possibility of powering down unused blocks to reduce power dissipation
„ Qualified in accordance with AEC-Q100
SAF7741_7
Product data sheet
© NXP B.V. 2010. All rights reserved.
Rev. 07 — 28 April 2010
2 of 83
SAF7741HV
NXP Semiconductors
Dual IF car radio and audio DSP (N1F)
2.2 Software Features
The following software features are available for the SAF7741HV:
„ Improved FM weak-signal processing
„ Integrated 19 kHz Multiplexed (MPX) filter and de-emphasis
„ Electronic adjustment of FM/AM level and FM channel separation
„ Variable IF bandwidth. This is controlled partly by the DSP software and depends on
the quality of the reception
„ Selective IF bandwidth for wideband FM, FM Weatherband and AM
„ Variable IF bandwidth on FM, dependent on the adjacent channel interference
„ Digital stereo decoder for FM and AM
„ Advanced digital Interference Absorption Circuit (IAC) for FM and AM
„ Digital Automatic Frequency Control (AFC)
„ RDS demodulation
„ Pause detection for RDS updates with audio mute during RDS updates
„ Baseband audio processing (treble, bass, balance, fader and volume)
„ Maximum of five audio SRCs
„ Dynamic loudness or bass boost
„ Audio level meter
„ Compact Disc (CD) dynamics compressor/expander
„ Improved AM processing with soft mute, high cut control, 6th order low-pass filtering
and AM audio IAC
„ Soft audio mute
„ Extended chime functions
„ Signal level, noise and multi-path detection for AM/FM signal quality information
„ AM audio AGC
„ AGC click suppression in AM mode
3. Applications
The SAF7741HV is designed for use in high-performance car radio systems.
4. Ordering information
Table 1.
Ordering information
Type Number
Package
Name
Description
SAF7741HV
HLQFP144
144 leads; plastic thermal enhanced low profile quad flat package; exposed N115F
die pad
Version
SAF7741_7
Product data sheet
© NXP B.V. 2010. All rights reserved.
Rev. 07 — 28 April 2010
3 of 83
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SAF7741HV
NXP Semiconductors
SAF7741_7
Product data sheet
5. Block diagram
(C) Audio Section
data_in
IQC
PDC1
IFAD_INPUTS_1
4
IF
ADC1
1k PRAM 2k XRAM
8k PROM 2k YRAM
1k YROM
I
INPUT
BUFFER
2x32x24
TDSP1
Q
Rev. 07 — 28 April 2010
Mux
DICE_CLK
2
RGPDAC2
Fosc
IIS
SHARED MEM
128x24
FIR
PDC2
4
Mux
IQC
Fig 1. Block diagram of SAF7741HV radio section
4
T1EIISnterface
i
3
4
10
T1
TDSP_IOF1..10
(A) Audio Section
T2
(B)Audio Section
RDSDEC1
RDS_CLK
RDS_DATA1
RDSDEC2
RDS_CLK2
RDS_DATA2
TDSP2
SHARED MEM
128x24
I
0.5k
PRAM
8k PROM
2k XRAM
2k YRAM
1k YROM
SAF7741HV
4 of 83
© NXP B.V. 2010. All rights reserved.
Dual IF car radio and audio DSP (N1F)
INPUT
BUFFER
2x32x24
OUT
MUXING
CRD
Q
AGC
IF
ADC2
ws,bck,
data_out
IIS
RGP
DAC2
AGC2_1
4
CRD
8FS
IIS
DIV
AGC2_2
IFAD_INPUTS_2
CRD
RGP
DAC1
RGPDAC1
100kHz/
400kHz
IIS
3
3
FIR
4
1
TDSP1E
AGC
AGC1_1
AGC1_2
DR _OUT
shared
mem
128x24
0.5k
2k XRAM
PRAM
2k YRAM
8k PROM
SAF7741HV
NXP Semiconductors
Dual IF car radio and audio DSP (N1F)
SAF7741HV
SD_HOST_
IN1..5
4
5
A
N
A
LS
OE
GL
SE
OC
UT
RO
CR
E
AIN0_R
AIN0_L
AIN1_R
AIN1_L
AIN2_R
AIN2_L
AIN3
AIN4
IN1
SPDIF1_IN2
3
BITSLICER
BITSLICER
dac_fl
dac_fr
AD3
dac_rl
ADSP
AD4
D
I
G
I
T
A
L
S
E
L
E
C
T
SO
OR
U
R
C
E
DIGITAL
SPDIF
DECODER
DIGITAL
SPDIF
DECODER
(A) RADIO
SECTION
dac_rr
AUDIO
dac_center
PROCESSING
dac_subw
AD5
3
IN4
WS_HOST
AD2
3
IN3
BCK_HOST
AD1
3
IN2
SPDIF1_IN1
SELECTOR
WS_HOST
FOSC
OSC
DIV
DAC
DAC_FL
DAC
DAC_FR
DAC
DAC_RL
DAC
DAC_RR
DAC
DAC_CENTER
DAC
DAC_SUBW
SDSP
8
800XRAM
1024YROM
7168PROM
256 PRAM
1280 YRAM
2816 XRAM
9216 PROM
WATCHDOG
dsp_clk
(B) RADIO
SECTION
FS_SYS
SD_HOST_OUT1..4
DSP
PLL
ADSP_IOF4..11
SCL
SDA
12C
SCL_DICE
SDA_DICE
Fosc
D PLL
I AUDIO
V
/4
FSREF_RADIO
FSREF_AUDIO
ADSP-TDSP1E
INTERFACE
(C) RADIO
SECTION
REGULATOR
4
Fig 2. Block diagram of SAF7741HV audio section
SAF7741_7
Product data sheet
© NXP B.V. 2010. All rights reserved.
Rev. 07 — 28 April 2010
5 of 83
SAF7741HV
NXP Semiconductors
Dual IF car radio and audio DSP (N1F)
6. Pinning information
DIC E_ CL KN
DIC E_ CL KP
TDI
RGPDAC2
RGPDAC1
TMS
IFADQ_ N 2
IFADQ_ P2
IFADI_ N2
IFADI_ P2
VD DA _1 V8
VIFAD BG
VSS _IFAD
VIFAD P
VIFAD N
VD D_ IFAD
IFADQ_ N 1
IFADQ_ P1
IFADI_ N1
IFADI_ P1
TRS TN
TCK
TDO
VSS S4
VD DD 4
SD A_ DIC E
SC L_ DIC E
VSS Q4
VD DQ4
AGC 2_ 2
AGC 2_ 1
AGC 1_ 2
AGC 1_ 1
VSS _M EM2
VD D_ MEM 2
TDS P_IOF1 0
6.1 Pinning
TDS P_ IOF 9
TDS P_ IOF 8
TDS P_ IOF 7
TDS P_ IOF 6
TDS P_ IOF 5
TDS P_ IOF 4
TDS P_ IOF 3
TDS P_ IOF 2
TDS P_ IOF 1
VD DD 3
VSSS3_DC
DR_SD_OUT_Q
DR_SD_OUT_I
DR_WS_OUT
DR_BCK_OUT
T1E_SD_IN
_
T1E_SD_OUT
_
T1E_WS
_
T1E _BCK
VD DQ3
VSS Q3
AD SP_ IO F11
AD SP_ IO F10
AD SP_ IO F9
AD SP_ IO F8
AD SP_ IO F7
AD SP_ IOF 6
AD SP_ IOF 5
AD SP_ IOF 4
SD _H OST_ OUT4
SD _H OST_OUT3
SD _H OST_ OUT2
SD _H OST_ OUT1
BC K_ HOST
WS_ HOS T
SD _H OST_IN5
DAC_RR
DAC_RL
VDACN
VDACP
VDD_DAC
DAC_FR
DAC_FL
DAC_SUBW
DAC_CENTER
V SSS2
VD D D2
RD S_ CL K1
R DS _D ATA1
RD S_ CL K2
R DS _D ATA2
R ESETN
FS _SY S
VS S_M EM1
V DD _M EM1
S CL
SD A
VSSQ2
VD DQ2
BC K_ IN2
WS_ IN2
S D_ IN2
BC K_ IN3
WS_ IN3
S D_ IN3
BC K_ IN4
WS_ IN4
S D_ IN4
SD _ HOST_ IN1
SD _ HOST_ IN2
SD _ HOST_ IN3
SD _ HOST_ IN4
OSC _ R EF_N
OSC _ IN
OSC _OU T
OSC _R EF_ P
AIN0 _R
AIN 0_ R _R EF
A IN 0_L _R EF
AIN0 _L
AIN1 _R
AIN1 _L
AIN2 _R
AIN 2_ R _R EF
A IN 2_L _R EF
AIN2 _L
VDD A_1 V8 _A DC
VAD CN
VADC P
VR EFAD
AIN3
A IN 3 _R EF
AIN4
A IN 4 _R EF
V DD_ A DC
SPD IF 1D _D VD 3 4
SPD IF 2D _D VD 56
V DD D1
V SSS1
B CK_ IN1
WS_ IN1
SD_ IN1
VDD _R EG
FEBR EG
CONR EG
GAPR EG
VD DQ1
VSSQ1
Fig 3. Pin configuration for the SAF7741HV
Table 2.
Pin allocation table
Pin Name
Pin
Number
Description
Pin Type
OSC_REF_N
1
Ground reference for oscillator, PLLs and tuner clock generator
vssco
OSC_IN
2
Crystal oscillator input
apio
OSC_OUT
3
Crystal oscillator output
apio
OSC_REF_P
4
1.8 V reference supply for oscillator, PLLs and tuner clock generator
vddco
AIN0_R
5
Right channel analog audio input 0
apio
AIN0_R_REF
6
Right common mode reference audio input 0
apio
AIN0_L_REF
7
Left common mode reference audio input 0
apio
AIN0_L
8
Left channel analog audio input 0
apio
AIN1_R
9
Right channel analog audio input 1
apio
AIN1_L
10
Left channel analog audio input 1
apio
AIN2_R
11
Right channel analog audio input 2
apio
SAF7741_7
Product data sheet
© NXP B.V. 2010. All rights reserved.
Rev. 07 — 28 April 2010
6 of 83
SAF7741HV
NXP Semiconductors
Dual IF car radio and audio DSP (N1F)
Table 2.
Pin allocation table …continued
Pin Name
Pin
Number
Description
Pin Type
AIN2_R_REF
12
Right common mode reference audio input 2
apio
AIN2_L_REF
13
Left common mode reference audio input 2
apio
AIN2_L
14
Left channel analog audio input 2
apio
VDDA_1V8_ADC
15
1.8 V supply for ADC
vddco
VADCN
16
Ground reference for audio ADCs and RGPDACs
apio
VADCP
17
Positive reference voltage for Audio ADCs and RGPDACs
apio
VREFAD
18
Common mode reference voltage ADCs
apio
AIN3
19
Analog audio input 3
apio
AIN3_REF
20
Common mode reference audio input 3
apio
AIN4
21
Analog audio input 4
apio
AIN4_REF
22
Common mode reference audio input 4
apio
VDD_ADC
23
3.3 V supply for audio ADCs
SPDIF_IN1
24
vddco
Input 1 SPDIF analog / input DVD-A channels 3 and 4
[1]
[1]
apio
apio
SPDIF_IN2
25
Input 2 SPDIF analog / input DVD-A channels 5 and 6
VDDD1
26
1.8 V positive supply (digital core)
vddi
VSSS1
27
Ground supply (digital core)
vssis
BCK_IN1
28
Inter-IC Sound
(I2S)
source 1 Bit Clock input
bpts5ptpht5v
WS_IN1
29
I2S
SD_IN1
30
I2S source 1 data input/input DVD-A channels 1 and 2
bpts5ptpht5v
VDD_REG
31
3.3 V supply for regulator
vddco
FEBREG
32
Feedback input monitoring the 1.8 V
apio
CONREG
33
Control output for external Positive-channel Metal Oxide Semiconductor
(PMOS) transistor
apio
GAPREG
34
Decoupling for regulator bandgap voltage
apio
VDDQ1
35
3.3 V positive supply (peripheral cells)
vdde
VSSQ1
36
Ground supply (peripheral cells)
vsse
DAC_RR
37
Audio output for the rear-right speaker
apio
DAC_RL
38
Audio output for the rear-left speaker
apio
VDACN
39
Ground reference voltage for the Audio DACs (ADAC)
apio
source 1 Word Select input
bpts5ptpht5v
VDACP
40
Positive reference voltage for the Audio DACs (ADAC)
apio
VDD_DAC
41
3.3 V supply for the Audio DACs (ADAC)
vddco
DAC_FR
42
Audio output for the front-right speaker
apio
DAC_FL
43
Audio output for the front-left speaker
apio
DAC_SUBW
44
Audio output for the sub-woofer
apio
DAC_CENTER
45
Audio output for the centre speaker
apio
VSSS2
46
Ground supply (digital core)
vssis
VDDD2
47
1.8 V positive supply (digital core)
vddi
RDS_CLK1
48
RDS bit clock (CLK) output 1/RDS external clock input 1
bpts5ptpht5v
RDS_DATA1
49
RDS data output 1
bpts5ptpht5v
RDS_CLK2
50
RDS bit clock output 2/RDS external clock input 2
bpts5ptpht5v
SAF7741_7
Product data sheet
© NXP B.V. 2010. All rights reserved.
Rev. 07 — 28 April 2010
7 of 83
SAF7741HV
NXP Semiconductors
Dual IF car radio and audio DSP (N1F)
Table 2.
Pin allocation table …continued
Pin Name
Pin
Number
Description
Pin Type
RDS_DATA2
51
RDS data output 2
bpts5ptpht5v
RESETN
52
General reset of chip (active low)
bpts5ptpht5v
FS_SYS
53
Fs system clock in/output
bpts10thdt5v
VSS_MEM1
54
Ground supply (digital core)
vssi
VDD_MEM1
55
1.8 V positive supply (memories)
vddcobf
I2C
bus
iic3m4sclt5v
SCL
56
Serial clock input
SDA
57
Serial data input/output I2C bus
iic3m4sdat5v
VSSQ2
58
Ground supply (peripheral cells)
vsse
VDDQ2
59
3.3 V positive supply (peripheral cells)
vdde
BCK_IN2
60
IIS source 2 Bit Clock input
bpts5ptpht5v
WS_IN2
61
IIS source 2 Word Select input
bpts5ptpht5v
SD_IN2
62
IIS source 2 data input
bpts5ptpht5v
BCK_IN3
63
IIS source 3 Bit Clock input
bpts5ptpht5v
WS_IN3
64
IIS source 3 Word Select input
bpts5ptpht5v
SD_IN3
65
IIS source 3 data input
bpts5ptpht5v
BCK_IN4
66
IIS source 4 Bit Clock input
bpts5ptpht5v
WS_IN4
67
IIS source 4 Word Select input
bpts5ptpht5v
SD_IN4
68
IIS source 4 data input/input SPDIF 1 digital
bpts5ptpht5v
SD_HOST_IN1
69
Host I2S 1 data input
bpts5ptpht5v
SD_HOST_IN2
70
Host I2S 2 data input
bpts5ptpht5v
SD_HOST_IN3
71
Host
I2S
3 data input
bpts5ptpht5v
I2S
SD_HOST_IN4
72
Host
4 data input
bpts5ptpht5v
SD_HOST_IN5
73
Host I2S 5 data input
bpts5ptpht5v
WS_HOST
74
Host I2S Word Select output/input
bpts10thdt5v
BCK_HOST
75
Host
I2S
Bit Clock output/input
bpts10thdt5v
I2S
SD_HOST_OUT1
76
Host
1 data output
bpts10thdt5v
SD_HOST_OUT2
77
Host I2S 2 data output
bpts10thdt5v
SD_HOST_OUT3
78
Host I2S 3 data output
bpts10thdt5v
SD_HOST_OUT4
I2S
4 data output
bpts10thdt5v
79
Host
ADSP_IOF4
80
Audio DSP (ADSP) general purpose I/O flag 4
bpts5ptpht5v
ADSP_IOF5
81
ADSP general purpose I/O flag 5
bpts5ptpht5v
ADSP_IOF6
82
Audio/SCR DSP general purpose I/O flag 6
bpts5ptpht5v
ADSP_IOF7
83
Audio/SRC DSP general purpose I/O flag 7
bpts5ptpht5v
ADSP_IOF8
84
Audio/SRC DSP general purpose I/O flag 8
bpts5ptpht5v
ADSP_IOF9
85
Audio/SRC DSP general purpose I/O flag 9
bpts5ptpht5v
ADSP_IOF10
86
Audio/SRC DSP general purpose I/O flag 10
bpts5ptpht5v
ADSP_IOF11
87
Audio/SRC DSP general purpose I/O flag 11
bpts5ptpht5v
VSSQ3
88
Ground supply (peripheral cells)
vsse
VDDQ3
89
3.3 V positive supply (peripheral cells)
vdde
T1E_BCK
90
Tuner I2S BCK output / digital radio interface 2 bit clock output
bpts10thdt5v
SAF7741_7
Product data sheet
© NXP B.V. 2010. All rights reserved.
Rev. 07 — 28 April 2010
8 of 83
SAF7741HV
NXP Semiconductors
Dual IF car radio and audio DSP (N1F)
Table 2.
Pin allocation table …continued
Pin Name
Pin
Number
Description
Pin Type
T1E_WS
91
Tuner I2S WS output / digital radio interface 2 word-select output
bpts10thdt5v
I2S
T1E_SD_OUT
92
Serial data output / Serial data output digital radio interface 2 word bpts10thdt5v
Tuner
select signal
T1E_SD_IN
93
Tuner I2S Serial data input / Serial data output digital radio interface 2
Q-signal
DR_BCK_OUT
94
Digital radio interface 1 bit clock output
bpts10thdt5v
DR_WS_OUT
95
Digital radio interface 1 word-select output
bpts10thdt5v
DR_SD_OUT_I
96
Serial data output digital radio interface 1 I-signal
bpts10thdt5v
DR_SD_OUT_Q
97
Serial data output digital radio interface 1 Q-signal
bpts10thdt5v
VSSS3_DC
98
Digital core DC ground connection
vssis
VDDD3
99
1.8 V positive supply (digital core)
vddi
TDSP_IOF1
100
Tuner DSP (TDSP) general purpose I/O flag 1
bpts5ptpht5v
TDSP_IOF2
101
Tuner DSP general purpose I/O flag 2
bpts5ptpht5v
TDSP_IOF3
102
Tuner DSP general purpose I/O flag 3
bpts5ptpht5v
TDSP_IOF4
103
Tuner DSP general purpose I/O flag 4
bpts5ptpht5v
TDSP_IOF5
104
Tuner DSP general purpose I/O flag 5
bpts5ptpht5v
TDSP_IOF6
105
Tuner DSP general purpose I/O flag 6
bpts5ptpht5v
TDSP_IOF7
106
Tuner DSP general purpose I/O flag 7
bpts5ptpht5v
TDSP_IOF8
107
Tuner DSP general purpose I/O flag 8
bpts5ptpht5v
TDSP_IOF9
108
Tuner DSP general purpose I/O flag 9
bpts5ptpht5v
TDSP_IOF10
109
Tuner DSP general purpose I/O flag 10
bpts5ptpht5v
bpts10thdt5v
VDD_MEM2
110
1.8 V positive supply (memories)
vddco
VSS_MEM2
111
Ground supply (digital core)
vssi
AGC1_1
112
Command input from TEF7000 connected to IFAD1 / Least Significant Bit
(LSB) gain control output to TEF6730 tuner connected to IFAD1
bpts5ptpht5v
AGC1_2
113
Request output to TEF7000 tuner connected to IFAD1 / Most Significant Bit bpts5ptpht5v
(MSB) gain control output to TEF6730 tuner connected to IFAD1
AGC2_1
114
Command input from TEF7000 connected to IFAD2 / Least Significant Bit
(LSB) gain control output to TEF6730 tuner connected to IFAD2
AGC2_2
115
Request output to TEF7000 tuner connected to IFAD2 / Most Significant Bit bpts5ptpht5v
(MSB) gain control output to TEF6730 tuner connected to IFAD2
VDDQ4
116
3.3 V positive supply (peripheral cells)
vdde
VSSQ4
117
Ground supply (peripheral cells)
vsse
I2C
bus
bpts5ptpht5v
iic3m4sclt5v
SCL_DICE
118
SCL output of the tuner
SDA_DICE
119
SDA input/output of the tuner I2C bus
iic3m4sdat5v
VDDD4
120
1.8 V positive supply (digital core)
vddi
VSSS4
121
Ground supply (digital core)
vssis
TDO
122
JTAG Test control data output
bpts5ptpht5v
TCK
123
JTAG Test clock
bpts5ptpht5v
TRSTN
124
JTAG Test reset, active low
bpts5ptpht5v
IFADI_P1
125
Positive phase of the first differential IF I input
aprf3v3
IFADI_N1
126
Negative phase of the first differential IF I input
aprf3v3
SAF7741_7
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Rev. 07 — 28 April 2010
9 of 83
SAF7741HV
NXP Semiconductors
Dual IF car radio and audio DSP (N1F)
Table 2.
Pin allocation table …continued
Pin Name
Pin
Number
Description
Pin Type
IFADQ_P1
127
Positive phase of the first differential IF Q input
aprf3v3
IFADQ_N1
128
Negative phase of the first differential IF Q input
aprf3v3
VDD_IFAD
129
3.3 V supply for IF ADCs and RGPDACs
vddco
VIFADN
130
Ground reference voltage for IF ADCs
apio
VIFADP
131
Decoupling for IF ADCs positive reference voltage
apio
VSS_IFAD
132
Ground supply for IF ADCs and RGPDACs
vssco
VIFADBG
133
Decoupling for IF ADCs bandgap voltage
apio
VDDA_1V8
134
1.8 V supply for IFADC and Audio ADCs
vddco
IFADI_P2
135
Positive phase of the second differential IF I input
aprf3v3
IFADI_N2
136
Negative phase of the second differential IF I input
aprf3v3
IFADQ_P2
137
Positive phase of the second differential IF Q input
aprf3v3
IFADQ_N2
138
Negative phase of the second differential IF Q input
aprf3v3
TMS
139
JTAG Test mode select
bpts5ptpht5v
RGPDAC1
140
RGP DAC 1 output
apio
RGPDAC2
141
RGP DAC 2 output
apio
TDI
142
JTAG Test control data input
bpts5ptpht5v
DICE_CLKP
143
100 kHz/400 kHz clock reference output to TEF6730/TEF7000 tuner
(positive)
apio
DICE_CLKN
144
100 kHz/400 kHz clock reference output to TEF6730/TEF7000 tuner
(negative)
apio
[1]
The maximum input voltage is 3.3 volts.
6.2 Pin description
Table 3.
Pad name description
Pad Name
Description
IICT5V
iic3m4sdat5v
IIC pad: 5 V-tolerant; data signal
iic3m4sclt5v
IIC pad: 5 V-tolerant; clock signal
IOT5V
bpts5ptpht5v
Bi-directional pad; plain input; 3-state output; SSO control; TTL with programmable hysteresis;
programmable pull-up and pull-down, repeater; 5 V- tolerant
bpts10thdt5v
Bi-directional pad; plain input ; 3-state output; 10 ns slew-rate control; TTL with hysteresis; pull-down; 5
V-tolerant
IO3V3
apio
Analog pad; analog input/output for RF applications; ESD diode to VDD supply
aprf
Analog pad; analog input/output for RF applications; ESD diode to VDDE supply
aprf3v3
Analog pad; analog supply for high-voltage application; high trigger-voltage ESD protection
IO3V3 (supply)
vddco
VDD pad connected to CORE VDD
vddcobf
VDD pad connected to CORE VDD with BigFET protection
vdde
VDD pad connected to external (noisy) VDD supply rail
SAF7741_7
Product data sheet
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Rev. 07 — 28 April 2010
10 of 83
SAF7741HV
NXP Semiconductors
Dual IF car radio and audio DSP (N1F)
Table 3.
Pad name description …continued
Pad Name
Description
vddi
VDD pad connected to CORE VDD and internal VDD supply rail in I/O ring
vssi
VSS pad connected to CORE VSS and internal VSS supply rail in I/O ring
vsse
VSS pad connected to external (noisy) VSS supply rail
vssis
VSS pad connected to CORE VSS, internal VSS supply rail in I/O ring and substrate rail in I/O ring
vssco
VSS pad connected to CORE VSS
7. Functional description
7.1 Radio subsystem
The complete radio system is able to receive FM, AM, Weatherband, RDS and FM/AM
digital radio. The SAF7741HV radio section will incorporate the following features (see
Figure 1):
• Two IFADCs to digitize the incoming analog IF signals from the tuner(s)
• Two Primary Decimation Chains (PDCs) for analog and digital radio reception,
including digital mixing to Zero IF (ZIF)
• Software-based radio functionality running on one or more DSPs depending on the
features set and dual or single tuner usage
The IFADC digitizes the incoming Near-Zero Intermediate Frequency (NZIF) signals. The
IFADC is a baseband ΣΔ ADC.
The PDC decimates the incoming data stream by a factor of 128 before passing it to the
software radio for processing.
For digital radio reception the PDC decimates the incoming data stream by 64 before it is
forwarded to the external co-processor.
The software radio consists of three Tuner DSPs: TDSP1, TDSP2 and TDSP1E. All three
TDSPs have a basically identical structure, but TDSP1 and TDSP2 are extended with:
• A Finite Impulse Response (FIR) filter
• CORDIC (COordinate Rotation DIgital Calculation) Rotate and De-rotate (CRD)
TDSP1E is extended with a CRD only. Each FIR (controlled by the TDSP) is used for
variable bandwidth control and for the Polar-to-Rectangular (P->R), Rectangular-to-Polar
(R->P) and DIV conversions that will be used for demodulation. Added to this block is a
2LOG(LD(x)) function.
In addition, a Radio General-Purpose DAC (RGPDAC) and an RDS decoder are included
for each tuner channel.
The SAF7741HV chip is capable of handling full dual radio. Depending on the firmware,
several such configurations are possible:
• Dual radio with two stereo-audio output channels. The attainable performance
depends on the DSP tuner firmware. The available feature set is less than that for
one-channel radio
SAF7741_7
Product data sheet
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Rev. 07 — 28 April 2010
11 of 83
SAF7741HV
NXP Semiconductors
Dual IF car radio and audio DSP (N1F)
• Dual tuner, which offers antenna, phased-array or MPX diversity
• Single tuner on the smallest possible hardware set: preferably one DSP
7.1.1 IFADCs
For each tuner path two fully differential ΣΔ IFADCs are used for the I and Q paths. For
each IFADC two fully differential input nodes are fed with a 300 kHz input signal. This
design provides good suppression of even harmonics. The noise is shaped by a 5th order
loop filter to get sufficient resolution in the band of interest, and for complex filtering the
input signal of the I and Q paths has a 90° phase shift.
The IFADCs are sampled by a 41.6 MHz clock. The output is a 1-bit bitstream signal with
a frequency of 41.6 MHz (see Figure 4).
10.4 MHz
IFADINPP
Rin
41.6 MHz
MIXER
Gm
Rin
IFADINPP
RDAC
LOOP
FILTER
QUANTIZER
VOUT
RDAC
DAC
41.6 MHz
Fig 4. Simplified block diagram of an IFADC
7.1.1.1
TEF6730 tuner compatibility mode
In this mode the IF input signal is 10.7 MHz differential. The mixer is in front of the IFADC,
and this converts the input signal down to 300 kHz using a quadrature 10.4 MHz square
wave. The 300 kHz down-converted signal is then fed to the IFADCs as I and Q signals.
Switching to TEF6730 tuner compatibility mode is performed via the I2C interface and is
only available to the microprocessor.
7.1.2 Primary decimation chain
The PDC (see Figure 5) decimates the incoming sample rate from the IFADC, shifts the
signal to baseband and applies Amplitude Gain Control (AGC) step compensation, linear
AGC correction and IQ Correction (IQC).
SAF7741_7
Product data sheet
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12 of 83
SAF7741HV
NXP Semiconductors
Dual IF car radio and audio DSP (N1F)
IQ FROM IFADC
TO DSP
IQC
PDC
LD INTERFACE
I2S
AGC
TUNER
TO DIGITAL RADIO COPROCESSOR
DSP
I2C
Fig 5. Block diagram of the PDC
The PDC decimates the incoming signal by 16 before shifting it to the baseband and
creating two paths: ‘wanted’ and ‘image’. After another decimation by two, the AGC stage
takes place to compensate for the tuner gain-reduction steps. The linear gain control
stage makes sure that there is maximum use of the dynamic range. After another
decimation by two the IQC stage takes place to compensate for imperfections in the
analog mixer of the tuner by measuring and correcting possible aliases between the
wanted and image signals. The PDC settings allow for different IF bandwidth corrections
and for local oscillator swap of the TEF7000. Communication between the tuner and
SAF7741HV uses the proprietary two-line LD interface for AGC, injection-mode and
bandwidth settings.
The PDC has two data outputs: one parallel inteface to the TDSPs and one I2S-like
interface to the external digital radio co-processor.
7.1.2.1
PDC Input
The PDC input is a complex bit stream from the 5th order converter. The I and Q bit
streams each have a sample rate of 41.6 MSa/s.
7.1.2.2
Input decimation
The input sample rate of 41.6 MSa/s is decimated by 16 MSa/s to 2.6 MSa/s.
7.1.2.3
Shift-to-baseband mixer
For the wanted signal, the TEF7000 tuner has an IF frequency of 300 kHz for FM and
60 kHz for AM: for the image signal these values are −300 kHz and −60 kHz respectively.
The shift-to-baseband mixer shifts the wanted signal by −fmix to baseband and the image
signal by +fmix. The mixer has two independent registers for the wanted frequency
alignment:
• fmix_0 with high-side injection
• fmix_1 with low-side injection
In TEF6730 mode fmix_0 and fmix_1 are 300 kHz for both FM and AM
SAF7741_7
Product data sheet
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13 of 83
SAF7741HV
NXP Semiconductors
Dual IF car radio and audio DSP (N1F)
I2C/DSP
MUX
I2C/DSP
FROM IFADC
I2C/DSP
2
16
AGC
2
I2C/DSP
2
IQC
2
2
I2S
AM
IBOC
TO DIGITAL RADIO
CO-PROCESSOR
MUX
TO DSP
2
I2C/DSP
I2C/DSP
COMMANDS
LD
REQUESTS INTERFACE
COMPLEX SIGNAL
Fig 6. PDC Block diagram for one data path
7.1.2.4
Mixer output decimation
The output signal of the shift-to-baseband mixer is decimated by two to 1.3 MSa/s before
it enters the AGC stage.
7.1.2.5
Gain control
Both the wanted and the image signals are gain-controlled in the AGC stage. This
contains a stepped gain stage, a linear gain stage and IF signal level detection. The linear
gain stage ensures that maximum use is made of the dynamic range (see Figure 7).
Max.DSP EVEL
L
HIGH LEVEL
LOW LEVEL
a: INPUT IN
TO AGC
b: AFTER STEPPED
AGC
Fig 7. Stepped AGC signal levels
Various gain-step compensation controls are implemented to reduce the audible effects of
the gain steps. To increase the dynamic range of the tuner, gain-step compensation takes
place in the AGC block of the PDC for:
• Step-response amplitude
• Step-response waveform
• Step-response timing
SAF7741_7
Product data sheet
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14 of 83
SAF7741HV
NXP Semiconductors
Dual IF car radio and audio DSP (N1F)
7.1.2.6
Stepped gain amplitude
The tuner communicates a new gain setting to the SAF7741HV via the DL interface. The
SAF7741HV has four independent and different stepped AGC banks:
•
•
•
•
AGC_A
AGC_B
AGC_C
AGC_D
The number of steps for each AGC bank and the associated resolution is listed in Table 4.
Table 4.
Stepped AGC gain reduction
AGC
Function
Number of Steps Number of Bits
Resolution
AGC_A
LNA_1
16
12
50 mdB
AGC_B
LNA_2
8
11
50 mdB
AGC_C
Mixer
4
10
50 mdB
AGC_D
IF
4
10
50 mdB
The AGC tables contain the corresponding gain reduction values of the tuner, expressed
in bits. Zero gain reduction is at the top of each table. The tuner has random access to the
table. The maximum single amplitude change of the AGC is 16 bits −1 LSB. This is
equivalent to 96 dB. This maximum amplitude change can be made in any combination of
AGC values from AGC_A up to AGC_D. The last gain reduction command from the tuner
is readable by the DSP in the AGC Change registers. Found in AGC Data Out registers
are:
• The total stepped gain reduction
• The linear gain reduction
• The resulting gain reduction
The TEF7000 tuner uses:
• AGC_A and AGC_B for wideband AGC (in this case LNA_1 and LNA_2)
• AGC_C for the mixer AGC
• AGC_D is used as IF_AGC
Remark: The AGC_A, AGC_B and AGC_D replace the pin-diode AGC in the TEF6730.
7.1.2.7
Step-response waveform
The compensating step-response waveform depends on the step response type to be
compensated. Compensating waveforms for the LNA and the mixer gain steps are stored
in ROM for both the IF response and the wideband response. The IF response is derived
from the PDC response before the AGC stage.
The step-response waveform from the ROM is used when the gain change is less than
12 dB. This results in compensation which is not audible and which therefore does not
require muting.
SAF7741_7
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15 of 83
SAF7741HV
NXP Semiconductors
Dual IF car radio and audio DSP (N1F)
When there is a gain change of more than 12 dB this is made step-wise without running
the compensation waveform. This is the case with either Alternate Frequency (AF)
updates or a pre-set change. These functions are always used in a muted condition and
are therefore not audible.
7.1.2.8
Step-response timing
In order to align for the bandwidth of the analog circuits, an alignment is made between
the response length and the response delay. This alignment is separate for the wideband
and the IF responses.
Both the delay and the response length for the IF response are dominated by the PDC
response before the AGC. These values are independent of the tuner response. The
wideband response is different for analog and for digital AM/FM.
DELAY
RESPONSE LENGTH
a: Low Bandwidth Step response
DELAY
RESPONSE LENGTH
b: High Bandwidth Step response
Fig 8. Step response length alignment for different tuner bandwidths
7.1.2.9
Perfect step compensation
Perfect step compensation of the tuner gain steps is made possible for signals within the
IF signal band by alignments of amplitude, waveform and waveform delay. Near-perfect
alignment is possible for off-centre signals within the IF signal band.
7.1.2.10
Non-perfect step compensation
Perfect compensation of the tuner gain steps is not possible for signals outside the IF
signal band. In such cases the resulting interference must be suppressed. In the PDC,
four signalling bits are provided for this purpose:
•
•
•
•
AGC_A_CHANGE
AGC_B_CHANGE
AGC_C_CHANGE
AGC_D_CHANGE
These bits can be read by the DSP and a soft-mute signal can be generated when
required.
7.1.2.11 AGC linear gain
Data-path signals that exceed a certain level are kept constant in a linear controlled-gain
stage (see Figure 9). Linear control avoids overload of the following signal stages and
makes sure that maximum use is made of the data path’s dynamic range. The I2C
interface sets the reference level for linear control as well as the corresponding attack and
delay values.
SAF7741_7
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SAF7741HV
NXP Semiconductors
Max. DSP level
Linear reference level
Dual IF car radio and audio DSP (N1F)
a: After Stepped AGC
a: After Linear AGC
Fig 9. Linear AGC signal levels
The linear control reference level should be above the maximum uncontrolled input level
of the linear control stage (See Figure 7). Settings of the reference level below the
maximum uncontrolled input level will result in a distorted output signal.
7.1.2.12
IF signal level detection
Signal level detection for wideband AGC is handled in the tuner. The resulting AGC steps
are then interfaced to SAF7741HV and a step compensation is made. The IF AGC is
controlled by level detectors within the PDC, and by IF detector high- and low-level
settings which can be set via IC. The level detectors in the PDC communicate with the
tuner to increase or decrease the level of the incoming signal.
The IF detector bandwidth is shown in Figure 10.
dB
500
AGC DETCTION BANDWIDTH
1000
1500
2000
2500
KHz
-20
-40
-60
-80
-100
-120
Fig 10. IF detector bandwidth
7.1.2.13
AGC output decimation
The output signal of the AGC is decimated by two to 650 kSa/s before it enters the IQC
stage.
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Dual IF car radio and audio DSP (N1F)
7.1.2.14
IQC stage
The IQC stage suppresses the image mirror co-channel within the wanted signal and
corrects for gain and phase imperfections in the analog mixer and the subsequent analog
data base. This is done by measuring and correcting possible correlations between the
wanted and the image signals.
The IQC is an adaptive algorithm based on a Normalized Least Mean Square (NLMS).
Normalization is performed off the data path in the Least Mean Square (LMS) adaptation
engine itself, and therefore does not affect the output signals of the PDC. It takes place in
steps of 6.0 dB with an associated averaging filter. Four coefficients are available to allow
the IQC to manage frequency dependencies introduced by the analog IF filters. The
adaptation rate parameter (mu) is controlled automatically at startup to make sure that the
coefficients converge correctly.
An adaptation freeze level can be set to prevent tap drift in weak signal conditions.n
TEF6730 mode the IQC stage is bypassed.
7.1.2.15
PDC output
The PDC has two outputs; one to the software radio and the other to the external pins. For
the output to the software radio a choice can be made between three signals. The first of
these is the wanted signal at 650 kSa/s. The bandwidth for this is shown in .Figure 11
dB
200
400
BANDWIDTH AT 16fs
600
800
1000
1200
KHz
-20
-40
-60
-80
-100
-120
Fig 11. PDC to EPICS output bandwidth at 650 kSa/s
The second choice is the wanted signal at 325 kSa/s. This is shown in Figure 11. The third
choice is the wanted/image signal pair at 325 kSa/s. The signal bandwidth for this is
shown in Figure 12.
SAF7741_7
Product data sheet
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Rev. 07 — 28 April 2010
18 of 83
SAF7741HV
NXP Semiconductors
Dual IF car radio and audio DSP (N1F)
100
dB
BANDWIDTH AT 8fs
300
400
200
500
600
KHz
-20
-40
-60
-80
-100
-120
Fig 12. PDC to EPICS output bandwidth at 325 kSa/s
For the I2S external output a choice can be made between FM and AM digital radio, both
at 650 kSa/s and both wanted-signal only. All PDC input and output signals are complex.
−60
−40
−20
dB
20
40
60
kHz
−20
−40
−60
−80
−100
Fig 13. AM digital radio bandwidth
7.1.2.16
LD interface
The SAF7741HV is designed for a generic tuner with TEF7000 architecture.
Communication between the tuner and the SAF7741HV uses the proprietary two-line LD
interface for AGC, injection-mode and bandwidth settings.
The tuner sends commands to the SAF7741HV while the SAF7741HV sends requests to
the tuner. A tuner command is always executed unconditionally by the SAF7741HV, but a
request from the SAF7741HV to the TEF7000 may be ignored.
SAF7741_7
Product data sheet
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19 of 83
SAF7741HV
NXP Semiconductors
Dual IF car radio and audio DSP (N1F)
AGC commands define the gain compensation required to compensate for the gain
change of the tuner, and can also reset detectors in the stepped and the linear AGC.
The LD interface commands and their bit allocation are listed in Table 5. Refer to the tuner
data sheet for the different signal bands.
Table 5.
LD interface command bit allocation
Bit
Function
Bit
Function
B22
Reserved
B10
AGC_C[1]
B21
Reserved
B09
AGC_C[0]
B20
Reserved
B08
AGC_D[1]
B19
Reserved
B07
AGC_D[0]
B18
Reserved
B06
AGC_DM
B17
AGC_A[3]
B05
RST_DET_D
B16
AGC_A[2]
B04
RST_LIN
B15
AGC_A[1]
B03
INJ
B14
AGC_A[0]
B02
INJM
B13
AGC_B[2]
B01
BW
B12
AGC_B[1]
B00
BWM
B11
AGC_B[0]
−
−
The LD interface requests from the SAF7741HV and their bit allocations are listed in
Table 6.
Table 6.
LD interface request bit allocation
Bit
Function
B06
Reserved
B05
Reserved
B04
Reserved
B03
DET_D[1]
B02
DET_D[0]
B01
INJ
B00
BW
In TEF6730 mode, the DL Interface is replaced by 2 IF-AGC bits.
7.1.3 Digital radio interface
For digital radio an I2S output is provided for the I and Q signals (see Figure 14). A GPIO
pin can be used as a blend input that makes it possible to switch from conventional FM
and AM processing to digital radio processing.
There are two possible ways to get digital radio data:
• Digital radio interface 1 output, from either PDC1 or PDC2
• Digital radio interface 2 output via the T1E I2S interface from PDC2
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20 of 83
SAF7741HV
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Dual IF car radio and audio DSP (N1F)
DR_WS
DR_BCK
DR_I_DAT
LSB
MSB
DR_Q_DAT
LSB
MSB
LSB
MSB
LSB
MSB
SAMPLE n−1
LSB
MSB
LSB
MSB
SAMPLE n
Fig 14. Digital radio I2S output format
7.1.4 RGP DAC
RGP digital-to-analog conversion is performed by a 10-bit DAC with a buffered output.
This is part of the radio subsystem and can be used for various functions linked to the
radio domain.
A double buffered interface is located between the DSP and the RGP DAC. The buffer is
2 × 8 words in length, which means that data with a maximum sample rate of 8 Fs (i.e.
325 kHz) can be transferred to the output when the DSP is running at 1 Fs (i.e.
40.625 kHz).
7.1.4.1
TEF6730 tuner compatibility
In TEF6730 tuner compatibility mode the general-purpose DAC can be used for
controlling the PIN diode in front of the tuner. In addition to its digital AGC function this
operates as second-level gain correction for the IFADC.
7.1.5 Radio Data System demodulator/decoder
7.1.5.1
General description
There are two Radio Data System (RDS) demodulation and decoder systems available on
the SAF7741HV. The description below applies to each of them.
The RDS function recovers the additional and inaudible RDS information transmitted by
FM radio broadcasting. The operational functions of the demodulator and the decoder are
in accordance with EBU specification EN50067.
The function processes the RDS signal frequency-multiplexed within the stereo MultiPleX
(MPX) signal to recover the information transmitted over the RDS data channel. This
processing consists of band-pass filtering, demodulation and RDS/ Radio Broadcast Data
System (RBDS) decoding. The RDS band-pass filter discards the audio content from the
input signal and reduces the bandwidth.
The RDS demodulator regenerates the raw RDS bitstream (bit rate = 1187.5 Hz) from the
modulated RDS signal. Connection to the RDS/RBDS decoder is by means of the DSP
flags (see Figure 15).
Under I2C control via bit rds_clkin an internal buffer can be used to read out the raw RDS
stream in bursts of 16 bits. With the I2C bit rds_clkout the RDS clock can be either
enabled or switched off.
SAF7741_7
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21 of 83
SAF7741HV
NXP Semiconductors
Dual IF car radio and audio DSP (N1F)
RDS_CLK<1,2>
RDS_DATA<1,2>
DECODER
BYPASS
MUX
RDS<1,2>_ CLKOUT
RDS<1,2>_ CLKIN
0
DSP
1
DAVN
OUTMUX
BSLP
STEREO
MPX
RDS
BANDPASS
FILTER
BSPA
RDS
DEMODU
LATOR
RDCL
DAC1
DAC0
0
1
RDS
BUF
MUX
RDDA
RDS/RBDS
DECODER
(RBDS+)
BIT
BUFFER
Fig 15. RDS/RBDS Functional block diagram
The RDS/RBDS decoder provides:
•
•
•
•
•
Block synchronization
Error detection
Error correction
Complex flywheel function
Programmable block data output
Newly processed RDS/RBDS block information is signaled to the main microcontroller as
‘new data available’ by use of the DAVN output. The block data itself and the
corresponding status information can be read out by means of an I2C bus request.
The RDS chain derives data information from the MPX signal independently of either the
analog or the digital audio streams. This allows RDS updates during playback from tape
or other sources.
7.1.5.2
RDS I/O modes
Apart from the control inputs and data outputs via the I2C inteface, the inputs and the
outputs related to the RDS function are listed in Table 7, Table 8 and Table 9
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Dual IF car radio and audio DSP (N1F)
Table 7.
Unbuffered raw (direct) RDS output mode (rds<1,2>_clkin = 0, rds<1,2>_clkout = 1
and DAVD mode: dac0 = 1, dac1 = 1)
Name
Description
RDS_CLK
Clock of the raw RDS bit stream. This is extracted from the bi-phase coded
baseband signal by the RDS demodulator. The clock period is 1.1875 kHz. See
Ref. 1 for more details.
RDS_DATA
Raw RDS bit stream, generated by the demodulator. This allows for external
receivers of the RDS data to clock the data on the RDS_CLK signal as well as on
its inverse. See Ref. 1 for more details.
Table 8.
Buffered raw RDS output mode (rds<1,2>_clkin = 1, rds<1,2>_clkout = 0 and
DAVD mode: dac0 = 1, dac1 = 1)
Name
Description
RDS_CLK
Burst clock, generated by the multi-processor. Bursts of 17 clock cycles are
expected. The average time between bursts = 13.5 ms.
RDS_DATA
Bursts of 16 raw RDS bits are put out under the control of the burst clock input.
This output is high after a data burst, and is pulled low when 16 new bits are
available and a new clock burst is awaited. The microprocessor has to monitor
this line at least every 13.4 ms.
Table 9.
DAVA, DAVB and DAVC modes (rds<1,2>_clkin = 0, rds<1,2>_clkout = 0)
Name
Description
davn
Data-available signal for synchronization of a data request between the main
controller and the decoder (for further information see Ref. 2).
Remark: Rds<1,2>_clkin = 1 and rds<1,2>_clkout = 1 is NOT an allowed mode.
Depending on the mode selected, the same output is used for RDS_DATA and DAVN (see
Figure 15).
7.1.5.3
RDS timing of clock and data signals in DAVD mode
The timing of the clock and data outputs is derived from the incoming data signal. Under
stable conditions the data will remain valid for 400 ms after the clock transition. The timing
of the data change is 100 ms before a positive clock change. This timing is well suited to
positive- and negative-triggered interrupts on a microprocessor.
It is possible that phase faults will occur during poor reception, in which case the duty
cycle of the clock and data signals will vary between a minimum of 0.5 and a maximum of
1.5 times the standard clock period. Faults in phase do not normally occur on a cyclical
basis. See also Section 14.1.
7.1.5.4
RDS bit buffer
The repetition frequency of the RDS data is 1187.5 Hz. This results in an interrupt on the
microprocessor every 842 ms, but the double 16-bit buffer allows this timing requirement
to be relaxed since the two 16-bit buffers are filled alternately. If a buffer has not been read
out by the time the other buffer is filled it will be overwritten and the old data will be lost.
While a 16-bit buffer is being filled the RDS bit buffer keeps the data line high.
When a 16-bit buffer is full the data line is pulled down. The microprocessor has to monitor
the data line at least every 13.5 ms. The data line remains low until the microprocessor
pulls the clock line low. This starts reading out of the buffer, and the first bit is put on the
data line. The RDS bit buffer puts a bit on the data line after every falling clock edge, and
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Dual IF car radio and audio DSP (N1F)
the data remains valid while the clock is high. After 16 falling and 16 rising edges the
whole buffer is read out and the bits are stored by the microprocessor. After a 17th falling
clock edge the data line is set high until the other 16-bit buffer is full. The microprocessor
stops communication by pulling the clock line high again. See Section 14.1.
7.1.5.5
RDS demodulator
The RDS demodulator is implemented in DSP software. See Ref. 1 for details of its
functionality.
Demodulator decoder interface: Communication between the RDS demodulator and
decoder is provided by Economic Parameterized Integrated Cores (EPICS) flags and
consists of four signals as shown in Figure 15.
Remark: Instead of the EPICS flags, the RDS decoder connection register can be used
for demodulator decoder communication. For further details see Ref. 3.
Table 10.
Signals provided by the demodulator
Name
Description
rdcl
Demodulator clock output.
Generated by the RDS/RBDS demodulator for every RDS/RBDS clock period
(1.1875 kHz). This pulse remains high for about half of an RDS/RBDS clock
period (∼420 μs). The rising edge of this signal is used as an input shift enable for
the decoder internal data buffer (RDS Data Output [RDDA] bit input).
It is assumed that the RDDA input will remain unchanged for at least one system
clock (10.4 MHz) after a rising RDCL edge.
rdda
Demodulator data output.
Represents the actual RDS/RBDS data bit. The RDDA is shifted into the decoder
module internal data buffer by detection of a rising edge on the RDCL input
signal.
bslp
Bit-Slip (BSLP) detected.
This is set to high for at least one RDS/RBDS clock period (1.1875 kHz), but only
when the demodulator detects a possible BSLP. The BSLP signal itself has to be
reset to low after one RDS/RBDS clock period.
Table 11.
Signals received by the demodulator
Name
Description
bspa
Bit-Slip Process Active (BSPA).
This is set to HIGH when the RDS decoder detects a BSLP: at all other times it is
LOW.
Remark: The current version of the SAF7741HV firmware does not use bslp/bspa
signalling. This is implemented in the hardware, and is therefore mentioned here for
information only.
7.1.6 8Fs I2S interface
The 8Fs I2S interface is used to transform the parallel data outputs of the TDSP1 (24 bits
wide) to serial data in I2S format, and then make that data available at the digital radio
interface 1 (see Figure 16). The TDSP1 has the capability to write data to the interface at
1Fs, 2Fs, 4Fs and 8Fs.
Depending on the flag values, the interface can send data in I2S format at 1Fs, 2Fs, 4Fs,
8Fs and 16Fs.
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Table 12 gives all possible combinations of speeds at which the interface receives and
sends data.
Table 12.
TDSP1/I2S interface receive and send data speeds
I2S Speed
TDSP1 Speed
1Fs
1Fs, 2Fs, 4Fs, 8Fs
2Fs
1Fs,2Fs, 4Fs, 8Fs, 16Fs
4Fs
1Fs,2Fs,4Fs, 8Fs,16Fs
8Fs
1Fs,2Fs,4Fs,8Fs, 16Fs
The size of the buffer is determined by the largest factor between the speeds of the
TDSP1 and the IIS, which is the case when the TDSP1 runs at either 1Fs and the IIS at
8Fs or when the TDSP1 runs at 2Fs and the IIS at 16Fs. In the first case the TDSP1 has
to be able to write two words of 24 bits - i.e. left data and right data for stereo samples at
1Fs speed - and the speed at which the read should be performed by the IIS interface is
8Fs. Therefore the required buffer size is 16 × 24 bits. Moreover, the buffer is required to
support double buffering; i.e. it can be written to and read from at the same time. This
makes the total size of the buffer 32 × 24 bits.
TDSP1
BUFFER
(32x24 bits)
IIS INTERFACE
T1E IIS INTERFAC
Fig 16. Top-level diagram of 8Fs I2S interface
7.1.7 Tuner I2S interface
The Tuner I2S interface provides a connection between the output multiplexer and
TDSP1E. There are two data converters, one converting parallel data (24 bits wide) to IIS
format and the second converting from I2S format to parallel. The two converters both run
at the TDSP1E sample rate. The format of the I2S data can be configured by setting the
applicable registers, and the internal I2S generator and I2S receiver both work as masters.
The result is that the signals ‘word select’ and ‘serial clock’ are always generated
internally.
7.1.8 Output multiplexer
The output multiplexer behind the tuner I2S interface maps four different serial data
streams to and from the pins:
•
•
•
•
Data going to or coming from the tuner I2S interface (I2S in/out)
Data T1 coming from the software radio and going to the SRC DSP (SDSP) (I2S out)
Data T2 coming from the software radio and going to the SDSP (I2S out)
Data coming from PDC2 (digital radio format out)
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Dual IF car radio and audio DSP (N1F)
7.1.9 Software radio user flags
le_addr1
le_read_inc1
INPUT
le_read_no_inc1
INTERFACE
data_out1
addr_in1
I
IFAD1
Q
le:0
le:1
le:2
d:1,d:2
LOGIC
MUX
le:33
le:34
le:35
le_addr2
le_read_inc2
I
INPUT
le_read_no_inc2
INTERFACE
data_out2
IFAD2
Q
EPICS7A
DIO
d:34,d:35
addr_in2
CRD le_Xin
phi2
FIR
phi2
le:3
le:4
le:5
le:7
le_Yin
le_Zin
le_cntr
data_in
Xlog_out
Xout
Yout
Zout
d:6
d:3
d:4
d:5
X_BUS
TO_EPICS
le:8
le:9
le:10
le_lin
le_Qin
le_cntr
data_in
Iout
Qout
d:8
d:9
EPICS INTERFACE_1
EPICS7A
EPICS7A
le_addr2
le_data_read_inc2
le_data_read_noinc2
le_data_write2
addr_data2
data_out2
le_addr1
le_data_read_inc1
le_data_read_noinc1
le_data_write1
addr_data1
data_out1
le:11
le:13
le:14
le:12
d:13,d:14
EPICS INTERFACE_2
le_addr2
le_addr1
le_data_read_inc2
le_data_read_inc1
le_data_read_noinc2
le_data_read_noinc1
le_data_write2
le_data_write1
addr_data2
addr_data1
data_out2
data_out1
le:15
le:17
le:18
le:16
d:31,d:32
le_addr
RGPDAC
RGPDAC
le_data_write
INTERFACE_1 addr_data_in
RGPDAC
RGPDAC
le_data_write
INTERFACE_2 addr_data_in
IIS_in
d:17,d:18
le:19
le:20
dio_en
zbus(21:16)
mode_bus
zbus(31:66)
RDS_CLOCK1
RDS_DATA1
RDS_BSLP1
RDS_BSLA1
F5
F6
F7
F8
le:30
le:31
le:32
RDS_CLOCK2
F9
le_addr
le:23
le:24
imode
iflag
xbus_from_epics_sfalg
le_addr
le:25
le:26
le_addr
le:21
le:22
le_addr
le_data_read_inc
IIS_in
le_data_read_no_inc
INTERFACE
addr_in
RDS_DATA2
RDS_BSLP2
RDS_BSLA2
data_out
IIS_out1
IIS_out
le_data_write
INTERFACE_1 addr_data_in
IIS_out2
IS_out
le_data_write
INTERFACE_2 addr_data_in
lflag
pflag
le_addr
IIS_out3
buf_oe
ymu_bus
IS_out
le_data_write
INTERFACE_3 addr_data_in
lflag
pflag
le:28
le:29
EPICS
FLAG
GEN
F10
F11
F12
IM
I
F0
iflag
sfalg
data
lost
im reset_i
imode d:27
phi2
Fig 17. Software radio TDSP1 DIO block diagram (superset of all TDSP DIOs)
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The user flags of the TDSPs can be programmed for various functions described below.
Every TDSP has 13 I/O flags available. Table 13 shows all the possibilities for each user
flag.
Table 13.
User Flag
TDSP user flags
Chip Pin Name
Mode[1]
Function
I/O
Stretch
F0
−
SFLAG input from EPICS flag generator IN
OFF
F1
TDSP_IOF1
User-defined in or out
IN/OUT
ON/OFF
F2
TDSP_IOF2
User-defined in or out
IN/OUT
ON/OFF
F3
TDSP_IOF3
User-defined in or out
IN/OUT
ON/OFF
F4
TDSP_IOF4
User-defined in or out
IN/OUT
ON/OFF
F5
TDSP_IOF5
User-defined in or out/clock output to
RDS decoder1
IN/OUT
ON/OFF
F6
TDSP_IOF6
User-defined in or out/data output to
RDS decoder1
IN/OUT
ON/OFF
F7
TDSP_IOF7
User-defined in or out/BSLP output to
RDS decoder1
IN/OUT
ON/OFF
F8
TDSP_IOF8
User-defined in or out/bspa input from
RDS decoder1
IN/OUT
ON/OFF
F9
TDSP_IOF9
User-defined in or out/clock output to
RDS decoder2
IN/OUT
ON/OFF
F10
TDSP_IOF10
User-defined in or out/data output to
RDS decoder2
IN/OUT
ON/OFF
F11
−
ADSP TDSP1E interface/RDS decoder
IN
ON/OFF
F12
−
IN
Out flag to the WDOG value
registers/ADSP TDSP1E interface/RDS
decoder
ON/OFF
[1]
All I2C-controllable
There are 10 general purpose I/O pins available for the software radio. These have to be
shared between the available TDSPs as shown in Figure 18. In this diagram only
TDSP_IOF1 is depicted since all the other flags are connected the same way.
In the description that follows the value of ‘n’ can be 1 to 10.
1. Pin TDSP_IOFn is wired directly to the input flag ‘n’ of each TDSP.
2. The output flags ‘n’ of all the TDSPs are OR-ed together and the resulting signal is
wired to TDSP_IOFn.
3. All the flags on all the separate TDSPs can be set to input or output in the I2C
registers. The pad of TDSP_IOFn is input when all TDSP flags ‘n’ are set to input:
otherwise it is used as an output.
4. All the flags on all separate TDSPs can be set to stretch mode or non-stretch mode in
the I2C registers.
There are exceptions to the above description. On the chip there are two RDS decoders
that can be connected to either of the TDSPs, using predefined pins on the DSP when
connected. The corresponding TDSP pins connected to the RDS decoder are then fixed
as RDS pins and are no longer available as user-defined. The stretch mode of the
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corresponding pins is switched off. Which RDS decoder is connected to which TDSP is
controlled in the I2C registers. Table 13 shows which flags are used for RDS when
connected.
TDSP1
RDS1
TDSP1E
TDSP2
RDS1
RDS2
F1 F2 F3 F4 F5 F6 F7 F8 F9 F10F11F12
F1_ mode (tdsp1)
RDS2
F1 F2 F3 F4 F5 F6 F7 F8 F9 F10F11F12
F1_ mode (tdsp2)
&
&
RDS1
RDS2
F1 F2 F3 F4 F5 F6 F7 F8 F9 F10F11F12
F1_ mode (tdsp1e)
&
F1_ mode (tdsp1)
F1_ mode (tdsp2)
F1_ mode (tdsp1e)
(Outpu t is ena b
led when one ou t of three mod es is ou tpu t)
TDSP_IO F1
Remark: F11 and F12 are not available outside of the chip.
Fig 18. Overview of RDS user-defined flag configuration
7.1.9.1
EPICS flag generator
The EPICS flag generator generates two flags: IFLAG and the Sync Flag (SFLAG). IFLAG
is connected to the ‘I’ input flag of the EPICS and SFLAG is connected to the user flag 0.
SFLAG indicates that the EPICS should use page0 of the EPICS interface memories to
avoid read and/or write errors and conflicts.
The normal duration of IFLAG is four EPICS clock periods. The SFLAG is set until the
next IFLAG is generated.
The EPICS can stretch (IMODE) IFLAG via the IM input.
7.1.9.2
Flag overview
When IFLAG is in stretch mode (IM is high) the flag is set at every rising edge of LFLAG.
IFLAG can be reset only with the RESET_I input connected to a DIO address. When this
address is read by the EPICS, RESET_I is pulsed. SFLAG is not stretched. If IFLAG is not
cleared before the next LFLAG the LOST_DATA flag is set.
When IFLAG is not in stretch mode (IM is low) then an IFLAG is generated at every rising
edge of the LFLAG . If at this point PFLAG is high, then SFLAG is set until the next rising
edge of LFLAG (see Figure 19). LFLAG and PFLAG are generated in the software radio
flag generator.
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Dual IF car radio and audio DSP (N1F)
- EPICS7A LFLAG @ 1fs
- PFLAG @ 0.5fs
- NO STRETCH MODE
LFLAG
PFLAG
IM
RESET_I
IFLAG
SFLAG
- EPICS7A LFLAG @ 2fs
- PFLAG @ 0.5fs
- NO STRETCH MODE
LFLAG
PFLAG
IM
RESET_I
IFLAG
SFLAG
- EPICS7A LFLAG @ 1fs
- PFLAG @ 0.5fs
- STRETCH MODE
LFLAG
PFLAG
RESET_I
IFLAG
SFLAG
LOST_DATA_FLAG
‘BORROW’ SOME TIME
FROM NEXT IFLAG-PERIOD
Fig 19. Overview of the user defined flag configuration
7.2 Audio subsystem
The audio subsystem (see Figure 2) consists mainly of four sequential sections:
•
•
•
•
Input section (analog and digital)
SRC section
Audio processing section
Audio output section
7.2.1 Input section
The audio input section is split into an analog and a digital input.
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7.2.1.1
Analog audio input paths
The analog input section consists of an analog source selector and five ADCs. The
outputs of the ADCs are connected to the ADSP. The audio sample rate of these inputs
can be a maximum of 55 kHz. When the ADSP runs at a higher rate the inputs need to be
routed via a software up-sampler.
7.2.2 Signal flow of the analog audio input
AIN0_L
AIN0_R
AIN1_L
AIN1_R
AIN2_L
AIN2_R
AIN3
AIN4
SWITCH BLOCK
ansel1
dif_sw0
+
gndsel1
-
Ri
Ri
- Ri
AD1
+
ansel2
Ri
+
gndsel2
-
dif_sw1
ADF
1»16
ADF
2»8
I2S
ADF
1»16
ADF
2»8
I2S
ADF
1»16
ADF
2»8
I2S
Ri
AD2
-
Ri
+
ansel3
Ri
+
gndsel3
-
dif_sw2
Ri
AD3
-
Ri
+
ansel4
Ri
+
gndsel4
dif_sw3
-
Ri
AD4
-
Ri
+
ansel5
Ri dif_sw4
+
gndsel5
-
Ri
AD5
-
Ri
+
AIN0_L_REF
AIN0_R_REF
AIN2_L_REF
AIN2_R_REF
AIN3_REF
AIN4_REF
R
VADCP
VADCN
+
VREFAD
-
R
Ri
Fig 20. Analog audio input switching block diagram
The input switching for the five possible analog channel setups is very flexible. Using the
switches gndsel0 to gndsel4 (see ) and ansel0 to ansel4 all combinations can be made
either for normal inputs or for high common-mode inputs with a ground connection (see
Figure 20)
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Dual IF car radio and audio DSP (N1F)
In principle, any signal input can be connected to any ADC. However, it is possible to
make the stereo signals use the even-numbered ADCs (ADC0, ADC 2 and ADC4) for the
left channels and the odd-numbered ones (ADC 1 and ADC 3) for the right channels. The
only conditions are that:
• When the input signals do not have a ground pin the minus input of the second
Op-amp in the signal chain must be connected by means of the gndsel switches to the
VREFAD line.
• When there is a high common-mode input with ground input pin the associated gndsel
switch must be connected to this pin.
• Some connections to the switching matrix are 'reserved'. These must not be used.
Table 14 and Table 15 show the possible connections.
Table 14.
Selection of analog signal switches
Position
ANSEL1 to ANSEL5
000
AIN0_L
001
AIN0_R
010
AIN2_L
011
AIN2_R
100
AIN3
101
AIN4
110
AIN1_L
111
AIN1_R
Table 15.
Selection of the analog ground switches
Position
ANSEL1 to ANSEL5
000
AIN0_L_REF
001
AIN0_R_REF
010
AIN2_L_REF
011
AIN2_R_REF
100
AIN3_REF
101
AIN4_REF
110
VREFAD
111
Reserved
7.2.3 Realization of the common mode inputs
A high Common-Mode Rejection Ratio (CMRR) can be created for all the analog inputs by
use of the ground pins. To create a signal input, connect the ground pin that is to be used
to the second Op-amp in the signal path by using the gndsel switch. This ensures that the
two signal lines that go to the ADC will contain the common-mode signal. The ADC itself
will suppress the signal very effectively, so in this way good common-mode signal
suppression will be achieved.
An example of a high common-mode stereo input with two ground shielding lines is shown
in Figure 21.
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Dual IF car radio and audio DSP (N1F)
CD PLAYER
LEFT
220nF
POSITIVE
CD PLAYER
LEFT
47μF
NEGATIVE
CD PLAYER
RIGHT
220nF
POSITIVE
CD PLAYER 47μF
RIGHT
NEGATIVE
anselX
8.2 kΩ
AIN0L
1nF
10 kΩ
Ri
gndselX
AIN0L
_REF
dif_swX
Ri
ADX
Ri
anselY
8.2 kΩ
AIN0R
1nF
10 kΩ
1M
Ri
gndselY
AIN0R
_REF
dif_swY
Ri
ADY
Ri
1M
VREFAD
22uF
Fig 21. High common-mode stereo input with two ground lines
In this example input voltage reduction is accomplished by the external 8.2 kΩ to 10 kΩ
resistor divider. The rather low-value resistor divider is necessary because in this case the
parasitic capacitance on pins AIN0_L and AIN0_R will reduce the common-mode signal
on them. The CMRR can be guaranteed when the source and cable impedance do not
exceed the specified value as stated in the conditions column of Table 35.This leads to a
reduction of the CMRR when the source impedance is too high. Half of the supply voltage
is provided as reference by connecting the negative inputs of the second operational
amplifier to VREFAD by means of the gnd_sel switches and the external 1.0 MΩ resistor.
The 1.0 nF capacitors are used for anti-aliasing.
An example of a high common-mode input with only one ground-shielding line is shown in
Figure 22.
CD PLAYER
LEFT
POSITIVE
220nF
8.2 kΩ
anselX
Ri
10 kΩ
CD PLAYER
CABLE
GROUND
AIN0L
1nF
47uF
AIN0L
_REF
gndselX
dif_swX
Ri
ADX
Ri
1nF
10 kΩ
CD PLAYER
RIGHT
POSITIVE
220nF
AIN0R
8.2 kΩ
anselY
Ri
AIN0R
_REF
gndselY
dif_swY
Ri
ADY
Ri
1MΩ
VREFAD
22uF
Fig 22. High common-mode stereo input with one ground line
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Dual IF car radio and audio DSP (N1F)
A full-stereo differential input of a CD changer is shown in Figure 23. The switches dif_sw
are shown open, and only when signals on the inputs (marked POS and NEG) are
different will analog-to-digital conversion take place. Common-mode signals on the inputs
will also appear as common-mode signals on the ADC inputs and will not be converted to
the digital data stream.
CD PLAYER 220nF 8.2 kΩ
LEFT
POSITIVE
10 kΩ
AIN0L
anselX
Ri
gndselX
10 kΩ
1nF
Ri
ADX
Ri
AIN0L
_REF
CD PLAYER 220nF 8.2 kΩ
LEFT
NEGATIVE
CD PLAYER 220nF 8.2 kΩ
RIGHT
POSITIVE
10 kΩ
dif_swX
1nF
AIN0R
anselY
Ri
dif_swY
Ri
1nF
ADY
gndselY
Ri
10 kΩ
CD PLAYER 220nF
RIGHT
NEGATIVE
1nF
AIN0R
_REF
8k2
VREFAD
22uF
Fig 23. Differential stereo input
The differential-mode application of a single-ended input is shown in Figure 24. In this
case the input voltage is reduced symmetrically with two 82 kΩ resistors and one100 kΩ
resistor. This neutralizes the effect of parasitic capacitance on the AIN3 input and the
AIN3_GND input to permit a relative high-ohmic resistor divider to be used. In this
example common-mode signals which have not been reduced in value are applied to the
ADC. The ADC itself has a very good CMRR, so this input also has a high CMRR.
PHONE
POSITIVE
220nF
8.2 kΩ
anselX
Ri
10 kΩ
PHONE
NEGATIVE
AIN3
220nF
1nF
gndselX
8.2 kΩ
dif_swX
Ri
ADX
Ri
AIN3_REF
1M
VREFAD
22uF
Fig 24. Differential mono input
In Figure 25 a single-ended input is shown. The reference here is VREFAD which is
connected internally, so no common-mode rejection can be expected.
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SAF7741HV
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Dual IF car radio and audio DSP (N1F)
220nF
8.2 kΩ
AIN3
PHONE
anselX
Ri
1nF
10 kΩ
PHONE
NEGATIVE
gndselX
dif_swX
Ri
ADX
Ri
AIN3_REF
VREFAD
22uF
Fig 25. Single-ended input
7.2.4 Audio ADC decimator paths (DAD)
7.2.4.1
Functional description
Decimation of the audio ADC signals is completed in a block called DAD. This block can
handle the signals from two ADCs, so a stereo signal can be processed.
1 Bit CODE
FILTER
CEAD
INTERFACE
CEAD
BLOCK
CONTROL
Enable DC FILTER
Fig 26. DAD block diagram
The input signal has a sample frequency of 128 × fs and comes from a third-order ΣΔ
ADC. The first step in the decimation process is done by the 1-bit code Cascaded
Integrator Comb (CIC) filter and Audio Decimation Filter 1 (ADF1) filter. See Figure 26.
The CIC filter decimates the input sample rate by a factor of 16 and thus results in a
sample rate of 8 × fs.
After the 1-bit code filter, sample reworking is necessary to enter the CEAD block and the
ADF2. The CEAD block further decimates the audio samples by 8, giving a sample rate of
1 × fs. The overall gain in the pass band of the decimation filter (including the CIC filter
and the CEAD block) becomes 4.85 dB. A nominal input level of −8.45 dB comes from the
ADC and results in a −3.6 dB level after decimation.
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SAF7741HV
NXP Semiconductors
Dual IF car radio and audio DSP (N1F)
The DC filter in the CEAD block is controlled by an I2C bit that can be found in Ref. 3.
Power-on reset circuitry is not implemented, which means that after power-up all filters will
go through a brief transient phase before they reach their steady-state behavior.
7.3 Audio Digital-to-Analog (ADAC) conversion
The ADAC module consists of a DAC, an interpolation filter and a noise shaper for the
audio. Both the analog and the digital functions are described here.
The digital part consists of an interpolation filter which increases the sample rate from 1 fs
to 128 fs and a third-order noise shaper that runs at 128 fs.
The analog part consists of six single-ended DAC modules for the left, the right, the centre
and the sub-woofer channels.
STEREO INTERPOLATOR
noise shaper
dern
4 bit sdac
128fs
DAC_FL
1fs
noise shaper
dern
4 bit sdac
128fs
DAC_FR
noise shaper
dern
4 bit sdac
128fs
DAC_RL
1fs
noise shaper
dern
4 bit sdac
128fs
DAC_RR
STEREO INTERPOLATOR
noise shaper
dern
4 bit sdac
128fs
DAC_CENTER
1fs
noise shaper
128fs
dern
4 bit sdac
DAC_SUBW
Fig 27. Audio DAC block diagram
7.3.1 Functional description
The audio DAC comprises these functions:
• Digital up-sampling filter
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SAF7741HV
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Dual IF car radio and audio DSP (N1F)
• 3rd order noise shaper
• DAC including Compensations and the DEM algorithm
7.3.2 Digital filters
The interpolation from 1 fs to 128 fs is done in four stages:
• The first stage is a 99 tap Half-Band (HB) filter that increases the sample rate from 1
fs to 2 fs. It has a steep transition band to correct for the missing inherent filter
function of the DAC used
• The second stage is a 31-tap FIR filter that increases the data rate from 2 fs to 8 fs. It
compensates for the roll-off caused by the Sample and Hold (SH) function prior to the
noise shaper
• The third stage is a simple hardware Linear Interpolator (LIN) function that increases
the sample rate from 8 fs to 16 fs. It removes the 8 fs component in the output
spectrum
• The fourth and last stage is a SH function increasing the sample rate from 16 fs to
128 fs.
The overall transfer characteristics can be found in Table 16.
Table 16.
Digital filter characteristics
Characteristics
Condition
Value (dB)
Passband ripple
0 Fs to 0.4535 Fs
+0.02
Stop band
>0.5465 Fs
−72
Dynamic range
0 Fs to 0.4535 Fs
>143
7.3.3 Noise shaper
The 3rd-order noise shaper operates at 128 fs, shifting the in-band quantization noise to
frequencies well above the audio band. This noise-shaping technique enables high
signal-to-noise ratios to be achieved at low frequencies. The noise-shaper output is
converted into an analog signal using a 4-bit Switched Resistor Digital-to-Analog
Converter (SDAC).
7.3.4 DAC (4-bit SDAC)
The 4-bit DAC is based on a switched resistor architecture which forms a controlled
voltage divider between the positive (VDACP) and the negative (VDACN) reference
supplies. The 4-bit input data from the noise shaper is decoded first to a 13-level
thermometer code to control the 15 taps of the converter. Data-Weighted Averaging
(DWA) is added to the decoding to guarantee that there is no correlation between the
input signal and the resistors used for that input signal.
After decoding and DWA the buffers connect the resistors to either the VDACP or the
VDACN pin so that the reference voltage will be divided depending on the input signal.
The result is an analog output voltage with a rail-to-rail maximum output swing. The output
impedance of this DAC is approximately 1.0 kΩ. By applying an external capacitor of 3.3
nF to the output pin a 1st order low-pass post-filter is introduced with a −3.0 dB roll-off at
48 kHz (dimensioned for fs = 44.1 kHz). This will reduce the 3rd-order noise-shaped
output spectrum of the DAC to a spectrum that increases with 2nd order.
Remark: The value of this capacitor depends on the actual sample frequency used.
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Dual IF car radio and audio DSP (N1F)
7.4 Digital audio I/O
Two groups of digital inputs to the audio subsystem can be distinguished:
• Inputs (I2S, SPDIF, I2S from radio subsystem) that run at their own sample frequency
• Inputs (HOST I2S) that run at a sample rate equal to that of the ADSP
At the output side only the HOST I2S outputs are available, also running at a sample rate
equal to that of the ADSP.
There are provisions to enable I2S input 4 as a digital SPDIF input and to configure I2S
input 1 and the SPDIF inputs as a six-channel DVD input, where the SPDIF inputs carry
the serial data for the four additional channels.
There is provision to enable I2S input 4 as a digital SPDIF input, and to configure I2S input
1 and the SPDIF inputs as a six-channel DVD input where the SPDIF inputs carry the
serial data for the four additional channels.
The I2S inputs (both primary and from the radio subsystem) and the SPDIF inputs are
sample-rate converted by the SRC implemented on an EPICS7A core. The SDSP
software supports three different modes:
• Stereo mode (maximum of five stereo SRCs)
• Multi-channel mode 1 (maximum of one six-channel SRC plus two stereo SRCs)
• Multi-channel mode 2 (one six-channel SRC)
The actual number of SRCs that can be active depends on the DSP clock frequency and
the required sample rate. An additional stereo SRC is possible on the platform device in
the ADSP and will depend on the code present in this DSP.
7.4.1 I2S inputs
An I2S digital interface bus can be used for communication with external digital sources.
This is a serial three-line bus that has:
• One line for data
• One line for the clock
• One line for word-select
For external digital sources the SAF7741HV can act as a slave so the external source is
master and supplies the clock.
Remark: The digital audio input is capable of handling multiple formats, so for simplicity
the serial digital audio inputs and outputs are referred to as I2S. However, this does not
mean that the format always conforms exactly to the published Philips I2S standard (see
Ref. 5).
The I2S input is capable of handling Philips I2S- and LSB-justified formats of 16-bit, 18-bit,
20-bit and 24-bit word sizes. See Figure 28.
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Dual IF car radio and audio DSP (N1F)
LEFT
WS
1
2
3
RIGHT
>=8 1
2
3
>=8
BCK
DATA
MSB
MSB
2
INPUT FORMAT I S
WS
MSB
RIGHT
LEFT
16 15
2
16 15
1
2
1
BCK
DATA
MSB
LSB
MSB
LSB
LSB JUSTIFIED FORMAT 16 BITS
WS
LEFT
RIGHT
18 17 16 15
18 17 16 15
BCK
DATA
MSB
WS
LSB
LSB JUSTIFIED FORMAT 18 BITS
LEFT
20 19 18 17 16 15
2
MSB
LSB
RIGHT
20 19 18 17 16 15
1
2
1
BCK
DATA
MSB
LSB
MSB
LSB
LSB JUSTIFIED FORMAT 20 BITS
WS
LEFT
24 23 22 21 20 19 18 17 16 15
2
1
RIGHT
24 23 22 21 20 19 18 17 16 15
2
1
BCK
DATA
MSB
LSB
MSB
LSB
LSB JUSTIFIED FORMAT 24 BITS
Fig 28. IIS formats
See Ref. 3 for the bits that must be programmed and for details of how to select the
required I2S format.
The number of BCK pulses may vary in the application. When the applied word length
exceeds 24 bits the LSBs are not used. The input circuitry cannot handle an unlimited
number of BCK pulses per WS period, so the maximum allowable number of BCKs per
period is 256.
It is not necessary for the WS to have a 50% duty cycle in Philips I2S standard format.
This means that the number of BCKs during high or low may be different. However this is
not allowed for LSB-justified formats.
External IIS sources with a wide sample-rate range are supported: from 8 kHz up to 192
kHz. This does not mean, however, that any sample rate can be applied to the inputs and
be handled simultaneously by the sample-rate conversion DSP. The audio bandwidth after
sample-rate conversion is of course always limited to half of the master sample rate Fs.
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Dual IF car radio and audio DSP (N1F)
7.4.1.1
General description of the SPDIF inputs
The design fulfils the requirements of the IEC60958 Digital Audio Interface specification
(see Ref. 6) except for the input voltage, which is required to have a digital level. The
interface is compliant with the electrical limitations of the pins (see Table 23).
There are two SPDIF independent input pins with their own SPDIF receivers. This means
that two SPDIF signals can be processed in parallel.
The SPDIF receiver is not fitted with an analog PLL. The incoming SPDIF stream is
sampled at a high frequency in the digital domain. From the SPDIF signal a 3-wire (I2Slike) serial bus is made consisting of word-select, data and bitclock lines. The Fs
frequency depends solely on the accuracy of the SPDIF signal input.
This design does not handle the user data bits of the SPDIF stream. The audio field of up
to 24 bits is available at its output. The audio bits are always decoded regardless of any
status bits; e.g. copy-protected, professional mode or data mode. However, a subset of
the channel status bits is decoded and made available to the ADSP and the SDSP. In
addition, the 'validity' bit is available. This means that the ADSP can prevent non-PCM
audio or data being processed as audio. See the relevant tables in Ref. 3 for the exact
channel status bits supported. The supported bits are extracted from the left channel only.
SPDIF format: The SPDIF format was conceived to transport 2-channel PCM audio for
distances of up to several hundred metres over a 3-wire balanced line. Alternatively the
signal could be carried for shorter distances over a 2-wire pair.
The SPDIF format can be partitioned into two main layers:
• The abstract model of frames and blocks
• The channel modulation
SPDIF channel modulation: The digital signal is coded using Bi-phase Mark Coding
(BMC), which is a type of phase modulation. In this scheme a logical 1 in the data
corresponds to two zero crossings in the coded signal and a logical 0 to one zero
crossing.
Clock
Data
BMC
Fig 29. Bi-phase mark coding
Since a logic 1 implies two transitions in the BMC signal, a clock at twice the bit rate
assumes the use of all rising signal edges.
SPDIF sample rates: The IEC60958 specification allows the use of sample rates from
22.05 kHz to 192 kHz. The SAF7741HV is designed to support a very wide range of
sample rates, but there are restrictions with respect to the processing power of the SDSP
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SAF7741HV
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Dual IF car radio and audio DSP (N1F)
and the actual contained bandwidth of the audio information. Any product derivative with a
fixed SDSP ROM code will have clear restrictions. The code for the SAF7741HV platform
can be chosen for different implementations.
Table 17.
Examples of the most common SPDIF sample frequencies
Sample frequency (kHz)
Data rate (Mbits)
Channel rate (Mbits)
44.1
2.8224
5.6448
48.0
3.0720
6.1440
32.0
2.0480
4.0960
7.5 Host I2S I/O
A HOST I2S interface is available that features five inputs and four outputs. Configuration
of the HOST I2S interface can be done via the I2C registers . Details can be found in
Ref. 3.
7.6 ADSP
The ADSP processes audio features on five stereo audio channels coming from the
SDSP, two stereo channels and one mono channel from the ADCs and eight stereo HOST
inputs. In addition to this the ADSP can be used to sample-rate convert one additional
stereo input to the same reference sample rate as all the other inputs. On the output side
there are eight to 10 HOST outputs. The ADSP will control the switches in SwitchBox2 of
the SDSP and SwitchBox1 in front of the ADC.
7.6.1 ADSP user flags
Eight user flags can be used to control several settings in the ADSP. The stretch mode as
well as I/O direction of those flags is user-definable. Furthermore, there are two flags that
are used as sample indicators for the SRC software and two flags that support an
interface towards the TDSP1E in the radio subsystem (fixed input flags). Finally there is
one flag that is connected to the WDOG status register. When this is used it must be
configured as an output. The table below shows the function of each flag.
Table 18.
ADSP user flags
Pin name
Flag
I/O
Stretch
−
F0
Internal divided sample rate flag (pflag)
IN
OFF
−
F1
Internal source sample rate flag
IN
ON
−
F2
ADSP TDSP1E interface
IN
OFF
−
F3
ADSP TDSP1E interface
IN
OFF
ADSP_IOF4
F4
User-defined input or output
IN/OUT
ON/OFF
ADSP_IOF5
F5
User-defined input or output
IN/OUT
ON/OFF
ADSP_IOF6
F6
User-defined input or output
IN/OUT
ON/OFF
ADSP_IOF7
F7
User-defined input or output
IN/OUT
ON/OFF
ADSP_IOF8
F8
User-defined input or output
IN/OUT
ON/OFF
ADSP_IOF9
F9
User-defined input or output
IN/OUT
ON/OFF
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Dual IF car radio and audio DSP (N1F)
Table 18.
Pin name
ADSP user flags
Flag
Mode [1]
Function
I/O
Stretch
ADSP_IOF10 F10
User-defined input or output
IN/OUT
ON/OFF
ADSP_IOF11 F11
User-defined input or output
IN/OUT
ON/OFF
−
Output flag to the WDOG status register
IN/OUT
ON/OFF
[1]
F12
All I2C controllable
In the description that follows, ‘n’ can be any value from 6 to11. See Figure 30 for details.
• The output flags ‘n’ of all the ADSPs or SDSPs are made to be OR-ed together, and
the resulting signal is wired to ADSP_IOFn
• All flags on all the individual ADSPs and SDSPs can be set to either ‘input’ or ‘output’
in the I2C registers. The pad of ADSP_IOFn is an input when the two ADSP/SDSP
flags ‘n’ are set to input: otherwise it is used as an output.
• All flags on the two separate ADSPs or SDSPs can be set to either stretch mode or
non-stretch mode in the I2C registers
• User flags 4 and 5 of the ADSP are always connected to pads ADSP_IOF4 and
ADSP_IOF5
• User flag ADSP_IOF11 is shared with the output wd_flag of the Watchdog (WDOG)
module. This is configured by the IIC control register WD_CTRL ($000090). Details
can be found in Ref. 3.
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41 of 83
SAF7741HV
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Dual IF car radio and audio DSP (N1F)
ADSP
F4 F5 F6
SDSP
F7 F8 F9 F10 F11
F6
F6 MODE
(ADSP)
F7 F8
F9 F10 F11
F6 MODE
(SDSP)
&
&
+
+
OUTPUT IS ENABLED WHEN
AT LEAST ONE F6 FLAGS IS SET TO OUTPUT
ADSP IOF4
ADSP IOF5
ADSP IOF6
xxxxx
(1) User flag 4 and user flag 5 of the ADSP are connected always to pad ADSP_IOF4 and
ADSP_IOF5 (respectively)
Fig 30. Schematic overview of the ADSP user-defined flag configuration
7.6.2 ADSP digital I/O inteface
The digital I/O interface (DIO) of the ADSP is realized via the XBUS. For the inputs a
LOGIC_MUX is placed in front of the XBUS of the DSP. Mux selection is decoded from the
instruction bus. For the SRC input, extra inputs are provided for the timestamp registers of
the reference sample rate and the to-be-converted input. For the other inputs with the
same sample rate but different arrival times, some extra buffering and scheduling of the
sample valid pulse is calculated by an ASFTIM block. For each output a buffer is
connected to the XBUS from the DSP and its latch-enable signal is decoded from the
instruction bus as well. For an overview see Figure 31.
For further information on DIO mapping of the registers, see Ref. 4.
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SAF7741HV
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Dual IF car radio and audio DSP (N1F)
NWSM_FS_REF (SDSP)
ASF
ChanAL
ChanAR
ASF
ChanBL
ChanBR
ASF
ChanCL
ChanCR
ASF
ChanDL
ChanDR
ASF
ChanEL
ChanER
ASF
FROM
SDSP
IIS1
IIS2
IIS3
IIS4
IIS_SPDIF1
IIS_SPDIF2
IIS_T1
IIS_T2
24
24
le
24
24
le
24
le
24
le
24
d:0
d:1
d:2
d:3
24
d:4
d:5
24
d:6
d:7
24
d:8
d:9
le
I_FLAG
stretch
IMODE
reset
P_FLAG
d:0
ASFTIM
ASF
NWSM_SRC
BCK
WS
I F0
F1
host_out1_disable
ADSP/
EPICS7A
CLK_DSP
FORMAT
IIS_IN1(2:0)
IIS_IN2(2:0)
IIS_IN3(2:0)
IIS_IN4(2:0)
SRC_IN_
SEL(2:0)
L
24
R
IIS_RECEIVER NWSM
SRC
d:10
d:11
LOGIC
MUX
le
ASF
le
L
R
3
HOST_IN1
HOST_IN2
HOST_IN3
HOST_IN4
HOST_IN5
IIS_RECEIVER
L
R
IIS_RECEIVER
L
R
IIS_RECEIVER
L
R
3
L
R
3
3
L
R
IIS_RECEIVER
L
R
3
L
R
3
d:22
d:23
latch
le
le
d:24
d:25
latch
le
le
2
FORMAT
DECODER
counter
NWSM_SRC
3
latch
le
le
2
TSR1
24
TSR2
24
24
le
NWSM_
AD12
24
le
NWSM_
AD34
24
le
NWSM_
AD56
24
le
NWSM_
HOST
24
le
24
24
d:18
d:19
24
d:20
d:21
24
d:22
d:23
24
d:24
d:25
HOST_IO
FORMAT(2:0)
d:32
d:33
latch
le
le
d:34
d:35
latch
le
le
24
d:26
d:27
24
d:28
d:29
le
24
2
d:36
d:37
2
latch
le
le
IntPol
IntPol
IntPol
le
DA1
DAC_FL
DA2
DAC_FR
DA3
DAC_RL
DA4
DAC_RR
DA5
DAC_CENTER
DA6
DAC_SUBW
CLK_DSP
ASF
le
24
HOST_OUT3
host_out4_disable
latch
le
le
2
d:16
24 d:17
host_out3_disable
d:28
d:29
2
d:14
24 d:15
HOST_OUT2
IIS
GEN
HOST_OUT4
2
d:13
host_out2_disable
latch
le
le
X_IN X_OUT
d:12
HOST_OUT1
le bck ws
d:26
d::27
TIME STAMP COURIER
3
d:20
d:21
2
3
NWSM_AD12
NWSM_AD34
NWSM_AD5
NWSM_HOST
ASF
newsam
le
IR_BUS
LOGIC
DECODER
HOST_IO_MODE
HOST_IO_ENA
ASF
CLK_DSP
WS_HOST
WS
1
WS_REF
BCK_HOST
BCK
1
HOST_IO_FORMAT(2:0)
BCK_REF(64 FS)
HOST_IO_MODE
Fig 31. ADSP digital I/O interface diagram
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SAF7741HV
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Dual IF car radio and audio DSP (N1F)
The input format of HOST_IN, HOST_OUT and SRC INPUT can be selected via an I2C
register. The source that will be sample-rate converted is also selected by I2C register bits
(see Ref. 3). Control of these I2C bits will be maintained by the ADSP and the
MicroProcessor Interface (MPI).
Extra DIO inputs are provided for registers that contain new sample time-stamps for the
stereo input and one extra register for the reference sample rate. Combined with the new
sample flags from the input and the reference flags, these time-stamps allow the DSP
program to convert the sample rate to the reference on the output.
7.6.3 ADSP-TDSP1E interface
The ADSP TDSP1E communication interface provides two general-purpose
communication channels between the ADSP and the TDSP1E, one for each direction.
Each channel has two registers of 24 bits each:
• For the channel from the ADSP to the TDSP1E, the ADSP writes the data to the
registers and the TDSP1E then reads this data
• For the channel from the TDSP1E to the ADSP, the TDSP1E writes the data to the
registers and the ADSP then reads this data
A full handshake mechanism is provided In addition to the communication channel, but
the communication channels can be used either with or without handshaking.
When the communication between the two DSPs requires a handshake, the software can
test the input flags. The flags are either cleared or set by hardware under the condition of
either reading from the second register or writing to the second register. See Figure 32 for
a block diagram of the communication interface.
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SAF7741HV
NXP Semiconductors
Dual IF car radio and audio DSP (N1F)
R1 A2T
COMMUNICATION INTERFACE
TDSP DATA
R2 A2T
AUDIO
TDSP DATA
SW RADIO
ADSP WRITE REG1
ADSP DATA
ADSP WRITE REG2
NOTIFICATION
LOGIC
ADSP BUFFER EMPTY
TDSP READ REG2
TDSP BUFFER FULL
F2 IN
F11 IN
TDSP1E
ADSP DATA
R1 T2A
ADSP
R2 T2A
TDSP WRITE REG1
TDSP DATA
NOTIFICATION
LOGIC
TDPS WRITE REG2
ADSP DATA
ADSP READ REG2
F3 IN
ADSP BUFFER FULL
TDSP BUFFER EMPTY
F12 IN
xxxxx
Fig 32. ADSP TDSP communication channel
7.6.3.1
Communication protocol example
Figure 33 is an example of the handshake protocol for one direction. The signal
adsp_write_reg2 is equal to the ADSP DIO write signal for register R2_A2T (see Ref. 4).
The signal ‘tdsp_read_reg2’ is equal to the TDSP1E DIO read signal for register R2_A2T.
These two signals are used to generate the flags ‘adsp_buffer_empty’ and
‘tdsp_buffer_full’.
ADSP DATA
ADSP WRITE REG2
(HARDWARE)
ADSP BUFFER EMPTY (F2 IN
TDSP BUFFER FULL (F11 IN
TDSP READ REG2
(HARDWARE)
TDSP DATA
XXXXX
Fig 33. Handshake example: ADSP to TDSP1E
SAF7741_7
Product data sheet
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Rev. 07 — 28 April 2010
45 of 83
SAF7741HV
NXP Semiconductors
Dual IF car radio and audio DSP (N1F)
7.6.3.2
Software interface description
The flag update is the result of either a 'write R2_A2T' or a 'write R2_T2A' instruction. For
this reason checking these flags at the next instruction after writing to a communication
interface register should be avoided because the flags will not have been updated yet. For
correct behavior there has to be at least one instruction (nop) between the write to either
R2_A2T or R2_T2A and the flag check. However, in practical programming terms this
should not be a restriction.
7.7 Sample-rate convertor DSP (SDSP)
7.7.1 Function
This SDSP is used solely for sample-rate conversion of five separate inputs to one master
output sample rate. The hardware supports five stereo inputs and outputs, the possible
input and output sample-rate combinations depending on the DSP clock frequency.
The digital inputs are grouped into four independent I2S inputs, two SPDIF digital inputs
and two I2S-like inputs from the TDSPs. All of these are stereo channels. Of these inputs,
five can be routed through the SDSP and one can be selected directly as input for the
ADSP. This means that six digital channels can be processed at the same time by the
ADSP where the sixth direct input on the ADSP needs to be sample-rate converted in the
ADSP. When a six-channel - i.e. three I2S channels - DVD source needs to be processed,
I2S input 1, SPDIF1D_DVD34 and SPDIF2D_56 are used to cover all three stereo
channels.
7.7.2 Flags
Six user flags are available for the software running in the SDSP, the stretch mode as well
as the I/O direction of these flags being user-definable. A further six ‘newsam’ flags are
used as sample indicators for the SRC software. These flags have stretch mode pre-set
and are hard-wire coded, and therefore cannot be changed; only disabled or enabled
using the corresponding I2C control bits. The function of each SDSP user flag is shown in
Table 19.
Table 19.
SDSP user flag function
Chip pin name Flag
Function
I/O
Stretch
-
F0
Reference sample rate flag
IN
ON
-
F1
Source 1 sample rate flag
IN
ON
-
F2
Source 2 sample rate flag
IN
ON
-
F3
Source 3 sample rate flag
IN
ON
-
F4
Source 4 sample rate flag
IN
ON
-
F5
Source 5 sample rate flag
IN
ON
[1]
ON/OFF [1]
ADSP_IOF6
F6
User-defined input or output
IN/OUT
ASDP_IOF7
F7
User-defined input or output
IN/OUT [1]
ON/OFF [1]
ADSP_IOF8
F8
User-defined input or output
IN/OUT [1]
ON/OFF [1]
User-defined input or output
[1]
ON/OFF [1]
ADSP_IOF9
F9
SAF7741_7
Product data sheet
Mode
IN/OUT
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46 of 83
SAF7741HV
NXP Semiconductors
Dual IF car radio and audio DSP (N1F)
Table 19.
SDSP user flag function
Chip pin name Flag
Function
Mode
I/O
Stretch
[1]
ON/OFF [1]
ADSP_IOF10
F10
User-defined input or output
IN/OUT
ADSP_IOF11
F11
User-defined input or output
IN/OUT [1]
ON/OFF [1]
-
F12
Out flag to the WDOG status register
IN/OUT [1]
ON/OFF [1]
[1]
I2C-controllable
7.7.3 DIO of the SDSP
For each stereo input one out of eight available stereo sources can be selected via a
switchbox. The input format of each stereo DIO input can then be selected via an I2C
register. For the location of these bits see Ref. 3.
The I2C bits are controlled by the ADSP and the MPI. DIO inputs are also available for the
registers that contain new sample timestamps of the five individual stereo inputs, and
there is one extra register for the reference sample rate. Combined with the new-sample
flags of the inputs and the reference flags, these timestamps allow the DSP program to
convert the five sample rates to the reference on the output (see Figure 34).
SAF7741_7
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Rev. 07 — 28 April 2010
47 of 83
SAF7741HV
NXP Semiconductors
Dual IF car radio and audio DSP (N1F)
SWITCHBOX
IIS1
IIS2
IIS3
IIS4
IIS_SPDIF1
IIS_SPDIF2
IIS_T1
IIS_T2
NWSM_SRC1
cntr_bus1
CONTROL
L
DATA R
3
FORMAT
IIS_IN1(2:0)
IIS_IN2(2:0)
IIS_IN3(2:0)
IIS_IN4(2:0)
24
LOGIC
MUX
d:0
d:1
FORMAT
DECODER
SRC1_IN_SEL(2:0)
NWSM_SRC2
cntr_bus1
CONTROL
1
&
L
3
DATA R
FORMAT
IIS_IN1(2:0)
IIS_IN2(2:0)
IIS_IN3(2:0)
IIS_IN4(2:0)
NWSM_FS_REF
NWSM_SRC1
src2_in
sel="100"
dvd
ctrl='1'
24
NWSM_SRC2
NWSM_SRC1
d:2
d:3
1
NWSM_SRC3
NWSM_SRC1
1
NWSM_SRC3
cntr_bus1
CONTROL
1
&
L
24
&
src3_in_sel="101"
dvd_ctrl='1'
NWSM_SRC4
NWSM_SRC5
src3_in
sel="101"
dvd
ctrl='1'
DATA R
FORMAT
IIS_IN1(2:0)
IIS_IN2(2:0)
IIS_IN3(2:0)
IIS_IN4(2:0)
src2_in_sel="100"
dvd_ctrl='1'
FORMAT
DECODER
SRC2_IN_SEL(2:0)
3
&
d:4
d:5
F0 F1 F2 F3 F4 F5
SDSP/
EPICS7A
FORMAT
DECODER
latch
le
latch
SRC3_IN_SEL(2:0)
le
latch
le
le
3
L
R
IIS_RECEIVER
FORMAT
IIS_IN1(2:0)
IIS_IN2(2:0)
IIS_IN3(2:0)
IIS_IN4(2:0)
24
d:6
d:7
latch
le
NWSM_SRC4
latch
le
FORMAT
DECODER
X_IN
X_OUT
latch
TO
ADSP
le
SRC4_IN_SEL(2:0)
latch
le
3
NWSM_SRC1
1
L
R
IIS_RECEIVER
24
latch
d:8
d:9
le
NWSM_SRC5
latch
FORMAT
IIS_IN1(2:0)
FORMAT
IIS_IN2(2:0)
DECODER
IIS_IN3(2:0)
IIS_IN4(2:0)
SRC5_IN_SEL(2:0)
le
latch
le
TIME STAMP COUNTER
NWSM_SRC2
src2_in_sel="100"
& dvd_ctr='1'
counter
1
NWSM_SRC3
TSR1
le
le TSR2
src3_in_sel="101"
& dvd_ctr='1'
NWSM_SRC4
le TSR3
NWSM_SRC5
le TSR5
NWSM_FS_REF
le TSR6
le TSR4
CLK_DSP
24
24
d:10
d:11
24
d:12
24
d:13
24
d:14
24
d:15
IR_BUS
d:0 d:2 d:4 d:6 d:8
d:1 d:3 d:5 d:7 d:9
LOGIC
DECODER
Fig 34. Digital inputs/outputs of the SDSP
SAF7741_7
Product data sheet
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Rev. 07 — 28 April 2010
48 of 83
SAF7741HV
NXP Semiconductors
Dual IF car radio and audio DSP (N1F)
7.8 Common system descriptions
This section provides descriptions of certain functions and blocks that are not exclusively
related to either the radio or the audio part of the SAF7741HV.
7.8.1 Oscillator
The SAF7741HV has a low-power Pierce oscillator with amplitude control and an inverter
for the gain stage. The inverter biasing together with capacitive input coupling gives the
gain stage Class C operation. When the circuit is oscillating there are sine waves at the
input (osc_in) and at the output (osc_out) with Vpp close to the 1.8 V oscillator supply Vdd.
The sine wave at the input and the output is converted by a low-jitter comparator into a
CMOS-compatible clock.
The oscillator block diagram is shown in Figure 35. The crystal should be connected to the
PCB as close as possible to the oscillator input and output pins of the chip. Care must
also be taken to make sure that the load capacitors Cx1 and Cx2 and OSC_REF_N have
a common ground plain. Loops must be made as small as possible in order to minimize
noise coupling to the crystal nodes, and in addition parasitics should be kept as small as
possible.
AGC
CLKOUT
Gm
COMP
Rbias
OSC IN
OSC OUT
ON CHIP
OFF CHIP
Xtal
Lx3
Cx1
Cx2
Cx3
COMMON GROUND PLANE
Lx3 and Cx3 should be connected only in combination with 3rd overtone crystals
Fig 35. Oscillator block diagram
Lx3 and Cx3 have to be added when the crystal is used at the third overtone frequency.
Table 20 gives specifications for fundamental and third-overtone frequency crystals. CL is
the typical load capacitance of the crystal and is usually specified by the manufacturer.
The actual CL influences the oscillation frequency. Using a crystal manufactured for a
different load capacitance will cause the circuit to oscillate at a slightly different frequency
(dependent on the quality of the crystal) from the specified one. Therefore, to obtain an
accurate time reference, it is advisable to use the load capacitors specified in Table 20. In
addition to start-up problems, the use of values other than those quoted can lead to
performance degradation due to an unstable clock reference.
SAF7741_7
Product data sheet
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Rev. 07 — 28 April 2010
49 of 83
SAF7741HV
NXP Semiconductors
Dual IF car radio and audio DSP (N1F)
Table 20.
Crystal parameters and external components
Name
Value
Third overtone
Fundamental
Maximum parallel capacitance (Cp) 7 pF
7 pF
Load capacitance (Cl)
10 pF
10 pF
Series resistance (Rs)
<60 Ω
<60 Ω
Cx1
≥12 pF
≥8 pF
Cx2
≥12 pF
≥8 pF
Cx3
10 nF
-
Lx3
2.2 μH
-
7.8.2 Voltage regulator
A voltage regulator controls all the 1.8 V supplies of the chip, with input from the 3.3 V
supply. An external PMOS power transistor is used to handle power. The regulated 1.8 V
supply is derived from a band-gap voltage AC-decoupled by an external capacitor so that
a very accurate output voltage is obtained.
ON CHIP
OFF CHIP
VDDREG
3.3V
I start up
GAPREG
CONREG
BAND GAP
EXTERNAL
PMOS
EXTERNAL
DECOUPLING
FEBREG
TO ALL
1.8V SUPPLIES
R1
VGAP
R2
GND
Fig 36. Voltage regulator block diagram
To speed up the settling time of the regulated supply voltage the external capacitor is
charged with a larger current during start-up. When the voltage across the capacitor is
close to the internal reference voltage this current is then switched off. A build in
hysteresis makes sure that this current stays switched off during normal operation.
7.8.2.1
Power dissipation of the external transistor
Under worst-case conditions the total power dissipation of the external PMOS transistor is
about the same as the power consumption of all the 1.8 V supplies. The application
diagram in Section 9 shows the voltage regulator application with the recommended
PHK04P02T power transistor.
SAF7741_7
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Rev. 07 — 28 April 2010
50 of 83
SAF7741HV
NXP Semiconductors
Dual IF car radio and audio DSP (N1F)
7.8.3 Clocking strategy
The overall clocking diagram is shown in Figure 37. The main clock source of the
generated clock frequencies is the crystal oscillator running at 41.6 MHz. This generates
the reference frequency for the:
•
•
•
•
IFADC
PDC
DSP_PLL
Audio PLL
The Audio PLL can also use either the FS_SYS pin or the WS_HOST pin as reference
when the SAF7741HV is in slave mode.
SAF7741_7
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51 of 83
SAF7741HV
NXP Semiconductors
Dual IF car radio and audio DSP (N1F)
WS_HOST_OUT
(IIC) audio_ref_sel
WS_
HOST
AUDIO _ref_dec
SIGNAL DETECT
WS
WS_HOST_IN
Sel
512 x Fs
256 x Fs (only)
FS_
SYS
256,384,
512 x Fs
512 x Fs
AUDIO PLL
AUDIO
CLOCK
DIVIDER
4
HOST_
out(8:1)
5
HOST_
in(8:1)
/512
ws_ref
/256
256 x Fs
bck
_ref
/8
BCK_HOST
pllr
(IIC)
apll_in_sel
SIGNAL
DETECT
FS
not(pd_dac_fl & pd_dac_fr)
/4
DAC front left
DAC front right
Fs_96k sel
PLL AUDIO Sel
DECODER
delay_r
not(pd_dac_ri & pd_dac_rr)
DAC rear left
ENABLE PDC1
DAC rear right
delay_f
not(pd_dac_c
& pd_dac_s)
DAC centre
DAC sub
not(pd_c & pd_dac_s)
/4
Interpolator centre sub
not(pd_dac_rl & pd_dac_rr)
PDC1
/2
Interpolator rear
not(pd_dac_fl & pd_dac_fr)
Interpolator front
/2
128 x Fs
256 x Fs
/1
Interpolator latch
ASFTM
not(pd_adc1 & pd_adc2)
DAD12
not(pd_adc3 & pd_adc4)
DAD34
not(pd_adc5)
PDC
Div
/2
DAD56
/4
not(pd_adc1 & pd_adc2)
/4
/8
PDC2
ADC1
/2
/16
/1
256 x Fs
/32
ADC2
not(pd_adc3 & pd_adc4)
ADC3
/64
/128
not(pd_adc5)
/416 or /104
ADC5
ENABLE PDC2
DSPPLL
AUDIO DSP
enable
IFAD1
IFAD2
Xosc
41.6 MHz
ADC4
TUNER
CLOCK
GENERATOR
SAMPLE RATE
CONVERTER
DSP
enable
TUNER DSP1
100/400kHz
TUNER CLOCK
PLL
/2
TUNER DSP1E
/4
/8
/4
TUNER DSP2
CLK_SPDIF
SPDIF RECEIVER 1
SPDIF RECEIVER 2
Fig 37. Clock strategy overview
SAF7741_7
Product data sheet
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Rev. 07 — 28 April 2010
52 of 83
SAF7741HV
NXP Semiconductors
Dual IF car radio and audio DSP (N1F)
Generation of the DSP and other clocks
The SAF7741HV has two PLL circuits: one (DSP PLL) to generate the system clock for
the DSPs and SPDIF receiver; the other (audio PLL) to generate the audio reference
clocks. The crystal oscillator (radio rate), FS_SYS (external rate) or WS_HOST (audio
rate) can be used as an input for the generation of the audio clocks. For the full setting
ranges of the two PLLs see Ref. 3.
The DSP PLL is used to generate the clock to the DSPs and the SPDIF block.
The clock frequency of the SPDIF block should be chosen so that its relation to the
sample rate of the incoming SPDIF Fs is 660 × Fs < SPDIF CLOCK < 2480 × Fs.
For reasons of power reduction the clock to major blocks can be stopped separately.
Exact bit definitions can be found in the CLK_EN register ($000050) and APD_CTRL1
register ($000040) of Ref. 3.
Audio clock generation is constructed in such a way that the ADSP can simultaneously
process audio samples of 48 kHz and 96 kHz (i.e. double the sample rate frequency).
These samples can be provided to the ADSP via the host inputs and received from the
ADSP via the host outputs. For each host input or output a selection can be made
between Fs or ½ × Fs. Exact bit definitions can be found in Ref. 3.
When the SAF7741HV is in master mode the audio PLL is used to generate Fs from the
crystal oscillator frequency of 41.6 MHz. Fs can be 44.1 kHz, 48 kHz or 96 kHz. When the
SAF7741HV is in the slave mode the AUDIO_PLL can lock onto either WS_HOST or
FS_SYS. If WS_HOST is used as an input its frequency can be 44.1 kHz, 48 kHz or 96
kHz. If FS_SYS pin is selected as the direct source for the internal audio clocks the
maximum sample rate is limited to 48 kHz.
For the PDC blocks (PDC1 and PDC2) the clocks are derived digitally from the crystal
oscillator frequency. The communication clock between SAF7741HV and the tuner IC can
be either 100 kHz or 400 kHz. To reduce noise this tuner clock signal is sent to the tuner
IC via a complementary current source. Frequency selection depends on the type of tuner
connected to the SAF7741HV.
7.8.4 DSP PLL description
The oscillator frequency of 41.6 MHz is first divided by four, then fed to the DSP PLL. The
DSP PLL output can be further divided by two, four or eight (depending on the I2C
settings) before being fed as the clock frequency to the DSP cores and the SPDIF block.
A partial overview of the available frequencies is given in Table 21. The DSP PLL
frequency is controlled via I2C registers.
The output frequency of DSP PLL can be calculated with the formula:
4
F out = 65 × 10 × ( 212 + MSEL ) ⁄ 2
( 3 – DSP_SEL )
Hz
(1)
Where:
• MSEL = the decimal value of the dsp_pll_msel bits of the I2C CLKPLL_CTR register
• DSP_SEL = the decimal value of the dsp_sel bits of the I2C CLKPLL_CTR register
The default output frequency of the DSP PLL is 130 MHz.
SAF7741_7
Product data sheet
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Rev. 07 — 28 April 2010
53 of 83
SAF7741HV
NXP Semiconductors
Dual IF car radio and audio DSP (N1F)
Figure 38 shows a simplified block diagram of the DSP PLL and the generation of the
DSP and SPDIF clocks.
I2C bits DSP_SEL[1:0]
OSC
/4
N DIVIDER
PFD
CCO
/1
/2
/4
/8
P DIVIDER
DSP clock
M DIVIDER
/1
/2
/4
/8
DECODER
I2C bits MSEL[7:0]
SPDIF clock
I2C bits SPDIF_SEL[1:0]
Fig 38. DSP PLL Diagram
Table 21.
M-divider
ratio
Example of DSP PLL setting
MSEL[7:0]
Clock frequency (MHz)
SPDIF_SEL=00 SPDIF_SEL=01 SPDIF_SEL=10 SPDIF_SEL=11
DSP_SEL=00
DSP_SEL=01
DSP_SEL=10
DSP_SEL=11
= M-divider
ratio ×
81.25 kHz
= M-divider
ratio ×
162.50 kHz
= M-divider
ratio ×
325.00 kHz
= M-divider
ratio ×
650.00 kHz
212
0(0x00)
17.225
34.450
68.900
137.800
213
1(0x02)
17.306
34.612
69.225
138.450
214
2(0x03)
17.387
34.775
69.550
139.100
390
178(0xB2)
31.687
63.375
126.750
253.500
400
188(0xBC)
32.50
65.00
130.00
260.00
420
208(0xD0)
34.125
68.250
136.500
273.000
421
209(0xD1)
34.206
68.412
136.825
273.650
422
210(0xD2)
34.287
68.575
137.150
274.300
7.8.5 Audio PLL details
The audio PLL block is responsible for the generation of 512 × Fs where Fs is the master
sampling frequency. The audio PLL has three different inputs:
• Crystal oscillator input at 41.6 MHz. The audio PLL is preset automatically to the
targeted frequencies of 512 × Fs for Fs = 44.1 kHz, Fs = 48 kHz and Fs = 96 kHz
• WS_HOST input. This is used to generate the 512 × Fs output frequencies for the
following input sampling frequencies: Fs = 44.1 kHz, Fs = 48 kHz and Fs = 96 kHz
• FS_SYS input. This is used to generate the 512 × Fs output frequencies for the
following input frequencies: 256 × Fs, 384 × Fs and 512 × Fs where Fs can be either
44.1 kHz or 48 kHz
SAF7741_7
Product data sheet
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Rev. 07 — 28 April 2010
54 of 83
SAF7741HV
NXP Semiconductors
Dual IF car radio and audio DSP (N1F)
To prevent the system from locking up when the WS_HOST or FS_SYS input drops out,
the audio PLL switches automatically to the crystal oscillator input for generating the
appropriate frequency. For example, if the WS_HOST input for Fs = 48 kHz drops out the
audio PLL selects the crystal oscillator as input and generates the 512 × Fs output
frequency with Fs = 48 kHz.
Table 22 lists all the targeted output frequencies. The first column in the table gives the
three possible inputs of the audio PLL while the second column lists the corresponding
input frequencies. The third column shows the targeted sampling frequencies that are
used to derive the output frequency of the PLL as shown in the last column of the table,
i.e. 512 × Fs.
Table 22.
List of frequencies generated by audio PLL
Input signal
Input signal frequency
Osc: Oscillator (41.6 Mhz) 41.6 MHz
WS_HOST
FS_SYS
Targeted Fs (kHz)
Targeted output
frequency = 512 × Fs
44.1
22.583 MHz
41.6 MHz
48
24.576 MHz
41.6 MHz
96
49.152 MHz
44.1 kHz
44.1
22.579 MHz
48 kHz
48
24.576 MHz
96 kHz
96
49.152 MHz
256 × Fs
44.1
22.579 MHz
384 × Fs
44.1
22.579 MHz
512 × Fs
44.1
22.579 MHz
256 × Fs
48
24.576 MHz
384 × Fs
48
24.576 MHz
512 × Fs
48
24.576 MHz
Remark: When the audio PLL is set to lock onto either WS_HOST or FS_SYS the actual
frequency of the input signal is allowed to deviate by up to 20% from the target Fs.
However, optimum audio performance of the SAF7741HV is guaranteed only at 44.1 kHz
and 48 kHz.
7.8.6 Tuner clock generation circuit
To decrease total system cost, the crystal oscillator of SAF7741HV can also be used as
reference clock for the tuner so that the external components of the the tuner’s own
crystal oscillator can be omitted. The technical advantage here is that the tuner and
SAF7741HV clock frequencies are coupled, which prevents performance deterioration as
a result of mismatched frequency domains.
The tuner clock generation circuit uses a differential output current to provide a 100
kHz/400 kHz reference clock. The reference frequency is derived from the crystal
oscillator. To get rid of the disturbances introduced by the digital dividers, the clock for the
current drivers is synchronized by the clean crystal oscillator clock. The differential output
current ensures that the interface between the tuner and SAF7741HV will not interfere
with the application. The output current depends on the number of connected tuners and
needs to be controlled by I2C. See Figure 39 for the dual tuner application.
For the TEF6730 the reference clock frequency can be set to 100 kHz.
SAF7741_7
Product data sheet
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Rev. 07 — 28 April 2010
55 of 83
SAF7741HV
NXP Semiconductors
Dual IF car radio and audio DSP (N1F)
Tuner 1
input buffer
inp
inn
SAF774x
output buffer
R1
180Ω
R2
180Ω
R3
180Ω
R4
180Ω
DICE_CLKP
DICE_CLKN
Tuner 2
input buffer
inp
inn
Fig 39. Dual tuner mode SAF7741HV
7.8.7 RESET sequence
The reset sequence is initiated by the RESETN pin going low, and will finish
approximately 1.0 ms after the pin goes high again.
For a correct reset sequence initialization, the oscillator must be running and the
oscillation must be stable. For small-pulse immunity the RESETN pin must be low during
at least forty oscillator clock periods for a valid reset.
The total time between the RESETN pin going high and the reset sequence finishing is
called the reset time, or tRESET, and is determined by the locking time of the PLLs. Once
both PLLs are in lock the internal reset will stay active for another 2047 oscillator clock
periods before the reset sequence completes. A reset will cause the chip to go into the
initialization state.
When there is a reset the following actions are performed:
• All the bits of the I2C registers are set to their default values
• The DSP’s program counter is reset to zero and kept there until the microprocessor
writes the correct values to the DSP_CTR register ($000010)
•
•
•
•
•
•
The DSP’s status registers are reset
All DSP I/O flags are set to their default modes
The IF processor block is reset
The RDS decoder is reset
The RS and I2C interfaces are reset
The WDOG is reset
The RESETN pin is active low and has an internal pull-up function.
SAF7741_7
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56 of 83
SAF7741HV
NXP Semiconductors
Dual IF car radio and audio DSP (N1F)
7.8.8 I2C interface
The I2C bus is for two-way, two-line-plus-ground communication between different ICs or
modules. The two lines are the Serial Data Line (SDA) and the Serial Clock Line (SCL).
The I2C interface allows access to:
•
•
•
•
•
Radio settings
PLL settings
AD volume control
DSP settings
All DSP registers and memories
The chip acts as an I2C slave, so the SCL clock is input only while the SDA is a
bi-directional line. Both standard-mode I2C (up to 100 kHz) and fast-mode I2C (up to
400 kHz) are supported.
7.8.8.1
I2C switch
The I2C switch enables communication with a secondary I2C bus connecting modules that
are sensitive to digital noise. The switch is bi-directional and is controlled by the I2C block
of the SAF7741HV. It has been designed specifically for an IF front-end chip for FM/AM
reception that works with low voltages delivered by the antenna, and which is therefore
easily disturbed by digital switching.
7.8.9 Watchdog (WDOG)
A Watchdog (WDOG) function has been added to each DSP to detect and signal
operating faults. This feature increases the overall robustness of the system, but it cannot
detect all DSP-related problems. The basic principle is that an instruction (mvi #FFFFFF,
rmy0;) that will certainly not occur elsewhere is added to the DSP program. This
instruction is inserted into the main software loop and will therefore be executed at regular
intervals. To detect whether or not a DSP is running correctly an external circuit will check
that the watchdog instruction has executed within a certain time slot. This slot is I2Cprogrammable to a maximum of 12.6 ms, and is therefore more than sufficient to
accomodate the longest software loop.
The watchdog is disabled when the clock of a particular DSP is stopped or when a DSP is
in reset.
The watchdog function offers a neat way of interrupting the external microcontroller. The
function can also be used to allow the DSPs to interrupt the microcontroller under
software control by means of output flag F12.
The interrupt output pad ADSP_IOF11 is connected to the WDOG logic and is combined
with the ADSP I/O flag F11.
8. I2C memory map and bit definitions
The separate I2C Memory Map and Bit Definitions (Ref. 3) contains all the defined I2C bits
and provides access to the memories of all the DSPs and the various registers throughout
the whole system. It also provides access to the secondary I2C bus for communicating
with the tuner.
SAF7741_7
Product data sheet
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Rev. 07 — 28 April 2010
57 of 83
SAF7741HV
NXP Semiconductors
Dual IF car radio and audio DSP (N1F)
To prevent EMC problems at the high-sensitivity tuner, normal I2C transmissions are not
applied to the I2C bus that is connected to the tuner. Instead the SAF7741HV has a
built-in I2C switch that becomes active the moment the so-called ‘secondary I2C bus
switch’ address is written to, and which de-activates again the moment an I2C stop code is
detected.
SAF7741_7
Product data sheet
© NXP B.V. 2010. All rights reserved.
Rev. 07 — 28 April 2010
58 of 83
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SAF7741_7
Product data sheet
9. Application diagrams
Rev. 07 — 28 April 2010
SAF7741HV
Dual IF car radio and audio DSP (N1F)
59 of 83
© NXP B.V. 2010. All rights reserved.
Fig 40. Single-tuner SAF7741 and TEF7000 application diagram
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NXP Semiconductors
SAF7741_7
Product data sheet
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SAF7741HV
Dual IF car radio and audio DSP (N1F)
60 of 83
© NXP B.V. 2010. All rights reserved.
Fig 41. SAF774x and TEF6730 connections
SAF7741HV
NXP Semiconductors
Dual IF car radio and audio DSP (N1F)
10. Limiting values
10.1 Electrical limiting values
Table 23.
Electrical limiting values (in accordance with the Absolute Maximum Continuous Ratings system
IEC134)
Symbol
Parameter
Min
Max
Unit
VDDD
Supply voltage, internal rail
−0.5
+2.5
V
VDDQ
Supply voltage, external rail
−0.5
+4.6
V
Vi
DC input voltage
All inputs, except for IFAD inputs
−0.5
(VDDQ + 2.5)
or 5.5
V
Vi_ifad
DC input voltage pins IFAD
IFAD pins only
−0.5
VDDQ
V
Isup
DC supply current per supply pin
-
100
mA
Ignd
DC ground current per ground pin
-
100
mA
Tamb
Ambient operating temperature
−40
+85
C
Tstg
Storage temperature
−40
+125
C
ESDS
ESD sensitivity
LU
Ptot
Conditions
Human body model pass voltage
level
AEC - Q100-002 - REV-D
2000
-
V
Charged device model pass
voltage level
AEC - Q100-011 - REV-B
C4
-
Class
Latch Up I-O trigger current
JESD78A
-
100
mA
Latch Up VDD trigger voltage
JESD78A
Total power dissipation
-
1.5 × VDDmax
V
-
1600
mW
Min
Typ
Max
Unit
11. Recommended operating conditions
Table 24.
Operating conditions
Symbol
Parameter
VDDD
Supply voltage, internal rail
1.73
1.8
1.95
V
VDDQ
Supply voltage, external rail
3.0
3.3
3.6
V
Tamb
Ambient temperature
−40
-
+85
C
Conditions
12. Thermal characteristics
Table 25.
Thermal characteristics
Symbol
Parameter
Conditions
Typ
Unit
Rth(j−a)
Thermal resistance from junction to ambient
Jedec 2S2P board with EPAD
connection
24
K/W
12.1 Thermal considerations in choosing a package
According to the worst-case simulations of the chip speed, the maximum allowable
junction temperature is 125 °C. Reducing the thermal resistance of the system is therefore
required, and a relatively effective way of doing this is to design an HLQFP144 with an
exposed die-pad. The metal of the die-pad is exposed at the bottom of the package and
SAF7741_7
Product data sheet
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Rev. 07 — 28 April 2010
61 of 83
SAF7741HV
NXP Semiconductors
Dual IF car radio and audio DSP (N1F)
must be soldered onto a thermal land pattern. The exposed die-pad is used as extra
ground pin in connection with the Kelvin capacitors (see Hardware description manual for
details). The exposed dip-pad is connected with two types of copper plated PCB vias to a
ground plane (see Figure 47). Soldering the die-pad onto the land pattern ensures that
there is good thermal conductivity between the chip and the PCB, but there is little
improvement to the thermal conductivity overall because power dissipation largely
depends upon:
• The heat-radiating area
• The exposure of this area to the environment
• The thermal conductivity of heat-radiating/convecting material
That is why the thermal land pattern must be connected to a large ground plane by a
number of vias that act as heat pipes. It is best to place the vias directly under the
exposed die-pad as they are only 12 mil to 13 mil wide at a 1.2 mm pitch. These vias are
exposed to the solder between the die-pad and the thermal land pattern. Making these
vias only 12 mil to 13 mil wide will prevent solder wicking through the holes during reflow.
The solder mask is not one large mask with the same size as the exposed die-pad, but is
sub-divided into 1.0 mm × 1.0 mm large squares at a pitch of 1.2 mm. However, making
vias of only 12 mil to 13 mil is expensive and here it is proposed to have the vias outside
the solder area. These vias can be larger than 12 mil to 13 mil because these are not on a
solder mask and are depicted here as 25 mil vias.
Thermally speaking, this is not the best solution but results in an acceptable thermal
resistance. Taking the above mentioned considerations into account, it can be stated that
the Rthj-a (thermal conductivity junction-to-ambient) of this package mounted on a
particular PCB (with a specific ground plane area and plating thickness) will be known
only after measuring the Rthj-a. The quality of the soldering of the die-pad to the land
pattern, determines largely the Rthj-a, and some testing by the set maker needs to be done
to be sure that in the production process automotive quality is guaranteed.
The following determine the total Rthj-a of this set-up:
•
•
•
•
•
•
The thickness of the PCB (equal to the length of the plugged VIAs)
The PCB material
The number of conductive layers in the PCB
The number of layers used to connect to the thermal VIAs
The thickness of the copper plating
The copper area exposed to the outside world
Normally, 70% of the IC power is dissipated via the PCB. This could increase to 90% by
using the exposed soldered die-pad solution.
SAF7741_7
Product data sheet
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Rev. 07 — 28 April 2010
62 of 83
SAF7741HV
NXP Semiconductors
Dual IF car radio and audio DSP (N1F)
12.2 Thermal considerations in choosing a package for the SAF7741HV
production chip
HLQFP144SOT612-3 EXPOSED DIE PAD
108
109
5.6 x 5.6 mm
EXPOSED
DIE PAD
A
PCB VIA SOLDER MASK PROPOSAL
TOP THERMAL
LAND PATTERNS
73
72
SOLDER
MASK
1 x 1 mm at
1.2 mm PITCH
ZE
e
E HE
CB
W M
bp
PIN 1 INDEX
144
37
36
1
e
bp
M
20 mil (0.51mm) VIAs 1oz
BARREL PLATING
DIE ATTACH
V M A
PCB TRACKS
B
HD
0.5mm
DEVICE
V M B
EXPOSED DIE PAD
THERMAL LAND
PATTERN
EXPOSED DIE PAD SOT612-3
GROUND RING
PRINTED CIRCUIT
PAD AND BOARD
BOARD
SOLDERING
20 mil (0.51 mm) VIA GROUND PLANE
CROSS SECTION CB
The package dimensions are indicated in Figure 47.
Fig 42. Thermal considerations for package choice
13. Static characteristics
13.1 Supply currents
Table 26.
Current for each supply pin or pin group
Symbol
Parameter
IP_DIG
IP_MEM
Conditions
Min
Typ
Max
Unit
DC supply current of the digital core, pins VDDDx. High activity of the DSPs at
Supply voltage 1.8 V (typical), 1.95 V (max)
135.2 MHz DSP frequency
-
220
290
mA
DC supply current of the memories, pins
VDD_MEMx.
Supply voltage 1.8 V (typical), 1.95 V (max)
High activity of the DSPs at
135.2 MHz DSP frequency
-
100
120
mA
IP_IO
DC supply current of the periphery, pins VDDQx.
Supply voltage 3.3 V (typical), 3.6 V (max)
Without an external load to
ground
-
2.5
8.0
mA
IP_ANA18
Supply current of the analog 1.8 V of IFADC, pin
VDDA_1V8.
Supply voltage 1.8 V (typical), 1.95 V (max)
-
1.6
4.0
mA
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SAF7741HV
NXP Semiconductors
Dual IF car radio and audio DSP (N1F)
Table 26.
Current for each supply pin or pin group …continued
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
IP_ADC18
Supply current of the analog 1.8 V of audio ADC,
pin VDDA_1V8_ADC.
Supply voltage 1.8 V (typical), 1.95 V (max)
-
15
19
mA
IP_AD
Supply current of the audio ADCs and SPDIF
bitslicer, pin VDD_ADC.
Supply voltage 3.3 V (typical) 3.6 V (max)
At zero input signal and zero output signal
18
23
mA
IP_VADCP
Supply current of the audio ADCs and RGP DAC,
pin VADCP.
Supply voltage 3.3 V (typical), 3.6 V (max)
-
0.5
0.7
mA
IP_IFADC
Supply current of the IFADCs and RGP DAC, pin
VDD_IFADC.
Supply voltage 3.3 V (typical), 3.6 V (max)
-
27
35
mA
IP_VDDDAC Supply current of the DAC, pin VDD_DAC. Supply At zero input and output
voltage 3.3 V (typical)
signal
-
0.7
1.2
mA
IP_VDACP
Supply current of the DAC, pin VDACP. Supply
voltage 3.3 V (typical), 3.6 V (max)
At zero input and output
signal
-
5.6
7.3
mA
IP_XTAL
Supply current XTAL oscillator, tuner clock
generator and PLLs, pin OSC_REF.
Supply voltage 1.8 V (typical), 1.95 V (max)
OSC functional mode at
41.6 MHz and a Cload = 10
pF.
PLLs at default settings.
-
3.2
4.1
mA
IP_REG
Supply current regulator, pin VDD_REG.
Supply voltage 3.3 V (typical), 3.6 V (max)
Functional mode
-
0.4
0.52
mA
Ptot
Total power dissipation
High activity of the DSPs at
135.2 MHz
-
800
1125
mW
13.2 DC characteristics
Table 27.
DC characteristics digital I/O (at Tamb = −40°C to +85 °C, VDDQ = 3.3 V unless otherwise stated )
Symbol Parameter
Conditions
Min
Typ
Max
Unit
VDDD
Operating supply voltage 1.8 V
analog and digital
All VDD pins with respect to Vss all
parts
1.73
1.8
1.95
V
VDDQ
Operating supply voltage 3.3 V
peripheral
All VDDQ pins with respect to Vss all
parts
3.0
3.3
3.6
V
VIH
High level, input voltage
All digital inputs and I/Os
2.0
-
-
V
VIL
Low level, input voltage
All digital inputs and I/Os
-
-
0.8
V
Vhyst
Input hysteresis voltage
All digital inputs and I/Os
0.4
-
-
V
VOH
Static output, high voltage
All digital inputs and I/Os
VDDQ
− 0.4
-
-
V
VOL
Static output, low voltage
All digital inputs and I/Os
-
-
0.4
V
IOZ
3-state leakage current towards
either VSSQ or VDDQ
Input voltage < VIL
-
−1
-
μA
Input voltage > VIH
-
1
-
μA
VIL < input voltage < VIH
-
20
-
μA
IOSH
Short circuit current, output high
Drive high. Pad connected to ground
-
-
40
mA
IOSL
Short circuit current, output low
Drive low. Pad connected to VDDQ
-
-
45
mA
IPU
Pull-up current
Vi = 0.0 V
-
−50
-
μA
IPD
Pull-down current
Vi = 3.3 V
-
50
-
μA
SAF7741_7
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Rev. 07 — 28 April 2010
64 of 83
SAF7741HV
NXP Semiconductors
Dual IF car radio and audio DSP (N1F)
Table 27.
DC characteristics digital I/O (at Tamb = −40°C to +85 °C, VDDQ = 3.3 V unless otherwise stated ) …continued
Symbol Parameter
Conditions
Min
Typ
Max
Unit
CIN
Including bond pads
-
-
3
pF
V
I2C
Input capacitance
pads
VIL
Low level input voltage
−0.5
-
0.3 ×
VDDQ
VIH
High level input voltage
0.7 ×
VDDQ
-
VDDQ + V
0.5
Vhys
Hysteresis voltage
0.1 ×
VDDQ
-
-
V
IOL
Low level output current
At VOL = 0.4V
3
-
-
mA
IOH
High level output current
0.3 × VDDQ <VOH < 0.7 × VDDQ
3
-
12
mA
All power supply voltages are within
the specified values
-
0.6
2
ms
-
-
2000
μA
Miscellaneous
tRESET
Time when the device is ready for
use after the rising edge of the
RESETN pin
Iddq
Digital quiescent (not active) current VDDD = 1.95 V
VDDQ = 3.6 V
14. Dynamic characteristics
Table 28.
Digital pins timing characteristics
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
tRF
Output rise/fall time digital pads non
slew-rate controlled
[1]
2.5
-
5.5
ns
tRF_SC
Output rise/fall time digital pads
slew-rate controlled
[1]
FMAX
Maximum operating frequency
[1]
[1]
10
-
-
ns
50
MHz
Output load = 30 pF. Measurement criteria is 10% to 90%.
14.1 RDS electrical specification
Remark: Refer to Ref. 1 for the timing figure in Direct Output mode.
Figure 43 shows the timing of the interface signals in buffer mode.
D0
RDS_DATA
D1
D2
D13
D14
D15
RDS_CLK
Twb
BLOCK READY
Tpb
Thb Tlb
START READING DATA
Fig 43. RDS Timing in buffer mode
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Rev. 07 — 28 April 2010
65 of 83
SAF7741HV
NXP Semiconductors
Dual IF car radio and audio DSP (N1F)
Table 29.
Timing of the RDS interface (see Figure 43)
Symbol
Parameter
Min
Typ
Max
Unit
Frdscl
Nominal clock frequency of the RDS clock
-
1187.5
-
Hz
Twb
Wait time
1
-
-
μs
Tpb
Periodic time
2
-
-
μs
Thb
Clock high-time
1
-
-
μs
Tlb
Clock low-time
1
-
-
μs
Fexcl
Input frequency External RDSA Clock
-
-
10
MHz
14.2 Digital radio output
DR_WS
TDR_BCK(H)
tr;DR_BCK
ts;DR_WS
th;DR_WS
tr;DR_BCK td;DR_DAT
DR_BCK
TDR_cy
th;DR_DAT
TDR_BCK(L)
ts;DR_DAT
DR_I_DAT
DR_Q_DAT
Fig 44. Digital radio I2S timing format
Table 30.
Timing digital radio outputs
Symbol
Parameter
Min
Typ
Max
Unit
TDR_cy
Bitclock cycle time
-
96.15
-
ns
tr;DR_BCK
Rise time
-
-
14
ns
tr;DR_BCK
Fall time
-
-
-
ns
TDR_BCK(H)
Bitclock time HIGH
34
-
-
ns
TDR_BCK(L)
Bitclock time LOW
34
-
-
ns
ts;DR_DAT
Data setup time
19
-
-
ns
th;DR_DAT
Data hold time
19
-
-
ns
td;DR_DAT
Data delay time
-
-
14
ns
ts;DR_WS
Word select setup time
19
-
-
ns
th;DR_WS
Word select hold time
19
-
-
ns
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SAF7741HV
NXP Semiconductors
Dual IF car radio and audio DSP (N1F)
14.3 IIS timing specification
LEFT
WS
RIGHT
tBCK(H)
tr
ts:ws
tf
th:ws
td:DAT
BCK
tBCK(L)
ts:DAT
th:DAT
DATA IN
LSB
DATA OUT
MSB
LSB
MSB
Fig 45. Input timing of the digital audio data inputs and the digital audio data outputs
Table 31.
Timing digital audio inputs and outputs (see Figure 45)
Symbol
Parameter
Min
Max
Unit
Tcy
Bitclock cycle time
162
-
ns
tr
Rise time
-
0.15 × Tcy
ns
tf
Fall time
-
0.15 × Tcy
ns
tBCK(H)
Bitclock time HIGH
0.35 × Tcy
-
ns
tBCK(L)
Bitclock time LOW
0.35 × Tcy
-
ns
ts;DAT
Data set-up time
0.2 × Tcy
-
ns
th;DAT
Data hold time
0.2 × Tcy
-
ns
td;DAT
Data delay time
-
0.15 × Tcy
ns
ts;WS
Word select set-up time
0.2 × Tcy
-
ns
th;WS
Word select hold time
0.2 × Tcy
-
ns
SAF7741_7
Product data sheet
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67 of 83
SAF7741HV
NXP Semiconductors
Dual IF car radio and audio DSP (N1F)
14.4 I2C electrical specifications
14.4.1 I2C timing
SDA
tHD;STA
tLOW
tBUF
tR
tSP
tF
SCL
P
S
tHD;STA
tHD;DAT
tHIGH
tSU;DAT
tSU;STA
tSU;STO
Sr
P
Fig 46. Definition of timing on the I2C bus
Table 32.
Timing I2C bus, see Figure 46
Symbol Parameter
Conditions Standard
Mode I2C Bus
Min
Max
Min
Max
Unit
fSCL
SCL clock frequency
0
100
0
400
kHz
tBUF
Bus free between a STOP and a
START condition
4.7
-
1.3
-
μs
tHD:STA
Hold time (repeated) START
condition.
After this period, the first clock
pulse is generated
4.0
-
0.6
-
μs
tLOW
LOW period of the SCL clock
4.7
-
1.3
-
μs
tHIGH
HIGH period of the SCL clock
4.0
-
0.6
-
μs
tSU:STA
Set-up time for a repeated
START condition
4.7
-
0.6
-
μs
tHD:DAT
DATA hold-time
0
-
0
0.9
μs
tSU:DAT
DATA set-up time
250
-
100
-
ns
tr
Rise time of both SDA and SCL
signals [1]
Cb in pF
20 +
0.1Cb
300
20 +
0.1Cb
300
ns
tf
Fall time of both SDA and SCL
signals [1]
Cb in pF
20 +
0.1Cb
300
20 +
0.1Cb
300
ns
tSU;STO
Set-up time for the STOP
condition
4.0
-
0.6
-
μs
Cb
Capacitive load for each bus line
-
400
-
400
pF
tSB
Pulse width of the spikes to be
suppressed by the input filter
0
80
0
80
ns
[1]
Measurement criteria is 30% to 70%.
SAF7741_7
Product data sheet
Fast Mode
I2C Bus
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Dual IF car radio and audio DSP (N1F)
14.5 SPDIF
Table 33.
Symbol
Analog SPDIF characteristics (conditions: Tamb = 25°C, unless otherwise stated)
Parameters
Conditions
Min
Typ
Max
Unit
VDD_SPD Supply voltage for the SPDIF
IF
3.0
3.3
3.6
V
SPVL
AC input level
0.2
-
3.6
Vpp
SPIR
Input resistance
5.5
8.5
14
kΩ
SPIC
Input capacity
-
50
-
pF
SPHYS
Hysteresis input
30
40
55
mV
SPCIN
Input couple capacitor
-
10
-
nF
fi = 1.0 kHz
14.6 Audio ADC
Table 34.
Audio ADC DC characteristics (conditions: Tamb = 25°C, unless otherwise stated)
Symbol
Parameter
VDDA_1v8_ADC
Min
Typ
Max
Unit
Supply voltage analog part
ADCs
1.73
1.80
1.95
V
VDD_ADC
Supply voltage analog part
ADCs
3.0
3.3
3.6
V
VREFAD
Common mode output
reference voltage ADCs
With respect to
VADCP/VADCN
47
50
53
%VADCP
ZOUT
Output impedance VREFAD
Iout <2 mA
-
10
100
Ω
VADCP
Positive input reference voltage
ADCs and RGPDAC
3.0
3.3
3.6
V
VADCN
Negative input reference
voltage ADCs and RGPDAC
−0.3
0
0.3
V
IVADCN
Negative input reference
current ADCs and RGPDAC
-
370
-
μA
Table 35.
Conditions
Audio ADC AC characteristics (conditions: Tamb = 25°C, VDD_ADC = 3.3 V, VDDA_1v8 = 1.8 V,
VADCP/VADCN = 3.3 V, Fs = 44.1 kHz, unless otherwise stated)
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
AILVL
Conversion input level at ADC input
<1% Total Harmonic
Distortion (THD)
-
-
0.7
Vrms
AIIRG
Input resistance AIN0 to AIN4
1
-
-
MΩ
AITHDC
THD+N AIN0 to AIN4 inputs
1 kHz,
0.5 Vrms,
BW = 20 kHz
-
−82
−76
dB
AISNRC
SNR AIN0 to AIN4 inputs
1 kHz,
BW = 20 kHz,
0 dB ref. = 0.5 Vrms
85
92
-
dBA
SAF7741_7
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SAF7741HV
NXP Semiconductors
Dual IF car radio and audio DSP (N1F)
Table 35.
Audio ADC AC characteristics (conditions: Tamb = 25°C, VDD_ADC = 3.3 V, VDDA_1v8 = 1.8 V,
VADCP/VADCN = 3.3 V, Fs = 44.1 kHz, unless otherwise stated)
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
AICRI
Crosstalk between inputs
1 kHz, 0.5 Vrms, measured
input ac grounded
65
-
-
dB
15 kHz, 0.5 Vrms, measured 50
input ac grounded
-
-
dB
CMRRCD
CMRR high common mode
AIN0_R_GND = 1 MΩ,
RCD Player GND cable =
<1 kΩ,
Fin = 1 kHz, 100 mVrms
60
-
-
dB
B_ADC
Audio input frequency response
−3 dB roll-off,
Fs = 44.1 kHz
20
-
-
kHz
14.7 IFADC
Table 36.
IFADC DC Characteristics (conditions: Tamb = 25°C, unless otherwise stated)
Symbol
Parameter
VDDA_1v8
Supply voltage analog part IFADC
Min
Typ
Max
Unit
1.73
1.80
1.95
V
VDD_IFADC Supply voltage analog part IFADC
and RGPDAC
3.0
3.3
3.6
V
VIFADCP
Positive output reference voltage
IFADC
2.65
-
3.0
V
VIFADCN
Negative input reference voltage
IFADC
−0.3
0
+0.3
V
VIFADCBG
Band gap output reference voltage
IFADC
1.15
1.26
1.30
V
IF_INPR
Single ended input resistance IFADC
in low IF mode
TEF7000 tuner application
16.5
20.9
25
kΩ
Single ended input resistance IFADC
in normal IF mode
TEF6730 tuner application
50
62.2
75
kΩ
Table 37.
Conditions
IFADC AC Characteristics in low IF mode (conditions: Tamb = 25°C, VDD_IFADC = 3.3 V, VDDA_1v8 = 1.8 V,
unless otherwise stated)
Symbol
Parameter
Min
Typ
Max
Unit
LIF_CNR3k
Carrier-to-Noise ratio total IF 1.4 Vpp input IFADC,
bandwidth 3 kHz,
typical application running
Conditions
90
100
-
dB
LIF_DNR
Dynamic range IF
Vdif = 0.5 Vrms
BW = 3.0 kHz
95
102
-
dB
LIF_IM_−6
Third order inter-modulation
with −6 dB signals IF
Two −6 dB signals at 300 kHz and 305 kHz, with respect to 0.0 dB
level
−88
−
dB
LIF_IM_−9
Third order inter-modulation
with −9 dB signals IF
Two −9 dB signals at 300 kHz and 305 kHz, with respect to 0.0 dB
level
−92
−
dB
LIF_IR
Image rejection IF
Two input signals that have a 90°
phase shift and equal gain
50
-
dB
SAF7741_7
Product data sheet
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Rev. 07 — 28 April 2010
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SAF7741HV
NXP Semiconductors
Dual IF car radio and audio DSP (N1F)
Table 38.
IFADC AC Characteristics in normal IF mode (conditions: Tamb = 25°C, VDD_IFADC = 3.3 V, VDDA_1v8 =
1.8 V, unless otherwise stated)
Symbol
Parameter
IF_CNR3k
Carrier-to-Noise ratio total IF 1.4 Vpp input IFADC,bandwidth 3
kHz; typical application running
Conditions
IF_DNR
Dynamic range IF
Vdif = 0.5 Vrms BW = 3.0 kHz
Min
Typ
Max
Unit
-
95
-
dB
-
97
-
dB
IF_IM_-6
Third order inter-modulation
with -6 dB signals IF
Two -6 dB signals at 10.71MHz
and 10.705MHz, with respect to
0.0 dB level
-
−81
-
dB
IF_IM_-9
Third order inter-modulation
with -9 dB signals IF
Two -9 dB signals [1] at 10.71MHz
and 10.705MHz, with respect to
0.0 dB level
-
−89
-
dB
IF_IR
Image rejection IF
Two input signals that have a 90°
phase shift and equal gain
45
50
-
dB
[1]
[1]
The two signals are at 10.700 MHz and 10.705 MHz.
14.8 Voltage regulator
Table 39.
Symbol
Analog regulator characteristics (conditions: Tamb = 25°C, unless otherwise stated)
Parameter
Conditions
Min
Typ
Max
Unit
VDD_REG
Supply voltage regulator
3.0
3.3
3.6
V
GAPREG
Band gap output reference voltage
regulator
-
1.246
-
V
VFEBREG
Voltage at the pins FEBREG
PMOST PHK04P02T in 1.82
application
1.91
1.95
V
VDD_REG = 3.3 V
0.5
-
VDD_REG − 0.3 V
-
0.5
see [1]
VCONREG Regulator control range
REGSU
[1]
Start-up time regulator
ms
Dependent on the external components.
14.9 Audio DAC (ADAC)
Table 40.
Symbol
Audio DAC DC characteristics (conditions: Tamb = 25°C, unless otherwise stated)
Parameter
Conditions
Min
Typ
Max
Unit
VDD_DAC DAC digital power supply
3.0
3.3
3.6
V
VDACP
Positive input reference voltage DAC
3.0
3.3
3.6
V
VDACN
Negative input reference voltage DAC
−0.3
0
+0.3
V
-
VDACP / 2 -
V
Rload >20 kΩ AC
coupled only
VOUT_DC Average DC output voltage
ROUTDA
DAC output resistance
0.7
1.0
1.3
kΩ
RREFDA
Resistance between VDACP and VDACN
-
0.66
-
kΩ
ISCDA
Output short-circuit current DAC
-
-
5.2
mA
B
Bandwidth DA
(Roll-off due to internal DA source resistance
and external capacitor / load)
-
48
-
kHz
At -3.0 dB,
Cfil = 3.3 nF NPO
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SAF7741HV
NXP Semiconductors
Dual IF car radio and audio DSP (N1F)
Table 40.
Audio DAC DC characteristics (conditions: Tamb = 25°C, unless otherwise stated)
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
B_DAC
Roll-off due to internal DAC filter
At -3.0 dB,
Fs = 44.1 kHz
20
-
-
kHz
DAC-CFIL Filter capacitance on DAC outputs
NPO capacitor used
-
3.3
-
nF
DAC-RL
AC coupled only
20
-
-
kΩ
Table 41.
Symbol
Allowed load resistor on DAC voltage outputs
Audio DAC AC characteristics (conditions: Tamb = 25°C, VDD_DAC = 3.3 V, VDACP / VDACCN = 3.3 V,
Rload AC = 20 kΩ, Fs = 44.1 kHz, unless otherwise stated)
Parameter
Conditions
VOUT_AC Output voltage AC of Op-Amp outputs at full
I2S signal
Min
Typ
Max
Unit
0.95
1.0
1.10
Vrms
PSRRDA
Reference power supply Ripple Rejection
DACs
Fripple = 1.0 kHz,
Vripple = 100 mVpeak,
CVDACP = 220 μF
3
6
-
dB
UNBAL
Deviation in output level of one of the six
DAC outputs with respect to the average of
the six outputs
Full-scale output
-
-
0.2
dB
XT
Channel separation between the outputs in
the audio band.
Front or Rear outputs digital silence, others
maximum volume
fi = 1.0 kHz
74
86
-
dB
THD and
N/S
DAC total harmonic distortion plus noise,
versus Output signal DAC
fi = 1.0 kHz,
−0.2 dB
Cfil = 3.3 nF NPO
-
−78
−70
dB
THD and
N/S 60
DAC total harmonic distortion plus noise,
versus Output signal DAC at -60 dB
fi = 1.0 kHz,
−60 dB,
Cfil = 3.3 nF NPO
-
−45
−40
dBA
SNR
Signal-to-Noise ratio.
This is the dB ratio between the full I2S
signal and the I2S digital silence noise
100
106
-
dBA
IM
Intermodulation distortion
-
-70
-55
dB
fi = 60 Hz and 7 kHz,
ratio = 4:1
14.10 RGPDAC
Table 42.
Symbol
RGPDAC DC Characteristics (conditions: Tamb = 25°C, unless otherwise stated)
Parameter
Conditions
Min
Typ
Max
Unit
VDD_IFADC Supply voltage analog part IFADC
and RGPDAC [1]
3.0
3.3
3.6
V
VADCP
Positive output reference voltage
Audio ADC [2]
3.0
3.3
3.6
V
VADCN
Negative input reference voltage
Audio ADC [2]
-0.3
0
0.3
V
DCR_RDA
DC output voltage range RGPDAC
VSS_IFA DC + 0.3
VDD_IF
ADC −
0.3
V
SAF7741_7
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SAF7741HV
NXP Semiconductors
Dual IF car radio and audio DSP (N1F)
Table 42.
RGPDAC DC Characteristics (conditions: Tamb = 25°C, unless otherwise stated)
Symbol
Parameter
ISC_RDA
Conditions
Min
Typ
Max
Unit
Output short circuit current RGPDAC Output short circuit current to
ground at maximum positive
output DC voltage
-
-
120
mA
RL_RDA
Resistive load RGPDAC
50
-
-
kΩ
CL_RDA
Capacitive load RGPDAC
-
-
200
pF
[1]
These are the same values as those given in Table 36. They have been added here because the same supply pins are connected to the
Audio AD and to the RGPDAC.
[2]
These are the same values as those given in Table 34. They have been added here because the same supply pins are connected to the
Audio ADC and to the RGPDAC.
Table 43.
RGPDAC AC Characteristics (conditions: Tamb = 25°C, VDD_IFADC = 3.3 V, unless otherwise stated)
Symbol
Parameter
R_RDA
Resolution of RGPDAC
INL_RDA
Integral non-linearity RGPDAC
DNL_RDA
Differential non-linearity RGPDAC
PSRR_RDA Power supply Ripple Rejection
RGPDAC
FS_RDA
Conditions
Min
Typ
Max
Unit
-
10
-
bits
F = 1.0 kHz,
Sampling rate = 400 kHz
-
2.5
7
LSB
levels
F = 1.0 kHz,
Sampling rate = 400 kHz
-
1.25
2.5
LSB
levels
Fripple = 1.0 kHz,
Vripple = 100 mVpeak peak
43
48
-
dB
-
-
400
kHz
Sample rate of RGPDAC
14.11 Tuner clock generator
Table 44.
Tuner clock generator characteristics (conditions: Tamb = 25°C, VDD_1V8 = 1.8 V, unless otherwise
stated)
Symbol
Parameter
Tcg_Clock
Clock output frequency
Conditions
Min
Typ
Max
-
400/100 -
Unit
kHz
[1]
Tcg_Cur
Output current sourcing/sinking
Single tuner mode
200
300
400
μA
Dual tuner mode
400
600
800
μA
Tcg_ICM
Common mode output current
From each pin to ground
−50
-
50
μA
Tcg_Vout
DC level at the outputs
DC level will be determined
by the load current
1.0
1.2
1.4
V
Tcg_Load
Load impedance
-
180
-
Ω
[1]
Depends on the type of the tuner connected to the SAF774x
14.12 Oscillator
Table 45.
Symbol
Oscillator characteristics (conditions: Tamb = 25°C [1], unless otherwise stated)
Parameter
Conditions
VDD_XTAL Supply voltage crystal oscillator
and PLL
SAF7741_7
Product data sheet
Min
Typ
Max
Unit
1.73
1.8
1.95
V
© NXP B.V. 2010. All rights reserved.
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SAF7741HV
NXP Semiconductors
Dual IF car radio and audio DSP (N1F)
Table 45.
Oscillator characteristics (conditions: Tamb = 25°C [1], unless otherwise stated)
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
XTFREQ
Crystal frequency
Cload = 10 pF, 3rd overtone
-
41.6
-
MHz
Adjustment tolerance
Tamb = 25°C
−50
-
+50
ppm
Temperature drift for WX
applications
−30
-
+30
ppm
Temperature drift AM/FM
applications
−50
-
+50
ppm
Aging drift (all applications)
−5
-
+5
ppm
XLOAD
Load capacitance
-
10
-
pF
RXTAL
Allowed loss resistor of the crystal
-
-
60
Ω
CPXTAL
Parallel package capacitance
-
-
7
pF
XROUT
Oscillator output impedance
AC method: Vim = 20 mVrms @ 1.0 MHz 600
-
1100
Ω
DC method: Vim = 600 mVrms @ DC
-
3150
W
AC method: Vim = 20 mVrms @ 1.0 MHz 13
24
35
mA/V
DC method: Vim = 600 mVrms @ DC
-
22
mA/V
XGM
[1]
Oscillator trans conductance
Cload = 10 pF
1350
13
The oscillator can operate within a temperature range of −40°C to 85°C.
SAF7741_7
Product data sheet
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SAF7741HV
NXP Semiconductors
Dual IF car radio and audio DSP (N1F)
15. Package outline
The package outline for the SAF7741HV is a SOT612-3 (HLQFP144). The outer
dimensions are 20 mm × 20 mm × 1.4 mm (see Figure 47).
The sub-package has a double down set with an exposed die-pad of 5.6 mm × 5.6 mm
and a ground ring at a higher level that is connected mechanically to the exposed die-pad.
Lead number 98 is a fused lead to this ground ring.
SAF7741_7
Product data sheet
© NXP B.V. 2010. All rights reserved.
Rev. 07 — 28 April 2010
75 of 83
SAF7741HV
NXP Semiconductors
Dual IF car radio and audio DSP (N1F)
HLQFP144: plastic thermal enhanced low profile quad flat package; 144 leads;
body 20 x 20 x 1.4 mm; exposed die pad
SOT612-3
c
y
exposed die pad
X
A
Dh
73
72
108
109
ZE
e
Eh
E HE
A A2
(A 3)
A1
θ
wM
Lp
bp
L
pin 1 index
detail X
37
144
1
36
v M A
ZD
wM
bp
e
D
B
HD
v M B
0
5
10 mm
scale
DIMENSIONS (mm are the original dimensions)
UNIT
A
max.
A1
A2
A3
bp
c
D(1)
Dh
E(1)
Eh
e
mm
1.6
0.12
0.05
1.45
1.35
0.25
0.27
0.17
0.20
0.09
20.1
19.9
5.7
5.5
20.1
19.9
5.7
5.5
0.5
HD
HE
22.15 22.15
21.85 21.85
L
Lp
v
w
y
1
0.75
0.45
0.2
0.08
0.08
ZD(1) ZE(1)
1.4
1.1
1.4
1.1
θ
o
7
o
0
Note
1. Plastic or metal protrusions of 0.25 mm maximum per side are not included.
OUTLINE
VERSION
SOT612-3
REFERENCES
IEC
JEDEC
JEITA
EUROPEAN
PROJECTION
ISSUE DATE
02-07-12
04-07-05
MS-026
Fig 47. SOT612-3 (HLQFP144) package outline
SAF7741_7
Product data sheet
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SAF7741HV
NXP Semiconductors
Dual IF car radio and audio DSP (N1F)
16. Abbreviations
Table 46.
Abbreviations
Acronym
Description
ADC
Analog−to−Digital Converter
ADF
Audio Decimation Filter
ADSP
Audio DSP
AF
Alternate Frequency
AFC
Automatic Frequency Control
AGC
Automatic Gain Control
AM
Amplitude Modulation
A/S−DSP
Audio/Sampled DSP
BCK
Bit-Clock
BSLP
Bit−Slip
BSPA
Bit−Slip Process Active
CD
Compact Disc
CIC
Cascaded Integrator Comb filter
Carrier Identification Code
CLK
Clock
CMOS
Complementary Metal Oxide Semiconductor
CMRR
Common Mode Rejection Ratio
CRD
Cordic Rate and De−rotate
DAC
Digital−to−Analog Converter
DAD
Audio DAC Decimation
DAVB
Digital Audio and Video Broadcasting
DAVN
Data Available Signal (on RDS)
Dice
Digital In Car Entertainment
DIO
Digital I/O (on EPICS7A)
DIV
Divide
Divider
DL
DiRaNa2 LeafDice
DRM
Digital Radio Mondiale
DSP
Digital Signal Processor
DVD
Digital Video Disc
Digital Versatile Disc
EBU
European Broadcasting Union
EPICS
Economic Parameterized Integrated CoreS
ESD
Electrostatic Discharge
FIR
Finite Impulse Response
FM
Frequency Modulation
GPIO
General Purpose I/O
I/O
Input/Output
I2C
Inter−IC Communication
SAF7741_7
Product data sheet
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77 of 83
SAF7741HV
NXP Semiconductors
Dual IF car radio and audio DSP (N1F)
Table 46.
Abbreviations …continued
Acronym
Description
I2S
Inter−IC Sound (a Philips standard)
IAC
Interference Absorption Circuit
IBOC
In−Band On−Channel
IF
Intermediate Frequency
IFADC
Intermediate Frequency Analog−to−Digital Converter
IFFC
IF Filter Compensation
IFLAG
I Flag (EPICS7A flag)
IIS
Inter−IC Sound (any data format)
IMODE
Input Flag Mode of EPICS7A
IQ
Quadra−tone Signals I and Q
IQC
IQ Correction
JTAG
Joint Test Action Group
kSa/s
kilo Samples per second
LFLAG
L Flag (EPICS7A flag)
LMS
Least Mean Square
LSB
Least Significant Bit
MPI
MicroProcessor Interface
MPX
Frequency MultiPleXed signal (audio/data)
MSa/s
Mega Samples per second
MSB
Most Significant Bit
MSEL
Selection for the M−divider
NSEL
Selection for the N−divider
NLMS
Normalized Least Mean Square
NZIF
Near Zero IF
PCB
Printed Circuit Board
PDC
Primary Decimation Chain
PLL
Phase Lock Loop
PMOS
Positive channel Metal Oxide Semiconductor
RBDS
Radio Broadcast Data System
Radio Broadcast Data Signals
RDS
Radio Data System
RDDA
RDS Data Output
Radio Digital DAta
RDCL
RDS CLock output (master mode)
RDS CLock input (slave mode)
RGP
Radio General Purpose
RGP DAC
Radio General Purpose Digital−to−Analog Converter
ROM
Read Only Memory
SCL
Serial Clock (I2C line)
SDA
Serial Data (I2C line)
SDSP
Sample Rate Converter DSP
SAF7741_7
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© NXP B.V. 2010. All rights reserved.
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78 of 83
SAF7741HV
NXP Semiconductors
Dual IF car radio and audio DSP (N1F)
Table 46.
Abbreviations …continued
Acronym
Description
SFLAG
Sync Flag
SPDIF
Sony/Philips Digital Interface Format
SRC
Sample Rate Converter
TDSP
Tuner DSP
THD
Total Harmonic Distortion
TTL
Transistor-Transistor Logic
VDD
Positive supply voltage
VDDA
Positive supply voltage (analog)
VDDE
Positive supply (peripheral cells)
VIA
A link between two layers of a PCB
VREFAD
Reference voltage for ADC
VSS
Negative supply voltage
VSSA
Negative supply voltage (analog)
VSSE
Ground supply (peripheral cells)
WB
Weather Band
WDOG
WatchDog
WS
Word−Size
XRAM
X (typically for DSP data) Random Access Memory
YRAM
Y (typically for DSP coefficients) Random Access Memory
YROM
Y (typically for DSP coefficients) Read Only Memory
ZIF
Zero IF
17. References
[1]
SAF7741HV Radio User Manual
[2]
SAF7741HV User Manual
[3]
SAF7741HV I2C Memory Map
[4]
SAF7741HV DIO Map
[5]
Official Philips I2S Standard Document (available from NXP Semiconductors, International
Marketing and Sales)
[6]
Digital Audio Interface specification (IEC60958-1 Edition 2, Part 1: General Part and
IEC60958-3 Edition 2, Part 3: Consumer Applications)
SAF7741_7
Product data sheet
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Rev. 07 — 28 April 2010
79 of 83
SAF7741HV
NXP Semiconductors
Dual IF car radio and audio DSP (N1F)
18. Revision history
Table 47.
Revision history
Document ID
Release Date
Data Sheet Status
Change Notice
Document
Number
Supersedes
DAF7741HV_7
20100428
Product data sheet
-
9397 750
SAF7741HV_6
Objective data sheet
-
9397 750
SAF7741HV_5
Objective data sheet
-
9397 750
SAF7741HV_4
-
9397 750
SAF7741HV_3
Modifications
•
Specification status changed to Product data sheet
DAF7741HV_6
20080712
Modifications
•
Figure 42 has been updated
SAF7741HV_5
20080509
Modifications
•
Some minor updates and corrections.
SAF7741HV_4
20080214
Objective data sheet
Modifications
•
Updated the single-tuner SAF7741 and TEF7000 application diagram (Figure 40).
SAF7741HV_3
20080125
Objective data sheet
-
9397 750
SAF7741HV_2
Objective data sheet
-
9397 750
SAF7741HV_1
Modifications
•
Some minor corrections.
SAF7741HV_2
20080117
Modifications
•
•
•
The format of this user manual has been redesigned to comply with the new identity guidelines of NXP Semiconductors
Legal texts have been adapted to the new company name where appropriate
Updated to incorporate changes since initial release.
SAF7741HV_1
20061031
Objective data sheet
-
9397 750
-
Contact information
For additional information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: salesaddresses@nxp.com
SAF7741_7
Product data sheet
© NXP B.V. 2010. All rights reserved.
Rev. 07 — 28 April 2010
80 of 83
SAF7741HV
NXP Semiconductors
Dual IF car radio and audio DSP (N1F)
19. Legal information
19.1 Data sheet status
Document status[1][2]
Product status[3]
Objective [short] data sheet
Development
This document contains data from the objective specification for product development.
Preliminary [short] data sheet
Qualification
This document contains data from the preliminary specification.
Product [short] data sheet
Production
This document contains the product specification.
Definition
[1]
Please consult the most recently issued document before initiating or completing a design.
[2]
The term ‘short data sheet’ is explained in section “Definitions”.
[3]
The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status
information is available on the Internet at URL http://www.nxp.com.
19.2 Definitions
Draft — The document is a draft version only. The content is still under
internal review and subject to formal approval, which may result in
modifications or additions. NXP Semiconductors does not give any
representations or warranties as to the accuracy or completeness of
information included herein and shall have no liability for the consequences of
use of such information.
Short data sheet — A short data sheet is an extract from a full data sheet
with the same product type number(s) and title. A short data sheet is intended
for quick reference only and should not be relied upon to contain detailed and
full information. For detailed and full information see the relevant full data
sheet, which is available on request via the local NXP Semiconductors sales
office. In case of any inconsistency or conflict with the short data sheet, the
full data sheet shall prevail.
19.3 Disclaimers
General — Information in this document is believed to be accurate and
reliable. However, NXP Semiconductors does not give any representations or
warranties, expressed or implied, as to the accuracy or completeness of such
information and shall have no liability for the consequences of use of such
information.
Right to make changes — NXP Semiconductors reserves the right to make
changes to information published in this document, including without
limitation specifications and product descriptions, at any time and without
notice. This document supersedes and replaces all information supplied prior
to the publication hereof.
Suitability for use — NXP Semiconductors products are not designed,
authorized or warranted to be suitable for use in medical, military, aircraft,
space or life support equipment, nor in applications where failure or
malfunction of a NXP Semiconductors product can reasonably be expected to
result in personal injury, death or severe property or environmental damage.
NXP Semiconductors accepts no liability for inclusion and/or use of NXP
Semiconductors products in such equipment or applications and therefore
such inclusion and/or use is at the customer’s own risk.
Applications — Applications that are described herein for any of these
products are for illustrative purposes only. NXP Semiconductors makes no
representation or warranty that such applications will be suitable for the
specified use without further testing or modification.
Limiting values — Stress above one or more limiting values (as defined in
the Absolute Maximum Ratings System of IEC 60134) may cause permanent
damage to the device. Limiting values are stress ratings only and operation of
the device at these or any other conditions above those given in the
Characteristics sections of this document is not implied. Exposure to limiting
values for extended periods may affect device reliability.
Terms and conditions of sale — NXP Semiconductors products are sold
subject to the general terms and conditions of commercial sale, as published
at http://www.nxp.com/profile/terms, including those pertaining to warranty,
intellectual property rights infringement and limitation of liability, unless
explicitly otherwise agreed to in writing by NXP Semiconductors. In case of
any inconsistency or conflict between information in this document and such
terms and conditions, the latter will prevail.
No offer to sell or license — Nothing in this document may be interpreted or
construed as an offer to sell products that is open for acceptance or the grant,
conveyance or implication of any license under any copyrights, patents or
other industrial or intellectual property rights.
19.4 Trademarks
Notice: All referenced brands, product names, service names and trademarks
are the property of their respective owners.
20. Contact information
For additional information, please visit: http://www.nxp.com
For sales office addresses, send an email to: salesaddresses@nxp.com
SAF7741_7
Product data sheet
© NXP B.V. 2010. All rights reserved.
Rev. 07 — 28 April 2010
81 of 83
SAF7741HV
NXP Semiconductors
Dual IF car radio and audio DSP (N1F)
21. Contents
1
General description . . . . . . . . . . . . . . . . . . . . . . 1
1.1
Radio processing . . . . . . . . . . . . . . . . . . . . . . . 1
1.2
Audio processing . . . . . . . . . . . . . . . . . . . . . . . 1
2
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
2.1
Hardware features . . . . . . . . . . . . . . . . . . . . . . 2
2.2
Software Features . . . . . . . . . . . . . . . . . . . . . . 3
3
Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
4
Ordering information . . . . . . . . . . . . . . . . . . . . . 3
5
Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 4
6
Pinning information . . . . . . . . . . . . . . . . . . . . . . 6
6.1
Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
6.2
Pin description . . . . . . . . . . . . . . . . . . . . . . . . 10
7
Functional description . . . . . . . . . . . . . . . . . . 11
7.1
Radio subsystem . . . . . . . . . . . . . . . . . . . . . . 11
7.1.1
IFADCs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
7.1.1.1
TEF6730 tuner compatibility mode . . . . . . . . . 12
7.1.2
Primary decimation chain . . . . . . . . . . . . . . . . 12
7.1.2.1
PDC Input . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
7.1.2.2
Input decimation . . . . . . . . . . . . . . . . . . . . . . . 13
7.1.2.3
Shift-to-baseband mixer . . . . . . . . . . . . . . . . . 13
7.1.2.4
Mixer output decimation . . . . . . . . . . . . . . . . . 14
7.1.2.5
Gain control . . . . . . . . . . . . . . . . . . . . . . . . . . 14
7.1.2.6
Stepped gain amplitude . . . . . . . . . . . . . . . . . 15
7.1.2.7
Step-response waveform . . . . . . . . . . . . . . . . 15
7.1.2.8
Step-response timing . . . . . . . . . . . . . . . . . . . 16
7.1.2.9
Perfect step compensation . . . . . . . . . . . . . . . 16
7.1.2.10 Non-perfect step compensation . . . . . . . . . . . 16
7.1.2.11 AGC linear gain . . . . . . . . . . . . . . . . . . . . . . . 16
7.1.2.12 IF signal level detection . . . . . . . . . . . . . . . . . 17
7.1.2.13 AGC output decimation . . . . . . . . . . . . . . . . . 17
7.1.2.14 IQC stage . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
7.1.2.15 PDC output . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
7.1.2.16 LD interface . . . . . . . . . . . . . . . . . . . . . . . . . . 19
7.1.3
Digital radio interface . . . . . . . . . . . . . . . . . . . 20
7.1.4
RGP DAC . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
7.1.4.1
TEF6730 tuner compatibility . . . . . . . . . . . . . . 21
7.1.5
Radio Data System demodulator/decoder . . . 21
7.1.5.1
General description . . . . . . . . . . . . . . . . . . . . 21
7.1.5.2
RDS I/O modes . . . . . . . . . . . . . . . . . . . . . . . 22
7.1.5.3
RDS timing of clock and data signals in DAVD
mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
7.1.5.4
RDS bit buffer . . . . . . . . . . . . . . . . . . . . . . . . . 23
7.1.5.5
RDS demodulator . . . . . . . . . . . . . . . . . . . . . . 24
7.1.6
8Fs I2S interface . . . . . . . . . . . . . . . . . . . . . . . 24
7.1.7
Tuner I2S interface . . . . . . . . . . . . . . . . . . . . . 25
7.1.8
Output multiplexer . . . . . . . . . . . . . . . . . . . . . 25
7.1.9
Software radio user flags . . . . . . . . . . . . . . . . 26
7.1.9.1
7.1.9.2
7.2
7.2.1
7.2.1.1
7.2.2
7.2.3
7.2.4
7.2.4.1
7.3
7.3.1
7.3.2
7.3.3
7.3.4
7.4
7.4.1
7.4.1.1
7.5
7.6
7.6.1
7.6.2
7.6.3
7.6.3.1
7.6.3.2
7.7
7.7.1
7.7.2
7.7.3
7.8
7.8.1
7.8.2
7.8.2.1
7.8.3
37
7.8.4
7.8.5
7.8.6
7.8.7
7.8.8
7.8.8.1
7.8.9
8
9
10
10.1
11
12
EPICS flag generator . . . . . . . . . . . . . . . . . . .
Flag overview. . . . . . . . . . . . . . . . . . . . . . . . .
Audio subsystem . . . . . . . . . . . . . . . . . . . . . .
Input section. . . . . . . . . . . . . . . . . . . . . . . . . .
Analog audio input paths . . . . . . . . . . . . . . . .
Signal flow of the analog audio input . . . . . . .
Realization of the common mode inputs . . . .
Audio ADC decimator paths (DAD) . . . . . . . .
Functional description . . . . . . . . . . . . . . . . . .
Audio Digital-to-Analog (ADAC) conversion. .
Functional description . . . . . . . . . . . . . . . . . .
Digital filters . . . . . . . . . . . . . . . . . . . . . . . . . .
Noise shaper . . . . . . . . . . . . . . . . . . . . . . . . .
DAC (4-bit SDAC) . . . . . . . . . . . . . . . . . . . . .
Digital audio I/O . . . . . . . . . . . . . . . . . . . . . . .
I2S inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . .
General description of the SPDIF inputs . . . .
Host I2S I/O . . . . . . . . . . . . . . . . . . . . . . . . . .
ADSP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
ADSP user flags. . . . . . . . . . . . . . . . . . . . . . .
ADSP digital I/O inteface . . . . . . . . . . . . . . . .
ADSP-TDSP1E interface . . . . . . . . . . . . . . . .
Communication protocol example . . . . . . . . .
Software interface description . . . . . . . . . . . .
Sample-rate convertor DSP (SDSP) . . . . . . .
Function . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Flags . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DIO of the SDSP . . . . . . . . . . . . . . . . . . . . . .
Common system descriptions . . . . . . . . . . . .
Oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Voltage regulator . . . . . . . . . . . . . . . . . . . . . .
Power dissipation of the external transistor . .
Clocking strategy . . . . . . . . . . . . . . . . . . . . . .
Generation of the DSP and other clocks . . . .
DSP PLL description . . . . . . . . . . . . . . . . . . .
Audio PLL details . . . . . . . . . . . . . . . . . . . . . .
Tuner clock generation circuit . . . . . . . . . . . .
RESET sequence . . . . . . . . . . . . . . . . . . . . .
I2C interface . . . . . . . . . . . . . . . . . . . . . . . . . .
I2C switch . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Watchdog (WDOG) . . . . . . . . . . . . . . . . . . . .
I2C memory map and bit definitions . . . . . . .
Application diagrams . . . . . . . . . . . . . . . . . . .
Limiting values . . . . . . . . . . . . . . . . . . . . . . . .
Electrical limiting values. . . . . . . . . . . . . . . . .
Recommended operating conditions . . . . . .
Thermal characteristics . . . . . . . . . . . . . . . . .
28
28
29
29
30
30
31
34
34
35
35
36
36
36
37
37
39
40
40
40
42
44
45
46
46
46
46
47
49
49
50
50
51
53
53
54
55
56
57
57
57
57
59
61
61
61
61
continued >>
SAF7741_7
Product data sheet
© NXP B.V. 2010. All rights reserved.
Rev. 07 — 28 April 2010
82 of 83
SAF7741HV
NXP Semiconductors
Dual IF car radio and audio DSP (N1F)
12.1
12.2
13
13.1
13.2
14
14.1
14.2
14.3
14.4
14.4.1
14.5
14.6
14.7
14.8
14.9
14.10
14.11
14.12
15
16
17
18
19
19.1
19.2
19.3
19.4
20
21
Thermal considerations in choosing a package . .
61
Thermal considerations in choosing a package for
the SAF7741HV production chip . . . . . . . . . . 63
Static characteristics. . . . . . . . . . . . . . . . . . . . 63
Supply currents. . . . . . . . . . . . . . . . . . . . . . . . 63
DC characteristics . . . . . . . . . . . . . . . . . . . . . 64
Dynamic characteristics . . . . . . . . . . . . . . . . . 65
RDS electrical specification . . . . . . . . . . . . . . 65
Digital radio output . . . . . . . . . . . . . . . . . . . . . 66
IIS timing specification . . . . . . . . . . . . . . . . . . 67
I2C electrical specifications. . . . . . . . . . . . . . . 68
I2C timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
SPDIF . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
Audio ADC . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
IFADC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70
Voltage regulator. . . . . . . . . . . . . . . . . . . . . . . 71
Audio DAC (ADAC) . . . . . . . . . . . . . . . . . . . . 71
RGPDAC . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
Tuner clock generator. . . . . . . . . . . . . . . . . . . 73
Oscillator. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
Package outline . . . . . . . . . . . . . . . . . . . . . . . . 75
Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . . 77
References . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
Revision history . . . . . . . . . . . . . . . . . . . . . . . . 80
Legal information. . . . . . . . . . . . . . . . . . . . . . . 81
Data sheet status . . . . . . . . . . . . . . . . . . . . . . 81
Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81
Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . 81
Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . 81
Contact information. . . . . . . . . . . . . . . . . . . . . 81
Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82
Please be aware that important notices concerning this document and the product(s)
described herein, have been included in section ‘Legal information’.
© NXP B.V. 2010.
All rights reserved.
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: salesaddresses@nxp.com
Date of release: 28 April 2010
Document identifier: SAF7741_7