Cypress Non-Burst-Mode Parallel NOR Flash Memory – Layout

Cypress Non-Burst-Mode Parallel NOR Flash Memory – Layout Guide for PCBs
Authors: Ume sh Pai naik, Siew Pin Woo, a nd Be njam in He intz
Associate d Pa rt Familie s: S29AS -J, S 29AL-J, S 29JL-J, S 29P L-J, S 29GL-N, S 29GL-P,
S29GL-S, a nd S 29GL-T
Rela ted Appli ca ti on Note s: AN98508, AN201383, and AN211622
AN216200 discusses printed circuit board (PCB) layout recommendations to improve signal integrity and system
performance when using Cypress non-burst-mode parallel NOR Flash memory.
This document provides general design recommendations for a PCB utilizing Cypress non-burst-mode parallel NOR
Flash Memory products. These guidelines include recommendations for both signal routing and power delivery to the
In general, to achieve the best performance, the PCB design should provide an impedance- and loss-controlled
environment, support a low-impedance power delivery system, and control electromagnetic interference (EMI).
This document serves as an initial reference for PCB designs using Cypress non-burst-mode parallel NOR Flash
products. It does not eliminate the need to perform signal integrity and power delivery simulations . Use Cypressprovided IBIS models as well as IBIS models from controller vendors for signal timing and crosstalk simulations. You
should verify actual signal characteristics empirically on prototype and validation build units.
If a design cannot meet the recommendations provided herein, perform detailed simulations to determine whether
deviations from the recommendations would affect bus performance.
Non-Burst-Mode Parallel NOR Flash Signal Description
Cypress non-burst-mode parallel NOR Flash products are available in single-die-per-package and dual-die-perpackage options . In both options, a single chip enable control input (CE#) enables all die within the package. Table
1 provides a summary with descriptions of all I/Os on the Cypress non-burst-mode parallel NOR Flash memory
device. Figure 1 presents a simplified signal connection diagram between the Cypress Flash Memory and the host
controller. Note that Table 1 and Table 2 summarize the I/Os found on all Cypress non-burst-mode parallel NOR
Flash devices and may not reflect an individual device. See product-specific datasheets, listed in Section 7, to
determine the I/Os for a particular device and for additional information regarding their function and operation.
Table 1. I/O Descriptions and PCB Connection Recommendations
Hardw are Reset. At V IL (Input Low Voltage), causes the device to reset control logic to
its standby state, ready for reading array data.
Chip Enable. At V IL, selects the device for data transfer w ith the host controller.
Output Enable. At V IL, causes outputs to be actively driven. At V IH (Input High Voltage),
causes outputs to be high impedance (HI-Z).
Write Enable. At V IL, indicates data transfer from host to device. At V IH, indicates data
transfer is from device to host.
Address inputs.
Data inputs and outputs.
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Cypress Non-Burst-Mode Parallel NOR Flash Memory – Layout Guide for PCBs
DQ15: Data inputs and outputs.
A-1: Least signific ant bit of the address input in byte mode.
Write Protect. At V IL, disables program and erase functions in a sector of the device. At
V IH, the sector is not protected. At VHH (Voltage for ACC Program Acceleration),
automatically places device in unlock bypass mode and supports accelerated
programming on devices that support it. WP# has an internal pull up; w hen
unconnected WP# is at V IH.
Output – open
Ready/Busy. Indicates whether the execution of an embedded algorithm is in progress.
Selects data bus width.
Pow er Supply
Core pow er supply.
Pow er Supply
Input/Output pow er supply.
Pow er Supply
Pow er supplied ground.
No Connect
Not connected internally, the pin/ball location may be used in the PCB as part of a
routing channel.
No Connect
Reserved for future use. Not currently connected internally; however, the pin/ball
location should be left unconnected and unused as a PCB routing channel for future
compatibility. The pin/ball may be used by a signal in the future.
Do not use; reserved by Cypress.
Figure 1. Host to Non-Burst-Mode Parallel NOR Flash Simplified Interface Connections
The signals listed in Table 1 form five distinct signal groups: data, address, read/write control, oth er controls, and
power/ground. During signal routing, you should give priority to the signal groups to ensure they maintain a high
quality signal. Table 2 ranks the signal integrity priority of the five signal groups, where one represents the highest
priority and four represents the lowest.
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Cypress Non-Burst-Mode Parallel NOR Flash Memory – Layout Guide for PCBs
Table 2. Signal Integrity Priority of Signal Groups
Signal Group
Pin Names
Signal Integrity Priority
Amax-A0, A-1
Read/Write Control
CE#, OE#, WE#
Other Controls
Pow er/Ground
See Section 5
The signal integrity priority denotes the importance of treating that particular signal group as a high -speed signal.
Note that the signal integrity priority does not necessarily dictate the order of signal routing.
Signal Breakout, Routing Strategy, and Impedance Control
Cypress recommends the following actions to improve signal integrity and impedance control.
Break out all signals on the top PCB layer, assuming that the second layer is a ground plane. This will allow
better impedance control and smaller impedance mismatch between the breakout traces and traces outside the
breakout area.
Connect VCC and VIO to the nearest power plane through vias that are located as close to the target power
ball/pin as possible. Traces from the land pad to the vias should be as thick as possible.
Connect VSS to the nearest ground plane through vias that are located as close to the target ground ball/pin as
possible. Traces from the land pad to the vias should be as thick as possible.
Use a smaller trace width (between 4-mil and 6-mil) and space adjacent traces approximately three trace widths
apart to achieve a 50-ohm impedance. The impedance of data traces depends on the PCB stack-up and the
trace width. Use either Microstrip or Stripline interconnects so long as the continuous trace impedance is 50
ohms (±10 percent) throughout the routing path.
Use buried vias and as few vias as possible to reduce impedance discontinuities due to additional capacitive
loading arising from through-hole vias. An y via attached to a trace will alter the signal delay of that trace.
Route all signal groups on the same signal layer and in the same signal configuration, either all microstrip or all
General Signal Routing Guidelines
The following guidelines define the recommended trace width and trace spacing, total length limitation, and lengthmatching requirements to achieve optimal signal integrity and timing margins. These recommendations assume
point-to-point routing between the host controller and the Cypress non-burst-mode parallel NOR Flash memory for
simplicity. If this is not the case, you should first select the topology type to follow (star, T, or daisy chain). Cypress
recommends star or T topology with the appropriate termination resistors determined from IBIS simulations.
Consider performing signal integrity simulations using Cypress -provided IBIS models to determine guidelines tailored
to your specific application.
Determine the exact values of signals trace width and trace spacing based on the trace impedance requirement.
Make the VSS plane serve as a primary reference, or return path, for all signals. The power layer should only
serve as a secondary signals reference option where a solid, continuous ground reference is present.
Avoid gaps or voids in reference planes to minimize or eliminate return current discontinuity.
Avoid routing traces at the edge of the reference plane.
When routing data signals , route the longest signals first. This allows adjustment for signals with shorter lengths.
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Cypress Non-Burst-Mode Parallel NOR Flash Memory – Layout Guide for PCBs
Isolate the ground return path of analog signals from digital noise whenever possible.
Keep all recommended signal routing lengths equal to the distance from package pin (source) to package pin
(destination) by considering package length compensation.
Use signal integrity tools to estimate actual trace velocities and path delays to validate the electrical properties
depending on the dielectric material. Cypress determines electrical properties of signal routing by assuming the
dielectric material is FR4. With this assumption, 1-inch equals approximately166-ps.
Signal Routing Geometry Constraints
4 .1 .1
Ma x im um T ota l Le ng th
4 .1 .2
The total load capacitance, which directly affects signal integrity, defines the absolute maximum length of signals
with respect to their reference plane.
 The total load capacitance should remain below 30 pF.
 Total load capacitance includes the following:
 Total trace length capacitance (~3.3 pF/inch with FR4 assumption),
 Ma ximum pin capacitance associated with any parasitic capacitance of connected devices such as
connectors and series resistors
 Ma ximum pin capacitance of the controller package.
The Read/Write operation timing requirements bound the total length of address, control, and data signal routing
lines, as stated in the product datasheet. Perform a channel timing simulation to ensure the system meets these
critical timing requirements . For example, address and data maximum lengths should ensure the required tACC
and tRC parameters for back-to-back read operations.
Best practice is to begin with the AC timing equations for key timing parameters provided on the Cypress nonburst-mode parallel NOR Flash and controller datasheets for the Flash interface.
Le n gt h Ma tc h in g
Length matching refers to the trace lengths from the memory package pin to the signal pin of the controller.
Length matching must include the effective electrical length of any vias.
Cypress recommends routing WE# first. WE# will determine the length mismatch requirements with CE#
through tCH, with address through tALS/t ALH, and with data through tDS/tDH.
Table 3 provides signal skew recommendations for the various signal groups. It is important to note the signal
polarities (rising edge and falling edge triggers) as well as the lead and lag timing to determine whether a specific
control signal should always lead or lag compared to another signal or Data bus.
Table 3. Length Match Recommendations for Signal Groups
Signal Group
4 .1 .3
Length Match Recommendation
± 500 mils
± 500 mils
Data to Read/Write Control
± 500 mils
Address to Read/Write Control
± 500 mils
The length of WP#, RY/BY#, and RESET# should be as small as possible. Avoid routing these signals adjacent
to higher-frequency signals to minimize noise from crosstalk.
Si gna l S pa c i n g C o ns tr a in ts
The center-to-center trace spacing should be greater than three times 'H' within a signal group is , where H is the
dielectric height between the signal and ground reference layer.
The center-to-center trace spacing between signal groups should be greater than three times the trace width. In
addition, the center-to-center trace spacing between Flash signals and other interface signals should be greater
than three times the trace width as well. Figure 2 provides a visualization of the recommended signal trace
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Cypress Non-Burst-Mode Parallel NOR Flash Memory – Layout Guide for PCBs
Figure 2. Recommended Signal Trace Spacing on the PCB
4 .1 .4
Te r m i na t i on
You should review the drive strength/impedance of the controller I/O as well as transmission line routing to
determine whether series termination is required on these lines. Drive strength for all three pressure, volume,
and temperature (PVT) (typical, minimum, and maximum corners) can be determined by reviewing the IBIS
IV/VT curves.
Refer to the appropriate Cypress product datasheet, listed in Section 7, for the RY/BY# pull-up resistor value.
Power Delivery Guidelines
The following power delivery guidelines will help ensure that there are no power issues within the system.
Connect each VSS pin/ball to a solid ground plane with its own unique via to improve IR drop.
Connect VCC pins/balls to a supply plane with its own unique via to improve IR drop.
Connect VIO pins/balls to a separate VIO plane through more than one via from the breakout layer.
At no point should VIO be greater than VCC +200-mV; therefore, you must keep these supply planes as noise-free
as possible. In addition, the regulator set points and tolerances should be selected with this restriction in mind as
there could be varying DC drops from the regulator pin to the VCC and VIO supply near the memory device.
Gaps between power planes should be at least 20 mil, where possible. A gap of at least 80 mil should exist
between power islands on the same layer, if possible. The air gap between power islands must be greater than
40 mil, preferably as much as 100 mil.
Power islands, such as VCC and VIO islands, should be at least 250-mil wide at the narrowest point to avoid
Maintain a minimum trace width of 20 mil for all supply traces , except at the package breakout area where vias
tie the supply to the nearest supply plane. Route the supply and ground traces (or planes) close to each other to
avoid large inductive loops.
Cypress recommends keeping the supply trace lengths less than or equal to 400-mil and keeping the trace
widths greater than or equal to 20 mil.
Utilize trace widths greater than 20 mil to maintain low impedance from the voltage regulator to the Flash voltage
supply pins/balls as well as from the voltage regulator to the controller Flash I/F supply pins /balls.
It is possible that voltage regulator will not be on the same PCB as the Flash package when using a module
configuration. In this case, you should maintain the lowest possible impedance on traces to VCC, VIO , and VSS.
Wider traces can help to ensure a lower impedance.
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Cypress Non-Burst-Mode Parallel NOR Flash Memory – Layout Guide for PCBs
If there is a connector between the Host Controller and the Cypress non-burst-mode parallel NOR Flash,
Cypress recommends the use of a G: S/P: G type connector configuration where 'S' refers to signal, 'G' refers to
GND, and 'P' refers to VCC.
It is best to add VCC, VIO , and GND test points as close as possible to each Flash package and next to the
voltage regulator. These test points will allow the measurement of VCC-GND and VIO-GND waveforms at both
VR M and the package.
Decoupling Capacitor Recommendations
Place the PCB decoupling capacitors as close to the package as possible.
Select decoupling capacitors that have low equivalent series inductance (ESL) and equivalent series resistance
VCC and GND trace routing from the capacitor should be as wide as possible to avoid inductive and resistive
A minimum two 1-uF 0402 ceramic capacitors should be placed between VCC and GND near each side of the
In additional to these decoupling capacitors ; two 0.1-uF 0402 ceramic capacitors should be placed, as close to
the package as possible, between VCC and GND and another two, as close as possible, between VIO and GND.
Cypress recommends using X7R or X5R capacitors with a rated voltage greater than or equal to at least two
times VCC max.
The decoupling capacitor trace length should remain short and should have a unique via, not shared with
another decoupling capacitor. Figure 3 presents good and poor examples of decoupling capacitor routing
Figure 3. Decoupling Capacitor Routing Techniques: (i) Poor Routing Examples, (ii) Good Routing Examples
Test Points and Oscilloscope Measurements
You should perform signal quality, timing, and power delivery characterization using industry-standard digital signal
evaluation techniques. The statements below outline a number of those techniques.
Test points should be as close as possible to the controller and Cypress non-burst-mode parallel NOR Flash
memory package pins for DQmax-DQ0 and RY/BY# signals. In addition, the test points should be located as
close as possible to the non-burst-mode parallel NOR Flash memory package pin for the remaining the signals.
Measure meaningful signals as close to the Flash memory as possible when the controller is driving. When the
Flash memory device is driving, the opposite is true.
While creating test pad, the stub (extra inductance and capacitance) resulting from the test pad should be
minimized. It is better to probe at the breakout via rather than creating test pad stubs. In addition, in the case of
4-layer PCBs with through-hole vias, probe signals at the bottom of the PCB on the through-hole vias if possible.
Document No. 002-16200 Rev. *A
Cypress Non-Burst-Mode Parallel NOR Flash Memory – Layout Guide for PCBs
While performing scope measurements , use a 3-GHz or greater bandwidth scope and low-impedance probes.
This will provide a more accurate representation of the waveform transition (such as the rising and the falling
portion of the waveform).
Always measure VCC-VSS and VIO-VSS at the controller, the voltage regulator, next to the connector (either side),
and at the Flash memory. This needs to be performed prior to making any signal measurements to ensure that
the supply is not noisy, which will affect the signal timing. In addition, these measurements establish the IR drop
from regulator to controller or the regulator to the Flash device.
While measuring signals, it is a good idea to set the trigger on the most common switching signals , such as
Related Documents
Table 4. Cypress Non-Burst-Mode Parallel NOR Flash Product Specific Datasheets.
Fam ily
3.0V GL-S Flash Memory Family, S29GL01GS 1 Gbit, S29GL512S 512 Mbit, S29GL256S 256 Mbit,
S29GL128S 128 Mbit Datasheet
3.0V GL-S Flash Memory, S29GL064S 64 Mbit Datasheet
S70GL02GS 2 Gbit (256 Mbyte) 3.0V Flash Memory Datasheet
S29GL064N, S29GL032N 64 Mbit, 32 Mbit 3 V Page Mode MirrorBit Flash Datasheet
S29GL01GT 1 Gbit and S29GL512T 512 Mbit Parallel NOR Flash Datasheet
S29GL01GP, S29GL512P, S29GL256P, S29GL128P 1 Gbit, 512, 256, 128 Mbit, 3 V, Page Flash w ith 90 nm
MirrorBit Process Technology Datasheet
S70GL02GP, 2 Gbit, 3.0 Volt-only Page Mode, S70GL- P MirrorBit® Flash Memory Datasheet
S29GL512N, S29GL256N, S29GL128N 512, 256, 128 Mbit, 3 V, Page Flash Featuring 110 nm MirrorBit
PL Family
S29PL-J 128/128/64/32 Mbit (8/8/4/2M x 16-Bit) V, Flash with Enhanced VersatileIO™ Datasheet
JL Family
S29JL064J 64 Mbit (8M x 8-Bit/4M x 16-Bit), 3 V, Simultaneous Read/Write Flash Datasheet
AL Family
S29AL016J 16 Mbit (2 M x 8-Bit/1 M x 16-Bit), 3 V, Boot Sector Flash Datasheet
AS Family
S29AS016J 16 Mbit (2 M x 8-Bit/1 M x 16-Bit), 1.8 V Boot Sector Flash Datasheet
GL Family
Document No. 002-16200 Rev. *A
Cypress Non-Burst-Mode Parallel NOR Flash Memory – Layout Guide for PCBs
Document History
Document Title: AN216200 – Cypress Non-Burst-Mode Parallel NOR Flash Memory – Layout Guide for PCBs
Document Number: 002-16200
Orig. of
Subm ission
New Application Note
Updated logo and copyright.
Description of Change
Document No. 002-16200 Rev. *A
Cypress Non-Burst-Mode Parallel NOR Flash Memory – Layout Guide for PCBs
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