Lecture 13: Introduction of Microcontroller Hardware

Objectives
EE 3170 Microcontroller
Applications
Lecture 13: Introduction to Microcontroller Hardware (Part
II- Input/Output)
- Miller §6.1 - §6.12
†
Describe the I/O ports of the 6811
†
Explain the basic parts of I/O programming
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Give examples of I/O device drivers
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Understand simple I/O programs
Based on slides for ECE3170 by Profs. Davis, Kieckhafer, Tan, and Cischke
EE3170/CC/Lecture#12-Part II
1
I/O Hardware Model
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68HC11 I/O Organization
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Specific Port Examples
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†
†
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Input devices get information from the
external world, often through sensors.
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Output devices
Observations
concept and requirements
generic response to an interrupt request
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Interrupts in the 68HC11
„
„
†
An embedded system uses input/output
devices to connect with the real world.
Interrupt-Driven I/O
„
†
†
PORTB
PORTC
Example of Polled I/O Operation
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2
How Does an Embedded System Interact with the
World?
Input/Output Architectures
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EE3170/CC/Lecture#13-Part II
hardware setup
response to an interrupt request
„
control physical systems or
display information.
Example of Interrupt Driven I/O
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I/O Hardware Model
„
You’re probably familiar with device drivers for your home computer.
EE3170/CC/Lecture#13-Part II
PORT B
†
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†
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†
„
„
SS
SCK
MOSI
MISO
TxD
RxD
R/W
AS
1
PORT E
EXPANDED MODE
EE3170/CC/Lecture#13-Part
II
Figure 1-1 Block Diagram
†
Low order address bits (A7…A0)
Data bits (D7…D0)
6
Most embedded microprocessors, including the
6811, are memory mapped.
This means that each I/O port has one or more
dedicated “memory”
addresses.
M68HC11
GENERAL DESCRIPTION
MOTOROLA
Lines are labeled: (A15…A8, AD7…AD0)
†
Data can then be written to the address for sending to1-3
the I/O device (output) or
Data can be read from the address for input to the
processor.
REFERENCE
MANUAL
„
Issue address during 1st half of a cycle
Transfer data during 2nd half of the same cycle
„
Transparent to the programmer
Lower performance solution
Clock period is long enough to include both phases in a single cycle
EE3170/CC/Lecture#13-Part II
CONTROL
PORT D
CIRCUITRY ENCLOSED BY DOTTED LINE IS EQUIVALENT TO MC68HC24.
This is a common technique to save lines & pins
„
A/D CONVERTER
What’s an I/O Port Address?
Bus usage within one bus cycle is time-multiplexed
„
SINGLE CHIP MODE
5
Some addr. & data bits share the same physical lines
†
SCI
CONTROL
PORT C
PORT A
Bus Architecture: A Side Note
†
SPI
PE7/AN7
PE6/AN6
PE5/AN5
PE4/AN4
PE3/AN3
PE2/AN2
PE1/AN1
PE0/AN0
Device drivers are software routines that let higher level
software use an I/O device.
STROBE AND HANDSHAKE
PARALLEL I/O
PD1/TxD
PD0/RxD
†
ADDRESS/DATA
PD5/SS
PD4/SCK
PD3/MOSI
PD2/MISO
„
BUS EXPANSION
ADDRESS
TIMER
SYSTEM
STRB
STRA
„
VRH
VRL
256 BYTES RAM
R/W
AS
„
A device attached to the I/O port
“Peripheral” to the computer
generates data and sends it to a port AND/OR
reads data from the port, and acts on it
VDD
VSS
512 BYTES EEPROM
PC7
PC6
PC5
PC4
PC3
PC2
PC1
PC0
„
RESET
CPU
A7/D7
A6/D6
A5/D5
A4/D4
A3/D3
A2/D2
A1/D1
A0/D0
I/O Device =
XIRQ
INTERRUPT LOGIC
PB7
PB6
PB5
PB4
PB3
PB2
PB1
PB0
†
PERIODIC INTERRUPT
„
IRQ/
8 KBYTES ROM
COP
„
E
OSCILLATOR
CLOCK LOGIC
MODE
CONTROL
A set of pins for data input or output
Maybe a register attached to the pins
The control protocol for the pins
PULSE ACCUMULATOR
„
XTAL EXTAL
A15
A14
A13
A12
A11
A10
A9
A8
I/O ports are the parts of a microcomputer that connect to its
environment.
MODB/
VSTBY
PA7/PAI/OC1
PA6/OC2/OC1
PA5/OC3/OC1
PA4/OC4/OC1
PA3/OC5/OC1
PA2/IC1
PA1/IC2
PA0/IC3
†
I/O Ports
MODA/
LIR
7
†
The frame of reference is the computer.
„
„
Input is to the computer from a device.
Output is from the computer to a device.
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I/O Hardware Model
†
I/O Organization
Input Port:
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†
68HC11 uses Memory Mapped I/O =
„
receives data from the incoming pins
makes it available to the data bus
generally does not latch the data
†
†
†
†
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Output Port:
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†
†
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value remains constant until a new value is output
Serial I/O port ⇒ moves data at 1bit per transfer
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Parallel I/O Port ⇒ moves data in word width chunks
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9
Typically 8-16 bits in parallel
68HC11 parallel I/O ports are 8-bits wide
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Input Port
Typical I/O Port
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input only
output only
programmable (bidirectional)
†
„
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A data register (latched or unlatched)
A command/status register
An I/O register can be
„
receives data from the data bus
makes it available on the outgoing pins
usually has a latch to hold the data for the device
It recognizes an address as itself
It transfers data on the data bus
It responds to Load and Store commands
An I/O Port can have more than 1 register
„
†
Each I/O port behaves like a single word of memory
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Output Port
Command & Status Register
†
This C/S register is part of the I/O port
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Usually one bit of it is a ready flag.
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The c/s register has its own address
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A different address than the data port
Purposes of C/S register
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Allow processor to read status info on the port
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Allow the processor to write commands to the port
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To alter the way the port behaves
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68HC11 – E “family” I/O Ports
68HC11 I/O Organization
†
e.g. Ready, Error, etc
68HC11 has 5 I/O ports
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PORTA -- 3 input, 4 output, and 1 bidirectional pin
„
„
PORTB -- 8 output pins
PORTC -- 8 bidirectional pins
PORTD -- 6 bidirectional pins
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PORTE -- 8 input pins
†
„
†
†
†
also used for timer and pulse accumulator I/O
also used for asynchronous serial comm
also used for Analog to Digital (A/D) conversion
can handle analog voltage inputs
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I/O Registers
I/O Memory Mapping Addresses
†
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„
†
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†
a 64-byte block addresses
at $1000 … $103F
The I/O port registers are a subset of that space
„
consisting of 11-bytes
not all at contiguous addresses in the block
We will consider PORTB and PORTC in this chapter
„
„
They are the simplest and most general purpose
Others are considered in later chapters
EE3170/CC/Lecture#13-Part II
Memory-Mapped I/O
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All built-in I/O and control regs are mapped into
Name
Address
Function
PORTA
$1000
Timer and Counter System
PORTB
$1004
Parallel Output
PORTC
$1003
Parallel Input/Output
PORTCL
$1005
PORTC Latch
PORTD
$1008
Serial Input/Output
PORTE
$100A
Analog-to-Digital Converters
PIOC
$1002
Parallel I/O Control
DDRC
$1007
Data Direction PORTC
DDRD
$1009
Data Direction PORTD
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PORTB
Parallel I/O Control Registers
†
Unidirectional 8-bit output port
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$1004 = PORTB Data Register’s Address
†
To do an output, simply store to $1004, e.g.
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†
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staa $1004
stab $1004
clr $1004
∗ Accumulator A → PORTB
∗ Accumulator B → PORTB
∗ $00 → PORTB
Details
„
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Output Pins hold a value until it is changed
At RESET, $00 → PORTB
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PORTC
PORTC Reg
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Programmable (bidirectional) 8-bit I/O port
†
†
Four Registers of Interest
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†
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0 = input pin,
1 = output pin
load from $1007 returns the last value stored
†
A store to an input pin is ignored
A load from an output pin returns last value stored
At RESET, $00 → PORTC
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PORTC Configuration Example:
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store to $1007 sets direction of each bit in PORTC
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†
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†
Data Direction Register for port C
†
Details
„
Defines the direction of individual pins in PORTC
„
∗ Accumulator A → PORTC
∗ PORTC → Accumulator A
DDRC Reg
The DDRC Register @ $1007
„
staa $1003
ldaa $1003
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DDRC Reg
†
„
†
Individual Pins can be configured as input or ouptut
To do an I/O ops, load or store @ $1003, e.g.
„
$1003 = PORTC = the data register
$1007 = DDRC = Data Direction Register for C
$1002 = PIOC = Parallel I/O Control register
$1005 = PORTCL = PORTC Latch register
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The PORTC Register @ $1003
ldaa
staa
#$F0
$1007
†
Stores $F0 = %1111,0000 into DDRC
†
Initializes PORTC such that
the current status of the PORTC pins
At Reset: $00 → DDRC (initializes PORTC as input)
„
„
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pins 7…4 = output pins
pins 3…0 = input pins
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PIOC Reg
†
The PIOC Register @ $1002
„
„
†
PORTCL Reg
†
An I/O port control register
Contains control bits for several ports
„
„
Sometimes it is necessary to latch an input
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PORTCL latches the contents of PORTC
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There is an external ready signal STRA = Strobe A
STAF is set on a change in the value of STRA
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†
Bit 7 = STAF bit = Status Flag bit
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The PORTC Latch Register @ $1005
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either rising edge or falling edge sensitive
†
„
Two step op: read PIOC, then read PORTCL, e.g.
†
EGA = 1 ⇒ STAF is rising edge sensitive
EGA = 0 ⇒ STAF is falling edge sensitive
EE3170/CC/Lecture#13-Part II
at the instant the STRA pin sets the STAF flag
Last detail: clearing the STAF flag in PIOC reg
Edge sensitivity is determined by Bit 1 = EGA bit
†
at the instant the input device presents it
†
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ldaa $1002
ldaa $1005
EE3170/CC/Lecture#13-Part II
Example: Figure 6-20
†
†
Details
Read Two Push-Button Switches
If both are closed, then light an LED, else turn it off
†
This is an asynchronous real-time application
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†
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†
Input Port is at address $4002
Output Port is at address $4003
Initial Conditions
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27
The input data is always “valid” (or meaningful)
Do not need a “ready” flag (or status register)
Read the two switches in real-time
Set or Clear the LED bit in real-time
Port Addresses
„
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Start with LED lit
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Flowchart for Program in Fig. 6-21
Key Bit-Manipulation Instructions
†
bclr address, mask
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„
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clear those bits of a mem word specified by the
mask
i.e. M[offset] ← M[offset] AND (mask)
Example:
†
†
†
†
EE3170/CC/Lecture#13-Part II
bset works the same to set the selected bits
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Bit Manipulation Instructions
30
Key Bit-Conditional Instructions
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brclr offset, X, mask, target
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„
„
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examines a memory word, M[X+offset]
If all bits selected by the mask byte are clear (= 0)
Then branch to the target address
In other words:
†
†
EE3170/CC/Lecture#13-Part II
M[offset] = 1101,0011
mask = 0100,0001 (select bits 6 and 0)
M[offset] ← (1101,0011) AND (1011,1110) =
(1001,0110)
31
IF
THEN
M[X=offset] AND mask = $00
Branch to Target
brset works the same if the selected bits are
set to 1
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Bit Conditional Instructions
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Why I/O Synchronization?
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†
I/O devices are typically much slower than processors
Can’t read from a device until it has the data ready
Can’t write to a device until it is ready to receive data
†
†
How: Two Forms of I/O Synch.
I/O Speed
„
usually when it is done processing the previous data
„
„
Polled I/O
„
„
„
†
„
Ready flag is connected to an “Interrupt” pin on proc.
When Pin = 1, the processor
†
device sets a 1-bit “ready” flag when it is ready
proc. waits for flag to be set before accessing the port
flag is cleared when proc. accesses the port
†
†
†
35
interrupts the current program
calls an Interrupt Service Routine (ISR) to access the port
then returns to the previous program
DMA (Direct Memory Access)
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EE3170/CC/Lecture#13-Part II
proc. enters a “polling loop” to read the ready flag
when the flag is set, then processor accesses port
processor ends up waiting for the device
Interrupt-Driven I/O
„
Processor must “synchronize” with I/O devices
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ISR supports Control of an independent bus master
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I/O Synchonization
†
I/O Synchronization is
determined by the
programming model
„
„
„
†
Polled I/O
Polled
Interrupt
DMA
I/O Synchronization is
constrained by interface
hardware between
CPU/Controller and I/O
Controller/Devices
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Polled I/O Example
Polled I/O Example
†
Program Function
„
„
User sets a number (0…F) with thumbwheel
User pushes the ready button
†
†
„
†
39
Sets STAF-bit in PiOC via STRA pin (rising edge)
Latches input value into PORTCL
Program loop continuously checks STAF bit of
PIOC
†
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Program reads PORTCL
Program outputs the input value to the display
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Polled I/O Example
Polled I/O Example
thumbwheel
/initialization
/copy thumbwheel
/initialization
//initialize PORTC
//read thumbwheel &
clear I/O flag
//set up PIOC
//position data
for output
/pushbutton
pushed?
N
/end
Y
//control display
/copy thumbwheel
to display
/end
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Polled I/O Example
†
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Polled I/O Example
Program of Figure 6-29
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Polled I/O Example
Observations about Polled I/O
†
Processor spends enormous amounts of
time waiting for the I/O device to be ready
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„
Human = seconds or tenths of seconds
Disk ≈ 10 ms for 1st word
†
„
Disk ≈ 0.1 ms between words
†
†
45
What Is Interrupt-Driven I/O?
†
†
„
„
†
CPU spends most of its time waiting for the device.
Solution:
„
Let device interrupt CPU when device is ready.
CPU drops what it was doing and services the port.
CPU returns to its original task.
„
46
†
Interrupt Request Pins (IRQ) on CPU
†
Interrupt Acknowledge Pins (IACK)
†
READY bit of port stat/com register is wired to an IRQ pin
†
CPU must check IRQ pins
†
Resembles a subroutine call
Done when device is ready
EE3170/CC/Lecture#13-Part II
EE3170/CC/Lecture#13-Part II
„
Interrupt Service Routine (ISR): routine that
services the I/O port
„
It is not doing useful work
What Hardware Do We Need for Interrupts?
Problem with polling:
„
@ 1GHz, 0.1 ms = 100,000 clock cycles
CPU spends all that time in the polling loop
„
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@ 1GHz, 10 ms = 10 million clock cycles
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checked between Instructions
CPU can ignore (mask) interrupt pins if an interrupt would be
inconvenient
„
Mask bit holds current mask status
„
Mask manipulation instructions
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How is Return from Interrupt Handled?
How Does Hardware Respond to an IRQ?
†
IF IRQ is masked, THEN ignore interrupt
†
ELSE
„ Identify the originator of the interrupt
„ Find the address of the ISR
„ Push the process state on the stack
†
†
†
„
†
Initiated by Return from Interrupt instruction
„
at end of Interrupt Service Routine
† 68HC11
Program Counter - address of next instruction to be fetched
Program Status - e.g. Condition Code register
Most CPUs don’t save general purpose registers
„ Takes a lot of time
„ Let the ISR push any registers it needs
= RTI
„
Undo all stack ops done by the interrupt
„
The next instruction the CPU fetches will be
the next instruction of the previous task.
PC ← Address of ISR routine
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Interrupts
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How Do We Know What Device Interrupted?
†
How to signal CPU
†
How to protect the
registers
STRB pulse high
Converting
in
background
doing something
†
Most CPU's have 2 - 8 IRQ pins
†
One pin usually Non-Maskable Interrupt (NMI)
„
read PIOC
usually for imminent disaster
doing something
†
Where to find the
subroutine
read PORTCL
doing something
†
reset STAF
How to come back
doing something
Remaining pins are prioritized (usually fixed priority)
„
usually more I/O devices than IRQ pins
„
may have simultaneous requests
„
must determine device that initiated IRQ
„
doing something
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51
then find address of the proper ISR
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How Do We Get the Address of the
Interrupting Device?
†
†
†
Static Vector Table (Table 7-2)
Static vector table or
Direct bus vectored interrupts or
Indirect bus vectored interrupts
†
Put address of ISR in a fixed memory location
†
Vector Table ≡ List of all ISR addresses
†
IRQ pin number points to Vector Table
†
Vector Table entry points to ISR
†
ISR can be anywhere in memory
†
All devices sharing one IRQ pin must use same ISR
†
CPU Hardware
† Fetches
vector table entry specified by pin number
that value into Program Counter (PC)
† Fetches 1st instruction of the ISR
† Loads
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Static Vector Table, p. 2
†
Example:
„
Number the IRQ pins
...
(0…N-1)
„
„
Assume :
†
Vector table starts @0000
†
1 stored address = 2 Bytes
...
Then:
†
is stored in M[2i:2i+1]
EE3170/CC/Lecture#13-Part II
Direct Bus Vectored Interrupts
0000
0001
0002
0003
2*i
2*i+1
2*(N-1)
2*(N-1) +1
ISR addr for IRQ pin i
54
†
Let the device send its ISR address to the
CPU
†
In response to IACK, device sends address
on data bus
†
CPU latches address into Program Counter
...
55
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Indirect Bus Vectored Interrupts
†
How Does the 6811 Handle Interrupts?
Device sends a pointer into the vector table
†
„
rather than actual address of ISR
„ think of it as a device I.D. number
„
†
Two interrupt Pins (active low)
„
†
CPU gets the actual address from the
vector table
IRQ -- maskable
XIRQ -- non-maskable
Device must latch its request
„
Done via a flag latch in the I/O port
Example: the STAF flag in the PIOC
„
Other external ports must implement their own latch
„
†
†
The most common approach, why?
†
†
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The Interrupt Process – request (Skipped)
Internal request
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„
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Pulse accumulator
Timer
SPI serial transfer
SCI serial system
Parallel I/O
1 - Global IRQ Enable
„
Bit 4 of CC register = I bit
„
Two instructions control the I bit
†
†
„
S X H I N Z V C
CLI ⇒ make I = 0 ⇒ enable IRQ
SEI ⇒ make I = 1 ⇒ disable IRQ
When an IRQ occurs,
†
†
†
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58
Enabling and Disabling Interrupts
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latch output is wired to IRQ
multiple devices can be Wire-ORed
EE3170/CC/Lecture#13-Part II
†
†
can be programmed to trigger an IRQ
hardware immediately pushes CCs
and disables IRQ to prevent infinite loop
ISR can enable IRQ by executing a CLI, if desired
IRQ will be automatically enabled upon Return
(when old CC is popped off stack)
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Hardware Response to IRQ
Enabling and Disabling Interrupts, p.2
†
2 - Enabling Individual I/O Port Flags
„ Each I/O port can disable its flag from initiating an
IRQ
„ For external ports it is up to the individual designer
„ For STAF flag in the PIOC it is controlled by STAI
bit
= 0 STAF interrupt is disabled
† STAI = 1 STAF interrupt is enabled
†
Save Process State
„
†
PC ← Address of ISR
„
†
†
†
„
can be enabled by ISR
automatically enabled on return from ISR
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IRQ-Driven I/O Example
Software Response to IRQ
†
IRQ Pin vector is in
M [FFF2:FFF3]
XIRQ Pin vector is in M [FFF4:FFF5]
RESET Pin vector is in M [FFFE:FFFF]
Disable IRQ
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61
Obtained from a static vector table in ($FFC0 - $FFFF)
†
† STAI
EE3170/CC/Lecture#13-Part II
PUSH: PC, CC, A, B, X, Y
ISR doesn’t have to save registers.
„
done by hardware
†
ISR should execute a CLI instruction to re-enable
IRQ as soon as it is safe to do so.
†
Return from Interrupt (RTI) instruction
„
Pops: Y, X, B, A, CC, PC
†
†
„
Popping PC returns to the previous task.
Popping CC
„ restores previous condition codes
„ restores previous IRQ enable bit
Result -- ISR leaves no residual effects on the task.
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IRQ-Driven I/O Example
†
IRQ-Driven I/O Example
IRQ ISR
Same Problem, Different Synchronization
„
„
User sets a number (0…F) with thumbwheel
User pushes the ready button (P.288)
† sets
STAF-bit in PIOC via STRA pin (rising edge)
input value into PORTCL
† Sets IRQ input: ← STAF Output
/initialization
† Latches
„
/valid STAF
interr?
thumbwheel
/copy thumbwheel
Program is Interrupted
/do something else
(something useful)
† ISR
reads PORTCL
† ISR outputs the input value to the display
† ISR returns to main program
/return to main
program
/end
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IRQ-Driven I/O Example
IRQ-Driven I/O Example
/copy thumbwheel
/initialization
//read thumbwheel &
clear I/O flag
//initialize PORTC
//position data
for output
//set up PIOC
/end
//control display
/end
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IRQ-Driven I/O Example
IRQ-Driven I/O Example
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IRQ Summary
†
IRQ advantages
„
„
„
†
Program can go about its business
† Doesn’t continuously poll ports
† Polling is a huge waste of CPU time
CPU services ports only when needed
Port management greatly simplified
IRQ Disadvantages
„
„
Main program execution time indeterminate
† depends on number and exact timing of IRQs
May make real-time deadlines harder to guarantee
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