3-17V 1A 3MHz Step-Down Converter in 3x3 QFN Package (Rev. B)

TPS62150, TPS62150A
TPS62151, TPS62152, TPS62153
www.ti.com
SLVSAL5B – NOVEMBER 2011 – REVISED JUNE 2013
3-17V 1A Step-Down Converter in 3x3 QFN Package
Check for Samples: TPS62150, TPS62150A, TPS62151, TPS62152, TPS62153
FEATURES
DESCRIPTION
1
•
•
•
•
•
•
•
•
•
•
•
•
•
•
TM
DCS-Control Topology
Input Voltage Range: 3 to 17V
Up to 1A Output Current
Adjustable Output Voltage from 0.9 to 6V
Pin-Selectable Output Voltage (nominal, + 5%)
Programmable Soft Start and Tracking
Seamless Power Save Mode Transition
Quiescent Current of 17µA (typ.)
Selectable Operating Frequency
Power Good Output
100% Duty Cycle Mode
Short Circuit Protection
Over Temperature Protection
Available in a 3 × 3 mm, QFN-16 Package
APPLICATIONS
•
•
•
•
•
•
The TPS6215X family is an easy to use synchronous
step down DC-DC converter optimized for
applications with high power density. A high switching
frequency of typically 2.5MHz allows the use of small
inductors and provides fast transient response as well
as high output voltage accuracy by utilization of the
DCS-Control™ topology.
With its wide operating input voltage range of 3V to
17V, the devices are ideally suited for systems
powered from either a Li-Ion or other batteries as well
as from 12V intermediate power rails. It supports up
to 1A continuous output current at output voltages
between 0.9V and 6V (with 100% duty cycle mode).
The output voltage startup ramp is controlled by the
soft-start pin, which allows operation as either a
standalone power supply or in tracking configurations.
Power sequencing is also possible by configuring the
Enable and open-drain Power Good pins.
In Power Save Mode, the devices show quiescent
current of about 17μA from VIN. Power Save Mode,
entered automatically and seamlessly if load is small,
maintains high efficiency over the entire load range.
In Shutdown Mode, the device is turned off and
shutdown current consumption is less than 2μA.
Standard 12V Rail Supplies
POL Supply from Single or Multiple Li-Ion
Battery
Solid-State Disk Drives
Embedded Systems
LDO replacement
Mobile PCs, Tablet, Modems, Cameras
The device, available in adjustable and fixed output
voltage versions, is packaged in a 16-pin QFN
package measuring 3 × 3 mm (RGT).
spacing
(3 .. 17)V
1.8V / 1A
2.2µH
PVIN
SW
AVIN
VOS
PG
EN
10uF
100k
22uF
TPS62151
SS/TR
3.3nF
FB
DEF
AGND
FSW
PGND
Figure 1. Typical Application and Efficiency
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2011–2013, Texas Instruments Incorporated
TPS62150, TPS62150A
TPS62151, TPS62152, TPS62153
SLVSAL5B – NOVEMBER 2011 – REVISED JUNE 2013
www.ti.com
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
ORDERING INFORMATION (1)
TA
OUTPUT VOLTAGE
PART NUMBER (2)
adjustable
TPS62150
adjustable
-40°C to 85°C
(1)
(2)
(3)
TPS62150A
PACKAGE
(3)
16-Pin QFN
ORDERING
PACKAGE MARKING
TPS62150RGT
QUA
TPS62150ARGT
PA8I
TPS62151RGT
QWO
1.8 V
TPS62151
3.3 V
TPS62152
TPS62152RGT
QWP
5.0 V
TPS62153
TPS62153RGT
QWQ
For detailed ordering information please check the PACKAGE OPTION ADDENDUM section at the end of this datasheet.
Contact the factory to check availability of other fixed output voltage versions.
While TPS6215X has PG=High Z, TPS62150A features PG=Low, when device is in shutdown through EN, UVLO or Thermal Shutdown.
ABSOLUTE MAXIMUM RATINGS (1)
over operating free-air temperature range (unless otherwise noted)
MIN
Pin voltage range
(2)
MAX
AVIN, PVIN
-0.3
20
EN, SS/TR
-0.3
VIN+0.3
SW
-0.3
VIN+0.3
DEF, FSW, FB, PG, VOS
-0.3
Power Good sink current PG
Temperature range
ESD rating (3)
(1)
(2)
(3)
V
7
V
mA
-40
125
Storage temperature range, Tstg
-65
150
CDM Charge device model
V
10
Operating junction temperature range, TJ
HBM Human body model
UNIT
°C
2
kV
0.5
kV
Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating
conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
All voltages are with respect to network ground terminal.
ESD testing is performed according to the respective JESD22 JEDEC standard.
THERMAL INFORMATION
THERMAL METRIC (1)
TPS6215X
θJA
Junction-to-ambient thermal resistance
θJC(TOP)
Junction-to-case(top) thermal resistance
θJB
Junction-to-board thermal resistance
11
ψJT
Junction-to-top characterization parameter
0.5
ψJB
Junction-to-board characterization parameter
10
θJC(BOTTOM)
Junction-to-case(bottom) thermal resistance
3.5
(1)
UNITS
RGT 16 PINS
29.1
15
°C/W
For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.
RECOMMENDED OPERATING CONDITIONS
over operating free-air temperature range (unless otherwise noted)
MIN
Supply Voltage, VIN (at AVIN and P VIN)
TYP
MAX
UNIT
3
17
V
Operating free air temperature, TA
–40
85
°C
Operating junction temperature, TJ
–40
125
°C
2
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SLVSAL5B – NOVEMBER 2011 – REVISED JUNE 2013
ELECTRICAL CHARACTERISTICS
over free-air temperature range (TA=-40°C to +85°C), typical values at VIN=AVIN=PVIN=12V and TA=25°C (unless otherwise
noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
SUPPLY
VIN
Input Voltage Range (1)
IQ
Operating Quiescent Current
EN = High, IOUT=0mA, device not switching
ISD
Shutdown Current (2)
EN = Low
VUVLO
TSD
Undervoltage Lockout Threshold
3
Falling Input Voltage
17
V
25
µA
1.5
4
µA
2.7
2.8
V
17
2.6
Hysteresis
200
Thermal Shutdown Temperature
mV
160
Thermal Shutdown Hysteresis
°C
20
CONTROL (EN, DEF, FSW, SS/TR, PG)
VH
High Level Input Threshold Voltage (EN,
DEF, FSW)
VL
Low Level Input Threshold Voltage (EN,
DEF, FSW)
ILKG
Input Leakage Current (EN, DEF, FSW)
0.9
EN = VIN or GND; DEF, FSW = VOUT or GND
V
0.3
V
µA
0.01
1
Rising (%VOUT)
92
95
98
Falling (%VOUT)
87
90
93
VTH_PG
Power Good Threshold Voltage
VOL_PG
Power Good Output Low
IPG = -2mA
0.07
0.3
V
ILKG_PG
Input Leakage Current (PG)
VPG = 1.8V
1
400
nA
ISS/TR
SS/TR Pin Source Current
2.5
2.7
µA
VIN ≥ 6V
90
170
VIN = 3V
120
VIN ≥ 6V
40
VIN = 3V
50
2.3
%
POWER SWITCH
High-Side MOSFET ON-Resistance
RDS(ON)
Low-Side MOSFET ON-Resistance
ILIMF
High-Side MOSFET Forward Current Limit (3) VIN = 12V, TA=25°C
1.4
1.7
70
mΩ
mΩ
2.2
A
100
nA
6.0
V
OUTPUT
VREF
Internal Reference Voltage (4)
ILKG_FB
Input Leakage Current (FB)
TPS62150, VFB=0.8V
Output Voltage Range (TPS62150)
VIN ≥ VOUT
DEF (Output Voltage Programming)
DEF = 0 (GND)
0.8
1
0.9
VOUT
DEF = 1 (VOUT)
VOUT
(1)
(2)
(3)
(4)
(5)
(6)
Initial Output Voltage Accuracy (5)
V
VOUT+5%
PWM mode operation, VIN ≥ VOUT +1V
-1.8
1.8
PWM mode operation, VIN ≥ VOUT +1V,
TA = –10°C to 85°C
-1.5
1.6
Power Save Mode operation, COUT=22µF
-2.3
%
2.8
Load Regulation (6)
VIN = 12V, VOUT = 3.3V, PWM mode
operation
0.05
%/A
Line Regulation (6)
3V ≤ VIN ≤ 17V, VOUT = 3.3V, IOUT = 1A, PWM
mode operation
0.02
%/V
The device is still functional down to Under Voltage Lockout (see parameter VUVLO).
Current into AVIN+PVIN pin.
This is the static current limit. It can be temporarily higher in applications due to internal propagation delay (see Current Limit And Short
Circuit Protection section).
This is the voltage regulated at the FB pin.
This is the accuracy provided by the device itself (line and load regulation effects are not included). For the fixed voltage versions the
(internal) resistive divider is included.
Line and load regulation depend on external component selection and layout (see Figure 17 and Figure 18).
Copyright © 2011–2013, Texas Instruments Incorporated
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SLVSAL5B – NOVEMBER 2011 – REVISED JUNE 2013
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DEVICE INFORMATION
SW
3
PG
4
PGND
VOS
EN
13
Exposed
Thermal Pad
5
6
7
8
DEF
2
14
FSW
SW
15
AGND
1
16
FB
SW
PGND
RGT PACKAGE
(TOP VIEW)
12
PVIN
11
PVIN
10
AVIN
9
SS/TR
Terminal Functions
PIN (1)
NAME
NO.
I/O
DESCRIPTION
SW
1,2,3
O
Switch node, which is connected to the internal MOSFET switches. Connect inductor between SW and
output capacitor.
PG
4
O
Output power good (High = VOUT ready, Low = VOUT below nominal regulation) ; open drain (requires
pull-up resistor; goes high impedance, when device is switched off)
FB
5
I
Voltage feedback of adjustable version connect resistive voltage divider to this pin. Its recommended to
connect FB to AGND on fixed output voltage versions for improved thermal performance.
AGND
6
FSW
7
I
Switching Frequency Select (Low ≈ 2.5MHz, High ≈ 1.25MHz (2) for typical operation) (3)
DEF
8
I
Output Voltage Scaling (Low = nominal, High = nominal + 5%) (3)
SS/TR
9
I
Soft-Start / Tracking Pin. An external capacitor connected to this pin sets the internal voltage reference rise
time. It can be used for tracking and sequencing.
AVIN
10
I
Supply voltage for control circuitry. Connect to same source as PVIN.
PVIN
11,12
I
Supply voltage for power stage. Connect to same source as AVIN.
13
I
Enable input (High = enabled, Low = disabled) (3)
14
I
Output voltage sense pin and connection for the control loop circuitry.
EN
VOS
PGND
15,16
Exposed
Thermal Pad
(1)
(2)
(3)
(4)
4
Analog Ground. Must be connected directly to the Exposed Thermal Pad and common ground plane.
Power ground. Must be connected directly to the Exposed Thermal Pad and common ground plane.
Must be connected to AGND (pin 6), PGND (pin 15,16) and common ground plane (4). Must be connected
to AGND. Must be soldered to achieve appropriate power dissipation and mechanical reliability.
For more information about connecting pins, see DETAILED DESCRIPTION and APPLICATION INFORMATION sections.
Connect FSW to VOUT or PG in this case.
An internal pull-down resistor keeps logic level low, if pin is floating.
See Figure 39.
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SLVSAL5B – NOVEMBER 2011 – REVISED JUNE 2013
FUNCTIONAL BLOCK DIAGRAM
PG
Soft
start
Thermal
Shtdwn
UVLO
AVIN
PVIN PVIN
PG control
HS lim
comp
EN*
SW
SS/TR
power
control
control logic
gate
drive
SW
DEF*
SW
FSW*
comp
LS lim
VOS
direct control
&
compensation
ramp
_
FB
comparator
+
timer tON
error
amplifier
DCS - ControlTM
*
This pin is connected to a pull down resistor internally
(see Detailed Description section).
AGND
PGND PGND
Figure 2. TPS62150 (adjustable output voltage)
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SLVSAL5B – NOVEMBER 2011 – REVISED JUNE 2013
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PG
Soft
start
Thermal
Shtdwn
UVLO
AVIN
PVIN PVIN
PG control
HS lim
comp
EN*
SW
SS/TR
power
control
control logic
DEF
gate
drive
SW
*
SW
FSW*
comp
LS lim
VOS
direct control
&
compensation
ramp
_
FB*
comparator
+
timer tON
error
amplifier
DCS - ControlTM
*
This pin is connected to a pull down resistor internally
(see Detailed Description section).
AGND
PGND PGND
Figure 3. TPS62151/2/3 (fixed output voltage)
6
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TPS62151, TPS62152, TPS62153
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SLVSAL5B – NOVEMBER 2011 – REVISED JUNE 2013
PARAMETER MEASUREMENT INFORMATION
List of Components
REFERENCE
DESCRIPTION
IC
17V, 1A Step-Down Converter, QFN
MANUFACTURER
L1
2.2µH, 3.1A, 0.165 x 0.165 in
Cin
10µF, 25V, Ceramic
Standard
Cout
22µF, 6.3V, Ceramic
Standard
Cs
3300pF, 25V, Ceramic
R1
depending on Vout
R2
depending on Vout
R3
100kΩ, Chip, 0603, 1/16W, 1%
TPS62150RGT, Texas Instruments
XFL4020-222MEB, Coilcraft
Standard
L1
VIN
VOS
AVIN
R3
PG
FB
EN
CIN
VOUT
SW
VIN
COUT
R1
TPS62150
SS/TR
CSS
FB
PG
DEF
AGND
FSW
PGND
R2
Figure 4. Measurement Setup
TYPICAL CHARACTERISTICS
Table of Graphs
DESCRIPTION
FIGURE
Efficiency
vs Output Current, vs Input Voltage
5 - 16
Output voltage
vs Output current (Load regulation), vs Input Voltage
(Line regulation)
17, 18
vs Input Voltage
19
vs Output Current
20
Quiescent Current
vs Input Voltage
21
Shutdown Current
vs Input Voltage
Power FET RDS(on)
vs Input Voltage (High-Side, Low-Side)
Output Voltage Ripple
vs output Current
Maximum Output Current
vs Input Voltage
Power Supply Rejection Ratio (PSSR)
vs Frequency
Switching Frequency
22
25
26
27, 28
PWM-PSM-PWM Mode Transition
Waveforms
Maximum Ambient Temperature
Copyright © 2011–2013, Texas Instruments Incorporated
23, 24
29
Load Transient Response
30 - 32
Startup
33, 34
Typical PWM Mode Operation
35
Typical Power Save Mode Operation
36
vs Load Current
37
vs Power Dissipation
38
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SLVSAL5B – NOVEMBER 2011 – REVISED JUNE 2013
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EFFICIENCY
vs
OUTPUT CURRENT
EFFICIENCY
vs
INPUT VOLTAGE
100.0
100.0
90.0
90.0
80.0
70.0
VIN=12V
VIN=17V
Efficiency (%)
Efficiency (%)
80.0
60.0
50.0
40.0
30.0
10.0
IOUT=10mA
50.0
IOUT=1mA
IOUT=1A
IOUT=100mA
40.0
0.001
0.01
Output Current (A)
0.1
VOUT=5.0V
L=2.2uH (XFL4020)
Cout=22uF
20.0
10.0
0.0
1
7
8
9
10
G001
11
12
13
Input Voltage (V)
14
15
16
Figure 6. Efficiency with 1.25MHz, Vout=5V
EFFICIENCY
vs
OUTPUT CURRENT
EFFICIENCY
vs
INPUT VOLTAGE
100.0
100.0
90.0
90.0
80.0
80.0
70.0
70.0
60.0
VIN=17V
50.0
VIN=12V
40.0
30.0
60.0
IOUT=10mA
50.0
IOUT=1mA
17
G001
Figure 5. Efficiency with 1.25MHz, Vout=5V
Efficiency (%)
Efficiency (%)
0.0
0.0001
IOUT=1A
IOUT=100mA
40.0
30.0
VOUT=5.0V
L=2.2uH (XFL4020)
Cout=22uF
20.0
10.0
0.0
0.0001
0.001
0.01
Output Current (A)
0.1
VOUT=5.0V
L=2.2uH (XFL4020)
Cout=22uF
20.0
10.0
0.0
1
7
8
9
10
G001
11
12
13
Input Voltage (V)
14
15
16
Figure 8. Efficiency with 2.5MHz, Vout=5V
EFFICIENCY
vs
OUTPUT CURRENT
EFFICIENCY
vs
INPUT VOLTAGE
100.0
100.0
90.0
90.0
80.0
80.0
70.0
VIN=12V
60.0
VIN=17V
VIN=5V
50.0
40.0
30.0
17
G001
Figure 7. Efficiency with 2.5MHz, Vout=5V
Efficiency (%)
Efficiency (%)
60.0
30.0
VOUT=5.0V
L=2.2uH (XFL4020)
Cout=22uF
20.0
70.0
60.0
IOUT=1A IOUT=100mA
IOUT=10mA
IOUT=1mA
50.0
40.0
30.0
VOUT=3.3V
L=2.2uH (XFL4020)
Cout=22uF
20.0
10.0
0.0
0.0001
0.001
0.01
Output Current (A)
0.1
Figure 9. Efficiency with 1.25MHz, Vout=3.3V
8
70.0
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VOUT=3.3V
L=2.2uH (XFL4020)
Cout=22uF
20.0
10.0
1
G001
0.0
4
5
6
7
8
9 10 11 12 13 14 15 16 17
Input Voltage (V)
G001
Figure 10. Efficiency with 1.25MHz, Vout=3.3V
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TPS62151, TPS62152, TPS62153
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SLVSAL5B – NOVEMBER 2011 – REVISED JUNE 2013
EFFICIENCY
vs
INPUT VOLTAGE
100.0
100.0
90.0
90.0
80.0
80.0
70.0
70.0
60.0
VIN=12V
50.0
Efficiency (%)
Efficiency (%)
EFFICIENCY
vs
OUTPUT CURRENT
VIN=17V
VIN=5V
40.0
30.0
10.0
0.0
0.0001
IOUT=1mA
IOUT=10mA
IOUT=1A
40.0
0.001
0.01
Output Current (A)
0.1
VOUT=3.3V
L=2.2uH (XFL4020)
Cout=22uF
20.0
10.0
0.0
1
4
5
6
7
8
G001
9 10 11 12 13 14 15 16 17
Input Voltage (V)
G001
Figure 11. Efficiency with 2.5MHz, Vout=3.3V
Figure 12. Efficiency with 2.5MHz, Vout=3.3V
EFFICIENCY
vs
OUTPUT CURRENT
EFFICIENCY
vs
INPUT VOLTAGE
100.0
100.0
90.0
90.0
80.0
80.0
70.0
VIN=12V
60.0
50.0
Efficiency (%)
Efficiency (%)
IOUT=100mA
50.0
30.0
VOUT=3.3V
L=2.2uH (XFL4020)
Cout=22uF
20.0
VIN=17V
VIN=5V
40.0
30.0
70.0
IOUT=1A
60.0
IOUT=100mA
50.0
IOUT=10mA
IOUT=1mA
40.0
30.0
VOUT=1.8V
L=2.2uH (XFL4020)
Cout=22uF
20.0
10.0
0.0
0.0001
0.001
0.01
Output Current (A)
0.1
VOUT=1.8V
L=2.2uH (XFL4020)
Cout=22uF
20.0
10.0
0.0
1
3
4
5
6
7
G001
8 9 10 11 12 13 14 15 16 17
Input Voltage (V)
G001
Figure 13. Efficiency with 1.25MHz, Vout=1.8V
Figure 14. Efficiency with 1.25MHz, Vout=1.8V
EFFICIENCY
vs
OUTPUT CURRENT
EFFICIENCY
vs
INPUT VOLTAGE
100.0
100.0
90.0
90.0
80.0
80.0
70.0
60.0
VIN=12V
Efficiency (%)
Efficiency (%)
60.0
VIN=17V
50.0
VIN=5V
40.0
30.0
70.0
60.0
IOUT=1A
50.0
IOUT=100mA
40.0
IOUT=10mA
IOUT=1mA
30.0
VOUT=0.9V
L=2.2uH (XFL4020)
Cout=22uF
20.0
10.0
0.0
0.0001
0.001
0.01
Output Current (A)
0.1
Figure 15. Efficiency with 1.25MHz, Vout=0.9V
Copyright © 2011–2013, Texas Instruments Incorporated
VOUT=0.9V
L=2.2uH (XFL4020)
Cout=22uF
20.0
10.0
1
G001
0.0
3
4
5
6
7
8 9 10 11 12 13 14 15 16 17
Input Voltage (V)
G001
Figure 16. Efficiency with 1.25MHz, Vout=0.9V
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OUTPUT VOLTAGE
vs
OUTPUT CURRENT
OUTPUT VOLTAGE
vs
INPUT VOLTAGE
3.40
3.40
3.30
VIN=5V
3.25
VOUT=3.3V
L=2.2uH (XFL4020)
Cout=22uF
0.001
0.01
Output Current (A)
0.1
IOUT=10mA
3.30
IOUT=1A
IOUT=100mA
3.25
VOUT=3.3V
L=2.2uH (XFL4020)
Cout=22uF
4
7
10
13
Input Voltage (V)
G001
16
G001
Figure 17. Output Voltage Accuracy (Load Regulation)
Figure 18. Output Voltage Accuracy (Line Regulation)
SWITCHING FREQUENCY
vs
INPUT VOLTAGE
SWITCHING FREQUENCY
vs
OUTPUT CURRENT
4
4
3.5
3.5
3
2.5
2
IOUT=0.5A
IOUT=1A
1.5
1
VOUT=3.3V
L=2.2uH (XFL4020)
Cout=22uF
0.5
0
4
6
8
10
12
Input Voltage (V)
14
16
3
2.5
2
1.5
1
0
18
0
0.2
0.5
Output Current (A)
G000
0.8
Figure 20. Switching Frequency
INPUT CURRENT
vs
INPUT VOLTAGE
INPUT CURRENT
vs
INPUT VOLTAGE
5.0
45.0
4.5
40.0
4.0
35.0
30.0
25°C
25.0
85°C
20.0
15.0
3.5
85°C
3.0
2.5
2.0
1.5
1.0
−40°C
5.0
3.0
6.0
9.0
12.0
Input Voltage (V)
−40°C
25°C
0.5
15.0
Figure 21. Quiescent Current
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G000
Figure 19. Switching Frequency
50.0
0.0
0.0
VIN=12V, VOUT=3.3V
L=2.2uH (XFL4020)
FSW=Low
0.5
10.0
10
IOUT=1mA
3.35
3.20
1
Switching Frequency (MHz)
Switching Frequency (MHz)
3.20
0.0001
Input Current (µA)
Output Voltage (V)
VIN=12V
Input Current (µA)
Output Voltage (V)
VIN=17V
3.35
18.0 20.0
G001
0.0
0.0
3.0
6.0
9.0
12.0
Input Voltage (V)
15.0
18.0 20.0
G001
Figure 22. Shutdown Current
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STATIC DRAIN-SOURCE-RESISTANCE (RDSon)
vs
INPUT VOLTAGE
STATIC DRAIN-SOURCE-RESISTANCE (RDSon)
vs
INPUT VOLTAGE
100.0
200.0
160.0
125°C
RDSon Low−Side (mΩ)
RDSon High−Side (mΩ)
180.0
140.0
85°C
120.0
100.0
25°C
80.0
−10°C
60.0
−40°C
40.0
80.0
125°C
60.0
85°C
25°C
40.0
−10°C
20.0
−40°C
20.0
0.0
0.0
3.0
6.0
9.0
12.0
Input Voltage (V)
15.0
0.0
0.0
18.0 20.0
18.0 20.0
G001
OUTPUT CURRENT
vs
INPUT VOLTAGE
3
VOUT=3.3V,
L=2.2uH (XFL4020)
Cout=22uF
2.5
Output Current (A)
Output Voltage Ripple (V)
15.0
OUTPUT VOLTAGE
vs
OUTPUT CURRENT
0.03
VIN=17V
0.02
0.01
2
0
0.1
0.2
0.3
−40°C
25°C
85°C
VOUT=3.3V
L=2.2uH (XFL4020)
Cout=22uF
1.5
1
0.5
VIN=5V
VIN=12V
0.4 0.5 0.6 0.7
Output Current (A)
0.8
0.9
0
1
4
5
6
7
G000
8
9 10 11 12 13 14 15 16 17
Input Voltage (V)
G000
Figure 25. Output Voltage Ripple
Figure 26. Maximum Output Current
POWER SUPPLY REJECTION RATIO
vs
FREQUENCY
POWER SUPPLY REJECTION RATIO
vs
FREQUENCY
100
100
90
VIN=12V
90
VIN=5V
80
VIN=5V
80
VIN=12V
70
70
VIN=17V
PSRR (dB)
PSRR (dB)
9.0
12.0
Input Voltage (V)
Figure 24. Low-Side Switch Resistance
0.04
60
50
40
30
VIN=17V
60
50
40
30
20
20
VOUT=3.3V, IOUT=1A
L=2.2uH (XFL4020)
Cin=10uF, Cout=22uF
10
0
6.0
Figure 23. High-Side Switch Resistance
0.05
0
3.0
G001
10
100
1k
10k
Frequency (Hz)
100k
1M
G000
Figure 27. Power Supply Rejection Ratio, fSW=2.5MHz
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VOUT=3.3V, IOUT=0.1A
L=2.2uH (XFL4020)
Cin=10uF, Cout=22uF
10
0
10
100
1k
10k
Frequency (Hz)
100k
1M
G000
Figure 28. Power Supply Rejection Ratio, fSW=2.5MHz
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OUTPUT VOLTAGE
vs
TIME
OUTPUT VOLTAGE
vs
TIME
Figure 29. PWM-PSM-Transition (VIN=12V, VOUT=3.3V with
50mV/div)
Figure 30. Load Transient Response (IOUT= 0.5 to 1 to 0.5 A,
VIN=12V, VOUT=3.3V)
OUTPUT VOLTAGE
vs
TIME
OUTPUT VOLTAGE
vs
TIME
Figure 31. Line Transient Response of Figure 30, rising
edge
Figure 32. Line Transient Response of Figure 30, falling
edge
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OUTPUT VOLTAGE
vs
TIME
OUTPUT VOLTAGE
vs
TIME
Figure 33. Startup into 100mA (VIN=12V, VOUT=3.3V)
Figure 34. Startup into 1A (VIN=12V, VOUT=3.3V)
PWM SIGNALS
vs
TIME
POWER SAVE MODE SIGNALS
vs
TIME
Figure 35. Typical Operation in PWM Mode (IOUT=1A)
Figure 36. Typical Operation in Power Save Mode
(IOUT=10mA)
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DETAILED DESCRIPTION
Device Operation
The TPS6215X synchronous switched mode power converters are based on DCS-Control™ (Direct Control with
Seamless Transition into Power Save Mode), an advanced regulation topology, that combines the advantages of
hysteretic, voltage mode and current mode control including an AC loop directly associated to the output voltage.
This control loop takes information about output voltage changes and feeds it directly to a fast comparator stage.
It sets the switching frequency, which is constant for steady state operating conditions, and provides immediate
response to dynamic load changes. To get accurate DC load regulation, a voltage feedback loop is used. The
internally compensated regulation network achieves fast and stable operation with small external components
and low ESR capacitors.
The DCS-ControlTM topology supports PWM (Pulse Width Modulation) mode for medium and heavy load
conditions and a Power Save Mode at light loads. During PWM, it operates at its nominal switching frequency in
continuous conduction mode. This frequency is typically about 2.5MHz with a controlled frequency variation
depending on the input voltage. If the load current decreases, the converter enters Power Save Mode to sustain
high efficiency down to very light loads. In Power Save Mode the switching frequency decreases linearly with the
load current. Since DCS-ControlTM supports both operation modes within one single building block, the transition
from PWM to Power Save Mode is seamless without effects on the output voltage.
Fixed output voltage versions provide smallest solution size and lowest current consumption, requiring only 3
external components. An internal current limit supports nominal output currents of up to 1A.
The TPS6215X family offers both excellent DC voltage and superior load transient regulation, combined with
very low output voltage ripple, minimizing interference with RF circuits.
Pulse Width Modulation (PWM) Operation
The TPS6215X operates with pulse width modulation in continuous conduction mode (CCM) with a nominal
switching frequency of 2.5 MHz or 1.25MHz, selectable with the FSW pin. The frequency variation in PWM is
controlled and depends on VIN, VOUT and the inductance. The device operates in PWM mode as long the output
current is higher than half the inductor's ripple current. To maintain high efficiency at light loads, the device
enters Power Save Mode at the boundary to discontinuous conduction mode (DCM). This happens if the output
current becomes smaller than half the inductor's ripple current.
Power Save Mode Operation
The TPS6215X's built in Power Save Mode will be entered seamlessly, if the load current decreases. This
secures a high efficiency in light load operation. The device remains in Power Save Mode as long as the inductor
current is discontinuous.
In Power Save Mode the switching frequency decreases linearly with the load current maintaining high efficiency.
The transition into and out of Power Save Mode happens within the entire regulation scheme and is seamless in
both directions.
TPS6215X includes a fixed on-time circuitry. This on-time, in steady-state operation, can be estimated as:
t ON =
VOUT
× 400ns
V IN
(1)
For very small output voltages, an absolute minimum on-time of about 80ns is kept to limit switching losses. The
operating frequency is thereby reduced from its nominal value, which keeps efficiency high. Using tON, the typical
peak inductor current in Power Save Mode can be approximated by:
I LPSM ( peak ) =
(V IN - VOUT )
× t ON
L
(2)
When VIN decreases to typically 15% above VOUT, the TPS6215X won't enter Power Save Mode, regardless of
the load current. The device maintains output regulation in PWM mode.
14
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100% Duty-Cycle Operation
The duty cycle of the buck converter is given by D=Vout/Vin and increases as the input voltage comes close to
the output voltage. In this case, the device starts 100% duty cycle operation turning on the high-side switch
100% of the time. The high-side switch stays turned on as long as the output voltage is below the internal
setpoint. This allows the conversion of small input to output voltage differences, e.g. for longest operation time of
battery-powered applications. In 100% duty cycle mode, the low-side FET is switched off.
The minimum input voltage to maintain output voltage regulation, depending on the load current and the output
voltage level, can be calculated as:
spacing
VIN (min) = VOUT (min) + I OUT (RDS ( on ) + RL )
(3)
where
IOUT is the output current,
RDS(on) is the RDS(on) of the high-side FET and
RL is the DC resistance of the inductor used.
Enable / Shutdown (EN)
When Enable (EN) is set High, the device starts operation.
Shutdown is forced if EN is pulled Low with a shutdown current of typically 1.5µA. During shutdown, the internal
power MOSFETs as well as the entire control circuitry are turned off. The internal resistive divider pulls down the
output voltage smoothly. An internal pull-down resistor of about 400kΩ is connected and keeps EN logic low, if
the pin is floating. It is disconnected if the pin is High.
Connecting the EN pin to an appropriate output signal of another power rail provides sequencing of multiple
power rails.
Soft Start / Tracking (SS/TR)
The internal soft start circuitry controls the output voltage slope during startup. This avoids excessive inrush
current and ensures a controlled output voltage rise time. It also prevents unwanted voltage drops from highimpedance power sources or batteries. When EN is set to start device operation, the device starts switching after
a delay of about 50µs and VOUT rises with a slope controlled by an external capacitor connected to the SS/TR
pin. See Figure 33 and Figure 34 for typical startup operation.
Connecting SS/TR directly to AVIN provides fastest startup behavior. The TPS6215X can start into a pre-biased
output. During monotonic pre-biased startup, both the power MOSFETs are not allowed to turn on until the
device's internal ramp sets an output voltage above the pre-bias voltage. If the device is set to shutdown
(EN=GND), undervoltage lockout or thermal shutdown, an internal resistor pulls the SS/TR pin down to ensure a
proper low level. Returning from those states causes a new startup sequence as set by the SS/TR connection.
A voltage supplied to SS/TR can be used for tracking a master voltage. The output voltage will follow this voltage
in both directions up and down (see APPLICATION INFORMATION).
Current Limit And Short Circuit Protection
The TPS6215X devices are protected against heavy load and short circuit events. At heavy loads, the current
limit determines the maximum output current. If the current limit is reached, the high-side FET will be turned off.
Avoiding shoot through current, the low-side FET will be switched on to sink the inductor current. The high-side
FET will turn on again, only if the current in the low-side FET has decreased below the low side current limit
threshold.
The output current of the device is limited by the current limit (see ELECTRICAL CHARACTERISTICS). Due to
internal propagation delay, the actual current can exceed the static current limit during that time. The dynamic
current limit can be calculated as follows:
spacing
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I peak ( typ ) = I LIMF +
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VL
× t PD
L
(4)
where
ILIMF is the static current limit, specified in the ELECTRICAL CHARACTERISTICS,
L is the inductor value,
VL is the voltage across the inductor (VIN - VOUT) and
tPD is the internal propagation delay.
The current limit can exceed static values, especially if the input voltage is high and very small inductances are
used. The dynamic high side switch the peak current can be calculated as follows:
(V - VOUT )× 30ns
I peak (typ ) = I LIMF + IN
L
(5)
Power Good (PG)
The TPS6215X has a built in power good (PG) function to indicate whether the output voltage has reached its
appropriate level or not. The PG signal can be used for startup sequencing of multiple rails. The PG pin is an
open-drain output that requires a pull-up resistor (to any voltage below 7V). It can sink 2mA of current and
maintain it's specified logic low level. It is high impedance when the device is turned off due to EN, UVLO or
thermal shutdown. TPS62150A features PG=Low in this case and can be used to actively discharge Vout (see
Figure 49). VIN must remain present for the PG pin to stay Low.
Pin-Selectable Output Voltage (DEF)
The output voltage of the TPS6215X devices can be increased by 5% above the nominal voltage by setting the
DEF pin to High (1). When DEF is Low, the device regulates to the nominal output voltage. Increasing the nominal
voltage allows adapting the power supply voltage to the variations of the application hardware. More detailed
information on voltage margining using TPS6215X can be found in SLVA489. A pull down resistor of about
400kOhm is internally connected to the pin, to ensure a proper logic level if the pin is high impedance or floating
after initially set to Low. The resistor is disconnected if the pin is set High.
Frequency Selection (FSW)
To get high power density with very small solution size, a high switching frequency allows the use of small
external components for the output filter. However switching losses increase with the switching frequency. If
efficiency is the key parameter, more than solution size, the switching frequency can be set to half (1.25 MHz
typ.) by pulling FSW to High. It is mandatory to start with FSW=Low to limit inrush current, which can be done by
connecting to VOUT or PG. Running with lower frequency a higher efficiency, but also a higher output voltage
ripple, is achieved. Pull FSW to Low for high frequency operation (2.5 MHz typ.). To get low ripple and full output
current at the lower switching frequency, it's recommended to use an inductor of at least 2.2uH. The switching
frequency can be changed during operation, if needed. A pull down resistor of about 400kOhm is internally
connected to the pin, acting the same way as at the DEF Pin (see above).
Under Voltage Lockout (UVLO)
If the input voltage drops, the under voltage lockout prevents misoperation of the device by switching off both the
power FETs. The under voltage lockout threshold is set typically to 2.7V. The device is fully operational for
voltages above the UVLO threshold and turns off if the input voltage trips the threshold. The converter starts
operation again once the input voltage exceeds the threshold by a hysteresis of typically 200mV.
Thermal Shutdown
The junction temperature (Tj) of the device is monitored by an internal temperature sensor. If Tj exceeds 160°C
(typ), the device goes into thermal shut down. Both the high-side and low-side power FETs are turned off and PG
goes high impedance. When Tj decreases below the hysteresis amount, the converter resumes normal
operation, beginning with Soft Start. To avoid unstable conditions, a hysteresis of typically 20°C is implemented
on the thermal shut down temperature.
(1)
16
Maximum allowed voltage is 7V. Therefore, it's recommended to connect it to VOUT or PG, not VIN.
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APPLICATION INFORMATION
The following information is intended to be a guideline through the individual power supply design process.
Programming The Output Voltage
While the output voltage of the TPS62150 is adjustable, the TPS62151/2/3 are programmed to fixed output
voltages. For fixed output versions, the FB pin is pulled down internally and may be left floating. It is
recommended to connect to AGND to improve thermal resistance. The adjustable version can be programmed
for output voltages from 0.9V to 6V by using a resistive divider from VOUT to AGND. The voltage at the FB pin is
regulated to 800mV. The value of the output voltage is set by the selection of the resistive divider from
Equation 6 (see Figure 4). It is recommended to choose resistor values which allow a current of at least 2uA,
meaning the value of R2 shouldn't exceed 400kΩ. Lower resistor values are recommended for highest accuracy
and most robust design. For applications requiring lowest current consumption, the use of fixed output voltage
versions is recommended.
æV
ö
R1 = R 2 çç OUT - 1÷÷
V
è REF
ø
(6)
In case the FB pin gets opened, the device clamps the output voltage at the VOS pin internally to about 7.4V.
External Component Selection
The external components have to fulfill the needs of the application, but also the stability criteria of the devices
control loop. The TPS6215X is optimized to work within a range of external components. The LC output filters
inductance and capacitance have to be considered in conjunction, creating a double pole, responsible for the
corner frequency of the converter (see Output Filter And Loop Stability section). Table 1 can be used to simplify
the output filter component selection.
Table 1. L-C Output Filter Combinations (1)
4.7µF
10µF
22µF
47µF
100µF
200µF
√
√
√
√
(2)
√
√
√
√
√
√
400µF
0.47µH
1µH
2.2µH
√
3.3µH
√
√
4.7µH
(1)
(2)
The values in the table are nominal values.
This LC combination is the standard value and recommended for most applications.
spacing
The TPS6215X can be run with an inductor as low as 1µH or 2.2µH. FSW should be set Low in this case.
However, for applications running with the low frequency setting (FSW=High) or with low input voltages, 3.3µH is
recommended. More detailed information on further LC combinations can be found in SLVA463.
Inductor Selection
The inductor selection is affected by several effects like inductor ripple current, output ripple voltage, PWM-toPSM transition point and efficiency. In addition, the inductor selected has to be rated for appropriate saturation
current and DC resistance (DCR). Equation 7 and Equation 8 calculate the maximum inductor current under
static load conditions.
spacing
I L(max) = I OUT (max) +
DI L(max)
2
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DI L(max) = VOUT
V
æ
ç 1 - OUT
V
ç
IN (max)
×ç
L(min) × f SW
ç
ç
è
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ö
÷
÷
÷
÷
÷
ø
(8)
where
IL(max) is the maximum inductor current,
ΔIL is the Peak to Peak Inductor Ripple Current,
L(min) is the minimum effective inductor value and
fSW is the actual PWM Switching Frequency.
spacing
Calculating the maximum inductor current using the actual operating conditions gives the minimum saturation
current of the inductor needed. A margin of about 20% is recommended to add. A larger inductor value is also
useful to get lower ripple current, but increases the transient response time and size as well. The following
inductors have been used with the TPS6215X and are recommended for use:
Table 2. List of Inductors
(1)
Type
Inductance [µH]
Saturation Current [A] (1) Dimensions [L x B x H]
mm
MANUFACTURER
XFL4020-222ME_
2.2 µH, ±20%
3.5
4 x 4 x 2.1
Coilcraft
XFL3012-222MEC
2.2 µH, ±20%
1.6
3 x 3 x 1.2
Coilcraft
XFL3012-332MEC
3.3 µH, ±20%
1.4
3 x 3 x 1.2
Coilcraft
VLS252012T-2R2M1R3
2.2 µH, ±20%
1.3
2.5 x 2 x 1.2
TDK
LPS3015-332
3.3 µH, ±20%
1.4
3 x 3 x 1.4
Coilcraft
744025003
3.3 µH, ±20%
1.5
2.8 x 2.8 x 2.8
Wuerth
PSI25201B-2R2MS
2.2 µH, ±20%
1.3
2 x 2.5 x 1.2
Cyntec
NR3015T-2R2M
2.2 µH, ±20%
1.5
3 x 3 x 1.5
Taiyo Yuden
Lower of IRMS at 40°C rise or ISAT at 30% drop.
spacing
The inductor value also determines the load current at which Power Save Mode is entered:
I load ( PSM ) =
1
DI L
2
(9)
Using Equation 8, this current level can be adjusted by changing the inductor value.
Capacitor Selection
Output Capacitor
The recommended value for the output capacitor is 22uF. The architecture of the TPS6215X allows the use of
tiny ceramic output capacitors with low equivalent series resistance (ESR). These capacitors provide low output
voltage ripple and are recommended. To keep its low resistance up to high frequencies and to get narrow
capacitance variation with temperature, it's recommended to use X7R or X5R dielectric. Using a higher value can
have some advantages like smaller voltage ripple and a tighter DC output accuracy in Power Save Mode (see
SLVA463).
Note: In power save mode, the output voltage ripple depends on the output capacitance, Its ESR and the peak
inductor current. Using ceramic capacitors provides small ESR and low ripple.
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Input Capacitor
For most applications, 10µF will be sufficient and is recommended, though a larger value reduces input current
ripple further. The input capacitor buffers the input voltage for transient events and also decouples the converter
from the supply. A low ESR multilayer ceramic capacitor is recommended for best filtering and should be placed
between PVIN and PGND as close as possible to those pins. Even though AVIN and PVIN must be supplied
from the same input source, it's recommended to place a capacitance of 0.1uF from AVIN to AGND, to avoid
potential noise coupling. An RC, low-pass filter from PVIN to AVIN may be used but is not required.
Soft Start Capacitor
A capacitance connected between SS/TR pin and AGND allows a user programmable start-up slope of the
output voltage. A constant current source supports 2.5µA to charge the external capacitance. The capacitor
required for a given soft-start ramp time for the output voltage is given by:
C SS = t SS ×
2.5mA
1.25V
[F ]
(10)
where
CSS is the capacitance (F) required at the SS/TR pin and
tSS is the desired soft-start ramp time (s).
spacing
NOTE
DC Bias effect: High capacitance ceramic capacitors have a DC Bias effect, which will
have a strong influence on the final effective capacitance. Therefore the right capacitor
value has to be chosen carefully. Package size and voltage rating in combination with
dielectric material are responsible for differences between the rated capacitor value and
the effective capacitance.
spacing
Tracking Function
If a tracking function is desired, the SS/TR pin can be used for this purpose by connecting it to an external
tracking voltage. The output voltage tracks that voltage. If the tracking voltage is between 50mV and 1.2V, the
FB pin will track the SS/TR pin voltage as described in Equation 11 and shown in Figure 37.
spacing
VFB » 0.64 × VSS / TR
(11)
VSS/TR
[V]
1.2
0.8
0.4
0.2
0.4
0.6
0.8
VFB [V]
Figure 37. Voltage Tracking Relationship
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Once the SS/TR pin voltage reaches about 1.2V, the internal voltage is clamped to the internal feedback voltage
and device goes to normal regulation. This works for rising and falling tracking voltages with the same behavior,
as long as the input voltage is inside the recommended operating conditions. For decreasing SS/TR pin voltage,
the device doesn't sink current from the output. So, the resulting decrease of the output voltage may be slower
than the SS/TR pin voltage if the load is light. When driving the SS/TR pin with an external voltage, do not
exceed the voltage rating of the SS/TR pin which is VIN+0.3V.
If the input voltage drops into undervoltage lockout or even down to zero, the output voltage will go to zero,
independent of the tracking voltage. Figure 38 shows how to connect devices to get ratiometric and simultaneous
sequencing by using the tracking function.
spacing
VOUT1
PVIN
SW
AVIN
VOS
PG
EN
TPS62150
SS/TR
FB
DEF
AGND
FSW
PGND
PVIN
SW
AVIN
VOS
VOUT2
R1
EN
PG
TPS62150
SS/TR
R2
FB
DEF
AGND
FSW
PGND
Figure 38. Sequence for Ratiometric and Simultaneous Startup
The resistive divider of R1 and R2 can be used to change the ramp rate of VOUT2 faster, slower or the same as
VOUT1.
A sequential startup is achieved by connecting the PG pin of VOUT1 to the EN pin of VOUT2. Ratiometric start
up sequence happens if both supplies are sharing the same soft start capacitor. Equation 10 calculates the soft
start time, though the SS/TR current has to be doubled. Details about these and other tracking and sequencing
circuits are found in SLVA470.
Note: If the voltage at the FB pin is below its typical value of 0.8V, the output voltage accuracy may have a wider
tolerance than specified.
Output Filter And Loop Stability
The devices of the TPS6215X family are internally compensated to be stable with L-C filter combinations
corresponding to a corner frequency to be calculated with Equation 12:
f LC =
1
2p L × C
(12)
Proven nominal values for inductance and ceramic capacitance are given in Table 1 and are recommended for
use. Different values may work, but care has to be taken on the loop stability which will be affected. More
information including a detailed L-C stability matrix can be found in SLVA463.
The TPS6215X devices, both fixed and adjustable versions, include an internal 25pF feedforward capacitor,
connected between the VOS and FB pins. This capacitor impacts the frequency behavior and sets a pole and
zero in the control loop with the resistors of the feedback divider, per equation Equation 13 and Equation 14:
spacing
20
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f zero =
SLVSAL5B – NOVEMBER 2011 – REVISED JUNE 2013
1
2p × R1 × 25 pF
(13)
spacing
f pole =
1
2p × 25 pF
æ 1
1 ö
÷÷
× çç
+
R
R
2 ø
è 1
(14)
spacing
Though the TPS6215x devices are stable without the pole and zero being in a particular location, adjusting their
location to the specific needs of the application can provide better performance in Power Save mode and/or
improved transient response. An external feedforward capacitor can also be added. A more detailed discussion
on the optimization for stability vs. transient response can be found in SLVA289 and SLVA466.
Layout Considerations
A proper layout is critical for the operation of a switched mode power supply, even more at high switching
frequencies. Therefore the PCB layout of the TPS6215X demands careful attention to ensure operation and to
get the performance specified. A poor layout can lead to issues like poor regulation (both line and load), stability
and accuracy weaknesses, increased EMI radiation and noise sensitivity.
See Figure 39 for the recommended layout of the TPS6215X, which is designed for common external ground
connections. Therefore both AGND and PGND pins are directly connected to the Exposed Thermal Pad. On the
PCB, the direct common ground connection of AGND and PGND to the Exposed Thermal Pad and the system
ground (ground plane) is mandatory. Also connect the VOS pin in the shortest way to VOUT at the output
capacitor.
Provide low inductive and resistive paths for loops with high di/dt. Therefore paths conducting the switched load
current should be as short and wide as possible. Provide low capacitive paths (with respect to all other nodes) for
wires with high dv/dt. Therefore the input and output capacitance should be placed as close as possible to the IC
pins and parallel wiring over long distances as well as narrow traces should be avoided. Loops which conduct an
alternating current should outline an area as small as possible, as this area is proportional to the energy radiated.
Sensitive nodes like FB and VOS need to be connected with short wires and not nearby high dv/dt signals (e.g.
SW). As they carry information about the output voltage, they should be connected as close as possible to the
actual output voltage (at the output capacitor). The capacitor on the SS/TR pin and on AVIN as well as the FB
resistors, R1 and R2, should be kept close to the IC and connect directly to those pins and the system ground
plane.
The Exposed Thermal Pad must be soldered to the circuit board for mechanical reliability and to achieve
appropriate power dissipation.
The recommended layout is implemented on the EVM and shown in its Users Guide, SLVU437. Additionally, the
EVM Gerber data are available for download here, SLVC394.
Copyright © 2011–2013, Texas Instruments Incorporated
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21
TPS62150, TPS62150A
TPS62151, TPS62152, TPS62153
SLVSAL5B – NOVEMBER 2011 – REVISED JUNE 2013
GND
R2
8
C
PVIN
AVIN
www.ti.com
7
R1
6
5
9
4
10
3
11
2
12
1
13
CIN
14
15
PG
16
EN
L1
to GND
plane
VOUT
COUT
to
AGND
GND
Figure 39. Layout Example
THERMAL INFORMATION
Implementation of integrated circuits in low-profile and fine-pitch surface-mount packages typically requires
special attention to power dissipation. Many system-dependent issues such as thermal coupling, airflow, added
heat sinks and convection surfaces, and the presence of other heat-generating components affect the powerdissipation limits of a given component.
Three basic approaches for enhancing thermal performance are listed below:
• Improving the power dissipation capability of the PCB design
• Improving the thermal coupling of the component to the PCB by soldering the Exposed Thermal Pad
• Introducing airflow in the system
For more details on how to use the thermal parameters, see the application notes: Thermal Characteristics
Application Note (SZZA017), and (SPRA953).
The TPS6215X is designed for a maximum operating junction temperature (Tj) of 125°C. Therefore the maximum
output power is limited by the power losses that can be dissipated over the actual thermal resistance, given by
the package and the surrounding PCB structures. If the thermal resistance of the package is given, the size of
the surrounding copper area and a proper thermal connection of the IC can reduce the thermal resistance. To
get an improved thermal behavior, it's recommended to use top layer metal to connect the device with wide and
thick metal lines. Internal ground layers can connect to vias directly under the IC for improved thermal
performance.
If short circuit or overload conditions are present, the device is protected by limiting internal power dissipation.
22
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TPS62151, TPS62152, TPS62153
www.ti.com
SLVSAL5B – NOVEMBER 2011 – REVISED JUNE 2013
Application Example As Power LED Supply
The TPS62150 can be used as a power supply for power LEDs. The FB pin can be easily set down to lower
values than nominal by using the SS/TR pin. With that, the voltage drop on the sense resistor is low to avoid
excessive power loss. Since this pin provides 2.5µA, the FB pin voltage can be adjusted by an external resistor
per Equation 15. This drop, proportional to the LED current, is used to regulate the output voltage (anode
voltage) to a proper level to drive the LED. Both analog and PWM dimming are supported with the TPS62150.
Figure 40 shows an application circuit, tested with analog dimming:
spacing
(4 .. 17) V
2.2 µH
PVIN
SW
AVIN
VOS
PG
EN
10uF
ADIM
22uF
TPS62150
FB
SS/TR
187k
DEF
AGND
FSW
PGND
0.3R
Figure 40. Single Power LED Supply
spacing
The resistor at SS/TR sets the FB voltage to a level of about 300mV and is calculated from Equation 15.
spacing
V FB = 0.64 × 2.5mA × R SS / TR
(15)
spacing
The device now supplies a constant current, set by the resistor at the FB pin, by regulating the output voltage
accordingly. The minimum input voltage has to be rated according the forward voltage needed by the LED used.
More information is available in the Application Note SLVA451.
spacing
Typical Applications
spacing
spacing
(5 .. 17)V
5V / 1A
2.2 µH
10uF
PVIN
SW
AVIN
VOS
PG
EN
100k
22uF
TPS62153
SS/TR
3.3nF
FB
DEF
AGND
FSW
PGND
Figure 41. 5V/1A Power Supply
spacing
spacing
spacing
spacing
Copyright © 2011–2013, Texas Instruments Incorporated
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23
TPS62150, TPS62150A
TPS62151, TPS62152, TPS62153
SLVSAL5B – NOVEMBER 2011 – REVISED JUNE 2013
www.ti.com
spacing
spacing
spacing
(3.3 .. 17)V
3.3V / 1A
2.2 µH
10uF
PVIN
SW
AVIN
VOS
100k
PG
EN
22uF
TPS62152
FB
SS/TR
3.3nF
DEF
AGND
FSW
PGND
Figure 42. 3.3V/1A Power Supply
spacing
spacing
spacing
(3 .. 17)V
2.5V / 1A
2.2 µH
PVIN
SW
AVIN
VOS
100k
PG
EN
10uF
390k
22uF
TPS62150
FB
SS/TR
3.3nF
DEF
AGND
FSW
PGND
180k
Figure 43. 2.5V/1A Power Supply
spacing
spacing
spacing
(3 .. 17)V
1.8V / 1A
2.2µH
10uF
PVIN
SW
AVIN
VOS
EN
100k
PG
22uF
TPS62151
SS/TR
3.3nF
FB
DEF
AGND
FSW
PGND
Figure 44. 1.8V/1A Power Supply
spacing
spacing
spacing
spacing
spacing
24
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Product Folder Links: TPS62150, TPS62150A TPS62151 TPS62152 TPS62153
TPS62150, TPS62150A
TPS62151, TPS62152, TPS62153
www.ti.com
SLVSAL5B – NOVEMBER 2011 – REVISED JUNE 2013
spacing
spacing
spacing
(3 .. 17)V
1.5V / 1A
2.2 µH
PVIN
SW
AVIN
VOS
100k
PG
EN
10uF
130k
22uF
TPS62150
FB
SS/TR
3.3nF
DEF
AGND
FSW
PGND
150k
Figure 45. 1.5V/1A Power Supply
spacing
spacing
spacing
(3 .. 17)V
1.2V / 1A
2.2 µH
PVIN
SW
AVIN
VOS
100k
PG
EN
10uF
75k
22uF
TPS62150
FB
SS/TR
3.3nF
DEF
AGND
FSW
PGND
150k
Figure 46. 1.2V/1A Power Supply
spacing
spacing
spacing
(3 .. 17)V
1V / 1A
2.2 µH
PVIN
SW
AVIN
VOS
PG
EN
10uF
100k
51k
22uF
TPS62150
SS/TR
3.3nF
FB
DEF
AGND
FSW
PGND
200k
Figure 47. 1V/1A Power Supply
Copyright © 2011–2013, Texas Instruments Incorporated
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25
TPS62150, TPS62150A
TPS62151, TPS62152, TPS62153
SLVSAL5B – NOVEMBER 2011 – REVISED JUNE 2013
www.ti.com
Application Example As Inverting Power Supply
spacing
The TPS62150 can be used as inverting power supply by rearranging external circuitry as shown in Figure 48.
As the former GND node now represents a voltage level below system ground, the voltage difference between
VIN and VOUT has to be limited for operation to the maximum supply voltage of 17V (see Equation 16).
spacing
V IN + VOUT £ V IN max
(16)
spacing
10uF
2.2µH
(3 .. 13.7)V
PVIN
SW
AVIN
VOS
10uF
PG
EN
1.21M
TPS62150
SS/TR
22uF
FB
3.3nF
DEF
AGND
FSW
PGND
383k
-3.3V
Figure 48. –3.3V Inverting Power Supply
spacing
The transfer function of the inverting power supply configuration differs from the buck mode transfer function,
incorporating a Right Half Plane Zero additionally. The loop stability has to be adapted and an output
capacitance of at least 22µF is recommended. A detailed design example is given in SLVA469.
spacing
Active Output Discharge
spacing
The TPS62150A pulls the PG pin Low, when the device is shut down by EN, UVLO or thermal shutdown.
Connecting PG to Vout through a resistor can be used to discharge Vout in those cases (see Figure 49). The
discharge rate can be adjusted by R3, which is also used to pull up the PG pin in normal operation. For reliability,
keep the maximum current into the PG pin less than 10mA.
spacing
(3 .. 17)V
1 / 2.2 µH
PVIN
Vout / 1A
SW
TPS62150A
AVIN
10uF
3.3nF
VOS
EN
PG
SS/TR
FB
DEF
AGND
FSW
PGND
R3
R1
22uF
R2
Figure 49. Discharge Vout through PG pin
26
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TPS62150, TPS62150A
TPS62151, TPS62152, TPS62153
www.ti.com
SLVSAL5B – NOVEMBER 2011 – REVISED JUNE 2013
REVISION HISTORY
Changes from Original (November 2011) to Revision A
Page
•
Added values to the Initial output voltage accuracy for TA = –10°C to 85°C ....................................................................... 3
•
Changed the description of the AGND pin, and added Note 3. ........................................................................................... 4
•
Power-Save Mode Operation section following Equation 1 ................................................................................................ 14
•
Changed the Layout Considerations section ...................................................................................................................... 21
•
Changed Figure 39 ............................................................................................................................................................. 22
Changes from Revision A (November 2012) to Revision B
Page
•
Added device TPS62150A to data sheet .............................................................................................................................. 1
•
Added device TPS62150A to Ordering Info table ................................................................................................................. 2
•
Added text to Power Good (PG) section regarding device TPS62150A. ........................................................................... 16
•
Added pin option to Footnote statement for Pin-Selectable Output Voltage (DEF) section. .............................................. 16
•
Added text to Frequency Selection (FSW) section for clarification. ................................................................................... 16
•
Added text to Tracking Function section for clarification. ................................................................................................... 20
•
Added application example regarding TPS62150A device. ............................................................................................... 26
Copyright © 2011–2013, Texas Instruments Incorporated
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27
PACKAGE OPTION ADDENDUM
www.ti.com
23-Jul-2013
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
Lead/Ball Finish
(2)
MSL Peak Temp
Op Temp (°C)
Device Marking
(3)
(4/5)
TPS62150ARGTR
ACTIVE
QFN
RGT
16
3000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
PA8I
TPS62150ARGTT
ACTIVE
QFN
RGT
16
250
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
PA8I
TPS62150RGTR
ACTIVE
QFN
RGT
16
3000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
-40 to 85
QUA
TPS62150RGTT
ACTIVE
QFN
RGT
16
250
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
-40 to 85
QUA
TPS62151RGTR
ACTIVE
QFN
RGT
16
3000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
-40 to 85
QWO
TPS62151RGTT
ACTIVE
QFN
RGT
16
250
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
-40 to 85
QWO
TPS62152RGTR
ACTIVE
QFN
RGT
16
3000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
-40 to 85
QWP
TPS62152RGTT
ACTIVE
QFN
RGT
16
250
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
-40 to 85
QWP
TPS62153RGTR
ACTIVE
QFN
RGT
16
3000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
-40 to 85
QWQ
TPS62153RGTT
ACTIVE
QFN
RGT
16
250
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
-40 to 85
QWQ
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
Addendum-Page 1
Samples
PACKAGE OPTION ADDENDUM
www.ti.com
23-Jul-2013
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
OTHER QUALIFIED VERSIONS OF TPS62152 :
• Automotive: TPS62152-Q1
NOTE: Qualified Version Definitions:
• Automotive - Q100 devices qualified for high-reliability automotive applications targeting zero defects
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
13-Jul-2013
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
TPS62150ARGTR
QFN
RGT
16
TPS62150ARGTT
QFN
RGT
TPS62150RGTR
QFN
RGT
TPS62150RGTT
QFN
TPS62151RGTR
SPQ
Reel
Reel
A0
Diameter Width (mm)
(mm) W1 (mm)
B0
(mm)
K0
(mm)
P1
(mm)
W
Pin1
(mm) Quadrant
3000
330.0
12.4
3.3
3.3
1.1
8.0
12.0
Q2
16
250
180.0
12.4
3.3
3.3
1.1
8.0
12.0
Q2
16
3000
330.0
12.4
3.3
3.3
1.1
8.0
12.0
Q2
RGT
16
250
180.0
12.4
3.3
3.3
1.1
8.0
12.0
Q2
QFN
RGT
16
3000
330.0
12.4
3.3
3.3
1.1
8.0
12.0
Q2
TPS62151RGTT
QFN
RGT
16
250
180.0
12.4
3.3
3.3
1.1
8.0
12.0
Q2
TPS62152RGTR
QFN
RGT
16
3000
330.0
12.4
3.3
3.3
1.1
8.0
12.0
Q2
TPS62152RGTT
QFN
RGT
16
250
180.0
12.4
3.3
3.3
1.1
8.0
12.0
Q2
TPS62153RGTR
QFN
RGT
16
3000
330.0
12.4
3.3
3.3
1.1
8.0
12.0
Q2
TPS62153RGTT
QFN
RGT
16
250
180.0
12.4
3.3
3.3
1.1
8.0
12.0
Q2
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
13-Jul-2013
*All dimensions are nominal
Device
Package Type
Package Drawing
Pins
SPQ
Length (mm)
Width (mm)
Height (mm)
TPS62150ARGTR
QFN
RGT
16
3000
552.0
367.0
36.0
TPS62150ARGTT
QFN
RGT
16
250
552.0
185.0
36.0
TPS62150RGTR
QFN
RGT
16
3000
552.0
367.0
36.0
TPS62150RGTT
QFN
RGT
16
250
552.0
185.0
36.0
TPS62151RGTR
QFN
RGT
16
3000
552.0
367.0
36.0
TPS62151RGTT
QFN
RGT
16
250
552.0
185.0
36.0
TPS62152RGTR
QFN
RGT
16
3000
552.0
367.0
36.0
TPS62152RGTT
QFN
RGT
16
250
552.0
185.0
36.0
TPS62153RGTR
QFN
RGT
16
3000
552.0
367.0
36.0
TPS62153RGTT
QFN
RGT
16
250
552.0
185.0
36.0
Pack Materials-Page 2
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