VP101 Data Sheet

THIS DOCUMENT IS FOR MAINTENANCE
PURPOSES ONLY AND IS NOT
RECOMMENDED FOR NEW DESIGNS
FEBRUARY 1994
DS3002-2.0
VP101
30/50MHz 8-BIT CMOS VIDEO DAC
The VP101 is a CMOS 8-bit video DAC designed for
use in high performance, high resolution colour graphics
applications.
The device uses video control inputs (BLANK, SYNC
and REF WHITE) to provide the VP101 with the video
pedestal levels required to generate RS-343A compatible
video signals into a doubly-terminated 75Ω load, or
alternatively to produce RS-170 video signals across a
singly-terminated 75Ω load.
Data and control inputs are fully pipelined to maintain
synchronisation between the DAC outputs.
The full scale output current is defined by a 1.2V
reference and a single resistor. The reference voltage is
included on-chip in the VP101, but may be supplied
externally if required (see Fig. 2).
Differential and integral linearity errors of the D-A
converters are guaranteed to be a maximum of ±1LSB over
the full operating temperature range.
VAA
AGND
B0
B1
B2
B3
CLOCK
R0
R1
R2
R3
V REF
FS ADJUST
AGND
AGND
VAA
VAA
ISYNC
IOG
IOR
IOB
AGND
BLANK
SYNC
AGND
IOB
IOR
IOG
ISYNC
VAA
AGND
FS ADJUST
V REF
COMP
REF WHITE
G3
G2
G1
G0
DP40
6 B3
5 B2
4 B1
3 B0
2 AGND
1 AGND
44 VAA
43 VAA
42 B 4
41 B 5
40 B 6
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
SYNC
BLANK
G7
G6
G5
G4
R7
R6
R5
R4
B7
V REF
FS ADJUST
AGND
AGND
VAA
VAA
ISYNC
IOG
IOR
IOB
AGND
12
13
14
15
16
17
18
19
20
21
22
44 B 3
43 B 2
42 B 1
41 B 0
40 AGND
39 AGND
38 VAA
37 VAA
36 B 4
35 B 5
34 B 6
23
24
25
26
27
28
29
30
31
32
33
GP44
SYNC
BLANK
G7
G6
G5
G4
R7
R6
R5
R4
B7
DC supply voltage (VAA) -0.3 to +7V
Digital input voltage-0.3 to VAA +0.3V
Analog output short circuit duration Indefinite
Ambient operating temperature 0°C to +70°C
Storage temperature range-55°C to +125°C
G5
G6
G7
11 COMP
10 REF WHITE
9 G3
8 G2
7 G1
6 G0
5 R3
4 R2
3 R1
2 R0
1 CLOCK
ORDERING INFORMATION
ABSOLUTE MAXIMIM RATINGS (Referenced to AGND)
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
HP44
APPLICATIONS
■ High Resolution Colour Graphics
■ CAE/CAD/CAM Applications
■ Image Processing
■ Video Reconstruction
■ Instrumentation
VP101-3 BA DP (Commercial - Plastic DIL Package)
VP101-3 BA HP (Commercial - J-lead Package)
VP101-5 BA DP (Commercial - Plastic DIL Package)
VP101-5 BA HP (Commercial - J-lead Package)
VP101-3 BA GP (Commercial - Plastic Leaded Chip
Carrier, Gullwing formed leads)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
17 COMP
16 REF WHITE
15 G 3
14 G 2
13 G 1
12 G 0
11 R 3
10 R 2
9 R1
8 R0
7 CLOCK
FEATURES
■ 30/50MHz Pipeline Operation
■ Triple 8-Bit D-A Converters
■ ±1 LSB Differential Linearity Error
■ ±1 LSB Integral Linearity Error
■ Guaranteed Monotonic
■ RS-343A/RS-170 Compatible Levels
■ Drives Doubly Terminated 75Ω Load
■ Single 5V Power Supply
■ Typical Power Dissipation 500mW
■ Direct Replacement for Bt101
■ On-Chip Reference Available
G4
R7
R6
R5
R4
B7
B6
B5
B4
Fig.1 Pin connections (not to scale) - top view
VP101
Fig.2 functional block diagram of VP101
RECOMENDED OPERATING CONDITIONS
Symb
ol
Min.
Value
Typ.
Max.
Supply voltage
VAA
4.75
5.00
5.25
V
Ambient operating temperature
Tamb
0
+70
°C
Output load
Reference voltage
(internal or external)
FS ADJUST resistor
RL
VREF
RSET
1.20
542
THERMAL CHARACTERISTICS
DP HP GP
Thermal resistance, chip-to-case θjc = 12 17 17 °C/W
Thermal resistance, chip-to-ambient θjc = 45 50 50 °C/W
2
Ω
37.5
1.14
Units
1.26
V
Ω
Conditions
123
Parameter
for RS-343A compatible output levels
VP101
ELECTRICAL CHARACTERISTICS
Test conditions (unless otherwise stated):
As specified in recommended operating conditions.
DC CHARACTERISTICS
Value
Typ.
Min.
Units
Max.
Bits
8
Resolution (each DAC)
Accuracy (each DAC)
Integral linearity error
Differential linearity error
Grey scale error
Monotonicity
±0.3
±0.3
±1%
guaranteed
INL
DNL
Digital inputs
Input high voltage
Input low voltage
Input high current
Input low current
VIH
VIL
IIH
IIL
Analog outputs
Grey scale current range
3.0
AGND-0.3
15
±1
±1
±5%
LSB
LSB
% grey scale
VAA+0.3
1.2
+1
-1
V
V
µA
µA
20
mA
LSB
20.40
mA
LSB
mA
LSB
mA
LSB
mA
LSB
mA
LSB
µA
LSB
µA
%
V
µA
V
ppm/°C
255
Output currents
White level relative to blank level
17.69
White level relative to black level
16.74
Black level relative to blank level
0.95
Blank level on IOR, IOB
19.06
276
17.62
255
1.44
21
5
0
7.62
111
5
0
Blank level on IOG
6.29
Sync level on IOG
0
LSB size
DAC to DAC matching
Output compliance
External VREF input current
Internal voltage reference
Internal VREF temperature coefficient
18.50
1.90
50
8.96
50
69.1
2
LSB
VOC
IREF
VREF
Conditions
+1.4
10
1.26
-0.5
1.20
40
1.14
123
Symbol
binary
coding
144424443
Parameter
RS-343A
tolerances
assumed
AC CHARACTERISTICS
Parameter
Symbol
Min.
VP101-5
Typ.
Max.
Min.
VP101-3
Typ.
Max.
Units
Max clock rate
fmax
50
30
MHz
Data and control setup time
Data and control hold time
tSU
tH
6
2
8
2
ns
ns
Clock cycle time
Clock pulse width high time
Clock pulse width low time
tCYC
tCLKH
tCLKL
20
8
8
33.3
10
10
ns
ns
ns
Analog output delay
Analog output rise/fall time
Analog output settling time
Glitch energy
Analog output skew
tDLY
tVRF
tS
IAA
10
15
100
0
3
ns
ns
ns
pV-sec
ns
1
1
Clock
100
140
mA
8
1
Pipeline delay
VAA supply current
10
12
100
0
3
1
1
120
175
9
1
Conditions
at fmax, VAA = 5V
3
VP101
CIRCUIT DESCRIPTION
As shown in the Fig. 2, the VP101 contains three 8-bit
D-A converters, input latches, and a loop amplifier.
On the rising edge of each clock cycle, (see Fig. 4), 24
bits of colour information (R0-R7, G0-G7, and B0-B7) are
latched into the device and presented to the three 8-bit D-A
converters. The REF WHITE input, also latched on the rising
edge of each clock cycle, and will force the inputs of each DA converter to $FF.
SYNC and BLANK are latched on the rising edge of the
clock to maintain synchronisation with the colour data. These
inputs add appropriately weighted currents to the analog
outputs, producing the specific output levels required for
video applications as shown in Fig. 3. Table 1 details how the
SYNC, BLANK, and REFWHITE inputs modify the output
levels.
The ISYNC current output is typically connected directly
to the IOG output and is used to encode sync information
onto the IOG output. If ISYNC is not connected to the IOG
output, sync information will not be encoded on the green
channel, and the IOR, IOG and IOB outputs will have the
same full scale output current.
Full Scale output current is set by an external resistor
(RSET) between the FS ADJUST pin and AGND. RSET has a
typical value of 542Ω for generation of RS-343A video into a
37.5Ω load. The VP101 may be used in applications where
an external 1.2V (typical) reference is provided, in which
case the external reference should be temperature
compensated and provide a low impedance output.
The D-A converters on the VP101 use a segmented
architecture in which bit currents are routed to either the
output or AGND by a sophisticated decoding scheme.This
architecture eliminates the need for precision component
ratios and greatly reduces the switching transients
associated with turning current sources on or off.
Monotonicity and low glitch energy are guaranteed by using
identical current sources and current steering their outputs.
An on-chip operational amplifier stabilises the full scale
output current against temperature and power supply
variations.
The analog outputs of the VP101 are capable of directly
driving a 37.5Ω load, such as a doubly terminated 75Ω coaxial cable or interpolation filters.
Fig.3 Composite video output waveform
IOG
(mA)
IOR/IOB
(mA)
REF
WHITE
SYNC
BLANK
DAC
I/P Data
White Level
26.68
19.06
1
1
1
$XX
White Level
26.68
19.06
0
1
1
$FF
Data
Data + 9.06
Data + 1.44
0
1
1
Data
Data-Sync
Data + 1.44
Data + 1.44
0
0
1
Data
Blank Level
9.06
1.44
0
1
1
$00
Blank-Sync
1.44
1.44
0
0
1
$00
Blank Level
7.62
0
X
1
0
$XX
Sync Level
0
0
X
0
0
$XX
Description
NOTE: Typical with full scale IOG = 26.68mA, RSET = 542Ω, VREF = 1.2V, ISYNC connected to IOG
Table 1: Video output truth table
4
VP101
Pin name
Description
BLANK
Composite blank control input. A logic ‘0’ forces the IOR, IOG and IOB outputs to the blanking level, as
illustrated in Table 1. It is latched on the rising edge of CLOCK. When BLANK is a logic zero, the R0-R7, G0G7, B0-B7, and REF WHITE inputs are ignored.
SYNC
Composite sync control input. A logic ‘0’ on this input switches off a 40 IRE current source on the ISYNC
output. SYNC does not override any other control or data input as shown in Table 1; therefore it should be
asserted only during the blanking interval. It is latched to the rising edge of CLOCK.
REF
WHITE
Reference white level control input. A logic ‘1’ on this input forces the IOR, IOG and IOB outputs to the white
level, regardless of the R0-R7, G0-G7 and B0-B7 inputs. It is latched on the rising edge of CLOCK. See table 1.
R0-R7
G0-G7
B0-B7
Red, Green, and Blue data inputs. R0, G0, and B0 are the least significant data bits. They are latched on the
rising edge of CLOCK. Coding is binary. Unused inputs should be connected to either the regular PCB power
or ground plane.
CLOCK
Clock input. The rising edge of CLOCK latches the R0-R7, G0-G7 and B0-B7 SYNC, BLANK, and REFWHITE
inputs. It is typically the pixel clock rate of the video system. It is recommended that the CLOCK input be
driven by a dedicated CMOS buffer.
IOR,IOG,
IOB
Red, Green, and Blue current outputs. these high impedance current sources are capable of directly driving a
doubly terminated 75Ω co-axial cable. All outputs, whether used or not, should have the same output load
(Note: A DC path to ground must be maintained).
ISYNC
Sync current output. Typically this current output is directly wired to the IOG output, and enables sync
information to be encoded onto the green channel. A logic ‘0’ on the SYNC input results in no current being
output to this pin, while logic ‘1’ results in the following current being output:
VREF (V)
ISYNC (mA) = 3468 X −−−−−−−
≡ 111 LSBs
RSET (Ω)
If sync information is not required on the green channel, this output may be connected to VAA and the SYNC
input tied high, causing the ISYNC current source to be turned off, reducing the power consumption.
FS
ADJUST
Full scale adjust control. A resistor (RSET) connected between this pin and AGND controls the magnitude of
the full video signal (Fig. 3). The current flowing in the RSET resistor is equal to 32 LSBs. note that the IRE
relationships in Fig. 3 are maintained, regardless of the full scale output current.
The relationship between RSET and full scale current on IOG (assuming ISYNC is connected to IOG) is:
VREF (V)
IOG (mA) = 12082 X −−−−−−−
≡ 387 LSBs
RSET (Ω)
The full scale output current on IOR, IOB (mA) for a given RSET is defined as:
VREF (V)
IOR, IOB (mA) = 8624 X −−−−−−−
≡ 276 LSBs
RSET (Ω)
COMP
Compensation pin. This pin provides compensation for the internal loop amplifier. A 0.01µF ceramic capacitor must
be connected between this pin and the nearest VAA pin.
Connecting the capacitor to VAA rather than to the AGND provides the highest possible power supply noise
rejection.
VREF
Voltage reference output. The output from an internal reference circuit, providing 1.2V (typical) reference.A
0.1µF ceramic capacitor must be used to decouple this output to VAA.
AGND
VAA
Analog ground. All AGND pins must be connected.
Analog power. All VAA pins must be connected.
5
VP101
APPLICATION NOTES
RS-343A and RS-170 Video Generation
For generation of RS-343A compatible video levels it is
recommended that a doubly terminated 75Ω load be used
with an RSET resistor value of approximately 542Ω
Similarly for generation of RS-170-compatible video, it is
recommended that a singly terminated 75Ω load be used
with an RSET value of about 774Ω. If the VP101 is not driving
a large capacitive load, there will be negligible difference in
video quality between doubly terminated 75Ω and singly
terminated 75Ω loads.t
If driving a large capacitive load (load RC >1/20IIfc) it is
recommended that an output buffer with unloaded gain >2 be
used to drive a doubly terminated 75Ω load.
COMP Resistor
To optimise the settling time of the VP101, a resistor
may be added in series between the COMP capacitor and
COMP pin. The series resistor damps inductive ringing on
COMP, thus improving settling time.
Non-Video Applications
The VP101 may be used in non-video applications by
disabling the video specific control inputs. REF WHITE
should be a logic ‘0’ while BLANC and SYNC should be a
logic ‘1’. ISYNC should be connected to VAA or AGND. All
three outputs will have the same full scale output current.
The relationship between RSET and full scale output
current (IOUT) in this configuration is as follows:
REF (V) ≡ 255 LSBs
Iout (mA) = 7968 X V
−−−−−−−
RSET (Ω)
VREF (V)
32 X RSET (Ω)
With the data inputs at $00, there is a DC offset current (Imin)
defined as follows:
Note that 1 LSB ≡
Imin (mA) = 656 X V
−−−−−−−
REF (V) ≡ 21 LSBs
RSET (Ω)
Therefore the total full scale output current will be IOUT +
Imin. The REF WHITE input may optionally be used as a
‘force to full scale’ control.
TIMING WAVEFORMS
Fig.4 Input/output timing
NOTES
1. Output delay, tDLY, measured from the 50% point of the rising edge of CLOCK to the 50% point of full scale transition.
2. Settling time, ts, measured from the 50% point of full scale transition to the output remaining within ± 1 LSB.
3. Output rise/fall time, tVRF, measured between the 10% and 90% points of full scale transition.
6
VP101
PCB LAYOUT CONSIDERATIONS
To obtain the optimum performance from the VP101
great care must be taken in the PCB layout to ensure low
noise power and ground lines. This can be achieved by
shielding the digital inputs and providing good decoupling.
Power and Ground Planes
The VP101 and its associated circuitry should have its
own power/ground planes connected at a single point
through a ferrite bead. It is important that the regular PCB
and ground planes do not overlay any portions of the analog
power or ground planes to minimise plane-to-plane noise
coupling.
Digital Signal Interconnect
The digital signal lines to the VP101 should be isolated
as much as possible from the analog circuitry. Due to the
high clock rates used, the clock lines to the VP101 should be
as short as possible to minimise noise pickup.
Any pull-up resistors used on the inputs should be
connected to the regular PCB power plane, not to the analog
power plane.
Supply Decoupling
Noise on the analog power plane will be further reduced
by the use of multiple decoupling capacitors (See Fig. 5).
Optimum performance is obtained with 0.1µF chip
ceramic capacitors placed as close as possible to the VAA
pins, with the shortest leads possible to reduce lead
inductance.
It should be noted that while the loop amplifier circuitry
of the VP101 will reject power supply noise, this rejection
decreases with frequency. Any high frequency noise on the
regular supply (such as produced by a switch mode power
supplies) must be adequately suppressed, else the designer
should consider using a three terminal regulator to supply
the analog power plane.
Analog Signal Interconnect
For optimum performance the analog output connectors
and source termination resistors should be as close as
possible to the VP101 to minimise noise pickup and
reflections due to impedance mismatch. The video out
signals should overlay the ground plane and not the analog
power plane, to maximise the high frequency power supply
rejection.
Fig.5 VP101 typical connections
7
VP101
HEADQUARTERS OPERATIONS
GEC PLESSEY SEMICONDUCTORS
Cheney Manor, Swindon,
Wiltshire SN2 2QW, United Kingdom.
Tel: (01793) 518000
Fax: (01793) 518411
GEC PLESSEY SEMICONDUCTORS
P.O. Box 660017,
1500 Green Hills Road,
Scotts Valley, California 95067-0017,
United States of America.
Tel: (408) 438 2900
Fax: (408) 438 5576
CUSTOMER SERVICE CENTRES
• FRANCE & BENELUX Les Ulis Cedex Tel: (1) 64 46 23 45 Fax: (1) 64 46 06 07
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Swindon Tel: (01793) 518510 Fax: (01793) 518582
These are supported by Agents and Distributors in major countries world-wide.
© GEC Plessey Semiconductors 1994 Publication No. DS3002 Issue No. 2.0 Feb 1994
This publication is issued to provide information only which (unless agreed by the Company in writing) may not be used, applied or reproduced for any purpose nor form part of any order or contract nor to be
regarded as a representation relating to the products or services concerned. No warranty or guarantee express or implied is made regarding the capability, performance or suitability of any product or service. The
Company reserves the right to alter without prior knowledge the specification, design or price of any product or service. Information concerning possible methods of use is provided as a guide only and does not
constitute any guarantee that such methods of use will be satisfactory in a specific piece of equipment. It is the user's responsibility to fully determine the performance and suitability of any equipment using such
information and to ensure that any publication or data used is up to date and has not been superseded. These products are not suitable for use in any medical products whose failure to perform may result in
significant injury or death to the user. All products and materials are sold and services provided subject to the Company's conditions of sale, which are available on request.
8
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