XE1413 - Semtech

XE1413
Bluetooth® Radio
XE1413
1.8V Ultra Low Power Bluetooth® RF Transceiver
GENERAL DESCRIPTION
FEATURES
The XE1413 is the next generation of ultra low
powered, fully integrated single-chip Bluetooth
radio transceiver solutions. Fully compliant with
Bluetooth Specification v1.2, the XE1413 offers
performances tailored for extremely low power
operation in handsets, headsets, and other powersensitive applications.
• Fully integrated single-chip transceiver with on-chip
VCO, synthesizer, PA, LNA, image-reject downconverter, IF filters, RSSI, and demodulator for the
ISM 2.4 GHz band
Transmitter output power is +2 dBm, while receiver
sensitivity is –85 dBm. The frequency range allows
operation in all 2.4 GHz Industrial, Scientific,
Medical (ISM) band regulatory jurisdictions.
• Low voltage supply (1.8 V)
Fabricated in a Silicon-Germanium (SiGe) Bi-polar
Complementary Metal Oxide Semiconductor
(BiCMOS) process, the XE1413 is a state-of-theart mixed signal device mounted in a tiny, low
profile 6 x 6 x 0.75 mm, 40-pin TQFN green
package.
• Peak receive current consumption = 24 mA
APPLICATIONS
• ISM 2.4 GHz frequency band
• Personal wireless connectivity
• Cellular phones, handsets, headsets, earpieces
• PDAs, palm-top computers
• PC and laptop computers
ORDERING INFORMATION
Extended Part Number
Description
XE1413I068TR LF
2.4 GHz Bluetooth
Transceiver
• Class 2 and 3 Bluetooth v1.2 compliant
• Typical receive sensitivity of –85 dBm at antenna
• Two internal voltage regulators (1.8 V and 1.5 V)
• Peak transmit current = 19 mA at maximum power
• Peak transmit current = 11 mA at –10 dBm
•
Low power timing clock mode (15 μA)
• Power-down current consumption <5 μA
• Temperature range of –40 to +85 °C is compliant with
the Bluetooth specification
• Digital crystal frequency error compensation up to ±36
ppm
• Programmable transmit power control over 26 dB
range with 2 dB steps
• High efficiency direct modulation transmitter using ΔΣ
fractional-N synthesizer
• Low phase noise and closed loop PLL transmitter
• Integrated PLL-based FSK digital demodulator.
No external component required
• High reliability, high yield SiGe BiCMOS
process with low multiplicative 1/f noise
• TQFN 40-pin, 6 x 6 package, 0.5 mm pitch,
lead-free
Rev 5 May 2006
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1
XE1413
Bluetooth® Radio
TABLE OF CONTENTS
1
CIRCUIT BLOCK DIAGRAM.............................................................................................................................. 3
2
PIN DESCRIPTION............................................................................................................................................. 4
3
FUNCTIONAL DESCRIPTION ........................................................................................................................... 5
3.1
3.2
3.3
3.3.1
3.3.2
3.3.3
3.3.4
3.3.5
3.4
3.5
3.6
3.6.1
3.6.2
3.7
3.7.1
3.7.2
3.7.3
3.8
3.8.1
3.9
3.9.1
3.9.2
3.9.3
3.9.4
3.9.5
3.9.6
3.9.7
3.9.8
3.10
3.11
3.12
3.13
4
4.1
4.2
4.3
4.4
5
RECEIVE BLOCK ................................................................................................................................................. 5
TRANSMIT BLOCK ............................................................................................................................................... 6
ANALOG CIRCUIT DESCRIPTIONS .......................................................................................................................... 6
LNA AND MIXER SIGNALS ................................................................................................................................... 6
DIFFERENTIAL PA OUTPUTS ...............................................................................................................................6
RF ANALOG POWER SUPPLIES ........................................................................................................................... 6
VCO BIAS DECOUPLING POINT ........................................................................................................................... 6
PLL LOOP FILTER .............................................................................................................................................. 7
MAIN CRYSTAL OSCILLATOR (MXTAL) BLOCK ........................................................................................................ 7
LOW POWER CRYSTAL OSCILLATOR (LPXO) BLOCK................................................................................................ 7
INTERNAL VOLTAGE REGULATOR AND POWER PIN CONSIDERATIONS ....................................................................... 8
CONFIGURATION USING NEITHER OF THE TWO INTERNAL VOLTAGE REGULATORS. .................................................. 8
CONFIGURATION USING BOTH INTERNAL REGULATORS AREG AND DREG ................................................................ 9
DIGITAL CIRCUIT DESCRIPTION ............................................................................................................................. 9
TIMING CONTROL DIGITAL STATE MACHINES ........................................................................................................ 9
TRANSMIT TIMING STATE MACHINE SEQUENCE .................................................................................................. 10
RECEIVE TIMING STATE MACHINE SEQUENCE AND THE SYNCHRONIZATION DETECT FUNCTION ............................... 11
BASEBAND INTERFACING AND SYMBOL TIMING RECOVERY ................................................................................... 13
BASEBAND SYMBOL RECOVERY ....................................................................................................................... 13
CLOCK CONTROL BLOCK AND OSCILLATOR CONTROL .......................................................................................... 14
MAIN CRYSTAL OSCILLATOR (MXTAL)................................................................................................................ 15
LOW POWER CRYSTAL OSCILLATOR (LPXO)....................................................................................................... 15
RC OSCILLATOR ............................................................................................................................................. 16
SLW_CLK_OUT STATE DURING ACTIVE RX AND TX PERIODS ................................................................................ 16
AUTO-SLEEP FUNCTION .................................................................................................................................. 16
32 KHZ/13 MHZ SYS_CLK_OUT CLOCK TRANSITION/DE-GLITCH CIRCUIT .............................................................. 16
AUTOMATIC MXTAL START-UP FUNCTION .......................................................................................................... 17
CLOCK CONTROL DEFAULT STATES .................................................................................................................. 17
SERIAL PROGRAMMING INTERFACE (SPI)........................................................................................................... 17
SERIAL WRITE OPERATION ............................................................................................................................... 18
RESET PIN OPERATION .................................................................................................................................... 18
REGISTERS .................................................................................................................................................... 19
PACKAGE INFORMATION .............................................................................................................................. 23
ELECTROSTATIC DISCHARGE (ESD) SENSITIVITY ............................................................................................... 24
SOLDERING REFLOW PROFILE ........................................................................................................................... 24
ELECTRICAL AND MECHANICAL SPECIFICATIONS ................................................................................................ 24
DATA RECEIVE AND TRANSMIT TIMING ............................................................................................................... 28
APPLICATION DIAGRAM................................................................................................................................ 29
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2
XE1413
Bluetooth® Radio
IF_VDD
RF_SWT
RF_SWR
NC
REG_PD
LPXO_IN
LPXO_OP
SYNC_DET
Pin 41:
Backside
Ground Pad
AREG_OUT
CIRCUIT BLOCK DIAGRAM
REG_BG
1
40
39
38
37
36
35
34
33
32
31
32 kHz Oscillator
AREG_VDD
1
MIX_VDD
2
RC Oscillator
Analog 1.8 V
Voltage Regulator
To Clock
Control Block
D_VDD_IO
To
Clock Control Block
REG_PD
LNA_VDD
70 kΩ
3
Digital Demodulator
Mixer
RF_INP
4
o
RF_INN
Multi-Stage Image Reject Low IF
90
LNA
5
ADC
Digital Control Lines to
Radio Circuit Blocks
Gaussian
Equalizer
ADC
PLL-Based
Digital Discriminator
Auto Threshold Adjust
Buffer
6
7
29
TX_EN
28
RX_EN
27
D_VDD
26
DREG_VDD
25
RX_DATA
24
TX_DATA
23
D_VDD_IO
22
SPI_DATA_OUT
21
SPI_DATA_IN
Internal Register Set
Two-Point
Direct
Modulation
Circuitry
DS MASH
1/N
1/N+1
PA
Digital 1.5 V
Voltage
Regulator
Modulation
Circuitry
ΔΣ Fractional-N Synthesizer
PA_OUT
PWR_RST_BAR
REG_PD
Bit Slicer
Mixer
NC
Rx/Tx
Digital
State Machines
30
PD
Gaussian
PA_VDD
8
MOD_REF
9
To Internal Clock Tree
Reference from Main
Crystal Oscillator
VCO/Modulation
Bias Decoupling
Clock
Control
Block
VCO_VDD
10
VCO VDD
Serial
Programming
Interface
14
15
16
17
18
19
20
XTAL_B
XTAL_VDD
SLW_CLK_OUT
SYS_CLK_OUT
SPI_EN_BAR
SPI_CLK_IN
LOOP_FILT_SW
13
XTAL_A
12
PLL_VDD
11
VCO_TUNE
Main Crystal Oscillator
Figure 1 - XE1413 Block Diagram, in TQFN40 package top-view
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XE1413
Bluetooth® Radio
2
PIN DESCRIPTION
Pin #
Name
Input/
Output
(Note 1)
Digital/
Analog
(Note 2)
Description
1
AREG_VDD
P
–
Input voltage to internal analog regulator (output 1.8V at pin 39)
2
MIX_VDD
P
–
Positive supply for the RF front end
3
LNA_VDD
P
–
Positive supply for the RF front end
4
RF_INP
I
A
Return path for RF input
5
RF_INN
I
A
RF input
6
NC
–
–
Do not connect
7
PA_OUT
O
A
Transmit PA output
8
PA_VDD
P
–
Positive supply for transmit PA
9
MOD_REF
O
A
VCO bias decoupling point
10
VCO_VDD
P
–
Positive supply for VCO
11
VCO_TUNE
I
A
VCO tuning port
12
LOOP_FILT_SW
O
A
Loop filter control
13
PLL_VDD
P
–
Positive supply for PLL
14
XTAL_A
I
A
Crystal oscillator input (MXTAL)
15
XTAL_B
O
A
Crystal oscillator output (MXTAL)
16
XTAL_VDD
P
–
Positive crystal oscillator supply
17
SLW_CLK_OUT
O
D
Slow digital clock output port
18
SYS_CLK_OUT
O
D
System digital clock output port
19
SPI_EN_BAR
I
D
SPI enable, active low
20
SPI_CLK_IN
I
D
SPI clock input port
21
SPI_DATA_IN
I
D
SPI data input port
22
SPI_DATA_OUT
O
D
SPI data output port
23
D_VDD_IO
P
–
Positive supply for the digital I/O pads
24
TX_DATA
I
D
Transmit data input port (from baseband)
25
RX_DATA
O
D
Over-sampled, bit sliced Rx data output to baseband
26
DREG_VDD
P
–
Input voltage to internal digital regulator (output 1.5V at D_VDD pin 27)
27
D_VDD
P
–
Positive supply voltage for digital circuits or regulated output of digital regulator
28
RX_EN
I
D
Receive sequence engaged when high (and TX_EN is low)
29
TX_EN
I
D
Transmit sequence engaged when high (and RX_EN is low)
30
PWR_RST_BAR
IO
D
Power-on reset and external reset. Bidirectional pin with open drain and internal 70
kΩ pull-up resistor to D_VDD_IO (pin 23)
31
SYNC_DET
I
D
Rx synchronization detect signal from baseband. If not used, connect a 100 kΩ
resistor to D_VDD_IO (pin 23) or to ground and set register 0x1B, bit[7] = 0.
32
LPXO_OP
O
A
32 kHz low power crystal output. If not used, leave unconnected.
33
LPXO_IN
I
A
32 kHz low power crystal input. If not used, connect to ground.
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XE1413
Bluetooth® Radio
Pin #
Name
Input/
Output
(Note 1)
Digital/
Analog
(Note 2)
Description
34
REG_PD
I
D
Regulator power-down pin for both regulators (D_VDD_IO = regulators disabled,
Ground = regulators enabled)
35
NC
–
–
Do not connect
36
RF_SWR
O
D
RF switch output control port, active high during receive cycle (inverted RF_SWT
signal). Pin 23 (D_VDD_IO) provides the “high” voltage for RF_SWR.
37
RF_SWT
O
D
RF switch output control port active high during transmit cycle (inverted RF_SWR
signal). Pin 23 (D_VDD_IO) provides the “high” voltage for RF_SWT.
38
IF_VDD
P
–
Positive supply for IF analog circuitry
39
AREG_OUT
P
–
Regulated 1.8 V output from internal analog voltage regulator
40
REG_BG
–
–
Regulator Bang-Gap decoupling. Requires a 1 nF capacitor from pin 40 to ground
when using internal 1.8 V regulator, AREG.
41
GND
G
–
Bottom ground pad.
Note 1:
I = input, O = output, P = power, G = ground
Note 2:
A = analog, D = digital
Table 1 - XE1413 Signal Descriptions
3
FUNCTIONAL DESCRIPTION
The XE1413 is an advanced, fully integrated mixed-signal digital radio transceiver specifically targeted for extreme
low power Bluetooth applications. When combined with a low power baseband device (such as the Semtech
SX1441, XE1431 or XE1402), the resulting solution consumes the lowest power of any other available Bluetooth
system.
The following functional elements are integrated into the XE1413 device:
• Low noise Voltage Controlled Oscillator (VCO)
with internal inductors and varactors
• Dynamic “packet-by-packet” Received Signal
Strength Indicator (RSSI) system
• Low noise fractional-N synthesizer
• Analog/Digital Converter (ADC), Phase Locked
Loop (PLL)-based digital demodulator and bit
slicer
• Two point Gaussian Frequency Shift Keying
(GFSK) modulator
• Low frequency, 32 kHz low power timing clock
oscillator
• PA (Bluetooth Class 2 and 3 operation)
• Software adjustable transmit power control block
(2 dB steps)
• Two voltage regulators (1.8 V and 1.5 V)
• Transmit and receive timing control digital state
machines
• Low-Noise Amplifier (LNA) and mixer
• High performance, dynamic Automatic Gain
Control (AGC) system
• Automatic synthesizer speed-up function
• Clock control block
• High performance, low Intermediate Frequency
(IF) image reject filtering
3.1 RECEIVE BLOCK
The single-ended LNA is followed by a single stage In-Phase and Quadrature (I/Q) down conversion to a low IF.
Effective image signal rejection is provided by IF signal processing in the complex signal domain, which allows the
desired signal to be separated from the undesired image signal.
Since primary Bluetooth applications are mobile in nature, there are packet-to-packet changes in signal path
propagation. Therefore, the multi-stage IF includes a fast AGC that adjusts the individual gains of each IF amplifier
section on a packet-by-packet basis. AGC setting is automatically optimized for each received packet using the
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XE1413
Bluetooth® Radio
internal RSSI system. The AGC setting is established at an early stage during packet reception and remains fixed
for the remainder of the packet.
Post-IF processing occurs in the digital domain after conversions using a low bit count ADC. A PLL-based digital
demodulator that consists of a Gaussian filter, equalizer, data bit slicer, and automatic threshold adjust (frequency
offset correction) allows the receiver to accurately track received signals that have poor frequency stability (transmit
carrier drift due to “dirty” transmitters). Asynchronous data is presented at pin 25 (RX_DATA) and is over-sampled
13 times. The receiver does not provide symbol timing information. A baseband device is required to manage the
symbol timing recovery, to select which of the samples provides the best Bit Error Rate (BER).
To facilitate fast frequency hopping performance, the XE1413 uses a low spurious, ΔΣ fractional-N synthesizer with
a low noise integrated VCO. This combination allows a very high comparison frequency that provides a wide loop
bandwidth for fast frequency hopping.
Several additional functions are incorporated to ensure rapid frequency acquisition. The LOOP_FILT_SW signal
(pin 12) is used to dynamically switch to a lower loop filter resistor, which increases the loop bandwidth and
effectively lowers the acquisition time. Charge pump current is also increased during acquisition. These functions
are fully automatic and no baseband intervention is required.
3.2 TRANSMIT BLOCK
The fractional-N synthesizer enables a “no-IF” transmitter. The 2.4 GHz VCO is directly modulated by application of
a two point filtered GFSK modulation approach. This eliminates the lower frequency oscillator, transmit IF, and
transmit upconverter (mixer) associated with conventional transmitter architectures.
The single-ended PA transmit power output is set through software register settings. The PA power control function
(i.e., ramp up) is controlled by the transmit state machine. As with all PAs, an abrupt transmit power transition
causes poor spectral performance. The on-board transmit state machine ensures adherence to the Bluetooth
spectral requirements. Again, this is an automatic function and requires no baseband intervention.
Operational control of the XE1413 requires limited baseband signaling. This efficiency is afforded by the timing
control digital state machines. These state machines, one for receive and one for transmit, manage time critical
radio functions that free the baseband from having to perform these tasks.
For specifics of the Bluetooth protocol, refer to the latest Bluetooth System Specification available from the official
Bluetooth website at http://www.bluetooth.com/.
3.3 ANALOG CIRCUIT DESCRIPTIONS
This section describes the analog signals and circuit blocks required for any application design using the XE1413
RF transceiver.
3.3.1 LNA and Mixer Signals
The RF_INP (pin 4) and RF_INN (pin 5) signals provide the unbalanced input to the LNA. The MIX_VDD (pin 2)
and LNA_VDD (pin 3) signals are dedicated power supply pins to the LNA and mixer blocks. The package ground
pad provides the supply return path. Ensure that this pad is properly grounded to the PCB.
3.3.2 Differential PA Outputs
The PA_OUT signal (pin 7) is the single-ended output of the transmitter PA. Transmit power can be adjusted in 2
dB steps using the reg_tx_power register (0x01, bits [3:0]).
3.3.3 RF Analog Power Supplies
The PA_VDD (pin 8), VCO_VDD (pin 10), and IF_VDD (pin 38) signals are dedicated RF analog power supplies for
the PA, VCO, and IF circuit blocks, respectively.
3.3.4 VCO Bias Decoupling Point
The MOD_REF (pin 9) signal is a VCO bias decoupling point that must be connected to ground with a capacitor.
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XE1413
Bluetooth® Radio
3.3.5 PLL Loop Filter
The VCO_TUNE (pin 11), LOOP_FILT_SW (pin 12), and PLL_VDD (pin 13) signals connect to the on-board VCO
and fractional-N PLL frequency synthesizer. The external PLL charge pump loop filter components connect from
pin 11 (VCO_TUNE) to pin 13 (PLL_VDD).
Pin 12 (LOOP_FILT_SW) connects a second low value resistor in parallel with the primary loop filter resistor to
improve settling times when a frequency hop takes place. This speed-up function is automatically controlled by the
internal receive and transmit state machines.
3.4 MAIN CRYSTAL OSCILLATOR (MXTAL) BLOCK
A 13 MHz crystal connects to the XTAL_A (pin 14) and XTAL_B (pin 15) signals as illustrated in Figure 2 to
complete the main crystal oscillator (MXTAL) circuit block. Register controlled, frequency adjust loading capacitors
can be programmed using the reg_clock1 register (0x05, bits[3:0]). This feature allows the baseband to correct
temperature-induced frequency drift.
When an external 13 MHz reference source is provided to the XE1413, place an AC coupling capacitor between
the source and pin 15 (XTAL_B), and disconnect pin 14 (XTAL_A). Note that XTAL_VDD (pin 16) must be applied
even when using an external reference signal source.
When an external reference is used, ensure that a clean, low phase noise, stable signal is presented to the
XE1413. Use of buffers on the reference path should be used with caution as some low cost buffers may degrade
performance.
XE1413
XE1413
XTAL_A
14
XTAL_A
15
XTAL_B
14
16
XTAL_B XTAL_VDD
15
∼
XTAL_VDD
n/c
16
1 nF
External 13 MHz source
300 mVpp minimum
xtal_vddpp maximum
Figure 2 - Main Crystal Oscillator Diagram, with XTAL and external source respectively
3.5 LOW POWER CRYSTAL OSCILLATOR (LPXO) BLOCK
The low power crystal oscillator (LPXO) clock is not used or required by the XE1413 circuitry. This cost-saving
feature is provided for baseband timing/clocking. It eliminates the need for a timing clock elsewhere in the system.
Several clock signals are available from the XE1413 through pins 18 (SYS_CLK_OUT) and 17 (SLW_CLK_OUT).
(Refer to the baseband interface description in this document.)
If an external 32 kHz crystal is not used, pin 32 (LPXO_OP) stays unconnected and pin 33 (LPXO_IN) should be
connected to ground. The low power crystal oscillator should be placed in power-down mode using the reg_clock4
register (0x21, bit[7] = 1).
In the event that a 32 kHz clock is available from the system, it can be used to drive the LPXO_OP signal (pin 32).
In this way the SYS_CLK_OUT signal (pin 18) can be used to provide either a 32 kHz or 13 MHz clock to the
baseband device.
Caution must be exercised when driving the low power crystal oscillator from an external source. Radio
performance should be verified in all operational states when using an external LPXO signal source (see Figure 3).
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7
XE1413
Bluetooth® Radio
∼
10 MΩ
XE1413
33
32
LPXO_IN
LPXO_IN
LPXO_OP
LPXO_IN
32
XE1413
External 32 kHz source
50 mVpp minimum
750 mVpp maximum
LPXO_OP
33
32
LPXO_OP
33
1 nF
XE1413
Figure 3 - LPXO External Source with configurations respectively: not used, 32KHz quartz, external source
3.6 INTERNAL VOLTAGE REGULATOR AND POWER PIN CONSIDERATIONS
The XE1413 offers two on-chip voltage regulators that eliminate external power supply components. One regulator
(AREG) is intended to power the analog radio circuits while the other regulator (DREG) is for the digital circuits.
Current consumption is 25 μA for each regulator. It is recommended that both regulators are powered down
whenever the XE1413 is in a power-down state. When the regulators are powered down, they enter a series pass
mode in which they pass the unregulated voltage to the output.
Pin 34 (REG_PD) is the regulator power-down pin. The regulators are powered down when REG_PD equals
D_VDD_IO. The regulators can also be powered down using register control.
3.6.1 Configuration Using Neither of the Two Internal Voltage Regulators.
The schematic diagram shown in Figure 4 indicates the power pin connections for those applications not using
either of the internal voltage regulators. The REG_PD signal (pin 34) must be asserted high for this configuration.
VDD_1.8V
VDD_1.8V
R4 not mounted
0.1uF
Antenna
RF_SWT
IF_VDD
AREG_OUT
REG_BG
AREG_VDD
32kHz
Y2
LPXO_IN
4.7pF
LPXO_OP
2.2 μF
IC
C12
REG_PD
C14
RF_SWR
C15
0Ω
SYNC_DET
VDD_1.8V
PWR_RST_BAR
MIX_VDD
C4 1.0 pF
L2
3.9 nH
RX_DATA
TX_DATA
3.9 nH
C23
4.7pF
R5 not
mounted
C21
2.2uF
RX_DATA
TX_DATA
VDD_1.8V
D_VDD_IO
SPI_DATA_OUT
PA_VDD
C8
SPI_DATA_IN
1 nF
C20
SPI_DATA_R2BB
SPI_DATA_BB2R
2.2 μF
MOD_REF
0.1 μF
C9
VDD_1.8V
VCO_VDD
C10
4.7 pF
C11
VCO_TUNE
0.1 μF
VDD_1.8V
SPI_CLK
C17 2.2 nF
VDD_1.8V
2.7 kΩ
R1
regulated input voltage
VDD_1.8V
SPI_CLK_IN
VDD_1.8V
an external VDD of 1.8V needs
to be supplied (VDD_1.8V)
RX_EN
DREG_VDD
PA_OUT
L3
TBD
RX_EN
0Ω
IC
SPI_EN_BAR
3
SYS_CLK_OUT
AS21392
SLW_CLK_OUT
5
3
TX_EN
RF_INN
XTAL_A
4
4.7 pF
2
1
PWR_RST_BAR
TX_EN
D_VDD
XE1413
C7
1
C1
SYNC_DET
RF_INP
XTAL_B
BP 2520
4.7 pF
XTAL_VDD
2
4.7 pF
PLL_VDD
6
L1
4
C3
C2 4.7 pF
0.1 μF
LNA_VDD
LOOP_FILT_SW
TBD
C24
2.2pF
C22
100kΩ
R3 not mounted
C6
R2
C24
27kΩ
4.7pF
Y1
13MHz
C19
SPI_EN_BAR
SYS_CLK
SLW_CLK
0.1 μF
C18 220 pF
Figure 4 - Application diagram when voltage regulators are not used
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XE1413
Bluetooth® Radio
3.6.2 Configuration Using Both Internal Regulators AREG and DREG
The schematic diagram shown in Figure 5 illustrates a typical circuit configuration using both internal regulators,
AREG and DREG.
VDDR=1.8V
AREG_VDD
2.2 μF
VDDR
Y2
RF_SWT
AREG_OUT
REG_BG
C5
Antenna
IF_VDD
1 nF
VDDM
REG_PD
32kHz
LPXO_IN
C12
0.1uF
C22
L2
3.9 nH
3.9 nH
the input of analog and digital regulator is VDDM
the output of the digital regulator is DVDD
VDDM
C20
PA_VDD
C8
SPI_DATA_IN
1 nF
SPI_DATA_R2BB
2.2 μF
SPI_DATA_BB2R
MOD_REF
0.1 μF
C9
VDDR
VCO_VDD
C10
C11
4.7 pF
0.1 μF
VCO_TUNE
SPI_CLK_IN
C23
4.7pF
SPI_DATA_OUT
SPI_EN_BAR
VDDR
RX_DATA
TX_DATA
D_VDD_IO
SYS_CLK_OUT
TBD
the output of analog regulator is VDDR
RX_DATA
TX_DATA
PA_OUT
L3
3
2
1
C21
DREG_VDD
IC
SLW_CLK_OUT
5
C4 1.0 pF
RX_EN
1.5V
2.2 μF
RF_INN
1
C1
XE1413
C7
XTAL_A
4
3
D_VDD
XTAL_B
BP 2520
RF_INP
XTAL_VDD
2
AS21392
TX_EN
RX_EN
4.7 pF
C3 4.7 pF
PWR_RST_BAR
TX_EN
PLL_VDD
C2 4.7 pF
4.7 pF
LNA_VDD
LOOP_FILT_SW
6
4
L1
2.2pF
0.1 μF
100kΩ
R3 not populated
TBD
C24
SYNC_DET
SYNC_DET
PWR_RST_BAR
MIX_VDD
C6
LPXO_OP
C14
4.7pF
IC
C15
2.2 μF
REG_PD
C13
0.1 μF
RF_SWR
C16
VDDR
C17 2.2 nF
regulated input voltage
2.7 kΩ
VDDM
R1
SPI_CLK
VDDR
R2
C24
27kΩ
4.7pF
Y1
13MHz
C19
SPI_EN_BAR
SYS_CLK
SLW_CLK
0.1 μF
C18 220 pF
Figure 5 - Both Analog (1.8 V AREG) and Digital (1.5 V DREG) Voltage Regulators Operating
3.7 DIGITAL CIRCUIT DESCRIPTION
This section describes the digital signals and circuit blocks required for any application design using the XE1413
RF transceiver. Figure 6 presents the relationship between the baseband to XE1413 signaling and the air interface
for a Bluetooth exchange. These timing sequences are explored in detail in this section and are for information
only.
3.7.1 Timing Control Digital State Machines
The XE1413 timing control digital state machines manage the internal timing. One transmit and one receive state
machine control the state of all internal circuit blocks. Internal timer settings have been optimized for peak radio
performance. The only timing managed by the baseband device relates to the transmit and receive enable signals
(TX_EN and RX_EN), and the transmit and receive data signals (TX_DATA and RX_DATA), in addition to tracking
transmit and receive timeslots.
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Receive Timeslot
TransmitTimeslot
RF at Antenna
RX_EN
TX_EN
RF_SWT
RF_SWR
RX_DATA
TX_DATA
SYNC_DET
SPI_EN_BAR
SPI_CLK_IN
(Note 1)
(Note 1)
1250 μs
Stabilization Period
1070 μs
(1250 – 180 μs)
End of Packet
625 μs
Stabilization Period
445 μs
(625 – 180 μs)
End of Packet
0
–180 μs
Stabilization Period
SPI_DATA_IN
Time (μs)
Note 1: SPI activity can be extended into the stabilization period
but should be completed by the start of the next timeslot.
Figure 6 - Air Interface Timing
3.7.2
Transmit Timing State Machine Sequence
Figure 7 shows timing administered by the transmit state machine. A brief 6 μs warm-up time is activated on the
rising edge of TX_EN, which is a general all-circuit stabilization period. All other activation sequence timings are
referenced to the end of this 6 μs interval.
The circuit that requires the longest time to settle is the VCO/PLL. This circuit starts its frequency hop and phase
settling as soon as the 6 μs warm-up time ends. Two techniques are applied to achieve rapid frequency hopping,
increased charge pump current and decreased loop filter resistance. Both techniques increase the loop bandwidth
offering a turbo, fast frequency switching mode.
The transmit/receive switch is engaged in the transmit state (RF_SWT, pin 37, goes high and RF_SWR, pin 36,
goes low) 32 μs into the VCO/PLL settling period. This is followed 16 μs later by the PA turn-on/ramp-up. After 75
μs the PLL circuit switches from turbo to normal mode. The charge pump current is returned to the normal level
and the low value loop filter resistor connected to LOOP_FILT_SW (pin 12) is switched out of the loop filter.
The VCO/PLL continues to settle until the 155 μs point (not shown in Figure 7). The final event is the application of
modulation data to the transmitter at pin 24 (TX_DATA). This occurs at the 174 μs point after the 6 μs warm-up
time.
This effectively allows a guard time of 20 μs between VCO/PLL settling and modulation data application. Before the
“Modulation On” instant, data present at TX_DATA is ignored by the XE1413.
The baseband must deliver the first transmit bit so that it appears at TX_DATA 180 μs after TX_EN is asserted
high. The transmit state machine generates an internal 1 MHz clock used to sample TX_DATA. This internal clock
is synchronized with the rising edge of TX_EN. The first sample occurs at the 180.5 μs point (0.5 μs after
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"Modulation On"). Transmit data bits are sampled mid symbol provided that the data bit stream transitions occur at
x μs (x integer) intervals from the rising edge of TX_EN.
The modulated carrier appears at the PA output 3.1 μs after the TX_DATA modulation begins (or more accurately,
3.1 μs after “Modulation On”). This delay – TX_DATA input to PA output – is known as the transmitter latency.
The activation sequence of the radio blocks as controlled by the state machine requires that the baseband assert
the TX_EN signal 183.1 μs before the beginning of the active timeslot (air interface Time Zero). Therefore, the
baseband must track when its next active timeslot is going to occur and then assert the TX_EN signal 183.1 μs
before this event. This is followed 180 μs later by TX_DATA (3.1 μs before the timeslot begins). The Bluetooth
specification allows a maximum timeslot window error of ±10 μs.
180 μs
stablilization period
174 μs
(address: 0x08[7:0] μs)
Modulation on
PLL settling,
turbo to normal
mode switch
32 μs
(address 0x3A[7:0] μs)
PA turn-on and
ramp-up time
TX_EN
48 μs
(address 0x09[7:0] μs)
T/R switch to transmit
6 μs
(address: 0x06[3:0] μs)
Warm-up tme
75 μs
(address: 0x07[7:0] + 1 μs)
Start of first bit of 4-bit Bluetooth
preamble at TX_DATA pin
TX_DATA
Modulated RF at PA output
3.1 μs
transmit
latency
Start of modulated RF with first bit
of 4-bit Bluetooth preamble
at PA output (air interface Time Zero)
NOT TO SCALE
Figure 7 - XE1413 Transmit Timing Sequence
3.7.3 Receive Timing State Machine Sequence and the Synchronization Detect Function
The XE1413 features a synchronization detect function. This signal, input from the baseband, is used by the
receive timing state machine to enhance the radio operation during the initiation of a Bluetooth session where the
air interface timing is not yet known. Figure 8 shows the receive timing administered by the receive timing state
machine. The warm-up time and VCO/PLL settling times are identical to the transmit timing sequence shown in
Figure 7.
The receive circuits are activated in sequence (front-end, IF, demodulator). This power-up sequence completes in 8
μs.
Towards the end of the stabilization period, the RSSI system is enabled to monitor the incoming RF power level.
The receive latency, the time between the beginning of a bit at the RF LNA input and the beginning of the
demodulated bit at RX_DATA output, is shown to be 4.6 μs. Ideally, the baseband must assert RX_EN at least
182.4 μs before the beginning of the expected receive timeslot (air interface Time Zero). When a Bluetooth system
is first activated it must find the piconet synchronization (timeslot boundaries), assuming an active piconet is in the
vicinity. Once radio power-up sequences and initialization programming are complete, the baseband asserts the
RX_EN signal (pin 28). Some time later (11 μs before the end of the stabilization period), the RSSI system begins
to actively monitor the incoming RF power level (the IF amplifier gains are at maximum with the AGC operating in
fast mode). This RF power detector is armed to trigger when the RSSI exceeds a threshold value. Whether this RF
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power is from a transmitting Bluetooth device, excess environmental noise, splatter from an adjacent channel, or
some other source is unknown to the radio.
If the RF source is sufficiently high to be detected by the RSSI power detector, the radio becomes fully active.
Active in this case means two events will occur:
1. RSSI information is used by the receive state machine to dynamically adjust the individual IF stage gains to
optimize signal reception (with fast AGC mode)
2. RX_DATA output is enabled to output demodulated data (or noise, if no signal is present)
The receiver continues to operate under fast AGC and the IF stage gains are dynamically adjusted based upon the
instantaneous RSSI level. This dynamic IF gain-adjust state exists until 30 μs beyond the end of the stabilization
time. At that instant, the receive state machine begins to clamp the IF amplifier gains, stage by stage, and switches
to slow AGC mode while continuing to output demodulated data on pin 25 (RX_DATA).
What happens after this point depends on whether the baseband has detected and recognized the access code.
187 μs
stablilization period
181 μs
(address 0x0A[7:0] μs)
11 μs
PLL settling,
turbo to normal
mode switch
RSSI starts to monitor
duty using maximum IF
gain and AGC fast mode
8 μs
Receive turn-on
sequence ends
RX_EN
127 μs
(address 0x35[7:0] – 1 μs)
Receive turn-on
sequence starts
6 μs
(address 0x06[3:0] μs)
Warm-up tme
75 μs
(address 0x07[7:0] + 1 μs)
Start of first bit of 4-bit Bluetooth
preamble at RX_DATA pin
RX_DATA
4.6 μs
receive
latency
Modulated RF at LNA Input
Start of modulated RF with first bit
of 4-bit Bluetooth preamble
at LNA input (air interface Time Zero)
NOT TO SCALE
Figure 8 - XE1413 Receive Timing Sequence
1 Baseband Detects and Recognizes the Access Code. The receiver state machine locks the IF amplifier gain
levels and switches to slow attack AGC mode. As long as the baseband asserts the SYNC_DETECT (pin 31)
signal to the radio within 255 μs after the RF power detector has been triggered, the radio continues to
demodulate the signal using slow AGC and current IF gain settings for the remainder of the packet. At the end
of the packet, the baseband sets RX_EN low, de-activating the receiver.
2 Baseband Cannot Recognize the Access Code. Either the access code is not the desired one, or there is no
transmitted signal at this instant. In either case, the radio continues to receive until 255 μs after the RF power
detector has been triggered, at which point a time-out occurs.
The receive timing state machine monitors the SYNC_DETECT pin for activity. When the baseband does not
recognize the access code, SYNC_DETECT is not asserted. The lack of this event causes the state machine to
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unfreeze the IF gains, switch to fast AGC mode, and re-arm the RSSI system RF power detector. All this occurs at
the 255 μs point. If the RF power detector is triggered, the radio is activated and the process begins again.
In the event that the received RF energy is not sufficiently high to be detected by the RSSI RF power detector, the
RSSI continues to monitor signal levels with maximum IF amplifier gains and fast AGC, but RX_DATA output is
disabled. This state exists as long as RF power is not detected or until RX_EN is brought low by the baseband.
Under ideal conditions, with only thermal noise at the antenna and RX_EN asserted, the RX_DATA output is
inactive, IF gain is maximized, and AGC is in fast mode. The RX_DATA signal stays high or low and does not
change state. The RSSI system threshold is set far below the Bluetooth sensitivity specification, which provides
good receive sensitivity.
Best performance is achieved when using the synchronization detect function. If the baseband device does not
support this operation, two alternative configurations may be used.
The first is to disable synchronization detect using the reg_sync_detect register (0x1B, bit[7] = 0) and tie the
SYNC_DETECT pin to ground or to the D_VDD_IO pin.
The second alternative is to leave the synchronization detect function enabled and tie the SYNC_DETECT pin to
the D_VDD_IO pin with a 100 kΩ pull-up resistor.
The power-up default state for the synchronization detect function is enabled.
3.8 BASEBAND INTERFACING AND SYMBOL TIMING RECOVERY
The XE1413 baseband interface provides fast, efficient baseband-radio interoperation. This section describes
interface Symbol Timing Recovery (STR) and the related interface signals (TX_EN, RX_EN, and SYNC_DETECT
are described elsewhere in this document). This interface is shown in Figure 9.
TX_DATA
RX_DATA
Demodulator
SYNC_DETECT
Data
Symbol Timing
Re-Timing
Recovery
RX_EN
Synthesizer
TX_EN
RF
Front End
Access Code
Correlator
SPI_EN_BAR
SPI_CLK_IN
Register SPI
Bank Slave
Slot
Timing
Packet
Encoding/
Decoding
SPI_DATA_IN
SPI_DATA_OUT
SYS_CLK_OUT
SPI
Master
SLW_CLK_OUT
PWR_RST_BAR
D_VDD_IO
XE1413
Baseband
Figure 9 - XE1413 Baseband Interface
3.8.1 Baseband Symbol Recovery
The algorithm implemented inside the baseband system affects the STR, symbol recovery, and the BER sensitivity
of the radio. The receive data appearing at the RX_DATA pin is a bit sliced demodulated output, presented without
timing information.
Each receive data bit is composed of 13 digital samples. Under ideal, large SNR conditions, all 13 bit slices are the
same level (either 1 or 0) and the data is clearly discernable to the eye when viewed on an analyzer. Symbol timing
recovery under these conditions is a trivial exercise for the baseband. However, with non-ideal conditions (low
SNR), each data bit received appears at the RX_DATA pin with some of the 13 samples dropped out (i.e., if the
transmitted data bit is a 1, not all of the 13 samples would be set to 1). This causes a level of uncertainty
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concerning the location of the bit cell boundaries (symbol timing) and, to a lesser extent, the data bit value (whether
1 or 0). The analyzer display would appear with 'noisy' or 'jittered' bit cell boundaries, complicating STR
determination. The internal filtering prevents dropouts from occurring mid-symbol.
As the SNR continues to decrease, the number of ‘noisy’ samples encroaches upon the middle of the symbol.
Various techniques and approaches may be applied by a particular baseband. In all cases, the solution requires
two determinations:
1. Establish the STR (i.e., determine where the bit cell boundaries occur)
2. Apply decision criteria to discern a 1 or 0
The most common STR approaches are over-sampling with correlation (applied to the access code word) and PLL
transition tracking. The decision criteria are also subject to differing approaches.
The use of a correlator STR scheme is strongly recommended. It will offer the best radio sensitivity and Carrier-toInterference (C/I) performance.
A poorly designed STR and decision criteria mechanism can degrade radio BER sensitivity performance. As such,
an awareness of the particular baseband algorithm is desirable. A baseband that applies over-sampling with
majority vote decision criteria using all samples causes a degraded BER since the samples near the edge of the
symbol boundaries have a high probability of error that can negatively influence the decision error probability.
The best approach is to use over-sampling to identify symbol timing only. To determine the bit value, use the one
sample that lies midway between bit cell boundaries. Do not use a majority vote decision criteria.
Note that some basebands may only perform STR at the beginning of the packet. Therefore, if the transmitting
system's crystal oscillator (reference source) and/or the receiving baseband crystal oscillator differ significantly
from their nominal frequencies, the BER can degrade towards the end of a packet.
This problem may manifest itself as high BER on DH3 or DH5 packets, but acceptable BER on DH1 packets. As
long as the transmitting and receiving reference sources meet the Bluetooth requirement for frequency accuracy (<
±20 ppm), no BER degradation occurs over the longest Bluetooth packet (DH5).
For example, assume the receiver reference source is at +20 ppm while the transmitter reference source is at –
20 ppm. The total difference is 40 ppm. Over a DH5 packet (i.e., 3000 symbols), the drift at the end of the packet
would be:
3000 μs x 40*10-6 ppm = 120 ns
With the XE1413 internal over-sampling at 13 MHz (every 77 ns), this error does not encroach upon the middle of
the symbol, so BER performance is not degraded.
Baseband sampling of the RX_DATA pin should be synchronized with the radio’s 13 MHz clock (SYS_CLK_OUT,
pin 18) for best performance. The RX_DATA output transitions on the rising edge of SYS_CLK_OUT.
3.9 CLOCK CONTROL BLOCK AND OSCILLATOR CONTROL
As illustrated in Figure 10, this block provides control of all oscillator/clock functions on the XE1413. There are
three oscillators (RC, MXTAL and LXPO) as inputs to the clock control block and two output clock pins on the
XE1413. These output clock pins (SYS_CLK_OUT and SLW_CLK_OUT) are used to provide clock signals to the
baseband device. The SLW_CLK_OUT and SYS_CLK_OUT signals can be enabled or disabled if the application
does not require them.
Figure 10 shows the different possible routing options, settings of multiplexers and the corresponding SPI registers.
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Figure 10 - Clock Control Block
3.9.1 Main Crystal Oscillator (MXTAL)
This oscillator provides a 13 MHz clock to the clock control block and can be routed only to the SYS_CLK_OUT.
Alternatively, the 13 MHz clock can be divided and then be provided as a slow clock at SYS_CLK_OUT (32 kHz) or
SLW_CLK_OUT (3.2 kHz or 32 kHz) This slow clock is generated by the 1/406.25 divider. In the 3.2 kHz case, a
further 1/10 division can be applied.
MXTAL can be powered down in the case a 13 MHz clock is not required (standby modes). Once MXTAL is
powered down an automatic MXTAL start-up function is armed (this function is described elsewhere in this
document). Start up time for MXTAL is 8 to 10 ms.
3.9.2 Low Power Crystal Oscillator (LPXO)
The output of this oscillator can be routed to either SYS_CLK_OUT (at 32 kHz) or SLW_CLK_OUT (3.2 kHz or 32
kHz), The LPXO clock is not required by the XE1413 for its own operation and can be suppressed if the application
does not require a low frequency clock.
An automatic LPXO detect circuit is incorporated into the clock control block to detect the presence of the 32 kHz
signal from LPXO. When this circuit is enabled the LPXO oscillation signal, if present, causes the LPXO detect
output to go high.
When no 32 kHz signal is detected by the LPXO detect circuit the derived 32 kHz clock from the 13 MHz MXTAL
will be selected.
When there is no LPXO crystal installed or there is no external 32 kHz clock driving the LPXO buffer, the buffer
should be configured in power-down mode.
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3.9.3 RC Oscillator
This oscillator provides a very low power (<10 μA), 32 kHz + 30% clock. The RC oscillator can be output to
SYS_CLK_OUT or SLW_CLK_OUT. The RC oscillator also plays a role in the power-on reset function of the
XE1413.
• SYS_CLK_OUT: Mux 1, using the reg_clock2 register (0x06, bit[7] = 1), and Mux 4, using the reg_clock1
register (0x05, bit[5] = 1)
• SLW_CLK_OUT: Mux 6 and Mux 5
The RC oscillator also plays a role in the power-on reset function of the XE1413. The SLW_CLK_OUT and
SYS_CLK_OUT signals are enabled using the reg_clock1 register (0x05, bit[7] = 1 and bit[6] = 1, respectively).
3.9.4 SLW_CLK_OUT State During Active Rx and Tx Periods
The SLW_CLK_OUT signal should be disabled during the active period of receive and transmit timeslots by setting
bit[7] = 0 in the reg_clock1 register (0x05). Failure to do so may degrade radio performance.
3.9.5 Auto-Sleep Function
An auto-sleep function gates the 13 MHz clock to the XE1413 radio blocks and powers them down. This feature
ensures the lowest inter-packet current consumption. The oscillators (MXTAL, LPXO, and RC), clock control block,
and SYS_CLK_OUT and SLW_CLK_OUT pins are independent of the auto-sleep function.
3.9.6 32 kHz/13 MHz SYS_CLK_OUT Clock Transition/De-Glitch Circuit
A de-glitch feature prevents extraneous clock edges when switching between 32 kHz and 13 MHz outputs on the
SYS_CLK_OUT pin (refer to Figure 11 and Figure 12 for the respective timing diagrams). The 16 ms delay shown
in Figure 12 between the SPI_EN_BAR signal going low and the SYS_CLK_OUT signal switching to 13 MHz is due
largely to MXTAL start-up time.
Write:
Reg 0x05[5] = 1 (13 MHz to 32 kHz transition)
Reg 0x05[4] = 0 (Optional for MXTAL shutdown)
SPI_EN_BAR
SYS_CLK_OUT
Switch From 13 MHz to 32 kHz
without glitch
Figure 11 - Timing Diagram, 13 MHz to 32 kHz
(1) Falling Edge Changes
Reg 0x05[5:4] to default values
(bit[5] = 0, bit[4] = 1),
SPI_EN_BAR Pulse Only
SPI_EN_BAR
Approximately 16 ms
SYS_CLK_OUT
(3) Clock switches to
MXTAL without glitch
(2)Keep 32 kHz clock
until MXTAL stable
Figure 12 - Timing Diagram, 32 kHz to 13 MHz
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3.9.7 Automatic MXTAL Start-up Function
An automatic MXTAL start-up function can be used to activate MXTAL when it has been disabled. This function
operates in conjunction with the 32 kHz/13 MHz SYS_CLK_OUT transition/de-glitch feature.
Triggered into action by a falling edge on SPI_EN_BAR, this feature immediately sets bit[4] = 1 in the reg_clock1
register (0x05) to enable MXTAL. Once a start-up and stabilization period for MXTAL ends (approximately 16 ms),
bit[5] in this register is set to 0 to transition SYS_CLK_OUT to 13 MHz from 32 kHz, glitch-free.
To use this feature, bits[5:4] in the reg_clock1 register (0x05) are set to 10b. At this point, the following states exist:
• A 32 kHz clock is present on SYS_CLK_OUT (transitioned from 13 MHz to 32 kHz without glitches using the
transition/de-glitch circuit).
• All radio blocks are powered down.
• MXTAL is powered down.
• The RC oscillator may or may not be powered down depending on the state of bit[6] in the reg_rc_osc register
(0x03). The default state is enabled (bit[6]=0)
• SLW_CLK_OUT may or may not be active depending on the state of bit[7] in the reg_clock1 register (0x05) and
the 32 kHz source. The source of this 32 kHz clock is assumed to be the low power crystal oscillator, LPXO
(alternative source is the RC oscillator, which must be selected by bit[7] in the reg_clock2 register, 0x06, before
MXTAL is disabled).
The automatic MXTAL enable function relieves the baseband from having to enable MXTAL through register
access, allowing it to immediately program the channel/power registers while MXTAL is starting up. Although
nominal start-up time for MXTAL is 8 to 10 ms, a 16 ms start-up period ensures sufficient guard time.
Note that the last SPI activity must be to set bits[5:4] in the reg_clock1 register (0x05) to 10b, which powers down
MXTAL and arms the automatic MXTAL start-up function.
3.9.8 Clock Control Default States
The clock control block diagram in Figure 10 shows the default power-on register configuration. This default state
comprises the following conditions:
• MXTAL enabled: reg_clock1 register (0x05), bit[4] = 1
• RC oscillator enabled: reg_rc_osc register (0x03), bit[6] = 0
• LPXO disabled, reg_clock4 register (0x21), bit[7] = 1
• 13 MHz clock present on SYS_CLK_OUT (pin 18): reg_clock1 register (0x05), bit[5] = 0
• SLW_CLK_OUT (pin 17) is enabled
• LPXO auto detect is disabled: reg_clock2 register (0x06), bit[5] = 1
3.10 SERIAL PROGRAMMING INTERFACE (SPI)
The SPI enables the baseband to read/write non-time critical data to/from the XE1413. The SPI is a standard fourpin interface. Ideally, all SPI activity should take place during inter-packet intervals when both TX_EN and RX_EN
signals are low. SPI activity during transmit or receive may interfere with radio performance. However, SPI activity
can be extended into the stabilization period but should be completed by the start of the next timeslot (refer to
Figure 6).
SPI_EN_BAR. This is an active low signal that activates the SPI interface. The baseband is expected to drive the
SPI_EN_BAR signal low when it wants to communicate with the XE1413.
SPI_CLK_IN. This signal is the serial interface clock from the baseband device. The XE1413 samples the SPI data
on the rising edge of the SPI_CLK_IN signal. The SPI_CLK_IN frequency can be between 1 and 5 MHz.
SPI_DATA_OUT. This signal is the data communication line from the XE1413 to the baseband device.
SPI_DATA_IN. This signal is the data communication line from the baseband device to the XE1413.
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3.11 SERIAL WRITE OPERATION
SPI transfers are arranged in a multi-byte format with the minimum transfer being two bytes. The first byte consists
of a one-bit read/write flag and a seven-bit address. The second byte is the data.
Data bytes from consecutive addresses can be written or read with the address auto-increment feature. This allows
the entire register file contents to be read or written in a single operation by simply holding SPI_EN_BAR low for an
extended period while continuing to apply the SPI_CLK_IN clock.
Refer to Figure 13 and Figure 14 for detailed SPI timing information.
tDSU
tDHD
SPI_EN_BAR
W A0 A1 A2 A3 A4 A5 A6 D0 D1 D2 D3 D4 D5 D6 D7
SPI_DATA_IN
SPI_CLK_IN
tEN_CLK
tCLK
tCKH
tCKL
tCLK_EN
Figure 13 - Baseband Write to XE1413 Timing Diagram
tDSU
tDHD
SPI_EN_BAR
R A0 A1 A2 A3 A4 A5 A6
SPI_DATA_IN
D0 D1 D2 D3 D4 D5 D6 D7
SPI_DATA_OUT
SPI_CLK_IN
tEN_CLK
tCLK
tCKH
tCKL
tCLK_EN
Figure 14 - Baseband Read From XE1413 Timing Diagram
3.12 RESET PIN OPERATION
The reset signal, PWR_RST_BAR (pin 30), is bi-directional. The output device of this pin uses an open drain
configuration with an internal 70 kΩ pull up resistor to D_VDD_IO. Two reset functions exist:
• A power-on reset occurs when the supply voltage is applied to the device. The XE1413 drives PWR_RST_BAR
low for 50 ms as timed by the internal RC oscillator. After this interval, the pin becomes an input and is pulled up
to D_VDD_IO by the internal resistor. All register values are set to their default values listed elsewhere in this
document (refer to Figure 15).
• A soft reset occurs when the baseband drives PWR_RST_BAR low for a minimum of 10 μs anytime after the
power-on reset event. All registers are reset to their default values except for bits[5:4] in the reg_clock1 register
at address 0x05.
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~1ms
D_VDD
SYS_CLK_OUT
~1.3V
20 ms +/- 30%
50 ms +/- 30%
PWR_RST_BAR
Figure 15 - Power-On Sequence with typical values
3.13 REGISTERS
User-programmable XE1413 registers are summarized in Table 2. Table 3 through to Table 15 provide more
detailed descriptions of each register. By default, all registers are readable by the baseband controller.
Under normal operation, the only SPI traffic should be to the reg_channel register (0x00), reg_tx_power register
(0x01), and reg_rssi register (0x02).
Do not access register addresses not listed in Table 2. Writing to these unlisted, reserved registers causes
erroneous device operation. If during design testing, one of these registers is inadvertently modified, simply
execute a reset using the PWR_RST_BAR pin.
All bits marked "Reserved" in Table 3 through Table 15 must not be changed. Caution must be exercised when the
baseband is programming registers with reserved bits.
Address
(Hexadecimal)
Register Name
W/R
(Note 1)
Description
00
reg_channel
W
Channel frequency selection
01
reg_tx_power
W
Transmit power attenuation
02
reg_rssi
R
Receive Signal Strength Indicator (RSSI)
03
reg_rc_osc
W
RC oscillator enable
05
reg_clock1
W
Clock selection and crystal tuning
06
reg_clock2
W
Low frequency clock source select
0B
reg_clock3
W
Low frequency clock source select
0C
reg_sensors
R
Crystal detect
1B
reg_sync_detect
W
Synchronization detect enable
21
reg_clock4
W
Low power crystal oscillator enable
36
reg_sync_detect_timer
W
Maximum time from detected RF power to rising edge of
SYNC_DET
3D
reg_chipcode
R
Device revision code
3F
reg_regulator_pwdn
W
Voltage regulator power-down control
Note 1: Reflects the direction of information flow between the baseband and the XE1413. W indicates that the contents of the register are expected to be written
to by the baseband device. An R indicates that the baseband only reads information; an attempt to write has no effect on the operation of the XE1413.
Table 2 - XE1413 Register Summary
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19
XE1413
Bluetooth® Radio
Bit Location
7
Description
Reset State (0x00)
Reserved (Note 1)
6:0
0
Channel frequency selection:
0x00 = 2.402 GHz
0x4E = 2.480 GHz
0000000
Note 1:“Reserved” bits must not be changed. This register sets the current channel in the synthesizer. Must be loaded before a rising edge on TX_EN or
RX_EN.
Table 3 - reg_channel Register (0x00)
Bit Location
Description
Reset State
(0x00)
7:4
Reserved (Note 1)
0000
3:0
Transmit power control in 1.8 ±0.4 dB steps:
0x00 = 0 dBm nominal
0x08 = –14 dBm nominal
0x0F = –27 dBm nominal
0000
“Reserved” bits must not be changed.
Note 1:
Table 4 - reg_tx_power Register (0x01)
Bit Location
7
Description
Reserved (Note 1)
6:0
Reset State
(0xxx)
0
RSSI digital readout for last received packet. Value in decimal represents signal level in dBm
xxx xxxx
(e.g., 0x14 = –20 dBm; 0x32 = –50 dBm).
The RSSI level is latched into register 0x02 approximately 30 μs after the start of the receive
packet. The SPI should not access the XE1413 during an active transmit or receive session.
Doing so may degrade the BER. The RSSI level is kept until the next receive slot.
“Reserved” bits must not be changed.
Note 1:
Table 5 - reg_rssi Register (0x02)
Bit Location
Description
Reset State
(0x12)
7
Reserved (Note 1)
0
6
RC oscillator enable: 0 = enable, 1 = disable
0
5:2
Reserved (Note 1)
0100
1
Reserved (Note 1)
1
0
Reserved (Note 1)
0
“Reserved” bits must not be changed.
Note 1:
Table 6 - reg_rc_osc Register (0x03)
Bit Location
Description
Reset State
(0xD8)
7
SLW_CLK_OUT enable: 1 = enable, 0 = disable
1
6
SYS_CLK_OUT enable: 1 = enable, 0 = disable
1
5
(Note 1)
SYS_CLK_OUT frequency selection: 1 = select 32 kHz output (from one of: RC oscillator, 32 kHz
LPXO, or divided 13 MHz MXTAL). 0 = select 13 MHz output (from 13 MHz crystal oscillator)
0
4
(Note 1)
MXTAL oscillator enable: 1 = enabled, 0 = disabled
1
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20
XE1413
Bluetooth® Radio
Bit Location
3:0
Description
4-bit crystal oscillator (MXTAL) tuning. Assumes 10 pF loading capacitor, 13 MHz crystal. Due to
internal loading capacitors, no external capacitors are required.
Reset State
(0xD8)
1000
0000 = +36 ppm nominally (±20%)
1111 = –36 ppm nominally (±20%)
This bit is only reset when power is applied to the XE1413. The reset signal, PWR_RST_BAR, does not reset this bit.
Note 1:
Table 7 - reg_clock1 Register (0x05)
Bit Location
7
Description
RC oscillator/XTAL source for 32 kHz: 1 = RC oscillator, 0 = one of the crystal oscillators (either
MXTAL or LPXO)
Reset State
(0x36)
0
6
MXTAL/LXTAL 32 kHz SYS_CLK_OUT manual source selection (MXTAL or LPXO)
0
5
MXTAL/LXTAL 32 kHz auto/manual selection for 32 kHz SYS_CLK_OUT source
1
4
Reserved (Note 1)
1
Reserved (Note 1)
0110
3:0
“Reserved” bits must not be changed.
Note 1:
Table 8 - reg_clock2 Register (0x06)
Bit Location
Description
Reset State
(0x34)
7
SLW_CLK_OUT source: 1 = RC oscillator, 0 = either MXTAL or LPXO crystal oscillator
0
6
RC oscillator 128 kHz/32 kHz frequency select (1 = 128 kHz, 0 = 32 kHz)
0
5
SLW_CLK_OUT 32 kHz/3.2 kHz select (1 = 32 kHz, 0 = 3.2 kHz)
1
4:0
Reserved (Note 1)
10100
“Reserved” bits must not be changed.
Note 1:
Table 9 - reg_clock3 Register (0x0B)
Bit Location
7
Description
LPXO oscillator detect: 0 = not detected,1 = detected
6:3
Reserved (Note 1)
2
1:0
Reset State
(0x07)
0
0000
MXTAL oscillator detect: 1 = detected, 0 = not detected
1
Reserved (Note 1)
11
“Reserved” bits must not be changed.
Note 1:
Table 10 - reg_sensors Register (0x0C)
Bit Location
7
Synchronization detect: 1 = enabled, 0 = disabled
6:0
Note 1:
Description
Reset State
(0xFD)
1
Reserved (Note 1)
1111101
“Reserved” bits must not be changed.
Table 11 - reg_sync_detect Register (0x1B)
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21
XE1413
Bluetooth® Radio
Bit Location
7
Description
Low power LPXO crystal enable_bar: 0 = enabled, 1 = disabled
6:0
Reserved (Note 1)
Reset State
(0x84)
1
0000100
“Reserved” bits must not be changed.
Note 1:
Table 12 - reg_clock4 Register (0x21)
Bit Location
Description
This value specifies the time, in μs, that the baseband IC has to return a synchronization detect
signal to the XE1413 once its RF power detector has been triggered.
7:0
Reset State
(0xFF)
11111111
Table 13 - reg_sync_detect_timer Register (0x36)
Bit Location
7:0
Description
Chip revision code
Reset State
(0x72)
01110010
Table 14 - reg_chipcode Register (0x3D)
Bit Location
Reset State
(0x00)
7
Digital regulator DREG power down: 0 = enable, 1 = power down
0
6
Analog regulator AREG power down: 0 = enable, 1 = power down
0
5:0
Note 1:
Description
Reserved (Note 1)
000000
“Reserved” bits must not be changed.
Table 15 - reg_regulator_pwdn Register (0x3F)
© Semtech 2006
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22
XE1413
Bluetooth® Radio
4
PACKAGE INFORMATION
Package dimensions (all in mm) for the XE1413 40-pin TQFN lead-free are shown below. The marking is shown in
top view
Figure 16:
XE1413
yyww
xxxxxx
xxxxxx
top view
Figure 16 - XE1413 Marking
© Semtech 2006
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23
XE1413
Bluetooth® Radio
4.1 ELECTROSTATIC DISCHARGE (ESD) SENSITIVITY
The XE1413 is a static-sensitive electronic device. Do not operate or store near strong electrostatic fields. Take
proper ESD precautions.
4.2 SOLDERING REFLOW PROFILE
The soldering reflow profile used by XE1413 is described in the standard IPC/JEDEC J-STD-020C (see
http://www.jedec.org/download/search/jstd020c.pdf).
4.3 ELECTRICAL AND MECHANICAL SPECIFICATIONS
The absolute maximum ratings of the XE1413 are provided in Table 16. The electrical specifications are provided in
Table 17 and the state definitions are in Table 18.
Parameter
Symbol
Minimum
Maximum
Units
Supply voltage to analog or digital circuits
VDD
–0.5
+3.6
V
I/O supply to baseband digital interface
VDDIO
–0.5
+3.6
V
Voltage applied to any input
VIN_MAX_ANALOG
–0.5
VDD
V
Voltage applied to any input
VIN_MAX_DIGITAL
–0.5
VDDIO
V
Storage temperature
TSTORAGE
–65
+125
°C
Note: Exposure to maximum rating conditions for extended periods may reduce device reliability. There is no damage to device with only one parameter set at
the limit and all other parameters set at or below their nominal values.
Table 16 - XE1413 Absolute Maximum Ratings
Parameter
Symbol
Test Condition
Min
Typical
Max
Units
General Specifications
Analog supply voltage
A_VDD
Pins 2, 3, 8, 10, 13,
16, and 38 only
1.7
1.8
2.2
V
Digital supply voltage (must be within
±0.3 V of analog supply voltage)
D_VDD
Pin 27 only
1.4
1.8
2.4
V
Digital I/O positive supply voltage
(D_VDD_IO ≥ A_VDD – 0.3 V)
D_VDD_IO
Pin 23 only
1.5
1.8
3.6
V
Voltage regulator input voltage for
1.8 V regulator (AREG)
AREG_VDD
Pin 1 only
2.3
3.0
3.6
V
Voltage regulator input voltage for
1.5 V regulator (DREG)
DREG_VDD
Pin 26 only
2.3
3.0
3.6
V
Operating temperature range,
Bluetooth-compliant
TOP
+85
°C
–40
Digital DC Characteristics
Logic high level in
VIN_HIGH
VDDIO – 0.4
V
Logic low level in
VIN_LOW
Logic high level out
VOUT_HIGH
Logic low level out
VOUT_LOW
Logic high level out
IOUT_HIGH
2
mA
Logic low level out
lOUT_LOW
2
mA
Logic output load capacitance
COUT
10
pF
Logic input capacitance
CIN
2
pF
0.4
VDDIO – 0.4
V
V
0.4
V
Receive
Operating frequency
fOP
Channel spacing
fCHAN
2.402
2.480
1.0
© Semtech 2006
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MHz
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24
XE1413
Bluetooth® Radio
Parameter
Receiver sensitivity at antenna input
Symbol
PR0B
Receiver sensitivity degradation due
to Bluetooth “dirty” transmitter
Test Condition
Min
0.1% BER
correlator-based
STR
Typical
Max
Units
–85
–80
dBm
1
dB
Bluetooth “dirty”
transmitter definition
Maximum input signal (desired or
interferer)
PIMAX
C/I performance
C/I
Receiver latency, antenna to bits at
pins of baseband device
TRX_LATENCY
RSSI range
RSSI
–18
–16
BQTF Bluetooth
v1.2 compliant
dB
μs
4.6
–90
RSSI absolute error for input signal
< –40 dBm
Receive data sampling rate
dBm
FDIGITIZATION
–40
dBm
6
dB
13
MHz
Current Drain (total A_VDD + D_VDD current) see Table 18 for state definitions
Peak current drain during receive
mode (D_VDD = 1.8 V)
IRECEIVE
26
mA
Peak current drain during receive
mode (D_VDD = 1.5 V)
IRECEIVE
24
mA
Peak current drain during transmit
mode, maximum transmit power
ITRANSMIT
19
mA
Peak current drain during transmit
mode, –10 dBm transmit power
ITRANSMIT–10
11
mA
Inter-packet current (RX_EN and
TX_EN low)
IINTER_PACKET
160
μA
Internal current drain with only 32
kHz crystal reference oscillator
running
ISLEEP_LPXO_
15
μA
Current drain in power-down mode
IPOWERDOWN
3
μA
13
MHz
ACTIVE
Crystal Oscillator
MXTAL, main crystal oscillator
fCLK
Maximum ESR =
40 Ω, crystal loading
capacitor
specification =
10 pF; tolerance 10
ppm, external
loading capacitors
not required
External main oscillator drive levels
(see Figure 2)
VMXTAL
AC coupling
Crystal tuning range with 4-bit SPI
programmability
13 MHz
XtalTUNING
LPXO, low power crystal oscillator
fLPXO
ESR = 50 kΩ
nominal, crystal
loading capacitor
specification =
10 pF, external
loading capacitors
not required
External low power oscillator drive
levels (see Figure 3)
VLPXO
AC coupling
0.3
±20
±30
XTAL_VDD
Vp-p
±40
ppm
32
kHz
50
750
mVp-p
2.402
2.480
GHz
Transmitter
Transmit band
© Semtech 2006
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25
XE1413
Bluetooth® Radio
Parameter
Maximum transmit output power at
antenna (see Figure 17)
Symbol
Test Condition
P0HIGH
Min
Typical
Max
Units
-4.0
0
2.5
dBm
26
dB
Transmit power attenuation
P0ATTENUATION
Transmit power attenuation step size
P0ATTEN_STEP
0
Transmitter spectral performance
PS
Transmitter latency, bits at baseband
pins to signal at antenna
TTX_LATENCY
3.1
μs
Transmit data sampling rate
FDIGITIZATION
1
MHz
200
ns
2
dB
BQTF Bluetooth
v1.2 compliant
dBm
SPI and Synchronization Detect Timing
SPI clock period
tCLK
100
SPI data setup time
tDSU
2
ns
SPI data hold time
tDHD
1
ns
SPI enable to clock rising edge
tEN_CLK
¼ tclk
ns
SPI clock falling edge to enable
tCLK_EN
SPI clock duty cycle
tCKL or tCKH
¼ tclk
ns
0.4 tCLK
Synchronization detect pulse width
0.6 tCLK
ns
65
ms
2/fmxtal
Reset Pin Timing
Power on reset output low time
(interval that PWR_RST_BAR, pin
30, output drives low when VDD
applied). See Figure 15.
35
Soft reset (minimum low input
interval to PWR_RST_BAR, pin 30,
from baseband to reset XE1413)
10
50
μs
Table 17 - XE1413 Electrical Specifications
(VDD = 1.8 V, @ +25 °C unless otherwise specified)
States
inter_packet
Description
13 MHz MXTAL running. Radio waiting for assertion of RX_EN or TX_EN.
sleep_lpxo_active
Only 32 kHz LPXO running. Radio blocks, MXTAL, and RC oscillator are all powered down.
sleep_rc_active
Only 32 kHz RC oscillator running. Radio blocks, MXTAL, and LPXO are all powered down.
Power down
All radio blocks, MXTAL, LPXO, and RC oscillator are powered down.
Receive
Receiver outputting demodulated data on RX_DATA pin.
Transmit
Transmitting at selected output power on selected channel.
Table 18 - XE1413 State Definitions
© Semtech 2006
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26
XE1413
Bluetooth® Radio
LEGEND
VDDR
output from XE1413
VDDR
input to XE1413
L2
3.9 nH
VDDM
C20
LPXO_IN
2.2 μF
PA_VDD
SPI_DATA_OUT
1 nF
SPI_DATA_IN
C9
VCO_VDD
C10
C11
4.7 pF
0.1 μF
VCO_TUNE
SPI_EN_BAR
MOD_REF
SPI_DATA_R2BB
SPI_DATA_BB2R
SPI_CLK_IN
C8
0.1 μF
SYS_CLK_OUT
C23
4.7pF
RX_DATA
TX_DATA
D_VDD_IO
VDDR
SPI_CLK
R1
Test conditions:
- VDDM = 3.0V
- ambient temperature 25°C
- xe1413 configured for usage of internal
analog and digital regulator
LPXO_OP
RX_DATA
TX_DATA
SLW_CLK_OUT
epoxy thickness: RF signal-ground
plane: 500um
IC
IC
XTAL_A
PCB material: FR4
2.2 μF
DREG_VDD
L3* 3.9 nH
VDDR
*
XE1413
PA_OUT
2
3
RX_EN
D_VDD
RF_INN
C4* 1.0 pF
TX_EN
C21
C7
1
1
IF_VDD
RF_INP
*
PWR_RST_BAR
RX_EN
XTAL_B
3
TX_EN
XTAL_VDD
AS21392
LNA_VDD
4.7 pF
4.7 pF
SYNC_DET
SYNC_DET
PWR_RST_BAR
PLL_VDD
5
4.7 pF
Y2
MIX_VDD
LOOP_FILT_SW
4
C3*
AREG_VDD
32kHz
0.1uF
C17 2.2 nF
VDDR
2.7 kΩ
6
4
C2* 4.7 pF
0.1 μF
100kΩ
R3 not populated
C24*
2.2pF
*
C22
C6
BT test equipment
- Anritsu MT8852A
- Agilent E1852B
AREG_OUT
REG_BG
2.2 μF
VDDR
BP 2520
4.7pF
2.2 μF
REG_PD
C12
1 nF
VDDM
C5
2
C14
C15
REG_PD
test points,
accessible on PCB
0.1 μF
RF_SWT
C16
RF_SWR
C13
pins not connected
R2
27kΩ
Bluetooth XE1413
Reference Design,
test setup
V1.0
Page 1/1
C24
4.7pF
Y1
13MHz
C19
SPI_EN_BAR
SYS_CLK
SLW_CLK
0.1 μF
C18 220 pF
Figure 17 - reference design, test setup
© Semtech 2006
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27
XE1413
Bluetooth® Radio
4.4 DATA RECEIVE AND TRANSMIT TIMING
Figure 18 and Figure 19 show the data receive and transmit timing diagrams, respectively.
RX_DATA
SYS_CLK_OUT (13 MHz)
13 samples of received data bit
Over sampled receive data transitions on the rising edge of SYS_CLK_OUT.
Baseband should sample receive data on the falling edge of SYS_CLK_OUT.
Figure 18 - RX_DATA vs. SYS_CLK_OUT Timing Diagram
1 μs
TX_DATA
(from Baseband)
First transmit bit
Internal XE1413 clock
(1 MHz)
TX_EN
(from Baseband)
First sampling edge occurs 180.5 μs
after TX_EN assertion
180 μs
Transmit data is sampled on the falling edge of the
internal 1 MHz sampling clock synchronized with TX_EN
Figure 19 - TX_DATA vs. TX_EN Timing Diagram
© Semtech 2006
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28
XE1413
Bluetooth® Radio
5
APPLICATION DIAGRAM
The Figure 20 shows a block diagram for a Bluetooth headset using the XE1413 radio.
An application schematic for a Bluetooth headset solution using the XE1413 and Semtech baseband and
application controller SX1441 is shown in Figure 21 and Figure 22.
Serial Flash
SPI
GPIO/UART
CODEC
Application
Processor
Bluetooth
Sequencer
GPIO
SX1441
Radio Interface
SEMTECH XE1413
Bluetooth Radio
Figure 20 - XE1413 and Semtech Bluetooth Headset Solution Block Diagram
LEGEND
VDDR
output from XE1413
VDDR
input to XE1413
*
C4 1.0 pF
LPXO_IN
LPXO_OP
IC
IF_VDD
IC
RX_DATA
TX_DATA
SPI_DATA_OUT
PA_VDD
C8
SPI_DATA_IN
1 nF
VDDM
C20
SPI_DATA_R2BB
2.2 μF
SPI_DATA_BB2R
VCO_VDD
C10
C11
4.7 pF
0.1 μF
VCO_TUNE
SPI_CLK_IN
C9
VDDR
SPI_EN_BAR
0.1 μF
SYS_CLK_OUT
MOD_REF
SLW_CLK_OUT
4.7pF
RX_DATA
TX_DATA
D_VDD_IO
epoxy thickness: RF signal-ground plane: 500um
SPI_CLK
R1
PRELIMINARY
Bluetooth Headset
Reference Design
V2.4
Page 1/2
2.2 μF
DREG_VDD
XTAL_A
*
XE1413
XTAL_B
C23
PCB material: FR4
RX_EN
D_VDD
L3* 3.9 nH
VDDR
TX_EN
C21
C7
L2* 3.9 nH
PWR_RST_BAR
RX_EN
PA_OUT
TBD
*
TX_EN
RF_INN
2
C1
LNA_VDD
RF_INP
4.7 pF
SYNC_DET
SYNC_DET
PWR_RST_BAR
XTAL_VDD
5
3
Y2
4.7 pF
1
3
0.1uF
PLL_VDD
4
AS21392
4.7 pF
32kHz
MIX_VDD
LOOP_FILT_SW
6
4
BP 2520
C3*
0.1 μF
REG_PD
C12
C17 2.2 nF
VDDR
2.7 kΩ
TBD
L1
C2* 4.7 pF
C22
100kΩ
R3 not populated
C6
2.2pF
AREG_VDD
2.2 μF
VDDR
C24*
AREG_OUT
REG_BG
C5
1
C14
4.7pF
1 nF
VDDM
Antenna
2
C15
2.2 μF
REG_PD
test points,
accessible on PCB
C13
0.1 μF
RF_SWT
C16
RF_SWR
pins not connected
R2
27kΩ
C24
4.7pF
Y1
13MHz
C19
SPI_EN_BAR
SYS_CLK
SLW_CLK
0.1 μF
C18 220 pF
Figure 21 - headset schematic, page 1/2
© Semtech 2006
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29
XE1413
Bluetooth® Radio
VDDM
VDDM
C42 0.1 μF
J1
SW2
CS_BAR
VCC
SO
HOLD_BAR
WP_BAR
SCK
SI
GND
VDDM
RX_DATA
RX_DATA
1kΩ
R37
1kΩ
TX_EN
TX_DATA
NSS[3]
TX_EN
NSS[4]
RX_EN
SYNC_DETECT
SPI_DATA_R2BB
SPI_DATA_BB2R
SPI_EN_BAR
SPI_CLK
SLW_CLK
SYS_CLK
SYNC_DETECT
SPI_DATA_IN
SPI_DATA_OUT
SPI_EN_BAR
SPI_CLK_OUT
SLW_CLOCK_IN
SYS_CLOCK_IN
C33
VREGA
VDD_ANA
R34
Regulated input voltage
PWR_RST_BAR
UA_CTS
UA_RTS
UA_TX
UA_RX
LEGEND
output from XE1431
input to XE1431
pins not connected
test points,
accessible on PCB
HCI_CTS
HCI_RTS
HCI_RX
HCI_TX
L30 470 μH
C40
1 μF
100 nF
VDD_DIG
VDD_PA
1 μF
VSS_PA
VSS_M
VSSIO_DIG
VSSIO
VSS_DIG
TP0
TP1
TP2
TP3
TP4
VREGD
VREF
VMIC_P
VDDM
C31 220 nF
C41
VMIC_N
220 nF
VDDIO
C32
R22
VDDM
SW3
PA_OUTP
VDDIO_DIG
1 μF
C43
C30
100 nF
SX1441
RX_EN
VDDBAT
Q1
1kΩ
VREG_OFF
R31
100kΩ
VDDA
R38
VDDM
WAKEUP
PB[0]
PB[1]
PB[2]
PB[3]
PB[4]
PB[5]
PB[6]
PB[7]
DBG[0]
DBG[1]
DBG[2]
DBG[3]
DBG[4]
DBG[5]
DBG[6]
DBG[7]
NSS[2]
R36
220 Ω
R33
NRESET
PA[0]
PA[1]
PA[2]
PA[3]
PA[4]
PA[5]
PA[6]
PA[7]
DOC_SDIO
DOC_SCK
NRESET
NSS[1]
MOSI
SCK
NSS[0]
MISO
SA25F010LMLF
TX_DATA
VDDM
SW1
220 Ω
VDDM
PA_OUTN
L21 470 μH
VDDM
C37
1 μF
REG_PD
VDDM VDDM VDDM
C34
0.1 μF
C35
0.1 μF
C36
1 μF
VDDD
VDDD
C38
4.7 μF
C39
1 μF
PRELIMINARY
Bluetooth Headset
Reference Design
V2.4
Page 2/2
Figure 22 - headset schematic, page 2/2
© Semtech 2006
All rights reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner.
The information presented in this document does not form part of any quotation or contract, is believed to be accurate and
reliable and may be changed without notice. No liability will be accepted by the publisher for any consequence of its use.
Publication thereof does not convey nor imply any license under patent or other industrial or intellectual property rights.
Semtech. assumes no responsibility or liability whatsoever for any failure or unexpected operation resulting from misuse,
neglect improper installation, repair or improper handling or unusual physical or electrical stress including, but not limited to,
exposure to parameters beyond the specified maximum ratings or operation outside the specified range.
SEMTECH PRODUCTS ARE NOT DESIGNED, INTENDED, AUTHORIZED OR WARRANTED TO BE SUITABLE FOR
USE IN LIFE-SUPPORT APPLICATIONS, DEVICES OR SYSTEMS OR OTHER CRITICAL APPLICATIONS. INCLUSION
OF SEMTECH PRODUCTS IN SUCH APPLICATIONS IS UNDERSTOOD TO BE UNDERTAKEN SOLELY AT THE
CUSTOMER’S OWN RISK. Should a customer purchase or use Semtech products for any such unauthorized application,
the customer shall indemnify and hold Semtech and its officers, employees, subsidiaries, affiliates, and distributors harmless
Contact Information
Semtech Corporation
Wireless and Sensing Products Division
200 Flynn Road, Camarillo, CA 93012
Phone (805) 498-2111 Fax : (805) 498-3804
© Semtech 2006
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