Maintenance/ Discontinued

For Audio Equipment
MN662724RPE
Signal Processing LSI for CD Players
Overview
Features
M
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(Optics servo)
Focus, tracking, and traverse servos
Automatic adjustment functions for FO/TR gain,
FO/TR offset, and FO/TR balance
Built-in D/A converter for drive voltage output
Built-in dropout countermeasures
Anti-shock functions
Built-in track cross counter
(Other)
Built-in playback pitch control function (normal
speed only)(±13%)
Built-in support for jitter-free disc rotation synchronization playback
Oscillator shutdown mode
Power management mode
Operating voltage 4.5 to 5.5V
Applications
CD Players
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The MN662724RPE is a CD signal processing LSI that,
on a single chip, combines an optics servo for the CD
player (focus, tracking, and traverse servos), digital signal processing (EFM demodulation and error correction),
and digital servo processing for the spindle motor.
(p
la
ne
(Digital signal processing)
Built-in DSL and PLL
Frame synchronization detection, holding, and
insertion
Subcode data processing
Q data CRC check
Built-in Q data register
CIRC error detection and correction
C1 decoder: duplex error correction
C2 decoder: triplex error correction
Built-in 16-K bits of RAM for de-interleaving
Audio data interpolation
Average, hold of previous values
Soft muting
Digital attenuation (256 levels)
Software attenuation (256 levels)
Auto cue detection function
Digital audio interface (EIAJ format)
Two audio data serial interfaces:
One switchable between bit rates of 64 fs and
48 fs; the other fixed at 48 f s.
(Spindle motor servo)
CLV digital servo
Switchable servo gain
ne
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BCLK
1
LRCK
2
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SRDATA
3
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DVDD1
4
n
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DVSS1
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6
TX
typ isc
7
MCLK
o
8
MDATA
e, nt
9
MLD
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10
SENSE
int ed
11
FLOCK
en in
12
TLOCK
an clu BLKCK
ce de SQCK 13
typ s f SUBQ 14
15
oll
e, DMUTE
16
o
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wi
ng 17
ne RST
18
d d fou 19
SMCK
PMCK
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BYTCK/TRVSTOP
CLDCK
FCLK
IPFLAG
FLAG
CLVS
CRC
DEMPH
FLAG6/RESY
SDAT48
TEST
AVDD1
LRCK48
AVSS1
BCLK48
RSEL
CSEL
PSEL
MSEL
SSEL
(p
la
M
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61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
(TOP VIEW)
QFS080-P-1414
LDON
BDO
RFDET
TRCRS
OFT
VDET
RFENV
TE
FE
TBAL
FBAL
VREF
FOD
TRD
KICK
ECS
ECM
PC
TVD
TRV
yp
e)
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
VDD
X2
X1
VSS
SBCK
SUBC
TOFS
PCK/DSLB
EFM/CK384
AVSS2
AVDD2
VCOF
PLLF
DSLF
DRF
IREF
ARF
WVEL
PLAY
PLLF2
MN662724RPE
For Audio Equipment
Pin Assignment
OFT
36
38
INPUT PORT
RFDET
BDO
39
A/D CONVERTER
35
17
VDET
19
63
20
77
79
59
58
DSL•PLL
VCO
DIGITAL
AUDIO
INTERFACE
16K
SRAM
SUBCODE
BUFFER
24
23
2
73
3
70
1
75
16
21
TRV
26
KICK
29
VREF
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MICROCOMPUTER
SUBCODE DEMODULATION
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INTERFACE
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DEINTERLEAVE
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CPU
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INTERPOLATION
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d d fou SOFT MUTING
CLV
isc r PDIGITAL
OUTPUT
D/A
SERVO
on roATTENUATION
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PORT
CONVERTER
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49
37
9
MLD
7
MCLK
8
MDATA
TRCRS
STAT
78
32
FE
33
TE
34
RFENV
SMCK
FCLK
PMCK
CSEL
MSEL
X2
X1
ne
VCOF
TIMING
GENERATOR
VCO
PITCH CONTROL
68
DEMPH
69
FLAG6/RESY
80
SSEL
14
SQCK
15
SUBQ
51
AVSS2
50
AVDD2
53
PCK/DSLB
52
EFM/CK384
48
PLLF
41
PLLF2
47
DSLF
45
IREF
46
DRF
44
ARF
76
RSEL
(p
la
M
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PSEL
60
57
4
5
18
71
CLVS
CRC
BLKCK
CLDCK
SBCK
SUBC
VDD
VSS
DVDD1
DVSS1
RST
TEST
For Audio Equipment
MN662724RPE
Block Diagram
66
67
13
62
56
55
74
AVSS1
72
AVDD1
65
FLAG
64
IPFLAG
SERVO
TIMING GENERATOR
6
61
25
22
27
28
31
30
12
11
42
40
54
TX
ECM
PC
LRCK
LRCK48
SRDATA
SDAT48
BCLK
BCLK48
DMUTE
BYTCK/TRVSTOP
ECS
TVD
TRD
FOD
TBAL
FBAL
TLOCK
FLOCK
PLAY
LDON
TOFS
43
WVEL
10
SENSE
MN662724RPE
For Audio Equipment
Pin Descriptions
Pin No.
1
Symbol
BCLK
I/O
O
Function Description
SRDATA bit clock output.
2
LRCK
O
Left/right channel discrimination signal output.
3
SRDATA
O
Serial data output.
4
DV DD1
I
Power supply for digital circuits.
5
DVSS1
I
Ground for digital circuits.
6
TX
O
Digital audio interface output signal.
7
MCLK
I
Microcomputer command clock input. (Data is latched at rising edge.)
8
MDATA
I
Microcomputer command data input.
9
MLD
I
Microcomputer command load signal input.
SENSE
O
Sense signal output. (OFT, FESL, NACEND, NAJEND, SFG, and NWTEND)
FLOCK
O
Focus servo pull-in signal.
"L" level: pull-in state.
12
TLOCK
O
Tracking servo pull-in signal.
"L" level: pull-in state.
13
BLKCK
O
Subcode block clock signal (fBLKCK=75Hz)
14
SQCK
I
15
SUBQ
O
16
DMUTE
I
17
STAT
O
External clock input for subcode Q register
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M
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10
"L" level: load.
Subcode Q data output
Muting input. (Effective only for an output bit rate of 64 fs) "H" level: muting.
Status signal.
(CRC, CUE, CLVS, TTSTOP, FCLV, SQOK, FLAG6, SENSE, FLOCK,
and TLOCK)
18
RST
I
19
SMCK
O
20
PMCK
O
21
TRV
O
22
TVD
O
23
PC
O
24
ECM
O
25
ECS
O
26
KICK
O
27
TRD
O
28
FOD
O
29
VREF
I
Reset input.
"L" level: reset.
If MSEL is "H" level, 8.4672 MHz clock signal is outputted.
If MSEL is "L" level, 4.2336 MHz clock signal is outputted.
88.2kHz clock signal output.
Traverse forced feed output.
(tristate)
Traverse drive output.
Spindle motor ON signal.
"L" level: ON (default).
Spindle motor drive signal (forced mode output). (tristate)
Spindle motor drive signal (servo error signal output)
Kick pulse output.
(tristate)
Tracking drive output.
Focus drive output.
Reference voltage for D/A output (TVD, ECS, TRD, FOD, FBAL, TBAL,
FBAL
O
31
TBAL
O
Tracking balance adjustment output.
32
FE
I
Focus error signal input.
(analog input)
33
TE
I
Tracking error signal input.
(analog input)
34
RFENV
I
RF envelope signal input.
(analog input)
35
VDET
I
Vibration detection signal input. "H" level: vibration detected.
36
OFT
I
Offtrack signal input.
"H" level: offtrack.
37
TRCRS
I
Track cross signal input.
(analog input)
ne
30
(p
la
and TOFS).
Focus balance adjustment output.
For Audio Equipment
MN662724RPE
Pins Descriptions (continued)
Pin No.
38
Symbol
RFDET
I/O
I
39
BDO
I
40
41
LDON
PLLF2
O
I/O
Function Description
RF detection signal input.
"L" level: detected.
Dropout signal input.
"H" level: dropout
Laser ON signal output.
"H" level: ON.
PLL loop-filter characteristic switching pin.
42
PLAY
O
Play signal output.
"H" level: play.
43
WVEL
O
Double-speed status signal output.
"H" level: double-speed.
44
ARF
I
RF signal input.
45
IREF
I
Reference current input pin
DSL bias pin.
DRF
I
47
DSLF
I/O
DSL loop-filter pin.
48
PLLF
I/O
PLL loop-filter pin.
49
VCOF
I/O
VCO loop-filter pin.
50
AV DD2
I
M
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46
51
AV SS2
I
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converter).
yp
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Power supply for analog circuits (DSL, PLL, D/A converter output, and A/D
Ground for analog circuits (DSL, PLL, D/A converter output, and A/D
converter).
52
EFM
O
or CK384
EFM signal output.
• EFM output.
• Crystal oscillator 16.9344 MHz output.
• 384 fs output from signal processing block. (During
variable-pitch operation, this is the VCO clock.)
Commands permit switching among the above three outputs.
53
PCK
O
or DSLB
54
TOFS
O
55
SUBC
O
56
SBCK
I
57
VSS
I
58
X1
I
59
X2
O
60
VDD
I
BYTCK or
O
61
Tracking offset adjustment output.
Subcode serial output.
Clock input for subcode serial output.
Ground for oscillator circuit.
Crystal oscillator circuit input pin.
f=16.9344MHz, 33.8688MHz
Crystal oscillator circuit output pin.
f=16.9344MHz, 33.8688MHz
Oscillator circuit power supply.
During default operation, byte clock signal output.
During command execution, traverse stop signal output. "H" level: stop mode.
CLDCK
O
63
FCLK
O
64
IPFLAG
O
Interpolation flag signal output.
65
FLAG
O
Flag signal output.
66
CLVS
O
Spindle servo phase synchronization signal output. "H" level: CLV.
ne
62
(p
la
TRVSTOP
f PCK=4.3218MHz
Clock for PLL or DSL balance output.
Subcode frame clock signal output pin.
(f CLDCK=7.35kHz)
Crystal frame clock signal output.
(f FCLK=7.35kHz)
"H" level: interpolation.
"L" level: rough servo.
67
CRC
O
Subcode CRC check result output.
"H" level: OK. "L" level: no good.
68
DEMPH
O
De-emphasis detection signal output.
"H" level: on.
MN662724RPE
For Audio Equipment
Pin Descriptions (continued)
Pin No.
69
Symbol
FLAG6
I/O
O
Function description
During default operation, FLAG6 output, that is the resetting signal for the
or RESY
address of RAM used to de-interleave error correction data. "L" level: address reset.
During command execution, RESY output, that is the frame resynchronization
signal. "H" level: synchronized.
70
SDAT48
O
"L" level: out of sync.
Serial data output for bit rate 48 fs.
TEST
I
Test pin.
72
AV DD1
I
Power supply for digital circuits.
Keep this at "H" level.
73
LRCK48
O
Left/right channel discrimination signal output for bit rate 48 fs.
74
AVSS1
I
Ground for digital circuits.
75
BCLK48
O
Bit clock output for bit rate 48 f s.
M
Di ain
sc te
on na
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71
76
RSEL
I
RF signal polarity selection pin.
"H" level: bright level is "H."
77
CSEL
I
Crystal oscillator frequency specification pin.
78
PSEL
I
79
MSEL
I
"L" level: bright level is "L."
yp
e)
"H" level: 33.8688 MHz.
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"L" level: 16.9344 MHz
Test pin.
SMCK pin output.
Keep this at "L" level.
SMCK frequency selection pin.
"H" level: 8.4672 MHz.
"L" level: 4.2336 MHz.
I
SUBQ pin output mode selection pin.
"H" level: Buffered Q code mode.
"L" level: CLDCK synchronization mode.
ne
SSEL
(p
la
80
ne
(p
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80
21
1
20
0.65
0.15
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61
0.825
M
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For Audio Equipment
MN662724RPE
Package Dimensions (Unit: mm)
QFS080-P-1414
16.2±0.2
14.0±0.2
60
41
40
0.3 -0.05
+0.10
SEATING PLANE
1.1±0.1
0.55±0.1
Request for your special attention and precautions in using the technical information and
semiconductors described in this book
(1) If any of the products or technical information described in this book is to be exported or provided to non-residents, the laws and
regulations of the exporting country, especially, those with regard to security export control, must be observed.
(2) The technical information described in this book is intended only to show the main characteristics and application circuit examples
of the products, and no license is granted under any intellectual property right or other right owned by our company or any other
company. Therefore, no responsibility is assumed by our company as to the infringement upon any such right owned by any other
company which may arise as a result of the use of technical information described in this book.
(3) The products described in this book are intended to be used for standard applications or general electronic equipment (such as office
equipment, communications equipment, measuring instruments and household appliances).
Consult our sales staff in advance for information on the following applications:
– Special applications (such as for airplanes, aerospace, automobiles, traffic control equipment, combustion equipment, life support
systems and safety devices) in which exceptional quality and reliability are required, or if the failure or malfunction of the products may directly jeopardize life or harm the human body.
– Any applications other than the standard applications intended.
M
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sc te
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(4) The products and product specifications described in this book are subject to change without notice for modification and/or improvement. At the final stage of your design, purchasing, or use of the products, therefore, ask for the most up-to-date Product
Standards in advance to make sure that the latest specifications satisfy your requirements.
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(5) When designing your equipment, comply with the range of absolute maximum rating and the guaranteed operating conditions
(operating power supply voltage and operating environment etc.). Especially, please be careful not to exceed the range of absolute
maximum rating on the transient state, such as power-on, power-off and mode-switching. Otherwise, we will not be liable for any
defect which may arise later in your equipment.
Even when the products are used within the guaranteed values, take into the consideration of incidence of break down and failure
mode, possible to occur to semiconductor products. Measures on the systems such as redundant design, arresting the spread of fire
or preventing glitch are recommended in order to prevent physical injury, fire, social damages, for example, by using the products.
(6) Comply with the instructions for use in order to prevent breakdown and characteristics change due to external factors (ESD, EOS,
thermal stress and mechanical stress) at the time of handling, mounting or at customer's process. When using products for which
damp-proof packing is required, satisfy the conditions, such as shelf life and the elapsed time since first opening the packages.
(p
lan
(7) This book may be not reprinted or reproduced whether wholly or partially, without the prior written permission of Matsushita
Electric Industrial Co., Ltd.