RT3669EA - Richtek

RT3669EA
Single Channel PWM Controller with 1 Integrated Driver and 1
LDO Regulator for AMD SVI2 GFX and FCH Power Supply
General Description
Features
RT3669EA is a single channel PWM controller with 1
integrated driver and 1 LDO regulator, it is compliant
with AMD SVI2 Voltage Regulator Specification to
support FP4 GFX power (VDDCR_GFX) and FCH
power (VDDCR_FCH_S5). The RT3669EA features
CCRCOT (Constant Current Ripple Constant On-Time)
with G-NAVP (Green-Native AVP), which is Richtek's
proprietary topology. G-NAVP makes it an easy setting

controller to meet all AMD AVP (Adaptive Voltage
Positioning) GFX requirements. The droop is easily
programmed by setting the DC gain of the error
amplifier. With proper compensation, the load transient
response can achieve optimized AVP performance. The
controller also uses the interface to issue VOTF
Complete and to send digitally encoded voltage and
current values for the GFX domains. The RT3669EA
can operate in diode emulation mode to enhance the
light load efficiency. And it provides the current gain
adjustment capability by pin setting. RT3669EA also
provides power good indication, thermal indication
(VRHOT_L), and it features complete fault protection
functions including over current, over voltage and under
voltage.










1-Phase (VDDCR_GFX) PWM Controller
1 Embedded MOSFET Driver
1 LDO Regulator for FCH
G-NAVPTM Topology
Support Dynamic Load-Line and Zero Load-Line
Diode Emulation Mode at Light Load Condition
SVI2 Interface to Comply with AMD Power
Management Protocol
Adjustable Current Gain Capability
DVID Enhancement
0.5% DAC Accuracy
Differential Remote Voltage Sensing

Build-in ADC for Pin Setting Programming,
Thermal Indication and VOUT, IOUT Reporting

Fast Transient Response
Power Good Indicator
Thermal Indicator (VRHOT_L)
OVP, UVP and UVLO
Over Current Protection




Applications

AMD FP4 GFX and FCH Power
Simplified Application Circuit
RT3669EA
VRHOT_L
PHASE
MOSFET
VVDDCR_GFX
SVC
To GFX
LDO_IN
SVD
SVT
LDO_OUT
VIN_LDO
VOUT_LDO
MUX_CTRL
VVDDNB
VSEN_NB_IN
Copyright © 2017 Richtek Technology Corporation. All rights reserved.
DS3669EA-02
March 2017
S5_OUT
VVDDCR_FCH_S5
is a registered trademark of Richtek Technology Corporation.
www.richtek.com
1
RT3669EA
Ordering Information
Pin Configuration
RT3669EA
(TOP VIEW)
Richtek products are :

RoHS compliant and compatible with the current
requirements of IPC/JEDEC J-STD-020.

Suitable for use in SnPb or Pb-free soldering processes.
Marking Information
3A=YM
DNN
3A= : Product Code
YMDNN : Date Code
32 31 30 29 28 27 26 25
VIN
RGND
COMP
FB
VSEN
ISEN1P
ISEN1N
VRHOT_L
1
24
2
23
3
22
4
21
GND
5
6
20
33
7
19
18
8
17
LDO_VIN
MUX_CTRL
FBA
LDO_OUT
S5_OUT
VSEN_NB_IN
VDDIO
SVT
9 10 11 12 13 14 15 16
TSEN
SET1
IMON
VREF_PINSET
VCC
PWROK
SVC
SVD
Note :
EN
PGOOD
NC
LGATE
PVCC
PHASE
UGATE
BOOT
Package Type
QW : WQFN-32L 4x4 (W-Type)
Lead Plating System
G : Green (Halogen Free and Pb Free)
WQFN-32L 4x4
Functional Pin Description
Pin No.
Pin Name
Pin Function
1
VIN
VIN input pin. Connect a low pass filter to this pin.
2
RGND
Return ground of GFX controller. This pin is the common negative input of
output voltage differential remote sense of GFX controller.
3
COMP
Error amplifier output pin of the GFX controller.
4
FB
Output voltage feedback input of GFX controller. This pin is the negative input
of the error amplifier for the GFX controller.
5
VSEN
GFX controller voltage sense input. This pin is connected to the terminal of
GFX controller output voltage.
6
ISEN1P
Positive current sense input for GFX controller.
7
ISEN1N
Negative current sense input for GFX controller.
8
VRHOT_L
Thermal indicator. This pin is an open drain output. (Active low)
9
TSEN
This pin provides two functions : platform setting, platform can use this pin to
set frequency, initial offset and per-phase OCP threshold of GFX Controller.
The other function is thermal sense input for VRHOT indicator, so this pin
must to be connected to the NTC network for thermal sense.
10
SET1
Platform setting pin. Platform can use this pin to set AI gain, QRTH of GFX
Controller.
11
IMON
Current monitor output for the GFX controller. This pin outputs a voltage
proportional to the output current.
12
This pin provides two functions : The 3.2V power supply for pin setting
function divided resistors. The other function is fixed 0.8V output reference
VREF_PINSET voltage, and the voltage is only used to offset the output voltage of IMON pin.
Connect a RC circuit from this pin to GND. The recommended resistor is from
3.9 to 10, and the capacitor is 0.47F.
Copyright © 2017 Richtek Technology Corporation. All rights reserved.
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is a registered trademark of Richtek Technology Corporation.
DS3669EA-02
March 2017
RT3669EA
Pin No.
Pin Name
Pin Function
VCC
Controller power supply. Connect this pin to 5V and place a decoupling
capacitor 2.2F at least. The decoupling capacitor is as close controller as
possible.
14
PWROK
System power good input. If PWROK is low, the SVI interface is disabled and
VR returns to BOOT-VID state with initial load-line slope and initial offset. If
PWROK is high, the SVI interface is running and the DAC decodes the
received serial VID codes to determine the output voltage.
15
SVC
Serial VID clock input.
16
SVD
Serial VID data input. This pin is a serial data line.
17
SVT
Serial VID telemetry output from VR. This pin is a push-pull output.
18
VDDIO
Processor memory interface power rail and serves as the reference for
PWROK, SVD, SVC and SVT. This pin is used by the VR to reference the
SVI pins.
19
VSEN_NB_IN
This pin is connected to the output of VDDNB controller.
20
S5_OUT
FCH power output.
21
LDO_OUT
LDO output.
22
FBA
LDO output voltage feedback input.
23
MUX_CTRL
MUX control input. When the pin pulled high, the S5_OUT output voltage is
forced to VSEN_NB_IN pin voltage. If the pin pulled low, the S5_OUT output
voltage is forced to VSEN_NB_IN pin voltage when the VSEN_NB_IN
voltage is greater than LDO_OUT voltage; otherwise, the S5_OUT voltage is
forced to LDO_OUT pin voltage.
24
LDO_VIN
LDO power input.
25
BOOT
Bootstrap supply of GFX controller for high-side MOSFET. This pin powers
high-side MOSFET driver.
26
UGATE
27
PHASE
28
PVCC
29
LGATE
Lower Gate Driver Output of GFX Controller. Connect this pin to the gate
input of low-side MOSFET.
30
NC
No internal connection.
31
PGOOD
Power good indicator for the GFX controller. This pin is an open drain output.
32
EN
Controller enable input pin.
13
33 (Exposed Pad) GND
Upper gate driver output of GFX controller. Connect this pin to the gate input
of high-side MOSFET.
Switch nodes of high-side driver for GFX controller. Connect this pin to highside MOSFET Source together with the low-side MOSFET Drain and the
inductor.
Driver power supply. Connect this pin to GND by the 2.2F ceramic capacitor
at least. The decoupling capacitor is as close controller as possible.
Ground. The exposed pad must be soldered to a large PCB and connected
to GND for maximum power dissipation.
Copyright © 2017 Richtek Technology Corporation. All rights reserved.
DS3669EA-02
March 2017
is a registered trademark of Richtek Technology Corporation.
www.richtek.com
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RT3669EA
VRHOT_L
PGOOD
VCC
EN
PWROK
VDDIO
SVT
SVD
SVC
TSEN
VSEN
IMONI
SET1
Functional Block Diagram
UVLO
GND
MUX
SVI2 Interface
Configuration Registers
Control Logic
ADC
From Control Logic
RGND
Loop Control
Protection Logic
AI_GFX
QR_TH
TONSET
OFFSET
PHOCP_TH
DAC
VIN
Soft Start&
Slew Rate Control
VSET
+
ERROR
AMP
Offset
Cancellation
-
+
+
FB
-
COMP
PWM
CMP
1.867m
ISEN1P
+
ISEN1N
-
BOOT
TON
GEN
PWM
Driver
PHASE
QR_TH
0.75 x AI_VDD
UGATE
LGATE
TONSET
RAMP
+
-
VREF_PINSET
IMON
VSEN
IMONI
OV/UV
+
OCP_SPIKE
Driver
POR
PVCC
OC
To Protection Logic
-
LDO
MUX_CTRL
VCC
+
VSEN_NB_IN
40mV
CMP
LDO_VIN
+
OP
-
+
-
LDO_OUT
-
0.4V
LDO_OUT
LDO_OUT
+
-
10mV
VSEN_NB_IN
FBA
0
POWER
_MUX
1
S5_OUT
Operation
The RT3669EA adopts G-NAVPTM (Green Native AVP)
which is Richtek's proprietary topology derived from
MUX and ADC
finite DC gain of EA amplifier with current mode control,
making it easy to set the droop to meet all AMD GFX
requirements of AVP (Adaptive Voltage Positioning).
The G-NAVPTM controller is one type of current mode
constant on-time control with DC offset cancellation.
The approach can not only improve DC offset problem
for increasing system accuracy but also provide fast
transient response. When current feedback signal
reaches COMP signal, it generates an on-time width
to achieve PWM modulation.
IMONI and VSEN. The ADC converts these analog
signals to digital codes for reporting or performance
adjustment.
Copyright © 2017 Richtek Technology Corporation. All rights reserved.
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The MUX supports the inputs from SET1, TSEN,
SVI2 Interface/Configuration Registers/Control
Logic
The SVI2 interface uses the SVC, SVD, and SVT pins
to communicate with GFX. The configuration registers
save the digital data from ADC output for reporting or
performance adjustment. The Control Logic controls
is a registered trademark of Richtek Technology Corporation.
DS3669EA-02
March 2017
RT3669EA
the ADC timing and generates the digital code of the
VID for VSEN voltage.
Loop Control Protection Logic
Loop control protection logic detects EN and UVLO
signals to initiate the soft-start function, and the
PGOOD and VRHOT_L will be controlled after the
soft-start is finished. When VRHOT indication event
occurs, the VRHOT_L pin voltage will be pulled low.
DAC
The DAC receives VID codes from the SVI2 control
logic to generate an internal reference voltage (VSET)
for controller.
RAMP
The Ramp generator is designed to improve noise
immunity and reduce jitter.
OC/OV/UV
VSEN and output current are sensed for over current,
over voltage and under voltage protection.
LDO
The LDO regulates its output voltage (LDO_OUT) with
the fixed reference voltage (0.4V). And the external
resistors connected to FBA pin can be adjust to
change the output voltage.
POWER_MUX
Soft-Start and Slew-Rate Control
This block controls the slew rate of the internal
reference voltage when output voltage changes.
Error Amplifier
If MUX_CTRL = High, then S5_OUT = VSEN_NB_IN.
If MUX_CTRL = Low, S5_OUT = VSEN_NB_IN or
LDO_OUT, refer to MUX description of Application
Information.
Error amplifier generates COMP signal by the
difference between VSET and FB.
Offset Cancellation
This block cancels the output offset voltage from
voltage ripple and current ripple to achieve accurate
output voltage.
UVLO
Detect the VCC pin voltage for under voltage lockout
protection and power on reset operation.
PWM CMP
The PWM comparator compares COMP signal and
current feedback signal to generate a signal for
TONGEN.
TONGEN
This block generates an on-time pulse which high
interval is based on the on-time setting and current
balance.
Copyright © 2017 Richtek Technology Corporation. All rights reserved.
DS3669EA-02
March 2017
is a registered trademark of Richtek Technology Corporation.
www.richtek.com
5
RT3669EA
Table 1. Serial VID Codes
SVID [7:0]
Voltage (V)
SVID [7:0]
Voltage (V)
SVID [7:0]
Voltage (V)
SVID [7:0]
Voltage (V)
0000_0000
1.55000
0010_0111
1.30625
0100_1110
1.06250
0111_0101
0.81875
0000_0001
1.54375
0010_1000
1.30000
0100_1111
1.05625
0111_0110
0.81250
0000_0010
1.53750
0010_1001
1.29375
0101_0000
1.05000
0111_0111
0.80625
0000_0011
1.53125
0010_1010
1.28750
0101_0001
1.04375
0111_1000
0.80000
0000_0100
1.52500
0010_1011
1.28125
0101_0010
1.03750
0111_1001
0.79375
0000_0101
1.51875
0010_1100
1.27500
0101_0011
1.03125
0111_1010
0.78750
0000_0110
1.51250
0010_1101
1.26875
0101_0100
1.02500
0111_1011
0.78125
0000_0111
1.50625
0010_1110
1.26250
0101_0101
1.01875
0111_1100
0.77500
0000_1000
1.50000
0010_1111
1.25625
0101_0110
1.01250
0111_1101
0.76875
0000_1001
1.49375
0011_0000
1.25000
0101_0111
1.00625
0111_1110
0.76250
0000_1010
1.48750
0011_0001
1.24375
0101_1000
1.00000
0111_1111
0.75625
0000_1011
1.48125
0011_0010
1.23750
0101_1001
0.99375
1000_0000
0.75000
0000_1100
1.47500
0011_0011
1.23125
0101_1010
0.98750
1000_0001
0.74375
0000_1101
1.46875
0011_0100
1.22500
0101_1011
0.98125
1000_0010
0.73750
0000_1110
1.46250
0011_0101
1.21875
0101_1100
0.97500
1000_0011
0.73125
0000_1111
1.45625
0011_0110
1.21250
0101_1101
0.96875
1000_0100
0.72500
0001_0000
1.45000
0011_0111
1.20625
0101_1110
0.96250
1000_0101
0.71875
0001_0001
1.44375
0011_1000
1.20000
0101_1111
0.95625
1000_0110
0.71250
0001_0010
1.43750
0011_1001
1.19375
0110_0000
0.95000
1000_0111
0.70625
0001_0011
1.43125
0011_1010
1.18750
0110_0001
0.94375
1000_1000
0.70000
0001_0100
1.42500
0011_1011
1.18125
0110_0010
0.93750
1000_1001
0.69375
0001_0101
1.41875
0011_1100
1.17500
0110_0011
0.93125
1000_1010
0.68750
0001_0110
1.41250
0011_1101
1.16875
0110_0100
0.92500
1000_1011
0.68125
0001_0111
1.40625
0011_1110
1.16250
0110_0101
0.91875
1000_1100
0.67500
0001_1000
1.40000
0011_1111
1.15625
0110_0110
0.91250
1000_1101
0.66875
0001_1001
1.39375
0100_0000
1.15000
0110_0111
0.90625
1000_1110
0.66250
0001_1010
1.38750
0100_0001
1.14375
0110_1000
0.90000
1000_1111
0.65625
0001_1011
1.38125
0100_0010
1.13750
0110_1001
0.89375
1001_0000
0.65000
0001_1100
1.37500
0100_0011
1.13125
0110_1010
0.88750
1001_0001
0.64375
0001_1101
1.36875
0100_0100
1.12500
0110_1011
0.88125
1001_0010
0.63750
0001_1110
1.36250
0100_0101
1.11875
0110_1100
0.87500
1001_0011
0.63125
0001_1111
1.35625
0010_0110
1.11250
0110_1101
0.86875
1001_0100
0.62500
0010_0000
1.35000
0100_0111
1.10625
0110_1110
0.86250
1001_0101
0.61875
0010_0001
1.34375
0100_1000
1.10000
0110_1111
0.85625
1001_0110
0.61250
0010_0010
1.33750
0100_1001
1.09375
0111_0000
0.85000
1001_0111
0.60625
0010_0011
1.33125
0100_1010
1.08750
0111_0001
0.84375
1001_1000
0.60000
0010_0100
1.32500
0100_1011
1.08125
0111_0010
0.83750
1001_1001
0.59375
Copyright © 2017 Richtek Technology Corporation. All rights reserved.
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is a registered trademark of Richtek Technology Corporation.
DS3669EA-02
March 2017
RT3669EA
SVID [7:0]
Voltage (V)
SVID [7:0]
Voltage (V)
SVID [7:0]
Voltage (V)
SVID [7:0]
Voltage (V)
0010_0101
1.31875
0100_1100
1.07500
0111_0011
0.83125
1001_1010
0.58750
0010_0110
1.31250
0100_1101
1.06875
0111_0100
0.82500
1001_1011
0.58125
1001_1100
0.57500
1011_0101 *
0.41875
1100_1110 *
0.26250
1110_0111*
0.10625
1001_1101
0.56875
1011_0110 *
0.41250
1100_1111 *
0.25625
1110_1000*
0.10000
1001_1110
0.56250
1011_0111 *
0.40625
1101_0000 *
0.25000
1110_1001*
0.09375
1001_1111
0.55625
1011_1000 *
0.40000
1101_0001 *
0.24375
1110_1010*
0.08750
1010_0000
0.55000
1011_1001 *
0.39375
1101_0010 *
0.23750
1110_1011*
0.08125
1010_0001
0.54375
1011_1010 *
0.38750
1101_0011 *
0.23125
1110_1100*
0.07500
1010_0010
0.53750
1011_1011 *
0.38125
1101_0100 *
0.22500
1110_1101*
0.06875
1010_0011
0.53125
1011_1100 *
0.37500
1101_0101 *
0.21875
1110_1110*
0.06250
1010_0100
0.52500
1011_1101 *
0.36875
1101_0110 *
0.21250
1110_1111*
0.05625
1010_0101
0.51875
1011_1110 *
0.36250
1101_0111 *
0.20625
1111_0000*
0.05000
1010_0110
0.51250
1011_1111 *
0.35625
1101_1000 *
0.20000
1111_0001*
0.04375
1010_0111
0.50625
1100_0000 *
0.35000
1101_1001 *
0.19375
1111_0010*
0.03750
1010_1000 *
0.50000
1100_0001 *
0.34375
1101_1010 *
0.18750
1111_0011*
0.03125
1010_1001 *
0.49375
1100_0010 *
0.33750
1101_1011 *
0.18125
1111_0100*
0.02500
1010_1010 *
0.48750
1100_0011 *
0.33125
1101_1100 *
0.17500
1111_0101*
0.01875
1010_1011 *
0.48125
1100_0100 *
0.32500
1101_1101 *
0.16875
1111_0110*
0.01250
1010_1100 *
0.47500
1100_0101 *
0.31875
1101_1110 *
0.16250
1111_0111*
0.00625
1010_1101 *
0.46875
1100_0110 *
0.31250
1101_1111 *
0.15625
1111_1000*
0.00000
1010_1110 *
0.46250
1100_0111 *
0.30625
1110_0000*
0.15000
1111_1001*
OFF
1010_1111 *
0.45625
1100_1000 *
0.30000
1110_0001*
0.14375
1111_1010*
OFF
1011_0000 *
0.45000
1100_1001 *
0.29375
1110_0010*
0.13750
1111_1011*
OFF
1011_0001 *
0.44375
1100_1010 *
0.28750
1110_0011*
0.13125
1111_1100*
OFF
1011_0010 *
0.43750
1100_1011 *
0.28125
1110_0100*
0.12500
1111_1101*
OFF
1011_0011 *
0.43125
1100_1100 *
0.27500
1110_0101*
0.11875
1111_1110*
OFF
1011_0100 *
0.42500
1100_1101 *
0.26875
1110_0110*
0.11250
1111_1111*
OFF
* Indicates TOB is 80mV for this VID code; unconditional VR controller stability required at all VID codes
Table 2. SET1 Pin Setting for GFX Controller AI Gain Ratio
SET1 Pin Setting Voltage

RD 
 VSET1_DIV  3.2 

RU  RD 

Min
Typical
Max
Unit
0
174
397
mV
25%
400
574
798
mV
50%
801
974
1198
mV
100%
1201
1374
1598
mV
0LL
Copyright © 2017 Richtek Technology Corporation. All rights reserved.
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AI_GFX
March 2017
is a registered trademark of Richtek Technology Corporation.
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RT3669EA
Table 3. SET1 Pin Setting for GFX Controller QR Threshold

RU  RD 
 VSET1_IR  80μ 

RU  RD 

SET1 Pin Setting Voltage
QR Threshold
(GFX)
Min
Typical
Max
Unit
801
850
898
mV
Disable
1001
1050
1098
mV
20mV
1101
1150
1198
mV
25mV
Table 4. TSEN Pin Setting for GFX Controller Frequency, Initial Offset and PHOCP Setting Ratio
TSEN Pin Setting Voltage

RD 
 VTSEN_DIV  3.2 

RU  RD 

Min
Typical
Max
Unit
0
23
47
mV
50
74
97
mV
200
224
247
mV
250
274
297
mV
400
424
447
mV
450
474
497
mV
601
624
648
mV
651
674
698
mV
801
824
848
mV
851
874
898
mV
1001
1024
1048
mV
1051
1074
1098
mV
1201
1225
1248
mV
1251
1275
1298
mV
1401
1425
1448
mV
1451
1475
1498
mV
PHOCP_TH = OCP_SPIKE × (PHOCP Setting Ratio) / M
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Frequency
(GFX)
Initial Offset
(GFX)
GFX PHOCP
Setting Ratio
(Percentage of
OCP_SPIKE)
25mV
0mV
300kHz
25mV
50mV
25mV
0mV
400kHz
25mV
50mV
150%
200%
150%
200%
150%
200%
150%
200%
150%
200%
150%
200%
150%
200%
150%
200%
(M : Phase Number)
is a registered trademark of Richtek Technology Corporation.
DS3669EA-02
March 2017
RT3669EA
Absolute Maximum Ratings
(Note 1)

VCC to GND ------------------------------------------------------------------------------------------------- 0.3V to 6.5V

PVCC to GND ----------------------------------------------------------------------------------------------- 0.3V to 6V

RGND to GND ---------------------------------------------------------------------------------------------- 0.3V to 0.3V

BOOT to PHASE ------------------------------------------------------------------------------------------- 0.3V to 6V

PHASE to GND
DC-------------------------------------------------------------------------------------------------------------- 0.3V to 32V
< 100ns ------------------------------------------------------------------------------------------------------- 8V to 38V

UGATE to PHASE
DC-------------------------------------------------------------------------------------------------------------- 0.3V to 6V
< 100ns ------------------------------------------------------------------------------------------------------- 5V to 7.5V

LGATE to GND
DC-------------------------------------------------------------------------------------------------------------- 0.3V to 6V
< 100ns ------------------------------------------------------------------------------------------------------- 2.5V to 7.5V

Other Pins ---------------------------------------------------------------------------------------------------- 0.3V to (VCC + 0.3V)

Power Dissipation, PD @ TA = 25C
WQFN32L 4x4--------------------------------------------------------------------------------------------- 3.59W

Package Thermal Resistance
(Note 2)
WQFN32L 4x4, JA--------------------------------------------------------------------------------------- 27.8C/W
WQFN32L 4x4, JC -------------------------------------------------------------------------------------- 7C/W

Lead Temperature (Soldering, 10 sec.) --------------------------------------------------------------- 260C

Junction Temperature ------------------------------------------------------------------------------------- 150C

Storage Temperature Range ---------------------------------------------------------------------------- 65C to 150C

ESD Susceptibility
(Note 3)
HBM (Human Body Model) ------------------------------------------------------------------------------ 2kV
Recommended Operating Conditions
(Note 4)

Supply Voltage, VCC -------------------------------------------------------------------------------------- 4.5V to 5.5V

Supply Voltage, PVCC ------------------------------------------------------------------------------------ 4.5V to 5.5V

Supply Voltage, VIN --------------------------------------------------------------------------------------- 4.5V to 26V

Ambient Temperature Range---------------------------------------------------------------------------- 40C to 85C

Junction Temperature Range --------------------------------------------------------------------------- 40C to 125C
Copyright © 2017 Richtek Technology Corporation. All rights reserved.
DS3669EA-02
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9
RT3669EA
Electrical Characteristics
(VCC = 5V, TA = 25C, unless otherwise specified)
Parameter
Symbol
Test Conditions
Min
Typ
Max
Unit
4.5
5
5.5
V
Input Power Supply
Supply Voltage
VCC
Supply Current
IVCC
EN = 3V, not switching
--
9
15
mA
Shutdown Current
ISHDN
EN = 0V
--
--
100
A
PVCC Supply Voltage
VPVCC
4.5
5
5.5
V
PVCC Supply Current
IPVCC
VBOOTX = 5V, not switching
--
120
--
A
VPOR_r
PVCC POR rising
--
3.85
4.1
V
VPOR_f
PVCC POR falling
3.4
3.65
--
V
100
200
350
mV
0.795
0.8
0.805
V
VDAC = 1.0000 to 1.5500
(no load, CCM mode)
0.5
0
0.5
%
SVID
VDAC = 0.8000 to 1.0000
5
0
5
mV
VDAC = 0.3000 to 0.8000
8
0
8
mV
VDAC = 0.2500 to 0.3000
80
0
80
mV
--
--
200
A
7.5
10
15
mV/s
4
--
4
mV
Driver Power On Reset (Driver POR)
Driver POR Threshold
Driver POR Hysteresis
VPOR_Hys
Reference and DAC
Reference Voltage Output
DC Accuracy
VREF
VFB
Reference and DAC
RGND Current
IRGND
EN = 3V, not switching
SR
SetVID fast
Slew Rate
Dynamic VID slew rate
Error Amplifier
Input Offset
VEAOFS
DC Gain
ADC
RL = 47k
70
80
--
dB
Gain-Bandwidth Product
GBW
CLOAD = 5pF
--
5
-
MHz
Output Voltage Range
VCOMP
RLOAD = 47k
0.3
--
3.6
V
EA Source/Sink Current
IEA,SRC /
IEA,SNK
--
5
--
mA
0.4
--
0.4
mV
Current Sense Amplifier
Input Offset Voltage
VOSCS
Impedance at Neg. Input
RISENxN
1
--
--
M
Impedance at Pos. Input
RISENxP
1
--
--
M
Input Range
VISEN_IN
VDAC = 1.1V,
(ISENxP ISENxN)
40
--
40
mV
Current Sense Gain Error
AISEN_Err
VDAC = 1.1V
2
--
2
%
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is a registered trademark of Richtek Technology Corporation.
DS3669EA-02
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RT3669EA
Parameter
Symbol
Test Conditions
Min
Typ
Max
VIH_EN
2
--
--
VIL_EN
--
--
0.8
ILEK_EN
1
--
1
Unit
EN and Logic Inputs
EN Threshold
Leakage Current of EN
SVC, SVD, PWROK
Hysteresis of SVC, SVD,
PWROK
V
A
VIH_SVI
Respect to VDDIO
70
--
100
VIH_SVI
Respect to VDDIO
0
--
35
VHYS_SVI
Respect to VDDIO
10
--
--
%
f SVC
(Note 5)
0.1
--
30
MHz
%
SVI2 Bus
SVC Frequency
Thermal Management
VRHOT Indicator Threshold
VTH_VRHOT
2.16
2.2
2.24
V
VRHOT Indicator Hysteresis
VHYS_VRHOT
50
75
100
mV
150
175
200
ns
--
250
400
ns
--
80
--
A
3.9
4.1
4.3
V
--
200
--
mV
1.8
1.85
1.9
V
0.3
1
3
s
600
500
400
mV
0.5
3
7
s
46.55
49
51.45
A
8
14
20
s
0.1
0.5
1
s
0
--
0.2
V
2
--
--
s
TON Setting
On-Time Setting
tON
Minimum Off Time
tOFF
VIN = 19V,VDAC = 1V,
[PSI0_L:PSI1_L]=00
(Note 6)
VDAC = 1V
ITSEN
VCC = 5V
Under Voltage Lockout
Threshold
VUVLO
VCC falling edge
Under Voltage Lockout
Hysteresis
VUVLO
Over Voltage Protection
Threshold
VOVP
Delay of OVP
tOVP
VSEN rising above
threshold
Under Voltage Protection
Threshold
VUVP
Respect to VID voltage
Delay of UVP
tUVP
VSEN falling below
threshold
OCP_SPIKE Threshold
IOCP_SPIKE
DCR = 1.1m,
RIMON = 7.95k
ITSEN
TSEN Source Current
Protection
OCP_SPIKE Trigger Delay
Delay of Per Phase OCP
tOCPSPIKE
_DLY
tPHOCP
VRHOT_L and PGOOD
Output Low Voltage at
VRHOT_L
VVRHOT_L
VRHOT_L Assertion Time
tVRHOTL
IVRHOT_L = 4mA
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11
RT3669EA
Parameter
Output Low Voltage at
PGOOD
Symbol
Test Conditions
Min
Typ
Max
Unit
VPGOOD
IPGOOD = 4mA
0
--
0.2
V
PGOOD Threshold
VTH_PGOOD
Respect to BOOT VID
--
300
--
mV
PGOOD Delay Time
tPGOOD
BOOT VID to PGOOD high
60
110
160
s
Maximum Reported Current
(FFh = OCP_SPIKE)
--
100
--
%IDD_
SPIKE
_OCP
Minimum Reported Current
(00h)
--
0
--
%IDD_
SPIKE
_OCP
IDDSPIKE Current Accuracy
--
--
3
%
Maximum Reported Voltage
(0_00h)
--
3.15
--
V
Minimum Reported Voltage
(1_F8h)
--
0
--
V
Voltage Accuracy
2
--
2
LSB
Current Report
Voltage Report
Switching Time
UGATE Rise Time
tUGATEr
3nF load
--
8
--
ns
UGATE Fall Time
tUGATEf
3nF load
--
8
--
ns
LGATE Rise Time
tLGATEr
3nF load
--
8
--
ns
LGATE Fall Time
tLGATEf
3nF load
--
4
--
ns
UGATE Turn-On Propagation
Delay
tUGATEpdh
Output unloaded
--
20
--
ns
LGATE Turn-On Propagation
Delay
tLGATEpdh
Output unloaded
--
20
--
ns
RUGATEsr
100mA source current
--
1
--

UGATE Driver Source Current IUGATEsr
VUGATE – VPHASE = 2.5V
--
2
--
A
UGATE Driver Sink
Resistance
RUGATEsk
100mA sink current
--
1
--

UGATE Driver Sink Current
IUGATEsk
VUGATE – VPHASE = 2.5V
--
2
--
A
LGATE Driver Source
Resistance
RLGATEsr
100mA source current
--
1
--

ILGATEsr
VLGATE = 2.5V
--
2
--
A
RLGATEsk
100mA sink current
--
0.5
--

ILGATEsk
VLGATE = 2.5V
--
4
--
A
0.95
--
5
V
Output
UGATE Driver Source
Resistance
LGATE Driver Source Current
LGATE Driver Sink
Resistance
LGATE Driver Sink Current
LDO
Input Voltage
VIN_LDO
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is a registered trademark of Richtek Technology Corporation.
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RT3669EA
Parameter
Symbol
Test Conditions
Min
Typ
Max
Unit
Output Voltage
VOUT_LDO
1.5
--
1.5
%
Reference Voltage
VREF_LDO
0.394
0.4
0.406
V
Dropout Voltage
VDrop_LDO
30
50
70
mV
Current Limit
IOC
0.6
1.3
1.5
A
Switch On Resistance
RDS(ON)
40
70
100
m
Current Limit
IOC_MUX
1.1
2.1
3.1
A
MUX_CTRL VIH
VIH_MUX
--
--
3
V
MUX_CTRL VIL
VIL_MUX
1
--
--
V
VIN_LDO = 0.95V,
IOUT_LDO = 200mA
Power MUX
Note 1. Stresses beyond those listed “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress
ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the
operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions may affect device
reliability.
Note 2. JA is measured under natural convection (still air) at TA = 25C with the component mounted on a high effective-thermalconductivity four-layer test board on a JEDEC 51-7 thermal measurement standard. JC is measured at the exposed pad
of the package.
Note 3. Devices are ESD sensitive. Handling precaution recommended.
Note 4. The device is not guaranteed to function outside its operating conditions.
Note 5. Min. SVC frequency defined in electrical spec. is related with different application. As min. SVC < 1MHz, VR can’t support
telemetry reporting function. As min. SVC < 400kHz, VR can’t support telemetry reporting function and VOTF complete
function.
Note 6. TON[PSI0_L:PSI1_L=00,01,10] = 0.8 * TON[PSI0_L:PSI1_L=11]
Copyright © 2017 Richtek Technology Corporation. All rights reserved.
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RT3669EA
Typical Application Circuit
4.7
13
5V
VCC
RT3669EA
2.2µF
0
28
5V
VDDIO
2.2
18
PVCC
VIN
4.7
1
0.1µF
2.2µF
33k
845
10
1.82k
COMP
3k
187k
9
510 100k/ = 4485
12 VREF_PINSET
VREF
8.45k
3.9
0.47µF
BOOT
124
11
470pF
64.9k
10k
25
VGFX_SENSE
VSS_SENSE
Reserved
VIN
2.2
0.1µF
10
LGATE
VGFX
0.36μH/1.1m 
27
29
1
910
0.47μF
LOAD
IMON
3.3nF
100k/  = 4485
VDDIO
POSCAP : 470μF/4.5m  x 3
ISEN1P 6
ISEN1N 7
3.3V
Reserved
MLCC : 22μF x 14
0.1μF
4.7k
4.7k 10k
LDO_VIN
15
5V
To CPU
16
24
10μF
8 VRHOT_L
14 PWROK
31 PGOOD
5V
LDO_OUT
1k
Enable
VVDDNB
Reserved
0
VOUT_LDO
4.7μF
340k
SVC
FBA
SVD
SVT
32 EN
19 VSEN_NB_IN
100pF
22
360k
S5_OUT
VVDDNB
(RT3661AB)
20
VVDDCR_FCH_S5
MLCC : 22μF x 2
4.7μF x 2
GND
23
VIN_LDO
21
17
1k
10
10µF x 2
UGATE 26
PHASE
RNTC
16k
3
39pF
FB 4
RGND 2
TSEN
RNTC
33k
VIN
VSEN 5
SET1
13k
68k
VDDIO
1µF
33 (Exposed Pad)
MUX_CTRL
MUX Control Signal
Timing Diagram
LGATEx
1.5V
1.5V
1.5V
1.5V
UGATEx
tUGATEpdh
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tLGATEpdh
is a registered trademark of Richtek Technology Corporation.
DS3669EA-02
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RT3669EA
Typical Operating Characteristics
GFX VR Power Off from EN
GFX VR Power On from EN
Boot VID = 0.8V
Boot VID = 0.8V
VGFX
(500mV/Div)
VGFX
(500mV/Div)
EN
(3V/Div)
EN
(3V/Div)
PGOOD
(3V/Div)
PGOOD
(3V/Div)
UGATE
(20V/Div)
UGATE
(20V/Div)
Time (500μs/Div)
Time (200μs/Div)
GFX VR UVP
GFX VR OCP_SPIKE
TSEN
(1V/Div)
ILoad
(17A/Div)
VRHOT_L
(2V/Div)
PGOOD
(3V/Div)
UGATE
(30V/Div)
LGATE
(10V/Div)
ILoad = 30A to 60A
Time (10ms/Div)
Time (10μs/Div)
GFX VR OVP
GFX VR UVP
VID = 1.1V
VID = 1.1V
VGFX
(500mV/Div)
VGFX
(800mV/Div)
PGOOD
(3V/Div)
PGOOD
(3V/Div)
UGATE
(30V/Div)
LGATE
(10V/Div)
UGATE
(30V/Div)
LGATE
(10V/Div)
Time (10μs/Div)
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RT3669EA
GFX VR Dynamic VID Up
GFX VR Dynamic VID Up
VGFX
VGFX
(400mV/Div)
SVD
(2V/Div)
SVT
(2V/Div)
SVD
(2V/Div)
VGFX
(200mV/Div)
SVT
(2V/Div)
VID = 1V to 1.06875V, ILoad = 11A
VID = 0.4V to 1V, ILoad = 2.2A
Time (20μs/Div)
Time (10μs/Div)
GFX VR Dynamic VID Up
GFX VR Dynamic VID Up
VGFX
VGFX
SVD
(2V/Div)
SVD
(2V/Div)
SVT
(2V/Div)
SVT
(2V/Div)
VGFX
(200mV/Div)
VID = 1V to 1.1V, ILoad = 11A
VGFX
(200mV/Div)
VID = 1V to 1.2V, ILoad = 11A
Time (10μs/Div)
Time (10μs/Div)
GFX VR Dynamic VID Up
GFX VR Load Transient
VGFX
(30mV/Div)
VGFX
SVD
(2V/Div)
SVT
(2V/Div)
VGFX
(300mV/Div)
VID = 1V to 1.4V, ILoad = 11A
Time (10μs/Div)
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ILoad
(17.5A/Div)
fLoad = 10kHz, ILoad = 10A to 35A
Time (5μs/Div)
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RT3669EA
GFX VR Load Transient
LDO Load Transient
VGFX
(30mV/Div)
IOUT_LDO
(100mA/Div)
VOUT_LDO
(20mV/Div)
ILoad
(17.5A/Div)
fLoad = 10kHz, ILoad = 35A to 10A
Load step = 200mA, Load SR = 2.5A/µs
Time (5μs/Div)
Time (500μs/Div)
FCH Power Transition from LDO to NB
FCH Power Transition from LDO to NB
VVDDCR_FCH_S5
VVDDCR_FCH_S5
VOUT_LDO
VOUT_LDO
VVDDNB
(200mV/Div)
VVDDNB
MUX_CTRL= L, IVDDCR_FCH_S5 = 0mA
(200mV/Div)
MUX_CTRL= L, IVDDCR_FCH_S5 = 200mA
Time (20μs/Div)
Time (20μs/Div)
FCH Power Transition from NB to LDO
FCH Power Transition from NB to LDO
VOUT_LDO
VOUT_LDO
VVDDCR_FCH_S5
VVDDCR_FCH_S5
VVDDNB
VVDDNB
(200mV/Div)
MUX_CTRL= L, IVDDCR_FCH_S5 = 0mA
Time (200μs/Div)
Copyright © 2017 Richtek Technology Corporation. All rights reserved.
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(200mV/Div)
MUX_CTRL= L, IVDDCR_FCH_S5 = 200mA
Time (200μs/Div)
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RT3669EA
Application Information
Power Ready (POR) Detection
Boot VID
During start-up, the RT3669EA will detect the voltage at
the voltage input pins : VCC, PVCC and EN. When VCC
> 4.3V and PVCC > 3.85V, the IC will recognize the
power state of system to be ready (POR = high) and
wait for enable command at the EN pin. After POR =
When EN goes high, GFX output begin to soft-start to
the Boot VID in CCM. Table 5 shows the Boot VID
setting. The Boot VID is determined by the SVC and
SVD input states at EN rising edge and it is in the
internal register. The digital soft-start circuit ramps up
high and VEN > 2V, the IC will enter start-up sequence
for GFX. If the voltage of VCC and EN pin drop below
low threshold, the IC will enter power down sequence
and all the functions will be disabled. Normally,
connecting system power to the EN pin is
recommended. The SVID will be ready in 2ms (max)
the reference voltage at a controlled slew rate to reduce
inrush current during start-up. When all the output
voltages are above power good threshold (300mV
below Boot VID) at the end of soft-start, the controller
asserts power good (PGOOD) after a time delay.
after the chip has been enabled. All the protection
latches (OVP, OCP, UVP) will be cleared only after
POR = low. The condition of VEN = low will not clear
these latches.
+ CMP
VCC
4.3V
+
PVCC
3.85V
CMP
2V
SVC
SVD
GFX Output Voltage (V)
0
0
1.1
0
1
1.0
1
0
0.9
1
1
0.8
Start-Up Sequence
Chip EN
-
Figure 1. Power Ready (POR) Detection
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18
Initial Startup VID (Boot VID)
+ CMP
EN
POR
Table 5. 2-Bit Boot VID Code
After EN goes high, the RT3669EA starts up and
operates according to the initial settings. Figure 2 shows
the simplified sequence timing diagram. The detailed
operation is described in the following.
is a registered trademark of Richtek Technology Corporation.
DS3669EA-02
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RT3669EA
T0
T1
T2
T3
T4
T5
T6
T7
T8
T9
T10
T11
VIN
LDO_VIN
PVCC, VCC
VDDIO
LDO_OUT
SVID
Send
Byte
SVC
SVID
Send
Byte
SVD
VOTF
Complete
VOTF
Complete
SVT
EN
PWROK
CCM
Boot VID
CCM
VDDCR_GFX
VID
CCM
Boot VID
CCM CCM
VID
CCM
CCM
PGOOD
Figure 2. Simplified Sequence Timing Diagram
Description of Figure 2 :
T0 : When the VIN and LDOVIN power are ready, the
RT3669EA will wait for VCC and PVCC POR.
T1 : After VCC power is ready, the LDO_OUT power on
and the voltage controlled by FBA pin voltage divider.
The GFX BOOT VID can be set by SVC pin and SVD
pin, and then latched at EN rising edge. SVT is driven
high by the RT3669EA.
T2 : The enable signal goes high and the GFX output
voltage ramp up to the Boot VID in CCM. The soft-start
slew rate is 2.5mV/s.
T3 : The GFX output voltage is within the regulation
limits and the PGOOD signal goes high.
transition according to the received SVID command and
send a VOTF Complete if the VID is greater than BOOT
VID and output voltage reaches target VID.
T7 : The PWROK pin goes low and the SVI2 interface
stops running. All output voltages go back to the Boot
VID in CCM.
T8 : The PWROK pin goes high again and the SVI2
interface starts running. The RT3669EA waits for SVID
command from processor.
T9 : A valid SVID command transaction occurs between
the processor and the RT3669EA.
T10 : The action is same with T6. The RT3669EA starts
T4 : The PWROK pin goes high and the SVI2 interface
starts running. The RT3669EA waits for SVID command
VID on-the-Fly transition and send a VOTF Complete if
the VID up and reaches target VID.
from processor.
T11 : The enable signal goes low and GFX output
voltage enter soft-shutdown mode. The soft-shutdown
slew rate is 2.5mV/s. The LDO_OUT voltage keeps
power on unless the VCC power down.
T5 : A valid SVID command transaction occurs between
the processor and the RT3669EA.
T6 : The RT3669EA starts VOTF (VID on-the-Fly)
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RT3669EA
Power-Down Sequence
SVI2 Wire Protocol
If the voltage at the EN pin falls below the enable falling
threshold, the controller is disabled. The voltage at the
The RT3669EA complies with AMD's Voltage Regulator
Specification, which defines the Serial VID Interface 2.0
PGOOD pin will immediately go low when EN pin signal
goes low, and the GFX controller executes softshutdown operation. The internal digital circuit ramps
down the reference voltage at the same slew rate as
that of in soft-start, making GFX output voltage
gradually decrease in CCM. The Boot VID information
stored in the internal register is cleared at POR. This
event forces the RT3669EA to check the SVC and SVD
inputs for a new Boot VID when the EN voltage goes
high again.
(SVI2) protocol. With SVI2 protocol, the processor
directly controls the reference voltage level of each
individual controller channel and determines which
controller operates in power saving mode. The SVI2
interface is a three-wire bus that connects a single
master to one or above slaves. The master initiates and
terminates SVI2 transactions and drives the clock, SVC,
and the data, SVD, during a transaction. The slave
drives the telemetry, SVT during a transaction. The
AMD processor is always the master. The voltage
PGOOD
The PGOOD is open-drain logic output. It provides the
power good signal when GFX output voltage is within
the regulation limits and no protection is triggered. The
pin is typically tied to 3.3V or 5V power source through
a pull-high resistor. During shutdown state (EN = low)
and the soft-start period, the PGOOD voltage is pulled
low. After a successful soft-start and GFX output
voltage is within the regulation limits, the PGOOD is
released high.
The voltage at the PGOOD pin will be pulled low when any
of the following events occurs : over-voltage protection,
under-voltage protection, over-current protection, and logic
low EN voltage.
regulator controller (RT3669EA) is always the slave.
The RT3669EA receives the SVID code and acts
accordingly. The SVI protocol supports 20MHz high
speed mode I2C, which is based on SVD data packet.
Table 6 shows the SVD data packet. A SVD packet
consists of a “Start” signal, three data bytes after each
byte, and a “Stop” signal. The 8-bit serial VID codes are
listed in Table1. After the RT3669EA has received the
stop sequence, it decodes the received serial VID code
and executes the command. The controller has the
ability to sample and report voltage and current for the
GFX domains. The controller reports this telemetry
serially over the SVT wire which is clocked by the
processor driven SVC. A bit TFN at SVD packet along
with the GFX domain selector bits are used by the
processor to change the telemetry functionality. The
telemetry bit definition is listed in Figure 3. The detailed
SVI2 specification is outlined in the AMD Voltage
Regulator and Voltage Regulator Module (VRM) and
Serial VID Interface 2.0 (SVI2) Specification.
Table 6. SVD Data Packet
Bit Time
Description
1:5
Always 11000b
GFX domain selector bit, if set then the following two data bytes contain the VID for GFX, the
PSI state for GFX, and the load-line slope trim and offset trim state for GFX.
6
8
Always 0b
10
PSI0_L
11 : 17
VID Code bits [7:1]
19
VID Code bit [0]
20
PSI1_L
21
TFN (Telemetry Functionality)
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RT3669EA
Bit Time
Description
22 : 24
Load Line Slope Trim [2:0]
25 : 26
Offset Trim [1:0]
Voltage and Current
Mode Selection
Bit Time…… START
1
2
3
GFX Voltage Bits
4
5
6
7
8
GFX Current Bits
9
10
11
12
13
14
15
16
17
18
19
20
STOP
SVC
SVT
Figure 3. Telemetry Bit Definition
PWROK and SVI2 Operation
The PWROK pin is an input pin, which is connected to
the global power good signal from the platform. Logic
high at this pin enables the SVI2 interface, allowing data
transaction between processor and the RT3669EA.
Once the RT3669EA receives a valid SVID code, it
decodes the information from processor to determine
the output target VID. The internal DAC then steps
up/down the reference voltage in a controlled slew rate,
making the output voltage shift to the required new VID.
If the PWROK input goes low during normal operation,
the SVI2 protocol stops running. The RT3669EA
immediately drives SVT high and modifies all output
voltages back to the Boot VID, which is stored in the
internal register right after the controller is enabled. The
controller does not read SVD and SVC inputs after the
loss of PWROK. If the PWROK input goes high again,
the SVI2 protocol resumes running. The RT3669EA
then waits to decode the SVID command from
processor for a new VID and acts as previously
described. The SVI2 protocol is only runs when the
PWROK input goes high after the voltage at the EN pin
goes high.
During the VID on-the-Fly transition, the RT3669EA will
force CCM operation in high performance mode. If the
controller channel operates in the power-saving mode
prior to the VID on-the-Fly transition, it will change to
high performance mode and implement CCM operation
when the controller implement VID up, and then remain
in high performance mode; if the controller implement
VID down in power-saving mode, it will decay down and
keep in power-saving mode. The voltage at the PGOOD
pin will keep high during the VID on-the-Fly transition.
The RT3669EA send a VOTF complete only at the end
of VID up transition. In the event of receiving a VID off
code, the RT3669EA steps the reference voltage of
required controller channel down to zero, hence making
the required output voltage decrease to zero, and the
voltage at the PGOOD pin will remain high since the VID
code is valid.
Power State Transition
The RT3669EA supports power state transition function
in GFX VR for the PSI[x]_L command from AMD
processor. The PSI[x]_L bit in the SVI2 protocol controls
the operating mode of the RT3669EA controller channel.
The default operation mode of GFX VR is 1-phase CCM.
VID on-the-Fly Transition
When the GFX VR receives PSI0_L = 0 and PSI1_L =
After the RT3669EA has received a valid SVID code, it
executes the VID on-the-Fly transition by stepping
up/down the reference voltage of the required controller
channel in a controlled slew rate, hence allowing the
0 or 1, the GFX VR will entry 1-phase diode emulation
mode. When the GFX VR receives PSI0_L = 1 and
output voltage to ramp up/down to target VID.
1-phase CCM upon receiving PSI0_L = 1 and PSI1_L =
1, see Table 7.
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PSI1_L = 0, the GFX VR remains 1-phase diode
emulation mode. In reverse, the GFX VR goes back to
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RT3669EA
The ADC monitors and decodes the voltage at this pin
only once after power up. After ADC decoding (only
once), a 80A current (when VCC = 5V) will be
Table 7. GFX VR Power State
Full Phase
Number
PSI0_L : PSI1_L
Mode
11
1 phase CCM
10
1
01
1 phase DEM
00
Differential Remote Sense Setting
The GFX controller has differential remote-sense inputs
to eliminate the effects of voltage drops along the PC
board traces, processor internal power routes and
socket contacts. The processor contains on-die sense
pins, including of VGFX_SENSE, and VSS_SENSE.
For GFX controller, connect FB to VGFX_SENSE with
a resistor to build the negative input path of the error
amplifier, and connect VSS_SENSE to RGND as shown
in Figure 4. The precision reference voltages refer to
RGND for accurate remote sensing.
FB
RGND
VGFX_SENSE
(2)
From equation (1) and (2) and Table 2 and 3, platform
users can set the above described pin setting functions.
AI_GFX
80µA
(VCC = 5V)
QR_TH
VREF
ADC
VSET1_DIV
RU
SET1
SET1
Register
RD
VSET1_IR
The RT3669EA provides the TSEN pin for platform
users to set the pin setting functions, including the GFX
SET1 Pin Setting
The RT3669EA provides the SET1 pin for platform
users to set the GFX controller current gain ratio
(AI_GFX), QR threshold (QR_TH). Platform designers
should use resistive voltage divider on the pin, refer to
Figure 5. The voltage (VREF) at VREF_PINSET pin will
be pulled up to 3.2V for SET1 pin setting after power
ready (POR), and then the voltage will change and fix
to 0.8V with a delay time for normal operation.
The divided voltage at the SET1 pin as below :
RD
RU  RD
RU  RD
RU  RD
TSEN Pin Setting
VSS_SENSE
Figure 4. Differential Remote Sense Connection
VSET1_ DIV  3.2 
VSET1_IR  80 
Figure 5. SET1 Pin Setting
Processor
GFX
Controller
generated at the SET1 pin for pin setting. That is the
voltage at SET1 pin described as below :
(1)
controller switching frequency (Fsw), Initial offset and
per-phase over current protection (PHOCP). Platform
designers should use resistive voltage divider on the pin,
refer to Figure 6. The voltage (VREF) at VREF_PINSET
pin will be pulled up to 3.2V for TSEN pin setting after
power ready (POR), and then the voltage will change
and fix to 0.8V with a delay time for normal operation.
The divided voltage at the TSEN pin described as
below :
VTSEN _ DIV  3.2 
(3)
Rp2
Rp1  Rp2
The ADC monitors and decodes the voltage at this pin
only once after power up. After ADC decoding (only
once), a 80A current (when VCC = 5V) will be
generated at the TSEN pin for thermal indicator and
protection functions.
From equation (3) and Table 4, platform users can set
the above described pin setting functions.
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RT3669EA
Refer to Figure 6, the RT3669EA provides the thermal
indicator function. The VRHOT_L pin is an open-drain
compensator gain, the HS_FET on-time is determined
by CCRCOT on-time generator. When load current
increases (VCS increases), the steady state COMP
output which is used for VR thermal indicator. When the
sensed voltage at TSEN pin is less than 2.2V, the
VRHOT_L signal will be pulled low to notify CPU that
the temperature is over the VRHOT temperature
threshold.
voltage also increases and induces VGFX_SENSE to
decrease, thus achieving AVP. A near-DC offset
canceling is added to the output of EA to eliminate the
inherent output offset of finite gain peak current mode
controller.
Thermal Indicator
VIN
After TSEN pin setting, a 80A current (when VCC = 5V)
will be generated at the TSEN pin for thermal indicator
function. And the voltage at TSEN pin as below :
Due to the VREF reference voltage cause the thermal
compensation become complex. In this way, the sensed
Driver
RC
LS_FET
0.75 x AI_GFX
+
1.867m
-
Offset
Canceling
RX2
C
ISEN1P
ISEN1N
IMON
EA
+
VGFX
RX1 CX
VCS
RIMON
VREF_PINSET
C2
C1
COMP
FB
RGND
R2
R1
+
voltage related VREF will be eliminated in ADC block.
The actual sensed voltage at TSEN pin described as
below :
+
CMP
-
(4)
COMP2
VTSEN
 R  R
 Rp2

  Rp1  Rp2  
 80 A   1 NTC   
   VREF  


R

R
R

R
R

R
NTC   p1
p2  
p2 
 p1
 1
HS_FET
L RSENSE
CCRCOT
PWM
Logic
VGFX_SENSE
VSS_SENSE
VDAC
 R  R
  Rp1  Rp2  
VTSEN_ADC  80 A   1 NTC   
  (5)

 R1  RNTC   Rp1  Rp2  
VRHOT_L
PHOCP
FSW
Thermal
Monitor
PROCHOT_L
80µA
(VCC = 5V)
VREF
ADC
2.2V
VTSEN
Register
RNTC
Rp1
TSEN
VTSEN_DIV
Voltage Loop and Current Loop
Current Sense Setting
VDDIO
Initial Offset
Figure 7.GFX Controller : Simplified Schematic with
R1
Rp2
Refer to Figure 7, for different RSENSE resistor, the
current sense method can classify as two types. The
method1 only use RX1 for lower RSENSE application,
and the method2 use RX1 and RX2 to divide the current
signal for higher RSENSE application. Richtek also
provide Excel based design tool to let user choose the
appropriate components quickly.
The current sense topology of the GFX controller is
Figure 6. TSEN Circuit
GFX Controller
Loop Control
The GFX controller adopts Richtek's proprietary GNAVPTM topology. The G-NAVPTM is based on the
finite gain peak current mode with CCRCOT (Constant
Current Ripple Constant On-Time) topology. The output
voltage, VGFX will decrease with increasing output load
current. The control loop consists of PWM modulators
with power stages, current sense amplifiers and an error
amplifier as shown in Figure 7.
continuous inductor current sensing. Therefore, the
controller has less noise sensitive. Low offset amplifiers
are used for loop control and over current detection. The
ISEN1P and ISEN1N pins denote the positive and
negative input of the current sense amplifier.
In order to optimize transient performance, the
recommended Req and CX will be set according to the
equation as below, and  recommended set to 1.1.
Req  CX   
L
RSENSE
(6)
Method1 : Req = RX1
(7)
Similar to the peak current mode control with finite
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RT3669EA
Loop Compensation
R X1  R X2
Method2 : Req  R  R
X1
X2
(8)
Considering the inductance tolerance, the resistor Req
has to be tuned on board by examining the transient
voltage. If the output voltage transient has an initial dip
below the minimum load-line requirement and the
response time is too fast causing a ring back, the value
of resistance should be increased. Vice versa, with a
high resistance, the output voltage transient has only a
small initial dip with a slow response time.
Droop Setting
It is very easy to achieve Active Voltage Positioning
(AVP) by properly setting the error amplifier gain due to
the native droop characteristics as shown in Figure 8.
This target is to have
VGFX = VDAC  ILOAD x RDROOP
(9)
Then solving the switching condition VCOMP2 = VCS in
Figure 7 yields the desired error amplifier gain as
GI
A V  R2 
R1 RDROOP
(11)
The pole frequency of the compensator must be set to
compensate the output capacitor ESR zero :
fP 
1
2  C  RC
(13)
Where C is the capacitance of output capacitor, and RC
is the ESR of output capacitor. C2 can be calculated as
follows :
C  RC
R2
(14)
The zero of compensator has to be placed at half of the
switching frequency to filter the switching related noise.
Such that,
C1 
Method2 :
GI  RSENSE 
output. A type-I compensator with one pole and one
zero is adequate for proper compensation. Figure 9
shows the compensation circuit. Previous design
procedure shows how to select the resistive feedback
components for the error amplifier gain. Next, C1 and
C2 must be calculated for compensation. The target is
to achieve constant resistive output impedance over the
widest possible frequency range.
C2 
(10)
Method1 :
GI  RSENSE 1.867m  RIMON  0.75  AI_GFX
Optimized compensation of the GFX controller allows
for best possible load step response of the regulator's
1
R1   fSW
(15)
R X2
1.867m  RIMON  0.75  AI_GFX
R X1  R X2
set by SET1 pin setting. RDROOP is the equivalent loadline resistance as well as the desired static output
impedance.
VGFX
C2
C1
R2
R1
VGFX_SENSE
FB
RGND
VSS_SENSE
VDAC
Figure 9. GFX Controller : Compensation Circuit
Initial and Dynamic Offset
The GFX controller features initial and dynamic offset
function. The GFX rail initial offset function can be
implemented through the TSEN pin setting. And the
dynamic offset can be implemented by SVI2 interface,
it controlled by CPU. Consider the offset factor, the GFX
output voltage described as below :
VGFX  VDAC  ILOAD  RDROOP  VINI_OFS  VDYN_OFS (16)
AV2 > AV1
AV2
AV1
0
EA
+
+
(12)
Where GI is the current sense amplifier gain. RSENSE is
the current sense resistor. If no external sense resistor
present, it is the equivalent resistance of the inductor.
RIMON is the IMON equivalent resistance. For the
PHOCP accuracy, the RIMON resistor need to set in 8k
to 70k. AI_GFX is the GFX controller current gain ratio
COMP
Load Current
VINI_OFS is the initial offset voltage set by pin setting
function, and the dynamic offset voltage, VDYN_OFS,
controlled by CPU, and it can be set through the SVI2
interface.
Figure 8. GFX Controller : Error Amplifier gain (AV)
Influence on VGFX Accuracy
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RT3669EA
Dynamic VID Enhancement
Current Monitoring and Reporting
During a dynamic VID event, the charging (dynamic VID
up) or discharging (dynamic VID down) current causes
The GFX controller provides current monitoring function
via inductor current sensing. In the G-NAVPTM
unwanted load-line effect which degrades the settling
time performance. The RT3669EA will hold the inductor
current to hold the load-line during a dynamic VID event.
The GFX controller will always enter CCM operation
when it receives dynamic VID up command; If GFX
controller receives dynamic VID down command, it will
hold the operating state.
technology, the output voltage is dependent on output
current, and the current monitoring function is achieved
by this characteristic of output voltage. The equivalent
output current will be sensed from inductor current
sensing and mirrored to the IMON pin. The resistor
connected to the IMON pin determines voltage of the
IMON output.
When the VID CCM down on light loading condition, the
negative inductor current will be produced, and it may
cause the audio noise and phase ring effect. For
For Method1 current sensing :
improving the problems, the controller set the dynamic
VID down slew rate to 0.625mV/s, the action will
reduce the negative current and phase ring effect.
Ramp Compensation
TM
G-NAVP
topology is one type of ripple based control
that has fast transient response. However, ripple based
control usually don't have good noise immunity. The
RT3669EA provides a ramp compensation to increase
noise immunity and reduce jitter at the switching node,
refer to Figure 10 shows the ramp compensation. When
the GFX controller takes phase shedding operation and
enters diode emulation mode, the internal ramp of GFX
controller will be modified for the reason of stability.
W/O ramp compensation
VO
Noise Margin
VREF
VCOMP - VCS
PWM
With ramp compensation
VO
VIMON  IL,SUM  DCRL 1.867m  RIMON  0.8
(17)
Where IL,SUM is the GFX output current, DCRL is the
current sense resistance, RIMON is the IMON pin
equivalent setting resistor, and the current sense gain
equal to 1.867m.
The ADC circuit of the GFX controller monitors the
voltage variation at the IMON pin, and this voltage is
decoded into digital format and stored into output
current register.
DIMON 
VIMON  0.8
 255 (Bits)
0.8
(18)
Quick Response
When the transient load step-up becomes quite large, it
is difficult for loop response to meet the energy transfer.
Hence, the output voltage generate undershoot to fail
specification. RT3669EA has Quick Response (QR)
mechanism which is able to improve this issue. It adopts
a nonlinear control mechanism which can disable
interleaving function and simultaneously turn on all
UGATE one pulse at instantaneous step-up transient
load to restrain the output voltage drooping. The output
voltage signal behavior needs to be detected so that QR
mechanism can be trigged. Refer to Figure 11, the
output voltage signal is via a remote sense line to
connect at the VSEN pin. The QR threshold can be set
by SET1 pin setting for GFX controller refers to Table 3.
Noise Margin
QR_TH
VRAMP
VCOMP - VCS
CMP
+
+
QR Pulse
Generation
Circuit
VSEN
PWM
Figure 10. Ramp Compensation
Figure 11. GFX Controller : Quick Response Triggering
Circuit
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RT3669EA
Over-Current Protection
The RT3669EA provides the over current protection
function. The OCP_SPIKE threshold will be set by the
PWM logic drivers. A 3s delay is used in UVLO
detection circuit to prevent false trigger.
current monitor resistor RIMON as below :
For Method1 current sensing :
OCP_SPIKE 
1.6  0.8
DCRL  1.867m  RIMON
(19)
For prevent the OCP false trigger, the trigger delay is
requirement, refer to Electrical Characteristics. When
output current is still higher than the OCP_SPIKE after
the trigger delay time, the OCP will be latched, and then
the GFX controller will turn off both high-side and lowside MOSFETs of all channels.
Per-Phase Over Current Protection
The GFX controller provides per-phase over current
protection (PHOCP) function, it only detected at soft-start
duration when VR power on. The PHOCP threshold is set
by TSEN pin setting described as below :
PHOCP_TH  OCP_SPIKE_NB  N
drops below IC POR threshold, the GFX controller will
trigger UVLO. The UVLO protection forces all high-side
and low-side MOSFETs off by shutting down internal
(20)
N is the GFX PHOCP setting ratio.
VDDCR_FCH_S5 Power and Power MUX
RT3669EA provides FP4 VDDCR_FCH_S5 power.
Refer to Figure 12, the VDDCR_FCH_S5 voltage is
determined by power MUX, it can be supplied by
VDDNB power (VVDDNB) or LDO power (VOUT_LDO).
Figure 13 shows the VDDCR_FCH_S5 power simplified
sequence timing diagram related with power MUX and
described as below :
T0 : MUX control signal is high, then VVDDCR_FCH_S5
voltage supplied by VVDDNB.
T1 : MUX control signal is low and VVDDNB > (VOUT_LDO
 10mV), then VVDDCR_FCH_S5 voltage supplied by
VVDDNB.
T2 : VVDDCR_FCH_S5 voltage supplied by VOUT_LDO
when VVDDNB < (VOUT_LDO 10mV).
T3 : Because of VVDDNB > (VOUT_LDO + 40mV), the
VVDDCR_FCH_S5 voltage supplied by VVDDNB.
If the PHOCP is triggered, the controller will turn off all
high-side and low-side MOSFETs to protect CPU.
MUX_CTRL
MUX Control Signal
VVDDNB
+
40mV
VOUT_LDO
-
10mV
+
-
The OVP circuit of the GFX controller monitors the
output voltage via the VSEN pin after POR. When the
LDO_OUT
delay is used in OVP detection circuit to prevent false
trigger.
Under-Voltage Protection (UVP)
The GFX controller implements UVP of VSEN pin. If
VSEN voltage is less than the internal reference by
500mV, the GFX controller will trigger UVP latch. The
UVP latch will turn off both high-side and low-side
MOSFETs. A 3s delay is used in UVP detection circuit
to prevent false trigger.
Under-Voltage Lock Out (UVLO)
During normal operation, if the voltage at the VCC pin
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VVDDCR_FCH_S5
0
VSEN voltage exceeds the OVP threshold 1.85V, OVP
is triggered and latched. The GFX controller will try to
turn on low-side MOSFET and turn off high-side
MOSFET of all active phases to protect the CPU. A 1s
CMP
+
-
Over-Voltage Protection (OVP)
VSEN_NB_IN
POWER S5_OUT
_MUX
1
Figure 12. VDDCR_FCH_S5 Circuit
T0
T1
T2
T3
MUX Control Signal
VVDDNB
VOUT_LDO
40mV
10mV
VVDDCR_FCH_S5
Figure 13. VDDCR_FCH_S5 Simplified Timing
Diagram
LDO Regulator
The LDO will operate when VCC power turns on. Figure
14 shows the LDO circuit, the output voltage can be set
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RT3669EA
by adjusting the resistor connected to FBA pin. And the
output voltage described as below :
 R  R2 
VOUT_LDO  0.4   1

 R2 
(21)
Be carefully, the external capacitors of the RT3669EA
are selected for regulator stability and performance.
When VOUT_LDO set to 0.775V, the recommended
resistors and capacitors as below : CIN = 10F, COUT =
4.7F, R1 = 340k, R2 = 360k, and Cf = 100pF.
can be calculated as below :
PD(MAX) = (125C  25C) / (27.8C/W) = 3.59W for a
WQFN-32L 4x4 package.
The maximum power dissipation depends on the
operating ambient temperature for the fixed TJ(MAX) and
the thermal resistance, JA. The derating curves in
Figure 15 allows the designer to see the effect of rising
ambient temperature on the maximum power
dissipation.
VCC
LDO_VIN
CIN
0.4V
+
OP
-
VOUT_LDO
LDO_OUT
COUT
R1
Cf
FBA
R2
Maximum Power Dissipation (W)1
4.0
VIN_LDO
Four-Layer PCB
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0.0
Figure 14. LDO Circuit
Thermal Considerations
The junction temperature should never exceed the
absolute maximum junction temperature TJ(MAX), listed
under Absolute Maximum Ratings, to avoid permanent
damage to the device. The maximum allowable power
dissipation depends on the thermal resistance of the IC
package, the PCB layout, the rate of surrounding airflow,
0
25
50
75
100
125
Ambient Temperature (°C)
Figure 15. Derating Curve of Maximum Power
Dissipation
and the difference between the junction and ambient
temperatures. The maximum power dissipation can be
calculated using the following formula :
PD(MAX) = (TJ(MAX)  TA) / JA
where TJ(MAX) is the maximum junction temperature, TA
is the ambient temperature, and JA is the junction-toambient thermal resistance.
For continuous operation, the maximum operating
junction temperature indicated under Recommended
Operating Conditions is 125C. The junction-toambient thermal resistance, JA, is highly package
dependent. For a WQFN-32L 4x4 package, the thermal
resistance, JA, is 27.8C/W on a standard JEDEC 517 high effective-thermal-conductivity four-layer test
board. The maximum power dissipation at TA = 25C
Copyright © 2017 Richtek Technology Corporation. All rights reserved.
DS3669EA-02
March 2017
is a registered trademark of Richtek Technology Corporation.
www.richtek.com
27
RT3669EA
Outline Dimension
Symbol
Dimensions In Millimeters
Dimensions In Inches
Min
Max
Min
Max
A
0.700
0.800
0.028
0.031
A1
0.000
0.050
0.000
0.002
A3
0.175
0.250
0.007
0.010
b
0.150
0.250
0.006
0.010
D
3.900
4.100
0.154
0.161
D2
2.650
2.750
0.104
0.108
E
3.900
4.100
0.154
0.161
E2
2.650
2.750
0.104
0.108
e
L
0.400
0.300
0.016
0.400
0.012
0.016
W-Type 32L QFN 4x4 Package
Richtek Technology Corporation
14F, No. 8, Tai Yuen 1st Street, Chupei City
Hsinchu, Taiwan, R.O.C.
Tel: (8863)5526789
Richtek products are sold by description only. Richtek reserves the right to change the circuitry and/or specifications without notice at any time. Customers should
obtain the latest relevant information and data sheets before placing orders and should verify that such information is current and complete. Richtek cannot assume
responsibility for use of any circuitry other than circuitry entirely embodied in a Richtek product. Information furnished by Richtek is believed to be accurate and reliable.
However, no responsibility is assumed by Richtek or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result
from its use. No license is granted by implication or otherwise under any patent or patent rights of Richtek or its subsidiaries.
Copyright © 2017 Richtek Technology Corporation. All rights reserved.
www.richtek.com
28
is a registered trademark of Richtek Technology Corporation.
DS3669EA-02
March 2017