A Strategy for Routing the MPC8536E in a Six-Layer PCB

Freescale Semiconductor
Application Note
AN3444
Rev. 0, 10/2007
A Strategy for Routing the MPC8536E
in a Six-Layer PCB
by
Michael George
DSD Applications
Freescale Semiconductor, Inc.
Austin, Texas
This application note is a design guide to assist the customer
in creating a low-layer, low-cost PCB design when using the
MPC8536E device. Key items of discussion include
assumed PCB stackup, power delivery to the device, and
proper signal referencing. Additionally, layout plots for the
device fan-out are also included.
NOTE
The schematic and Gerber data shown within
this application note is intended merely to
demonstrate the fan-out and power delivery
strategy necessary to achieve a six-layer
PCB. The schematic and Gerber data does not
include all the decoupling, nor do they show
all the necessary pull-ups and AC caps
required outside the BGA fan-out area. This
level of detail is captured as part of the
MPC8536E development system.
© Freescale Semiconductor, Inc., 2007. All rights reserved.
Freescale Confidential Proprietary
Contents
Ballmap Organization . . . . . . . . . . . . . . . . . . . . .2
Interface Support in Six Layers . . . . . . . . . . . . . .2
Board Stackup Considerations . . . . . . . . . . . . . .4
3.1 Stackup Proposal . . . . . . . . . . . . . . . . . . . .4
4 Signal Breakout . . . . . . . . . . . . . . . . . . . . . . . . . .6
4.1 Inside the BGA area. . . . . . . . . . . . . . . . . .6
4.2 Outside the BGA Area . . . . . . . . . . . . . . . .8
4.3 Trace Spacing Outside the BGA Area . . . .8
5 Via Usage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9
6 Power and Ground Strategy. . . . . . . . . . . . . . . .10
6.1 Power Planes . . . . . . . . . . . . . . . . . . . . . .10
6.2 Current Delivery . . . . . . . . . . . . . . . . . . . .14
6.3 PLL Filters . . . . . . . . . . . . . . . . . . . . . . . .14
6.4 Sharing Power Supplies . . . . . . . . . . . . . .15
6.5 Bypass Capacitor Placement . . . . . . . . . .16
6.6 Bulk Capacitors . . . . . . . . . . . . . . . . . . . .20
7 Signal Layer Gerber Plot . . . . . . . . . . . . . . . . . .21
8 Fan-Out Schematics . . . . . . . . . . . . . . . . . . . . .26
9 Current Delivery in the BGA Field . . . . . . . . . . .40
9.1 Via Current Capacity . . . . . . . . . . . . . . . .41
9.2 Alternate Plane Current Capacity . . . . . .42
10 References. . . . . . . . . . . . . . . . . . . . . . . . . . . . .45
11 Revision History . . . . . . . . . . . . . . . . . . . . . . . . .46
1
2
3
Ballmap Organization
1
Ballmap Organization
The MPC8536E is a 783-pin, 28 × 28 BGA array. The bus organization of the device is shown in Figure 1.
A28
A1
DDR
Local
Bus
Srds2
Core
and
Plat
Srds1
TSEC
USB
PCI and
3.3 V I/O
Figure 1. MPC8536E Bus Groupings
(Viewed from the top of the device)
2
Interface Support in Six Layers
Though the MPC8536E device can be fully broken out in six layers, there are a handful of signals that are
not necessarily optimal from a signal integrity perspective, mainly due to splits in the reference plane. Such
cases are very limited and are, therefore manageable. Table 1 enumerates the MPC8536E interfaces and
whether there is proper signal referencing in the six-layer PCB fan-out example.
Table 1. Interface Support in Six Layers
Interface
Configuration
Reference Plane
Comment
DDR2
Full 64-bit + ECC
DDR Data—GND
DDR ADDR—1.8 V
DDR CLKs—1.8 V
Fully supported.
ETSEC
RGMII
RGMII I/O—2.5 V
GTX_CLK125—GND
Both Ethernet ports can be fully routed in RGMII
mode with proper signal referencing to the
TVDD/LVDD power split, set at 2.5 V.
Signals needed for GMII can be broken out, but have
breaks in their reference plane.
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Interface Support in Six Layers
Table 1. Interface Support in Six Layers (continued)
Interface
POR Config
Configuration
Reference Plane
Comment
All user defined POR pins are GND and PWR
accessible.
Fully supported. Some POR pins cross splits but
since they are static, there is no concern.
PCI
Full 32-bit PCI with 3 GNTs
and 3 REQs
GND
PCI_REQ[4:5] and PCI_GNT[4:5] not broken out on
same layer as rest of the PCI bus.
LB
All signals are accessible
GND and PWR
LB_LAD[23:31] cross split boundaries. These signals
are not edge sensitive, therefore imperfections in their
transitions can be managed. Use of stitching caps
could be used.
SERDES1
All eight lanes accessible
GND
Fully supported
SERDES2
Both lanes accessible
GND
Fully supported
IRQ
All IRQs (0–11) and
IRQ_OUT useable
GND and PWR
Fully supported
SPI
All signals are accessible
GND
Fully supported
SDHC
All signals are accessible
GND
Fully supported
JTAG/COP
All signals are accessible
GND and PWR
Fully supported
DUARTS
Both UART ports are fully
accessible
GND and PWR
Fully supported
USB
All three ports fully accessible GND
Power pins and All unique powers accessible N/A
AVDD filters
I2C
Fully supported
GND and PWR
Fully supported
SYSCLK, RTC, and DDRCLK GND and PWR
accessible
Fully supported
1588
All signals are accessible
GND and PWR
Signals cross split boundaries. Most customers do
not use. Use of stitching caps could be used.
GPIO and
miscellaneous
signals
All signals are accessible
GND and PWR
Fully supported
TRIG_OUT
PWR
Signal crosses split boundaries. Noncritical debug
signal. Use of stitching cap could be used.
Clocking
DEBUG
Both I2C port accessible
Fully supported
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3
Board Stackup Considerations
3
Board Stackup Considerations
This section presents the considerations associated with the PCB and its stackup. Table 2 list the target
impedances needed in a six-layer design.
Table 2. Target Impedance for a Typical MPC8536E Design
Connection
Interface
Target Impedance
DDR2
8536E-to-DDR2 memory
Single ended impedance = 55–60 Ω
Differential impedance = 100 Ω ± 10%
SERDES1 (PCIe)
8536E-to-PCIe connector or device
MicroStrip
Single ended impedance = 60 ± 15%
Differential impedance = 100 Ω ± 20%
Stripline
Single ended impedance = 60 ± 15%
Differential impedance = 100 Ω ± 15%
SERDES2
(SGMII/SATA)
8536E-to-connector or device
Differential impedance = 100 Ω ± 15%
All 8536E signals
8536E-to-connector or device
Single ended interface = 55–60 Ω
USB differential
USB Phy to connector
Differential impedance = 90 Ω ± 15%
Ethernet differential
Ethernet Phy to connector
Differential impedance = 100 Ω ± 15%
Other system Items:
Additional considerations for the stackup include
• Must utilize high volume, low cost PCB technology
• Routing density
• Aspect ratio less than 10:1
• Drill size set at 10 mil
• Common core construction
• Proper signal referencing for all critical signals
3.1
Stackup Proposal
Figure 2 shows a viable stackup for achieving the target impedances noted in Table 2. The target card
thickness used is 62 mils (±7 mils). All signal routing is done on the inner two signal layers, or on the top
and bottom signal layers. No signal routing is performed on the power and ground layers.
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Board Stackup Considerations
Figure 2. Example Six-Layer PCB Stackup (Provided by Sanmina-SCI; www.sanmina-sci.com)
Table 3. Impedance Information (Provided by Sanmina-SCI; www.sanmina-sci.com)
Layer
Type
Line Width
Center-to-Center
tpd
(ps/in.)
Impedance
(Ω)
1
Single-ended
Microstrip
5 mil
n/a
153
55.15
1
Differential
Microstrip
4 mil
8 mil
154
93.28
1
Differential
Microstrip
5 mil
12 mil
154
96.54
3
Single-ended
Stripline
4 mil
n/a
179
56.0
3
Differential
Stripline
4 mil
10 mil
181
96.38
4
Single-ended
Stripline
4 mil
n/a
179
56.0
4
Differential
Stripline
4 mil
10 mil
181
96.38
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Signal Breakout
Table 3. Impedance Information (Provided by Sanmina-SCI; www.sanmina-sci.com) (continued)
4
4.1
Layer
Type
Line Width
Center-to-Center
tpd
(ps/in.)
Impedance
(Ω)
6
Single-ended
Microstrip
5 mil
n/a
153
55.15
6
Differential
Microstrip
4 mil
8 mil
154
93.28
6
Differential
Microstrip
5 mil
12 mil
154
96.54
Signal Breakout
Inside the BGA area
The key strategy used in breaking-out the MPC8536E is centered on the use of inexpensive through-hole
vias and the use of two track routing for the inner and bottom layers (see Figure 4). For all mainstream
PCB fabrication shops, this approach is considered “production-level” technology and is capable of being
produced in high volumes. Additionally, this approach produces a cheaper overall PCB design, avoiding
the additional cost associated with blind and buried type approaches.
The key items of the strategy are as follows:
• 1 mm (39.3 mil) ball pitch
• Plastic substrate
• 22 mil attach pad on top layer
• 19 mil via pad
• 28 mil anti-pad
• Single track routing on top layer (between attach pads)
• Two track routing on inner layers and on the bottom layer
— Using 4 mil traces and 4 mil space
Figure 3 and Figure 4 show the track routing strategy used for each of the signal layers.
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Signal Breakout
Signal Layer #1 (top)
Signal Layer #2
Row 12
Row 7
Drill = 10 mil
Pad = 19 mil
Row 1
Attach Pad
22 mil
2 traces per row
Width >= 4 mil
3 traces per row
Width = 4 mil
Space = 4 mil
Figure 3. Signal Routing (Top and Layer #2)
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Signal Breakout
Signal Layer #3
Signal Layer #4
2 traces per row
Width = 4 mil
2 traces per row
Width = 4 mil
Row 12
Row 7
Row 3
Figure 4. Signal Routing (Signal Layer #3 and Bottom)
4.2
Outside the BGA Area
Inside the BGA area, two track routing limits the minimum trace width to 4 mils and the minimum spacing
to 4 mils. Outside the BGA area, this is not the case. Since wider traces have less dielectric loss, the
designer may find it useful to use larger trace widths once outside the via array. Similarly, in the cases of
differential pairs, the air gaps can be adjusted as needed in order to hit desired impedance targets.
4.3
Trace Spacing Outside the BGA Area
To minimize crosstalk opportunities once outside the BGA area, the spacing between differing signal
groups must be observed. This spacing, denoted as ‘S,’ is based on the dielectric thickness ‘H’ (shown in
Figure 5). For the stackup shown in Figure 2, the dielectric thickness is 4.0. Using a 3:1 spacing rule, the
air gap between differing signal groups should be at least 12 mil.
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Via Usage
Trace 1
S
Trace 2
H
Reference Plane
Figure 5. Trace Spacing Outside the BGA Area
5
Via Usage
For the six-layer PCB a 10-mil drill is used. A 10-mil drill has favorably cost advantages since smaller drill
sizes incur additional cost. During fabrication, the drill tolerance is specified as +0/–3 mil, giving a
finished hole size (FHS) of approximately 7–7.5 mil.
Using a 10-mil drill an aspect ratio of ~ 6:1 is realized. This aspect ratio is based on an 0.062-inch board
thickness and is well within the high volume, production capabilities of all mainstream PCB vendors.
Figure 6 depicts the via model used for the six-layer PCB.
39.3 mil (1 mm) BGA Pitch
28 mil Anti-Pad
19 mil Pad
10 mil Drill
7–7.5 mil FHS
11.3 mil
19.3 mil
Standard Via
Legend
= Section of power plane flowing between vias
= Outer layer signal tracks
= Inner layer signal tracks
= Via barrel/via pad copper
= PCB
Figure 6. Cross Section of PCB
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Power and Ground Strategy
6
Power and Ground Strategy
The MPC8536E requires several power supplies for each subsystem (DDR, Ethernet, SerDes, and so forth)
as well as the interconnect fabric itself (the platform voltage). The total number of supplies a system needs
depends on the interfaces, the interface voltages required to connect with external peripherals, and the
number of those voltages that are common and shareable.
Consult the MPC8536E PowerQUICC™ III Integrated Processor Hardware Specifications for accurate
voltage and current requirements. For convenience, Table 4 provides a snapshot of the MPC8536E power
requirements at the date of this application note. The table also reflects the unique power splits which
where constructed in the six-layer PCB example (refer to the Power Rails column). In short, a total of
seven unique power rails are used.
Table 4. MPC8536E Power Requirements 1
1
Typical
Voltage
Tolerance
PMAX
1.1 V
or
1.0 V
±50 mV
7W
VDD_PLAT
AVDD_PLAT
AVDD_PCI
AVDD_DDR
AVDD_LBIU
AVDD_SRDS
AVDD_SRDS2
1.0 V
±50 mV
5W
SerDes
SVDD
XVDD
1.0 V
±50 mV
0.71W
DDR2 bus
GVDD
1.8 V
±90 mV
2.5 W
Ethernet
LVDD
TVDD
2.5 V
±125 mV
0.24 W
Local bus
BVDD
3.3 V
±125 mV
0.33 W
Misc/PCI
OVDD
3.3 V
±125 mV
0.33 W
Power Rails
Symbol
Core power
VDD_CORE
AVDD_CORE
Platform
(internal buses)
These figures are subject to change without notice. Consult the latest
version of the MPC8536E PowerQUICC™ III Integrated Processor Hardware
Specifications.
Note that Table 4 lists the power requirements for the MPC8536E only; it does not include requirements
for external devices, memory, and so forth. At the very least, additional power is needed to drive connected
I/O pins, and the internal logic of the other devices often shared with the MPC8536E supplies.
6.1
Power Planes
The following pictures (Figure 7 through Figure 10) highlight the power strategy used for the six-layer
PCB. The ground reference for the PCB is a solid ground plane at layer 2. Since it is a solid plane with no
splits, the ground layer is not shown.
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Power and Ground Strategy
Figure 7. Power Plane (Layer 5 of 6)
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Power and Ground Strategy
Figure 8. SXVDD Power (Layer 2 of 6)
Figure 9. VDD PLAT (Layer 4 of 6)
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Power and Ground Strategy
Figure 10. OVDD, VDD_PLAT, and Rest of SXVDD (Layer 6 of 6—Bottom)
For sensitive supplies (such as XVDD and SVDD), a key requirement for power sharing is that the planes
be relatively isolated. One effective strategy is to route the power planes separately and tie them together
at the power source. See Figure 11.
MPC8536E
XVDD
SVDD
VDD_PLAT
1.0 V Power Supply
Figure 11. Common Source Split Planes
Another strategy is to use a low-pass filter to eliminate coupled noise, as long as there is sufficient current
capacity in the components and connections. In either case, once separated, treat the two as independent
power planes and route and bypass them separately.
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Power and Ground Strategy
6.2
Current Delivery
An important consideration in the six-layer PCB is ensuring all power rails have sufficient copper for
proper current delivery. The two highest power rails on the MPC8536E are VDD_CORE and VDD_PLAT. The
max power requirement for VDD_CORE is 7 W and the max power requirements for VDD_PLAT is 5 W.
Within a congested BGA array, the current travels down multiple 11-mil trace segments as it travels to the
power pins, assuming the via stackup referenced in Figure 6 is used. The current-carrying capacity of these
11-mil traces is highly dependent on the current model chosen, either IPC2221A or the newer research
performed by Johannes Adam of Flomerics Ltd. For greater detail on these two approaches see Section 9,
“Current Delivery in the BGA Field.”
In short, Table 5 depicts the current capacity differences between the two approaches assuming a
maximum temperature rise of 20°C. Additionally, the last column highlights the current capacity assumed
for the MPC8536E six-layer PCB.
Table 5. Current Capacity of an 11-mil Trace Adam’s Model vs. IPC
Location
Copper Plating
(oz.)
11-mil Trace
(Adam’s Model)
(A)
11-mil Trace
(IPC2221A)
(A)
11-mil Trace
(Capacity Assumed for the
MPC8536E Six-Layer PCB)
(A)
Outer
0.5
1.210
0.777
1.0
1.0
1.711
1.285
1.5
1.5
2.420
1.730
N/A
2.0
3.422
2.130
N/A
0.5
1.149
0.390
0.75
1.0
1.625
0.582
1.1
1.5
2.299
0.865
N/A
2.0
3.251
1.065
N/A
Inner
Taking the last column from Table 5 and the number of 11-mil channels achieved in the six-layer PCB,
Table 6 highlights the current capacity for both VDD_CORE and VDD_PLAT.
Table 6. Current Capacity Achieved in the Six-Layer PCB
Power Rail
6.3
Current per
Copper Weight
No. of 11-mil Traces
Trace
Used
Supplying Power
(A)
(oz.)
Total Current Supplied
in Six-Layer PCB
(A)
Total Current
Required
VDD_CORE
1.0
13
1.1
14.3
6.4 A (7 W/1.1 V)
VDD_PLAT
0.5
11
0.75
8.25
5.0 A (5 W/1.0 V)
PLL Filters
The MPC8536E has six PLLs which each require a filter circuit. The PLL pins are placed on the package
in order to minimize noise and to allow ease during layout. An example layout for the filters are shown in
Figure 12. This figure shows the filters for AVDD_PCI, AVDD_DDR, AVDD_CORE, and AVDD_PLAT. The
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Power and Ground Strategy
residual filters would be similar. For the exact filter values refer to the MPC8536E PowerQUICC™ III
Integrated Processor Hardware Specifications.
To ensure a high quality filter is realized, use the following rules:
• Place the components of the filter as close a possible to their respective pin
• Keep the traces as short as possible
• Use a 10-mil trace width or larger. An area fill is also a possibility.
• Maintain at least 20-mil clearance between the filter and other signals.
Filters
Figure 12. Example Layout for AVDD Filters
6.4
Sharing Power Supplies
The six-layer design referenced in this application note assumes all processor powers referenced in Table 4
are supplied by unique power supplies. If the customer chooses, further sharing of power supplies can be
achieved to reduce the number of supplies needed at the board-level. Table 7 shows some acceptable
options for sharing MPC8536E power rails.
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Power and Ground Strategy
Table 7. MPC8536E Power Requirements
Power Source
Symbol
Voltage
Comments
Core power +
PLL filter
VDD_CORE
AVDD_CORE
1.0 V
If core and platform rails are shared, the upper core frequency is restricted.
Additionally, there is no option for disabling the core power when the device is
in ‘deep sleep’ state and the platform is alive.
PLLs are sourced from RC filter circuit derived from 1.0 V rail.
Platform
(internal buses)
+ other PLL
filters
VDD_PLAT
AVDD_PCI
AVDD_DDR
AVDD_LBIU
AVDD_SRDS
AVDD_SRDS2
SerDes
SVDD
XVDD
Memory
GVDD
1.8 V
Unique rail on the MPC8536E device. Could possibly be shared with another
1.8 V device on the board.
Ethernet
LVDD
TVDD
2.5 V
2.5 V is readily usable by most PHYs; however, 3.3 V is not suitable for RGMII
mode.
Local bus
BVDD
Separate filtered plane but derived from the same 1.0 V power regulator.
2.5 V requires low-voltage flash memory and so forth
Or alternatively
Ethernet
LVDD
TVDD
Local bus
BVDD
PCI/Misc
OVDD
6.5
3.3 V
3.3 V is not suitable for RGMII mode
Bypass Capacitor Placement
Because of the high current transients on the VDD_CORE and VDD_PLAT power pins, take care to bypass
these power pins and to provide a good connection between the BGA pads and the power and ground
planes. In particular, the SMD capacitors should have pads directly attached to the via ring (or even better,
within it using via-in-pad methods). Figure 13 shows the dispersion of VDD_CORE and VDD_PLAT power
pins along with the ground pattern.
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Power and Ground Strategy
L
M
N
P
R
T
U
V
W
Y
11
12
13
14
15
16
17
18
19
20
21
22
23
24
VDD_PLAT
Ground
VDD_CORE
Figure 13. MPC8536E VDD_CORE, VDD_PLAT, and Ground Pattern (Bottom View)
NOTE
This is a bottom view of the center portion of interest within the BGA array.
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Power and Ground Strategy
After the power and grounds are escaped, the SMD 0402 capacitors can be placed so that the capacitor
pads attach directly to the power vias on the side. Minimize or eliminate the trace between the via and the
capacitor pad. Figure 14 shows three possible attachment methods.
All are SMD0402
Vias Embedded in Pads
Vias to the Side of Pads
Vias Offset From Pads
Best
Good
OK
Figure 14. MPC8536E SMD Capacitor Via Placement
Using either of these methods, Figure 15 shows the relative attachment of the SMD 0402 capacitors.
Again, this is a view through the top of the board.
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Power and Ground Strategy
N
P
C
M
C
L
R
T
V
U
W
Y
11
12
13
C
C
C
14
C
C
15
C
C
C
C
C
C
C
C
C
C
16
C
17
C
C
C
18
19
C
C
C
20
21
22
23
24
VDD_PLAT
GROUND
VDD_CORE
Figure 15. MPC8536E CORE, PLAT, and Ground SMD 0402 Capacitor Placement (Bottom View)
Other capacitors, such as those required for the other power rails, are not shown but can be attached in the
same manner. If the PCB is not permitted to use via-in-pad connections, the capacitors can be shifted to
attach to a pad in the area between the BGA pads. In that case, use the same relative pattern, but each
capacitor shifts a little.
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Power and Ground Strategy
6.6
Bulk Capacitors
Bulk capacitors can be placed outside the periphery of the MPC8536E die, as close as reasonably possible.
Systems with heatsinks and/or sockets probably need some additional spacing, but the high-frequency
capacitors handle the fastest transients, allowing the bulk capacitors to be spaced a little further away. Keep
them within 2 cm. Figure 16 shows the MPC8536E VDD_CORE and VDD_PLAT bulk capacitor placement.
Low-ESR
Bulk Capacitors
A1
A28
MPC8536E
0.46 mils
0.46 mils
VPLAT
Power
Split
Low-ESR
Bulk Capacitors
VCORE
Power
Split
Figure 16. MPC8536E Bulk Capacitor Placement (Top View)
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Signal Layer Gerber Plot
7
Signal Layer Gerber Plot
Figure 17 through Figure 20 show the signal layers for the six-layer PCB example. Again, the intent is to
demonstrate that the MPC8536E signals can be broken in a six-layer PCB and does not include all the
decoupling, nor does it show all the necessary pull-ups, AC caps, and other circuitry that would be required
outside the BGA fan-out area. This level of detail is captured as part of the MPC8536E development
system.
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Signal Layer Gerber Plot
Figure 17. Top Gerber Plot (Layer 1 of 6)
A Strategy for Routing the MPC8536E in a Six-Layer PCB, Rev. 0
22
Freescale Confidential Proprietary
Freescale Semiconductor
Signal Layer Gerber Plot
Figure 18. Signal #2 Gerber Plot (Layer 3 of 6)
A Strategy for Routing the MPC8536E in a Six-Layer PCB, Rev. 0
Freescale Semiconductor
Freescale Confidential Proprietary
23
Signal Layer Gerber Plot
Figure 19. Signal #3 Gerber Plot (Layer 4 of 6)
A Strategy for Routing the MPC8536E in a Six-Layer PCB, Rev. 0
24
Freescale Confidential Proprietary
Freescale Semiconductor
Signal Layer Gerber Plot
Figure 20. Bottom Gerber Plot (Layer 6 of 6)
A Strategy for Routing the MPC8536E in a Six-Layer PCB, Rev. 0
Freescale Semiconductor
Freescale Confidential Proprietary
25
Fan-Out Schematics
8
Fan-Out Schematics
This section contains the fan-out schematics used to perform the six-layer PCB study. It does not include
all the decoupling, nor does it show all the necessary pull-ups, AC caps, and other circuitry that would be
required outside the BGA fan-out area. This level of detail is captured as part of the MPC8536E
development system.
2
3
4
8536
5
6
7
DDR SECTION
PBGA_28X28X1MM_SKT
9C2
9D2
9D2
9D2
9D2
9D2
10D2
10D2
10D2
10D2
10D2
10D2
10C6
9C6
BI
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
MCK0
MCK0_B
MCK1
MCK1_B
MCK2
MCK2_B
MCK3
MCK3_B
MCK4
MCK4_B
MCK5
MCK5_B
00
01
02
03
04
05
06
07
08
09
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
MDQ<00..63>
GVDD
18
R4
18
R3
MCK0
MCK0_B
MCK1
MCK1_B
MCK2
MCK2_B
MCK3
MCK3_B
MCK4
MCK4_B
MCK5
MCK5_B
A26
B26
C22
D21
D25
B25
D22
E21
A24
A23
B20
A20
A25
B24
B21
A21
E19
D19
E16
C16
F19
F18
F17
D16
B18
A18
A15
B14
B19
A19
A16
B15
D1
F3
G1
H2
E4
G5
H3
J4
B2
C3
F2
G2
A2
B3
E1
F1
L5
L4
N3
P3
J3
K4
N4
P4
J1
K1
P1
R1
J2
K2
P2
R2
MDQ00
MDQ01
MDQ02
MDQ03
MDQ04
MDQ05
MDQ06
MDQ07
MDQ08
MDQ09
MDQ10
MDQ11
MDQ12
MDQ13
MDQ14
MDQ15
MDQ16
MDQ17
MDQ18
MDQ19
MDQ20
MDQ21
MDQ22
MDQ23
MDQ24
MDQ25
MDQ26
MDQ27
MDQ28
MDQ29
MDQ30
MDQ31
MDQ32
MDQ33
MDQ34
MDQ35
MDQ36
MDQ37
MDQ38
MDQ39
MDQ40
MDQ41
MDQ42
MDQ43
MDQ44
MDQ45
MDQ46
MDQ47
MDQ48
MDQ49
MDQ50
MDQ51
MDQ52
MDQ53
MDQ54
MDQ55
MDQ56
MDQ57
MDQ58
MDQ59
MDQ60
MDQ61
MDQ62
MDQ63
K15
H15
MDIC1
MDIC0
A13
MAPAR_ERR_B
MDIC1
MDIC0
U1
A9
B9
J11
H11
J6
K6
A8
B8
J13
H13
H8
J8
MVREF
A28
MDQS0
MDQS0_B
MDQS1
MDQS1_B
MDQS2
MDQS2_B
MDQS3
MDQS3_B
MDQS4
MDQS4_B
MDQS5
MDQS5_B
MDQS6
MDQS6_B
MDQS7
MDQS7_B
MDQS8
MDQS8_B
C23
D24
A22
B22
E17
C18
B16
A17
K5
J5
D2
C1
M3
M4
N1
M2
D13
E13
MDQS0
MDQS0_B
MDQS1
MDQS1_B
MDQS2
MDQS2_B
MDQS3
MDQS3_B
MDQS4
MDQS4_B
MDQS5
MDQS5_B
MDQS6
MDQS6_B
MDQS7
MDQS7_B
MDQS8
MDQS8_B
MECC0
MECC1
MECC2
MECC3
MECC4
MECC5
MECC6
MECC7
G12
D14
F11
C11
G14
F14
C13
D12
0
1
2
3
4
5
6
7
MDM0
MDM1
MDM2
MDM3
MDM4
MDM5
MDM6
MDM7
MDM8
C25
B23
D18
B17
G4
C2
L3
L2
F13
MBA0
MBA1
MBA2
A4
B5
B13
MA00
MA01
MA02
MA03
MA04
MA05
MA06
MA07
MA08
MA09
MA10
MA11
MA12
MA13
MA14
MA15
B7
G8
C8
A10
D9
C10
A11
F9
E9
B12
A5
A12
D11
F7
E10
F10
MPC8536
DDR_SDRAM
1 OF 10
MVREF
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
9A5
9A5
9A5
9A5
9A5
9A5
9A5
9A5
9A5
9A5
9A5
9A5
9A5
9B5
9B5
9B5
9B5
9B5
10A5
10A5
10A5
10A5
10A5
10A5
10A5
10A5
10A5
10A5
10A5
10A5
10B5
10B5
10B5
10B5
10B5
10B5
0
1
2
00
01
02
03
04
05
06
07
08
09
10
11
12
13
14
15
BI
9A2
10D2
10A2
MDM<0..8>
BI
MBA<0..2>
OUT
9B2
10B2
MA<00..15>
OUT
9B2
10B2
9A2
10B2
MWE_B
B4
MWE_B
OUT
9C2
10C2
MRAS_B
MCAS_B
C5
E7
MRAS_B
MCAS_B
OUT
OUT
9C2
9C2
10C2
10C2
MCS0_B
MCS1_B
MCS2_B
MCS3_B
D3
H6
C4
G6
MCS0_B
MCS1_B
MCS2_B
MCS3_B
OUT
OUT
OUT
OUT
9C2
9C2
10C2
10C2
MCKE0
MCKE1
MCKE2
MCKE3
H10
K10
G10
H9
MCKE0
MCKE1
MCKE2
MCKE3
OUT
OUT
OUT
OUT
9C2
9C2
10C2
10C2
MODT0
MODT1
MODT2
MODT3
E5
H7
E6
F6
MODT0
MODT1
MODT2
MODT3
OUT
OUT
OUT
OUT
9C2
9C2
10C2
10C2
MAPAR_OUT
A6
OUT
9D2
MAPAR_OUT
9D2
C1
0.1UF
MECC_<0..7>
0
1
2
3
4
5
6
7
8
IN
10D3
PROJECT:
8536_FAN_OUT_SCHEMATIC
ENGINEER:
2
3
FREESCALE
4
C
fid
i l
5
P
6
ENGINEER
NAME
7
DRAWING
i
A Strategy for Routing the MPC8536E in a Six-Layer PCB, Rev. 0
26
Freescale Confidential Proprietary
Freescale Semiconductor
Fan-Out Schematics
2
3
4
5
6
7
PBGA_28X28_1MM_SKT
U1
11D6
11D6
11D6
11D6
11D6
11D6
11C6
11C6
IN
IN
IN
IN
IN
IN
IN
IN
SD1_RX0
SD1_RX0_B
SD1_RX1
SD1_RX1_B
SD1_RX2
SD1_RX2_B
SD1_RX3
SD1_RX3_B
N28
N27
P26
P25
R28
R27
T26
T25
SD1_RX0
SD1_RX0_B
SD1_RX1
SD1_RX1_B
SD1_RX2
SD1_RX2_B
SD1_RX3
SD1_RX3_B
11C6
11C6
11C6
11C6
11C6
11C6
11C6
11C6
IN
IN
IN
IN
IN
IN
IN
IN
SD1_RX4
SD1_RX4_B
SD1_RX5
SD1_RX5_B
SD1_RX6
SD1_RX6_B
SD1_RX7
SD1_RX7_B
Y26
Y25
AA28
AA27
AB26
AB25
AC28
AC27
SD1_RX4
SD1_RX4_B
SD1_RX5
SD1_RX5_B
SD1_RX6
SD1_RX6_B
SD1_RX7
SD1_RX7_B
SS
V27
SD1_TST_CLK
SD1_TST_CLK_B
T22
T23
SD1_TX0
SD1_TX0_B
SD1_TX1
SD1_TX1_B
SD1_TX2
SD1_TX2_B
SD1_TX3
SD1_TX3_B
M23
M22
N21
N20
P23
P22
R21
R20
SD1_TX0
SD1_TX0_B
SD1_TX1
SD1_TX1_B
SD1_TX2
SD1_TX2_B
SD1_TX3
SD1_TX3_B
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
11D3
11D3
11D3
11D3
11D3
11D3
11C3
11C3
SD1_TX4
SD1_TX4_B
SD1_TX5
SD1_TX5_B
SD1_TX6
SD1_TX6_B
SD1_TX7
SD1_TX7_B
U21
U20
V23
V22
W21
W20
Y23
Y22
SD1_TX4
SD1_TX4_B
SD1_TX5
SD1_TX5_B
SD1_TX6
SD1_TX6_B
SD1_TX7
SD1_TX7_B
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
11C3
11C3
11C3
11C3
11C3
11C3
11C3
11C3
SD1_REF_CLK
SD1_REF_CLK_B
U28
U27
SD1_PLL_TPD
SD1_PLL_TPA
V28
V26
SD1_PLL_TPD
SD1_PLL_TPA
AE28
M26
SD1_IMP_CAL_TX
SD1_IMP_CAL_RX
MPC8536
SERDES 1
2 OF 10
SD1_IMP_CAL_TX
SD1_IMP_CAL_RX
AGND_SRDS
SD1_TST_CLK
SD1_TST_CLK_B
TP5
TP6
SD1_REF_CLK
SD1_REF_CLK_B
TP7
TP13
TP8
TP14
R8
PCI
EXPR
TP141
TP142
100
R7
200
PBGA_28X28_1MM_SKT
U1
SD2_TST_CLK
SD2_TST_CLK_B
TP1
GMII
TP2
TP3
TP4
P6
P7
N8
N9
SD2_RX0
SD2_RX0_B
SD2_RX1
SD2_RX1_B
SD2_RX0
SD2_RX0_B
SD2_RX1
SD2_RX1_B
SD2_TX0
SD2_TX0_B
SD2_TX1
SD2_TX1_B
L8
L9
SD2_TST_CLK
SD2_TST_CLK_B
P11
P12
M11
M12
TP10
TP9
SD2_TX0
SD2_TX0_B
SD2_TX1
SD2_TX1_B
SATA OR SGMII
TP48
TP112
TP89
TP90
MPC8536
SERDES 2
3 OF 10
T2
AGND_SRDS2
SD2_REF_CLK
SD2_REF_CLK_B
M6
M7
SD2_REF_CLK
SD2_REF_CLK_B
SD2_PLL_TPA
SD2_PLL_TPD
T3
L7
SD2_PLL_TPA
SD2_PLL_TPD
SD2_IMP_CAL_RX
SD2_IMP_CAL_TX
R7
L6
SD2_IMP_CAL_RX
SD2_IMP_CAL_TX
TP17
TP18
TP11
TP15
TP12
TP16
R10
100
200
R9
PROJECT:
8536_FAN_OUT_SCHEMATIC
ENGINEER:
2
3
4
SC
C
5
6
ENGINEER
NAME
7
DRAWING
f
A Strategy for Routing the MPC8536E in a Six-Layer PCB, Rev. 0
Freescale Semiconductor
Freescale Confidential Proprietary
27
Fan-Out Schematics
2
3
4
PCI
5
32
6
7
BIT
PBGA_28X28_1MM_SKT
AD26
AE25
AF26
AG26
AF25
AC24
AG27
AD24
AG25
AE24
AG24
AH23
AH24
AC23
AE23
AF23
AC20
AE19
AF18
AC19
AE18
AB19
AB18
AE17
AD17
AA18
AC16
AB17
AC15
AA17
Y17
AB15
00
01
02
03
04
05
06
07
08
09
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
U1
PCI1_AD00
PCI1_AD01
PCI1_AD02
PCI1_AD03
PCI1_AD04
PCI1_AD05
PCI1_AD06
PCI1_AD07
PCI1_AD08
PCI1_AD09
PCI1_AD10
PCI1_AD11
PCI1_AD12
PCI1_AD13
PCI1_AD14
PCI1_AD15
PCI1_AD16
PCI1_AD17
PCI1_AD18
PCI1_AD19
PCI1_AD20
PCI1_AD21
PCI1_AD22
PCI1_AD23
PCI1_AD24
PCI1_AD25
PCI1_AD26
PCI1_AD27
PCI1_AD28
PCI1_AD29
PCI1_AD30
PCI1_AD31
PCI1_AD<31..00>
AH25
AD22
AD20
AD18
PCI1_C_BE0_B
PCI1_C_BE1_B
PCI1_C_BE2_B
PCI1_C_BE3_B
BI
BI
BI
BI
PCI1_PAR
AC22
PCI1_PAR
BI
PCI1_CLK
AH26
PCI1_FRAME_B
PCI1_TRDY_B
PCI1_IRDY_B
PCI1_STOP_B
PCI1_DEVSEL_B
AE20
AF21
AB20
AD21
AC21
PCI1_C_BE0_B
PCI1_C_BE1_B
PCI1_C_BE2_B
PCI1_C_BE3_B
MPC8536
PCI1
4 OF 10
PCI1_IDSEL
AE16
PCI1_PERR_B
PCI1_SERR_B
AB21
AF22
PCI1_REQ0_B
PCI1_REQ1_B
PCI1_REQ2_B
GPIO00_PCI1_REQ3_B
GPIO01_PCI1_REQ4_B
AA16
W16
AF13
Y15
AE15
PCI1_GNT0_B
PCI1_GNT1_B
PCI1_GNT2_B
GPIO02_PCI1_GNT3_B
GPIO03_PCI1_GNT4_B
W18
Y16
AF14
AA15
AC14
12D1
BI
12D3
PCI1_CLK
PCI1_FRAME_B
PCI1_TRDY_B
PCI1_IRDY_B
PCI1_STOP_B
PCI1_DEVSEL_B
12C3
12B8
12B8
12B6
12C6
12C3
12C3
12B8
12C3
12C6
12C8
12B3
12B3
12B3
12B3
12B3
12B6
12B6
12B6
12B6
12B6
12B3
12B3
12B6
12B6
TP25
BI
BI
BI
BI
BI
PCI1_IDSEL
PCI1_PERR_B
PCI1_SERR_B
12B8
12B6
12B6
12B3
12B1
12B1
12B1
12B1
12B1
TP19
BI
BI
12B1
12B1
PCI1_REQ0_B
PCI1_REQ1_B
PCI1_REQ2_B
GPIO00_PCI1_REQ3_B
GPIO01_PCI1_REQ4_B
BI
BI
BI
12B1
12B3
12B6
TP22
TP23
PCI1_GNT0_B
PCI1_GNT1_B
PCI1_GNT2_B
GPIO02_PCI1_GNT3_B
GPIO03_PCI1_GNT4_B
BI
BI
BI
12B1
12B3
12B6
TP144
TP145
12D5
PROJECT:
8536_FAN_OUT_SCHEMATIC
ENGINEER:
2
3
4
SC
C
5
6
ENGINEER
NAME
7
DRAWING
f
A Strategy for Routing the MPC8536E in a Six-Layer PCB, Rev. 0
28
Freescale Confidential Proprietary
Freescale Semiconductor
Fan-Out Schematics
2
3
4
5
6
7
LOCAL BUS
PBGA_28X28_1MM_SKT
13A2
BI
LAD<00..31>
00
01
02
03
04
05
06
07
08
09
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
13D2
OUT
LA<27..31>
27
28
29
30
31
TP185
TP130
TP131
TP132
LDP0
LDP1
LDP2
LDP3
K22
L21
L22
K23
K24
L24
L25
K25
L28
L27
K28
K27
J28
H28
H27
G27
G26
F28
F26
F25
E28
E27
E26
F24
E24
C26
G24
E23
G23
F22
G22
G21
U1
LAD00
LAD01
LAD02
LAD03
LAD04
LAD05
LAD06
LAD07
LAD08
LAD09
LAD10
LAD11
LAD12
LAD13
LAD14
LAD15
LAD16
LAD17
LAD18
LAD19
LAD20
LAD21
LAD22
LAD23
LAD24
LAD25
LAD26
LAD27
LAD28
LAD29
LAD30
LAD31
L19
K16
K17
H17
G17
LA27
LA28
LA29
LA30
LA31
K26
G28
B27
E25
LDP0
LDP1
LDP2
LDP3
LCS0_B
LCS1_B
LCS2_B
LCS3_B
LCS4_B
LCS5_B_DMA_DREQ2_B
LCS6_B_DMA_DACK2_B
LCS7_B_DMA_DDONE2_B
LWE0_B_LBS0_B_LFWE_B
LWE1_B_LBS1_B
LWE2_B_LBS2_B
LWE3_B_LBS3_B
MPC8536
LOCAL BUS
5 OF 10
K18
G19
H19
H20
G16
H16
J16
L18
LCS0_B
LCS1_B
LCS2_B
LCS3_B
LCS4_B
LCS5_B_DMA_DREQ2_B
LCS6_B_DMA_DACK2_B
LCS7_B_DMA_DDONE2_B
TP27
TP28
TP29
TP30
TP31
TP32
TP33
TP34
J22
H22
H23
H21
LWE0_B_LBS0_B_LFWE_B
LWE1_B_LBS1_B
LWE2_B_LBS2_B
LWE3_B_LBS3_B
TP35
TP36
TP37
TP38
LBCTL
J25
LBCTL
OUT
LALE
J26
LALE
OUT
LGPL0_LFCLE
LGPL1_LFALE
LGPL2_LOE_B_LFRE_B
LGPL3_LFWP_B
LGPL4_LGTA_B_LUPWAIT_LPBSE_LFRB
LGPL5
J20
K20
G20
H18
L20
K19
LGPL0_LFCLE
LGPL1_LFALE
LGPL2_LOE_B_LFRE_B
LGPL3_LFWP_B
LGPL4_LGTA_B_LUPWAIT_LPBSE_LFRB
LGPL5
LCLK0
LCLK1
LCLK2
H24
J24
H25
LCLK2
LSYNC_IN
LSYNC_OUT
D27
D28
GPIO4_SDHC_CD
GPIO5_SDHC_WP
SDHC_CLK
SDHC_CMD
SDHC_DAT0
SDHC_DAT1
SDHC_DAT2
SDHC_DAT3
SPI_CS0_SDHC_DAT4
SPI_CS1_SDHC_DAT5
SPI_CS2_SDHC_DAT6
SPI_CS3_SDHC_DAT7
SPI
& SD
INTERFACE
SPI_MOSI
SPI_MISO
SPI_CLK
LCLK0
LCLK1
LSYNC_IN
LSYNC_OUT
AH11
AG10
AG13
AH10
GPIO4_SDHC_CD
GPIO5_SDHC_WP
SDHC_CLK
SDHC_CMD
AG12
AH12
AH13
AG11
AE8
AC10
AF9
AA10
SDHC_DAT0
SDHC_DAT1
SDHC_DAT2
SDHC_DAT3
SPI_CSO_SDHC_DAT4
SPI_CS1_SDHC_DAT5
SPI_CS2_SDHC_DAT6
SPI_CS3_SDHC_DAT7
AF8
AD9
AD8
SPI_MOSI
SPI_MISO
SPI_CLK
13B2
13C1
TP47
TP44
TP45
TP42
TP49
TP43
TP39
TP40
TP41
TP46
TP26
TP117
TP118
TP119
TP120
TP121
TP122
TP123
TP124
TP125
TP126
TP127
TP128
TP129
TP160
TP161
PROJECT:
8536_FAN_OUT_SCHEMATIC
ENGINEER:
2
3
FREESCALE
4
Confidential
5
6
ENGINEER
NAME
7
DRAWING
Proprietary
A Strategy for Routing the MPC8536E in a Six-Layer PCB, Rev. 0
Freescale Semiconductor
Freescale Confidential Proprietary
29
Fan-Out Schematics
2
3
4
5
GIBABIT
6
ETHERNET -
7
RGMII
PBGA_28X28_1MM_SKT
14C3
14C3
14C3
14C3
OUT
OUT
OUT
OUT
14C3
OUT
14C3
OUT
TSEC1_TXD4
TSEC1_TXD5
TSEC1_TXD6
TSEC1_TXD7
W6
W4
W5
W3
Y5
Y8
AA5
AA8
TSEC1_TXD0
TSEC1_TXD1
TSEC1_TXD2
TSEC1_TXD3
TSEC1_TXD4
TSEC1_TXD5
TSEC1_TXD6
TSEC1_TXD7
TSEC1_TX_EN
TSEC1_TX_ER
TSEC1_TX_CLK
TSEC1_GTX_CLK
TSEC1_CRS
TSEC1_COL
W1
AB5
AB4
W2
AA9
AB6
TSEC1_TX_EN
TSEC1_TX_ER
TSEC1_TX_CLK
TSEC1_GTX_CLK
TSEC1_CRS
TSEC1_COL
TP173
TP174
TP175
TP176
TSEC1_RXD4
TSEC1_RXD5
TSEC1_RXD6
TSEC1_RXD7
Y2
Y1
Y3
AA2
Y6
AB8
AB7
AB3
TSEC1_RXD0
TSEC1_RXD1
TSEC1_RXD2
TSEC1_RXD3
TSEC1_RXD4
TSEC1_RXD5
TSEC1_RXD6
TSEC1_RXD7
TP177
TSEC1_RX_DV
TSEC1_RX_ER
TSEC1_RX_CLK
AA1
Y9
AA3
TSEC1_RX_DV
TSEC1_RX_ER
TSEC1_RX_CLK
Y10
Y11
EC_MDC
EC_MDIO
TSEC1_TXD0
TSEC1_TXD1
TSEC1_TXD2
TSEC1_TXD3
TP146
TP147
TP148
TP149
TP150
TP151
TP162
TP172
14D3
14D3
14D3
14D3
IN
IN
IN
IN
TSEC1_RXD0
TSEC1_RXD1
TSEC1_RXD2
TSEC1_RXD3
14D3
IN
14D3
IN
14A1
14A1
OUT
BI
EC_MDC
EC_MDIO
TP20
TP21
TP24
TSEC_1588_CLK
TSEC_1588_TRIG_IN0
TSEC_1588_TRIG_IN1
W9
W8
W7
TSEC_1588_CLK
TSEC_1588_TRIG_IN0
TSEC_1588_TRIG_IN1
U1
MPC8536
ETHERNET
6 OF 10
TSEC3_TXD0
TSEC3_TXD1
TSEC3_TXD2
TSEC3_TXD3
TSEC3_TXD4
TSEC3_TXD5
TSEC3_TXD6
TSEC3_TXD7
T6
T5
T7
T8
V9
U8
V8
T12
TSEC3_TXD0
TSEC3_TXD1
TSEC3_TXD2
TSEC3_TXD3
TSEC3_TXD4
TSEC3_TXD5
TSEC3_TXD6
TSEC3_TXD7
OUT
OUT
OUT
OUT
TSEC3_TX_EN
TSEC3_TX_ER
TSEC3_TX_CLK
TSEC3_GTX_CLK
TSEC3_CRS
TSEC3_COL
V5
U9
U10
U5
T10
T9
TSEC3_TX_EN
TSEC3_TX_ER
TSEC3_TX_CLK
TSEC3_GTX_CLK
TSEC3_CRS
TSEC3_COL
OUT
TSEC3_RXD0
TSEC3_RXD1
TSEC3_RXD2
TSEC3_RXD3
TSEC3_RXD4
TSEC3_RXD5
TSEC3_RXD6
TSEC3_RXD7
V3
U2
U3
V1
V6
U6
U13
U12
TSEC3_RX_DV
TSEC3_RX_ER
TSEC3_RX_CLK
EC_GTX_CLK125
TSEC_1588_CLK_OUT
TSEC_1588_TRIG_OUT0
TSEC_1588_TRIG_OUT1
TSEC_1588_PULSE_OUT1
TSEC_1588_PULSE_OUT2
TSEC3_RXD0
TSEC3_RXD1
TSEC3_RXD2
TSEC3_RXD3
TSEC3_RXD4
TSEC3_RXD5
TSEC3_RXD6
TSEC3_RXD7
V2
T4
U1
TSEC3_RX_DV
TSEC3_RX_ER
TSEC3_RX_CLK
AA6
EC_GTX_CLK125
V10
U11
W10
V11
T11
14B3
14B3
14B3
14B3
TP152
TP153
TP154
TP155
14B3
TP156
TP157
14B3
OUT
TP178
TP179
14C3
14B3
14B3
14B3
IN
IN
IN
IN
TP180
TP181
TP182
TP183
IN
TP184
14C3
14C3
IN
TP50
TSEC_1588_CLK_OUT
TSEC_1588_TRIG_OUT0
TSEC_1588_TRIG_OUT1
TSEC_1588_PULSE_OUT1
TSEC_1588_PULSE_OUT2
TP163
TP164
TP165
TP166
TP167
PROJECT:
8536_FAN_OUT_SCHEMATIC
ENGINEER:
ENGINEER
NAME
A Strategy for Routing the MPC8536E in a Six-Layer PCB, Rev. 0
30
Freescale Confidential Proprietary
Freescale Semiconductor
Fan-Out Schematics
2
3
4
MISC
5
/
6
7
OTHERS
PBGA_28X28_1MM_SKT
U1
TEMP_ANODE
TEMP_CATHODE
TP54
TP55
TP56
TP57
TP52
TP53
TP58
TP51
TP59
TP60
TP61
TP62
TP63
TP64
TP65
TP66
TP67
TP68
TP69
TP70
TP71
TP72
TP73
TP74
TP75
TP76
TP77
TP78
TP79
TP80
TP81
GPIO10_DMA_DACK0_B
GPIO11_DMA_DACK1_B
AD6
AE10
GPIO12_DMA_DDONE0_B
GPIO13_DMA_DDONE1_B
AA11
AB11
TRIG_OUT_READY_QUIESCE_B
TRIG_IN
GPIO10_DMA_DACK0_B
GPIO11_DMA_DACK1_B
HRESET_B
SRESET_B
GPIO12_DMA_DDONE0_B
HRESET_REQ_B
GPIO13_DMA_DDONE1_B
GPIO14_DMA_DREQ0_B
GPIO15_DMA_DREQ1_B
AB10
AD11
GPIO14_DMA_DREQ0_B
GPIO15_DMA_DREQ1_B
UDE_B
MCP_B
AB14
Y14
UDE_B
MCP_B
IRQ00
IRQ01
IRQ02
IRQ03
IRQ04
IRQ05
IRQ06
IRQ07
IRQ08
IRQ09_DMA_DREQ3_B
IRQ10_DMA_DACK3_B
IRQ11_DMA_DDONE3_B
AG22
AF17
AB23
AF19
AG17
AF16
AA22
Y19
AB22
AE13
AD13
AD14
IRQ00
IRQ01
IRQ02
IRQ03
MPC8536
IRQ04
MISC
IRQ05
IRQ06
7 OF 10
IRQ07
IRQ08
IRQ09_DMA_DREQ3_B
IRQ10_DMA_DACK3_B
IRQ11_DMA_DDONE3_B
IRQ_OUT_B
AC17
IRQ_OUT_B
UART_SOUT0
UART_SIN0
UART_CTS0_B
UART_RTS0_B
AF10
AC12
AE11
AB12
UART_SOUT0
UART_SIN0
UART_CTS0_B
UART_RTS0_B
UART_SOUT1
UART_SIN1
UART_CTS1_B
UART_RTS1_B
AA12
AF12
Y12
AD12
UART_SOUT1
UART_SIN1
UART_CTS1_B
UART_RTS1_B
AG18
AH17
CKSTP_IN_B
CKSTP_OUT_B
AH14
AC13
AF15
SYSCLK
DDRCLK
RTC
CKSTP_IN_B
CKSTP_OUT_B
TP99
TP113
TP111
SYSCLK
DDRCLK
RTC
IIC1_SDA
IIC1_SCL
IIC2_SCL
IIC2_SDA
MSRCID0
MSRCID1
MSRCID2
MSRCID3
MSRCID4
MDVAL
R4
R5
V19
W19
TEMP_ANODE
TEMP_CATHODE
TRIG_OUT_READY_QUIESCE_B
TRIG_IN
AG16
AG19
AG15
AH22
AG21
AH15
AG14
W12
W13
V12
W14
W11
V13
TP84
TP85
HRESET_B
SRESET_B
HRESET_REQ_B
IIC1_SDA
IIC1_SCL
IIC2_SCL
IIC2_SDA
MSRCID0
MSRCID1
MSRCID2
MSRCID3
MSRCID4
MDVAL
AA13
TEST_SEL_B
L2_TSTCLK
L1_TSTCLK
LSSD_MODE_B
AA20
AA21
AC25
L2_TSTCLK
L1_TSTCLK
LSSD_MODE_B
TDI
TDO
TCK
TRST_B
TMS
AH28
AF28
AG28
AH21
AH27
TDI
TDO
TCK
TRST_B
TMS
POWER_OK
POWER_EN
ASLEEP
AC26
AE27
AG20
POWER_OK
POWER_EN
ASLEEP
W15
TP86
TP87
TP88
TP158
TP159
TP100
TP101
TEST_SEL_B
CLK_OUT
TP82
TP83
TP91
TP92
TP93
TP94
TP95
TP96
TP97
TP102
TP103
TP110
TP104
TP105
TP106
TP107
TP108
CLK_OUT
TP114
TP115
TP109
TP98
PROJECT:
8536_FAN_OUT_SCHEMATIC
ENGINEER:
ENGINEER
NAME
A Strategy for Routing the MPC8536E in a Six-Layer PCB, Rev. 0
Freescale Semiconductor
Freescale Confidential Proprietary
31
2
3
4
5
6
7
Fan-Out Schematics
32
1
8
GVDD
A
OVDD
GVDD01
GVDD02
GVDD03
GVDD04
GVDD05
GVDD06
GVDD07
GVDD08
GVDD09
GVDD10
GVDD11
GVDD12
GVDD13
GVDD14
GVDD15
GVDD16
GVDD17
GVDD18
GVDD19
GVDD20
GVDD21
GVDD22
GVDD23
GVDD24
GVDD25
GVDD26
GVDD27
GVDD28
GVDD29
GVDD30
GVDD31
GVDD32
GVDD33
GVDD34
X2VDD01
X2VDD02
X2VDD03
R11
N12
L11
8 OF 10
XVDD01
XVDD02
XVDD03
XVDD04
XVDD05
XVDD06
XVDD07
XVDD08
XVDD09
XVDD10
CORE
SXVDD
SXVDD
PCI
M21
N23
P20
R22
T20
U23
V21
W22
Y20
AA23
1
AVDD_SRDS 7D5
C116
C123
2.2UF
2.2UF
C130
3300PF
R12
1
VDD_PLAT
AVDD_SRDS2 7D5
C117
C124
2.2UF
2.2UF
C131
3300PF
R13
C125
2.2UF
2.2UF
AVDD_DDR 7D5
C132
0.1UF
R2
AVDD_LBIU
C119
C126
2.2UF
2.2UF
0.1UF
R5
TP133
TP134
7D5
C133
10
SENSEVDD
SENSEVSS
PLATFORM
C118
10
AVDD_PCI1
C120
C127
2.2UF
2.2UF
7D5
C134
10
0.1UF
LTVDD
GIGABIT
R6
ETHERNET
VDD_CORE
Freescale Semiconductor
AVDD_DDR
AVDD_SRDS2
AVDD_SRDS
AVDD_LBIU
AVDD_PCI1
AVDD_PLAT
AVDD_CORE
BVDD
LOCAL
BUS
AVDD_PLAT
C121
VDD_PLAT
D
R1
EXPRESS XMTR PWR
SENSEVSS
SENSEVDD
S2VDD01
S2VDD02
S2VDD03
P13
U16
L16
M15
N14
R14
P15
N16
M13
U14
T13
L14
T15
R16
V16
V15
R6
N7
M9
SVDD01
SVDD02
SVDD03
SVDD04
SVDD05
SVDD06
SVDD07
SVDD08
SVDD09
SVDD10
SVDD11
SVDD12
SVDD13
SVDD14
SVDD15
LVDD2
LVDD1
TVDD1
TVDD2
EXPRESS RCVR PWR
C
VDD_CORE01
VDD_CORE02
VDD_CORE03
VDD_CORE04
VDD_CORE05
VDD_CORE06
VDD_CORE07
VDD_CORE08
VDD_CORE09
VDD_CORE10
VDD_CORE11
VDD_CORE12
VDD_CORE13
VDD_CORE14
POWER
AA4
AA7
V4
U7
PCI
M27
N25
P28
R24
R26
T24
T27
U25
W24
W26
Y24
Y27
AA25
AB28
AD27
U1
MPC8536
AVDD_CORE
AVDD_PLAT
AVDD_PCI1
AVDD_LBIU
AVDD_SRDS
AVDD_SRDS2
AVDD_DDR
SXVDD
VDD_CORE
PBGA_28X28_1MM_SKT
AH16
AH18
AH20
C28
W28
T1
AH19
SIGNALS
BVDD01
BVDD02
BVDD03
BVDD04
BVDD05
BVDD06
BVDD07
BVDD08
MISC
L23
J18
J23
J19
F20
F23
H26
J21
B
OVDD01
OVDD02
OVDD03
OVDD04
OVDD05
OVDD06
OVDD07
OVDD08
OVDD09
OVDD10
OVDD11
OVDD12
OVDD13
OVDD14
OVDD15
OVDD16
VDD_PLAT1
VDD_PLAT2
VDD_PLAT3
VDD_PLAT4
VDD_PLAT5
VDD_PLAT6
VDD_PLAT7
VDD_PLAT8
VDD_PLAT9
VDD_PLAT10
Y18
AG2
AD4
AB16
AF6
AC18
AB13
AD10
AE14
AD16
AD25
AF27
AE22
AF11
AF20
AF24
T19
T17
V17
U18
R18
N18
M19
P19
P17
M17
Freescale Confidential Proprietary
A Strategy for Routing the MPC8536E in a Six-Layer PCB, Rev. 0
B1
B11
C7
C9
C14
C17
D4
D6
R3
D15
E2
E8
C24
E18
F5
E14
C21
G3
G7
G9
G11
H5
H12
E22
F15
J10
K3
K12
K14
H14
D20
E11
M1
N5
DDR POWER
C128
0.1UF
2.2UF
2.2UF
C122
C129
2.2UF
2.2UF
R11
7C8
7C8
7C8
7D8
7D8
7D8
7D8
7D5
C135
10
AVDD_CORE 7D5
C136
10
0.1UF
ANALOG FILTERS
PROJECT:
DATE:
8536_FAN_OUT_SCHEMATIC
ENGINEER:
1
2
3
FREESCALE
4
Confidential
5
Proprietary
6
ENGINEER
REV
NAME
7
Tue
DRAWING
Jul
X1
31
12:15:27
2007
PAGE:
7
8
OF 14
Freescale Semiconductor
2
3
4
5
6
7
8
PBGA_28X18_1MM_SKT
ISP1505CBS
M20
M24
N22
P21
R23
T21
U22
V20
W23
Y21
X2GND01
X2GND02
X2GND03
X2GND04
R12
M10
N11
L12
S2GND01
S2GND02
S2GND03
S2GND04
P8
P9
N6
M8
VCC
VCC_1
VCC_2
8A6
8B6
8B6
8B6
8B6
8B6
8B6
8B6
USB1_D0
USB1_D1
USB1_D2
USB1_D3
USB1_D4
USB1_D5
USB1_D6
USB1_D7
2
1
24
22
20
19
18
17
DATA0
DATA1
DATA2
DATA3
DATA4
DATA5
DATA6
DATA7
8B6
8B6
8B6
8B6
USB1_DIR
USB1_STP
USB1_NXT
USB1_CLK
14
15
16
21
12
DIR
STP
NXT
CLOCK
RESET*
10
11
XTAL1
XTAL2
U3
8
VBUS_FAULT
DM
5
DP
6
USB1_PWRFAULT
8A4
8A4
8A4
8A4
8A4
8A4
8A4
8A4
9
13
REG3V3
REG1V8
4
RREF
MPC8536
GROUND
TP168
TP169
8B6
8B6
8B6
8B6
8B6
8B6
8B6
8C6
USB2_D0
USB2_D1
USB2_D2
USB2_D3
USB2_D4
USB2_D5
USB2_D6
USB2_D7
2
1
24
22
20
19
18
17
DATA0
DATA1
DATA2
DATA3
DATA4
DATA5
DATA6
DATA7
8C6
8C6
8C6
8C6
USB2_DIR
USB2_STP
USB2_NXT
USB2_CLK
14
15
16
21
12
DIR
STP
NXT
CLOCK
RESET*
10
11
XTAL1
XTAL2
U4
8
VBUS_FAULT
DM
5
DP
6
TP170
TP171
8C6
8C6
8C6
8C6
8C6
8C6
8C6
8C6
USB3_D0
USB3_D1
USB3_D2
USB3_D3
USB3_D4
USB3_D5
USB3_D6
USB3_D7
2
1
24
22
20
19
18
17
DATA0
DATA1
DATA2
DATA3
DATA4
DATA5
DATA6
DATA7
8C6
8C6
8C6
8C6
USB3_DIR
USB3_STP
USB3_NXT
USB3_CLK
14
15
16
21
12
DIR
STP
NXT
CLOCK
RESET*
10
11
XTAL1
XTAL2
USB2_NXT
USB2_DIR
USB2_STP
USB2_CLK
GPIO08_USB2_PCTL0
GPIO09_USB2_PCTL1
8B6 USB2_PWRFAULT
8D4
8D4
8D4
8D4
8D4
8D4
8D4
8D4
4
RREF
USB2_D0
USB2_D1
USB2_D2
USB2_D3
USB2_D4
USB2_D5
USB2_D6
USB2_D7
8C4
8C4
8C4
8C4
9
13
REG3V3
REG1V8
USB3_D0
USB3_D1
USB3_D2
USB3_D3
USB3_D4
USB3_D5
USB3_D6
USB3_D7
USB3_NXT
USB3_DIR
USB3_STP
USB3_CLK
8D6 USB3_PWRFAULT
8D4
8D4
8D4
8D4
U2
VBUS_FAULT
8
DM
5
DP
6
REG3V3
REG1V8
GND_PAD
VCC
VCC_1
VCC_2
8B4
8B4
8B4
8C4
8C4
8C4
8C4
8C4
8C6
ISP1505CBS
7
3
23
USB1_NXT
USB1_DIR
USB1_STP
USB1_CLK
GPIO06_USB1_PCTL0
GPIO07_USB1_PCTL1
8A6 USB1_PWRFAULT
USB2_PWRFAULT
25
9 OF 10
VCC
VCC_1
VCC_2
USB1_D0
USB1_D1
USB1_D2
USB1_D3
USB1_D4
USB1_D5
USB1_D6
USB1_D7
8B4
8A4
8A4
8B4
ISP1505CBS
7
3
23
8B6
PBGA_28X28_1MM_SKT
GND_PAD
XGND01
XGND02
XGND03
XGND04
XGND05
XGND06
XGND07
XGND08
XGND09
XGND10
7
3
23
25
SGND01
SGND02
SGND03
SGND04
SGND05
SGND06
SGND07
SGND08
SGND09
SGND10
SGND11
SGND12
SGND13
SGND14
SGND15
SGND16
M28
N26
P24
P27
R25
T28
U24
U26
V24
W25
Y28
AA24
AA26
AB24
AB27
AD28
GND_PAD
U1
RREF
U1
AB1
AB2
AC1
AC2
AD2
AE1
AE2
AF1
USB1_D0
USB1_D1
USB1_D2
USB1_D3
USB1_D4
USB1_D5
USB1_D6
USB1_D7
AF2
AH1
AG1
AD1
AC3
AC4
AH2
USB1_NXT
USB1_DIR
USB1_STP
USB1_CLK
GPIO06_USB1_PCTL0
GPIO07_USB1_PCTL1
USB1_PWRFAULT
AD3
AE3
AE4
AF4
AE5
AF5
AC6
AE6
USB2_D0
USB2_D1
USB2_D2
USB2_D3
USB2_D4
USB2_D5
USB2_D6
USB2_D7
AC7
AF7
AD7
AD5
AG9
AC9
AC8
USB2_NXT
USB2_DIR
USB2_STP
USB2_CLK
GPIO08_USB2_PCTL0
GPIO09_USB2_PCTL1
USB2_PWRFAULT
AH3
AG3
AH4
AG4
AG5
AH6
AG6
AH7
USB3_D0
USB3_D1
USB3_D2
USB3_D3
USB3_D4
USB3_D5
USB3_D6
USB3_D7
AG7
AG8
AH8
AH5
AH9
USB3_NXT
USB3_DIR
USB3_STP
USB3_CLK
USB3_PWRFAULT
MPC8536
USB
OF 10
10
8D6
9
13
4
PROJECT:
ENGINEER:
3
FREESCALE
4
Confidential
5
Proprietary
NC01
NC02
NC03
NC04
NC05
NC06
NC07
NC08
NC09
NC10
NC11
NC12
NC13
NC14
NC15
NC16
NC17
NC18
NC19
NC20
NC21
USB3_PWRFAULT
DATE:
8536_FAN_OUT_SCHEMATIC
2
C19
D7
D10
K13
L10
R10
B6
F12
J7
P10
M25
W27
N24
N10
R8
J9
W17
K9
V25
L13
R9
NC01
NC02
NC03
NC04
NC05
NC06
NC07
NC08
NC09
NC10
NC11
NC12
NC13
NC14
NC15
NC16
NC17
NC18
NC19
NC20
NC21
6
ENGINEER
Tue
REV
NAME
7
DRAWING
Jul
X1
31
11:49:05
20
PAGE:
8
8
OF
33
Fan-Out Schematics
GND01
GND02
GND03
GND04
GND05
GND06
GND07
GND08
GND09
GND10
GND11
GND12
GND13
GND14
GND15
GND16
GND17
GND18
GND19
GND20
GND21
GND22
GND23
GND24
GND25
GND26
GND27
GND28
GND29
GND30
GND31
GND32
GND33
GND34
GND35
GND36
GND37
GND38
GND39
GND40
GND41
GND42
GND43
GND44
GND45
GND46
GND47
GND48
GND49
GND50
GND51
GND52
GND53
GND54
GND55
GND56
GND57
GND58
GND59
GND60
GND61
GND62
GND63
GND64
GND65
GND66
GND67
GND68
GND69
GND70
GND71
GND72
GND73
GND74
GND75
GND76
GND77
GND78
GND79
GND80
GND81
GND82
GND83
GND84
GND85
GND86
GND87
GND88
GND89
25
A Strategy for Routing the MPC8536E in a Six-Layer PCB, Rev. 0
Freescale Confidential Proprietary
D5
AE7
F4
D26
D23
C12
C15
E20
D8
B10
AF3
E3
J14
K21
F8
A3
F16
E12
E15
D17
L1
F21
H1
G13
G15
G18
C6
A14
A7
G25
H4
C20
J12
J15
J17
F27
M5
J27
K11
L26
K7
K8
T14
V14
M16
M18
P14
N15
N17
N19
N2
P5
P16
P18
M14
R15
R17
R19
T16
T18
L17
U15
U17
U19
V18
C27
Y13
AE26
AA19
AE21
B28
AC11
AD19
AD23
L15
AD15
AG23
AE9
A27
V7
Y7
AC5
U4
Y4
AE12
AB9
AA14
N13
R13
Fan-Out Schematics
2
3
4
5
6
7
MEMORY CONNECTOR #1
CONN_240_DDR2_VERT_SPECIAL_1OF2
10A2
10B2
10B2
10B2
1B6
1B6
1C6
1C6
DQS0
DQS0n
DQS1
DQS1n
DQS2
DQS2n
DQS3
DQS3n
DQS4
DQS4n
DQS5
DQS5n
DQS6
DQS6n
DQS7
DQS7n
DQS8
DQS8n
MECC_<0..7>
BI
MDM<0..8>
BI
IN
MBA<0..2>
IN
MA<00..15>
10C2
10C2
10C2
0
1
2
3
4
5
6
7
42
43
48
49
161
162
167
168
CB0
CB1
CB2
CB3
CB4
CB5
CB6
CB7
0
1
2
3
4
5
6
7
8
125
134
146
155
202
211
223
232
164
DM0 (DQS9)
DM1 (DQS10)
DM2 (DQS11)
DM3 (DQS12)
DM4 (DQS13)
DM5 (DQS14)
DM6 (DQS15)
DM7 (DQS16)
DM8 (DQS17)
0
1
2
71
190
54
00
01
02
03
04
05
06
07
08
09
10
11
12
13
14
15
188
183
63
182
61
60
180
58
179
177
70
57
176
196
174
173
1D6
1D6
1D6
IN
IN
IN
MWE_B
MRAS_B
MCAS_B
73
192
74
1D6
1D6
IN
IN
MCS0_B
MCS1_B
193
76
1D6
1D6
IN
IN
MODT0
MODT1
195
77
1D6
1D6
IN
IN
MCKE0
MCKE1
52
171
1A2
1A2
1A2
1A2
1A2
1A2
IN
IN
IN
IN
IN
IN
MCK0
MCK0_B
MCK1
MCK1_B
MCK2
MCK2_B
185
186
137
138
220
221
18
10D2 1A7
1D1 10D2
10D2
10D2
10D3
1D6
1
55
MVREF
IN
OUT MAPAR_ERR_B
BI
IN
IN
119
120
239
240
101
238
I2C_SDA
I2C_SCL
19
68
MAPAR_OUT
(ECC0)
(ECC1)
(ECC2)
(ECC3)
(ECC4)
(ECC5)
(ECC6)
(ECC7)
DQ0
DQ1
DQ2
DQ3
DQ4
BA0
DQ5
BA1
DQ6
BA2
DQ7
DQ8
DQ9
A0
DQ10
P1
A1
DQ11
A2
DDR2 DIMM
DQ12
A3
DQ13
A4
DQ14
A5
DQ15
A6
DQ16
A7
DQ17
A8
DQ18
A9
DQ19
A10
(AP)
DQ20
A11
DQ21
A12
DQ22
A13
DQ23
A14
DQ24
A15
DQ25
DQ26
WE
DQ27
RAS
DQ28
CAS
DQ29
DQ30
S0
DQ31
S1
DQ32
DQ33
ODT0
DQ34
ODT1
DQ35
DQ36
CKE0
DQ37
CKE1
DQ38
DQ39
CK_H0
DQ40
NC
CK_L0
DQ41
102
CK_H1
DQ42
CK_L1
DQ43
CK_H2
DQ44
Not Supported
CK_L2
126,
135,
147,
156 DQ45
DQ46
165,
203,
212,
224
RESET
DQ47
233
DQ48
DQ49
DQ50
VREF
RC
DQ51
DQ52
SDA
DQ53
SCL
DQ54
SA0
DQ55
SA1
DQ56
SA2
DQ57
DQ58
VDDSPD
DQ59
DQ60
PWR2_SEL_OPT1
DQ61
Normally
NC on DDR2
PWR1_SEL_OPT1
DQ62
DQ63
7
6
16
15
28
27
37
36
84
83
93
92
105
104
114
113
46
45
3
4
9
10
122
123
128
129
12
13
21
22
131
132
140
141
24
25
30
31
143
144
149
150
33
34
39
40
152
153
158
159
80
81
86
87
199
200
205
206
89
90
95
96
208
209
214
215
98
99
107
108
217
218
226
227
110
111
116
117
229
230
235
236
MDQS0
MDQS0_B
MDQS1
MDQS1_B
MDQS2
MDQS2_B
MDQS3
MDQS3_B
MDQS4
MDQS4_B
MDQS5
MDQS5_B
MDQS6
MDQS6_B
MDQS7
MDQS7_B
MDQS8
MDQS8_B
00
01
02
03
04
05
06
07
08
09
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
1A5
1A5
1A5
1A5
1A5
1A5
1A5
1A5
1A5
1A5
1A5
1A5
1B5
1B5
1B5
1B5
1B5
1B5
10A5
10A5
10A5
10A5
10A5
10A5
10A5
10A5
10A5
10A5
10A5
10A5
10B5
10B5
10B5
10B5
10B5
10B5
CONN_240_DDR2_VERT_SPECIAL_1OF2
GVDD
102
126
135
147
156
165
203
212
224
53
59
64
67
69
172
178
184
187
189
197
233
66
50
MDQ<00..63>
BI
1B2
NC1
NC2
NC3
GVDD
P2
NC4
NC5
NC6
NC7
NC8
NC9
VDD1
VDD2
VDD3
VDD4
VDD5
VDD6
VDD7
VDD8
VDD9
VDD10
VDD11
NC10
GROUND
VDDQ1
2, 5, 8, 11,
14,
17,
20,VDDQ2
23,
26,
29,
32,
35,
38, VDDQ3
VDDQ4
41,
44,
47,
65,
VDDQ5
79,
82,
85,
88,
91,
VDDQ6
94,
97,
100,
103,
106, VDDQ7
109,
112,
115,
118,
121,VDDQ8
124,
127,
130,
133,
136,VDDQ9
VDDQ10
139,
142,
145,
148,
151,
VDDQ11
154,
157,
160,
163,
166,
169,
198,
201,
204,
207,
210,
213,
216,
219,
222,
225,
228,
231,
234,
237
51
56
62
72
75
78
170
175
181
191
194
PWR2_SEL_OPT2
PWR1_SEL_OPT2
10C6
PROJECT:
8536_FAN_OUT_SCHEMATIC
ENGINEER:
2
3
4
5
6
ENGINEER
Tue
REV
NAME
7
DRAWING
A Strategy for Routing the MPC8536E in a Six-Layer PCB, Rev. 0
34
Freescale Confidential Proprietary
Freescale Semiconductor
Fan-Out Schematics
2
3
4
5
6
7
MEMORY CONNECTOR #2
9A2
9A2
1B6
1B6
9B2
9B2
1C6
1C6
DQS0
DQS0n
DQS1
DQS1n
DQS2
DQS2n
DQS3
DQS3n
DQS4
DQS4n
DQS5
DQS5n
DQS6
DQS6n
DQS7
DQS7n
DQS8
DQS8n
MECC_<0..7>
BI
MDM<0..8>
BI
IN
MBA<0..2>
IN
MA<00..15>
9C2
9C2
9C2
0
1
2
3
4
5
6
7
42
43
48
49
161
162
167
168
CB0
CB1
CB2
CB3
CB4
CB5
CB6
CB7
0
1
2
3
4
5
6
7
8
125
134
146
155
202
211
223
232
164
DM0 (DQS9)
DM1 (DQS10)
DM2 (DQS11)
DM3 (DQS12)
DM4 (DQS13)
DM5 (DQS14)
DM6 (DQS15)
DM7 (DQS16)
DM8 (DQS17)
0
1
2
71
190
54
00
01
02
03
04
05
06
07
08
09
10
11
12
13
14
15
188
183
63
182
61
60
180
58
179
177
70
57
176
196
174
173
1D6
1D6
1D6
IN
IN
IN
MWE_B
MRAS_B
MCAS_B
73
192
74
1D6
1D6
IN
IN
MCS2_B
MCS3_B
193
76
1D6
1D6
IN
IN
MODT2
MODT3
195
77
1D6
1D6
IN
IN
MCKE2
MCKE3
52
171
1A2
1A2
1A2
1A2
1A2
1A2
IN
IN
IN
IN
IN
IN
MCK3
MCK3_B
MCK4
MCK4_B
MCK5
MCK5_B
185
186
137
138
220
221
1A7
9D2
IN
OUT
MVREF
MAPAR_ERR_B
9D2
9D2
BI
IN
I2C_SDA
I2C_SCL
18
9D2
1D1
9D2
1D6
IN
1
55
119
120
239
240
101
238
MAPAR_OUT
19
68
(ECC0)
(ECC1)
(ECC2)
(ECC3)
(ECC4)
(ECC5)
(ECC6)
(ECC7)
DQ0
DQ1
DQ2
DQ3
DQ4
BA0
DQ5
BA1
DQ6
BA2
DQ7
DQ8
CONN_240_DDR2_VERT_SPECIAL_1OF2
DQ9
A0
DQ10
P2
A1
DQ11
A2
DDR2 DIMM
DQ12
A3
DQ13
A4
DQ14
A5
DQ15
A6
DQ16
A7
DQ17
A8
DQ18
A9
DQ19
A10
(AP)
DQ20
A11
DQ21
A12
DQ22
A13
DQ23
A14
DQ24
A15
DQ25
DQ26
WE
DQ27
RAS
DQ28
CAS
DQ29
DQ30
S0
DQ31
S1
DQ32
DQ33
ODT0
DQ34
ODT1
DQ35
DQ36
CKE0
DQ37
CKE1
DQ38
DQ39
CK_H0
DQ40
NC
CK_L0
DQ41
102
CK_H1
DQ42
CK_L1
DQ43
CK_H2
DQ44
Not Supported
CK_L2
126,
135,
147,
156 DQ45
DQ46
165,
203,
212,
224 DQ47
RESET
233
DQ48
DQ49
DQ50
VREF
RC
DQ51
DQ52
SDA
DQ53
SCL
DQ54
SA0
DQ55
SA1
DQ56
SA2
DQ57
VDDSPD
DQ58
DQ59
DQ60
PWR2_SEL_OPT1
DQ61
Normally
NC on DDR2
PWR1_SEL_OPT1
DQ62
DQ63
7
6
16
15
28
27
37
36
84
83
93
92
105
104
114
113
46
45
3
4
9
10
122
123
128
129
12
13
21
22
131
132
140
141
24
25
30
31
143
144
149
150
33
34
39
40
152
153
158
159
80
81
86
87
199
200
205
206
89
90
95
96
208
209
214
215
98
99
107
108
217
218
226
227
110
111
116
117
229
230
235
236
MDQS0
MDQS0_B
MDQS1
MDQS1_B
MDQS2
MDQS2_B
MDQS3
MDQS3_B
MDQS4
MDQS4_B
MDQS5
MDQS5_B
MDQS6
MDQS6_B
MDQS7
MDQS7_B
MDQS8
MDQS8_B
00
01
02
03
04
05
06
07
08
09
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
1A5
1A5
1A5
1A5
1A5
1A5
1A5
1A5
1A5
1A5
1A5
1A5
1B5
1B5
1B5
1B5
1B5
1B5
9A5
9A5
9A5
9A5
9A5
9A5
9A5
9A5
9A5
9A5
9A5
9A5
9A5
9B5
9B5
9B5
9B5
9B5
CONN_240_DDR2_VERT_SPECIAL_1OF2
GVDD
102
126
135
147
156
165
203
212
224
53
59
64
67
69
172
178
184
187
189
197
233
NC1
NC3
BI
1B2
GVDD
NC4
NC5
NC6
NC7
NC8
NC9
VDD1
VDD2
VDD3
VDD4
VDD5
VDD6
VDD7
VDD8
VDD9
VDD10
VDD11
NC10
66
50
MDQ<00..63>
P1
NC2
GROUND
VDDQ1
2, 5, 8, 11,
14,
17,
20,VDDQ2
23,
26,
29,
32,
35,
38, VDDQ3
VDDQ4
41,
44,
47,
65,
VDDQ5
79,
82,
85,
88,
91,
VDDQ6
94,
97,
100,
103,
106, VDDQ7
109,
112,
115,
118,
121,VDDQ8
124,
127,
130,
133,
136,VDDQ9
VDDQ10
139,
142,
145,
148,
151,
VDDQ11
154,
157,
160,
163,
166,
169,
198,
201,
204,
207,
210,
213,
216,
219,
222,
225,
228,
231,
234,
237
51
56
62
72
75
78
170
175
181
191
194
PWR2_SEL_OPT2
PWR1_SEL_OPT2
9C6
PROJECT:
DATE
8536_FAN_OUT_SCHEMATIC
ENGINEER:
2
3
4
5
ENGINEER
6
REV
NAME
7
Tue
Jul
31
X1
DRAWING
A Strategy for Routing the MPC8536E in a Six-Layer PCB, Rev. 0
Freescale Semiconductor
Freescale Confidential Proprietary
35
Fan-Out Schematics
2
3
4
PCI
5
6
7
EXPRESS CONNECTOR
J1
pciexpress_conn_x16
A13
A14
REFCLKP
PRSNT1
PRSNT2_1
REFCLKN
PRSNT2_2
A11
B10
PERST
PRSNT2_3
P3.3V_AUX
PRSNT2_4
TDI
B5
B6
SMCLK
TDO
SMDAT
TCK
TMS
B11
B79
B78
B75
B74
B71
B70
B67
B66
B63
B62
B59
B58
B55
B54
B51
B50
IN
IN
SD1_TX7_B
SD1_TX7
B46
IN
IN
SD1_TX6_B
SD1_TX6
B42
2B7
2B7
IN
IN
SD1_TX5_B
SD1_TX5
B38
2B7
2B7
IN
IN
SD1_TX4_B
SD1_TX4
B34
IN
IN
SD1_TX3_B
SD1_TX3
B28
2B7
2B7
IN
IN
SD1_TX2_B
SD1_TX2
B24
2B7
2B7
IN
IN
SD1_TX1_B
SD1_TX1
B20
2B7
2A7
IN
IN
SD1_TX0_B
SD1_TX0
B15
2B7
2B7
2B7
2B7
X4 LANE
2B7
2B7
X4 LANE
B45
WAKE_N
TRST
PETn15
PERn15
PERp15
PETp15
PETn14
PERn14
PETp14
PERp14
PETn13
PERn13
PETp13
PERp13
PETn12
PERn12
PETp12
PERp12
PETn11
PERn11
PETp11
PERp11
PETn10
PERn10
PETp10
PERp10
PERn9
PETn9
PETp9
PERp9
PETn8
PERn8
PERp8
PETp8
+3.3V
PETn7
PERn7
B8 A9 A10
PETp7
PERp7
A1
B17
B31
B48
B81
A6
A7
A5
A8
B9
A81
A80
A77
A76
A73
A72
A69
A68
A65
A64
A61
A60
A57
A56
A53
A52
A48
A47
+12V
B41
PETn6
PERn6
B1 B2 B3 A2 A3
PERp6
PETp6
A44
A43
SD1_RX7_B
SD1_RX7
OUT
OUT
2B2
2B2
SD1_RX6_B
SD1_RX6
OUT
OUT
2B2
2B2
SD1_RX5_B
SD1_RX5
OUT
OUT
2B2
2B2
SD1_RX4_B
SD1_RX4
OUT
OUT
2B2
2B2
SD1_RX3_B
SD1_RX3
OUT
OUT
2B2
2B2
SD1_RX2_B
SD1_RX2
OUT
OUT
2B2
2B2
SD1_RX1_B
SD1_RX1
OUT
OUT
2B2
2B2
SD1_RX0_B
SD1_RX0
OUT
OUT
2B2
2A2
GND
B37
B33
B27
B23
B19
B14
PETn5
PETp5
PETn4
PETp4
PETn3
B4 A4 B7 A12 B13 A15
B16 B18 A18 A20 B21
B22 A23 A24 B25 B26
A27 A28 B29 A31 B32
A34 B35 B36 A37 A38
B39 B40 A41 A42 B43
B44 A45 A46 B47 B49
A49 A51 B52 B53 A54
A55 B56 B57 A58 A59
B60 B61 A62 A63 B64
PETp3
PETn2
PETp2
PETn1
PETp1
PERn5
PERp5
PERn4
PERp4
PERn3
PERp3
B65
A66
A67
B68
B69
A70
A75
A71
B76
B72
B77
B73
A78
A74
A79
B80
A82
B3 B12 B30 A32
A50 B82 A19
PERn2
PERp2
NC
PERn1
A33
PERp1
PETn0
PERn0
PETp0
PERp0
A40
A39
A36
A35
A30
A29
A26
A25
A22
A21
A17
A16
X4 LANE
X4 LANE
PROJECT:
8536_FAN_OUT_SCHEMATIC
ENGINEER:
2
3
4
5
6
ENGINEER
NAME
7
DRAW
A Strategy for Routing the MPC8536E in a Six-Layer PCB, Rev. 0
36
Freescale Confidential Proprietary
Freescale Semiconductor
Freescale Semiconductor
1
2
3
4
5
6
7
8
A
CONNECTOR
PCI
32-BIT
CONNECTOR
PCI
3B6
3C6
3C6
3B6
3C6
BI
BI
BI
BI
BI
B
12B6
12B6
12B3
12B3
3C6
3C6
BI
BI
A34
B37
B35
A36
A38
B39
B40
B42
PCI1_FRAME_B
PCI1_DEVSEL_B
PCI1_IRDY_B
PCI1_TRDY_B
PCI1_STOP_B
PCI1_PERR_B
PCI1_SERR_B
3C6
3C6
IN
OUT
FRAME
TDI
DEVSEL
TDO
IRDY
TCK
TRDY
TMS
TRST
LOCK
PERR
INTA
SERR
INTB
INTC
SDONE
INTD
REQ
C_BE3
REQ64
C_BE2
ACK64
C_BE1
IDSEL
PAR
NC1
B20
A20
B21
A22
B23
A23
B24
A25
B27
A28
B29
A29
B30
A31
B32
A32
A44
B45
A46
B47
A47
B48
A49
B52
B53
A54
B55
A55
B56
A57
B58
A58
AD31
AD30
AD29
AD28
AD27
AD26
AD25
AD24
AD23
AD22
A21
A53
B43
3C6
3C6
PCI1_DEVSEL_B
PCI1_IRDY_B
PCI1_TRDY_B
PCI1_STOP_B
PCI1_PERR_B
BI
BI
PCI1_SERR_B
A40
A41
B49
IN
OUT
A17
B18
PCI1_GNT1_B
PCI1_REQ1_B
A5
B6
A8
B61
A12
A24
A48
B22
B57
AD15
AD13
A39
B36
PCI1_C_BE1_B
PCI1_C_BE0_B
A43
PCI1_PAR
IN
3B6
3B6
3B6
3B6
3B6
12B6
12B6
12B6
12B8
12C6
12B8
12B8
12B8
12C6
A61
B62
A62
B5
NC2
NC4
A13
A30
A56
B28
B12
A35
B3
B34
B13
A37
B15
B38
A18
A42
B17
B46
NC5
NC6
12C8
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
09
08
07
06
05
04
03
02
01
00
A9
A11
A14
A19
B10
B14
NC
A9 A11 A14
B10 B14
145154-1
PRSNT1
145154-1
PRSNT2
FRAME
TDI
DEVSEL
TDO
TCK
IRDY
TRDY
TMS
STOP
TRST
LOCK
PERR
INTA
SERR
INTB
INTC
SDONE
INTD
A19
AD12
AD11
AD10
AD9
AD8
AD7
AD6
AD5
AD4
AD3
AD2
B20
A20
B21
A22
B23
A23
B24
A25
B27
A28
B29
A29
B30
A31
B32
A32
A44
B45
A46
B47
A47
B48
A49
B52
B53
A54
B55
A55
B56
A57
B58
A58
B9
B11
A4
B4
B2
A3
A1
A6
B7
A7
B8
12B3
12B3
12B3
12B3
12B3
12B1
12B1
12B1
12B1
12B1
3B6
3C6
3C6
3B6
3C6
BI
BI
BI
BI
BI
PCI1_FRAME_B
12B3
12B3
12B1
12B1
3C6
3C6
BI
BI
PCI1_PERR_B
A34
B37
B35
A36
A38
B39
B40
B42
PCI1_DEVSEL_B
PCI1_IRDY_B
PCI1_TRDY_B
PCI1_STOP_B
PCI1_SERR_B
A40
A41
B49
3C6
3C6
GNT
REQ
C_BE3
REQ64
C_BE2
ACK64
C_BE1
IDSEL
PAR
NC1
AD31
+3.3V
AD30
A21
A53
B43
AD29
AD28
AD27
AD26
AD25
AD24
AD23
A5
B6
-12V
B1
AD18
AD17
AD16
AD15
AD14
AD13
A8
B61
A61
B62
A39
B36
A62
PCI1_C_BE2_B
PCI1_C_BE1_B
PCI1_C_BE0_B
A43
PCI1_PAR
BI
BI
BI
BI
IN
IN
OUT
3B6
3B6
3B6
3B6
3B6
PCI1_REQ2_B
12B3
12B8
12B8
12B8
12C3
12B8
12C3
12C3
12C3
VCC_3.3
A9
B5
NC2
A11
NC4
GND
A12
A24
A13
A30
B12
A35
B13
A37
A18
A42
A48
B22
B57
A56
B28
B3
B34
B15
B38
B17
B46
NC5
NC6
A14
A19
B10
B14
NC
A9 A11 A14
B10 B14
A19
AD12
AD11
AD10
AD9
AD8
AD7
AD6
AD5
AD4
AD3
AD2
AD1
12D5
12D1
3D4
BI
TDI
DEVSEL
TDO
IRDY
TCK
TRDY
TMS
STOP
TRST
LOCK
PERR
INTA
SERR
INTB
INTC
SDONE
INTD
B9
B11
A4
B4
B2
A3
A1
A6
B7
A7
B8
SBO
M66EN
GNT
A60
B60
REQ64
C_BE2
ACK64
C_BE1
REQ
C_BE3
B20
A20
B21
A22
B23
A23
B24
A25
B27
A28
B29
A29
B30
A31
B32
A32
A44
B45
A46
B47
A47
B48
A49
B52
B53
A54
B55
A55
B56
A57
B58
A58
IDSEL
AD31
PAR
AD30
AD29
AD28
AD27
AD26
AD25
AD24
AD23
AD22
A21
A53
B43
A27
B25
B54
A33
B31
A39
B36
A45
B41
A5
B6
A8
B61
A61
B62
A62
B5
B13
A37
A18
A42
A11
B15
B38
B17
B46
NC3
A12
A24
A13
A30
B12
A35
A48
B22
A56
B28
B3
B34
AD13
NC2
-12V
B1
AD15
PCI1_C_BE0_B
PCI1_PAR
IN
NC4
NC5
NC6
B57
A9 A11 A14
B10 B14
A19
AD12
AD11
AD10
AD9
AD8
AD7
AD6
AD5
AD4
AD3
AD2
AD1
AD0
VIO:
3.3V
or
3.3V
or
5V
5V
VCC_3.3
12D1
3D4
BI
VCC_3.3
PCI1_AD<31..00>
PCI1_AD<31..00>
DATE:
4
5
6
ENGINEER
Tue
REV X1
NAME
7
Jul
DRAWING
31 12:15:30
2007
PAGE:
12
8
OF 14
37
Fan-Out Schematics
ENGINEER:
3
12C6
NC
8536_FAN_OUT_SCHEMATIC
2
12C3
12B6
12C3
12C3
12C6
A14
A19
B10
B14
PROJECT:
1
3B6
12B3
12B6
12B6
12C3
A2
GND
AD14
PCI1_C_BE1_B
+12V
AD19
AD16
A9
3B6
3B6
3B6
3B6
BI
BI
BI
BI
PCI1_C_BE2_B
A43
NC1
+5V
AD20
AD17
PCI1_C_BE3_B
+3.3V
AD21
AD18
B26
B33
B44
A52
AD0
12D3
PCI1_AD<31..00>
PRSNT1
PRSNT2
A17
B18
A26
AD0
5V
145154-1
145154-1
C_BE0
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
09
08
07
06
05
04
03
02
01
00
A45
B41
NC3
VIO:
or
3V:
5V:
FRAME
12C8
A2
AD22
AD19
A33
B31
B26
B33
B44
A52
PCI1_C_BE3_B
PCI1_GNT2_B
+12V
AD21
AD20
A27
B25
B54
+5V
AD1
3.3V
CLK
RST
SBO
M66EN
C_BE0
A26
A45
B41
NC3
B1
GND
AD14
A33
B31
-12V
AD19
AD16
BI
BI
BI
BI
PCI1_C_BE2_B
A60
B60
A2
AD20
AD17
B26
B33
B44
A52
PCI1_C_BE3_B
+12V
AD21
AD18
A27
B25
B54
+5V
A10
A16
A59
BI
12B1
12B1
A34
B37
B35
A36
A38
B39
B40
B42
PCI1_FRAME_B
BI
BI
BI
BI
BI
+3.3V
VIO:
12D5
12D3
3D4
12B6
12B6
3B6
3C6
3C6
3B6
3C6
GNT
A26
D
A6
B7
A7
B8
12B1
12B1
12B1
12B1
12B1
3C6
3C6
C_BE0
C
A4
B4
B2
A3
A1
12B6
12B6
12B6
12B6
12B6
SBO
A60
B60
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
09
08
07
06
05
04
03
02
01
00
B9
B11
M66EN
A17
B18
PCI1_REQ0_B
PRSNT1
PRSNT2
STOP
A40
A41
B49
PCI1_GNT0_B
145154-1
145154-1
3V:
5V:
B19
B59
12B3
12B3
12B3
12B3
12B3
3V:
5V:
A10
A16
A59
12B6
12B6
12B6
12B6
12B6
CLK
RST
CLK
RST
B16
A15
A10
A16
A59
B16
A15
B16
A15
CONNECTOR
J7
PCICONN_3V_32BIT_BLOCK
J6
PCICONN_3V_32BIT_BLOCK
J5
PCICONN_3V_32BIT_BLOCK
32-BIT
B19
B59
32-BIT
B19
B59
Freescale Confidential Proprietary
A Strategy for Routing the MPC8536E in a Six-Layer PCB, Rev. 0
PCI
Fan-Out Schematics
2
3
4
5
6
7
LOCAL BUS LATCHES
4B2
IN
LAD<00..31>
1
1
U507
74ALVCH32973KR_LFBGA96
15
A1
14
B1
13
C1
12
D1
11
E1
10
F1
09
G1
08
H1
1A1
1Q1
1A2
1Q2
1A3
1Q3
1A4
1Q4
1A5
1Q5
1A6
1Q6
1A7
1Q7
1A8
1Q8
1B1
1B2
1B3
1B4
H3
H4
4B6
1B6
1LOE
1B7
LBCTL
IN
1B5
1LE
A4
A3
1DIR
1TOE
see
pwr
1B8
J1
06
K1
05
L1
04
M1
03
N1
02
P1
01
R1
00
T1
pins
2Q2
2A2
GND
2A3
B3
D3
E3
G3
K3
M3
N3
R3
2A5
2A6
2A7
2A8
2Q3
B42Q4
D4
2Q5
E4
G42Q6
K42Q7
M4
2Q8
N4
R4
2B1
2B2
2B3
4B6
IN
2B4
LALE
T3
T4
2LE
2B5
2LOE
2B6
2B7
J4
J3
A2
C2
E2
G2
J2
L2
N2
R2
2DIR
A1
B6
30
B1
C6
29
C1
D6
28
D1
E6
27
E1
F6
26
F1
25
G1
24
H1
G6
H6
2B8
Y1
Y2
D3
Y3
D4
Y4
D5
Y5
D6
Y6
D7
Y7
IN
D8
Y8
1Q3
1A4
1Q4
1A5
1Q5
1A6
1Q6
1A7
1Q7
1A8
1Q8
1B2
C5
1B3
D5
1B4
E5
H3
F5
H4
G5
1LE
1B5
1LOE
1B6
1B7
H5
A4
1DIR
1TOE
see
pwr
J6
1B8
23
J1
L6
22
K1
21
L1
N6
20
M1
pins
P6
19
N1
R6
18
P1
T6
17
R1
16
T1
J5
2A1
2Q2
2A2
GND
2A3
B3
D3
E3
G3
K3
M3
N3
R3
2A4
2A5
2A6
2A7
2A8
2Q3
B42Q4
D4
2Q5
E4
G42Q6
K42Q7
M4
2Q8
N4
R4
2B1
K5
2B2
L5
2B3
M5
2B4
N5
T3
P5
T4
R5
2LE
2B5
2LOE
2B6
2B7
T5
J4
B2
A2
D2
C2
F2
E2
H2
31
G2
K2
30
J2
M2
29
L2
P2
28
N2
T2
27
R2
A6
B6
C6
D6
E6
F6
G6
H6
A5
B5
C5
D5
E5
F5
G5
H5
map for
2Q1
K6
M6
2DIR
2B8
J6
K6
L6
M6
N6
P6
R6
T6
J5
K5
L5
M5
N5
P5
R5
T5
2TOE
D1
Y1
D2
Y2
D3
Y3
D4
Y4
D5
Y5
D6
Y6
D7
Y7
D8
Y8
B2
D2
F2
H2
K2
M2
P2
T2
REV 4
OCT 23 2002
REV 4
OCT 23 2002
4C2
1Q2
1A3
B5
J3
D2
1Q1
1A2
1B1
2TOE
D1
1A1
A5
map for
2A1
2A4
U508
74ALVCH32973KR_LFBGA96
31
A3
2Q1
07
A6
LA<27..31>
PROJECT:
8536_FAN_OUT_SCH
ENGINEER:
2
3
4
5
ENGINEER
NAME
6
A Strategy for Routing the MPC8536E in a Six-Layer PCB, Rev. 0
38
Freescale Confidential Proprietary
Freescale Semiconductor
Fan-Out Schematics
1
2
3
4
GBE PHY 1 OF 3
5
6
GBE PHY 2 OF 3
7
GBE PHY 3 OF 3
U6
vsc8244_3of3_sys_pwr_pbga260
5C3
5C3
IN
BI
EC_MDC
P16
MDC
EC_MDIO
P17
MDIO
P18
MDINT_0
N16
MDINT_1
N17
MDINT_2
N18
L17
VSC8244HG
TDI
J16
TDO
K16
TMS
K18
TCK
K17
TRST
L16
EEDAT
XTAL1
CLK125MAC
R17
CLK125MICRO
M18
REF_REXT
REF_FILT
M17
D14
D15
E4
C9
XTAL2
VSS_1
RESET
VSS_2
SOFT_RESET
VDD12_1
VDD12_2
VDD12_3
C11
C13
VSS_4
C14
VSS_5
D7
VSS_6
D8
VSS_7
F2
VDD12_4
VSS_9
G7
VDD12_5
VSS_10
G8
VSS_11
VDD12_7
VSS_12
G10
N3
VDD12_8
VSS_13
G11
R3
VDD12_9
VSS_14
G12
VSS_15
H7
H4
VDDDIG_1
VSS_16
H8
H15
VDDDIG_2
VSS_17
H9
J15
P4
R4
VDDDIG_3
VSS_18
VDDDIG_4
VSS_19
VDDDIG_5
VSS_20
VDDDIG_6
VSS_21
R15
VDDDIG_8
VSS_23
J9
R9
R11
R12
C8
D4
D5
D6
VDDIO_MAC_2
VDDIO_MAC_3
VDDIO_MAC_4
VDDIO_MAC_5
VDDIO_MAC_6
VDD33_1
VDD33_2
VDD33_3
VDD33_4
VSS_24
J10
VSS_25
J11
VSS_26
J12
VSS_27
K2
VSS_28
K3
VSS_29
K4
VSS_30
K7
VSS_31
K8
VSS_32
K9
VSS_33
K10
VSS_34
K11
VSS_35
K12
VSS_36
L3
VSS_37
L7
VSS_38
L8
L9
NC
D9
VDD33_5
D10
VDD33_6
See
spec.
D11
VDD33_7
VSS_39
D12
VDD33_8
VSS_40
D13
VDD33_9
VSS_41
F15
VDD33_10
VSS_42
L12
VSS_43
M4
VSS_44
N4
VSS_45
N15
VSS_46
P2
VSS_47
P3
VSS_48
P15
VSSIO_4
VSSIO_5
VSSIO_6
VSSIO_7
M15
VSSIO_3
M12
VSSIO_2
VDD_MICRO
M11
VDD_CTL
VSSIO_1
L15
VDD33_13
M9
K15
VDD33_12
M8
R16
VDD33_11
M7
L4
M10
G15
V18
TXD_2_0
TXD_2_2
T10
U18
TXD_1_0
TXD_1_2
U10
T18
TXD_0_0
TXD_0_2
TSEC3_TX_EN
U17
TX_CTL_0
TSEC3_GTX_CLK
V17
5C6
5C6
5C6
5C6
5C6
5C6
OUT
OUT
OUT
OUT
TSEC3_RXD3
TSEC3_RXD2
TSEC3_RXD1
TSEC3_RXD0
V10
5B2
5B2
IN
IN
IN
IN
IN
IN
5C2
5C2
5C2
5C2
L11
5C3
5C3
OUT
OUT
OUT
OUT
OUT
OUT
NC21
NC06
NC22
RXD_1_0
RXD_0_0
RX_CLK_0
RX_CTL_0
NC07
NC08
NC09
NC10
NC11
U14
T14
V13
U13
TSEC1_RX_CLK
TSEC1_RX_DV
NC20
NC05
T8
G1
F1
G2
H1
H2
L10
NC19
NC04
V7
V14
TSEC1_RXD3
TSEC1_RXD2
TSEC1_RXD1
TSEC1_RXD0
NC18
NC03
RXD_3_2
T13
TSEC1_GTX_CLK
NC02
J1
J2
K1
L1
L2
M1
RXD_2_2
U15
TSEC1_TX_EN
NC17
RXD_3_0
V15
TSEC1_TXD3
TSEC1_TXD2
TSEC1_TXD1
TSEC1_TXD0
NC01
TXD_3_1
RXD_1_2
RXD_0_2
RX_CLK_2
RX_CTL_2
M2
N1
N2
P1
R1
R2
NC25
NC26
NC27
NC29
TXD_1_1
TXD_1_3
TXD_0_1
TXD_0_3
V6
TX_CLK_1
NC13
NC14
NC15
NC16
TX_CLK_3
T1
T2
U1
U2
V1
NC28
NC30
NC31
NC32
NC33
RXD_3_1
RXD_3_3
V12
RXD_2_1
RXD_2_3
T4
U12
RXD_1_1
RXD_1_3
U4
T12
RXD_0_1
RXD_0_3
V4
RX_CLK_1
RX_CTL_1
RX_CLK_3
RX_CTL_3
A16
TXVPC_0
TXVPC_2
A8
B16
TXVNC_0
TXVNC_2
B8
A15
TXVPD_0
TXVPD_2
A7
B15
TXVND_0
TXVND_2
B7
J18
LED4_0
LED4_2
C5
J17
LED3_0
LED3_2
C4
H18
LED2_0
LED2_2
C3
H17
LED1_0
LED1_2
B2
H16
LED0_0
LED0_2
A2
A14
TXVPA_1
TXVPA_3
A6
B14
TXVNA_1
TXVNA_3
B6
A13
TXVPB_1
TXVPB_3
A5
B13
TXVNB_1
TXVNB_3
B5
A12
TXVPC_1
TXVPC_3
A4
B12
TXVNC_1
TXVNC_3
B4
A11
TXVPD_1
TXVPD_3
A3
B11
TXVND_1
TXVND_3
B3
G18
LED4_1
LED4_3
A1
G17
LED3_1
LED3_3
D3
G16
LED2_1
LED2_3
E3
F18
LED1_1
LED1_3
F3
F17
LED0_1
LED0_3
G3
F16
CMODE0
TXREF_0
R13
E18
CMODE1
TXREF_1
R10
E17
CMODE2
TXREF_2
R8
E16
CMODE3
TXREF_3
T3
D16
CMODE4
C18
CMODE5
C17
CMODE6
C16
CMODE7
T5
V3
U11
B9
0
2
1
3
U5
V11
T11
A9
TXVNB_2
V5
U6
NC12
B10
TXVPB_2
TXVNB_0
U7
NC23
TX_CTL_3
A10
TXVNA_2
TXVPB_0
B17
T7
T6
TX_CTL_1
TXVPA_2
TXVNA_0
A17
V8
TXD_2_3
TXD_2_1
TXVPA_0
B18
U8
NC24
TXD_3_3
A18
T9
RXD_2_0
D2
D1
E1
E2
E15
5B2
5B2
5B2
5B2
TX_CLK_2
U9
V16
T16
OUT TSEC3_RX_CLK
OUT TSEC3_RX_DV
TX_CLK_0
TX_CTL_2
T15
U16
J7
J8
R7
IN
V9
H12
VSS_22
VDDIO_MAC_1
5B6
TXD_3_2
H11
VDDDIG_7
R6
IN
TXD_3_0
H10
R14
R5
5B6
T17
B1
C1
C2
C6
C7
C15
G9
M3
J4
TSEC3_TXD3
TSEC3_TXD2
TSEC3_TXD1
TSEC3_TXD0
G4
H3
VDD12_6
IN
IN
IN
IN
C12
VSS_3
VSS_8
5B6
5B6
5B6
5B6
C10
F4
J3
VSC8244HG
MDINT_3
L18
M16
vsc8244_1of3_ports_pbga260
VSC8244HG
EECLK
D17
D18
U6
U6
vsc8244_2of3_macs_pbga260
MICRO_REF
R18
V2
U3
PROJECT:
8536_FAN_OUT_SCHEMAT
ENGINEER:
1
2
3
4
5
6
ENGINEER
NAME
7
A Strategy for Routing the MPC8536E in a Six-Layer PCB, Rev. 0
Freescale Semiconductor
Freescale Confidential Proprietary
39
Current Delivery in the BGA Field
9
Current Delivery in the BGA Field
The MPC8536E comes in a 1 mm pitch, 783 BGA package arranged as a 28 × 28 array (with pin A1
missing). The BGA pads and vias usually have the physical parameters listed Table 8.
Table 8. MPC8536E Escape Dimensions
Dimension
Drill diameter
Size
10 mils
Finished hole size (FHS)
7–7.5 mils
Pad
19 mils
Anti-pad
28 mils
Thermal relief
33 mils2
Via keepout
23 mils
Notes
Via drill
After plating
Clearance from via pads to adjacent plane area-fills
As above, but for traces on signal (inner) planes
Keep the following points in mind while reading this section:
•
•
The remainder of this section is based on the padstack dimensions in Table 8. If a different padstack
is used, most or all of the numbers derived probably need to be recalculated.
It is assumed that each BGA connection carries current equally, no matter its proximity to the
power supply and/or processor internal power pads. In reality, the current is nonuniformly
distributed due to internal BGA-to-die substrate connections and other factors. There are no
guaranteeable distributions among the power pins.
All comments in this section about power planes apply equally to the return ground. Multilayer PCBs often
have multiple ground planes, so this restriction is occasionally overlooked; however, the ground return
path requirements are exactly equal to the power source path requirements.
In addition to bypass capacitor placement, the designer must also consider the wholesale delivery of power
to the VDD pins. On most PCBs, the power plane is not actually solid, but is perforated by numerous vias.
This is illustrated in Figure 21, where the wide plane is actually only as wide as its narrowest point.
PSU
Power Plane Area-Fill
W=7 Units
Effective Width =
W=3 * 1U
CPU
Figure 21. Restricted Current Flow
A Strategy for Routing the MPC8536E in a Six-Layer PCB, Rev. 0
40
Freescale Confidential Proprietary
Freescale Semiconductor
Current Delivery in the BGA Field
For many applications, the effect of the vias passing through the power plane on the flow of current is
insignificant. However, as the power reaches the outer periphery of the MPC8536E, it must flow through
the outer array of signal BGA vias. While some BGA pads may not need vias (outer BGA pads may be
able to route out on the top layers); in most cases the number of interfering vias ranges from 8 to 11.
For many layouts, the outer one or two BGA pads do not require vias as these signals are usually “escaped”
on the top layer of the PCB. Delivering power properly to the power pins requires planning the flow of
current around these vias, or more properly, the antivias or antipads that surround the via and cause a hole
on the power plane layer. When coupled with a 1-mm spacing, the cross section of the PCB typically
resembles that shown in Figure 6.
The anti-pad is larger than the spacing between the via barrels, which in effect reduces the width and
capacity of the trace. In effect, the power plane is not a solid plane but a parallel array of traces with one
of the following widths:
• 11.3 mils, when planes must be isolated from both vias
• 19.3 mils, when planes connect to one of the vias
The standard formulae to determine the limits of the copper trace are described in the IPC-2221A standard
and are given by:
0.44
× ( viaPlating × viaDiameter × π )
0.44
× ( viaPlating ¥ viaDiameter × π )
I ( Trace, Outer ) = 0.048 × ( maxTempRise )
I ( Trace, Inner ) = 0.024 × ( maxTempRise )
0.725
Eqn. 1
0.725
Eqn. 2
Using these formulae, and using an 11-mil trace as a standard (rounded down from the actual 11.3-mil max
trace width), for various layout rules the amount of current that can be safely carried, assuming a maximum
temperature rise of 20°C, is shown in Table 9.
Table 9. Current-Carrying Capacity per Standard IPC2221A
Location
Copper Plating
(oz.)
11-mil Trace
(A)
Outer
0.5
0.777
1.0
1.285
1.5
1.730
2.0
2.130
0.5
0.390
1.0
0.582
1.5
0.865
2.0
1.065
Inner
9.1
Via Current Capacity
Unless the power is delivered on the top plane and attaches directly to the BGA pad of the processor (which
as noted is fairly difficult to accomplish), power is delivered from one or more PCB planes to the processor
through vias. Given the padstack parameters in Table 8 and the number of vias allocated, the next step to
A Strategy for Routing the MPC8536E in a Six-Layer PCB, Rev. 0
Freescale Semiconductor
Freescale Confidential Proprietary
41
Current Delivery in the BGA Field
ensure a quality PDS is to evaluate the individual and aggregate via current capacity using the following
formula:
IVIA = 0.048 × ( maxTempRise )
0.44
× ( viaPlating × viaDiameter × π )
0.725
Eqn. 3
Table 10 shows a few via current capacities for given PCB process parameters.
Table 10. Via Capacity
maxTempRise
(°C)
viaPlating
(mil)
viaDiameter
(mil)
IVIA
(A)
Notes
10
1
10
1.609
Standard
10
1
11
1.724
—
10
1
15
2.159
—
10
1.5
10
2.159
—
20
1
10
2.183
—
At 1.609 A/via, we have a maximum current capacity of 22.5 A for VDD_CORE (14 vias * 1.609), and 16
A for VDD_PLAT (10 * 1.609).
9.2
Alternate Plane Current Capacity
Research performed by Johannes Adam of Flomerics as preparatory work for a revision to one of the rules
of the IPC2221 standard (specifically, design rule 2152), found that the formula for outer traces was based
on materials and assumptions no longer prevalent. Additionally, he discovered that the 50 percent derating
factor used for inner traces is wholly arbitrary and should be approximately 5 percent. In particular,
thermal conduction to adjacent traces and power planes was found to be vastly more important than
conduction to free space. Refer to Section 10, “References,” for details on this paper and associated
historical data.
At the time of publication, the IPC2221 has not been updated based on these findings, so the designer can
either follow the published standards and accept overly conservative numbers or incorporate the pending
changes. Freescale cannot recommend one course over the other and advises designers to consult the
original source documentation and decide for themselves. Examining the IEEE paper, “case 5” shows an
outer trace of variable width over a 35 um (1 oz. copper) plane. This correlates nicely with an external
power connection residing over an inner ground plane immediately adjacent to it. Such a plane is desirable
not only for power purposes but for routing differential pairs such as those on the SerDes or DDR
interfaces. Extracting the data for a 0.3 mm trace (~11 mils), and applying a curve fitting process to the
data produces the following formula, which is represented in Figure 22:
2
T ( trace ) = 19.473 + 3.228IMAX + 4.469IMAX + 0.385IMAX
3
Eqn. 4
A Strategy for Routing the MPC8536E in a Six-Layer PCB, Rev. 0
42
Freescale Confidential Proprietary
Freescale Semiconductor
Current Delivery in the BGA Field
90
80
70
Trace Temp, degC
60
50
0.3 mm (ADAMS)
0.3 mm (curve fit)
40
30
20
10
0
0
0.5
1
1.5
2
2.5
3
3.5
Current, A
Figure 22. Extrapolated Current Flow
CAUTION
This curve is valid only for the 0.3 mm trace. The IPC standard will likely
include a more complicated curve equation that accepts both current and
trace width as a parameter.
Note that the Y-axis is the total trace temperature. Because we are concerned with a maximum 20°C rise,
the Y-axis starts at 20 as the ambient temperature is also assumed to be 20°C. The crossover point of 40°C
occurs when I = 1.711 A. Using this new data, Table 9 can be updated as shown in Table 11:
Table 11. Current-Carrying Capacity Extrapolated from Adams
Location
Copper Plating
(oz.)
A/11-mil Trace
(A)
Outer
0.5
1.210
1.0
1.711
1.5
2.420
2.0
3.422
A Strategy for Routing the MPC8536E in a Six-Layer PCB, Rev. 0
Freescale Semiconductor
Freescale Confidential Proprietary
43
Current Delivery in the BGA Field
Table 11. Current-Carrying Capacity Extrapolated from Adams (continued)
Location
Copper Plating
(oz.)
A/11-mil Trace
(A)
Inner
0.5
1.149
1.0
1.625
1.5
2.299
2.0
3.251
The IEEE paper included in the references explains why the classic IPC-275/IPC2221A values for inner
current layers are extremely misleading. IPC-2152 is not published at the time of this application note.
A Strategy for Routing the MPC8536E in a Six-Layer PCB, Rev. 0
44
Freescale Confidential Proprietary
Freescale Semiconductor
References
10 References
Table 12 lists useful resources for further reading.
Table 12. References
Document
Source
IPC Standards:
IPC-D-275
IPC-2221A
IPC-2152
www.ipc.org
New Correlations Between Electrical Current and
Temperature Rise in PCB Traces
Johannes Adam,
Flomerics Ltd.
20th IEEE SEMI-THERM Symposium
0-7803-8363-X/04/$20.00 ©2004 IEEE
www.flomerics.com/flotherm/technical_papers/t341.pdf
Martin Tarr, University of Bolton
www.ami.ac.uk/courses/ami4817_dti/u02/pdf/meah0221.pdf
Decoupling Capacitors, a Designer’s Roadmap to Optimal
Decoupling Networks for Integrated Circuits
(CSC240_MUCCIOLI)
Freescale Semiconductor
http://www.freescale.com/files/ftf_2005/doc/reports_
presentations/CSC240_MUCCIOLI.pdf
Interactive trace-width calculator
http://circuitcalculator.com/wordpress/2006/01/31/pcb-trace-wi
dth-calculator
DC Line Resistance and Current Carrying Capacity
Merix Inc.
http://www.merix.com/technology.php?section=processes&
page=technology/_processes.html
A Strategy for Routing the MPC8536E in a Six-Layer PCB, Rev. 0
Freescale Semiconductor
Freescale Confidential Proprietary
45
Revision History
11 Revision History
Table 13 provides a revision history for this application note.
Table 13. Document Revision History
Rev.
Number
Date
0
10/07
Description
Initial release.
A Strategy for Routing the MPC8536E in a Six-Layer PCB, Rev. 0
46
Freescale Confidential Proprietary
Freescale Semiconductor
Revision History
A Strategy for Routing the MPC8536E in a Six-Layer PCB, Rev. 0
Freescale Semiconductor
Freescale Confidential Proprietary
47
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Document Number: AN3444
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