ADM-PCIE-8V3 User Manual V1.8

ADM-PCIE-8V3
User Manual
Document Revision: 1.9
28th June 2017
ADM-PCIE-8V3 User Manual
© 2017 Copyright Alpha Data Parallel Systems Ltd.
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ADM-PCIE-8V3 User Manual
Table Of Contents
1
Introduction ...................................................................................................................................... 1
1.1
Key Features ................................................................................................................................. 1
1.2
Order Code .................................................................................................................................... 1
2
PCB Information .............................................................................................................................. 2
2.1
Physical Specifications .................................................................................................................. 2
2.2
Chassis Requirements ................................................................................................................... 2
2.2.1
PCI Express ............................................................................................................................... 2
2.2.2
Mechanical Requirements ......................................................................................................... 2
2.2.3
Power Requirements ................................................................................................................. 2
2.3
Thermal Performance .................................................................................................................... 3
2.4
Optional Blower ............................................................................................................................. 3
3
Functional Description .................................................................................................................... 5
3.1
Overview ........................................................................................................................................ 5
3.1.1
Switches .................................................................................................................................... 6
3.1.2
LEDs .......................................................................................................................................... 7
3.2
Clocking ......................................................................................................................................... 8
3.2.1
PCIe Reference Clocks ............................................................................................................. 8
3.2.2
Fabric Clock ............................................................................................................................... 8
3.2.3
Programming Clock (EMCCLK) ................................................................................................. 8
3.2.4
QSFP28 ..................................................................................................................................... 9
3.2.5
FireFly ........................................................................................................................................ 9
3.2.6
DDR4 SDRAM Reference Clocks .............................................................................................. 9
3.3
PCI Express ................................................................................................................................. 11
3.4
DDR4 SDRAM ............................................................................................................................. 11
3.5
QSFP28 ....................................................................................................................................... 12
3.6
FireFly .......................................................................................................................................... 13
3.7
System Monitor ............................................................................................................................ 15
3.7.1
System Monitor Status LEDs ................................................................................................... 15
3.8
SMA Timing Input ........................................................................................................................ 16
3.9
USB Front Panel Interface ........................................................................................................... 17
3.10
Configuration ............................................................................................................................... 17
3.10.1
Configuration From Flash Memory .......................................................................................... 17
3.10.1.1
Custom Flash Write Interface .............................................................................................. 18
3.10.1.2
Building and Programming Configuration Images ............................................................... 18
3.10.2
Configuration via JTAG ............................................................................................................ 18
3.11
GPIO Option ................................................................................................................................ 18
3.11.1
Direct Connect FPGA Signals .................................................................................................. 19
3.11.2
Low Speed Serial IO ................................................................................................................ 19
3.12
User EEPROM ............................................................................................................................. 19
Appendix A Complete Pinout Table .................................................................................................................. 21
List of Tables
Table 1
Table 2
Table 3
Table 4
Table 5
Table 6
Mechanical Dimensions ..................................................................................................................... 2
Available Power By Rail ..................................................................................................................... 2
SW1 Switch Functions ....................................................................................................................... 6
LED Details ........................................................................................................................................ 7
PCIe Reference Clocks ..................................................................................................................... 8
Fabric Clock ....................................................................................................................................... 8
ADM-PCIE-8V3 User Manual
Table 7
Table 8
Table 9
Table 10
Table 11
Table 12
Table 13
Table 14
Table 15
Table 16
EMCCLK ............................................................................................................................................ 9
QSFP28 Reference Clocks ................................................................................................................ 9
QSFP28 Jitter Attenuated Reference Clocks ..................................................................................... 9
FireFly Reference Clocks .................................................................................................................. 9
Memory Reference Clocks .............................................................................................................. 10
QSFP28 Part Numbers .................................................................................................................... 12
FireFly Part Numbers ....................................................................................................................... 14
Voltage, Current, and Temperature Monitors ................................................................................... 15
Status LED Definitions ..................................................................................................................... 16
Complete Pinout Table ..................................................................................................................... 21
Figure 1
Figure 2
Figure 3
Figure 4
Figure 5
Figure 6
Figure 7
Figure 8
Figure 9
Figure 10
Figure 11
Figure 12
Figure 13
ADM-PCIE-8V3 Product Photo .......................................................................................................... 1
Thermal Performance ........................................................................................................................ 3
Optional Blower ................................................................................................................................. 4
ADM-PCIE-8V3 Block Diagram ......................................................................................................... 5
Switches ............................................................................................................................................ 6
LEDs .................................................................................................................................................. 7
Clock Topology .................................................................................................................................. 8
QSFP Locations ............................................................................................................................... 12
FireFly Locations ............................................................................................................................. 13
FireFly Breakout to Front Panel ....................................................................................................... 13
Timing Input Schematic ................................................................................................................... 16
Flash Address Map .......................................................................................................................... 17
GPIO Connector .............................................................................................................................. 19
List of Figures
ADM-PCIE-8V3 User Manual
1 Introduction
The ADM-PCIE-8V3 is a high-performance reconfigurable computing card intended for Data Center applications,
featuring a Xilinx Virtex UltraScale FPGA.
Figure 1 : ADM-PCIE-8V3 Product Photo
1.1 Key Features
Key Features
•
PCIe Gen1/2/3 x1/2/4/8/16 capable (x16 requires bifurcation)
•
Half-length, low-profile x16 PCIe form factor
•
Two banks of DDR4 SDRAM 72 bit wide memory (ECC), 16GB (8GB per bank) default rated at 2400MT/s,
32GB option rated at 1866MT/s.
•
Two QSFP28/zQSFP+ sites capable of data rates up to 28 Gbps per channel (112 Gbps per cage)
•
Two Samtec FireFly sites capable of data rates up to 28 Gbps per channel (112 Gbps per module). Can be
routed to front panel or adjacent card slots.
•
Optional SMA/U.FL timing input
•
Front Panel JTAG Access via USB port
•
FPGA configurable over USB/JTAG and BPI configuration flash
•
XCVU095-2FFVC1517E FPGA
•
Voltage, current, and temperature monitoring
1.2 Order Code
ADM-PCIE-8V3/VU095-2E (m)(q)(f)(g)
See http://www.alpha-data.com/pdfs/adm-pcie-8v3.pdf for complete ordering options.
Introduction
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2 PCB Information
2.1 Physical Specifications
The ADM-PCIE-8V3 complies with PCI Express CEM revision 3.0.
Description
Total Dy
Measure
68.9 mm
Total Dx (Inc. QSFP Cages)
174 mm
Total Dz
17.45 mm
Weight
230 grams
Table 1 : Mechanical Dimensions
2.2 Chassis Requirements
2.2.1 PCI Express
The ADM-PCIE-8V3 is capable of PCIe Gen 1/2/3 with 1/2/4/8/16 lanes, using the Xilinx Integrated Block for PCI
Express.
2.2.2 Mechanical Requirements
A 16-lane physical PCIe slot is required for mechanical compatibility.
Each ADM-PCIE-8V3 is shipped with a full height PCIe card bracket installed by default. A half-height bracket is
shipped along with the product and can be easily changed out with a philips screw driver. If the application
requires a low-profile bracket and the order quantity is high, contact sales@alpha-data.com to get the correct
bracket fitted before shipping.
2.2.3 Power Requirements
The PCIe Specification permits a standard low-profile, half-length PCIe card to dissipate up to 25 W of power,
drawn from the PCIe slot. The ADM-PCIE-8V3 may consume more than 25 W of power for larger user FPGA
designs. Power estimation requires the use of the Xilinx XPE spreadsheet and/or a power estimator tool
available from Alpha Data. Please contact support@alpha-data.com to obtain this tool.
The power available to the rails calculated using XPE are as follows:
Voltage
Source Name
Current Capability
0.95
VCC_INT + VCCINT_IO + VCC_BRAM
36A
1.8
VCCAUX + VCCAUX_IO + VCC_BRAM + VCCO_1.8V
6A
3.3
VCCO_3.3V
6A
1.2
VCCO_1.2V
9A
1.8
MGTVCCAUX
1.0
MGTAVCC
9A
1.2
MGTAVTT
15A
1A
Table 2 : Available Power By Rail
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PCB Information
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ADM-PCIE-8V3 User Manual
2.3 Thermal Performance
The ADM-PCIE-8V3 comes with a heat sink to reduce the heat of the FPGA which is typically the hottest point on
the card. The FPGA die temperature must remain under 100 degrees Celsius or the system monitor will clear the
FPGA design to ensure the card does not overheat. To calculate the FPGA die temperature, take your application
power and multiply by Theta JA from the chart below, and add your systems internal ambient temperature. If you
are using the fan provided with the board, you will find Theta JA is approximately 1.27 degC/W for the board in
still air.
The power dissipation can be estimated by using the Alpha Data power estimator in conjuction with the Xilinx
Power Estimator (XPE) downloadable at http://www.xilinx.com/products/technology/power/xpe.html. Download
the UltraScale tool and set the Device to Virtex UltraScale, VU095, FFVC1516, -2, Extended. Set the ambient
temperature to your system ambient and select User Override for the Effective Theta JA and enter the figure
associated with your system LFM in the blank field. Proceed to enter all applicable design elements and
utilization in the following spreadsheet tabs. Next aquire the 8V3 power estimator from Alpha Data by contacting
support@alpha-data.com. You will then plug in the FPGA power figures along with DDR4 and QSFP/Firefly
usage to get an estimated board level power dissipation.
The graph below shows Theta JA of the board with two 3.5 watt QSFP loopback connectors inserted.
Figure 2 : Thermal Performance
2.4 Optional Blower
Because it is possible for generic PC chassis to not provide sufficient airflow to cool the FPGA, the
ADM-PCIE-8V3 is shipped with an uninstalled blower. The blower is optional and can be easily installed with a
Philips screw driver at the discretion of the user. Ensure the opening is facing the heatsink fins. The blower
hangs off the back of the PCB outside of the PCIe card envelope. After screwing the blower into the heatsink,
plug in the small power connector into the connector in the corner of the board.
PCB Information
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ADM-PCIE-8V3 User Manual
Figure 3 : Optional Blower
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PCB Information
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ADM-PCIE-8V3 User Manual
3 Functional Description
3.1 Overview
The ADM-PCIE-8V3 is a versatile reconfigurable computing platform with a Virtex UltraScale VU095-2E FPGA,
two Gen3x8 PCIe interface, two banks of DDR4 both 72 bits wide (for 64 bits with 8 bits ECC), two QSFP28
cages capable of 8x 28G or 2x 112G Serial IO of any Xilinx supported standard (Ethernet, SRIO, Infiniband,
etc.), two Samtec FireFly connectors also capable of 28G/channel, a U.FL input for a timing synchronization
input, a 12 pin header for general purpose use (clocking, control pins, debug, etc.) and low speed serial
communications, and a robust system monitor.
Auxiliary IO
BPI
Config
(gpio, timing,
serial coms, etc)
System
Monitor
USB
JTAG
QSFP28 Cage
(4x28 Gbps max)
FireFly
(4x28Gbps max)
HRIO HRIO MGT MGT
0
MGT
(4x28 Gbps max)
QSFP28 Cage
FireFly
(4x28Gbps max)
XCVU095-2
FFVC1517E
MGT
HPIO
x72
HPIO
x72
DDR4 Bank 0
DDR4-2400/1866, 8/16GB
DDR4 Bank 1
DDR4-2400/1866, 8/16GB
MGT MGT MGT MGT
(0,4)
(5,7)
(8,11)
(12,15)
MAC ID
EEPROM
x16 PCIe Gen3 Edge
Figure 4 : ADM-PCIE-8V3 Block Diagram
Functional Description
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3.1.1 Switches
The ADM-PCIE-8V3 has a quad DIP switch SW1, located on the rear side of the board. The function of each
switch in SW1 is detailed below:
Figure 5 : Switches
Switch
Factory
Default
Function
OFF State
ON State
SW1-1
OFF
User
Switch
Pin AV27 = '1'
Pin AV27 = '0'
SW1-2
OFF
Flash
Lockdown
Flash block Lockdown enabled
Flash block Lockdown disabled
SW1-3
OFF
Service
Mode
Regular Operation
Firmware update service mode
SW1-4
OFF
PCIe Edge
JTAG
JTAG to FPGA from USB
JTAG to FPGA from PCIe Edge
Table 3 : SW1 Switch Functions
Use IO Standard "LVCMOS18" when constraining the user switch pin.
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Functional Description
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ADM-PCIE-8V3 User Manual
3.1.2 LEDs
There are 6 LEDs on the ADM-PCIE-8V3, 3 of which are general purpose and whose meaning can be defined by
the user. The other four have fixed functions described below:
D2
D4
USER_LED_G1 DONE
D5
STAT_0
D6
STAT_1
D7
D8
USR_LED_R
USR_LED_G0
Figure 6 : LEDs
Comp.
Ref.
Function
ON State
OFF State
D4
DONE
FPGA is configured
FPGA is not configured
D8
USER_LED_G0
User defined '0' pin AT27
User defined '1' pin AT27
D2
USER_LED_G1
User defined '0' pin AU27
User defined '1' pin AU27
D7
USER_LED_R
User defined '0' pin AU23
User defined '1' pin AU23
D5
Status 0
D6
Status 1
See Status LED Definitions
See Status LED Definitions
Table 4 : LED Details
Use IO Standard "LVCMOS18" when driving the user LED pins.
Functional Description
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ADM-PCIE-8V3 User Manual
3.2 Clocking
The ADM-PCIE-8V3 provides reference clocks for the DDR4 SDRAM banks and the I/O interfaces available to
the user. After a clock is programmed to a certain frequency, that frequency will become the default on power-up.
Any clock out of an Si5338 Clock Synthesizer is re-configurable over I2C. This allows the user to configure
almost any arbitrary clock frequencies during application run time. Please see the Alpha Data API functions for
examples of how this is done.
Note: use "set_property BITSTREAM.CONFIG.UNUSEDPIN {Pullnone} [current_design]" to ensure the user
design does not interfere with the I2C interface to the reprogramable clock generator.
Card Edge PCIe Ref Clock (100MHz)
25MHz
30ppm
Source
Si5338
Clock
Synth
PCIe Ref Clock (MGTREFCLK0_226)
NB6L11S
Fanout
QSFP28 161.1328125MHz Factory Default (MGTREFCLK0_128)
QSFP28 161.1328125MHz Factory Default (MGTREFCLK0_129)
NB6L11S
Fanout
FireFly 161.1328125MHz Factory Default (MGTREFCLK0_125)
FireFly 161.1328125MHz Factory Default (MGTREFCLK0_126)
NB6L11S
Fanout
Memory Interface Clock 300Mhz (IO Bank 44)
Memory Interface Clock 300Mhz (IO Bank 94)
FABRIC_CLK 300MHz (IO Bank 94)
Figure 7 : Clock Topology
3.2.1 PCIe Reference Clocks
The 16 MGT lanes connected to the PCIe card edge use MGT tiles 224 through 227 and use the system 100
MHz clock (PCIE_REFCLK).
Signal
Target FPGA Input
I/O Standard
"P" pin
"N" pin
PCIE_REFCLK
MGTREFCLK0_226
HCSL
AA7
AA6
Table 5 : PCIe Reference Clocks
3.2.2 Fabric Clock
The design offers a fabric clock called FABRIC_CLK which is permanently fixed at 300 MHz. This clock is
intended to be used for IDELAY elements in FPGA designs. The fabric clock is connected to a Global Clock (GC)
pin.
Signal
Target FPGA Input
I/O Standard
"P" pin
"N" pin
FABRIC_CLK
IO_L12P_T1U_GC_94
DIFF_HSTL_I_18
AP26
AP27
Table 6 : Fabric Clock
3.2.3 Programming Clock (EMCCLK)
An 100MHz clock is fed into the EMCCLK pin to drive the BPI flash device during configuration of the FPGA.
Page 8
Functional Description
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ADM-PCIE-8V3 User Manual
Signal
Target FPGA Input
I/O Standard
pin
REFCLK100M
IO_L24P_T3U_N10_EMCCLK_65
LVCMOS18
AJ28
Table 7 : EMCCLK
3.2.4 QSFP28
The QSFP28 cages are located in MGT tiles 129 and 128 and use a 161.1328125MHz default reference clock.
Note that this clock frequency can be changed to any arbitrary clock frequency up to 400MHz by re-programing
the Si5338 reprogrammable clock oscillator via system monitor. This can be done using the Alpha Data API or
over USB with the appropriate Alpha Data Software tools.
Signal
Target FPGA Input
I/O Standard
"P" pin
"N" pin
GTY_CLK_0B
MGTREFCLK0_129
LVDS
N33
N34
GTY_CLK_0C
MGTREFCLK0_128
LVDS
U33
U34
Table 8 : QSFP28 Reference Clocks
The QSFP28 cages are also located such that they can be clocked from a Si5328 jitter attenuator clock
multiplier. If jitter attenuation is required please see the reference documentation for the Si5328. https://
www.silabs.com/Support%20Documents/TechnicalDocs/Si5328.pdf
The Si5328 is configured with a 114.285MHz oscilator on XA and XB, SDA is at FPGA pin L29 (1.8V), SCL is at
FPGA pin L30 (1.8V) with external pull-ups included.
The Si5328 input clock comes from FPGA pins M29 and M30, and includes 100 Ohm AC coupled termination on
the 1.8V FPGA bank.
Signal
Target FPGA Input
I/O Standard
SI5328_REFCLK_OUT0
MGTREFCLK1_129
LVDS
L33
L34
SI5328_REFCLK_OUT1
MGTREFCLK1_128
LVDS
"P" pin
R33
"N" pin
R34
Table 9 : QSFP28 Jitter Attenuated Reference Clocks
3.2.5 FireFly
The two FireFly sites are located in MGT tile 125 and 126 and use a 161.1328125MHz default reference clock.
Note that this clock frequency can be changed to any arbitrary clock frequency up to 400MHz by re-programing
the Si5338 reprogrammable clock oscillator via system monitor. This can be done using the Alpha Data API or
over USB with the appropriate Alpha Data Software tools.
Signal
Target FPGA Input
I/O Standard
"P" pin
"N" pin
GTY_CLK_1B
MGTREFCLK0_126
LVDS
AE33
AE34
GTY_CLK_1C
MGTREFCLK0_125
LVDS
AJ33
AJ34
Table 10 : FireFly Reference Clocks
3.2.6 DDR4 SDRAM Reference Clocks
The two banks of DDR4 SDRAM memory each require a separate reference clock, as per Xilinx UltraScale MIG
design guidelines. The reference clocks for these interfaces are detailed below:
Both clocks are 300MHz by default.
Functional Description
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ADM-PCIE-8V3 User Manual
Signal
Target FPGA Input
MEM_CLK_0
IO_L13_T2L_GC_44
LVDS
G31
G32
MEM_CLK_1
IO_L11_T2L_GC_94
DIFF_HSTL_I_18
I/O Standard
"P" pin
AN25
"N" pin
AN26
Table 11 : Memory Reference Clocks
DIFF_TERM_ADV = TRUE is required for LVDS termination
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Functional Description
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ADM-PCIE-8V3 User Manual
3.3 PCI Express
The ADM-PCIE-8V3 is capable of PCIe Gen 1/2/3 with 1/2/4/8/16 lanes (where 16-lanes requires a two
bifurcated 8-lane interfaces). The FPGA drives these lanes directly using the Integrated PCI Express block from
Xilinx. Negotiation of PCIe link speed and number of lanes used is generally automatic and does not require user
intervention.
PCI Express reset (PERST#) connected to the FPGA at both pins AJ31 and AP33.
The other pin assignments for the high speed lanes are provided in the pinout attached to the Complete Pinout
Table
Note:
Different motherboards/backplanes will benefit from different RX equalization schemes within the PCIe IP core
provided by Xilinx. Alpha Data recommends using the following setting if a user experiences link errors or
training issues with their system: within the IP core generator, change the mode to "Advanced" and open the
"GT Settings" tab, change the "form factor driven insertion loss adjustment" from "Add-in Card" to
"Chip-to-Chip" (See Xilinx PG239 for more details).
3.4 DDR4 SDRAM
Two banks of DDR4 SDRAM memory are soldered down to the board. While the factory default is 8GB/per bank,
16GB/bank is also supported through a built variant. Please see Order Code for all order options. The memory
interface is 72-bit wide data (64 data + 8 ECC). Maximum signaling rate is 2400 MT/s for 16GB total and
1688MT/s with 32GB total.
Memory solutions are available from the Xilinx Memory Interface Generator (MIG) tool. An example memory
excersizer project is included in the ADM-PCIE-8V3 SDK. All constraint information is included in Complete
Pinout Table. Alpha Data has also provided a custom csv timing file for use with Xilinx MIG. This can be
downloaded from the ADM-PCIE-8V3 product page.
8Gb components used (standard) are Micron MT40A1G8PM-083E
16Gb components used (build variant) are Micron MT40A2G8PM-093E
Functional Description
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ADM-PCIE-8V3 User Manual
3.5 QSFP28
Two QSFP28 cages are available at the front panel. Both cages are capable of housing either active optical or
passive copper QSFP28 or QSFP compatible components. The communication interface can run at up to
28Gbps per channel. There are eight channels between the two QSFP28 cages (total maximum bandwidth of
224Gbps). These cages are ideally suited for 8x 25G or 2x 100G Ethernet or any other protocol supported by the
Xilinx GTY Transceivers. Please see Xilinx User Guide UG578 for more details on the capabilities of the
transceivers.
Both QSFP28 cages have control signals connected to the FPGA. Their connectivity is detailed in the Complete
Pinout Table at the end of this document. The notation used in the pin assignments is QSFP0 and QSFP1 with
locations clarified in the diagram below.
Use the QSFP*_SEL_1V8_L in conjunction with the OPTICAL_SCL_1V8 and OPTICAL_SDA_1V8 pins as
detailed in Complete Pinout Table to communicate with QSFP28 register space.
Note:
The LP_MODE (Low Power Mode) to each QSFP28 cage is pulled up by default. For many high performance
optical transcievers to operate, this pin must be driven low by the FPGA.
Figure 8 : QSFP Locations
The order options for the ADM-PCIE-8V3 include an option to fit the QSFP28 optical transceivers. The table
below shows the part number for the transceivers fitted with each option.
Order Code
Description
Part Number
Manufacturer
Q10
40G (4x10) QSFP Optical Transceiver
FTL410QE2C
Finisar
Q14
56G (4x14) QSFP Optical Transceiver
FTL414QB2C
Finisar
Q25
100G (4x25) QSFP28 Optical Transceiver
FTLC9551REPM
Finisar
Table 12 : QSFP28 Part Numbers
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Functional Description
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ADM-PCIE-8V3 User Manual
3.6 FireFly
Two FireFly receptacles along the top of the board allow for additional 100G breakouts (with MPO) to the front
panel or for internal chassis ring connections. The FireFly connections have the same capabilities as the
QSFP28 cages. The ADM-PCIE-8V3 only supports optical FireFly modules. More information on FireFly can be
found at https://www.samtec.com/optics/optical-cable/mid-board/firefly
Both FireFly sites have control signals connected to the FPGA. Their connectivity is detailed in the Complete
Pinout Table at the end of this document. The notation used in the pin assignments is FireFly0 and FireFly1 with
locations clarified in the diagram below.
Use the FIREFLY*_SEL_1V8_L in conjunction with the OPTICAL_SCL_1V8 and OPTICAL_SDA_1V8 pins as
detailed in Complete Pinout Table to communicate with QSFP28 register space.
Figure 9 : FireFly Locations
The FireFly modules are broken out to the front panel as shown in the image below. The Samtec FireFly optical
module ties the PCB to the front panel where an industry standard MPO coupler is used for attachment to
external cabling.
Figure 10 : FireFly Breakout to Front Panel
The order options for the ADM-PCIE-8V3 include an option to fit the FireFly optical transceivers. The table below
shows the part number for the transceivers fitted with each option.
Functional Description
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ADM-PCIE-8V3 User Manual
Order Code
Description
Part Number
Manufacturer
F14
56G/40G (4x14/10) FireFly Optical Transceiver
ECUO-B04-14-017-0-3-1-1-01
Samtec
F28
28G/25G (4x28/25) FireFly Optical Transceiver
ECUO-B04-28-017-0-3-1-1-01
Samtec
Table 13 : FireFly Part Numbers
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ADM-PCIE-8V3 User Manual
3.7 System Monitor
The ADM-PCIE-8V3 has the ability to monitor temperature, voltage, and current of the system to check on the
operation of the board. The monitoring is implemented using an Atmel AVR microcontroller.
If the core FPGA temperature exceeds 100 degrees Celsius, the FPGA will be cleared to prevent damage to the
card. This function was implemented on sn172 and newer. Older cards should be protected using the FPGA over
tempeature shutdown constraint.
Control algorithms within the microcontroller automatically check line voltages and on board temperatures and
shares makes the information available to the FPGA over a dedicated serial interface built into the Alpha Data
reference design package (sold separately). The information can also be accessed directly from the
microcontroller over the USB interface on the front panel or via the IPMI interface available at the PCIe card
edge.
Monitors
Index
Purpose/Description
ETC
ETC
Elapsed time counter (seconds)
EC
EC
Event counter (power cycles)
12.0V
ADC00
Board Input Supply
3.3V
ADC01
Board Input Supply
3.3V
ADC02
Board Input Auxilary Power Supply
3.3V
PSU0OK
Internal logic voltage
2.5V
ADC03
Clock and DRAM Voltage Supply
1.8V
PSU0OK
FPGA IO Voltage (VCCO)
1.8V
ADC04
Transceiver Power (AVCC_AUX)
1.2V
ADC05
DDR4 SDRAM and FPGA memory I/O
1.2V
ADC06
Transceiver Power (AVTT)
0.9V
ADC07
Transceiver Power (AVCC)
0.85V
ADC08
FPGA Core Supply (VccINT)
0.6V
ADC09
DDR4 Termination Voltage
12V_I
ADC10
12V input current in amps
3.3V_I
ADC11
3.3V input current in amps
1.8V_MGT_I
ADC12
1.8V MGT supply current in amps
2.5V_DIG_I
ADC13
2.5V supply current in amps
uC_Temp
TMP00
FPGA on-die temperature
Board0_Temp
TMP01
Board temperature near front panel
Board1_Temp
TMP02
Board temperature near back top corner
FPGA_Temp
TMP03
FPGA on-die temperature
Table 14 : Voltage, Current, and Temperature Monitors
3.7.1 System Monitor Status LEDs
LEDs D6 (Red) and D5 (Green) indicate the card health status.
Functional Description
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ADM-PCIE-8V3 User Manual
LEDs
Status
Green
Running and no alarms
Green + Red
Standby (Powered off)
Flashing Green + Flashing Red
(together)
Attention - critical alarm active
Flashing Green + Flashing Red
(alternating)
Service Mode
Flashing Green + Red
Attention - alarm active
Red
Missing application firmware or
invalid firmware
FPGA configuration cleared to
protect board
Flashing Red
Table 15 : Status LED Definitions
3.8 SMA Timing Input
All cards are fitted with a U.FL connector that can be utilized as a timing input. This connector can be accessed
with a U.FL cable internal to the chassis, or cabled to an SMA or similar connector at the frton panel. Contact
sales@alpha-data.com for front panel connector options.
Input is on FPGA pin P30, IOSTANDARD LVCMOS18
The signal is isolated through a optical isolator part number ACPL-M61L with a 739 ohm of series resistance.
Figure 11 : Timing Input Schematic
Page 16
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ADM-PCIE-8V3 User Manual
3.9 USB Front Panel Interface
For convenience the FPGA can be configured directly from the USB connection on the front panel. The
ADM-PCIE-8V3 utilizes the Digilent USB-JTAG converter box which is supported by the Xilinx software tool suite.
Simply connect a micro-USB AB type cable between the ADM-PCIE-8V3 USB port and a host computer with
Vivado installed. Vivado Hardware Manager will automatically recognize the FPGA and allow you to configure the
FPGA and the BPI configuration PROM.
The same USB connector is used to directly access the system monitor system. All voltages, currents,
temperatures, and non-volatile clock configuration settings can be accessed using Alpha Data's avr2util software
at this interface.
Avr2util is downloadable here:
ftp://ftp.alpha-data.com/pub/firmware/utilities/windows/archive/avr2util-win-2.5.0.zip
The USB driver install file is downloadable here:
ftp://ftp.alpha-data.com/pub/firmware/utilities/windows/archive/avr2_usb_inf.zip
Use "avr2util.exe /?" to see all options.
For example "avr2util.exe /usbcom com4 display-sensors" will desiplay all sensor values.
3.10 Configuration
There are two main ways of configuring the FPGA on the ADM-PCIE-8V3:
•
From Flash memory, at power-on, as described in Section 3.10.1
•
Using USB cable connected at the front panel USB port Section 3.10.2
3.10.1 Configuration From Flash Memory
The FPGA can be automatically configured at power-on from a 1 Gbit BPI flash memory device (Micron part
number MT28GU01GAAA1EGC-0SIT). This Flash device is divided into two regions of 64 MiByte each, where
each region is sufficiently large to hold an uncompressed bitstream for a VU095 FPGA.
The ADM-PCIE-8V3 is shipped with a bitstream, corresponding to the "dma_demo" FPGA design from the
ADM-PCIE-8V3 SDK, programmed into region 1 and "reg_access" programmed into region 0. This permits basic
confidence and performance testing to be performed on a board without needing to program anything into the
Flash memory. Alpha Data recommends that region 0 is used as a fallback image; this permits relatively simple
recovery, without requiring direct programming of the FPGA over the front panel USB connection, in the event of
programming a "bad" bitstream into region 1.
Data Region
The flash address map is as detailed below:
Region 0
Failsafe
Start Address (Bytes)
0x000_0000
(64 MiB)
0x400_0000
Region 1
Default
(64 MiB)
Figure 12 : Flash Address Map
At power-on, the FPGA attempts to configure itself automatically in BPI mode from region 1 unless the
configuration header on the bitstream ultilizes multi-boot. Multibook and ICAP can be used to selected between
the two configuration regions to be loaded into the FPGA. See Xilinx UG570 MultiBoot for details.
Functional Description
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The Lockdown function of the Flash device is controlled via switch SW1-2. When SW1-2 is OFF, any blocks in
the Flash whose Lockdown flag is set are write-protected. The factory default for the Lockdown flag of all Flash
blocks is clear, so that any block in the Flash can be written.
3.10.1.1 Custom Flash Write Interface
Alpha Data's reference design bridge allows users to write images to the BPI configuration flash over the PCIE
interface. Other customers may want similar functionality built into their own IP. In order to enable this
functionality, users must reference the FLASH* pins in Complete Pinout Table and utilize the STARTUPE3
primitive to control certain dedicated configuration pins (i.e. D0-D3). Complete details on the STARTUPE3
primitive can be found in Xilinx UG570.
3.10.1.2 Building and Programming Configuration Images
Generate a bitfile with these constraints (see xapp1220):
•
•
•
•
•
•
•
•
set_property BITSTREAM.GENERAL.COMPRESS {TRUE} [ current_design ]
set_property BITSTREAM.CONFIG.EXTMASTERCCLK_EN {DIV-1} [current_design]
set_property BITSTREAM.CONFIG.BPI_SYNC_MODE {TYPE1} [current_design]
set_property BITSTREAM.CONFIG.UNUSEDPIN {Pullnone} [current_design]
set_property BITSTREAM.CONFIG.OVERTEMPSHUTDOWN Enable [current_design]
set_property CONFIG_MODE {BPI16} [current_design]
set_property CFGBVS GND [ current_design ]
set_property CONFIG_VOLTAGE 1.8 [ current_design ]
Generate an MCS file with these properties (write_cfgmem):
•
•
•
•
•
-format MCS
-size 128
-interface BPIx16
-loadbit "up 0x0000000 <directory/to/file/filename.bit>" (failsafe location)
-loadbit "up 0x2000000 <directory/to/file/filename.bit>" (default location)
Program with vivado hardware manager with these settings:
•
•
•
BPI part number: mt28gu01gaax1e-bpi-x16
State of non-config mem I/O pins: Pull-none
RS bits: 25:24
3.10.2 Configuration via JTAG
A micro-USB AB Cable may be attached to the front panel USB port. This permits the FPGA to be reconfigured
using the Xilinx Vivado Hardware Manager via the integrated Digilent JTAG converter box.
3.11 GPIO Option
The ADM-PCIE-8V3 has an optional GPIO feature. This feature is not fit by default and must be specified in the
part number. See Order Code for more details on ordering options.
The GPIO option consists of a versatile shrouded connector from Molex with part number 0878331220 that give
users with custom IO requirements multiple connectivity options. The connector houses two types of signal,
direct connect to FPGA signals and low speed serial communication signals.
Recommended mating plug: Molex 0875681273
Page 18
Functional Description
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ADM-PCIE-8V3 User Manual
Figure 13 : GPIO Connector
3.11.1 Direct Connect FPGA Signals
Four nets are broken out to the GPIO header as two differential pairs. These signal are suitable for any 1.8V
supported signaling standards supported by the Xilinx UltraScale architecture. See Xilinx UG571 for IO options.
LVDS and 1.8 CMOS are popular options.
The direct connect GPIO signals are limited to 1.8V by a quickswitch (74CBTLVD3861BQ) in order to protect the
FPGA from overvoltage on IO pins. This quickswitch allows the signals to travel in either direction with only 4
ohms of series impedance and less than 1ns of propagation delay. The nets are directly connected to the FPGA
after the quickswitch.
Direct connect signal names are labeled GP0_1V8_P/N and GP1_1V8_P/N to show polarity and grouping. The
signal pin allocations can be found in Complete Pinout Table
3.11.2 Low Speed Serial IO
A pin configurable serial buffer transceiver allows for RS232, RS485, and RS422 signal standard support. For
details on configuring the transceiver please reference the IC manufacturer datasheet. Linear Technologies part
number LTC2870. Direct link: http://cds.linear.com/docs/en/datasheet/28701fa.pdf
Signal naming is kept consistent with the Linear Tech datasheet and FPGA pin allocations can be found in the
Complete Pinout Table. Be sure to constrain and drive each control pin for expected behavior.
3.12 User EEPROM
A 2Kb I2C user EEPROM is provided for storing MAC addresses or other user information. The EEPROM is part
number M24C02-RMC6TG.
The address pins A2, A1, and A0 are all strapped to a logical '0'.
Write protect (WP), Serial Clock (SCL), and Serial Data (SDA) pin assignments can be found in Complete Pinout
Table with the names SPARE_WP, SPARE_SCL, and SPARE_SDA respectively.
WP, SDA, and SCL signals all have external pull-up resistors on the card.
Functional Description
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Appendix A: Complete Pinout Table
Pin
Number
Signal Name
Bank Voltage
AU24
AVR_B2U_1V8
1.8
AW26
AVR_HS_B2U_1V8
1.8
AV26
AVR_HS_CLK_1V8
1.8
AV24
AVR_HS_U2B_1V8
1.8
AV25
AVR_MON_CLK_1V8
1.8
AU25
AVR_U2B_1V8
1.8
AB10
CCLK
1.8
F9
DDR4_0_A0
1.2
G9
DDR4_0_A1
1.2
D9
DDR4_0_A10
1.2
H11
DDR4_0_A11
1.2
E8
DDR4_0_A12
1.2
J11
DDR4_0_A13
1.2
C9
DDR4_0_A14
1.2
B11
DDR4_0_A15
1.2
K12
DDR4_0_A16
1.2
H9
DDR4_0_A17
1.2
G11
DDR4_0_A2
1.2
D11
DDR4_0_A3
1.2
E12
DDR4_0_A4
1.2
G10
DDR4_0_A5
1.2
F10
DDR4_0_A6
1.2
J9
DDR4_0_A7
1.2
J8
DDR4_0_A8
1.2
F12
DDR4_0_A9
1.2
C12
DDR4_0_ACT_N
1.2
H7
DDR4_0_ALERT_N
1.2
F8
DDR4_0_BA0
1.2
H8
DDR4_0_BA1
1.2
D10
DDR4_0_BG0
1.2
E11
DDR4_0_BG1
1.2
B10
DDR4_0_C0
1.2
C11
DDR4_0_C1
1.2
Table 16 : Complete Pinout Table (continued on next page)
Complete Pinout Table
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ADM-PCIE-8V3 User Manual
Pin
Number
Signal Name
Bank Voltage
A9
DDR4_0_C2
1.2
G12
DDR4_0_CK_C
1.2
H12
DDR4_0_CK_T
1.2
B9
DDR4_0_CKE
1.2
E10
DDR4_0_CS_N
1.2
N12
DDR4_0_DM0
1.2
P14
DDR4_0_DM1
1.2
G15
DDR4_0_DM2
1.2
D14
DDR4_0_DM3
1.2
E20
DDR4_0_DM4
1.2
B20
DDR4_0_DM5
1.2
H22
DDR4_0_DM6
1.2
N22
DDR4_0_DM7
1.2
J13
DDR4_0_DM8
1.2
L10
DDR4_0_DQ0
1.2
L9
DDR4_0_DQ1
1.2
M15
DDR4_0_DQ10
1.2
M17
DDR4_0_DQ11
1.2
M14
DDR4_0_DQ12
1.2
N18
DDR4_0_DQ13
1.2
N16
DDR4_0_DQ14
1.2
N17
DDR4_0_DQ15
1.2
F15
DDR4_0_DQ16
1.2
E16
DDR4_0_DQ17
1.2
F14
DDR4_0_DQ18
1.2
E17
DDR4_0_DQ19
1.2
N9
DDR4_0_DQ2
1.2
G16
DDR4_0_DQ20
1.2
F17
DDR4_0_DQ21
1.2
E15
DDR4_0_DQ22
1.2
G17
DDR4_0_DQ23
1.2
A17
DDR4_0_DQ24
1.2
C16
DDR4_0_DQ25
1.2
B16
DDR4_0_DQ26
1.2
A14
DDR4_0_DQ27
1.2
Table 16 : Complete Pinout Table (continued on next page)
Page 22
Complete Pinout Table
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ADM-PCIE-8V3 User Manual
Pin
Number
Signal Name
Bank Voltage
B17
DDR4_0_DQ28
1.2
B14
DDR4_0_DQ29
1.2
M9
DDR4_0_DQ3
1.2
D16
DDR4_0_DQ30
1.2
D15
DDR4_0_DQ31
1.2
F18
DDR4_0_DQ32
1.2
F20
DDR4_0_DQ33
1.2
F19
DDR4_0_DQ34
1.2
D21
DDR4_0_DQ35
1.2
E18
DDR4_0_DQ36
1.2
G19
DDR4_0_DQ37
1.2
E21
DDR4_0_DQ38
1.2
G20
DDR4_0_DQ39
1.2
M10
DDR4_0_DQ4
1.2
D18
DDR4_0_DQ40
1.2
B22
DDR4_0_DQ41
1.2
A19
DDR4_0_DQ42
1.2
A18
DDR4_0_DQ43
1.2
C19
DDR4_0_DQ44
1.2
B19
DDR4_0_DQ45
1.2
A22
DDR4_0_DQ46
1.2
C18
DDR4_0_DQ47
1.2
G22
DDR4_0_DQ48
1.2
J20
DDR4_0_DQ49
1.2
K11
DDR4_0_DQ5
1.2
H19
DDR4_0_DQ50
1.2
J19
DDR4_0_DQ51
1.2
H18
DDR4_0_DQ52
1.2
J18
DDR4_0_DQ53
1.2
G21
DDR4_0_DQ54
1.2
K18
DDR4_0_DQ55
1.2
L20
DDR4_0_DQ56
1.2
L18
DDR4_0_DQ57
1.2
N19
DDR4_0_DQ58
1.2
M21
DDR4_0_DQ59
1.2
Table 16 : Complete Pinout Table (continued on next page)
Complete Pinout Table
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Page 23
ADM-PCIE-8V3 User Manual
Pin
Number
Signal Name
Bank Voltage
M11
DDR4_0_DQ6
1.2
M19
DDR4_0_DQ60
1.2
M22
DDR4_0_DQ61
1.2
L19
DDR4_0_DQ62
1.2
M20
DDR4_0_DQ63
1.2
H16
DDR4_0_DQ64
1.2
K15
DDR4_0_DQ65
1.2
J16
DDR4_0_DQ66
1.2
J14
DDR4_0_DQ67
1.2
K13
DDR4_0_DQ68
1.2
L13
DDR4_0_DQ69
1.2
K10
DDR4_0_DQ7
1.2
H14
DDR4_0_DQ70
1.2
J15
DDR4_0_DQ71
1.2
L17
DDR4_0_DQ8
1.2
M16
DDR4_0_DQ9
1.2
L12
DDR4_0_DQS0_C
1.2
M12
DDR4_0_DQS0_T
1.2
L14
DDR4_0_DQS1_C
1.2
L15
DDR4_0_DQS1_T
1.2
E13
DDR4_0_DQS2_C
1.2
F13
DDR4_0_DQS2_T
1.2
A15
DDR4_0_DQS3_C
1.2
B15
DDR4_0_DQS3_T
1.2
E22
DDR4_0_DQS4_C
1.2
F22
DDR4_0_DQS4_T
1.2
B21
DDR4_0_DQS5_C
1.2
C21
DDR4_0_DQS5_T
1.2
K20
DDR4_0_DQS6_C
1.2
K21
DDR4_0_DQS6_T
1.2
K22
DDR4_0_DQS7_C
1.2
L22
DDR4_0_DQS7_T
1.2
K16
DDR4_0_DQS8_C
1.2
K17
DDR4_0_DQS8_T
1.2
A10
DDR4_0_ODT
1.2
Table 16 : Complete Pinout Table (continued on next page)
Page 24
Complete Pinout Table
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ADM-PCIE-8V3 User Manual
Pin
Number
Signal Name
Bank Voltage
G7
DDR4_0_PAR
1.2
F7
DDR4_0_RESET_N
1.2
J10
DDR4_0_TEN
1.2
AN9
DDR4_1_A0
1.2
AM9
DDR4_1_A1
1.2
AR8
DDR4_1_A10
1.2
AL10
DDR4_1_A11
1.2
AP8
DDR4_1_A12
1.2
AK11
DDR4_1_A13
1.2
AP9
DDR4_1_A14
1.2
AV10
DDR4_1_A15
1.2
AT11
DDR4_1_A16
1.2
AL8
DDR4_1_A17
1.2
AP11
DDR4_1_A2
1.2
AU9
DDR4_1_A3
1.2
AT10
DDR4_1_A4
1.2
AL12
DDR4_1_A5
1.2
AM12
DDR4_1_A6
1.2
AM10
DDR4_1_A7
1.2
AL11
DDR4_1_A8
1.2
AP7
DDR4_1_A9
1.2
AV9
DDR4_1_ACT_N
1.2
AR10
DDR4_1_ALERT_N
1.2
AN11
DDR4_1_BA0
1.2
AR9
DDR4_1_BA1
1.2
AP12
DDR4_1_BG0
1.2
AN10
DDR4_1_BG1
1.2
AW13
DDR4_1_C0
1.2
AU10
DDR4_1_C1
1.2
AW11
DDR4_1_C2
1.2
AN7
DDR4_1_CK_C
1.2
AM7
DDR4_1_CK_T
1.2
AU12
DDR4_1_CKE
1.2
AT12
DDR4_1_CS_N
1.2
AG12
DDR4_1_DM0
1.2
Table 16 : Complete Pinout Table (continued on next page)
Complete Pinout Table
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Page 25
ADM-PCIE-8V3 User Manual
Pin
Number
Signal Name
Bank Voltage
AK15
DDR4_1_DM1
1.2
AP16
DDR4_1_DM2
1.2
AV16
DDR4_1_DM3
1.2
AP21
DDR4_1_DM4
1.2
AU20
DDR4_1_DM5
1.2
AG19
DDR4_1_DM6
1.2
AL18
DDR4_1_DM7
1.2
AG14
DDR4_1_DM8
1.2
AK9
DDR4_1_DQ0
1.2
AK10
DDR4_1_DQ1
1.2
AL13
DDR4_1_DQ10
1.2
AM14
DDR4_1_DQ11
1.2
AL15
DDR4_1_DQ12
1.2
AM17
DDR4_1_DQ13
1.2
AL17
DDR4_1_DQ14
1.2
AM13
DDR4_1_DQ15
1.2
AR15
DDR4_1_DQ16
1.2
AP14
DDR4_1_DQ17
1.2
AT15
DDR4_1_DQ18
1.2
AR14
DDR4_1_DQ19
1.2
AH10
DDR4_1_DQ2
1.2
AP17
DDR4_1_DQ20
1.2
AN16
DDR4_1_DQ21
1.2
AN17
DDR4_1_DQ22
1.2
AN15
DDR4_1_DQ23
1.2
AU15
DDR4_1_DQ24
1.2
AT17
DDR4_1_DQ25
1.2
AV15
DDR4_1_DQ26
1.2
AT16
DDR4_1_DQ27
1.2
AV14
DDR4_1_DQ28
1.2
AW17
DDR4_1_DQ29
1.2
AJ11
DDR4_1_DQ3
1.2
AW14
DDR4_1_DQ30
1.2
AW18
DDR4_1_DQ31
1.2
AP19
DDR4_1_DQ32
1.2
Table 16 : Complete Pinout Table (continued on next page)
Page 26
Complete Pinout Table
ad-ug-1308_v1_9.pdf
ADM-PCIE-8V3 User Manual
Pin
Number
Signal Name
Bank Voltage
AT20
DDR4_1_DQ33
1.2
AN21
DDR4_1_DQ34
1.2
AR19
DDR4_1_DQ35
1.2
AN20
DDR4_1_DQ36
1.2
AR18
DDR4_1_DQ37
1.2
AR20
DDR4_1_DQ38
1.2
AP18
DDR4_1_DQ39
1.2
AJ9
DDR4_1_DQ4
1.2
AW19
DDR4_1_DQ40
1.2
AU22
DDR4_1_DQ41
1.2
AV19
DDR4_1_DQ42
1.2
AW22
DDR4_1_DQ43
1.2
AU18
DDR4_1_DQ44
1.2
AT22
DDR4_1_DQ45
1.2
AW21
DDR4_1_DQ46
1.2
AU19
DDR4_1_DQ47
1.2
AH19
DDR4_1_DQ48
1.2
AJ22
DDR4_1_DQ49
1.2
AH12
DDR4_1_DQ5
1.2
AF21
DDR4_1_DQ50
1.2
AH22
DDR4_1_DQ51
1.2
AF20
DDR4_1_DQ52
1.2
AJ19
DDR4_1_DQ53
1.2
AH21
DDR4_1_DQ54
1.2
AJ21
DDR4_1_DQ55
1.2
AM19
DDR4_1_DQ56
1.2
AK20
DDR4_1_DQ57
1.2
AM22
DDR4_1_DQ58
1.2
AL22
DDR4_1_DQ59
1.2
AG10
DDR4_1_DQ6
1.2
AM20
DDR4_1_DQ60
1.2
AK19
DDR4_1_DQ61
1.2
AN19
DDR4_1_DQ62
1.2
AL20
DDR4_1_DQ63
1.2
AF15
DDR4_1_DQ64
1.2
Table 16 : Complete Pinout Table (continued on next page)
Complete Pinout Table
ad-ug-1308_v1_9.pdf
Page 27
ADM-PCIE-8V3 User Manual
Pin
Number
Signal Name
Bank Voltage
AJ17
DDR4_1_DQ65
1.2
AH17
DDR4_1_DQ66
1.2
AJ14
DDR4_1_DQ67
1.2
AG15
DDR4_1_DQ68
1.2
AJ13
DDR4_1_DQ69
1.2
AJ12
DDR4_1_DQ7
1.2
AG17
DDR4_1_DQ70
1.2
AJ16
DDR4_1_DQ71
1.2
AM15
DDR4_1_DQ8
1.2
AN14
DDR4_1_DQ9
1.2
AH9
DDR4_1_DQS0_C
1.2
AG9
DDR4_1_DQS0_T
1.2
AL16
DDR4_1_DQS1_C
1.2
AK16
DDR4_1_DQS1_T
1.2
AT13
DDR4_1_DQS2_C
1.2
AR13
DDR4_1_DQS2_T
1.2
AV17
DDR4_1_DQS3_C
1.2
AU17
DDR4_1_DQS3_T
1.2
AP22
DDR4_1_DQS4_C
1.2
AN22
DDR4_1_DQS4_T
1.2
AV21
DDR4_1_DQS5_C
1.2
AV22
DDR4_1_DQS5_T
1.2
AH20
DDR4_1_DQS6_C
1.2
AG20
DDR4_1_DQS6_T
1.2
AL21
DDR4_1_DQS7_C
1.2
AK21
DDR4_1_DQS7_T
1.2
AH15
DDR4_1_DQS8_C
1.2
AH16
DDR4_1_DQS8_T
1.2
AR11
DDR4_1_ODT
1.2
AM8
DDR4_1_PAR
1.2
AN12
DDR4_1_RESET_N
1.2
AV11
DDR4_1_TEN
1.2
U9
DONE_1V8
1.8
L28
DXEN
1.8
J29
DY
1.8
Table 16 : Complete Pinout Table (continued on next page)
Page 28
Complete Pinout Table
ad-ug-1308_v1_9.pdf
ADM-PCIE-8V3 User Manual
Pin
Number
Signal Name
Bank Voltage
H32
DZ
1.8
AJ28
EMCCLK_B
1.8
J28
EN_485/EN_232_L
1.8
AP27
FABRIC_CLK_N
1.8(Do Not Use DIFFTERM)
AP26
FABRIC_CLK_P
1.8(Do Not Use DIFFTERM)
LB
1.8
N29
N28
FEN
B30
FIREFLY0_MODPRS_L
1.8
AL39
FIREFLY0_RX0_N
MGT
1.8
AL38
FIREFLY0_RX0_P
MGT
AJ39
FIREFLY0_RX1_N
MGT
AJ38
FIREFLY0_RX1_P
MGT
AG39
FIREFLY0_RX2_N
MGT
AG38
FIREFLY0_RX2_P
MGT
AE39
FIREFLY0_RX3_N
MGT
AE38
FIREFLY0_RX3_P
MGT
D28
FIREFLY0_SEL_1V8_L
1.8
AM36
FIREFLY0_TX0_N
MGT
AM35
FIREFLY0_TX0_P
MGT
AK36
FIREFLY0_TX1_N
MGT
AK35
FIREFLY0_TX1_P
MGT
AH36
FIREFLY0_TX2_N
MGT
AH35
FIREFLY0_TX2_P
MGT
AF36
FIREFLY0_TX3_N
MGT
AF35
FIREFLY0_TX3_P
MGT
A30
FIREFLY1_MODPRS_L
1.8
AV37
FIREFLY1_RX0_N
MGT
AV36
FIREFLY1_RX0_P
MGT
AU39
FIREFLY1_RX1_N
MGT
AU38
FIREFLY1_RX1_P
MGT
AR39
FIREFLY1_RX2_N
MGT
AR38
FIREFLY1_RX2_P
MGT
AN39
FIREFLY1_RX3_N
MGT
AN38
FIREFLY1_RX3_P
MGT
C28
FIREFLY1_SEL_1V8_L
1.8
Table 16 : Complete Pinout Table (continued on next page)
Complete Pinout Table
ad-ug-1308_v1_9.pdf
Page 29
ADM-PCIE-8V3 User Manual
Pin
Number
Signal Name
Bank Voltage
AW34
FIREFLY1_TX0_N
MGT
AW33
FIREFLY1_TX0_P
MGT
AU34
FIREFLY1_TX1_N
MGT
AU33
FIREFLY1_TX1_P
MGT
AT36
FIREFLY1_TX2_N
MGT
AT35
FIREFLY1_TX2_P
MGT
AP36
FIREFLY1_TX3_N
MGT
AP35
FIREFLY1_TX3_P
MGT
AK29
FLASH_A0
1.8
AK30
FLASH_A1
1.8
AN30
FLASH_A10
1.8
AN31
FLASH_A11
1.8
AN29
FLASH_A12
1.8
AP29
FLASH_A13
1.8
AN32
FLASH_A14
1.8
AN33
FLASH_A15
1.8
AR29
FLASH_A16
1.8
AR30
FLASH_A17
1.8
AP28
FLASH_A18
1.8
AR28
FLASH_A19
1.8
AK28
FLASH_A2
1.8
AR31
FLASH_A20
1.8
AT31
FLASH_A21
1.8
AV31
FLASH_A22
1.8
AW31
FLASH_A23
1.8
AW28
FLASH_A24
1.8
AW29
FLASH_A25
1.8
AL28
FLASH_A3
1.8
AL30
FLASH_A4
1.8
AM30
FLASH_A5
1.8
AL32
FLASH_A6
1.8
AM32
FLASH_A7
1.8
AP31
FLASH_A8
1.8
AP32
FLASH_A9
1.8
AM33
FLASH_ADV_L
1.8
Table 16 : Complete Pinout Table (continued on next page)
Page 30
Complete Pinout Table
ad-ug-1308_v1_9.pdf
ADM-PCIE-8V3 User Manual
Pin
Number
Signal Name
Bank Voltage
AE8
FLASH_CE_L
1.8
AB8
FLASH_DQ0
1.8
AD8
FLASH_DQ1
1.8
AG27
FLASH_DQ10
1.8
AH27
FLASH_DQ11
1.8
AK31
FLASH_DQ12
1.8
AL31
FLASH_DQ13
1.8
AM28
FLASH_DQ14
1.8
AM29
FLASH_DQ15
1.8
Y8
FLASH_DQ2
1.8
AC8
FLASH_DQ3
1.8
AF30
FLASH_DQ4
1.8
AG30
FLASH_DQ5
1.8
AF28
FLASH_DQ6
1.8
AG28
FLASH_DQ7
1.8
AH30
FLASH_DQ8
1.8
AH31
FLASH_DQ9
1.8
AV29
FLASH_OE_L
1.8
AW27
FLASH_WAIT
1.8
AV30
FLASH_WE_L
1.8
AR26
FPGA_CPLD_SPARE
1.8
AW23
FPGA_FLASH_RST_L
1.8
F30
GP0_1V8_N
1.8
G30
GP0_1V8_P
1.8
E31
GP1_1V8_N
1.8
E30
GP1_1V8_P
1.8
N34
GTY_CLK_0B_PIN_N
MGT_REFCLK
N33
GTY_CLK_0B_PIN_P
MGT_REFCLK
U34
GTY_CLK_0C_PIN_N
MGT_REFCLK
U33
GTY_CLK_0C_PIN_P
MGT_REFCLK
AE34
GTY_CLK_1B_PIN_N
MGT_REFCLK
AE33
GTY_CLK_1B_PIN_P
MGT_REFCLK
AJ34
GTY_CLK_1C_PIN_N
MGT_REFCLK
AJ33
GTY_CLK_1C_PIN_P
MGT_REFCLK
M27
H/F
1.8
Table 16 : Complete Pinout Table (continued on next page)
Complete Pinout Table
ad-ug-1308_v1_9.pdf
Page 31
ADM-PCIE-8V3 User Manual
Pin
Number
Signal Name
Bank Voltage
T10
INIT_B_1V8
1.8
G32
MEM_CLK_0_N
1.8(Requires DIFFTERM)
G31
MEM_CLK_0_P
1.8(Requires DIFFTERM)
MEM_CLK_1_N
1.8(Do Not Use DIFFTERM)
AN25
MEM_CLK_1_P
1.8(Do Not Use DIFFTERM)
AG29
AN26
ONBRD_CLK_1V8
1.8
AH29
ONBRD_DATA_1V8
1.8
C29
OPTICAL_INT_1V8_L
1.8
B29
OPTICAL_RESET_1V8_L
1.8
A28
OPTICAL_SCL_1V8
1.8
A29
OPTICAL_SDA_1V8
1.8
AA6
PCIE_REFCLK_PIN_N
MGT_REFCLK
AA7
PCIE_REFCLK_PIN_P
MGT_REFCLK
J1
PCIE_RX0_N
MGT
J2
PCIE_RX0_P
MGT
L1
PCIE_RX1_N
MGT
L2
PCIE_RX1_P
MGT
AJ1
PCIE_RX10_N
MGT
AJ2
PCIE_RX10_P
MGT
AL1
PCIE_RX11_N
MGT
AL2
PCIE_RX11_P
MGT
AN1
PCIE_RX12_N
MGT
AN2
PCIE_RX12_P
MGT
AR1
PCIE_RX13_N
MGT
AR2
PCIE_RX13_P
MGT
AU1
PCIE_RX14_N
MGT
AU2
PCIE_RX14_P
MGT
AV3
PCIE_RX15_N
MGT
AV4
PCIE_RX15_P
MGT
N1
PCIE_RX2_N
MGT
N2
PCIE_RX2_P
MGT
R1
PCIE_RX3_N
MGT
R2
PCIE_RX3_P
MGT
U1
PCIE_RX4_N
MGT
U2
PCIE_RX4_P
MGT
Table 16 : Complete Pinout Table (continued on next page)
Page 32
Complete Pinout Table
ad-ug-1308_v1_9.pdf
ADM-PCIE-8V3 User Manual
Pin
Number
Signal Name
Bank Voltage
W1
PCIE_RX5_N
MGT
W2
PCIE_RX5_P
MGT
AA1
PCIE_RX6_N
MGT
AA2
PCIE_RX6_P
MGT
AC1
PCIE_RX7_N
MGT
AC2
PCIE_RX7_P
MGT
AE1
PCIE_RX8_N
MGT
AE2
PCIE_RX8_P
MGT
AG1
PCIE_RX9_N
MGT
AG2
PCIE_RX9_P
MGT
H4
PCIE_TX0_PIN_N
MGT
H5
PCIE_TX0_PIN_P
MGT
K4
PCIE_TX1_PIN_N
MGT
K5
PCIE_TX1_PIN_P
MGT
AK4
PCIE_TX10_PIN_N
MGT
AK5
PCIE_TX10_PIN_P
MGT
AM4
PCIE_TX11_PIN_N
MGT
AM5
PCIE_TX11_PIN_P
MGT
AP4
PCIE_TX12_PIN_N
MGT
AP5
PCIE_TX12_PIN_P
MGT
AT4
PCIE_TX13_PIN_N
MGT
AT5
PCIE_TX13_PIN_P
MGT
AU6
PCIE_TX14_PIN_N
MGT
AU7
PCIE_TX14_PIN_P
MGT
AW6
PCIE_TX15_PIN_N
MGT
AW7
PCIE_TX15_PIN_P
MGT
M4
PCIE_TX2_PIN_N
MGT
M5
PCIE_TX2_PIN_P
MGT
P4
PCIE_TX3_PIN_N
MGT
P5
PCIE_TX3_PIN_P
MGT
T4
PCIE_TX4_PIN_N
MGT
T5
PCIE_TX4_PIN_P
MGT
V4
PCIE_TX5_PIN_N
MGT
V5
PCIE_TX5_PIN_P
MGT
AB4
PCIE_TX6_PIN_N
MGT
Table 16 : Complete Pinout Table (continued on next page)
Complete Pinout Table
ad-ug-1308_v1_9.pdf
Page 33
ADM-PCIE-8V3 User Manual
Pin
Number
Signal Name
Bank Voltage
AB5
PCIE_TX6_PIN_P
MGT
AD4
PCIE_TX7_PIN_N
MGT
AD5
PCIE_TX7_PIN_P
MGT
AF4
PCIE_TX8_PIN_N
MGT
AF5
PCIE_TX8_PIN_P
MGT
AH4
PCIE_TX9_PIN_N
MGT
AH5
PCIE_TX9_PIN_P
MGT
AJ31
PERST_1V8_0_L
1.8
AP33
PERST_1V8_1_L
1.8
J30
POWER9_SCL_1V8
1.8
J31
POWER9_SDA_1V8
1.8
P30
PPS_BUF_1V8
1.8
V10
PROGRAM_B_1V8
1.8
U8
PUDC_B
1.8
E28
QSFP0_LP_MODE_1V8
F29
QSFP0_MODPRS_L
1.8
G39
QSFP0_RX0_N
MGT
G38
QSFP0_RX0_P
MGT
E39
QSFP0_RX1_N
MGT
E38
QSFP0_RX1_P
MGT
C39
QSFP0_RX2_N
MGT
C38
QSFP0_RX2_P
MGT
B37
QSFP0_RX3_N
MGT
B36
QSFP0_RX3_P
MGT
D31
QSFP0_SEL_1V8_L
1.8
F36
QSFP0_TX0_N
MGT
1.8
F35
QSFP0_TX0_P
MGT
D36
QSFP0_TX1_N
MGT
D35
QSFP0_TX1_P
MGT
C34
QSFP0_TX2_N
MGT
C33
QSFP0_TX2_P
MGT
A34
QSFP0_TX3_N
MGT
A33
QSFP0_TX3_P
MGT
G29
QSFP1_LP_MODE_1V8
1.8
F33
QSFP1_MODPRS_L
1.8
Table 16 : Complete Pinout Table (continued on next page)
Page 34
Complete Pinout Table
ad-ug-1308_v1_9.pdf
ADM-PCIE-8V3 User Manual
Pin
Number
Signal Name
Bank Voltage
R39
QSFP1_RX0_N
MGT
R38
QSFP1_RX0_P
MGT
N39
QSFP1_RX1_N
MGT
N38
QSFP1_RX1_P
MGT
L39
QSFP1_RX2_N
MGT
L38
QSFP1_RX2_P
MGT
J39
QSFP1_RX3_N
MGT
J38
QSFP1_RX3_P
MGT
D30
QSFP1_SEL_1V8_L
1.8
P36
QSFP1_TX0_N
MGT
P35
QSFP1_TX0_P
MGT
M36
QSFP1_TX1_N
MGT
M35
QSFP1_TX1_P
MGT
K36
QSFP1_TX2_N
MGT
K35
QSFP1_TX2_P
MGT
H36
QSFP1_TX3_N
MGT
H35
QSFP1_TX3_P
MGT
H33
RA
1.8
L27
RB
1.8
H28
RXEN_L
1.8
L30
SI5328_1V8_SCL
L29
SI5328_1V8_SDA
1.8
M30
SI5328_REFCLK_IN_N
1.8 (Requires DIFFTERM)
M29
SI5328_REFCLK_IN_P
1.8(Requires DIFFTERM)
L34
SI5328_REFCLK_OUT0_PIN_N
MGT_REFCLK
L33
SI5328_REFCLK_OUT0_PIN_P
MGT_REFCLK
R34
SI5328_REFCLK_OUT1_PIN_N
MGT_REFCLK
R33
SI5328_REFCLK_OUT1_PIN_P
MGT_REFCLK
AT25
SPARE_SCL
1.8
AT26
SPARE_SDA
1.8
AP23
SPARE_WP
1.8
AW24
SRVC_MD_L_1V8
1.8
Y10
TCK
1.8
AC9
TDI
1.8
Y9
TDO
1.8
1.8
Table 16 : Complete Pinout Table (continued on next page)
Complete Pinout Table
ad-ug-1308_v1_9.pdf
Page 35
ADM-PCIE-8V3 User Manual
Pin
Number
Signal Name
Bank Voltage
H29
TE485
1.8
AD10
TMS
1.8
AT27
USER_LED_G0
1.8
AU27
USER_LED_G1
1.8
AU23
USER_LED_R
1.8
AV27
USR_SW
1.8
Table 16 : Complete Pinout Table
Page 36
Complete Pinout Table
ad-ug-1308_v1_9.pdf
ADM-PCIE-8V3 User Manual
Revision History
Date
Revision
Changed By
13 Jan 2016
1.0
K. Roth
Initial Release
15 Jan 2016
1.1
K. Roth
Added GPIO Option , and User EEPROM
25 Feb 2016
1.2
K. Roth
Added FireFly Breakout to Front Panel and description of
breakout, updated ADM-PCIE-8V3 Block Diagram to show
EEPROM, correct FPGA pin N29 net name from FB to LB
as in LTC2870 datasheet, added weight in Physical
Specifications, updated configuration flash part number in
Configuration From Flash Memory
23 Mar 2016
1.3
K. Roth
updated DDR4 SDRAM to list part numbers and reference
online csv, added note to drive LP_MODE low in section
QSFP28, Changed reference from ADM-XRC SDK to ADMPCIE-8V3 SDK, removed notes on automatic temperature
monitoring.
6 Jun 2016
1.4
K. Roth
Added Building and Programming Configuration Images,
Correct clock pin locations in PCIe Reference Clocks,
added note to use pullnone in Clocking, added note about
SEL pins to QSFP28 and FireFly, updated Thermal
Performance to use test results.
22 Aug 2016
1.5
K. Roth
Updated LEDs to correct Green LED index reference
mismatch
6 Jan 2017
1.6
K. Roth
Added available power by rail table to Power Requirements,
Added section: Custom Flash Write Interface, Updated
clock termination recommendation to HSTL_I in Clocking,
Added note about PCIe RX equalization options.
1 May 2017
1.7
K. Roth
Scaled thermal performance graph to match innacuracies of
current measurement circuit Thermal Performance, updated
Optional Blower to remove reference to vertical fan,
updated length and part number options in FireFly, updated
section USB Front Panel Interface to include avr2util
utilization.
21 Jun 2017
1.8
K. Roth
Updated all reference to DDR4 speeds at 16GB to be
2400MT/s and 32GB to be 1866MT/s.
28 Jun 2017
1.9
D. Flint
Updated Thermal Performance with data from more
accurate testing.
Revision Table
ad-ug-1308_v1_9.pdf
Nature of Change
Page 37
ADM-PCIE-8V3 User Manual
Page Intentionally left blank
Address:
Telephone:
Fax:
email:
website:
4.8
4 West Silvermills Lane,
Edinburgh, EH3 5BD, UK
+44 131 558 2600
+44 131 558 2700
sales@alpha-data.com
http://www.alpha-data.com
Address:
Telephone:
Fax:
email:
website:
611 Corporate Circle Suite H
Golden, CO 80401
(303) 954 8768
(866) 820 9956 - toll free
sales@alpha-data.com
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