3-V to 6-V Input, 1.5-A Output Synchronous

Typical Size
(6,3 mm x 6,4 mm)
TPS54110
SLVS500C – DECEMBER 2003 – REVISED FEBRUARY 2011
www.ti.com
3-V TO 6-V Input, 1.5-A Output Synchronous-Buck PWM
Switcher with Integrated FETs ( SWIFT™)
Check for Samples: TPS54110
FEATURES
DESCRIPTION
•
As members of the SWIFT family of dc/dc regulators,
the TPS54110 low-input-voltage high-output-current
synchronous-buck PWM converter integrates all
required active components. Included on the
substrate with the listed features are a true, highperformance, voltage error amplifier that provides
high performance under transient conditions; an
undervoltage-lockout circuit to prevent start-up until
the input voltage reaches 3 V; an internally and
externally set slow-start circuit to limit in-rush
currents; and a power-good output useful for
processor/logic reset, fault signaling, and supply
sequencing.
1
2
•
•
•
•
•
•
Integrated MOSFET Switches for High
Efficiency at 1.5-A Continuous Output Source
or Sink Current
0.9-V to 3.3-V Adjustable Output Voltage With
1% Accuracy
Externally Compensated for Design Flexibility
Fast Transient Response
Wide PWM Frequency: Fixed 350 kHz, 550 kHz,
or Adjustable 280 kHz to 700 kHz
Load Protected by Peak Current Limit and
Thermal Shutdown
Integrated Solution Reduces Board Area and
Total Cost
APPLICATIONS
•
•
•
•
Low-Voltage, High-Density Systems With
Power Distributed at 5 V or 3.3 V
Point of Load Regulation for High
Performance DSPs, FPGAs, ASICs, and
Microprocessors
Broadband, Networking, and Optical
Communications Infrastructure
Portable Computing/Notebook PCs
The TPS54110 device is available in a thermally
enhanced 20-pin TSSOP (PWP) PowerPAD™
package, which eliminates bulky heatsinks. TI
provides evaluation modules and the SWIFT designer
software tool to aid in quickly achieving highperformance power supply designs to meet
aggressive equipment development cycles.
Simplified Schematic
EFFICIENCY
vs
OUTPUT CURRENT
6.8 µH
Input
VIN
Output
PH
100
TPS54110
BOOT
10 µF
0.047 µF
95
100 µF
90
PGND
Efficiency - %
85
33 pF
COMP
19.1 kΩ
3.92 kΩ
VBIAS
VSENSE
0.1 µF
2700 pF
80
75
70
65
2.05 kΩ
60
AGND
2200 pF
55
3.92 kΩ
Compensation
Network
50
0
0.25
0.5
IO-
0.75
1
1.25.
1.5
Output Current - A
1
2
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
SWIFT, PowerPAD are trademarks of Texas Instruments.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
© 2003–2011, Texas Instruments Incorporated
TPS54110
SLVS500C – DECEMBER 2003 – REVISED FEBRUARY 2011
www.ti.com
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
ORDERING INFORMATION
(1)
TJ
OUTPUT VOLTAGE
PACKAGED DEVICES
PLASTIC HTSSOP (PWP) (1)
–40°C to 125°C
Adjustable to 0.891 V
TPS54110PWP
The PWP package is also available taped and reeled. Add an R suffix to the device type (i.e., TPS54110PWPR). See application
section of data sheet for PowerPAD drawing and layout information.
ABSOLUTE MAXIMUM RATINGS
over operating free-air temperature range unless otherwise noted (1)
Input voltage range, VI
Output voltage range, VO
Source current, IO
VALUE
UNIT
VIN, SS/ENA, SYNC
–0.3 to 7
V
RT
–0.3 to 6
V
VSENSE
–0.3 to 4
V
BOOT
–0.3 to 17
V
VBIAS, PWRGD, COMP
–0.3 to 7
V
PH
–0.6 to 10
V
PH
Internally Limited
COMP, VBIAS
6
PH
Sink current
Voltage differential
mA
3.5
A
6
mA
SS/ENA,PWRGD
10
mA
AGND to PGND
±0.3
V
COMP
Continuous power dissipation
See Thermal Information Table
Operating virtual junction temperature range, TJ
–40 to 150
°C
Storage temperature, Tstg
–65 to 150
°C
(1)
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating
conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
RECOMMENDED OPERATING CONDITIONS
MIN
Input voltage range, VI
Operating junction temperature, TJ
NOM
MAX
UNIT
3
6
V
–40
125
°C
THERMAL INFORMATION
TPS54110
THERMAL METRIC (1)
PWP
UNITS
20 PINS
θJA
Junction-to-ambient thermal resistance
34.0
θJCtop
Junction-to-case (top) thermal resistance
21.2
θJB
Junction-to-board thermal resistance
6.7
ψJT
Junction-to-top characterization parameter
0.3
ψJB
Junction-to-board characterization parameter
6.5
θJCbot
Junction-to-case (bottom) thermal resistance
1.5
(1)
2
°C/W
For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.
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ELECTRICAL CHARACTERISTICS
TJ = –40°C to 125°C, VIN = 3 V to 6 V (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
fs = 350 kHz, SYNC ≤ 0.8 V, RT open
4.5
8.5
fs = 550 kHz, Phase pin open,
SYNC ≥ 2.5 V, RT open,
5.8
9.6
1
1.4
2.95
3
UNIT
SUPPLY VOLTAGE, VIN
VIN input voltage range
Quiescent current
3
Shutdown, SS/ENA = 0 V
6
V
mA
UNDER VOLTAGE LOCK OUT
Start threshold voltage, UVLO
Stop threshold voltage, UVLO
2.70
Hysteresis voltage, UVLO
Rising and falling edge deglitch,
UVLO (1)
2.80
V
0.12
V
2.5
µs
BIAS VOLTAGE
VO
Output voltage, VBIAS
Output current, VBIAS
I(VBIAS) = 0
2.70
2.80
(2)
2.90
V
100
µA
0.900
V
CUMULATIVE REFERENCE
Vref
Accuracy
0.882
0.891
REGULATION
Line regulation (1) (3)
Load regulation (1) (3)
IL = 0.75 A,
fs = 350 kHz,
TJ = 85°C
0.05
IL = 0.75 A,
fs = 550 kHz,
TJ = 85°C
0.05
IL = 0 A to 1.5 A, fs = 350 kHz,
TJ = 85°C
0.01
IL = 0 A to 1.5 A
fs = 550 kHz,
TJ = 85°C
0.01
SYNC ≤ 0.8 V,
RT open
280
350
420
SYNC ≥ 2.5 V,
RT open
440
550
660
RT = 180 kΩ (1% resistor to AGND) (1)
252
280
308
RT = 100 kΩ (1% resistor to AGND)
460
500
540
663
700
762
%/V
%/A
OSCILLATOR
Internally set free-running
frequency range
Externally set free-running
frequency range
RT = 68 kΩ (1% resistor to AGND)
(1)
High-level threshold voltage,
SYNC
2.5
V
700
kHz
ns
330
Ramp valley (1)
0.75
Ramp amplitude (peak-to-peak) (1)
V
1
Minimum controllable on time (1)
V
200
Maximum duty cycle
(1)
(2)
(3)
0.8
50
Frequency range, SYNC (1)
kHz
V
Low-level threshold voltage,
SYNC
Pulse duration, SYNC (1)
kHz
90
ns
%
Specified by design
Static resistive loads only
Specified by the circuit used in Figure 9.
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ELECTRICAL CHARACTERISTICS (continued)
TJ = –40°C to 125°C, VIN = 3 V to 6 V (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
90
110
5
MAX
UNIT
ERROR AMPLIFIER
Error-amplifier open loop voltage
gain
1 kΩ COMP to AGND (4)
Error-amplifier unity gain
bandwidth
Parallel 10 kΩ, 160 pF COMP to AGND (4)
3
Error-amplifier common-mode
input voltage range
Powered by internal LDO (4)
0
IIB
Input bias current, VSENSE
VSENSE = Vref
VO
Output voltage slew rate
(symmetric), COMP (4)
60
dB
MHz
VBIAS
V
250
nA
1.2
V/µs
PWM COMPARATOR
PWM comparator propagation
delay time, PWM comparator
input to PH pin (excluding dead
time)
10 mV overdrive (4)
70
85
ns
1.20
1.40
V
SLOW-START/ENABLE
Enable threshold voltage,
SS/ENA
0.82
Enable hysteresis voltage,
SS/ENA (4)
Falling-edge deglitch, SS/ENA
0.03
(4)
V
µs
2.5
Internal slow-start time
2.6
Charge current, SS/ENA
SS/ENA = 0 V
Discharge current, SS/ENA
SS/ENA = 1.3 V, VI = 1.5 V
3.35
4.1
ms
3
5
8
µA
1.5
2.3
4
mA
POWER GOOD
Power-good threshold voltage
VSENSE falling
Power-good hysteresis voltage (4)
Power-good falling-edge
deglitch (4)
Output saturation voltage,
PWRGD
I(sink) = 2.5 mA
Leakage current, PWRGD
VI = 5.5 V
93
%Vref
3
%Vref
35
µs
0.18
0.30
V
1
µA
CURRENT LIMIT
Current limit trip point
VI = 3 V, output shorted (4)
3.0
VI = 6 V, output shorted (4)
3.5
A
Current-limit leading edge
blanking time
100
ns
Current-limit total response time
200
ns
THERMAL SHUTDOWN
Thermal-shutdown trip point (4)
135
Thermal-shutdown hysteresis (4)
150
165
°C
°C
10
OUTPUT POWER MOSFETS
rDS(on)
(4)
(5)
(6)
4
Power MOSFET switches (5)
IO = 1.5 A,
VI = 6 V (6)
240
480
IO = 1.5 A,
VI = 3 V (6)
345
690
mΩ
Specified by design
Includes package and bondwire resistance
Matched MOSFETs, low side rDS(on) production tested, high side rDS(on) specified by design
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PIN ASSIGNMENTS
PWP PACKAGE
(TOP VIEW)
AGND
VSENSE
COMP
PWRGD
BOOT
PH
PH
PH
PH
PH
1
2
3
4
5
6
7
8
9
10
20
19
18
17
16
15
14
13
12
11
RT
SYNC
SS/ENA
VBIAS
VIN
VIN
VIN
PGND
PGND
PGND
TERMINAL FUNCTIONS
TERMINAL
DESCRIPTION
NAME
NO.
AGND
1
Analog ground—internally connected to the sensitive analog-ground circuitry. Connect to PGND and PowerPAD.
BOOT
5
Bootstrap input. 0.022-µF to 0.1-µF low-ESR capacitor connected from BOOT to PH generates floating drive for the
high-side FET driver.
COMP
3
Error amplifier output. Connect compensation network from COMP to VSENSE.
PGND
11–13
Power ground. High current return for the low-side driver and power MOSFET. Connect PGND with large copper
areas to the input and output supply returns, and negative terminals of the input and output capacitors. Connect to
AGND and PowerPAD.
PH
6–10
Phase input/output. Junction of the internal high and low-side power MOSFETs, and output inductor.
PWRGD
4
Power-good open drain output. High when VSENSE ≥ 93% Vref, otherwise PWRGD is low. Note that output is low
when SS/ENA is low or internal shutdown signal active.
RT
20
Frequency setting resistor input. Connect a resistor from RT to AGND to set the switching frequency, fs.
SS/ENA
18
Slow-start/enable input/output. Dual-function pin that provides logic input to enable/disable device operation and
capacitor input to externally set the start-up time.
SYNC
19
Synchronization input. Dual-function pin that provides logic input to synchronize to an external oscillator or pin select
between two internally set switching frequencies. When used to synchronize to an external signal, a resistor must be
connected to the RT pin.
VBIAS
17
Internal bias regulator output. Supplies regulated voltage to internal circuitry. Bypass VBIAS pin to AGND pin with a
high quality, low ESR 0.1-µF to 1.0-µF ceramic capacitor.
VIN
VSENSE
14–16
2
Input supply for the power MOSFET switches and internal bias regulator. Bypass VIN pins to PGND pins close to
device package with a high quality, low ESR 1-µF to 10-µF ceramic capacitor.
Error amplifier inverting input.
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FUNCTIONAL BLOCK DIAGRAM
VBIAS
AGND
VIN
Enable
Comparator
SS/ENA
Falling
Edge
Deglitch
1.2 V
Hysteresis: 0.03 V
2.5 µs
VIN UVLO
Comparator
VIN
2.95 V
Hysteresis: 0.16 V
REG
VBIAS
SHUTDOWN
VIN
ILIM
Comparator
Thermal
Shutdown
150C
°
3- 6V
Leading
Edge
Blanking
Falling
and
Rising
Edge
Deglitch
100 ns
BOOT
2.5 µs
SS_DIS
SHUTDOWN
Internal/External
Slow-start
(Internal Slow-start Time = 3.35 ms
PH
+
-
RQ
S
Error
Amplifier
Reference
VREF = 0.891 V
PWM
Comparator
LOUT
VO
CO
Adaptive Dead-Time
and
Control Logic
VIN
OSC
PGND
Powergood
Comparator
PWRGD
VSENSE
Falling
Edge
Deglitch
0.93 Vref
TPS54110
Hysteresis: 0.03 Vref
VSENSE
6
COMP
RT
SHUTDOWN
35 µs
SYNC
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TYPICAL CHARACTERISTICS
DRAIN-SOURCE ON-STATE
RESISTANCE
vs
JUNCTION TEMPERATURE
IO = 1.5 A
0.5
0.4
0.3
0.2
0.1
VI = 5 V
IO = 1.5 A
0.3
0.2
0.1
0
−40
0
−40
0
25
85
f − Internally Set Oscillator Frequency −kHz
0.4
VI = 3.3 V
Drain-Source On-State Resistance − Ω
Drain-Source On-State Resistance − Ω
0.6
125
0
25
125
85
750
650
SYNC ≥ 2.5 V
550
450
SYNC ≤ 0.8 V
350
250
−40
TJ − Junction Temperature − °C
TJ − Junction Temperature − °C
0
85
25
125
TJ − Junction Temperature − °C
Figure 1.
Figure 2.
Figure 3.
EXTERNALLY SET OSCILLATOR
FREQUENCY
vs
JUNCTION TEMPERATURE
VOLTAGE REFERENCE
vs
JUNCTION TEMPERATURE
OUTPUT VOLTAGE REGULATION
vs
INPUT VOLTAGE
800
0.8950
0.895
RT = 68 k
600
RT = 100 k
500
400
RT = 180 k
300
200
−40
0
85
25
VO − Output Voltage Regulation − V
TA = 85°C
700
Vref − Voltage Reference − V
f − Externally Set Oscillator Frequency − kHz
INTERNALLY SET OSCILLATOR
FREQUENCY
vs
JUNCTION TEMPERATURE
DRAIN-SOURCE ON-STATE
RESISTANCE
vs
JUNCTION TEMPERATURE
0.893
0.891
0.889
0.887
0.885
−40
125
TJ − Junction Temperature − °C
25
85
125
0.8870
3
3.80
−40
Phase
−80
−100
60
−120
40
Gain
20
−140
−160
0
−180
−20
−200
1M 10 M
1k
10 k 100 k
Internal Slow-Start Time − ms
−20
−60
80
6
INTERNAL SLOW-START TIME
vs
JUNCTION TEMPERATURE
Phase − Degrees
100
4
5
VI − Input Voltage − V
Figure 6.
0
RL= 10 kΩ,
CL = 160 pF,
TA = 25°C
120
Gain − dB
fS = 350 kHz
Figure 5.
140
100
0.8890
0.8850
0
ERROR AMPLIFIER
OPEN LOOP RESPONSE
10
0.8910
TJ − Junction Temperature − °C
Figure 4.
0
0.8930
f − Frequency − Hz
Figure 7.
3.65
3.50
3.35
3.20
3.05
2.90
2.75
−40
0
25
85
TJ − Junction Temperature − °C
125
Figure 8.
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APPLICATION INFORMATION
Figure 9 shows the schematic diagram for a typical TPS54110 application. The TPS54110 can provide up to
1.5 A of output current at a nominal output voltage of 3.3 V. For proper thermal performance, the exposed
PowerPAD underneath the device must be soldered down to the printed-circuit board.
R7
10 kΩ
VIN (4.5 − 5.5 V)
C8
2200 pF
PWRGD
+
C1
10 µF
U2
TPS54110PWP
R4
71.5 kΩ
20
19
18
17
16
15
14
C5
.047 µF
C4
0.1 µF
13
C9
10 µF
12
11
RT
AGND
SYNC
VSENSE
SS/ENA
COMP
VBIAS PWRGD
VIN
BOOT
VIN
PH
VIN
PH
PGND
PH
PGND
PH
1
R3
19.1 kΩ
C6
2700 pF
2
3
4
5
R5
2.05 kΩ
R1
10.7 kΩ
C7
33 pF
R2
3.92 kΩ
C3 0.047 µF
6
7
8
L1
6.8 µH
9
1
10
PGND
PH
PwrPd
2
3.3 V at 1.5 A
C2
100 µF
21
Figure 9. Application Schematic
Design Procedure
The following design procedure can be used to select component values for the TPS54110. Alternately, the
SWIFT Designer Software can be used to generate a complete design. The SWIFT Designer Software uses an
iterative design procedure to access a comprehensive database of components when generating a design. This
section presents a simplified discussion of the design process.
Design Parameters
The required parameters to begin the design process and values for this design example are listed in Table 1.
Table 1. Design Parameters
DESIGN PARAMETER
EXAMPLE VALUE
Input voltage range
4.5 to 5.5 V
Output voltage
3.3 V
Input ripple voltage
100 mV
Output ripple voltage
30 mV
Output current rating
1.5 A
Operating frequency
700 kHz
As an additional constraint, the design is set up to be small size and low component height.
Switching Frequency
The switching frequency is set within the range of 280 kHz to 700 kHz by connecting a resistor from the RT pin
to AGND. Equation 1 is used to determine the proper RT value.
100 ´ 500kHz
RT(k W) =
¦s(kHz)
(1)
In this example, the timing-resistor value chosen for R4 is 71.5 kΩ, setting the switching frequency to 700 kHz.
8
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Alternately, the TPS54110 can be set to preprogrammed switching frequencies of 350 kHz or 550 kHz by
connecting pins RT and SYNC as shown in Table 2.
Table 2. Design Parameters
FREQUENCY
RT
SYNC
350 kHz
Float
Float or AGND
550 kHz
Float
≥ 2.5 V
Input Capacitors
The TPS54110 requires an input decoupling capacitor and, depending on the application, a bulk input capacitor.
The minimum value for the decoupling capacitor, C9, is 10 uF. A high quality ceramic type X5R or X7R with a
voltage rating greater than the maximum input voltage is recommended. A bulk input capacitor may be needed,
especially if the TPS54110 circuit is not located within approximately 2 inches from the input voltage source. The
capacitance value is not critical, but the voltage rating must be greater than the maximum input voltage including
ripple voltage. The capacitor must filter the input ripple voltage to acceptable levels.
Input ripple voltage can be approximated by Equation 2:
I
´ 0.25
DVIN= OUT(MAX)
+ (IOUT(MAX) ´ ESRMAX )
CBULK ´ ¦SW
(2)
Where
IOUT(MAX) is the maximum load current, ƒSW is the switching frequency, CBULK is the bulk capacitor value and
ESRMAX is the maximum series resistance of the bulk capacitor.
Worst-case RMS ripple current is approximated by Equation 3:
I
ICIN = OUT(MAX)
2
(3)
In this case the input ripple voltage is 66 mV with a 10-µF bulk capacitor. Figure 15 shows the measured ripple
waveform. The RMS ripple current is 0.75 A. The maximum voltage across the input capacitors is VINMAX +
ΔVIN/2. The bypass capacitor and input bulk capacitor are each rated for 6.3 V and a ripple-current capacity of
1.5 A, providing some margin. It is very important that the maximum ratings for voltage and current are not
exceeded under any circumstance.
Output Filter Components
Two components, L1 and C2, are selected for the output filter. Since the TPS54110
externally-compensated device, a wide range of filter-component types and values are supported.
is
an
Inductor Selection
Use Equation 4 to calculate the minimum value of the output inductor:
VOUT ´ (VIN(MAX)-VOUT )
LMIN =
VIN(MAX) ´ KIND ´ IOUT ´ FSW
(4)
KIND is a coefficient that represents the amount of inductor ripple current relative to the maximum output current.
For designs using low-ESR capacitors such as ceramics, use KIND = 0.2. When using higher ESR output
capacitors, KIND = 0.1 yields better results. If higher ripple currents can be tolerated, KIND can be increased
allowing for a smaller output-inductor value.
This example design uses KIND = 0.2, yielding a minimum inductor value of 6.29 µH. The next-higher standard
value of 6.8 µH is chosen for this design. If a lower inductor value is desired, a larger amount of ripple current
must be tolerated.
The RMS-current and saturation-current ratings of the output filter inductor must not be exceeded. The RMS
inductor current can be found from Equation 5:
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2
IL(RMS) = I OUT(MAX) +
1 æ VOUT ´ (VIN(MAX) - VOUT ) ö
´ç
÷
12 è VIN(MAX) ´ LOUT ´ FSW ´ 0.8 ø
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2
(5)
The peak inductor current is determined from Equation 6:
VOUT ´ (VIN(MAX)-VOUT)
IL(PK) = IOUT(MAX) +
1.6 ´ VIN(MAX) ´ LOUT ´ FSW
(6)
For this design, the RMS inductor current is 1.503 A and the peak inductor current is 1.673 A. The inductor
chosen is a Coilcraft DS3316P-682 6.8 µH. It has a saturationcurrent rating of 2.8 A and an RMS current rating
of 2.2 A, easily meeting these requirements.
Capacitor Selection
The important design parameters for the output capacitor are dc voltage, ripple current, and equivalent series
resistance (ESR). The dc-voltage and ripple-current ratings must not be exceeded. The ESR rating is important
because along with the inductor current it determines the output ripple voltage level. The actual value of the
output capacitor is not critical, but some practical limits do exist. Consider the relationship between the desired
closed-loop crossover frequency of the design and LC corner frequency of the output filter. In general, it is
desirable to keep the closed-loop crossover frequency at less than 1/5 of the switching frequency. With high
switching frequencies such as the 700 kHz frequency of this design, internal circuit limitations of the TPS54110
limit the practical maximum crossover frequency to about 100 kHz. To allow adequate phase gain in the
compensation network, set the LC corner frequency to approximately one decade below the closed-loop
crossover frequency. This limits the minimum capacitor value for the output filter to:
COUT (MIN) =
æ K ö
´ç
÷
LOUT è 2p¦CO ø
1
2
(7)
where K is the frequency multiplier for the spread between fLC and fCO. K should be between 5 and 15, typically
10 for one decade of difference.
For a desired crossover of 60 kHz, K=10 and a 6.8 μH inductor, the minimum value for the output capacitor is
100 μF. The selected output capacitor must be rated for a voltage greater than the desired output voltage plus
one half the ripple voltage. Any derating factors must also be included. The maximum RMS ripple current in the
output capacitor is given by Equation 8:
1 é VOUT ´ (VIN(MAX) - VOUT ) ù
´
ICOUT(RMS) =
12 êë VIN(MAX) ´ LOUT ´ FSW ´ NC úû
(8)
where NC is the number of output capacitors in parallel.
The maximum ESR of the output capacitor is determined by the allowable output ripple specified in the initial
design parameters. The output ripple voltage is the inductor ripple current times the ESR of the output filter so
the maximum specified ESR as listed in the capacitor data sheet is given by Equation 9:
æV
´ L ´ F ´ 0.8 ö
ESRMAX =NC ´ çç IN(MAX) OUT SW
÷÷ ´ DVp-p(MAX)
è VOUT ´ (VIN(MAX)-VOUT ) ø
(9)
For this design example, a single 100 µF output capacitor is chosen for C2. The calculated RMS ripple current is
80 mA and the maximum ESR required is 87 mΩ. An example of a suitable capacitor is the Sanyo Poscap
6TPC100M, rated at 6.3 V with a maximum ESR of 45 milliohms and a ripple-current rating of 1.7 A.
Other capacitor types work well with the TPS54110, depending on the needs of the application.
Compensation Components
The external compensation used with the TPS54110 allows for a wide range of output-filter configurations. A
large range of capacitor values and dielectric types are supported. The design example uses type 3
compensation consisting of R1, R3, R5, C6, C7 and C8. Additionally, R2 and R1 form a voltage-divider network
that sets the output voltage. These component reference designators are the same as those used in the SWIFT
Designer Software.
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There are a number of different ways to design a compensation network. This procedure outlines a relatively
simple procedure that produces good results with most output filter combinations. Use the SWIFT Designer
Software for designs with unusually high closed-loop crossover frequencies; with low-value, low-ESR output
capacitors such as ceramics; or if you are unsure about the design procedure.
A number of considerations apply when designing compensation networks for the TPS54110. The compensated
error-amplifier gain must not be limited by the open-loop amplifier gain characteristics and must not produce
excessive gain at the switching frequency. Also, the closed-loop crossover frequency must be set less than one
fifth of the switching frequency, and the phase margin at crossover must be greater than 45 degrees. The
general procedure outlined here meets these requirements without going into great detail about the theory of
loop compensation.
First, calculate the output filter LC corner frequency using Equation 10:
1
¦LC =
2p LOUTCOUT
(10)
For the design example, ƒLC = 6103 Hz.
Choose a closed-loop crossover frequency greater than fLC and less than one fifth of the switching frequency.
Also, keep the crossover frequency below 100 kHz, as the error amplifier may not provide the desired gain at
higher frequencies. The 60-kHz crossover frequency chosen for this design provides comparatively wide loop
bandwidth while still allowing adequate phase boost to ensure stability.
Next, the values for the compensation components that set the poles and zeros of the compensation network are
calculated. Assuming an R1 value > than R5 and a C6 value > C7, the pole and zero locations are given by
Equation 11 through Equation 14:
1
¦Z1 =
2pR3C6
(11)
1
¦Z 2 =
2pR1C8
(12)
1
¦P1 =
2pR5C8
(13)
1
¦P 2 =
2pR3C7
(14)
Additionally there is a pole at the origin, which has unity gain at a frequency:
1
¦INT =
2pR1C6
(15)
This pole is used to set the overall gain of the compensated error amplifier and determines the closed loop
crossover frequency. Since R1 is given as 10 kΩ and the crossover frequency is selected as 60 kHz, the desired
fINT is calculated from Equation 16:
10 - 0.74 ´ ¦CO
¦INT =
2
(16)
And the value for C6 is given by Equation 17:
1
C6 =
2pR1¦INT
(17)
Since C6 is calculated to be 2900 pF, and the location of the integrator crossover frequency is important in
setting the overall loop crossover, adjust the value of R1 so that C6 is a standard value of 2700 pF, using
Equation 18:
1
R1 =
2pC6¦LC
(18)
The value for R1 is 10.7 KΩ
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The first zero, fZ1 is located at one half the output filter LC corner frequency, so R3 is calculated from:
1
R3 =
pC6¦LC
(19)
The second zero, fZ2 is located at the output filter LC corner frequency, so C8 is calculated from:
1
C8 =
2pR1¦LC
(20)
The first pole, fP1 is located to coincide with output filter ESR zero frequency. This frequency is given by:
1
¦ESR 0 =
2pRESRCOUT
(21)
where RESR is the equivalent series resistance of the output capacitor.
In this case, the ESR zero frequency is 35.4 kHz, and R5 is calculated from:
1
R5 =
2pC8¦ESR
(22)
The final pole is placed at a frequency high enough above the closed-loop crossover frequency to avoid causing
an excessive phase decrease at the crossover frequency while still providing enough attenuation so that there is
little or no gain at the switching frequency. The fP2 pole location for this circuit is set to 4 times the closed-loop
crossover frequency and the last compensation component value C7 is derived:
1
C7 =
8pR3¦CO
(23)
Finally, calculate the R2 resistor value for the output voltage of 3.3 V using Equation 24:
R1 ´ 0.891
R2 =
VOUT -0.891
(24)
For this TPS54110 design, use R1 = 10.7 kΩ instead of 10.0 kΩ. R2 is then 3.92 kΩ.
Since capacitors are only available in a limited range of standard values, the nearest standard value was chosen
for each capacitor. The measured closed-loop response for this design is shown in Figure 19.
BIAS and Bootstrap Capacitors
Every TPS54110 design requires a bootstrap capacitor (C3), and a bias capacitor (C4). The bootstrap capacitor
must be between 0.022 µF and 0.1 µF. This design uses 0.047 µF. The bootstrap capacitor is located between
the PH pins and BOOT. The bias capacitor is connected between the VBIAS pin and AGND. Recommended
values are 0.1 µF to 1.0 µF. This design uses 0.1 µF. Use high-quality ceramic capacitors with X7R or X5R
grade dielectric for temperature stability. Place them as close to the device pins as possible.
Grounding and PowerPAD Layout
The TPS54110 has two internal grounds (analog and power). Inside the TPS54110, the analog ground connects
all noise-sensitive signals, while the power ground connects the noisier power signals. The PowerPAD must be
tied directly to AGND. Noise injected between the two grounds can degrade the performance of the TPS54110,
particularly at higher output currents. However, ground noise on an analog ground plane can also cause
problems with some of the control and bias signals. For these reasons, separate analog and power ground
planes are recommended. Tie these two planes together directly at the IC to reduce noise between the two
grounds. The only components that tie directly to the power-ground plane are the input capacitor, the output
capacitor, the input voltage decoupling capacitor, and the PGND pins of the TPS54110. The layout of the
TPS54110 evaluation module represents recommended layout for a 2-layer board. Documentation for the
TPS54110 evaluation module is obtained from the Texas Instruments web site under the TPS54110 product
folder and in the application note, TI literature number SLVA109.
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6 PL ∅ 0.0130
4 PL ∅ 0.0180
Connect Pin 1 to Analog Ground Plane
in This Area for Optimum Performance
Minimum Recommended Thermal Vias: 6 × .013 dia.
Inside Powerpad Area 4 × .018 dia. Under Device as Shown.
Additional .018 dia. Vias May be Used if Top Side Analog
Ground Area is Extended.
0.0150
0.06
0.0227
0.0600
0.0400
0.2560
0.2454
0.1010
0.0400
0.0600
0.0256
0.1700
0.1340
0.0620
0.0400
Minimum Recommended Top
Side Analog Ground Area
Minimum Recommended Exposed
Copper Area For Powerpad. 5mm
Stencils may Require 10 Percent
Larger Area
Figure 10. Recommended Land Pattern for 20-Pin PWP PowerPAD
Layout Considerations for Thermal Performance
For operation at full rated load current, the analog ground plane must provide adequate heat dissipation area. A
3-inch-by-3-inch plane of 1-ounce copper is recommended, though not mandatory, depending on ambient
temperature and airflow. Most applications have larger areas of internal ground plane available. Connect the
PowerPAD to the largest area available. Additional areas on the top or bottom layers also help dissipate heat.
Use any area available when 1.5-A or greater operation is desired. Connect the exposed area of the PowerPAD
to the analog ground-plane layer with 0.013-inch-diameter vias to avoid solder wicking through the vias. An
adequate design includes six vias in the PowerPAD area with four additional vias located under the device
package. The size of the vias under the package, but not in the exposed thermal pad area, can be increased to
0.018. Additional vias in areas not under the device package enhance thermal performance.
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PERFORMANCE GRAPHS
All performance data shown for VI = 5 V, VO = 3.3 V, fs = 700 kHz, TA = 25°C, Figure 9
EFFICIENCY
vs
OUTPUT CURRENT
POWER DISSIPATION
vs
OUTPUT CURRENT
LOAD REGULATION
vs
OUTPUT CURRENT
1.2
100
0.05
95
Efficiency − %
85
80
75
70
65
60
1
Output Voltage Varistion − %
PD − Power Dissipation − W
0.04
90
0.8
0.6
0.4
0.2
0.03
0.02
0.01
0
−0.01
−0.02
−0.03
−0.04
55
50
0
0.25
0.5
0.75
1
1.25
1.5
IO − Output Current − A
−0.05
0
0
0.25
0.5
0.75
1
1.25
0
1.5
0.25
Figure 11.
Figure 12.
LINE REGULATION
vs
INPUT VOLTAGE
0.5
0.75
1
1.25
1.5
IO − Output Current − A
IO − Output Current − A
Figure 13.
INPUT VOLTAGE RIPPLE
OUTPUT VOLTAGE RIPPLE
0.02
VI = 50 mV/div (AC)
Output Voltage Varistion − %
0.015
VO = 10 mV/div (AC)
0.01
IO = 0.75 A
0.005
0
V(phase)= 2 V/div
V(phase)= 2 V/div
IO = 0 A
−0.005
IO = 1.5 A
−0.01
−0.015
−0.02
4.5
4.75
5
5.25
5.5
Time = 500 ns/div
Time = 500 ns/div
VI − Input Voltage − V
OUTPUT VOLTAGE TRANSIENT
RESPONSE
Figure 15.
Figure 16.
START UP WAVEFORM
MEASURED LOOP RESPONSE
180
60
VO= 10 mV/div (AC)
VI = 2 V/div
150
50
Phase
40
60
VO = 1 V/div
Gain − dB
20
IO= 1 V/div
10
30
Gain
0
0
−10
−30
−20
−60
−30
−90
−40
−120
−50
−150
−180
1M
−60
Time = 200 s/div
Time = 5 ms/div
120
90
30
Phase − Degrees
Figure 14.
100
1k
10 k
100 k
f − Frequency − Hz
Figure 17.
14
Figure 18.
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Very-Small Form-Factor Application
R7
10 kΩ
VIN
C8
560 pF
PWRGD
+
R4
71.5 kΩ
C1
OPEN
U2
TPS54110PWP
20
19
18
17
16
15
14
C5
OPEN
C4
0.1 µF
C9
10 µF
13
12
11
RT
AGND
SYNC
SS/ENA
VSENSE
COMP
VBIAS PWRGD
VIN
BOOT
VIN
PH
VIN
PH
PGND
PH
PGND
PH
1
R3
1.74 kΩ
C6
1000 pF
2
3
4
5
R5
432 Ω
R1
10.0 kΩ
R2
14.7 kΩ
C7
47 pF
C3 0.047 µF
6
7
8
L1
1 µH
9
10
PGND
PH
PwrPd
1
2
1.5 V at 1.5 A
C2
10 µF
21
Figure 20. Small Form-Factor Reference Design
Figure 20 shows an application schematic for a TPS54110 application designed for extremely small size. To
achieve this goal, the design procedure given in the previous application circuit is modified. For example, in order
to use a small-footprint Coilcraft DO3314-103MX inductor, the maximum-allowable inductor ripple current was
increased above that normally specified. A small 0805 10-µF ceramic capacitor is used in the output filter. All the
additional components are 0402 case size.
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All performance data shown for VI = 5 V, VO = 1.5 V, FS = 700 kHz, TA = 25°C, Figure 20
EFFICIENCY
vs
OUTPUT CURRENT
POWER DISSIPATION
vs
OUTPUT CURRENT
LOAD REGULATION
vs
OUTPUT CURRENT
100
0.1
95
Efficiency − %
85
VI = 5 V
80
75
70
65
1.2
Output Voltage Varistion − %
PD − Power Dissipation − W
0.08
90
1
0.8
0.6
VI = 5 V
0.4
VI = 3.3 V
60
55
0.2
VI = 3.3 V
0.06
0.04
0.02
−0.04
0
0.25
0.5
0.75
1
1.25
−0.08
0
1.5
IO − Output Current − A
VI = 5 V
−0.06
0
50
VI = 3.3 V
0
−0.02
−0.1
0.25
0.5
0.75
1
1.25
1.5
0
0.25
0.5
0.75
1
1.25
IO − Output Current − A
IO − Output Current − A
Figure 21.
Figure 22.
LINE REGULATION
vs
INPUT VOLTAGE
1.5
Figure 23.
INPUT VOLTAGE RIPPLE
OUTPUT VOLTAGE RIPPLE
0.02
Output Voltage Varistion − %
VI = 50 mV/div (AC)
VO = 20 mV/div (AC)
0.015
0.01
IO = 0.75 A
0.005
0
IO = 0 A
V(phase) = 2 V/div
V(phase) = 2 V/div
−0.005
−0.01
IO = 1.5 A
−0.015
−0.02
3
3.5
4
4.5
5
5.5
6
Time = 500 ns/div
Time = 500 ns/div
VI − Input Voltage − V
Figure 24.
Figure 25.
OUTPUT VOLTAGE TRANSIENT
RESPONSE
Figure 26.
START UP WAVEFORM
VI = 1 V/div
VO= 20 mV/div (AC)
VO = 500 mV/div
IO= 1 V/div
Time = 5 ms/div
Time = 200 s/div
Figure 27.
16
Figure 28.
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Two-Output Sequenced-Startup Application
PWRGD_3P3
VI 5 V
R7
C8
560 pF
10 kΩ
+
R4
71.5 kΩ
C1
470 µF
U1
TPS54110PWP
20
RT
AGND
19
SYNC VSENSE
18
SS/ENA COMP
17
VBIAS PWRGD
16
VIN
BOOT
15
VIN
PH
14
VIN
PH
13
PGND
PH
12
PH
PGND
11 PGND
PH
PWPD
21
C4
0.1 µF
C9
10 µF
1
2
3
4
5
6
C6
R3
1.74 kΩ 1000 pF
R1
10 kΩ
R2
3.74 kΩ
C7
47 pF
C3 0.047 µF
7
8
9
L1
1 µH
10
1
3.3 V at 1.5 A
C2
10 µF
R8
PWRGD_1P5
C13
560 pF
U2
TPS54110PWP
20
19
18
17
16
C10
0.1 µF
C15
10 µF
15
14
13
12
11
RT
AGND
SYNC VSENSE
SS/ENA COMP
VBIAS PWRGD
VIN
BOOT
VIN
PH
VIN
PH
PGND
PH
PH
PGND
PGND
PH
PWPD
21
VOUT1
2
10 kΩ
R9
71.5 kΩ
R5
432 Ω
1
R12
432 Ω
C5
R6
1.74 kΩ 1000 pF
2
C11
3
47 pF
4
5 C14 0.047 µF
6
7
8
9
10
R11
10 kΩ
R10
14.7 kΩ
L2
1 µH
1
VOUT2
2
1.5 V at 1.5 A
C12
10 µF
Figure 29. TPS54110 Sequencing Application Circuit
In Figure 29, the power-good output of U1 is used as a sequencing signal in a two-output design. Connecting the
PWRGD pin of U1 to the SS/ENA pin of U2 causes the 1.5-V output to ramp up after the 3.3-V output is within
regulation. Figure 30 shows the startup waveforms associated with this circuit.
When VIN reaches the UVLO-start threshold, the U1 output ramps up towards the 3.3-V set point. After the output
reaches 90 percent of 3.3 V, the U1 asserts the power-good signal driving the U2 SS/ENA input high. The output
of U2 then ramps up towards the final output set point of 1.5 V.
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VIN − 5 V/div
U1 − VOUT1
3.3 − 2 V/div
U1 PWRGD
− 5 V/div
U2 − VOUT2 1.5 − 2 V/div
Figure 30. Sequencing Start Up Waveforms
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DETAILED DESCRIPTION
Under Voltage Lock Out (UVLO)
The TPS54110 incorporates an under voltage lockout circuit to keep the device disabled when the input voltage
(VIN) is insufficient. During power up, internal circuits are held inactive until VIN exceeds the nominal UVLO
threshold voltage of 2.95 V. Once the UVLO start threshold is reached, device start-up begins. The device
operates until VIN falls below the nominal UVLO stop threshold of 2.8 V. Hysteresis in the UVLO comparator,
and a 2.5-µs rising and falling edge deglitch circuit reduce the likelihood of shutting the device down due to noise
on VIN.
Slow-Start/Enable (SS/ENA)
The slow-start/enable pin provides two functions; first, the pin acts as an enable (shutdown) control by keeping
the device turned off until the voltage exceeds the start threshold voltage of approximately 1.2 V. When SS/ENA
exceeds the enable threshold, device start up begins. The reference voltage fed to the error amplifier is linearly
ramped up from 0 V to 0.891 V in 3.35 ms. Similarly, the converter output voltage reaches regulation in
approximately 3.35 ms. Voltage hysteresis and a 2.5-µs falling edge deglitch circuit reduce the likelihood of
triggering the enable due to noise.
The second function of the SS/ENA pin provides an external means of extending the slow-start time with a
low-value capacitor connected between SS/ENA and AGND. Adding a capacitor to the SS/ENA pin has two
effects on start-up. First, a delay occurs between release of the SS/ENA pin and start up of the output. The delay
is proportional to the slow-start capacitor value and lasts until the SS/ENA pin reaches the enable threshold. The
start-up delay is approximately:
1.2V
td=C(SS) ´
5ma
(25)
Second, as the output becomes active, a brief ramp-up at the internal slow-start rate may be observed before the
externally set slow-start rate takes control and the output rises at a rate proportional to the slow-start capacitor.
The slow-start time set by the capacitor is approximately:
0.7V
t(SS)=C(SS) ´
5ma
(26)
The actual slow-start is likely to be less than the above approximation due to the brief ramp-up at the internal
rate.
VBIAS Regulator (VBIAS)
The VBIAS regulator provides internal analog and digital blocks with a stable supply voltage over variations in
junction temperature and input voltage. A high quality, low-ESR, ceramic bypass capacitor is required on the
VBIAS pin. X7R or X5R grade dielectrics are recommended because their values are more stable over
temperature. Place the bypass capacitor close to the VBIAS pin and returned to AGND. External loading on
VBIAS is allowed, with the caution that internal circuits require a minimum VBIAS of 2.70 V, and external loads
on VBIAS with ac or digital switching noise may degrade performance. The VBIAS pin may be useful as a
reference voltage for external circuits.
Voltage Reference
The voltage reference system produces a precise Vref signal by scaling the output of a temperature stable
bandgap circuit. During manufacture, the bandgap and scaling circuits are trimmed to produce 0.891 V at the
output of the error amplifier, with the amplifier connected as a voltage follower. The trim procedure adds to the
high precision regulation of the TPS54110, since it cancels offset errors in the scale and error amplifier circuits.
Oscillator and PWM Ramp
The oscillator frequency can be set to internally fixed values of 350 kHz or 550 kHz using the SYNC pin as a
static digital input. If a different frequency of operation is required for the application, the oscillator frequency can
be externally adjusted from 280 kHz to 700 kHz by connecting a resistor from the RT pin to ground and floating
the SYNC pin. The switching frequency is approximated by the following equation, where R is the resistance
from RT to AGND:
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SWITCHING FREQUENCY=
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100kW
´ 500 kHz
R
(27)
External synchronization of the PWM ramp is possible over the frequency range of 330 kHz to 700 kHz by driving
a synchronization signal into SYNC and connecting a resistor from RT to AGND. Choose an RT resistor that sets
the free-running frequency to 80% of the synchronization signal. Table 3 summarizes the frequency selection
configurations.
Table 3. Summary of the Frequency Selection Configurations
SWITCHING FREQUENCY
SYNC PIN
RT PIN
350 kHz, internally set
Float or AGND
Float
550 kHz, internally set
≥ 2.5 V
Float
Externally set 280 kHz to 700 kHz Float
R = 68 k to 180 k
Externally synchronized
frequency
R = RT value for 80% of external
synchronization frequency
Synchronization signal
Error Amplifier
The high-performance, wide-bandwidth, voltage error amplifier sets the TPS54110 apart from most dc/dc
converters. The user is given the flexibility to use a wide range of output L- and C-filter components to suit the
particular application needs. Type-2 or type-3 compensation can be employed using external compensation
components.
PWM Control
Signals from the error-amplifier output, oscillator, and current-limit circuit are processed by the PWM control
logic. Referring to the internal block diagram, the control logic includes the PWM comparator, OR gate, PWM
latch, and portions of the adaptive dead-time and control-logic block. During steady-state operation below the
current-limit threshold, the PWM-comparator output and oscillator pulse train alternately reset and set the PWM
latch. Once the PWM latch is set, the low-side FET remains on for a minimum duration set by the oscillator pulse
duration. During this period, the PWM ramp discharges rapidly to its valley voltage. When the ramp begins to
charge back up, the low-side FET turns off and high-side FET turns on. As the PWM ramp voltage exceeds the
error-amplifier output voltage, the PWM comparator resets the latch, thus turning off the high-side FET and
turning on the low-side FET. The low-side FET remains on until the next oscillator pulse discharges the PWM
ramp.
During transient conditions, the error amplifier output could be below the PWM ramp valley voltage or above the
PWM peak voltage. If the error-amplifier output is high, the PWM latch is never reset and the high-side FET
remains on until the oscillator pulse signals the control logic to turn the high-side FET off and the low-side FET
on. The device operates at its maximum duty cycle until the output voltage rises to the regulation set-point,
setting VSENSE to approximately the same voltage as Vref. If the error-amplifier output is low, the PWM latch is
continually reset and the high-side FET does not turn on. The low-side FET remains on until the VSENSE
voltage decreases to a range that allows the PWM comparator to change states. The TPS54110 is capable of
sinking current continuously until the output reaches the regulation set-point.
If the current-limit comparator remains tripped longer than 100 ns, the PWM latch resets before the PWM ramp
exceeds the error-amplifier output. The high-side FET turns off and low-side FET turns on to decrease the
energy in the output inductor, and consequently the output current. This process is repeated each cycle that the
current-limit comparator is tripped.
Dead-Time Control and MOSFET Drivers
Adaptive dead-time control prevents shoot-through current from flowing in both N-channel power MOSFETs
during the switching transitions by actively controlling the turn-on times of the MOSFET drivers. The high-side
driver does not turn on until the gate-drive voltage to the low-side FET is below 2 V. The low-side driver does not
turn on until the voltage at the gate of the high-side MOSFETs is below 2 V. The high-side and low-side drivers
are designed with 300-mA source and sink capability to quickly drive the power MOSFETs gates. The low-side
driver is supplied from VIN, while the high-side driver is supplied from the BOOT pin. A bootstrap circuit uses an
external BOOT capacitor and an internal 2.5-Ω bootstrap switch connected between the VIN and BOOT pins.
The integrated bootstrap switch improves drive efficiency and reduces external-component count.
20
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Product Folder Link(s): TPS54110
TPS54110
www.ti.com
SLVS500C – DECEMBER 2003 – REVISED FEBRUARY 2011
Overcurrent Protection
Cycle-by-cycle current limiting is achieved by sensing the current flowing through the high-side MOSFET and
differential amplifier and comparing it to the preset overcurrent threshold. The high-side MOSFET is turned off
within 200 ns of reaching the current-limit threshold. A 100-ns leading-edge blanking circuit prevents false
tripping of the current limit. Current-limit detection occurs only when current flows from VIN to PH when sourcing
current to the output filter. Load protection during current-sink operation is provided by thermal shutdown.
Thermal Shutdown
The device uses the thermal shutdown to turn off the power MOSFETs and disable the controller if the junction
temperature exceeds 150°C. The device is released from shutdown when the junction temperature decreases to
10°C below the thermal-shutdown trip point, and starts up under control of the slow-start circuit. Thermal
shutdown provides protection when an overload condition is sustained for several milliseconds. In a
persistent-fault condition, the device cycles continuously; starting up under control of the soft-start circuit, heating
up due to the fault, and then shutting down upon reaching the thermal-shutdown point.
Power Good (PWRDG)
The power-good circuit monitors for undervoltage conditions on VSENSE. If the voltage on VSENSE is 7% below
the reference voltage, the open-drain PWRGD output is pulled low. PWRGD is also pulled low if VIN is less than
the UVLO threshold, or SS/ENA is low, or if thermal shutdown asserts. When VIN = UVLO threshold, SS/ENA =
enable threshold, and VSENSE > 93% of Vref, the open-drain output of the PWRGD pin is high. A hysteresis
voltage equal to 3% of Vref and a 35-µs falling-edge deglitch circuit prevent tripping of the power-good
comparator due to high frequency noise.
PCB Layout Considerations
The VIN pins are connected together on the printed board (PCB) and bypassed with a low-ESR ceramic bypass
capacitor. Minimize the loop area formed by the bypass capacitor connections, the VIN pins, and the TPS54110
ground pins. The recommended bypass capacitor is 10-μF (minimum) ceramic with X5R or X7R dielectric. The
optimum placement is closest to the VIN pins and the AGND and PGND pins. See Figure 31 for an example
layout. It has an area of ground on the top layer directly under the IC, with an exposed area for connection to the
PowerPAD. Use vias to connect this ground area to any internal ground planes. Use additional vias at the ground
side of the input and output filter capacitors as well. Tie the AGND and PGND pins to the PCB ground area
under the device as shown. Use a separate wide trace for the analog-ground path, connecting the voltage
set-point divider, timing resistor RT, slow-start capacitor and bias-capacitor grounds. Tie the PH pins together
and route to the output inductor. Since the PH connection is the switching node, locate the inductor very close to
the PH pins, and minimize the area of the conductor to prevent excessive capacitive coupling. Connect the boot
capacitor between the phase node and the BOOT pin as shown. Keep the boot capacitor close to the IC and
minimize the conductor trace lengths. Connect the output-filter capacitor(s) as shown between the VOUT trace
and PGND. It is important to keep the loop formed by the PH pins, Lout, Cout and PGND as small as is practical.
Place the compensation components from the VOUT trace to the VSENSE and COMP pins. Do not place these
components too close to the PH trace. Due to the size of the IC package and the device pin-out, they must be
somewhat closely routed while maintaining as much separation as possible, yet keeping the layout compact.
Connect the bias capacitor from the VBIAS pin to analog ground using the isolated analog ground trace. If a
slow-start capacitor or RT resistor is used, or if the SYNC pin is used to select 350-kHz operating frequency,
connect them to this trace as well.
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Product Folder Link(s): TPS54110
21
TPS54110
SLVS500C – DECEMBER 2003 – REVISED FEBRUARY 2011
www.ti.com
ANALOG GROUND TRACE
FREQUENCY SET RESISTOR
AGND
RT
SYNC
VSENSE
COMPENSATION
NETWORK
COMP
SS/ENA
PWRGD
BOOT
CAPACITOR
BOOT
SLOW START
CAPACITOR
VBIAS
Exposed
Powerpad
Area
BIAS CAPACITOR
VIN
PH
VIN
PH
VIN
PH
PGND
PH
PGND
PH
PGND
VIN
VOUT
LOUT
OUTPUT INDUCTOR
PH
COUT
OUTPUT
FILTER
CAPACITOR
INPUT
BYPASS
CAPACITOR
INPUT
BULK
FILTER
PGND
TOPSIDE GROUND AREA
VIA to Ground Plane
Figure 31. PC Board Layout Example
22
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Product Folder Link(s): TPS54110
PACKAGE OPTION ADDENDUM
www.ti.com
8-Nov-2014
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
Lead/Ball Finish
MSL Peak Temp
(2)
(6)
(3)
Op Temp (°C)
Device Marking
(4/5)
TPS54110PWP
ACTIVE
HTSSOP
PWP
20
70
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
-40 to 85
TPS54110
TPS54110PWPG4
ACTIVE
HTSSOP
PWP
20
70
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
-40 to 85
TPS54110
TPS54110PWPR
ACTIVE
HTSSOP
PWP
20
2000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
-40 to 85
TPS54110
TPS54110PWPRG4
ACTIVE
HTSSOP
PWP
20
2000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
-40 to 85
TPS54110
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Addendum-Page 1
Samples
PACKAGE OPTION ADDENDUM
www.ti.com
8-Nov-2014
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
OTHER QUALIFIED VERSIONS OF TPS54110 :
• Automotive: TPS54110-Q1
NOTE: Qualified Version Definitions:
• Automotive - Q100 devices qualified for high-reliability automotive applications targeting zero defects
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
14-Jul-2012
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
TPS54110PWPR
Package Package Pins
Type Drawing
SPQ
HTSSOP
2000
PWP
20
Reel
Reel
A0
Diameter Width (mm)
(mm) W1 (mm)
330.0
16.4
Pack Materials-Page 1
6.95
B0
(mm)
K0
(mm)
P1
(mm)
7.1
1.6
8.0
W
Pin1
(mm) Quadrant
16.0
Q1
PACKAGE MATERIALS INFORMATION
www.ti.com
14-Jul-2012
*All dimensions are nominal
Device
Package Type
Package Drawing
Pins
SPQ
Length (mm)
Width (mm)
Height (mm)
TPS54110PWPR
HTSSOP
PWP
20
2000
367.0
367.0
38.0
Pack Materials-Page 2
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