Implementing SpaceWire Clock and Data Recovery in

Application Note AC444
Implementing SpaceWire Clock and Data Recovery
in RTG4 FPGAs
Table of Contents
Purpose . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
Internal References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
External References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
Design Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
SpaceWire Coding and Signaling Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
SpaceWire Clock and Data Recovery . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
RTG4 SpaceWire Clock Recovery Block Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Using RTG4 SpaceWire Clock Recovery Block
Implementing the RTG4 Data Recovery Block .
I/O Delay Adjustment . . . . . . . . . . . . . .
Timing Analysis of RTG4 Data Recovery Block
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.8
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11
12
Design Examples . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Simulating the Design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Running the Design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Conclusion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Appendix - Design and Programming Files . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
List of Changes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Purpose
RTG4™ field programmable gate array (FPGA) contains built-in RX clock recovery circuit for SpaceWire
application. The RX clock recovery circuit and the FPGA logic allows easy implementation of the
SpaceWire receiver block in the RTG4 FPGA device. This application note describes uses of the RX
clock recovery circuit and SpaceWire receiver implementation with a reference design. The reference
design is implemented in the RTG4 Development Kit.
Introduction
The SpaceWire protocol is widely used to handle the payload data on-board a spacecraft. It uses
data-strobe (DS) encoding, which encodes the transmission clock with the data into data and strobe
therefore the clock can be recovered by xor-ing the data and strobe lines together. The recovered clock
provides the clock signals used by the receiver. The clock recovery and receiver circuitry design appears
to be simple but could presents serious timing closure challenges when targeted onto a generic FPGA
architecture. Microsemi RTG4 device has built-in RX clock recovery block with good jitter tolerance for
SpaceWire application. The RX clock recovery block and the FPGA logic element allow easy
implementation for SpaceWire receiver circuit. This application note demonstrates how to use this built-in
RX clock recovery block to recover the SpaceWire clock and to reliably capture the input data. It also
provides two design examples showing SpaceWire transmit and receive block running at 100 and 400
Mbps in the RTG4 ES device at room temperature. The RX clock recovery block running at 400 Mbps in
the RTG4 production (RTG4 PROTO) device at best and worst operating condition will be available in a
future revision of the application note.
March 2016
© 2016 Microsemi Corporation
Revision 2
1
Implementing SpaceWire Clock and Data Recovery in RTG4 FPGAs
References
Internal References
•
UG0574: RTG4 FPGA Fabric User Guide
•
UG0586: RTG4 FPGA Clocking Resources User Guide
•
RTG4 Macro Library User Guide
External References
•
ECSS-E-50-12A standard from European Cooperation for Space Standardization
Design Requirements
Table 1 • Design Requirements
Design Requirements and Details
Description
Hardware Requirements
–
RTG4 Development Kit:
•
RTG4 Development Board with one RT4G150
device in a ceramic package with 1,657 pins
•
12 V adapter (provided along with the kit)
•
FlashPro4 programmer (provided along with the Kit
RTG4 SpaceWire Daughter Card1
–
Host PC or Laptop
Any 64-bit Windows Operating System
Software Requirements
Libero® system-on-chip (SoC)
v11.7
Note: The SpaceWire daughter card is for internal validation only at this time and not available as a standard product.
SpaceWire Coding and Signaling Overview
SpaceWire is a high-speed data link standard that provides a unified, high-speed data-handling
infrastructure for connecting sensors, processing elements, mass memory units, downlink telemetry
subsystems, and electrical ground support equipment (EGSE). SpaceWire links operate from 2 Mbps to
400 Mbps over a full-duplex, point-to-point serial link. SpaceWire uses DS encoding scheme, where data
(D) signal follows the data bitstream; that is, high when the data bit is 1 and low when the data bit is 0.
The strobe (S) signal changes state whenever the data does not change from one bit to the next. This
coding scheme is illustrated in Figure 1 on page 3. The DS encoding and SpaceWire standard is
described in ECSS-E-50-12A standard from European Cooperation for Space Standardization. The DS
encoding scheme is also used in the IEEE Standard 1355--1995 [1] and IEEE 1394--1995 (Firewire)
Standard [6].
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Implementing SpaceWire Clock and Data Recovery in RTG4 FPGAs
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Figure 1 • DS Encoding
The SpaceWire uses low voltage differential signaling (LVDS) for the D and S signals. LVDS employs
balanced signals to provide very high-speed interconnection using a low voltage swing of 350 mV typical.
The signaling levels used by LVDS are shown in Figure 2. Generally, a SpaceWire link comprises two
pairs of differential signals, one pair transmitting the D and S signals in one direction and the other pair
transmitting D and S in the opposite direction.
Figure 2 • SpaceWire LVDS Signaling Levels
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Implementing SpaceWire Clock and Data Recovery in RTG4 FPGAs
SpaceWire Clock and Data Recovery
SpaceWire interface can be implemented in generic architecture FPGAs; however, the SpaceWire clock
recovery circuitry design at the receiver side, presents serious challenges specific to the FPGA device
architecture. A first real challenge is related to the tight timing constraints required between data and
strobe signals to generate a glitchfree and good jitter tolerance recovered clock. An additional challenge
is caused by the fact that received data are in the clock domain of the remote SpaceWire transmitter and
must be re-timed to the recovered clock. Figure 3 shows the logic scheme for clock and data recovery.
The SpaceWire clock is recovered by Xor-ing D and S signals. The data signal is recovered by sampling
the D input on both edges of the recovered clock. In addition, the capture data is re-timed to the
recovered clock domain to avoid any meta-stability issue.
Figure 3 • SpaceWire Clock and Data Recovery Logic
When implementing the SpaceWire clock and data recovery block, the following cases must be
considered:
4
•
Case1: S change, D stable
•
Case2: D change, S stable
•
Case3: S change to next S change, D stable
•
Case4: D change to next D change, S stable
Revision 2
Implementing SpaceWire Clock and Data Recovery in RTG4 FPGAs
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Figure 4 • SpaceWire Data and Strobe with Clock Recovery Scenario
To ensure proper operation of the SpaceWire clock recovery circuitry, user must comply with the
following:
1. When data is changing, the data event arrives before the clock edge. This ensures that the
correct data value is sampled.
Longest (D ---> Capture_FF*:D) < Shortest (D ---> Capture_FF*:CK) - Setup (FF)
EQ 1
2. When strobe is changing, a strobe event is not generating a clock edge that captures the wrong
data
Bit_Period + Shortest (D ---> Capture_FF*:D) > Longest (S ---> Capture_FF*:CK)…….
EQ 2
The RTG4 device has the hardened RX clock recovery blocks that allow easy implementation of the
SpaceWire clock recovery with a good jitter tolerance. In addition, the RTG4 architecture allows
hardwired path for SpaceWire data input to a flip-flop (IO-FF) to capture the incoming data. The I/Os
include a programmable input delay setting that allows users to control the SpaceWire data path delay
and easily meet EQ 1 and EQ 2 requirement.
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Implementing SpaceWire Clock and Data Recovery in RTG4 FPGAs
The following sections describe implementing the RX clock and data recovery block in RTG4 detail:
RTG4 SpaceWire Clock Recovery Block Overview
The RTG4 device has hardened RX clock recovery blocks, which reside in the clock conditioning circuits
(CCCs). There are two blocks of RX clock recovery in each CCC block, as shown in Figure 5. Each RX
Clock recovery block has its own MUXing logic to select two inputs for data and strobe. The data input is
also passed on to the FPGA fabric for SpaceWire receiver and other SpaceWire protocol implementation.
Figure 5 • RTG4 SpaceWire RX Clock Recovery Block in CCC
Figure 6 shows detail implementation of the RX clock recovery block in RTG4, which includes the XOR
logic. The RX clock recovery block includes de-glitching circuit to prevent any unwanted narrow clock
pulse at output. The de-glitching circuit includes delay setting that is used to add optional filtering to filter
either single event transient (SET) or system-level glitches. Enabling the delay is done globally through
an option that is available in the Libero SoC software. The generated RX clock is radiation hardened and
drives the hardened global clock network.
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Revision 2
Implementing SpaceWire Clock and Data Recovery in RTG4 FPGAs
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Implementing SpaceWire Clock and Data Recovery in RTG4 FPGAs
The two inputs for data and strobe dedicated input pads can be configured to use either single ended or
differential I/O standards. RTG4 device has up to 16 sets of SpaceWire input signals (16 pair of data and
strobe). Table 2 shows the SpaceWire pins in the RTG4 device. Note that when data and strobe
dedicated input pads are configured as single-ended I/O, only the P pins are used.
Table 2 • SpaceWire Pins in RTG4 device
Port
Direction
Description
SPWR_xyz_w_RX_STROBE_[P/N]
Input
Differential Input Strobe signal from I/O pad
SPWR_xyz_w_RX_DATA_[P/N]
Input
Differential Input Data signal from I/O pad
Notes:
1. xy represents individual SpaceWire block located at specific chip corner—NE, SE, SW, or NW.
2. z is CCC number of either 0 or 1 for the corresponding corner of the RTG4 chip.
3. w refers to one of the two possible input pins associated with SPWR_xyz_[0,1].
The RTG4 ES devices only support up to 12 sets of SpaceWire data and strobe input pins while the
production devices support up to 16 sets of SpaceWire data and strobe input pins (12 sets in MSIOD and
4 sets in DDRIO banks) to implement SpaceWire data and clock recovery block. MSIOD bank supports
true LVDS, but DDRIO bank does not support true LVDS. So, the user needs to implement pseudo-LVDS
or other techniques to use those I/Os. In addition, the SpaceWire data and clock placed in DDRIO bank
have limited performance compared to the SpaceWire data and clock placed in DDRIO bank.
Future version of the application note and data will have more info. Note that some of the pin
assignments are changing in the production devices. Refer to SpaceWire Pin Mapping from RTG4
ES/MS Silicon to PROTO/Flight Silicon for more information.
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Implementing SpaceWire Clock and Data Recovery in RTG4 FPGAs
Using RTG4 SpaceWire Clock Recovery Block
This section explains how to use the RTG4 SpaceWire RX clock recovery block in the design. Designers
need to use the RTG4 CCC configurator in the Libero SoC software to configure the RX clock recovery
block. The RX clock recovery block generates the RX clock that can drive anyone of the global outputs.
The following steps describe how to configure the RTG4 SpaceWire Clock Recovery block, design flow
proceeds from right to left in the GUI:
1. Open the RTG4 CCC configurator and click the Advanced tab, as shown in Figure 7.
Figure 7 • SpaceWire RX Clock Recovery Block Selection in CCC Configurator
2. Select the desired output clocks from the four different global clocks—GL0, GL1, GL2, and GL3.
In addition, user can also select four core clocks—Y0, Y1, Y2, and Y3. However, Microsemi
recommends to select the global clock when implementing the SpaceWire RX clock recovery
block.
3. For each selected output clock, select the reference input clock from which the output is
derived—RX0 Clock Recovery or RX1 Clock Recovery.
4. Select the data pad as CLK_PAD1 or CLK_PAD3. The strobe pad is automatically selected.
5. Click OK to generate the RTG4 CCC configurator.
The dedicated input pad for data and strobe can also be configured as either single ended or differential
I/O standard. For differential option, selecting one dedicated pad for the data signal automatically selects
the corresponding pad as it is a pair of P and N pads. Refer to the RTG4 Clock Conditioning Circuit with
PLL Configuration for more information on the RX clock recovery options.
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Implementing SpaceWire Clock and Data Recovery in RTG4 FPGAs
Implementing the RTG4 Data Recovery Block
Implementing the SpaceWire receiver requires the arrival of data event before the clock edge generated
from the same data and a strobe events, to prevent incorrect capture of data, as shown in EQ 1 and
EQ 2. Figure 8 shows a basic SpaceWire data recovery block implementation in the RTG4 device. Users
need to use the hardened RX clock recovery block to recover the clock and DDR_IN macro to capture
the data on both the rising and falling edges. User can use the recovered clock and recovered data to
implement the rest of the SpaceWire receiver logic. The clock and data recovery block uses hardwired
delay and the delay from the data and strobe input to clock generation is almost the same. It guaranties
that EQ 2 is always satisfied and users just need to ensure EQ 1 is satisfied. Users may need to use the
I/O delay settings to satisfy EQ 1, as described in "I/O Delay Adjustment" section on page 12.
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Figure 10 and Figure 11 show data Recovery block and waveforms with the added registers to recover
the original data.
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Implementing SpaceWire Clock and Data Recovery in RTG4 FPGAs
I/O Delay Adjustment
The RTG4 ES device has up to 12 sets of SpaceWire data and strobe input signals. Since the SpaceWire
links can operate from 2 Mbps to 400 Mbps, users may need to adjust the I/O delay so that the clock
samples the correct data. For 100 Mbps design, users do not need to adjust the I/O delay as the recovery
clock arrives after the data arrives the DDR_IN register. For 400 Mbps design, users need to compute the
data path and clock path delay and use recovery clock period (rx_clk_prd) to choose the design
approach. Figure 12 shows the I/O delay calculation. In addition, if the strobe signal is arriving before the
first data is sent, designers can latch the data in DDR_IN using the previous edge. Figure 13 on page 13
shows the waveform for this implementation.
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Figure 13 • SpaceWire Data Recovery using Alternative Method
Note: The RTG4 device supports glitch filter up to 400 ps. The skew between data and strobe cannot be
above 400 ps.
Timing Analysis of RTG4 Data Recovery Block
SpaceWire uses a DS encoding scheme that encodes the transmission clock with the data into data and
strobe. The clock is recovered by xor-ing the data and strobe lines together and is used to capture the
data input. To ensure proper operation of the SpaceWire clock recovery circuit, the launch and capture of
data must be on the same clock edge. Figure 14 shows a typical single clock cycle path setup and hold
check window.
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Figure 15 shows the SpaceWire cycle path setup and hold check window.
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Implementing SpaceWire Clock and Data Recovery in RTG4 FPGAs
To run timing analysis on the SpaceWire data and clock recovery block for ES silicon, users need to
apply the following sdc constraints prior of running timing analysis.
Note: The SDC example uses SpaceWire recovery clock of 100 MHz.
#SpaceWire clock and data recovery block constrain file
set spwr_clock_frequency 200
set clock_period 5
set half_clock_period 2.5
#Clock Constraints
# Define clock constraint on STROBE PIN
create_clock -name { CLK0_SPWR_STROBE_PADP } -period 5 \
-waveform { 0.000 2.5 } { CLK0_SPWR_STROBE_PADP }
create_clock -name { CLK0_SPWR_STROBE_PADN } -period 5 \
-waveform { 2.5 0.000 } { CLK0_SPWR_STROBE_PADN }
#Input Delay Constraints
# Identify clock associated with the DATA pins
set_input_delay
[get_ports {
set_input_delay
[get_ports {
0.00 -clock { CLK0_SPWR_STROBE_PADP } \
CLK1_SPWR_DATA_PADN CLK1_SPWR_DATA_PADP }]
0.00 -clock { CLK0_SPWR_STROBE_PADN } \
CLK1_SPWR_DATA_PADN CLK1_SPWR_DATA_PADP }]
#Max / Min Delay Constraints
# Max Delay = 0
set_max_delay 0.0 -from \
[get_ports { CLK1_SPWR_DATA_PADN CLK1_SPWR_DATA_PADP }]
# Min Delay = -(Clock Period/2)
set_min_delay -2.5 -from \
[get_ports { CLK1_SPWR_DATA_PADN CLK1_SPWR_DATA_PADP }]
Design Examples
This application note provides two design examples:
•
Design1 - Shows RTG4 SpaceWire RX Clock Recovery block running at 100 Mbps.
•
Design2 - Shows RTG4 SpaceWire RX Clock Recovery block running at 400 Mbps.
These designs have SpaceWire signal generator that generates the SpaceWire data and strobe. The
SpaceWire signals are loop back using a SpaceWire daughter card. The RX clock recovery block uses
the transmitted SpaceWire signals and generates the clock. This clock is used to sample the incoming
data. This sampled data is verified against the expected data.
Figure 16 on page 15 shows the top-level block diagram. The top-level design example includes the
following
sub-blocks:
14
•
SpaceWire data and strobe generation block: Generates SpaceWire data and strobe signals.
The data is a counter pattern. A CCC is used to generate data at the desired rates. Also, it
includes a switch sync and register block sub-block, that synchronizes the DIP switch inputs and
configures the register block to send control signals to SpaceWire data and strobe generation
block.
•
SpaceWire clock and data recovery: This block includes the SpaceWire RX clock recovery
block to generate the SpaceWire clock from the SpaceWire signals. Also, it samples the incoming
data using SpaceWire recovered clock.
•
SpaceWire recovery data verification block: This block compares the sampled incoming data
against the expected SpaceWire data.
•
Counter: A 28-bit counter clocked by the SpaceWire recovered clock.
Revision 2
Implementing SpaceWire Clock and Data Recovery in RTG4 FPGAs
Figure 16 • Top-Level Block Diagram
Table 3 shows the top-level interface signals.
Table 3 • Top-Level Interface Signals
Signal
Direction
Description
CLK0_SPWR_STROBE_PADP
Input
Differential Input Strobe signal from I/O pad (PADP)
CLK0_SPWR_STROBE_PADN
Input
Differential Input Strobe signal from I/O pad (PADN)
CLK1_SPWR_DATA_PADP
Input
Differential Input Data signal from I/O pad (PADP)
CLK1_SPWR_DATA_PADN
Input
Differential Input Data signal from I/O pad (PADN)
Cntout
Output
Counter using SpaceWire recovery clock
DATAP
Output
SpaceWire Differential Data output (PADP)
DATAN
Output
SpaceWire Differential Data output (PADN)
STRBP
Output
SpaceWire Differential Strobe output (PADP)
STRBN
Output
SpaceWire Differential Strobe output (PADN)
DEVRST_N
Input
Device reset Input
DIP1
Input
DIP switch1, used to initiate SpaceWire signal counter generation
DIP2
Input
DIP switch2, used to insert error pattern in SpaceWire signal counter
generation
DIP3
Input
DIP switch3, used to insert same data and strobe pattern in
SpaceWire signal
DIP8
Input
DIP switch8, start the APB state machine
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Implementing SpaceWire Clock and Data Recovery in RTG4 FPGAs
Table 3 • Top-Level Interface Signals (continued)
Signal
Direction
Expected_GL0
Output
Description
Expected SpaceWire clock
PADP
Input
Differential clock input space data and strobe generation block
(PADP)
PADN
Input
Differential clock input space data and strobe generation block
(PADN)
Recovered_data
Output
SpaceWire recovery data
rd_err
Output
APB read error
result
Output
Compare SpaceWire recovery data and expected data
Spacewire_GL0
Output
Actual SpaceWire clock
wr_err
Output
APB write error
Simulating the Design
The reference Design1 includes testbench to simulate the design in the Libero SoC software. The
testbench provides the main reference clock for SpaceWire data and strobe generation block. The
testbench also loopbacks the SpaceWire data and strobe signals. The design waits until DIP1 switch
input level is high. Once it is high, it sends SpaceWire data and strobe. The SpaceWire clock and data
recovery block recover the clock and data. The SpaceWire data checking block does the final verification.
Figure 17 • SpaceWire Design1 Simulation Waveform
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Implementing SpaceWire Clock and Data Recovery in RTG4 FPGAs
Running the Design
The following steps describe how to run the design in the RTG4 Development Kit. Design1 and design2
examples use the same steps.
1. Connect the SpaceWire daughter card to the RTG4 Development Kit board.
Figure 18 • RTG4 Development Kit
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Implementing SpaceWire Clock and Data Recovery in RTG4 FPGAs
Figure 19 shows SpaceWire daughter card connected to the RTG4 Development Kit board.
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Figure 19 • RTG4 Development Kit Connected to SpaceWire Daughter Card
2. Open the Spacewire_RTG4 Libero project. Refer to "Appendix: Design and Programming Files"
on page 20.
3. Connect the RTG4 Development Kit to the PC using FlashPro4.
4. Connect the Power supply to the J9 connector.
5. Switch ON the power supply switch, SW6.
6. Select Run PROGRAM Action in the Libero Design Flow window to program the RTG4 device.
7. After successful programming, Switch ON the DIP1 switch and power cycle the board. A counter
pattern on LED1-4 is displayed. Power cycle the device after programming successfully.
8. LED8 is high when the data compare is passing.
9. Switch ON the DIP2 switch to introduce error in data pattern and power cycle the device. An
LED8 flickers as data comparison switches between Pass and Fail.
10. Switch OFF DIP2 switch.
18
Revision 2
Implementing SpaceWire Clock and Data Recovery in RTG4 FPGAs
11. Switch ON DIP3 switch to send same data and strobe signal.
A counter pattern on LED1-4 stops counting as there is no SpaceWire recovered clock.
12. Switch OFF the power supply switch, SW6.
Conclusion
SpaceWire designs can be implemented in the RTG4 device. There are several challenges to implement
SpaceWire designs on general FPGAs. The complex one is the recovery block implementation. The builtin RX clock recovery block in the RTG4 and the fabric architecture allows easy implementation device.
Implementation of the SpaceWire RX clock recovery and data recovery in RTG4 FPGA is explained in
detail and the design examples are provided for reference.
Revision 2
19
Implementing SpaceWire Clock and Data Recovery in RTG4 FPGAs
Appendix: Design and Programming Files
Download the RTG4 SpaceWire design files from the Microsemi Corporation website:
http://soc.microsemi.com/download/rsc/?f=rt4g_ac444_spacewire_liberov11p7_df. The RTG4 design file
consists of a Libero Verilog project and programming files (*.stp) for the RTG4 Development Kit. Refer
to the Readme.txt file included in the design file folder for the directory structure and description.
20
Revision 2
Implementing SpaceWire Clock and Data Recovery in RTG4 FPGAs
List of Changes
The following table shows important changes made in this document for each revision.
Date
Changes
Page
Revision 2
(April 2016)
Updated the document for Libero SoC v11.7 software release (SAR 78009).
NA
Revision 1
(October 2015)
Initial release.
NA
Revision 2
21
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