AS5043

AS5043
Programmable 360° Magnetic Angle
Encoder with Absolute SSI and Analog
Outputs
General Description
The AS5043 is a contactless magnetic angle encoder for
accurate measurement up to 360°.
It is a system-on-chip, combining integrated Hall elements,
analog front end and digital signal processing in a single device.
The AS5043 provides a digital 10-bit as well as a programmable
analog output that is directly proportional to the angle of a
magnet, rotating over the chip.
The analog output can be configured in many ways, including
user programmable angular range, adjustable output voltage
range, voltage or current output, etc...
An internal voltage regulator allows operation of the AS5043
from 3.3V or 5.0V supplies.
Ordering Information and Content Guide appear at end of
datasheet.
Key Benefits & Features
The benefits and features of AS5043, Programmable 360°
Magnetic Angle Encoder with Absolute SSI and Analog Outputs
are listed below:
Figure 1:
Added Value of Using AS5043
Benefits
Features
• Highest reliability and durability
• Contactless high resolution rotational position
encoding over a full turn of 360 degrees
• Simple programming
• Simple user-programmable zero position
• Multiple interfaces
• Serial communication interface (SSI)
• Programmable 10-bit analog output
• Ideal for robotic and motor applications
• Input mode for optimizing noise vs. speed
• Failure diagnostics
• Failure detection mode for magnet placement
monitoring and loss of power supply
• Easy setup
• Serial read-out of multiple interconnected AS5043
devices using Daisy Chain mode
• Small form factor
• SSOP 16 (5.3mm x 6.2mm)
• Robust environmental tolerance
• Wide temperature range: -40°C to 125°C
ams Datasheet
[v1-83] 2017-Jul-18
Page 1
Document Feedback
AS5043 − General Description
Applications
AS5043, Programmable 360° Magnetic Angle Encoder with
Absolute SSI and Analog Outputs is ideal for applications with
an angular travel range from a few degrees up to a full turn of
360°, such as:
• Industrial applications:
• Contactless rotary position sensing
• Robotics
• Valve controls
• Automotive applications:
• Throttle position sensors
• Gas/brake pedal position sensing
• Headlight position control
• Front panel rotary switches
• Replacement of potentiometers
Figure 2:
Typical Arrangement of AS5043 and Magnet
Page 2
Document Feedback
ams Datasheet
[v1-83] 2017-Jul-18
AS5043 − General Description
Block Diagram
The functional blocks of this device are shown below:
Figure 3:
AS5043 Block Diagram
MagRNGn
Mode
Sin
DSP
Hall Array
&
Frontend
Amplifier
Cos
DO
Absolute
Interface
(SSI)
CSn
CLK
OTP
Register
DACref
FB
10
Programming
Parameters
Vout
10bit
DAC
+
DACout
Prog_DI
ams Datasheet
[v1-83] 2017-Jul-18
Page 3
Document Feedback
AS5043 − Pin Assignment
Pin Assignment
Figure 4:
AS5043 Pin Configuration SSOP16
MagRngn
1
16
VDD5V
Mode
2
15
VDD3V3
CSn
3
14
NC
CLK
4
13
NC
NC
5
12
Vout
DO
6
11
FB
VSS
7
10
DACout
Prog_DI
8
9
DACref
Package = SSOP16 (16 lead Shrink Small Outline Package)
Figure 5:
Pin Description SSOP16
Pin
Symbol
Type
1
MagRngn
DO_OD
Magnet Field Magnitude RaNGe warning; active low, indicates
that the magnetic field strength is outside of the recommended
limits.
2
Mode
DI_PD, ST
Mode input. Select between low noise (low, connect to VSS) and
high speed (high, connect to VDD5V) mode at power up. Internal
pull-down resistor.
3
CSn
DI_PU, ST
Chip Select, active low; Schmitt-Trigger input, internal pull-up
resistor (~50kΩ)
4
CLK
DI,ST
5
NC
-
6
DO
DO_T
7
VSS
S
8
Prog_DI
DI_PD
9
DACref
AI
DAC Reference voltage input for external reference
10
DACout
AO
DAC output (unbuffered, Ri ~8kΩ)
11
FB
AI
Feedback, OPAMP inverting input
Page 4
Document Feedback
Description
Clock Input of Synchronous Serial Interface; Schmitt-Trigger input
Must be left unconnected
Data Output of Synchronous Serial Interface
Negative Supply Voltage (GND)
OTP Programming Input and Data Input for Daisy Chain mode.
Internal pull-down resistor (~74kΩ).
Should be connected to VSS if programming is not used
ams Datasheet
[v1-83] 2017-Jul-18
AS5043 − Pin Assignment
Pin
Symbol
Type
Description
12
Vout
AO
OPAMP output
13
NC
-
Must be left unconnected
14
NC
-
Must be left unconnected
15
VDD3V3
S
3V-Regulator Output for internal core, regulated from
VDD5V.Connect to VDD5V for 3V supply voltage. Do not load
externally.
16
VDD5V
S
Positive Supply Voltage, 3.0 to 5.5 V
Abbreviations for Pin Types in Figure 5:
DO_OD
: Digital output open drain
DI_PD
: Digital input pull-down
DI_PU
: Digital input pull-up
S
: Supply pin
DO_T
: Digital output /tri-state
ST
: Schmitt-Trigger input
AI
: Analog input
AO
: Analog output
D1
: Digital input
Pin Description
Pins 7, 15 and 16 are supply pins, pins 5, 13 and 14 are for
internal use and must be left open.
Pin 1 is the magnetic field strength indicator, MagRNGn. It is
an open-drain output that is pulled to VSS when the magnetic
field is out of the recommended range (45mT to 75mT). The chip
will still continue to operate, but with reduced performance,
when the magnetic field is out of range. When this pin is low,
the analog output at pins #10 and #12 will be 0V to indicate the
out-of-range condition.
Pin 2 MODE allows switching between filtered (slow) and
unfiltered (fast mode). This pin must be tied to VSS or VDD5V,
and must not be switched after power up.
Pin 3 Chip Select (CSn; active low) selects a device for serial
data transmission over the SSI interface. A “logic high” at CSn
forces output DO to digital tri-state.
Pin 4 CLK is the clock input for serial data transmission over the
SSI interface.
ams Datasheet
[v1-83] 2017-Jul-18
Page 5
Document Feedback
AS5043 − Pin Assignment
Pin 6 DO (Data Out) is the serial data output during data
transmission over the SSI interface.
Pin 8 PROG_DI is used to program the different operation
modes, as well as the zero-position in the OTP register.
This pin is also used as a digital input to shift serial data through
the device in Daisy Chain Mode.
Pin 9 DACref is the external voltage reference input for the
Digital-to-Analog Converter (DAC). If selected, the analog
output voltage on pin 12 (Vout) will be ratiometric to the voltage
on this pin.
Pin10 DACout is the unbuffered output of the DAC. This pin
may be used to connect an external OPAMP, etc. to the DAC.
Pin 11 FB (Feedback) is the inverting input of the OPAMP buffer
stage.
Access to this pin allows various OPAMP configurations.
Pin 12 Vout is the analog output pin. The analog output is a DC
voltage, ratiometric to VDD5V (3.0 – 5.5V) or an external voltage
source and proportional to the angle.
Page 6
Document Feedback
ams Datasheet
[v1-83] 2017-Jul-18
AS5043 − Absolute Maximum Ratings
Absolute Maximum Ratings
Stresses beyond those listed in Absolute Maximum Ratings
may cause permanent damage to the device. These are stress
ratings only. Functional operation of the device at these or any
other conditions beyond those indicated in Operating
Conditions is not implied. Exposure to absolute maximum
rating conditions for extended periods may affect device
reliability.
Figure 6:
Absolute Maximum Ratings
Symbol
VDD5V
VDD3V3
Vin
Parameter
DC supply voltage at pin
VDD5V
Input pin voltage
Iscr
Input current
(latchup immunity)
ESD
Electrostatic discharge
Tstrg
Storage temperature
TBody
Body temperature
RHNC
Relative humidity
(non condensing)
MSL
Moisture sensitivity level
ams Datasheet
[v1-83] 2017-Jul-18
Min
Max
Units
-0.3
7
V
Pin VDD5V
5
V
Pin VDD3V3
-0.3
VDD5V +0.3
-0.3
5
-0.3
7.5
-100
100
5
3
Pins MagRngn, Mode, CSn, CLK,
DO, DACout, FB, Vout
V
Pin DACref
Pin PROG_DI
mA
JEDEC 78
kV
MIL 883 E method 3015
125
ºC
Min – 67°F; Max 257°F
260
ºC
t=20s to 40s, IPC/JEDEC
J-Std-020C
Lead finish 100% Sn “matte tin”
85
%
±2
-55
Note
Maximum floor life time of 168h
Page 7
Document Feedback
AS5043 − Electrical Characteristics
Electrical Characteristics
Operating Conditions
Figure 7:
Operating Conditions
Symbol
Parameter
Min
Tamb
Ambient temperature
-40
Isupp
Supply current
VDD5V
Supply voltage at pin VDD5V
Typ
Max
Unit
125
°C
16
21
mA
4.5
5.0
5.5
V
Note
-40°F to 257°F
5V operation
VDD3V3
Voltage regulator output
voltage at pin VDD3V3
3.0
3.3
3.6
V
VDD5V
Supply voltage at pin VDD5V
3.0
3.3
3.6
V
VDD3V3
Supply voltage at pin VDD3V3
3.0
3.3
3.6
V
3.3V operation (pins VDD5V
and VDD3V3 connected)
DC Characteristics for Digital Inputs and
Outputs
CMOS Schmitt-Trigger Inputs: CLK, CSn (Internal
Pull-Up), Mode (Internal Pull-Down)
(operating conditions: Tamb = -40°C to 125°C, VDD5V = 3.0V to
3.6V (3V operation) VDD5V = 4.5V to 5.5V (5V operation) unless
otherwise noted)
Figure 8:
CMOS Schmitt-Trigger Inputs: CLK, CSn (CSn = Internal Pull-Up), Mode (Internal Pull-Down)
Symbol
Parameter
VIH
High level input voltage
VIL
Low level input voltage
VIon-VIoff
ILEAK
IiL
IiH
Min
Max
0.7 * VDD5V
V
0.3 * VDD5V
Schmitt Trigger hysteresis
1
Input leakage current
-1
1
-30
30
-100
100
Page 8
Document Feedback
Note
Normal operation
V
V
Pull-up low level input current
Pull-down high level input
current
Unit
Pin CLK,
VDD5V = 5.0V
μA
Pin CSn,
VDD5V= 5.0V
Pin Mode,
VDD5V= 5.0V
ams Datasheet
[v1-83] 2017-Jul-18
AS5043 − Electrical Characteristics
CMOS Input: Program Input (Prog)
(operating conditions: Tamb = -40°C to 125°C, VDD5V = 3.0V to
3.6V (3V operation) VDD5V = 4.5V to 5.5V (5V operation) unless
otherwise noted)
Figure 9:
CMOS Input: Program Input (Prog)
Symbol
Parameter
VIH
High level input voltage
VPROG
High level input voltage
VIL
Low level input voltage
IiL
Pull-down high level input
current
Min
Max
Unit
0.7 * VDD5V
5
V
See Programming
Conditions
V
0.3 * VDD5V
V
100
μA
Note
During
programming
VDD5V: 5.5V
CMOS Output Open Drain: MagRngn
(operating conditions: Tamb = -40°C to 125°C, VDD5V = 3.0V to
3.6V (3V operation) VDD5V = 4.5V to 5.5V (5V operation) unless
otherwise noted).
Figure 10:
CMOS Output Open Drain: MagRngn
Symbol
VOL
Parameter
Low level output voltage
Min
Max
Unit
VSS+0.4
V
IO
Output current
4
2
mA
IOZ
Open drain leakage current
1
μA
ams Datasheet
[v1-83] 2017-Jul-18
Note
VDD5V: 4.5V
VDD5V: 3V
Page 9
Document Feedback
AS5043 − Electrical Characteristics
Tristate CMOS Output: DO
(operating conditions: Tamb = -40°C to 125°C, VDD5V = 3.0V to
3.6V (3V operation) VDD5V = 4.5V to 5.5V (5V operation) unless
otherwise noted).
Figure 11:
Tristate CMOS Output: DO
Symbol
Parameter
VOH
High level output voltage
VOL
Low level output voltage
Min
Max
VDD5V-0.5
Unit
Note
V
VSS+0.4
V
IO
Output current
4
2
mA
IOZ
Tri-state leakage current
1
μA
VDD5V: 4.5V
VDD5V: 3V
Digital-to-Analog Converter
Figure 12:
Digital-to-Analog Converter
Symbol
Parameter
Min
Resolution
VOUTM1
Output range
VOUTM2
ROut,DAC
Vref
Max
10
Unit
Note
bit
Vref
V
0% …100% Vref
(default)
ClampMdEn = 0
(default)
0.10
*Vref
0.90
*Vref
V
10% …90% Vref
ClampMdEn = 1
8
kΩ
Unbuffered Pin
DACout (#10)
VDD3V3
- 0.2
V
DAC reference =
external: Pin:
DACref (#9)
RefExt EN = 1
VDD5V /
2
V
DAC reference =
internal
RefExtEn = 0 (default)
0.2
INLDAC
Integral
non-linearity
±1.5
LSB
DNLDAC
Differential
non-linearity
±0.5
LSB
1
LSB
All analog modes
2
LSB
At 360°-0°
transition, 360°
mode only
Hyst
Analog
output
hysteresis
Page 10
Document Feedback
OTP Setting
0
Output
resistance
DAC
reference
voltage (DAC
full scale
range)
Typ
Non-Linearity of
DAC and OPAMP;
-40°C to 125°C,
for all analog
modes: 1LSB =
Vref / 1024
OR1,OR0 = 00 (default)
ams Datasheet
[v1-83] 2017-Jul-18
AS5043 − Electrical Characteristics
OPAMP Output Stage
Figure 13:
OPAMP Output Stage
Symbol
Parameter
Min
VDD5V
Power Supply
Range
3.0
CL
Parallel Load
Capacitance
RL
Parallel Load
Resistance
4.7
A0
Open Loop Gain
92
VosOP
Offset Voltage RTI
-5
VoutL
Output Range Low
Typ
Max
Unit
5.5
V
100
pF
kΩ
130
144
dB
5
mV
0.05 *
VDD5V
V
Note
3.3V operation
3 sigma
Linear range of analog
output
VoutH
Output Range High
0.95 *
VDD5V
Isink
Current capability
sink
4.8
50
mA
Permanent short circuit
current: Vout to VDD5V
Isource
Current capability
source
4.6
66
mA
Permanent short circuit
current: Vout to VSS
Vnoise
Output noise
160
V
220
490
2
Gain
ams Datasheet
[v1-83] 2017-Jul-18
OPAMP gain
(non-inverting)
1
μVrms
Over full temperature
range;
BW= 1Hz …10MHz,
Gain = 2x
Internal; OTP: FB_int EN = 1
4
External OTP: FB_int EN = 0
(default) With external
resistors, pins Vout [#12]
and FB [#11]:
see Figure 33
Page 11
Document Feedback
AS5043 − Electrical Characteristics
Magnetic Input Specification
(operating conditions: Tamb = -40°C to 125°C, VDD5V = 3.0V to
3.6V (3V operation) VDD5V = 4.5V to 5.5V (5V operation) unless
otherwise noted).
Two-pole cylindrical diametrically magnetized source:
Figure 14:
Magnetic Input Specification
Symbol
Parameter
Min
Typ
6
dmag
Diameter
4
tmag
Thickness
2.5
Bpk
Magnetic input
field amplitude
Boff
Magnetic offset
45
fmag_abs
Disp
Input frequency
(rotational speed
of magnet)
Displacement
radius
Recommended
magnet material
and temperature
drift
Page 12
Document Feedback
Unit
mm
mm
Field non-linearity
fmag_inc
Max
Note
Recommended magnet: Ø 6mm x
2.5mm for cylindrical magnets
75
mT
Required vertical component of the
magnetic field strength on the die’s
surface, measured along a concentric
circle with a radius of 1.1mm
± 10
mT
Constant magnetic stray field
5
%
Including offset gradient
10
Hz
Absolute mode: 600 rpm @ readout of
1024 positions (see Figure 48)
166
Hz
Incremental mode: no missing pulses
at rotational speeds of up to 10,000
rpm (see Figure 48)
0.25
mm
Max. offset between defined device
center and magnet axis
-0.12
NdFeB (Neodymium Iron Boron)
%/K
-0.035
SmCo (Samarium Cobalt)
ams Datasheet
[v1-83] 2017-Jul-18
AS5043 − Electrical Characteristics
Electrical System Specifications
(operating conditions: Tamb = -40°C to 125°C, VDD5V = 3.0V to
3.6V (3V operation) VDD5V = 4.5V to 5.5V (5V operation) unless
otherwise noted).
Figure 15:
Electrical System Specifications
Symbol
RES
Parameter
Min
Typ
Resolution (1)
INLopt
Integral non-linearity
(optimum)(1)
INLtemp
Integral non-linearity
(optimum) (1)
INL
Integral non-linearity (1)
DNL
Differential non-linearity (1)
Max
Unit
10
bit
0.352 deg
deg
Maximum error with respect to
the best line fit. Verified at
optimum magnet placement,
Tamb =25 °C.
deg
Maximum error with respect to
the best line fit. Verified at
optimum magnet placement,
Tamb = -40°C to 125°C
± 1.4
deg
Best line fit = (Errmax – Errmin) /
2 Over displacement tolerance
with 6mm diameter magnet,
Tamb = -40°C to 125°C
± 0.176
deg
10bit, no missing codes
± 0.5
± 0.9
0.06
TN
deg
RMS
Transition noise (1)
0.03
Note
1 sigma, fast mode
(pin MODE = 1)
1 sigma, slow mode (pin
MODE=0 or open)
Von
Power-ON reset threshold
ON voltage; 300mV typ.
hysteresis
1.37
2.2
2.9
V
DC supply voltage 3.3V
(VDD3V3)
Voff
Power-ON reset threshold
OFF voltage; 300mV typ.
hysteresis
1.08
1.9
2.6
V
DC supply voltage 3.3V
(VDD3V3)
tPwrUp
Power-up time,
Until offset compensation
finished, OCF = 1, Angular
Data valid
tdelay
System propagation delay
absolute output : delay of
ADC and DSP
ams Datasheet
[v1-83] 2017-Jul-18
20
Fast mode (pin MODE=1)
ms
80
Slow mode (pin MODE=0 or
open)
96
Fast mode (pin MODE=1)
μs
384
Slow mode (pin MODE=0 or
open)
Page 13
Document Feedback
AS5043 − Electrical Characteristics
Symbol
fS, mode 0
fS, mode 1
CLK
Parameter
Min
Typ
Max
2.48
2.61
2.74
Internal sampling rate for
absolute output
Note
Tamb = 25°C, slow mode (pin
MODE = 0 or open)
kHz
2.35
2.61
2.87
Tamb = -40°C to 125°C, slow
mode (pin MODE = 0 or open)
9.90
10.4
2
10.94
Tamb = 25°C, fast mode (pin
MODE = 1)
9.38
10.4
2
Internal sampling rate for
absolute output
Read-out frequency
Unit
kHz
>0
Tamb = -40°C to 125°C, fast
mode (pin MODE = 1)
11.46
1
MHz
Max. clock frequency to read
out serial data
Note(s) and/or Footnote(s):
1. Digital interface
Figure 16:
Integral and Differential Non-Linearity Example (exaggerated curve)
1023
D 10bit code
1023
Actual curve
2
TN
1
0
512
Ideal curve
DNL+1LSB
INL
0.35°
512
0
0q
q
360 q
D [degrees]
Integral Non-Linearity (INL) is the maximum deviation between
actual position and indicated position.
Differential Non-Linearity (DNL) is the maximum deviation of
the step length from one position to the next.
Transition Noise (TN) is the repeatability of an indicated
position.
Page 14
Document Feedback
ams Datasheet
[v1-83] 2017-Jul-18
AS5043 − Electrical Characteristics
Timing Characteristics
Synchronous Serial Interface (SSI)
(operating conditions: Tamb = -40°C to 125°C, VDD5V = 3.0V to
3.6V (3V operation) VDD5V = 4.5V to 5.5V (5V operation) unless
otherwise noted).
Figure 17:
Synchronous Serial Interface (SSI)
Symbol
Parameter
t DO active
Data output activated
(logic high)
tCLK FE
First data shifted to
output register
T CLK / 2
Start of data output
t DO valid
Data output valid
t DO tristate
Data output tristate
t CSn
Pulse width of CSn
fCLK
Read-out frequency
ams Datasheet
[v1-83] 2017-Jul-18
Min
Typ
Max
Unit
100
ns
Time between falling edge of CSn
and data output activated
500
ns
Time between falling edge of CSn
and first falling edge of CLK
500
ns
Rising edge of CLK shifts out one bit
at a time
413
ns
Time between rising edge of CLK
and data output valid
100
ns
After the last bit DO changes back to
“tristate”
ns
CSn = high; To initiate read-out of
next angular position
MHz
Clock frequency to read out serial
data
500
>0
1
Note
Page 15
Document Feedback
AS5043 − Electrical Characteristics
Programming Conditions
(operating conditions: Tamb = -40°C to 125°C, VDD5V = 3.0V to
3.6V (3V operation) VDD5V = 4.5V to 5.5V (5V operation) unless
otherwise noted).
Figure 18:
Programming Conditions
Symbol
Parameter
Min
Typ
Max
Unit
Note
Time between rising edge at
Prog pin and rising edge of CSn
Programming enable
time
2
μs
t Data in
Write data start
2
μs
t Data in valid
Write data valid
250
ns
t Load PROG
Load programming
data
3
μs
t PrgR
Rise time of VPROG
before CLKPROG
0
μs
t PrgH
Hold time of VPROG
after CLKPROG
0
t Prog enable
CLK PROG
t PROG
t PROG finished
Write data –
programming CLKPROG
CLK pulse width
Hold time of VPROG
after programming
1.8
2
Write data at the rising edge of
CLKPROG
5
μs
250
kHz
2.2
μs
During programming; 16 clock
cycles
μs
Programmed data is available
after next power-on
7.5
V
Must be switched OFF after
zapping
1
V
Line must be discharged to this
level
2
V PROG
Programming voltage
7.3
V ProgOff
Programming voltage
OFF level
0
I PROG
Programming current
130
mA
During programming
Analog read CLK
100
kHz
Analog readback mode
Programmed Zener
voltage (log.1)
100
mV
VRef-VPROG during analog
readback mode (see Analog
Readback Mode)
CLKAread
Vprogrammed
Vunprogrammed
Unprogrammed Zener
voltage (log. 0)
Page 16
Document Feedback
1
7.4
V
ams Datasheet
[v1-83] 2017-Jul-18
AS5043 − Functional Description
Functional Description
The AS5043 is manufactured in a CMOS standard process and
uses a spinning current Hall technology for sensing the
magnetic field distribution across the surface of the chip.
The integrated Hall elements are placed in a circle around the
center of the device and deliver a voltage representation of the
magnetic field perpendicular to the surface of the IC.
Through Sigma-Delta Analog / Digital Conversion and Digital
Signal-Processing (DSP) algorithms, the AS5043 provides
accurate high-resolution absolute angular position
information. For this purpose a Coordinate Rotation Digital
Computer (CORDIC) calculates the angle and the magnitude of
the Hall array signals.
The DSP is also used indicate movements of the magnet
towards or away from the chip and to indicate, when the
magnetic field is outside of the recommended range
(status bits = MagInc, MagDec; hardware pin = MagRngn).
A small low cost diametrically magnetized (two-pole) standard
magnet, centered over the chip, is used as the input device.
The AS5043 senses the orientation of the magnetic field and
calculates a 10-bit binary code. This code can be accessed via a
Synchronous Serial Interface (SSI). In addition, the absolute
angular representation is converted to an analog signal,
ratiometric to the supply voltage.
The analog output can be configured in many ways, such as
360°/180°/90° or 45° angular range, external or internal DAC
reference voltage, 0-100%*VDD or 10-90% *VDD analog output
range, external or internal amplifier gain setting.
The various output modes as well as a user programmable zero
position can be programmed in an OTP register. As long as no
programming voltage is applied to pin PROG, the new setting
may be overwritten at any time and will be reset to default when
power is cycled. To make the setting permanent, the OTP
register must be programmed by applying a programming
voltage.
The AS5043 is tolerant to magnet misalignment and unwanted
external magnetic fields due to differential measurement
technique and Hall sensor conditioning circuitry.
It is also tolerant to airgap and temperature variations due to
Sin-/Cos- signal evaluation.
ams Datasheet
[v1-83] 2017-Jul-18
Page 17
Document Feedback
AS5043 − 3.3V / 5V Operation
3.3V / 5V Operation
The AS5043 operates either at 3.3V ±10% or at 5V ±10%. This is
made possible by an internal 3.3V Low-Dropout (LDO) Voltage
regulator. The core supply voltage is always taken from the LDO
output, as the internal blocks are always operating at 3.3V.
For 3.3V operation, the LDO must be bypassed by connecting
VDD3V3 with VDD5V (see Figure 19).
For 5V operation, the 5V supply is connected to pin VDD5V,
while VDD3V3 (LDO output) must be buffered by a 1 to10μF
capacitor, which should be placed close to the supply pin.
The VDD3V3 output is intended for internal use only. It should
not be loaded with an external load.
The voltage levels of the digital interface I/O’s correspond to
the voltage at pin VDD5V, as the I/O buffers are supplied from
this pin (see Figure 19).
Figure 19:
Connections for 5V / 3.3V Supply Voltages
A buffer capacitor of 100nF is recommended in both cases close
to pin VDD5V. Note that pin VDD3V3 must always be buffered
by a capacitor. It must not be left floating, as this may cause an
instable internal 3.3V supply voltage which may lead to larger
than normal jitter of the measured angle.
Page 18
Document Feedback
ams Datasheet
[v1-83] 2017-Jul-18
10-Bit Absolute Synchronous
Serial Interface (SSI)
The serial data transmission timing is outlined in Figure 21: if
CSn changes to logic low, Data Out (DO) will change from high
impedance (tri-state) to logic high and the read-out sequence
will be initiated. After a minimum time t CLK FE, data is latched
into the output shift register with the first falling edge of CLK.
Each subsequent rising CLK edge shifts out one bit of data.The
serial word contains 16 bits, the first 10 bits are the angular
information D[9:0], the subsequent 6 bits contain system
information, about the validity of data such as OCF, COF, LIN,
Parity and Magnetic Field status (increase / decrease /
out of range).
A subsequent measurement is initiated by a logic “high” pulse
at CSn with a minimum duration of t CSn. Data transmission
may be terminated at any time by pulling CSn = high.
Serial Data Contents
D9:D0 absolute angular position data (MSB is clocked out first).
OCF (Offset Compensation Finished), logic high indicates that
the Offset Compensation Algorithm has finished and data is
valid.
COF (CORDIC Overflow), logic high indicates an out of range
error in the CORDIC part. When this bit is set, the data at D9:D0
is invalid. The absolute output maintains the last valid angular
value. This alarm may be resolved by bringing the magnet
within the X-Y-Z tolerance limits.
LIN (Linearity Alarm), logic high indicates that the input field
generates a critical output linearity. When this bit is set, the data
at D9:D0 may still be used, but may contain invalid data. This
warning may be resolved by bringing the magnet within the
X-Y-Z tolerance limits.
Data D9:D0 is valid, when the status bits have the following
configurations:
Figure 20:
Status Bit Outputs
OCF
1
COF
0
ams Datasheet
[v1-83] 2017-Jul-18
LIN
0
Mag INC
Mag DEC
0
0
0
1
1
0
Parity
Even checksum of bits 1:15
Page 19
Document Feedback
AS5043 − 10-Bit Absolute Synchronous Serial Inter face (SSI)
MagInc, (Magnitude Increase) becomes HIGH, when the
magnet is pushed towards the IC, thus the magnetic field
strength is increasing.
MagDec, (Magnitude Decrease) becomes HIGH, when the
magnet is pulled away from the IC, thus the magnetic field
strength is decreasing.
Both signals HIGH indicate a magnetic field that is out of the
allowed range (see Figure 22).
Note(s): Pin 1 (MagRngn) is a combination of MagInc and
MagDec. It is active low via an open drain output and requires
an external pull-up resistor. If the magnetic field is in range, this
output is turned OFF. (logic “high”).
Even Parity bit for transmission error detection of bits 1 …15
(D9 …D0, OCF, COF, LIN, MagInc, MagDec)
The absolute angular output is always set to a resolution of 10
bit / 360°. Placing the magnet above the chip, angular values
increase in clockwise direction by default.
Figure 21:
Synchronous Serial Interface with Absolute Angular Position Data
CSn
t CLK FE
T CLK / 2
t CSn
1
CLK
DO
D9
t DO active
Page 20
Document Feedback
t DO valid
8
D8
D7
D6
D5
D4
D3
Angular Position Data
D2
1
16
D1
D0
OCF
COF
LIN
Mag
INC
Status Bits
Mag
DEC
t CLK FE
Even
PAR
D9
t DO Tristate
ams Datasheet
[v1-83] 2017-Jul-18
AS5043 − 10-Bit Absolute Synchronous Serial Interface (SSI)
Z-Axis Range Indication (Push Button Feature,
Red/Yellow/Green Indicator)
The AS5043 provides several options of detecting movement
and distance of the magnet in the vertical (Z-) direction. Signal
indicators MagINC, MagDEC and LIN are available as status bits
in the serial data stream, while MagRngn is an open-drain
output that indicates an out-of range status (On in YELLOW or
RED range). Additionally, the analog output provides a safety
feature in the form that it will be turned OFF when the magnetic
field is too strong or too weak (RED range). The serial data is
always available, the red/yellow/green status is indicated by the
status bits as shown below:
Figure 22:
Magnetic Field Strength Indicators
SSI Status Bits
Hardware Pins
Description
Mag
INC
Mag
DEC
LIN
Mag
Rngn
Analog
Output
0
0
0
OFF
Enabled
No distance change
Magnetic Input Field OK (GREEN range,
~45mT … 75mT)
0
1
0
OFF
Enabled
Distance increase, GREEN range; Pull-function. This
state is dynamic and only active while the magnet is
moving away from the chip.
1
0
0
OFF
Enabled
Distance decrease, GREEN range; Push- function. This
state is dynamic and only active while the magnet is
moving towards the chip.
1
1
0
ON
Enabled
YELLOW Range: Magnetic field is ~ 25mT …45mT or
~75mT …135mT. The AS5043 may still be operated in
this range, but with slightly reduced accuracy.
Disabled
RED Range: Magnetic field is ~<25mT or >~135mT. The
analog output will be turned OFF in this range by
default. It can be enabled permanently by OTP
programming (see Diagnostic Output Mode).
It is still possible to use the absolute serial interface in
the red range, but not recommended.
1
1
ams Datasheet
[v1-83] 2017-Jul-18
1
ON
Page 21
Document Feedback
AS5043 − Mode Input Pin
Mode Input Pin
The absolute angular position is sampled at a rate of 10.4kHz
(t=96μs) in fast mode and at a rate of 2.6kHz (t=384μs) in slow
mode.
These modes are selected by pin MODE (#2) during the power
up of the AS5043. This pin activates or deactivates an internal
filter, which is used to reduce the digital jitter and consequently
the analog output noise.
Activating the filter by pulling Mode = LOW reduces the
transition noise to <0.03° rms. At the same time, the sampling
rate is reduced to 2.6kHz and the signal propagation delay is
increased to 384μs. This mode is recommended for high
precision, low speed and ≤360° applications.
Deactivating the filter by setting Mode = HIGH increases the
sampling rate to 10.4kHz and reduces the signal propagation
delay to 96μs. The transition noise will increase to <0.06° rms.
This mode is recommended for higher speed and
full scale= 360° applications.
Switching the MODE pin affects the following parameters:
Figure 23:
Mode Pin Settings
Parameter
Slow Mode
(Pin MODE = 0)
Fast Mode
(Pin MODE = 1)
Sampling rate
2.61 kHz (383μs)
10.42 kHz (95.9μs)
Transition noise (1 sigma)
≤ 0.03° rms
≤ 0.06° rms
Propagation delay
384μs
96μs
Startup time
20ms
80ms
The MODE pin should be set at power-up. A change of the mode
during operation is not allowed.
Page 22
Document Feedback
ams Datasheet
[v1-83] 2017-Jul-18
AS5043 − Daisy Chain Mode
The Daisy Chain mode allows connection of several AS5043’s
in series, while still keeping just one digital input for data
transfer (see “Data IN” in Figure 24 below). This mode is
accomplished by connecting the data output (DO; pin 9) to the
data input (Prog; pin 8) of the subsequent device. An RC filter
must be implemented between each PROG pin of device n and
DO pin of device n+1, to prevent the encoders to enter the
alignment mode, in case of ESD discharge, long cables, or not
conform signal levels or shape. Using the values R=100R and
C=1nF allow a max. CLK frequency of 1MHz on the whole chain.
The serial data of all connected devices is read from the DO pin
of the first device in the chain. The length of the serial bit stream
increases with every connected device, it is
Daisy Chain Mode
n * (16+1) bits:
e.g. 34 bit for two devices, 51 bit for three devices, etc…
The last data bit of the first device (Parity) is followed by a
dummy bit and the first data bit of the second device (D9), etc…
(see Figure 25).
Figure 24:
Daisy Chain Hardware Configuration
CSn
CSn
CLK
CLK
CLK
CLK
PROG
DO
DI
CSn
CSn
100R
DO
100R
PROG
PROG
GND
GND
GND
MCU
DO
1nF
1nF
AS5043
AS5043
AS5043
Figure 25:
Daisy Chain Data Transfer Timing Diagram
CSn
t C LK F E
T C LK /2
1
C LK
DO
D9
t D O active
t D O valid
8
D8
D7
D6
D5
D4
D3
D2
16
D1
D0
A ngular P osition D ata
COF
LIN
M ag
IN C
S tatus B its
1
ams Datasheet
[v1-83] 2017-Jul-18
OCF
st
D evice
M ag E ve n
DEC PAR
D
1
2
D9
D8
3
D7
A ngular P osition D ata
2 nd D evice
Page 23
Document Feedback
AS5043 − Analog Output
Analog Output
The analog output Vout provides an analog voltage that is
proportional to the angle of the rotating magnet and
ratiometric to the supply voltage VDD5V (max.5.5V). It can
source or sink currents up to ±1mA in normal operation (up to
66mA short circuit current).
The analog output block consists of a digital angular range
selector, a 10-bit Digital-to-Analog converter and an OPAMP
buffer stage (see Figure 33).
The digital range selector allows a preselection of the angular
range for 360°,180°,90° or 45° (see Figure 38). Fine-tuning of the
angular range can be accomplished by adjusting the gain of the
OPAMP buffer stage.
The reference voltage for the Digital-to-Analog converter (DAC)
can be taken internally from VDD5V / 2. In this mode, the output
voltage is ratiometric to the supply voltage.
Alternatively, an external DAC reference can be applied at pin
DACref (#9). In this mode, the analog output is ratiometric to
the external reference voltage.
An ON-chip diagnostic feature turns the analog output OFF in
case of an error (broken supply or magnetic field out of range;
see Figure 22).
The DAC output can be accessed directly at pin #10 DACout.
The addition of an OPAMP to the DAC output allows a variety
of user configurable options, such as variable output voltage
ranges and variable output voltage versus angle response. By
adding an external transistor, the analog voltage output can be
buffered to allow output currents up to hundred milliamperes
or more.
Furthermore, the OPAMP can be configured as constant current
source.
As an OTP option, the DAC can be configured to 2 different
output ranges:
a) 0 to 100% V DACref. The reference point may be either taken
from VDD5V/2 or from the external DACref input. The
0%… 100% range allows easy replacement of potentiometers.
Due to the nature of rail-to-rail outputs, the linearity will
degrade at output voltages that are close to the supply rails.
b) 10%… 90% V DACref. This range allows better linearity, as the
OPAMP is not driven to the rails. Furthermore, this mode allows
failure detection, when the analog output voltage is outside of
the normal operating range of 10%… 90%VDD, as in the case
of broken supply or when the magnetic field is out of range and
the analog output is turned OFF.
Page 24
Document Feedback
ams Datasheet
[v1-83] 2017-Jul-18
AS5043 − Analog Output
Analog Output Voltage Modes
The Analog output voltage modes are programmable by OTP.
Depending on the application, the analog output can be
selected as rail-to-rail output or as clamped output with
10%-90% VDD5V.
The output is ratiometric to the supply voltage (VDD5V), which
can range from 3.0V to 5.5V. If the DAC reference is switched to
an external reference (pin DACref ), the output is ratiometric to
the external reference.
Full Scale Mode
This output mode provides a ratiometric DAC output of (0% to
100%)x Vref 1, amplified by the OPAMP stage (default =internal
2x gain, see Figure 33)
Figure 26:
Analog Output, Full Scale Mode (shown for 360°mode)
Vref
100%
analog
output
voltage
0V
angle
0°
90°
180°
270°
360°
Note(s):
• In real case the output does not reach 100% Vref, because
of saturation effects of the OPAMP output driver
transistors. Figure 26 describes a linear output voltage
from rail to rail (0V to VDD) over 360°.
• See Figure 38 for further angular range programming
options.
ams Datasheet
[v1-83] 2017-Jul-18
Page 25
Document Feedback
AS5043 − Analog Output
Diagnostic Output Mode
Figure 27:
Diagnostic Output Mode
In an error case, the output
voltage is in the grey area
Vref
100%
90%
analog
output
voltage
normal
operating
area
10%
0%
0°
90°
180°
270°
360°
angle
In Diagnostic Output Mode (see Figure 27) the analog output
of the internal DAC ranges from 10% - 90% Vref 1. In an error case,
either when the supply is interrupted or when the magnetic
field is in the “red” range, (see Figure 22) the output is switched
to 0V and thus indicates the error condition.
It is possible to enable the analog output permanently (it will
not be switched OFF even if the magnetic field is out of range).
To enable this feature an OTP bit in the factory setting must be
set. The corresponding bit is FS6. See application note
AS5040-20 (Extended features of OTP programming) for further
details. The application note is available for download at the
ams website.
1. Vref = internal: ½ * VDD5V (pin #16) or external: VDACref (pin#9), depending on Ref_extEN bit in OTP (0=int., 1=ext.)
Page 26
Document Feedback
ams Datasheet
[v1-83] 2017-Jul-18
AS5043 − Analog Output
The analog and digital outputs will have the following
conditions:
Figure 28:
The Analog and Digital Outputs
Status
Normal operation
Magnetic field out of range
DAC Output Voltage
10% - 90% Vref (1)
< 10% Vref (1),
DAC output is switched to 0V
Broken positive power supply
(VOUT pull down resistor at
receiving side)
< 10% VDD (2)
Broken power supply ground
(VOUT pull down resistor at
receiving side)
< 10% VD (2)
Broken positive power supply
(VOUT pull up resistor at
receiving side)
> 90% VDD(2)
Broken power supply ground
(VOUT pull up resistor at
receiving side)
> 90% VDD(2)
SSI Digital Output
#0 - #1023 (0°-360°), MagRngn = 1
#0 - #1023 (0°-360°)
Out of range is signaled in status bits:
MagInc=MagDec=LIN=1, MagRngn= 0
With pull down resistor at DO (receiving
side), all bits read by the SSI will be “0”-s,
indicating a non-valid output
Note(s) and/or Footnote(s):
1. Vref = internal: ½ * VDD5V (pin #16) or external: V DACref (pin#9), depending on Ref_extEN bit in OTP (0=int., 1=ext.).
2. VDD = positive supply voltage at receiving side (3.0 – 5.5V).
ams Datasheet
[v1-83] 2017-Jul-18
Page 27
Document Feedback
AS5043 − Programming the AS5043
Programming the AS5043
After power-on, programming the AS5043 is enabled with the
rising edge of CSn and Prog = logic high. 16 bit configuration
data must be serially shifted into the OTP register via the
Prog-pin. The first “CCW” bit is followed by the zero position
data (MSB first) and the Analog Output Mode setting as shown
in Figure 38. Data must be valid at the rising edge of CLK (see
Figure 29). Following this sequence, the voltage at pin Prog
must be raised to the programming voltage V PROG (see
Figure 29). 16 CLK pulses (t PROG) must be applied to program
the fuses. To exit the programming mode, the chip must be reset
by a power-on-reset. The programmed data is available after
the next power-up.
Note(s): During the programming process, the transitions in
the programming current may cause high voltage spikes
generated by the inductance of the connection cable. To avoid
these spikes and possible damage to the IC, the connection
wires, especially the signals PROG and VSS must be kept as short
as possible. The maximum wire length between the VPROG
switching transistor and pin PROG (see Figure 31) should not
exceed 50mm (2 inches).
To suppress eventual voltage spikes, a 10nF ceramic capacitor
should be connected close to pins PROG and VSS. This capacitor
is only required for programming, it is not required for normal
operation. The clock timing t clk must be selected at a proper
rate to ensure that the signal PROG is stable at the rising edge
of CLK (see Figure 29). Additionally, the programming supply
voltage should be buffered with a 10μF capacitor mounted
close to the switching transistor. This capacitor aids in providing
peak currents during programming. The specified
programming voltage at pin PROG is 7.3 –7.5V (see
Programming Conditions). To compensate for the voltage drop
across the V PROG switching transistor, the applied programming
voltage may be set slightly higher (7.5 - 8.0V, see Figure 31).
OTP Register Contents:
Page 28
Document Feedback
CCW
Counter Clockwise Bit
• ccw=0 – angular value increases in
clockwise direction
• ccw=1 – angular value increases in
counterclockwise direction
Z [9:0]
Programmable Zero / Index Position
FB_intEN
OPAMP gain setting: 0=external, 1=internal
RefExtEN
DAC reference: 0=internal, 1=external
ClampMd EN
Analog output span: 0=0-100%,
1=10-90%*VDD
Output Range
(OR0, OR1)
[1:0]
Analog Output Range Selection
00 = 360°; 01 = 180°; 10 = 90°; 11 = 45°
ams Datasheet
[v1-83] 2017-Jul-18
AS5043 − Programming the AS5043
Figure 29:
Programming Access – OTP Write Cycle
CSn
tDatain
Prog
CCW
Z9
Z8
Z7
Z6
Z5
1
CLKPROG
tProg enable
Z4
Z3
Z2
Z1
Z0
FB_int
EN
RefExt
EN
Clamp
Md En
Output
Range1
Output
Range0
8
tDatain valid
16
tclk
see text
Analog Modes
Zero Position
Figure 30:
Complete OTP Programming Sequence
Write Data
Programming Mode
Power Off
CSn
Prog
7.5V
VDD
VProgOff
0V
Data
1
16
CLKPROG
tLoad PROG
ams Datasheet
[v1-83] 2017-Jul-18
tPrgH
tPrgR
tPROG
tPROG finished
Page 29
Document Feedback
AS5043 − Programming the AS5043
USB
Figure 31:
OTP Programming Hardware Connection of AS5043 (shown with AS5043 demoboard)
Zero Position Programming
The AS5043 allows easy assembly of the system, as the actual
angle of the magnet does not need to be considered. By OTP
programming, any position can be assigned as the new
permanent zero position with an accuracy of 0.35° (all modes).
Using the same procedure, the AS5043 can be calibrated to
assign a given output voltage to a given angle. With this
approach, all offset errors (DAC + OPAMP) are also compensated
for the calibrated position.
Essentially, for a given mechanical position, the angular
measurement system is electrically rotated (by changing the
Zero Position value in the OTP register), until the output
matches the desired mechanical position.
The example in Figure 32 below shows a configuration for 5V
supply voltage and 10%-90% output voltage range. It adjusted
by Zero Position Programming to provide an analog output
voltage of 2.0 Volts at an angle of 180°. The slope of the curve
may be further adjusted by changing the gain of the OPAMP
output stage and by selecting the desired angular range
(360°/180°/90°/45°).
Page 30
Document Feedback
ams Datasheet
[v1-83] 2017-Jul-18
AS5043 − Programming the AS5043
Figure 32:
Zero Position Programming (shown for 360° mode)
VDD5V
5V
analog
output
voltage
the output can be electrically rotated to
match a given output voltage to any
mechanical position
2V
0V
0°
90°
180°
270°
Mechanical
360° angle
Analog Mode Programming
The analog output can be configured in many ways: It consists
of three major building blocks,
• A digital range preselector,
• A 10-bit Digital-to-Analog-Converter (DAC),
• An OP-AMP buffer stage.
In the default configuration (all OTP bits = 0), the analog
output is set for 360° operation, internal DAC reference
(VDD5V/2), external OPAMP gain, 0-100% ratiometric to VDD5V.
Shown below is a typical example for a 0°-360° range, 0-5V
output. The complete application requires only one external
component, a buffer capacitor at VDD3V3 and has only 3
connections VDD, VSS and Vout (connectors 1-3).
Note(s): The default setting for the OPAMP feedback path
is:FB_intEn=0=external. The external resistors Rf and Rg must be
installed. In the programmed state (FB_intEn=1=internal), these
resistors do not need to be installed as the feedback path is internal
(Rf_int and Rg_int).
ams Datasheet
[v1-83] 2017-Jul-18
Page 31
Document Feedback
AS5043 − Programming the AS5043
Figure 33:
Analog Output Block Diagram
Magnetic field range alarm. Active
lo . Leave open or connect to
VSS if not used
Mode pin.
Default = open
( low noise)
1
AS 5043
External DAC reference pin.
Leave open or connect to
VSS if not used
VDD5V
15
LDO
3.3V
REF_extEN
VDD3V3
+
1=ext
0
0
1
1
OR1
fro
DSP
360°
180°
90°
45°
1-10µF
VDD5 V / 2
0
1
0
1
0=int
10
Vref
OR0
Range
Selector
VDD
Connect pins 15 and
16 for VDD= 3.0-3.6V .
Do NOT connect for
VDD = 4. 5-5.5V !
16
DACref
Mode
MagRng
1
9
2
10bit
digital
DAC
DACout
0 - 100% VDD5V /2
10bit
analog
+
VOUT
-
ClampMdEN
DAC output pin.
Leave open if not used
0=ext
0= 0-100% * Vref (def.)
1= 10-9 0% * Vref
FB_intEN
Vout
12
Rf_int
30k
2
Rf
RLmin
= 4k7
CL
<100pF
1=int
Rg_int
30k
Rg
Gain = 2x (int)
FB
CSn CLK DO
3
4
6
Digital serial
interface, 10bit/360° .
Leave open if not
used. CSn and CLK
may also be tied to
VSS if not used
PROG
8
for OTP
programming and
alignment mode
only. Leave open
or connect to VSS
if not used
NC NC
5
13
NC
VSS
7
14
Test pins.
Leave open
3 VSS
VDD
Vou
0
Page 32
Document Feedback
11
OP-Amp feedback pin.
Leave open if not used.
360°angle
ams Datasheet
[v1-83] 2017-Jul-18
AS5043 − Programming the AS5043
Angular Range Selector
The Angular Range selector allows a digital pre-selection of the
angular range. The AS5043 can be configured for a full scale
angular range of 45°, 90°, 180° or 360°. In addition, the Output
voltage versus angle response can be fine-tuned by setting the
gain of the OP-AMP with external resistors and the maximum
output voltage can be set in the DAC.
The combination of these options allows to configure the
operation range of the AS5043 for all angles up to 360° and
output voltages up to 5.5V.
The response curve for the analog output is linear for the
selected range (45°/90°/180°/360°). In addition, the slope is
mirrored at 180° for 45°- and 90°- modes and has a step response
at 270° for the 180°-mode. This allows the AS5043 to be used in
a variety of applications. In these three modes, the output
remains at Vout,max and Vout,min to avoid a sudden output
change when the mechanical angle is rotated beyond the
selected analog range. In 360°-mode, a jitter between Vout,max
and Vout,min at the 360° point is also prevented due to a
hysteresis.
Figure 34:
360° Angular Range (default)
g
g
(
)
1023
0
ams Datasheet
[v1-83] 2017-Jul-18
0
0°
256
90°
512
180°
768
270°
1 0 2 4 a n g le *)
360°
Page 33
Document Feedback
AS5043 − Programming the AS5043
Figure 35:
180° Angular Range
1023
0
0
0°
256
90°
512
180°
768
270°
1024
360°
a n g le
512
180°
768
270°
1024
360°
a n g le
Figure 36:
90° Angular Range
1023
0
Page 34
Document Feedback
0
0°
256
90°
ams Datasheet
[v1-83] 2017-Jul-18
AS5043 − Programming the AS5043
Figure 37:
45° Angular Range
511
0
0 128 256
0° 45° 90°
512
180°
640
225°
1024
360°
a n g le
Figure 38:
Digital Range Selector Programming Option
Output
Range1
Output
Range0
0
0
0
1
See Figure 35
Analog resolution= 10bit (1024 steps) over 180°
Analog step size: 1LSB = 0.175°
1
0
See Figure 36
Analog resolution= 10bit (1024 steps) over 90°
Analog step size: 1LSB = 0.088°
1
1
See Figure 37
Analog resolution= 9 bit (512 steps) over 45°
Analog step size: 1LSB = 0.088°
Mode
See Figure 34
Note
(1)
Default mode,
Analog resolution= 10bit (1024 steps) over 360°
Analog step size: 1LSB = 0.35°
Note(s) and/or Footnote(s):
1. The resolution on the digital SSI interface is always 10bit (0.35°/step) over 360°, independent on analog mode.
ams Datasheet
[v1-83] 2017-Jul-18
Page 35
Document Feedback
AS5043 − Programming the AS5043
Repeated OTP Programming
Although a single AS5043 OTP register bit can be programmed
only once (from 0 to 1), it is possible to program other,
unprogrammed bits in subsequent programming cycles.
However, a bit that has already been programmed should not
be programmed twice. Therefore it is recommended that bits
that are already programmed are set to “0” during a
programming cycle.
Non-Permanent Programming
It is also possible to re-configure the AS5043 in a
non-permanent way by overwriting the OTP register.
This procedure is essentially a “Write Data” sequence (see
Figure 29) without a subsequent OTP programming cycle.
The “Write Data” sequence may be applied at any time during
normal operation. This configuration remains set while the
power supply voltage is above the power-on reset level (see
Electrical System Specifications).
See Application Note AN5000-20 for further information.
Digital-to-Analog Converter (DAC)
The DAC has a resolution of 10bit (1024 steps) and can be
configured for the following options.
Internal or External Reference
The default DAC reference is the voltage at pin #16 (VDD5V)
divided by 2 (see Figure 32). Using this reference, a system that
has an output voltage ratiometric to the supply voltage can be
built.
Optionally, an external reference source, applied at pin#9
(DACref ) can be used. This programming option is useful for
applications requiring a precise output voltage that is
independent of supply fluctuations, for current sink outputs or
for applications with a dynamic reference, e.g. attenuation of
audio signals.
Page 36
Document Feedback
ams Datasheet
[v1-83] 2017-Jul-18
AS5043 − Programming the AS5043
0-100% or 10-90% Full Scale Range
The reference voltage for the DAC is buffered internally. The
recommended range for the external reference voltage is 0.2V
to (VDD3V3 -0.2)V.
The DAC output voltage will be switched to 0V, when the
magnetic field is out of range, when the MagInc and MagDec
indicators are both =1 and the MagRngn-pin (#1) will go low.
The default full scale output voltage range is 0-100%*VDD5V.
Due to limitations in the output stage of an OP-Amp buffer, it
cannot drive the output voltage from 0-100% rail-to-rail.
Without load, the minimum output voltage at 0° will be a few
millivolts higher than 0V and the maximum output voltage will
be slightly lower than VDD5V. With increasing load, the voltage
drops will increase accordingly.
As a programming option, an output range of 10-90%*VDD5V
can be selected. In this mode, there is no saturation at the upper
and lower output voltage limits like in the 0-100% mode and it
allows failure detection as the output voltage will be outside
the 10-90% limits, when the magnetic field is in the “red” range
(Vout=0V, see Figure 22) or when the supply to the chip is
interrupted (Vout =0V or VDD5V).
The unbuffered output of the DAC is accessible at pin #10
(DACout). This output must not be loaded.
OP-AMP Stage
The DAC output is buffered by a non-inverting Op-Amp stage.
The amplifier is supplied by VDD5V (pin #16) and can hence
provide output voltages up to 5V.
By allowing access to the inverting input of the Op-Amp and
with the addition of a few discrete components it can be
configured in many ways, like high current buffer, current sink
output, adjustable angle range, etc...
Per default, the gain of the Op-Amp must be set by two external
resistors (see Figure 22). Optionally, the fixed internal gain
setting (2x) may be programmed by OTP, eliminating the need
for external resistors.
ams Datasheet
[v1-83] 2017-Jul-18
Page 37
Document Feedback
AS5043 − Programming the AS5043
Output Noise
The noise level at the analog output depends on two states of
the digital angular output:
• The digital angular output value is stable.
In this case, the output noise is the figure given as Vnoise
in OPAMP Output Stage. Note that the noise level is given
for the default gain of 2x For other gains, it must be scaled
accordingly.
• The digital output is at the edge of a step.
In this case, the digital output may jitter between two
adjacent values. The rate of jitter is specified as transition
noise (parameter TN in Electrical System Specifications).
The resulting output noise is calculated by:
(EQ1)
• VDD5V + V
V noise, Vout = TN
----------------------------------noise, OPAMP
360
where:
Vnoise, Vout = noise level at pin Vout in Vrms
TN = transition noise (in °rms; see Electrical System
Specifications)
VDD5V = Supply voltage VDD5V in V
V noise, OPAMP = noise level of OPAMP (OPAMP Output Stage) in
Vrms
Application Examples
See Application Note AN5043-10 for AS5043 Application
Examples.
Page 38
Document Feedback
ams Datasheet
[v1-83] 2017-Jul-18
AS5043 − Analog Readback Mode
Non-volatile programming (OTP) uses on-chip Zener diodes,
which become permanently low resistive when subjected to a
specified reverse current.
The quality of the programming process depends on the
amount of current that is applied during the programming
process (up to 130mA). This current must be provided by an
external voltage source. If this voltage source cannot provide
adequate power, the Zener diodes may not be programmed
properly.
In order to verify the quality of the programmed bits, an analog
level can be read for each Zener diode, giving an indication
whether this particular bit was properly programmed or not.
To put the AS5043 in Analog Readback Mode, a digital sequence
must be applied to pins CSn, PROG and CLK as shown in
Figure 39. The digital level for this pin depends on the supply
configuration (3.3V / 5V Operation).
The second rising edge on CSn (OutpEN) changes pin PROG to
a digital output and the log. high signal at pin PROG must be
removed to avoid collision of outputs (grey area in Figure 39).
The following falling slope of CSn changes pin PROG to an
analog output, providing a reference voltage Vref, that must be
saved as a reference for the calculation of the subsequent
programmed and unprogrammed OTP bits.
Following this step, each rising slope of CLK outputs one bit of
data in the reverse order as during programming. (see
Figure 39: Output Range OR0 and -1, ClampMdEn, RefExtEn,
FB_IntEn, Z0 …Z9, ccw)
During analog readback, the capacitor at pin PROG (see
Figure 31) should be removed to allow a fast readout rate.
The measured analog voltage for each bit must be subtracted
from the previously measured Vref, and the resulting value
gives an indication on the quality of the programmed bit: a
reading of <100mV indicates a properly programmed bit and a
reading of >1V indicates a properly unprogrammed bit.
A reading between 100mV and 1V indicates a faulty bit, which
may result in an undefined digital value, when the OTP is read
at power-up.
Following the 16th clock (after reading bit “ccw”), the chip must
be reset by disconnecting the power supply.
Analog Readback Mode
Figure 39:
Analog OTP Register Read
P ro g E N
P o w e r-o n R e s e t;
c yc le su p ply
A n a log R e a d b a ck D ata a t P R O G
O u tpE N
CSn
V re f
In te rn al
te st bit
dig it al
PROG
V p ro gra m m ed
O R0 O R1
C la m p R ef E xt
M dEN
EN
V u n p rog ram m e d Z 5
Z6
Z7
Z8
Z9
c cw
P rog ch an g es t o O u tp u t
1
CLK
t L oa d P ro g
ams Datasheet
[v1-83] 2017-Jul-18
16
C L K A re ad
Page 39
Document Feedback
AS5043 − Alignment Mode
Alignment Mode
The alignment mode simplifies centering the magnet over the
chip to gain maximum accuracy and XY-alignment tolerance.
This electrical centering method allows a wider XY-alignment
tolerance (0.485mm radius) than mechanical
centering(0.25mm radius) as it eliminates the placement
tolerance of the die within the IC package (±0.235mm).
Alignment mode can be enabled with the falling edge of CSn
while Prog = logic high (Figure 40). The Data bits D9-D0 of the
SSI change to a 10-bit displacement amplitude output. A high
value indicates large X or Y displacement, but also higher
absolute magnetic field strength. The magnet is properly
aligned, when the difference between highest and lowest value
over one full turn is at a minimum.
Under normal conditions, a properly aligned magnet will result
in a reading of less than 32 over a full turn.
Stronger magnets or short gaps between magnet and IC may
show values larger than 32. These magnets are still properly
aligned as long as the difference between highest and lowest
value over one full turn is at a minimum.
The MagINC and MagDEC indicators will be = 1 when the
alignment mode reading is < 32. At the same time, hardware
pin MagRngn (#1) will be pulled to VSS.
The Alignment mode can be reset to normal operation mode
by a power-on-reset (cycle power supply) or by a falling edge
of CSn with PROG =low (see Figure 40).
Figure 40:
Enabling the Alignment Mode
PROG
CSn
AlignMode enable
Read-out
via SSI
2μs 2μs
min. min.
Figure 41:
Exiting Alignment Mode
PROG
CSn
Page 40
Document Feedback
exit AlignMode
Read-out
via SSI
ams Datasheet
[v1-83] 2017-Jul-18
AS5043 − Choosing the Proper Magnet
Typically the magnet should be 6mm in diameter and ≥2.5mm
in height. Magnetic materials such as rare earth AlNiCo, SmCo5
or NdFeB are recommended.
Choosing the Proper Magnet
The magnet’s field strength perpendicular to the die surface
should be verified using a gauss-meter. The magnetic field B v
at a given distance, along a concentric circle with a radius of
1.1mm (R1), should be in the range of ±45mT to ±75mT. (see
Figure 42).
Figure 42:
Typical Magnet and Magnetic Field Distribution
typ. 6mm diameter
N
S
Magnet axis
R1
Magnet axis
Vertical field
component
Vertical field
component
Bv
(45…75mT)
0
360
360
N
S
R1 concentric circle;
radius 1.1mm
ams Datasheet
[v1-83] 2017-Jul-18
Page 41
Document Feedback
AS5043 − Choosing the Proper Magnet
Physical Placement of the Magnet
The best linearity can be achieved by placing the center of the
magnet exactly over the defined center of the IC package as
shown in Figure 43.
Figure 43:
Defined IC Center and Magnet Displacement Radius
3.9 mm
3.9 mm
1
2.433 mm
Defined
center
Rd
2.433 mm
Page 42
Document Feedback
Area of recommended maximum
magnet misalignment
ams Datasheet
[v1-83] 2017-Jul-18
AS5043 − Choosing the Proper Magnet
Magnet Placement
The magnet’s center axis should be aligned within a
displacement radius R d of 0.25mm from the defined center of
the IC with reference to the edge of pin #1 (see Figure 43). This
radius includes the placement tolerance of the chip within the
SSOP-16 package (± 0.235mm).
The displacement radius Rd is 0.485mm with reference to the
center of the chip (see Alignment Mode).
The vertical distance should be chosen such that the magnetic
field on the die surface is within the specified limits (see
Figure 42). The typical distance “z” between the magnet and
the package surface is 0.5mm to 1.8mm with the recommended
magnet (6mm x 3mm). Larger gaps are possible, as long as the
required magnetic field strength stays within the defined limits.
A magnetic field outside the specified range may still produce
usable results, but the out-of-range condition will be indicated
by MagINCn (pin 1), which will be pulled low. At this condition,
the angular data is still available over the digital serial interface
(SSI), but the analog output will be turned OFF.
Figure 44:
Vertical Placement of the Magnet
N
Die surface
S
Package surface
z
0.576mm ± 0.1mm
1.282mm ± 0.15mm
ams Datasheet
[v1-83] 2017-Jul-18
Page 43
Document Feedback
AS5043 − Simulation Modelling
Simulation Modelling
Figure 45:
Arrangement of Hall Sensor Array on Chip (principle)
With reference to Figure 45, a diametrically magnetized
permanent magnet is placed above or below the surface of the
AS5043. The chip uses an array of Hall sensors to sample the
vertical vector of a magnetic field distributed across the device
package surface. The area of magnetic sensitivity is a circular
locus of 1.1mm radius with respect to the center of the die. The
Hall sensors in the area of magnetic sensitivity are grouped and
configured such that orthogonally related components of the
magnetic fields are sampled differentially.
The differential signal Y1-Y2 will give a sine vector of the
magnetic field. The differential signal X1-X2 will give an
orthogonally related cosine vector of the magnetic field.
The angular displacement (θ) of the magnetic source with
reference to the Hall sensor array may then be modelled by:
(EQ2)
( Y1 – Y2 )
Θ = arc tan  -------------------------- ± 0.5°
( X1 – X2 )
The ±0.5° angular error assumes a magnet optimally aligned
over the center of the die and is a result of gain mismatch errors
of the AS5043. Placement tolerances of the die within the
package are ±0.235mm in X and Y direction, using a reference
point of the edge of pin #1 (Figure 45).
Page 44
Document Feedback
ams Datasheet
[v1-83] 2017-Jul-18
AS5043 − Simulation Modelling
In order to neglect the influence of external disturbing
magnetic fields, a robust differential sampling and ratiometric
calculation algorithm has been implemented. The differential
sampling of the sine and cosine vectors removes any common
mode error due to DC components introduced by the magnetic
source itself or external disturbing magnetic fields. A
ratiometric division of the sine and cosine vectors removes the
need for an accurate absolute magnitude of the magnetic field
and thus accurate Z-axis alignment of the magnetic source.
The recommended differential input range of the magnetic
field strength (B (X1-X2) ,B(Y1-Y2) ) is ±75mT at the surface of the
die. In addition to this range, an additional offset of ±5mT,
caused by unwanted external stray fields is allowed.
The chip will continue to operate, but with degraded output
linearity, if the signal field strength is outside the recommended
range. Too strong magnetic fields will introduce errors due to
saturation effects in the internal preamplifiers. Too weak
magnetic fields will introduce errors due to noise becoming
more dominant.
ams Datasheet
[v1-83] 2017-Jul-18
Page 45
Document Feedback
AS5043 − Failure Diagnostics
Failure Diagnostics
The AS5043 also offers several diagnostic and failure detection
features:
Magnetic Field Strength Diagnosis
By Software: the MagINC and MagDEC status bits will both be
high when the magnetic field is out of range.
By Hardware: Pin #1 (MagRngn) is a logical NAND-ed
combination of the MagInc and MagDec status bits. It is an
opendrain output and will be turned ON (= low with external
pull-up resistor) when the magnetic field is out of range.
By Hardware: Pin #12 (Vout) is the analog output of the DAC
and OP-Amp. The analog output will be 0V, when the magnetic
field is out of range (all analog modes).
Power Supply Failure Detection
By Software: If the power supply to the AS5043 is interrupted,
the digital data read by the SSI will be all “0”s. Data is only valid,
when bit OCF is high, hence a data stream with all “0”s is invalid.
To ensure adequate low levels in the failure case, a pull-down
resistor (~10kΩ) should be added between pin DO and VSS at
the receiving side.
By Hardware: The MagRngn pin is an open drain output and
requires an external pull-up resistor. In normal operation, this
pin is high ohmic and the output is high. In a failure case, either
when the magnetic field is out of range or the power supply is
missing, this output will become low. To ensure an adequate
low level in case of a broken power supply to the AS5043, the
pull-up resistor (~10kΩ) must be connected to the positive
supply at pin 16 (VDD5V).
Page 46
Document Feedback
ams Datasheet
[v1-83] 2017-Jul-18
AS5043 − Angular Output Tolerances
Angular Output Tolerances
Accuracy of Digital Outputs
Accuracy is defined as the error between measured angle and
actual angle. It is influenced by several factors:
• The non-linearity of the analog-digital converters,
• Internal gain and mismatch errors,
• Non-linearity due to misalignment of the magnet
As a sum of all these errors, the accuracy with centered
magnet = (Err max – Err min)/2 is specified as better than ±0.5
degrees @ 25°C (see Figure 47).
Misalignment of the magnet further reduces the accuracy.
Figure 46 shows an example of a 3D-graph displaying
nonlinearity over XY-misalignment. The center of the square
XY-area corresponds to a centered magnet (see dot in the center
of the graph). The X- and Y- axis extends to a misalignment of
±1mm in both directions. The total misalignment area of the
graph covers a square of 2mm x 2 mm (79mil x 79mil) with a
step size of 100μm.
For each misalignment step, the measurement as shown in
Figure 47 is repeated and the accuracy (Errmax – Err min )/2 (e.g.
0.25° in Figure 47) is entered as the Z-axis in the 3D-graph.
ams Datasheet
[v1-83] 2017-Jul-18
Page 47
Document Feedback
AS5043 − Angular Output Tolerances
Accuracy of Analog Output
The analog output has the same accuracy as the digital output
with the addition of the nonlinearities of the DAC and the
OPAMP (±1LSB; see Figure 38 and 0).
Figure 46:
Example of Linearity Error Over XY Misalignment
The maximum non-linearity error on this example is better than
±1 degree (inner circle) over a misalignment radius of ~0.7mm.
For volume production, the placement tolerance of the IC
within the package (±0.235mm) must also be taken into
account.
The total nonlinearity error over process tolerances,
temperature and a misalignment circle radius of 0.25mm is
specified better than ±1.4 degrees.
The magnet used for this measurement was a cylindrical NdFeB
(Bomatec® BMN-35H) magnet with 6mm diameter and 2.5mm
in height.
Page 48
Document Feedback
ams Datasheet
[v1-83] 2017-Jul-18
AS5043 − Angular Output Tolerances
Figure 47:
Example of Linearity Error Over 360º
Linearity error with centered magnet [degrees]
0.5
0.4
0.3
0.2
transition noise
0.1
Err max
0
-0.1 1
-0.2
55
109 163 217 271 325 379 433 487 541 595 649 703 757 811 865 919 973
Err min
-0.3
-0.4
-0.5
Transition Noise
Transition noise is defined as the jitter in the transition between
two steps.
Due to the nature of the measurement principle (Hall sensors
+ Preamplifier + ADC), there is always a certain degree of noise
involved.
This transition noise voltage results in an angular transition
noise at the outputs. It is specified as 0.06 degrees rms
(1 sigma) 2 in fast mode (pin MODE = high) and 0.03 degrees rms
(1 sigma)2 in slow mode (pin MODE = low or open). These values
are the repeatability of an indicated angle at a given mechanical
position.
The transition noise has different implications on the type of
output that is used:
• Absolute Output; SSI Interface:
The transition noise of the absolute output can be reduced
by the user by applying an averaging of readings. An
averaging of 4 readings will reduce the transition noise by
6dB or 50%, e.g. from 0.03°rms to 0.015°rms (1 sigma)2 in
slow mode.
• Analog Output:
Ideally, the analog output should have a jitter that is less
than one digit. In 360° mode, both fast or slow mode may
be selected for adequate low jitter. In 180°, 90° or 45°
mode, where the step sizes are smaller, slow mode should
be selected to reduce the output jitter.
2. Statistically, 1 sigma represents 68.27% of readings, 3 sigma represents 99.73% of readings.
ams Datasheet
[v1-83] 2017-Jul-18
Page 49
Document Feedback
AS5043 − Angular Output Tolerances
High Speed Operation
Sampling Rate
The AS5043 samples the angular value at a rate of 10.42k
samples per second (ksps) in fast mode and 2.61ksps in slow
mode.
Consequently, a new reading is performed each 96μs. (fast
mode) or 384μs (slow mode).
At a stationary position of the magnet, this sampling rate
creates no additional error.
Absolute Mode
With the given sampling rates, the number of samples (n) per
turn for a magnet rotating at high speed can be calculated by
(EQ3)
60
n = --------------------------rpm • 96μs
(EQ4)
60
n = ------------------------------- for slow mode
rpm • 384μs
for fast mode
In practice, there is no upper speed limit. The only restriction is
that there will be fewer samples per revolution as the speed
increases.
Regardless of the rotational speed, the absolute angular value
is always sampled at the highest resolution.
Figure 48:
Speed Performance
Fast Mode
(Pin Mode = 1)
Slow Mode
(Pin Mode = 0 or Open)
610rpm = 1024 samples / turn
610rpm = 256 samples / turn
1220rpm = 512 samples / turn
1220rpm = 128 samples / turn
2441rpm = 256 samples / turn
2441rpm = 64 samples / turn
etc…
etc…
Page 50
Document Feedback
ams Datasheet
[v1-83] 2017-Jul-18
AS5043 − Angular Output Tolerances
Output Delays
The propagation delay is the delay between the time that the
sample is taken until it is available as angular data. This delay
is 96μs in fast mode (pin Mode = high) and 384μs in slow mode
(pin Mode = low or open).
The analog output produces no further delay, the output
voltage will be updated as soon as it is available. Using the SSI
interface for data transmission, an additional delay must be
considered, caused by the asynchronous sampling (0
….1/fsample) and the time it takes the external control unit to
read and process the angular data from the AS5043.
Angular Error Caused by Propagation Delay
A rotating magnet will cause an angular error caused by the
propagation delay. This error increases linearly with speed:
(EQ5)
Where:
e sampling = angular error [º]
rpm = rotating speed [rpm]
pr.delay = propagation delay [seconds]
Note(s): Since the propagation delay is known, it can be
automatically compensated by the control unit processing the
data from the AS5043.
Internal Timing Tolerance
The AS5043 does not require an external ceramic resonator or
quartz. All internal clock timings for the AS5043 are generated
by an ON-chip RC oscillator. This oscillator is factory trimmed
to ±5% accuracy at room temperature (±10% over full
temperature range). This tolerance influences the ADC
sampling rate:
• Absolute Output; SSI Interface:
A new angular value is updated every
96μs ± 5% (Mode = 1) or
384μs ± 5% (Mode = 0 or open)
ams Datasheet
[v1-83] 2017-Jul-18
Page 51
Document Feedback
AS5043 − Angular Output Tolerances
Temperature
Magnetic Temperature Coefficient
One of the major benefits of the AS5043 compared to linear Hall
sensors is that it is much less sensitive to temperature. While
linear Hall sensors require a compensation of the magnet’s
temperature coefficients, the AS5043 automatically
compensates for the varying magnetic field strength over
temperature. The magnet’s temperature drift does not need to
be considered, as the AS5043 operates with magnetic field
strengths from ±45mT …±75mT.
Example:
A NdFeB magnet has a field strength of 75mT @ -40ºC and a
temperature coefficient of -0.12% per Kelvin. The temperature
change is from -40ºC to 125ºC = 165K.
The magnetic field change is: 165 x -0.12% = -19.8%, which
corresponds to 75mT at -40ºC and 60mT at 125ºC.
The AS5043 can compensate for this temperature related field
strength change automatically, no user adjustment is required.
Accuracy Over Temperature
The influence of temperature in the absolute accuracy is very
low. While the accuracy is ≤ ±0.5º at room temperature, it may
increase to ≤ ±0.9º due to increasing noise at high
temperatures.
Timing Tolerance Over Temperature
The internal RC oscillator is factory trimmed to ±5%. Over
temperature, this tolerance may increase to ±10%. Generally,
the timing tolerance has no influence in the accuracy or
resolution of the system, as it is used mainly for internal clock
generation.
Page 52
Document Feedback
ams Datasheet
[v1-83] 2017-Jul-18
AS5043 − Mechanical Data
Mechanical Data
The internal Hall elements are located in the center of the
package on a circle with a radius of 1 mm.
Figure 49:
Hall Element Positions
Note(s) and/or Footnote(s):
1. All dimensions in mm.
2. Die thickness 381μm nom.
3. Adhesive thickness 30 ± 15μm.
4. Leadframe downset 200 ± 38μm.
5. Leadframe thickness 152±8 μm.
ams Datasheet
[v1-83] 2017-Jul-18
Page 53
Document Feedback
AS5043 − Package Drawings & Mark ings
Package Drawings & Markings
Figure 50:
16-Lead Shrink Small Outline Package SSOP-16
Symbol
Min
Typ
Max
A
A1
A2
b
c
D
E
E1
e
L
L1
L2
R
Θ
N
1.73
0.05
1.68
0.25
0.09
6.07
7.65
5.2
1.86
0.13
1.73
0.315
6.20
7.8
5.3
0.65
0.75
1.25 REF
0.25 BSC
4º
16
1.99
0.21
1.78
0.38
0.20
6.33
7.9
5.38
0.63
0.09
0º
0.95
RoHS
Green
8º
Note(s) and/or Footnote(s):
1. Dimensioning and tolerancing conform to ASME Y14.5M-1994.
2. All dimensions are in millimeters. Angles in degrees.
3. N is the total number of terminals.
Page 54
Document Feedback
ams Datasheet
[v1-83] 2017-Jul-18
AS5043 − Package Drawings & Markings
Figure 51:
Package Marking
YYWWMZZ
AS5043 @
Figure 52:
Package Code
YY
Last two digits of the
manufacturing year
WW
M
Manufacturing week
Plant identifier
ZZ
@
Free choice/
traceability code
Sublot identifier
JEDEC Package Outline Standard:
MO - 150 AC
Thermal Resistance R th(j-a) :
typ. 151 K/W in still air, soldered on PCB
IC's marked with a white dot or the letters
"ES" denote Engineering Samples
ams Datasheet
[v1-83] 2017-Jul-18
Page 55
Document Feedback
AS5043 − Recommended PCB Footprint
Recommended PCB Footprint
Figure 53:
Recommended PCB Footprint
Figure 54:
Recommended Footprint Data
Recommended Footprint Data
Page 56
Document Feedback
mm
inch
A
9.02
0.355
B
6.16
0.242
C
0.46
0.018
D
0.65
0.025
E
5.01
0.197
ams Datasheet
[v1-83] 2017-Jul-18
AS5043 − Ordering & Contact Information
Ordering & Contact Information
Figure 55:
Ordering Information
Ordering Code
Package
Marking
Delivery Form
Delivery Quantity
AS5043-ASSM
SSOP-16
AS5043
Tape & Reel
500 pcs/reel
AS5043-ASST
SSOP-16
AS5043
Tape & Reel
2000 pcs/reel
Buy our products or get free samples online at:
www.ams.com/ICdirect
Technical Support is available at:
www.ams.com/Technical-Support
Provide feedback about this document at:
www.ams.com/Document-Feedback
For further information and requests, e-mail us at:
ams_sales@ams.com
For sales offices, distributors and representatives, please visit:
www.ams.com/contact
Headquarters
ams AG
Tobelbader Strasse 30
8141 Premstaetten
Austria, Europe
Tel: +43 (0) 3136 500 0
Website: www.ams.com
ams Datasheet
[v1-83] 2017-Jul-18
Page 57
Document Feedback
AS5043 − RoHS Compliant & ams Green Statement
RoHS Compliant & ams Green
Statement
RoHS: The term RoHS compliant means that ams AG products
fully comply with current RoHS directives. Our semiconductor
products do not contain any chemicals for all 6 substance
categories, including the requirement that lead not exceed
0.1% by weight in homogeneous materials. Where designed to
be soldered at high temperatures, RoHS compliant products are
suitable for use in specified lead-free processes.
ams Green (RoHS compliant and no Sb/Br): ams Green
defines that in addition to RoHS compliance, our products are
free of Bromine (Br) and Antimony (Sb) based flame retardants
(Br or Sb do not exceed 0.1% by weight in homogeneous
material).
Important Information: The information provided in this
statement represents ams AG knowledge and belief as of the
date that it is provided. ams AG bases its knowledge and belief
on information provided by third parties, and makes no
representation or warranty as to the accuracy of such
information. Efforts are underway to better integrate
information from third parties. ams AG has taken and continues
to take reasonable steps to provide representative and accurate
information but may not have conducted destructive testing or
chemical analysis on incoming materials and chemicals. ams AG
and ams AG suppliers consider certain information to be
proprietary, and thus CAS numbers and other limited
information may not be available for release.
Page 58
Document Feedback
ams Datasheet
[v1-83] 2017-Jul-18
AS5043 − Copyrights & Disclaimer
Copyrights & Disclaimer
Copyright ams AG, Tobelbader Strasse 30, 8141 Premstaetten,
Austria-Europe. Trademarks Registered. All rights reserved. The
material herein may not be reproduced, adapted, merged,
translated, stored, or used without the prior written consent of
the copyright owner.
Devices sold by ams AG are covered by the warranty and patent
indemnification provisions appearing in its General Terms of
Trade. ams AG makes no warranty, express, statutory, implied,
or by description regarding the information set forth herein.
ams AG reserves the right to change specifications and prices
at any time and without notice. Therefore, prior to designing
this product into a system, it is necessary to check with ams AG
for current information. This product is intended for use in
commercial applications. Applications requiring extended
temperature range, unusual environmental requirements, or
high reliability applications, such as military, medical
life-support or life-sustaining equipment are specifically not
recommended without additional processing by ams AG for
each application. This product is provided by ams AG “AS IS”
and any express or implied warranties, including, but not
limited to the implied warranties of merchantability and fitness
for a particular purpose are disclaimed.
ams AG shall not be liable to recipient or any third party for any
damages, including but not limited to personal injury, property
damage, loss of profits, loss of use, interruption of business or
indirect, special, incidental or consequential damages, of any
kind, in connection with or arising out of the furnishing,
performance or use of the technical data herein. No obligation
or liability to recipient or any third party shall arise or flow out
of ams AG rendering of technical or other services.
ams Datasheet
[v1-83] 2017-Jul-18
Page 59
Document Feedback
AS5043 − Document Status
Document Status
Document Status
Product Preview
Preliminary Datasheet
Datasheet
Datasheet (discontinued)
Page 60
Document Feedback
Product Status
Definition
Pre-Development
Information in this datasheet is based on product ideas in
the planning phase of development. All specifications are
design goals without any warranty and are subject to
change without notice
Pre-Production
Information in this datasheet is based on products in the
design, validation or qualification phase of development.
The performance and parameters shown in this document
are preliminary without any warranty and are subject to
change without notice
Production
Information in this datasheet is based on products in
ramp-up to full production or full production which
conform to specifications in accordance with the terms of
ams AG standard warranty as given in the General Terms of
Trade
Discontinued
Information in this datasheet is based on products which
conform to specifications in accordance with the terms of
ams AG standard warranty as given in the General Terms of
Trade, but these products have been superseded and
should not be used for new designs
ams Datasheet
[v1-83] 2017-Jul-18
AS5043 − Revision Information
Revision Information
Changes from 1-82 (2015-Dec-07) to current revision 1-83 (2017-Jul-18)
Updated Figure 55
Page
57
Note(s) and/or Footnote(s):
1. Page and figure numbers for the previous version may differ from page and figure numbers in the current revision
2. Correction of typographical errors is not explicitly mentioned.
ams Datasheet
[v1-83] 2017-Jul-18
Page 61
Document Feedback
AS5043 − Content Guide
Content Guide
Page 62
Document Feedback
1
1
2
3
General Description
Key Benefits & Features
Applications
Block Diagram
4
5
Pin Assignment
Pin Description
7
Absolute Maximum Ratings
8
8
8
8
9
9
10
10
11
12
13
15
16
Electrical Characteristics
Operating Conditions
DC Characteristics for Digital Inputs and Outputs
CMOS Schmitt-Trigger Inputs: CLK, CSn (Internal
Pull-Up), Mode (Internal Pull-Down)
CMOS Input: Program Input (Prog)
CMOS Output Open Drain: MagRngn
Tristate CMOS Output: DO
Digital-to-Analog Converter
OPAMP Output Stage
Magnetic Input Specification
Electrical System Specifications
Timing Characteristics
Programming Conditions
17
18
Functional Description
3.3V / 5V Operation
19
19
21
10-Bit Absolute Synchronous Serial Interface (SSI)
Serial Data Contents
Z-Axis Range Indication (Push Button Feature, Red/Yellow/Green Indicator)
22
23
Mode Input Pin
Daisy Chain Mode
24
25
25
26
Analog Output
Analog Output Voltage Modes
Full Scale Mode
Diagnostic Output Mode
28
30
31
33
36
36
36
36
37
37
38
38
Programming the AS5043
Zero Position Programming
Analog Mode Programming
Angular Range Selector
Repeated OTP Programming
Non-Permanent Programming
Digital-to-Analog Converter (DAC)
Internal or External Reference
0-100% or 10-90% Full Scale Range
OP-AMP Stage
Output Noise
Application Examples
ams Datasheet
[v1-83] 2017-Jul-18
AS5043 − Content Guide
ams Datasheet
[v1-83] 2017-Jul-18
39
40
Analog Readback Mode
Alignment Mode
41
42
43
Choosing the Proper Magnet
Physical Placement of the Magnet
Magnet Placement
44
Simulation Modelling
46
46
46
Failure Diagnostics
Magnetic Field Strength Diagnosis
Power Supply Failure Detection
47
47
48
49
50
50
51
51
51
52
52
52
52
Angular Output Tolerances
Accuracy of Digital Outputs
Accuracy of Analog Output
Transition Noise
High Speed Operation
Sampling Rate
Output Delays
Angular Error Caused by Propagation Delay
Internal Timing Tolerance
Temperature
Magnetic Temperature Coefficient
Accuracy Over Temperature
Timing Tolerance Over Temperature
53
54
56
57
58
59
60
61
Mechanical Data
Package Drawings & Markings
Recommended PCB Footprint
Ordering & Contact Information
RoHS Compliant & ams Green Statement
Copyrights & Disclaimer
Document Status
Revision Information
Page 63
Document Feedback