200pin Unbuffered DDR2 SDRAM SO-DIMMs based on 512 Mb B ver.
This Hynix unbuffered Slim Outline Dual In-Line Memory Module(DIMM) series consists of 512Mb B ver. DDR2 SDRAMs
in Fine Ball Grid Array(FBGA) packages on a 200pin glass-epoxy substrate. This Hynix 512Mb B ver. based Unbuffered
DDR2 SO-DIMM series provide a high performance 8 byte interface in 67.60mm width form factor of industry standard.
It is suitable for easy interchange and addition.
FEATURES
•
JEDEC standard Double Data Rate2 Synchronous
DRAMs (DDR2 SDRAMs) with 1.8V +/- 0.1V Power
Supply
•
All inputs and outputs are compatible with SSTL_1.8
interface
•
Posted CAS
•
Programmable CAS Latency 3 ,4 ,5
•
OCD (Off-Chip Driver Impedance Adjustment) and
ODT (On-Die Termination)
•
Fully differential clock operations (CK & CK)
•
Programmable Burst Length 4 / 8 with both sequential and interleave mode
•
Auto refresh and self refresh supported
•
8192 refresh cycles / 64ms
•
Serial presence detect with EEPROM
•
DDR2 SDRAM Package: 60ball(x8), 84ball(x16)
FBGA
•
67.60 x 30.00 mm form factor
•
Lead-free Products are RoHS compliant
ORDERING INFORMATION
Part Name
Density
Organization
# of
DRAMs
# of
ranks
Materials
Power
Consumption
HYMP532S64BP6-E3/C4/Y5/S5
256MB
32Mx64
4
1
Lead free*
Normal
HYMP564S64BP6-E3/C4/Y5/S5
512MB
64Mx64
8
2
Lead free
Normal
HYMP512S64BP8-E3/C4/Y5/S5
1GB
128Mx64
16
2
Lead free
Normal
HYMP532S64BLP6-E3/C4/Y5/S5
256MB
32Mx64
4
1
Lead free
Low
HYMP564S64BLP6-E3/C4/Y5/S5
512MB
64Mx64
8
2
Lead free
Low
HYMP512S64BLP8-E3/C4/Y5/S5
1GB
128Mx64
16
2
Lead free
Low
Notes:
1. All Hynix’ DDR2 Lead-free parts are compliant to RoHS.
This document is a general product description and is subject to change without notice. Hynix Semiconductor does not assume any
responsibility for use of circuits described. No patent licenses are implied.
Rev. 0.3 / Aug. 2007
1
1200pin Unbuffered DDR2 SDRAM SO-DIMMs
SPEED GRADE & KEY PARAMETERS
E3
(DDR2-400)
C4
(DDR2-533)
Y5
(DDR2-667)
S5
(DDR2-800)
Unit
Speed@CL3
400
400
400
400
Mbps
Speed@CL4
400
533
533
533
Mbps
Speed@CL5
-
-
667
800
Mbps
Speed@CL6
-
-
-
800
Mbps
CL-tRCD-tRP
3-3-3
4-4-4
5-5-5
5-5-5
tCK
ADDRESS TABLE
Density
Organization Ranks
SDRAMs
# of
DRAMs
# of row/bank/column Address
Refresh
Method
256MB
32M x 64
1
32Mb x 16
4
13(A0~A12)/2(BA0~BA1)/10(A0~A9)
8K / 64ms
512MB
64M x 64
2
32Mb x 16
8
13(A0~A12)/2(BA0~BA1)/10(A0~A9)
8K / 64ms
1GB
128M x 64
2
64Mb x 8
16
14(A0~A13)/2(BA0~BA1)/10(A0~A9)
8K / 64ms
Rev. 0.3 / Aug. 2007
2
1200pin Unbuffered DDR2 SDRAM SO-DIMMs
PIN DESCRIPTION
Symbol
Type
Polarity
Pin Description
The system clock inputs. All address an commands lines are sampled on the cross point of
the rising edge of CK and falling edge of CK. A Delay Locked Loop(DLL) circuit is driven
from the clock inputs and output timing for read operations is synchronized to the input
clock.
CK[1:0], CK[1:0]
Input
Cross
Point
CKE[1:0]
Input
Active
High
Activates the DDR2 SDRAM CK signal when high and deactivates the CK signal when low.
By deactivating the clocks, CKE low initiates the Power Down mode or the Self Refresh
mode.
S[1:0]
Input
Active
Low
Enables the associated DDR2 SDRAM command decoder when low and disables the command decoder when high. When the command decoder is disabled, new commands are
ignored but previous operations continue. Rank 0 is selected by S0; Rank 1 is selected by
S1
RAS, CAS, WE
Input
Active
Low
When sampled at the cross point of the rising edge of CK and falling edge of CK, CAS, RAS
and WE define the operation to be executed by the SDRAM.
BA[1:0]
Input
ODT[1:0]
Input
Selects which DDR2 SDRAM internal bank of four is activated.
Active
High
Asserts on-die termination for DQ, DM, DQS and DQS signals if enabled via the DDR2
SDRAM mode register.
A[9:0], A10/AP,
A[15:11]
Input
During a Bank Activate command cycle, defines the row address when sampled at the
cross point of the rising edge of CK and falling edge of CK. During a Read or Write command cycle, defines the column address when sampled at the cross point of the rising
edge of CK and falling edge of CK. In addition to the column address, AP is used to invoke
autoprecharge operation at the end of the burst read or write cycle. If AP is high., autoprecharge is selected and BA0-BAn defines the bank to be precharged. If AP is low, autoprecharge is disabled. During a Precharge command cycle., AP is used in conjunction with
BA0-BAn to control which bank(s) to precharge. If AP is high, all banks will be precharged
regardless of the state of BA0-BAn inputs. If AP is low, then BA0-BAn are used to define
which bank to precharge.
DQ[63:0]
In/Out
Data Input/Output pins.
DM[7:0]
Input
DQS[7:0], DQS[7:0] In/Out
Active
High
The data write masks, associated with one data byte. In Write mode, DM operates as a
byte mask by allowing input data to be written if it is low but blocks the write operation if
it is high. In Read mode, DM lines have no effect.
Cross
point
The data strobe, associated with one data byte, sourced whit data transfers. In Write
mode, the data strobe is sourced by the controller and is centered in the data window. In
Read mode, the data strobe is sourced by the DDR2 SDRAMs and is sent at leading edge
of the data window. DQS signals are complements, and timing is relative to the crosspoint
of respective DQS and DQS. If the module is to be operated in single ended strobe mode,
all DQS signals must be tied on the system board to VSS and DDR2 SDRAM mode registers
programmed appropriately.
VDD, VDDSPD,VSS
Supply
Power supplies for core, I/O, Serial Presense Detect, and ground for the module.
SDA
In/Out
This is a bidirectional pin used to transfer data into or out of the SPD EEPROM. A resister
must be connected to VDD to act as a pull up.
SCL
Input
This signals is used to clock data into and out of the SPD EEPROM. A resistor may be connected from SCL to VDD to act as a pull up.
SA[1:0]
Input
Address pins used to select the Serial Presence Detect base address.
TEST
In/Out
The TEST pin is reserved for bus analysis tools and is not connected on normal memory
modules(SODIMMs).
Rev. 0.3 / Aug. 2007
3
1200pin Unbuffered DDR2 SDRAM SO-DIMMs
PIN ASSIGNMENT
Pin
NO.
Front
Side
Pin
NO.
Back
Side
Pin
NO.
Front
Side
Pin
NO.
Back
Side
Pin
NO.
Front
Side
Pin
NO.
Back
Side
Pin
NO.
Front
Side
Pin
NO.
Back
Side
1
VREF
2
VSS
51
DQS2
52
DM2
101
A1
102
A0
151
DQ42
152
DQ46
3
VSS
4
DQ4
53
VSS
54
VSS
103
VDD
104
VDD
153
DQ43
154
DQ47
5
DQ0
6
DQ5
55
DQ18
56
DQ22
105
A10/AP
106
BA1
155
VSS
156
VSS
7
DQ1
8
VSS
57
DQ19
58
DQ23
107
BA0
108
RAS
157
DQ48
158
DQ52
9
VSS
10
DM0
59
VSS
60
VSS
109
WE
110
S0
159
DQ49
160
DQ53
11
DQS0
12
VSS
61
DQ24
62
DQ28
111
VDD
112
VDD
161
VSS
162
VSS
13
DQS0
14
DQ6
63
DQ25
64
DQ29
113
CAS
114
ODT0
163
15
VSS
16
DQ7
65
VSS
66
VSS
115
NC/S1
116
A13
165
VSS
166
CK1
17
DQ2
18
VSS
67
DM3
68
DQS3
117
VDD
118
VDD
167
DQS6
168
VSS
19
DQ3
20
DQ12
69
NC
70
DQS3
119 NC/ODT1
120
NC
169
DQS6
170
DM6
21
VSS
22
DQ13
71
VSS
72
VSS
121
VSS
122
VSS
171
VSS
172
VSS
23
DQ8
24
VSS
73
DQ26
74
DQ30
123
DQ32
124
DQ36
173
DQ50
174
DQ54
25
DQ9
26
DM1
75
DQ27
76
DQ31
125
DQ33
126
DQ37
175
DQ51
176
DQ55
27
VSS
28
VSS
77
VSS
78
VSS
127
VSS
128
VSS
177
VSS
178
VSS
NC,TEST 164
CK1
29
DQS1
30
CK0
79
CKE0
80
DQS4
130
DM4
179
DQ56
180
DQ60
31
DQS1
32
CK0
81
VDD
82
VDD
131
DQS4
132
VSS
181
DQ57
182
DQ61
33
VSS
34
VSS
83
NC
84
NC/A15
133
VSS
134
DQ38
183
VSS
184
VSS
35
DQ10
36
DQ14
85
BA2
86
NC/A14
135
DQ34
136
DQ39
185
DM7
186
DQS7
37
DQ11
38
DQ15
87
VDD
88
VDD
137
DQ35
138
VSS
187
VSS
188
DQS7
39
VSS
40
VSS
89
A12
90
A11
139
VSS
140
DQ44
189
DQ58
190
VSS
41
VSS
42
VSS
91
A9
92
A7
141
DQ40
142
DQ45
191
DQ59
192
DQ62
43
DQ16
44
DQ20
93
A8
94
A6
143
DQ41
144
VSS
193
VSS
194
DQ63
NC/CKE1 129
45
DQ17
46
DQ21
95
VDD
96
VDD
145
VSS
146
DQS5
195
SDA
196
VSS
47
VSS
48
VSS
97
A5
98
A4
147
DM5
148
DQS5
197
SCL
198
SA0
49
DQS2
50
NC
99
A3
100
A2
149
VSS
150
VSS
199
VDDSPD
200
SA1
Pin Location
2
Back
Front
1
39 41
Rev. 0.3 / Aug. 2007
200
40 42
199
4
1200pin Unbuffered DDR2 SDRAM SO-DIMMs
FUNCTIONAL BLOCK DIAGRAM
256MB(32Mbx64) : HYMP532S64B(L)P6
3 Ω + /− 5 %
/S 1
N .C .
O DT1
N .C .
CKE1
N .C .
CKE0
ODT0
/S 0
DQS0
LDQS
DQS4
LDQS
/D Q S 0
/U D Q S
/D Q S 4
/L D Q S
LDM
DM4
DM0
/C S
ODT
CKE
I/O 0
DQ 32
I/O 0
DQ1
I/O 1
DQ 33
I/O 1
DQ2
I/O 2
DQ 34
I/O 2
DQ3
I/O 3
DQ 35
I/O 3
DQ4
I/O 4
DQ 36
I/O 4
DQ5
I/O 5
I/O 5
DQ6
I/O 6
DQ7
I /O 7
DQ 37
DQ 38
DQ 39
D0
UDQS
DQS1
/U D Q S
UDM
DM1
DQ8
I/O 6
DQS5
UDQS
/U D Q S
DQ 40
DQ8
I/O 9
DQ 41
I/O 9
I/O 1 0
DQ 42
I/O 1 0
DQ 11
I/O 1 1
DQ 43
I/O 1 1
DQ 12
I/O 1 2
DQ 44
I/O 1 2
DQ 13
I/O 1 3
DQ 45
I/O 1 3
DQ 14
DQ 15
I/O 1 4
DQ 46
DQ47
I /O 1 5
I /O 1 5
/L D Q S
DM2
/C S
ODT
CKE
DQS6
LDQS
/D Q S 6
/L D Q S
I/ O 0
DQ48
I/O 0
DQ 17
I/ O 1
DQ49
I/O 1
DQ 18
I/ O 2
DQ50
I/O 2
DQ 19
I/ O 3
DQ51
I/O 3
DQ 20
I/ O 4
DQ52
I/O 4
DQ 21
I/ O 5
DQ53
I/O 5
DQ 22
I/ O 6
DQ54
I/O 6
DQ 23
I/O 7
DQ 55
I/O 7
D1
DQS3
UDQS
DQS7
UDQS
/D Q S 3
/U D Q S
/D Q S 7
/U D Q S
DM7
UDM
I/ O 8
DQ56
DQ 25
I/ O 9
DQ57
I /O 9
DQ 26
I /O 1 0
DQ58
I/O 1 0
DQ 27
I /O 1 1
DQ59
I/O 1 1
DQ 28
I /O 1 2
DQ60
I/O 1 2
DQ 29
I /O 1 3
DQ61
I/O 1 3
DQ 30
I /O 1 4
DQ62
I/O 1 4
DQ 31
I/O 1 5
DQ 63
I/ O 1 5
SCL
3 Ω + /- 5 %
SDRAMS
SDRAMS
SDRAMS
SDRAMS
SDRAMS
D 0 -3
D 0 -3
D 0 -3
D 0 -3
D 0 -3
SA0
SA1
VDD S P D
CK0
2 lo a d s
V REF
SCL
A0
A1
A2
D3
UDM
DQ 24
B A 0 -B A 1
A 0 -A N
/R A S
/C A S
/W E
/C S
LDM
DQ 16
DM3
CKE
I/O 1 4
DM6
LDM
ODT
I/O 8
DQ 10
LDQS
D2
UDM
DM5
DQS2
CKE
I /O 7
/D Q S 5
I/O 8
/D Q S 2
ODT
LDM
DQ0
/D Q S 1
/C S
I /O 8
SDA
SDA
S e r ia l P D
WP
S e r ia l P D
S D R A M S D O -D 3
/C K 0
CK1
2 lo a d s
VDD
S D R A M S D O -D 3 , V D D a n d V D D Q
VSS
S D R A M S D O -D 3 , S P D
/C K 1
N o te s :
1 . R e s is to r v a lu e s a r e 2 2 O h m + /- 5 %
Rev. 0.3 / Aug. 2007
5
1200pin Unbuffered DDR2 SDRAM SO-DIMMs
FUNCTIONAL BLOCK DIAGRAM
512MB(64Mbx64): HYMP564S64B(L)P6
3 Ω +/− 5 %
O DT 1
O DT 0
CKE 1
CKE 0
/S 1
/S 0
LDQS
LDM
LDM
LDM
LDM
DQ 0
I/ O 0
I/ O 0
DQ 32
I/ O 0
I/ O 0
DQ 1
I/ O 1
I/ O 1
DQ 33
I/ O 1
I/ O 1
DQ 2
I/ O 2
I/ O 2
DQ 34
I/ O 2
I/ O 2
DQ 3
I/ O 3
I/ O 3
DQ 35
I/ O 3
I/ O 3
DQ 4
I/ O 4
I/ O 4
DQ 36
I/ O 4
I/ O 4
DQ 5
I/ O 5
I/ O 5
I/ O 5
I/ O 5
DQ 6
I/ O 6
I/ O 6
DQ 7
I/ O 7
DQ 37
DQ 38
DQ 39
DM 0
DQ S 1
/ DQ S 1
DM 1
DQ 8
D0
I/ O 7
UDQS
UDQ S
/ UDQ S
/ UDQ S
UDM
UDM
I/ O 8
DM 4
D4
DQ S 5
/ DQ S 5
I/ O 6
I/ O 7
I/ O 6
D2
I/ O 7
UDQ S
UDQ S
/ UDQ S
/ UDQ S
I/ O 8
DQ 40
I/ O 8
I/ O 8
DQ 8
I/ O 9
I/ O 9
DQ 41
I/ O 9
I/ O 9
DQ 10
I/ O 10
I/ O 10
DQ 42
I/ O 10
I/ O 10
DQ 11
I/ O 11
I/ O 11
DQ 43
I/ O 11
I/ O 11
DQ 12
I/ O 12
I/ O 12
DQ 44
I/ O 12
I/ O 12
DQ 13
I/ O 13
I/ O 13
DQ 45
I/ O 13
I/ O 13
DQ 14
I/ O 14
I/ O 14
DQ 46
I/ O 14
I/ O 14
DQ 15
I/ O 15
I/ O 15
DQ 47
I/ O 15
I/ O 15
LDM
LDM
LDM
LDM
DQ 16
I/ O 0
I/ O 0
DQ 48
I/ O 0
I/ O 0
DQ 17
I/ O 1
I/ O 1
DQ 49
I/ O 1
I/ O 1
DQ 18
I/ O 2
I/ O 2
DQ 50
I/ O 2
I/ O 2
DQ 19
I/ O 3
I/ O 3
DQ 51
I/ O 3
I/ O 3
DQ 20
I/ O 4
I/ O 4
DQ 52
I/ O 4
I/ O 4
DQ 21
I/ O 5
I/ O 5
DQ 53
I/ O 5
DQ 22
I/ O 6
I/ O 6
DQ 54
I/ O 6
DQ 23
I/ O 7
DQ 55
I/ O 7
DQ S 3
/ DQ S 3
DM 3
D1
UDQ S
UDQ S
DQ S 7
/ UDQ S
/ UDQ S
/ DQ S 7
UDM
DM 7
UDM
I/ O 8
DQ 24
I/ O 7
D5
DQ 56
I/ O 5
D3
I/ O 6
I/ O 7
UDQ S
UDQ S
/ UDQ S
/ UDQ S
UDM
I/ O 8
I/ O 8
D7
UDM
I/ O 8
DQ 25
I/ O 9
I/ O 9
DQ 57
I/ O 9
I/ O 9
DQ 26
I/ O 10
I/ O 10
DQ 58
I/ O 10
I/ O 10
DQ 27
I/ O 11
I/ O 11
DQ 59
I/ O 11
I/ O 11
DQ 28
I/ O 12
I/ O 12
DQ 60
I/ O 12
I/ O 12
DQ 29
I/ O 13
I/ O 13
DQ 61
I/ O 13
I/ O 13
DQ 30
I/ O 14
I/ O 14
DQ 62
I/ O 14
I/ O 14
DQ 31
I/ O 15
DQ 63
I/ O 15
I/ O 15
I/ O 15
/ CS
ODT
DM 6
LDQS
/ UDQ S
CKE
LDQ S / CS
/ LDQ S
ODT
DQ S 6
/ DQ S 6
CKE
/ CS
ODT
LDQ S
/ UDQ S
CKE
DM 2
ODT
LDQ S / CS
/ LDQS
CKE
DQ S 2
/ DQ S 2
D6
UDM
UDM
DM 5
/ CS
/ UDQ S
ODT
/ CS
CKE
LDQ S
/ UDQ S
ODT
DQ S 4
/ DQ S 4
CKE
/ CS
ODT
LDQ S
/ UDQ S
CKE
/ CS
ODT
LDQ S
/ UDQ S
CKE
DQ S 0
/ DQ S 0
3 Ω +/- 5 %
BA0 - BA1
A 0- AN
/ RAS
/ CAS
/WE
SDRAM S
SDRAM S
SDRAM S
SDRAM S
SDRAM S
D 0 -7
D 0 -7
D 0 -7
D 0 -7
D 0 -7
SCL
SCL
A0
A1
A2
SA 0
SA 1
V DD SPD
CK0
SDA
SDA
Serial PD
WP
Notes :
1. Resistor values are 22 Ohm +/- 5%
Serial PD
4 loads
/ CK 0
CK 1
V REF
SDRAM S DO -D 3
V DD
SDRAM S DO - D 3 , V DD and V DD Q
V SS
SDRAM S DO - D 3 , SPD
4 loads
/ CK 1
Rev. 0.3 / Aug. 2007
6
1200pin Unbuffered DDR2 SDRAM SO-DIMMs
FUNCTIONAL BLOCK DIAGRAM
1GB(128Mbx64) : HYMP512S64B(L)P8
3 Ω +/- 5%
CKE 1
ODT1
/S1
CKE 0
ODT1
/S0
/ DQS 0
DQS 0
DM0
DQS / CS0 ODT0 CKE0
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
/ DQS
DM
I/ O 0
DM
I/ O0
I/ O 1
I/ O 1
I/ O 2
DQS1
/ DQS1
DM1
D1
I/ O 2
I/ O 3
I/ O 3
I/ O 4
I/ O 4
I/ O 5
I/ O 6
I/ O 7
I/ O 5
I/ O 6
I/ O7
DQS / CS0 ODT0 CKE0
DQ8
DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
/ DQS
DM
I/ O 0
DM
I/ O0
I/ O 1
I/ O 1
D3
I/ O 2
I/ O 3
I/ O 3
I/ O 4
I/ O 4
I/ O 5
I/ O 6
I/ O 7
I/ O 5
I/ O 6
I/ O7
DQS / CS0 ODT0 CKE0
DQ16
DQ17
DQ18
DQ19
DQ20
DQ21
DQ22
DQ23
/ DQS
DM
I/ O 0
DM
I/ O0
I/ O 1
I/ O 2
DQS3
/ DQS3
DM3
I/ O 1
I/ O 2
D5
I/ O 3
I/ O 3
I/ O 4
I/ O 4
I/ O 5
I/ O 6
I/ O 7
I/ O 5
I/ O 6
I/ O7
DQS / CS0 ODT0 CKE0
DQ24
DQ25
DQ26
DQ27
DQ28
DQ29
DQ30
DQ31
/ DQS
DM
I/ O 0
DM
I/ O0
I/ O 1
I/ O 1
I/ O 2
D7
I/ O 2
I/ O 3
I/ O 3
I/ O 4
I/ O 4
I/ O 5
I/ O 6
I/ O 7
I/ O 5
I/ O 6
I/ O7
DQS5
/ DQS5
DM5
DQS6
/ DQS6
DM6
DQS7
/ DQS7
DM7
SDRAMS
SDRAMS
SDRAMS
SDRAMS
SDRAMS
5.6 pF
8 loads
5.6 pF
8 loads
/ CK0
CK 1
Rev. 0.3 / Aug. 2007
I/ O 1
D2
I/ O 2
I/ O 2
I/ O 3
I/ O 3
I/ O 4
I/ O 4
I/ O 5
I/ O 6
I/ O 7
I/ O 5
I/ O 6
I/ O 7
/ DQS
DM
I/ O 0
DM
I/ O 0
I/ O 1
I/ O 1
D4
I/ O 2
I/ O 2
I/ O 3
I/ O 3
I/ O 4
I/ O 4
I/ O 5
I/ O 6
I/ O 7
I/ O 5
I/ O 6
I/ O 7
/ DQS
DM
I/ O 0
DM
I/ O 0
I/ O 1
I/ O 2
D6
I/ O 3
I/ O 3
I/ O 4
I/ O 4
I/ O 5
I/ O 6
I/ O 7
I/ O 5
I/ O 6
I/ O 7
/ DQS
DM
I/ O 0
DM
I/ O 0
I/ O 3
I/ O 4
I/ O 4
I/ O 5
I/ O 6
I/ O 7
I/ O 5
I/ O 6
I/ O 7
A0
A1
V REF
SDRAMS DO -D15
V DD
SDRAMS DO -D15, V DD and VDDQ
D 16
SDA
Event/WP
WP
R(Event) = 0Ω
SPD
Serial Presense
Detect (SPD)
A2
R(WP) = 0Ω
For normal operation only R(WP) is placed.
For the SPD temperture sensor option
only R(Event) is placed.
I/ O 2
I/ O 3
SA1
SA2
Notes:
I/ O 1
D8
I/ O 2
D 14
DQS / CS1 ODT1 CKE1
/ DQS
I/ O 1
D 12
DQS / CS1 ODT1 CKE1
/ DQS
I/ O 1
I/ O 2
D 10
DQS / CS1 ODT1 CKE1
/ DQS
SA0
D0-D15
D0-D15
D0-D15
D0-D15
D0-D15
VDD SPD
CK 0
/ CK1
DM
I/ O 0
I/ O 1
SCL
10 Ω +/- 5%
BA 0 - BA 2
A0- AN
/ RAS
/ CAS
/ WE
DM
I/ O 0
DQS / CS0 ODT0 CKE0
DQ56
DQ57
DQ58
DQ59
DQ60
DQ61
DQ62
DQ63
D 15
/ DQS
DQS / CS0 ODT0 CKE0
DQ48
DQ49
DQ50
DQ51
DQ52
DQ53
DQ54
DQ55
DQS / CS1 ODT1 CKE1
/ DQS
DQS / CS0 ODT0 CKE0
DQ 40
DQ41
DQ42
DQ43
DQ44
DQ45
DQ46
DQ47
D 13
DQS / CS1 ODT1 CKE1
/ DQS
DQS / CS0 ODT0 CKE0
DQ32
DQ33
DQ34
DQ35
DQ36
DQ37
DQ38
DQ39
D 11
DQS / CS1 ODT1 CKE1
/ DQS
DQS4
/ DQS4
DM4
D9
DQS / CS1 ODT1 CKE1
/ DQS
I/ O 2
DQS2
/ DQS2
DM2
DQS / CS1 ODT1 CKE1
/ DQS
Event
#Unless otherwise noted, resistor values
are 22 Ω9+/- 5% DQ wiring may differ from
that described in this drawing;described
in this drawing; however, DQ/DM/DQS/DQS
relationships are maintained as shown
SDRAMS DO - D15, SPD
7
1200pin Unbuffered DDR2 SDRAM SO-DIMMs
ABSOLUTE MAXIMUM RATINGS
Parameter
Symbol
Value
Unit
Note
VDD
- 1.0 V ~ 2.3 V
V
1
Voltage on VDDL pin relative to Vss
VDDL
-0.5V ~ 2.3 V
V
1
Voltage on VDDQ pin relative to Vss
VDDQ
- 0.5 V ~ 2.3 V
V
1
VIN, VOUT
- 0.5 V ~ 2.3 V
V
1
Storage Temperature
TSTG
-50 ~ +100
Storage Humidity(without condensation)
HSTG
5 to 95
Voltage on VDD pin relative to Vss
Voltage on any pin relative to Vss
C
1
%
1
o
Notes:
1. Stress greater than those listed may cause permanent damage to the device. This is a stress rating only, and device
functional operation at or above the conditions indicated is not implied. Expousure to absolute maximum rating con
ditions for extended periods may affect reliability.
OPERATING CONDITIONS
Parameter
Symbol
Rating
Units
DIMM Operating temperature(ambient)
TOPR
0 ~ +55
oC
Notes
DIMM Barometric Pressure(operating & storage)
PBAR
105 to 69
K Pascal
1
DRAM Component Case Temperature Range
TCASE
0 ~+95
oC
2
Notes:
1. Up to 9850 ft.
2. If the DRAM case temperature is Above 85oC, the Auto-Refresh command interval has to be reduced to
tREFI=3.9us. For Measurement conditions of TCASE, please refer to the JEDEC document JESD51-2.
DC OPERATING CONDITIONS (SSTL_1.8)
Parameter
Min
Max
Unit
VDD
1.7
1.9
V
VDDL
1.7
1.9
V
VDDQ
1.7
1.9
V
1
Input Reference Voltage
VREF
0.49 x VDDQ
0.51 x VDDQ
V
2
EEPROM Supply Voltage
VDDSPD
1.7
3.6
V
Termination Voltage
VTT
VREF-0.04
VREF+0.04
V
Power Supply Voltage
Symbol
Note
3
Notes:
1. VDDQ must be less than or equal to VDD.
2. Peak to peak ac noise on VREF may not exceed +/-2% VREF(dc)
3. VTT of transmitting device must track VREF of receiving device.
Rev. 0.3 / Aug. 2007
8
1200pin Unbuffered DDR2 SDRAM SO-DIMMs
INPUT DC LOGIC LEVEL
Parameter
Symbol
Min
Max
Unit
Input High Voltage
VIH(DC)
VREF + 0.125
VDDQ + 0.3
V
Input Low Voltage
VIL(DC)
-0.30
VREF - 0.125
V
Note
INPUT AC LOGIC LEVEL
Parameter
Symbol
AC Input logic High
AC Input logic Low
DDR2 400/533
DDR2 667
Unit
Min
Max
Min
Max
VIH(AC)
VREF + 0.250
-
VREF + 0.200
-
V
VIL(AC)
-
VREF - 0.250
-
VREF - 0.200
V
AC INPUT TEST CONDITIONS
Symbol
Condition
Value
Units
Notes
0.5 * VDDQ
V
1
VREF
Input reference voltage
VSWING(MAX)
Input signal maximum peak to peak swing
1.0
V
1
SLEW
Input signal minimum slew rate
1.0
V/ns
2, 3
Notes:
1.
2.
Input waveform timing is referenced to the input signal crossing through the VREF level applied to the device
under test.
The input signal minimum slew rate is to be maintained over the range from VREF to VIH(ac) min for rising edges
and the range from VREF to VIL(ac) max for falling edges as shown in the below figure.
3.
AC timings are referenced with input waveforms switching from VIL(ac) to VIH(ac) on the positive transitions
and VIH(ac) to VIL(ac) on the negative transitions.
VDDQ
VIH(ac) min
VIH(dc) min
VREF
VIL(dc) max
VIL(ac) max
VSWING(MAX)
VSS
delta TF
Falling Slew =
delta TR
VREF - VIL(ac) max
delta TF
Rising Slew =
VIH(ac)min - VREF
delta TR
< Figure : AC Input Test Signal Waveform>
Rev. 0.3 / Aug. 2007
9
1200pin Unbuffered DDR2 SDRAM SO-DIMMs
Differential Input AC logic Level
Symbol
Parameter
Min.
Max.
Units
Note
VID (ac)
ac differential input voltage
0.5
VDDQ + 0.6
V
1
VIX (ac)
ac differential cross point voltage
0.5 * VDDQ - 0.175
0.5 * VDDQ + 0.175
V
2
1. VIN(DC) specifies the allowable DC execution of each input of differential pair such as CK, CK, DQS, DQS, LDQS,
LDQS, UDQS and UDQS.
2. VID(DC) specifies the input differential voltage |VTR -VCP | required for switching, where VTR is the true input
(such as CK, DQS, LDQS or UDQS) level and VCP is the complementary input (such as CK, DQS, LDQS or UDQS) level.
The minimum value is equal to VIH(DC) - VIL(DC).
VDDQ
VTR
Crossing point
VID
VIX or VOX
VCP
VSSQ
< Differential signal levels >
Notes:
1. VID(AC) specifies the input differential voltage |VTR -VCP | required for switching, where VTR is the true input signal
(such as CK, DQS, LDQS or UDQS) and VCP is the complementary input signal (such as CK, DQS, LDQS or UDQS).
The minimum value is equal to V IH(AC) - VIL(AC).
2. The typical value of VIX(AC) is expected to be about 0.5 * VDDQ of the transmitting device and VIX(AC) is expected to
track variations in VDDQ . VIX(AC) indicates the voltage at whitch differential input signals must cross.
DIFFERENTIAL AC OUTPUT PARAMETERS
Symbol
VOX (ac)
Parameter
ac differential cross point voltage
Min.
Max.
Units
Note
0.5 * VDDQ - 0.125
0.5 * VDDQ + 0.125
V
1
Notes:
1. The typical value of VOX(AC) is expected to be about 0.5 * VDDQ of the transmitting device and VOX(AC) is expected to
track variations in VDDQ . VOX(AC) indicates the voltage at whitch differential output signals must cross.
Rev. 0.3 / Aug. 2007
10
1200pin Unbuffered DDR2 SDRAM SO-DIMMs
OUTPUT BUFFER LEVELS
OUTPUT AC TEST CONDITIONS
Symbol
Parameter
SSTL_18
Units
Notes
VOTR
Output Timing Measurement Reference Level
0.5 * VDDQ
V
1
Notes:
1. The VDDQ of the device under test is referenced.
OUTPUT DC CURRENT DRIVE
Symbol
Parameter
SSTl_18
Units
Notes
IOH(dc)
Output Minimum Source DC Current
- 13.4
mA
1, 3, 4
IOL(dc)
Output Minimum Sink DC Current
13.4
mA
2, 3, 4
Notes:
1. VDDQ = 1.7 V; VOUT = 1420 mV. (VOUT - VDDQ)/IOH must be less than 21 ohm for values of VOUT between VDDQ and
VDDQ - 280 mV.
2. VDDQ = 1.7 V; VOUT = 280 mV. VOUT/IOL must be less than 21 ohm for values of VOUT between 0 V and 280 mV.
3. The dc value of VREF applied to the receiving device is set to VTT
4. The values of IOH(dc) and IOL(dc) are based on the conditions given in Notes 1 and 2. They are used to test device
drive current capability to ensure VIH min plus a noise margin and VIL max minus a noise margin are delivered to an
SSTL_18 receiver.
The actual current values are derived by shifting the desired driver operating point along a 21 ohm load line to define
a convenient driver current for measurement.
Rev. 0.3 / Aug. 2007
11
1200pin Unbuffered DDR2 SDRAM SO-DIMMs
PIN Capacitance (VDD=1.8V,VDDQ=1.8V, TA=25℃. f=1MHz )
256MB : HYMP532S64B[L]P6
Pin
Symbol
Min
Max
Unit
CK, CK
CCK
12
15
pF
CKE, ODT,CS
CI1
27
30
pF
Address, RAS, CAS, WE
CI2
25
32
pF
DQ, DM, DQS, DQS
CIO
6.0
7.5
pF
Symbol
Min
Max
Unit
CK, CK
CCK
17
20
pF
CKE, ODT,CS
CI1
22
25
pF
Address, RAS, CAS, WE
CI2
28.5
37.0
pF
DQ, DM, DQS, DQS
CIO
10.0
12.0
pF
Symbol
Min
Max
Unit
CK, CK
CCK
25
49
pF
CKE, ODT,CS
CI1
32
58
pF
Address, RAS, CAS, WE
CI2
47
96
pF
DQ, DM, DQS, DQS
CIO
16
20
pF
512MB : HYMP564S64B[L]P6
Pin
1GB : HYMP512S64B[L]P8
Pin
Notes:
1. Pins not under test are tied to GND.
2. These values are guaranteed by design and tested on a sample basis only.
Rev. 0.3 / Aug. 2007
12
1200pin Unbuffered DDR2 SDRAM SO-DIMMs
IDD SPECIFICATIONS (TCASE : 0 to 95oC)
256MB, 32M x 64 SO- DIMM : HYMP532S64B[L]P6
Symbol
E3
(DDR 400@CL 3)
C4
(DDR 533@CL 4)
Y5
(DDR 667@CL 5)
Unit
IDD0
440
460
480
mA
IDD1
520
540
560
mA
IDD2P
32
32
32
mA
IDD2Q
160
180
200
mA
IDD2N
180
200
220
mA
IDD3P(F)
120
120
140
mA
IDD3P(S)
48
48
48
mA
IDD3N
200
240
260
mA
IDD4W
840
1000
1120
mA
IDD4R
800
880
1000
mA
IDD5B
640
680
720
mA
note
IDD6
20
20
20
mA
1
IDD6(L)
16
16
16
mA
1
IDD7
1320
1340
1360
mA
512MB, 64M x 64 SO - DIMM : HYMP564S64B[L]P6
Symbol
E3
(DDR 400@CL 3)
C4
(DDR 533@CL 4)
Y5
(DDR 667@CL 5)
S5
(DDR 800@CL 5)
Unit
IDD0
640
700
740
816
mA
IDD1
720
780
820
888
mA
IDD2P
64
64
64
64
mA
IDD2Q
320
360
400
440
mA
IDD2N
360
400
440
480
mA
IDD3P(F)
240
240
280
280
mA
note
IDD3P(S)
96
96
96
96
mA
IDD3N
400
480
520
576
mA
IDD4W
1040
1240
1380
1488
mA
IDD4R
1000
1120
1260
1388
mA
IDD5B
840
920
980
1088
mA
IDD6
40
40
40
40
mA
1
IDD6(L)
32
32
32
32
mA
1
IDD7
1520
1580
1620
1688
mA
Notes:
1. IDD6 current values are guaranteed up to Tcase of 85℃ max.
Rev. 0.3 / Aug. 2007
13
1200pin Unbuffered DDR2 SDRAM SO-DIMMs
1GB, 128M x 64 SO - DIMM : HYMP512S64B[L]P8
Symbol
E3
(DDR 400@CL 3)
C4
(DDR 533@CL 4)
Y5
(DDR 667@CL 5)
S5
(DDR 800@CL 5)
Unit
IDD0
1040
1080
1200
1328
mA
IDD1
1120
1160
1240
1368
mA
IDD2P
128
128
128
128
mA
IDD2Q
480
640
720
800
mA
note
IDD2N
560
720
800
880
mA
IDD3P(F)
480
480
560
560
mA
IDD3P(S)
192
192
192
192
mA
IDD3N
800
880
960
1056
mA
IDD4W
1520
1800
2000
2288
mA
IDD4R
1440
1640
1920
2208
mA
IDD5B
1680
1800
1920
2128
mA
IDD6
80
80
80
80
mA
1
1
IDD6(L)
64
64
64
64
mA
IDD7
2160
2200
2240
2688
mA
Notes:
1. IDD6 current values are guaranteed up to Tcase of 85℃ max.
Rev. 0.3 / Aug. 2007
14
1200pin Unbuffered DDR2 SDRAM SO-DIMMs
IDD Meauarement Conditions
Symbol
Conditions
Units
IDD0
Operating one bank active-precharge current; tCK = tCK(IDD), tRC = tRC(IDD), tRAS = tRASmin(IDD);CKE is HIGH, CS is HIGH between valid commands;Address bus inputs are SWITCHING;Data bus
inputs are SWITCHING
mA
IDD1
Operating one bank active-read-precharge current ; IOUT = 0mA;BL = 4, CL = CL(IDD), AL = 0;
tCK = tCK(IDD), tRC = tRC (IDD), tRAS = tRASmin(IDD), tRCD = tRCD(IDD) ; CKE is HIGH, CS is HIGH
between valid commands ; Address bus inputs are SWITCHING ; Data pattern is same as IDD4W
mA
IDD2P
Precharge power-down current ; All banks idle ; tCK = tCK(IDD) ; CKE is LOW ; Other control and address
bus inputs are STABLE; Data bus inputs are FLOATING
mA
IDD2Q
Precharge quiet standby current;All banks idle; tCK = tCK(IDD);CKE is HIGH, CS is HIGH; Other control and
address bus inputs are STABLE; Data bus inputs are FLOATING
mA
IDD2N
Precharge standby current; All banks idle; tCK = tCK(IDD); CKE is HIGH, CS is HIGH; Other control and
address bus inputs are SWITCHING; Data bus inputs are SWITCHING
mA
IDD3P
Active power-down current; All banks open; tCK = tCK(IDD); CKE is LOW; Fast PDN Exit MRS(12) = 0
Other control and address bus inputs are STABLE; Data bus inputs are FLOATSlow PDN Exit MRS(12) = 1
ING
IDD3N
Active standby current; All banks open; tCK = tCK(IDD), tRAS = tRASmax(IDD), tRP =tRP(IDD); CKE is
HIGH, CS is HIGH between valid commands; Other control and address bus inputs are SWITCHING; Data bus
inputs are SWITCHING
mA
IDD4W
Operating burst write current; All banks open, Continuous burst writes; BL = 4, CL = CL(IDD), AL = 0; tCK
= tCK(IDD), tRAS = tRASmax(IDD), tRP = tRP(IDD); CKE is HIGH, CS is HIGH between valid commands;
Address bus inputs are SWITCHING; Data bus inputs are SWITCHING
mA
IDD4R
Operating burst read current; All banks open, Continuous burst reads, IOUT = 0mA; BL = 4, CL = CL(IDD),
AL = 0; tCK = tCK(IDD), tRAS = tRASmax(IDD), tRP = tRP(IDD); CKE is HIGH, CS is HIGH between valid commands; Address bus inputs are SWITCHING;; Data pattern is same as IDD4W
mA
IDD5B
Burst refresh current; tCK = tCK(IDD); Refresh command at every tRFC(IDD) interval; CKE is HIGH, CS is
HIGH between valid commands; Other control and address bus inputs are SWITCHING; Data bus inputs are
SWITCHING
mA
IDD6
Self refresh current; CK and CK at 0V; CKE ≤ 0.2V; Other control and address bus inputs are FLOATING; Data
bus inputs are FLOATING. IDD6 current values are guaranted up to Tcase of 85℃ max.
mA
IDD7
Operating bank interleave read current; All bank interleaving reads, IOUT = 0mA; BL = 4, CL = CL(IDD),
AL = tRCD(IDD)-1*tCK(IDD); tCK = tCK(IDD), tRC = tRC(IDD), tRRD = tRRD(IDD), tRCD = 1*tCK(IDD); CKE is
HIGH, CS is HIGH between valid commands; Address bus inputs are STABLE during DESELECTs; Data pattern is
same as IDD4R; - Refer to the following page for detailed timing conditions
mA
mA
mA
Notes:
1. IDD specifications are tested after the device is properly initialized
2. Input slew rate is specified by AC Parametric Test Condition
3. IDD parameters are specified with ODT disabled.
4. Data bus consists of DQ, DM, DQS, DQS, RDQS, RDQS, LDQS, LDQS, UDQS, and UDQS. IDD values must be met with all combinations
of EMRS bits 10 and 11.
5. Definitions for IDD
LOW is defined as Vin ≤ VILAC(max)
HIGH is defined as Vin ≥ VIHAC(min)
STABLE is defined as inputs stable at a HIGH or LOW level
FLOATING is defined as inputs at VREF = VDDQ/2
SWITCHING is defined as: inputs changing between HIGH and LOW every other clock cycle (once per two clocks) for address and
control signals, and inputs changing between HIGH and LOW every other data transfer (once per clock)
for DQ signals not including masks or strobes.
Rev. 0.3 / Aug. 2007
15
1200pin Unbuffered DDR2 SDRAM SO-DIMMs
Electrical Characteristics & AC Timings
Speed Bins and CL,tRCD,tRP,tRC and tRAS for Corresponding Bin
Speed
DDR2-800
DDR2-667
DDR2-533
DDR2-400
Bin(CL-tRCD-tRP)
5-5-5
5-5-5
3-3-3
4-4-4
Parameter
min
min
min
min
CAS Latency
5
5
3
5
ns
tRCD
12.5
15
11.25
15
ns
tRP
12.5
15
11.25
15
ns
tRAS
45
45
45
40
ns
tRC
57.25
60
56.25
55
ns
Unit
AC Timing Parameters by Speed Grade
DDR2-400
Parameter
DDR2-533
Symbol
Unit
Min
Max
Min
Max
Note
Data-Out edge to Clock edge Skew
tAC
-600
+600
-500
500
ps
DQS-Out edge to Clock edge Skew
tDQSCK
-500
+500
-500
450
ns
Clock High Level Width
tCH
0.45
0.55
0.45
0.55
CK
Clock Low Level Width
tCL
0.45
0.55
0.45
0.55
CK
Clock Half Period
tHP
min(tCL,tCH)
-
min
(tCL,tCH)
-
ns
System Clock Cycle Time
tCK
5000
8000
3750
8000
ps
DQ and DM input setup time(differential strobe)
tDS
150
-
100
-
ps
1
DQ and DM input hold time(differential strobe)
tDH
275
-
225
-
ps
1
DQ and DM input setup time(single ended strobe)
tDS1
25
-
-25
-
ps
1
DQ and DM input hold time(single ended strobe)
tDH1
25
-
-25
-
ps
1
Control & Address input Pulse Width for each input
tIPW
0.6
-
0.6
-
tCK
tDIPW
0.35
-
0.35
-
tCK
tHZ
-
tAC max
-
tAC max
ps
DQ and DM input pulse witdth for each input
Data-out high-impedance window from CK, /CK
tLZ(DQS)
tAC min
tAC max
tAC min
tAC max
ps
DQ low-impedance time from CK/CK
tLZ(DQ)
2*tAC min
tAC max
2*tAC min
tAC max
ps
DQS-DQ skew for DQS and associated DQ signals
tDQSQ
-
350
-
300
ps
tQHS
-
450
-
400
ps
tQH
tHP - tQHS
-
tHP - tQHS
-
ps
First DQS latching transition to associated clock edge
tDQSS
-0.25
+ 0.25
-0.25
+ 0.25
tCK
DQS input high pulse width
tDQSH
0.35
-
0.35
-
tCK
DQS input low pulse width
tDQSL
0.35
-
0.35
-
tCK
DQS low-impedance time from CK/CK
DQ hold skew factor
DQ/DQS output hold time from DQS
Rev. 0.3 / Aug. 2007
16
1200pin Unbuffered DDR2 SDRAM SO-DIMMs
- continued DDR2-400
Parameter
DDR2-533
Symbol
Unit
Min
Max
Min
Max
DQS falling edge to CK setup time
tDSS
0.2
-
0.2
-
tCK
DQS falling edge hold time from CK
tDSH
0.2
-
0.2
-
tCK
Mode register set command cycle time
tMRD
2
-
2
-
tCK
Write postamble
tWPST
0.4
0.6
0.4
0.6
tCK
Write preamble
tWPRE
0.35
-
0.35
-
tCK
Address and control input setup time
tIS
350
-
250
-
ps
Address and control input hold time
tIH
475
-
375
-
ps
Read preamble
tRPRE
0.9
1.1
0.9
1.1
tCK
Read postamble
tRPST
0.4
0.6
0.4
0.6
tCK
Auto-Refresh to Active/Auto-Refresh command
period
tRFC
105
-
105
-
ns
Row Active to Row Active Delay for 1KB page size
tRRD
7.5
-
7.5
-
ns
Row Active to Row Active Delay for 2KB page size
tRRD
10
-
10
-
ns
Four Activate Window for 1KB page size
tFAW
37.5
-
37.5
-
ns
Four Activate Window for 2KB page size
tFAW
50
-
50
-
ns
CAS to CAS command delay
tCCD
2
Write recovery time
tWR
15
-
15
-
ns
Auto Precharge Write Recovery + Precharge Time
tDAL
WR+tRP
-
tWR+tRP
-
tCK
Write to Read Command Delay
tWTR
10
-
7.5
-
ns
Internal read to precharge command delay
tRTP
7.5
7.5
ns
Exit self refresh to a non-read command
tXSNR
tRFC + 10
tRFC + 10
ns
Exit self refresh to a read command
tXSRD
200
-
200
-
tCK
tXP
2
-
2
-
tCK
Exit active power down to read command
tXARD
2
2
tCK
Exit active power down to read command
(Slow exit, Lower power)
tXARDS
6 - AL
6 - AL
tCK
tCKE
3
3
tCK
tAOND
2
2
2
tAC(min)
tAC(max)+1
tAC(min)+2
2tCK+
tAC(max)+1
2.5
AOF
AOFPD
Exit precharge power down to any non-read
command
CKE minimum pulse width
(high and low pulse width)
ODT turn-on delay
t
ODT turn-on
ODT turn-on(Power-Down mode)
t
AONPD
t
ODT turn-off delay
Rev. 0.3 / Aug. 2007
AOFD
t
ODT turn-off
ODT turn-off (Power-Down mode)
AON
t
2
Note
tCK
2
tCK
tAC(min)
tAC(max)+1
ns
tAC(min)+2
2tCK+tAC(m
ax)+1
ns
2.5
2.5
2.5
tCK
tAC(min)
tAC(max)+0
.6
tAC(min)
tAC(max)+
0.6
ns
2.5
2.5
tAC(min)+2
2.5tCK+tAC(
max)+1
ns
17
1200pin Unbuffered DDR2 SDRAM SO-DIMMs
- continued DDR2-400
Parameter
DDR2-533
Symbol
Unit
Min
Max
Min
Note
Max
ODT to power down entry latency
tANPD
tAC(min)
tAC(max)+0.
6
3
tCK
ODT power down exit latency
tAXPD
tAC(min)+2
2.5tCK+
tAC(max)+1
8
tCK
OCD drive mode output delay
tOIT
3
0
tDelay
8
tIS+tCK+tIH
tREFI
-
7.8
-
7.8
us
2
tREFI
-
3.9
-
3.9
us
3
Minimum time clocks remains ON after
CKE asynchronously drops LOW
Average periodic Refresh Interval
12
ns
ns
Note :
1. For details and notes, please refer to the relevant HYNIX component datasheet(HY5PS12[8/16]21B[L]FP).
2. 0°C ≤ TCASE ≤ 85°C
3. 85°C < TCASE ≤ 95°C
Rev. 0.3 / Aug. 2007
18
1200pin Unbuffered DDR2 SDRAM SO-DIMMs
Parameter
Symbol
DDR2-667
DDR2-800
min
max
min
max
DQ output access time from CK/CK
tAC
-450
+450
-400
+400
DQS output access time from CK/CK
Unit
Note
ps
tDQSCK
-400
+400
-350
+350
ps
CK high-level width
tCH
0.45
0.55
0.45
0.55
tCK
CK low-level width
tCL
0.45
0.55
0.45
0.55
tCK
CK half period
tHP
min(tCL,
tCH)
-
min(tCL,
tCH)
-
ps
Clock cycle time, CL=x
tCK
3000
8000
2500
tDS
100
-
50
-
ps
1
tDH
175
-
125
-
ps
1
Control & Address input pulse width for each
input
tIPW
0.6
-
0.6
-
tCK
DQ and DM input pulse width for each input
tDIPW
0.35
-
0.35
-
tCK
Data-out high-impedance time from CK/CK
tHZ
-
tAC max
-
tAC max
ps
DQS low-impedance time from CK/CK
tLZ(DQS)
tAC min
tAC max
tAC min
tAC max
ps
DQ low-impedance time from CK/CK
tLZ(DQ)
2*tAC min
tAC max
2*tAC min
tAC max
ps
DQS-DQ skew for DQS and associated DQ
signals
tDQSQ
-
240
-
200
ps
DQ and DM input setup time
(differential strobe)
DQ and DM input hold time
(differential strobe)
ps
DQ hold skew factor
tQHS
-
340
-
300
ps
DQ/DQS output hold time from DQS
tQH
tHP - tQHS
-
tHP - tQHS
-
ps
First DQS latching transition to associated
clock edge
tDQSS
- 0.25
+ 0.25
- 0.25
+ 0.25
tCK
DQS input high pulse width
tDQSH
0.35
-
0.35
-
tCK
DQS input low pulse width
tDQSL
0.35
-
0.35
-
tCK
DQS falling edge to CK setup time
tDSS
0.2
-
0.2
-
tCK
DQS falling edge hold time from CK
tDSH
0.2
-
0.2
-
tCK
Mode register set command cycle time
tMRD
2
-
2
-
tCK
Write postamble
tWPST
0.4
0.6
0.4
0.6
tCK
Write preamble
tWPRE
0.35
-
0.35
-
tCK
tIS
200
-
175
-
ps
Address and control input setup time
Address and control input hold time
tIH
275
-
250
-
ps
Read preamble
tRPRE
0.9
1.1
0.9
1.1
tCK
Read postamble
tRPST
0.4
0.6
0.4
0.6
tCK
Activate to precharge command
tRAS
45
70000
45
70000
ns
Active to active command period for 1KB page
size products
tRRD
7.5
-
7.5
-
ns
Active to active command period for 2KB page
size products
tRRD
10
-
10
-
ns
Four Active Window for 1KB page size products
tFAW
37.5
-
35
-
ns
Four Active Window for 2KB page size products
tFAW
50
-
45
-
ns
Rev. 0.3 / Aug. 2007
19
1200pin Unbuffered DDR2 SDRAM SO-DIMMs
- continued Parameter
Symbol
DDR2-667
min
DDR2-800
max
min
max
Note
CAS to CAS command delay
tCCD
2
Write recovery time
tWR
15
-
15
-
ns
Auto precharge write recovery + precharge
time
tDAL
WR+tRP
-
WR+tRP
-
tCK
Internal write to read command delay
tWTR
7.5
-
7.5
-
ns
Internal read to precharge command delay
tRTP
7.5
Exit self refresh to a non-read command
tXSNR
tRFC + 10
Exit self refresh to a read command
tXSRD
200
-
200
-
tCK
tXP
2
-
2
-
tCK
tXARD
2
2
tCK
tXARDS
7 - AL
8 - AL
tCK
tCKE
3
3
tCK
AOND
2
2
2
2
tCK
tAON
tAC(min)
tAC(max)+0.7
tAC(min)
tAC(max)
+0.7
ns
tAONPD
tAC(min)+
2
2tCK+
tAC(max)+1
tAC(min)
+2
2tCK+
tAC(max)+1
ns
2.5
2.5
2.5
2.5
tCK
tAOF
tAC(min)
tAC(max)+
0.6
tAC(min)
tAC(max)
+0.6
ns
ODT turn-off (Power-Down mode)
tAOFPD
tAC(min)+
2
2.5tCK+
tAC(max)+1
tAC(min)
+2
2.5tCK+
tAC(max)+1
ns
ODT to power down entry latency
tANPD
3
3
ODT power down exit latency
tAXPD
8
8
OCD drive mode output delay
tOIT
0
tDelay
tIS+tCK+tI
H
tREFI
-
7.8
-
7.8
us
2
tREFI
-
3.9
-
3.9
us
3
Exit precharge power down to any non-read
command
Exit active power down to read command
Exit active power down to read command
(Slow exit, Lower power)
CKE minimum pulse width(high and low pulse
width)
ODT turn-on delay
t
ODT turn-on
ODT turn-on(Power-Down mode)
ODT turn-off delay
ODT turn-off
Minimum time clocks remains ON after CKE
asynchronously drops LOW
Average periodic Refresh Interval
t
AOFD
2
Unit
tCK
7.5
ns
tRFC + 10
12
0
ns
tCK
tCK
12
tIS+tCK
+tIH
ns
ns
Note :
1. For details and notes, please refer to the relevant HYNIX component datasheet(HY5PS12[8/16]21B[L]FP).
2. 0°C ≤ TCASE ≤ 85°C
3. 85°C < TCASE ≤ 95°C
Rev. 0.3 / Aug. 2007
20
1200pin Unbuffered DDR2 SDRAM SO-DIMMs
PACKAGE OUTLINE
32Mx64 - HYMP532S64B[L]P6
Front
67.60
2.00 Min
Side
3.8 max
4.00 +/-0.10
30.00
20.00
Detail-B
2.15
PIN 39
Detail-A
PIN 41
11.40
1.80±0.10
4.20
47.40
11.40
1.50±0.10
2.45
PIN 2
PIN 199
6.00
PIN 1
Back
Detail-B
1.00 ± 0.10
47.40
PIN 200
PIN 40 PIN 42
Detail of Contacts A
Detail of Contacts B (Front)
Detail of Contacts B (Back)
0.60
1.50
4.00±0.10
2.55
0.20±0.15
4.20
2.70±0.10
0.45±0.03
2.40±0.10
1.80
1.0±0.05
4.20
Note:
1. All dimensions are in millimeters.
2. All outline dimensions and tolerances follow the JEDEC standard.
Rev. 0.3 / Aug. 2007
21
1200pin Unbuffered DDR2 SDRAM SO-DIMMs
PACKAGE OUTLINE
64Mx64 - HYMP564S64B[L]P6
Front
67.60
2.00 Min
Side
3.8 max
4.00 +/-0.10
30.00
20.00
Detail-B
2.15
PIN 39
Detail-A
PIN 41
11.40
1.80±0.10
4.20
47.40
11.40
1.50±0.10
PIN 2
Back
Detail-B
1.00 ± 0.10
47.40
PIN 200
PIN 40 PIN 42
Detail of Contacts A
Detail of Contacts B (Front)
Detail of Contacts B (Back)
2.55
0.20±0.15
4.20
0.60
2.70±0.10
1.50
4.00±0.10
2.45
PIN 199
6.00
PIN 1
0.45±0.03
2.40±0.10
1.80
1.0±0.05
4.20
Note:
1. All dimensions are in millimeters.
2. All outline dimensions and tolerances follow the JEDEC standard.
Rev. 0.3 / Aug. 2007
22
1200pin Unbuffered DDR2 SDRAM SO-DIMMs
PACKAGE OUTLINE
128Mx64 - HYMP512S64B[L]P8
Front
67.60
2.00 Min
Side
3.8 max
4.00 +/-0.10
30.00
20.00
Detail-B
2.15
PIN 39
Detail-A
PIN 41
11.40
1.80±0.10
4.20
2.45
47.40
11.40
1.50±0.10
PIN 2
PIN 199
6.00
PIN 1
1.00 ± 0.10
Back
Detail-B
47.40
PIN 200
PIN 40 PIN 42
Detail of Contacts A
Detail of Contacts B (Front)
Detail of Contacts B (Back)
0.60
1.50
4.00±0.10
2.55
0.20±0.15
4.20
2.70±0.10
0.45±0.03
2.40±0.10
1.80
1.0±0.05
4.20
Note:
1. All dimensions are in millimeters.
2. All outline dimensions and tolerances follow the JEDEC standard.
Rev. 0.3 / Aug. 2007
23
1200pin Unbuffered DDR2 SDRAM SO-DIMMs
REVISION HISTORY
Revision
History
Date
First Version Release
Aug. 2005
Corrected editorial typos
Sep. 2005
0.2
Updated IDD all values
Aug. 2006
0.3
DIMM outline corrected
Aug. 2007
0.1
Rev. 0.3 / Aug. 2007
Remark
24