Samsung 256MB, DDR II SDRAM, 533MHz, soDIMM Datasheet

256MB, 512MB, 1GB Unbuffered SODIMMs DDR2 SDRAM

DDR2 Unbuffered SODIMM

200pin Unbuffered SODIMM based on 512Mb B-die

64bit Non-ECC

INFORMATION IN THIS DOCUMENT IS PROVIDED IN RELATION TO SAMSUNG PRODUCTS,

AND IS SUBJECT TO CHANGE WITHOUT NOTICE.

NOTHING IN THIS DOCUMENT SHALL BE CONSTRUED AS GRANTING ANY LICENSE,

EXPRESS OR IMPLIED, BY ESTOPPEL OR OTHERWISE,

TO ANY INTELLECTUAL PROPERTY RIGHTS IN SAMSUNG PRODUCTS OR TECHNOLOGY. ALL

INFORMATION IN THIS DOCUMENT IS PROVIDED

ON AS "AS IS" BASIS WITHOUT GUARANTEE OR WARRANTY OF ANY KIND.

1. For updates or additional information about Samsung products, contact your nearest Samsung office.

2. Samsung products are not intended for use in life support, critical care, medical, safety equipment, or similar applications where Product failure couldresult in loss of life or personal or physical harm, or any military or defense application, or any governmental procurement to which special terms or provisions may apply.

* Samsung Electronics reserves the right to change products or specification without notice.

Rev. 1.5 Aug. 2005

256MB, 512MB, 1GB Unbuffered SODIMMs

DDR2 Unbuffered SODIMM Ordering Information

Part Number Density Organization

M470T3354BG(Z)3-CD5/CC


M470T3354BZ3-LD5/CC

M470T3354BZ0-LD5/CC



M470T6554BZ3-LD5/CC

M470T6554BZ0-LD5/CC

M470T2953BS(Y)3-CD5/CC

M470T2953BS(Y)0-CD5/CC

M470T2953BY3-LD5/CC

M470T2953BY0-LD5/CC

256MB

256MB

256MB

256MB

512MB

512MB

512MB

512MB

1GB

1GB

1GB

1GB

Note: “Z” and “Y” of Part number(11th digit) stand for Lead-free products.

Note: “3” of Part number(12th digit) stand for Dummy Pad PCB products.

32Mx64

32Mx64

32Mx64

32Mx64

64Mx64

64Mx64

64Mx64

64Mx64

128Mx64

128Mx64

128Mx64

128Mx64

Features

Component Composition

32Mx16(K4T51163QB)*4

32Mx16(K4T51163QB)*4

32Mx16(K4T51163QB)*4

32Mx16(K4T51163QB)*4

32Mx16(K4T51163QB)*8

32Mx16(K4T51163QB)*8

32Mx16(K4T51163QB)*8

32Mx16(K4T51163QB)*8

64Mx8(K4T51083QB)*16

64Mx8(K4T51083QB)*16

64Mx8(K4T51083QB)*16

64Mx8(K4T51083QB)*16

• Performance range

Speed@CL3

Speed@CL4

CL-tRCD-tRP

D5(DDR2-533)

400

533

4-4-4

CC(DDR2-400)

400

400

3-3-3

Unit

Mbps

Mbps

CK

• JEDEC standard 1.8V ± 0.1V Power Supply

• V

DDQ

= 1.8V ± 0.1V

• 200 MHz f

CK

for 400Mb/sec/pin, 267MHz f

CK

for 533Mb/sec/pin

• 4 Banks

• Posted CAS

• Programmable CAS Latency: 3, 4, 5

• Programmable Additive Latency: 0, 1 , 2 , 3 and 4

• Write Latency(WL) = Read Latency(RL) -1

• Burst Length: 4 , 8(Interleave/nibble sequential)

• Programmable Sequential / Interleave Burst Mode

• Bi-directional Differential Data-Strobe (Single-ended data-strobe is an optional feature)

• Off-Chip Driver(OCD) Impedance Adjustment

• On Die Termination

• Average Refresh Period 7.8us at lower than a T

CASE

85 °C, 3.9us at 85°C < T

CASE

< 95 °C

- support High Temperature Self-Refresh rate enable feature

• Package: 60ball FBGA - 64Mx8 , 84ball FBGA - 32Mx16

• All of Lead-free products are compliant for RoHS

Note: For detailed DDR2 SDRAM operation, please refer to Samsung’s Device operation & Timing diagram.

DDR2 SDRAM

2

2

2

2

2

2

Number of

Rank

1

1

2

2

1

1

Height

30mm

30mm

30mm

30mm

30mm

30mm

30mm

30mm

30mm

30mm

30mm

30mm

Address Configuration

Organization

64Mx8(512Mb) based Module

32Mx16(512Mb) based Module

Row Address

A0-A13

A0-A12

Column Address

A0-A9

A0-A9

Bank Address

BA0-BA1

BA0-BA1

Auto Precharge

A10

A10

Rev. 1.5 Aug. 2005


Pin Configurations (Front side/Back side)

Pin

1

23

25

27

29

31

17

19

21

7

9

3

5

11

13

15

43

45

47

49

33

35

37

39

41

Pin

52

74

76

78

80

82

68

70

72

54

56

58

60

62

64

66

94

96

98

100

84

86

88

90

92

Pin

51

73

75

77

79

81

67

69

71

53

55

57

59

61

63

65

93

95

97

99

83

85

87

89

91

Pin

2

24

26

28

30

32

18

20

22

4

6

8

10

12

14

16

44

46

48

50

34

36

38

40

42

Front

V

REF

V

SS

DQ0

DQS1

V

SS

DQ10

DQ11

V

SS

V

SS

DQ16

DQ17

V

SS

DQS2

DQ1

V

SS

DQS0

DQS0

V

SS

DQ2

DQ3

V

SS

DQ8

DQ9

V

SS

DQS1

Back

V

SS

DQ4

CK0

V

SS

DQ14

DQ15

V

SS

V

SS

DQ20

DQ21

V

SS

NC

V

SS

DQ12

DQ13

V

SS

DM1

V

SS

CK0

DQ5

V

SS

DM0

V

SS

DQ6

DQ7

Front

DQS2

V

SS

DQ18

NC

V

SS

DQ26

DQ27

V

SS

CKE0

V

DD

NC

BA2

V

DD

A12

DQ19

V

SS

DQ24

DQ25

V

SS

DM3

A9

A8

V

DD

A5

A3

Back

DM2

V

SS

DQ22

DQ23

V

SS

DQ28

DQ29

V

SS

DQS3

DQS3

V

SS

DQ30

DQ31

V

SS

NC/CKE1

V

DD

NC

NC

V

DD

A11

A7

A6

V

DD

A4

A2

Pin

101

117

119

121

123

125

127

129

131

103

105

107

109

111

113

115

143

145

147

149

133

135

137

139

141

Front

A1

V

DD

A10/AP

BA0

WE

V

DD

CAS

NC/S1

V

DD

NC/ODT1

V

SS

DQ32

DQ33

V

SS

DQS4

DQS4

V

SS

DQ34

DQ35

V

SS

DQ40

DQ41

V

SS

DM5

V

SS

Note : NC = No Connect; NC, TEST(pin 163)is for bus analysis tool and is not connected on normal memory modules.

Pin

102

118

120

122

124

126

128

130

132

104

106

108

110

112

114

116

144

146

148

150

134

136

138

140

142

Pin Description

Pin Name

CK0,CK1

CK0,CK1

CKE0,CKE1

RAS

CAS

WE

S0,S1

A0~A9, A11~A13

A10/AP

BA0,BA1

ODT0,ODT1

SCL

Function

Clock Inputs, positive line

Clock Inputs, negative line

Clock Enables

Row Address Strobe

Column Address Strobe

Write Enable

Chip Selects

Address Inputs

Address Input/Autoprecharge

SDRAM Bank Address

On-die termination control

Serial Presence Detect(SPD) Clock Input

Pin Name

SDA

SA1,SA0

DQ0~DQ63

DM0~DM7

DQS0~DQS7

DQS0~DQS7

TEST

V

DD

V

SS

V

REF

V

DD

SPD

NC

Back

A0

V

DD

BA1

RAS

S0

V

DD

ODT0

A13

V

DD

NC

V

SS

DQ36

DQ37

V

SS

DM4

V

SS

DQ38

DQ39

V

SS

DQ44

DQ45

V

SS

DQS5

DQS5

V

SS

DDR2 SDRAM

Pin

151

167

169

171

173

175

177

179

181

153

155

157

159

161

163

165

193

195

197

199

183

185

187

189

191

Front

DQ42

DQ57

V

SS

DM7

V

SS

DQ58

DQ59

V

SS

SDA

SCL

V

DD

SPD

DQ43

V

SS

DQ48

DQ49

V

SS

NC, TEST

V

SS

DQS6

DQS6

V

SS

DQ50

DQ51

V

SS

DQ56

Pin

152

168

170

172

174

176

178

180

182

154

156

158

160

162

164

166

194

196

198

200

184

186

188

190

192

Function

SPD Data Input/Output

SPD address

Data Input/Output

Data Masks

Data strobes

Data strobes complement

Logic Analyzer specific test pin (No connect on So-DIMM)

Core and I/O Power

Ground

Input/Output Reference

SPD Power

Spare pins, No connect

Back

DQ46

V

SS

DM6

V

SS

DQ54

DQ55

V

SS

DQ60

DQ61

V

SS

DQS7

DQS7

V

SS

DQ62

DQ47

V

SS

DQ52

DQ53

V

SS

CK1

CK1

DQ63

V

SS

SA0

SA1

Rev. 1.5 Aug. 2005


Input/Output Functional Description

Symbol

CK0-CK1

CK0-CK1

CKE0-CKE1

S0-S1

BA0~BA1

ODT0~ODT1

A0~A9,

A10/AP,

A11~A13

DQ0~DQ63

DM0~DM7

DQS0~DQS7

DQS0~DQS7

Type

Input

Input

Input

RAS, CAS, WE Input

Input

Input

Input

In/Out

Input

In/Out

Function

The system clock inputs. All address and command lines are sampled on the cross point of the rising edge of CK and falling edge of CK . A Delay Locked Loop (DLL) circuit is driven from the clock input and output timing for read operations is synchronized to the input clock.

Activates the DDR2 SDRAM CK signal when high and deactivates the CK signal when low, By deactivating the clocks, CKE low initiates the Power Down mode or the Self Refesh mode.

Enables the associated DDR2 SDRAM command decoder when low and disables the command decoder when high. When the command decoder is disabled, new commands are ignored but previous operations continue. Rank 0 is selected by S0,

Rank 1 is selected by S1. Ranks are also called “Physical banks”.

When sampled at the cross point of the rising edge of CK and falling edge of CK, CAS, RAS, and WE define the operation to be executed by the SDRAM.

Selects which DDR2 SDRAM internal bank is activated.

Asserts on-die termination for DQ, DM, DQS, and DQS signals if enabled via the DDR2 SDRAM Extended Mode Register

Set (EMRS).

During a Bank Activate command cycle, defines the row address when sampled at the cross point of the rising edge of CK and falling edge of CK. During a Read or Write command cycle, defines the column address when sampled at the cross point of the rising edge of CK and falling edge of CK. In addition to the column address, AP is used to invoke autoprecharge operation at the end of the burst read or write cycle. If AP is high, autoprecharge is selected and BA0-BAn defines the bank to be precharged. If AP is low, autoprecharge is disabled. During a Precharge command cycle, AP is used in conjunction with BA0-BAn to control which bank(s) to precharge. If AP is high, all banks will be pecharged regardiess of the state of

BA0-BAn inputs. If AP is low, then BA0-BAn are used to define which bank to precharge.

Data Input/Output pins.

The data write masks, associated with one data byte. In Write mode, DM operates as a byte mask by allowing input data to be written if it is low but blocks the write operation if it is high. In

Read mode, DM lines have no effect.

The data strobes, associated with one data byte, sourced with data transfers. In Write mode, the data strobe is sourced by the controller and is centered in the data window. In Read mode, the data strobe is sourced by the DDR2 SDRAMs and is sent at the leading edge of the data window. DQS signals are complements, and timing is relative to the crosspoint of respective

DQS and DQS If the module is to be operated in single ended strobe mode, all DQS signals must be tied on the system board to VSS and DDR2 SDRAM mode registers programmed appropriately.

V

DD

,V

DD

SPD,V

SS

Supply Power supplies for core, I/O, Serial Presence Detect, and ground for the module.

SDA

SCL

SA0~SA1

TEST

In/Out

Input

Input

In/Out

This is a bidirectional pin used to transfer data into or out of the SPD EEPROM. A resistor must be connected to V

DD as a pull up.

to act

This signal is used to clock data into and out of the SPD EEPROM. A resistor may be connected from SCL to V

DD a pull up.

to act as

Address pins used to select the Serial Presence Detect base address.

The TEST pin is reserved for bus analysis tools and is not connected on normal memory modules(SO-DIMMs).

Rev. 1.5 Aug. 2005


Functional Block Diagram: 512MB, 64Mx64 Module

(Populated as 2 rank of x16 DDR2 SDRAMs)

M470T6554BG(Z)3/M470T6554BG(Z)0

3 Ω + 5%

ODT1

ODT0

CKE1

CKE0

S1

S0

DQS0

DQS0

DM0

DQS1

DQS1

DM1

DQ8

DQ9

DQ10

DQ11

DQ12

DQ13

DQ14

DQ15

DQ0

DQ1

DQ2

DQ3

DQ4

DQ5

DQ6

DQ7

LDQS

LDQS

LDM

I/O 0

I/O 1

I/O 2

I/O 3

I/O 4

I/O 5

I/O 6

I/O 7

UDQS

UDQS

UDM

I/O 8

I/O 9

I/O 10

I/O 11

I/O 12

I/O 13

I/O 14

I/O 15

CS

D0

C

K

E

O

D

T

LDQS

LDQS

LDM

I/O 0

I/O 1

I/O 2

I/O 3

I/O 4

I/O 5

I/O 6

I/O 7

UDQS

UDQS

UDM

I/O 8

I/O 9

I/O 10

I/O 11

I/O 12

I/O 13

I/O 14

I/O 15

CS

D4

C

K

E

O

D

T

DQS4

DQS4

DM4

DQS5

DQS5

DM5

DQ40

DQ41

DQ42

DQ43

DQ44

DQ45

DQ46

DQ47

DQ32

DQ33

DQ34

DQ35

DQ36

DQ37

DQ38

DQ39

LDQS

LDQS

LDM

I/O 0

I/O 1

I/O 2

I/O 3

I/O 4

I/O 5

I/O 6

I/O 7

UDQS

UDQS

UDM

I/O 8

I/O 9

I/O 10

I/O 11

I/O 12

I/O 13

I/O 14

I/O 15

CS

D2

C

K

E

O

D

T

LDQS

LDQS

LDM

I/O 0

I/O 1

I/O 2

I/O 3

I/O 4

I/O 5

I/O 6

I/O 7

UDQS

UDQS

UDM

I/O 8

I/O 9

I/O 10

I/O 11

I/O 12

I/O 13

I/O 14

I/O 15

CS

D6

C

K

E

O

D

T

DQS2

DQS2

DM2

DQS6

DQS6

DM6

DQS3

DQS3

DM3

DQ24

DQ25

DQ26

DQ27

DQ28

DQ29

DQ30

DQ31

DQ16

DQ17

DQ18

DQ19

DQ20

DQ21

DQ22

DQ23

LDQS

LDQS

LDM

I/O 0

I/O 1

I/O 2

I/O 3

I/O 4

I/O 5

I/O 6

I/O 7

UDQS

UDQS

UDM

I/O 8

I/O 9

I/O 10

I/O 11

I/O 12

I/O 13

I/O 14

I/O 15

CS C

K

E

D1

O

D

T

LDQS

LDQS

LDM

I/O 0

I/O 1

I/O 2

I/O 3

I/O 4

I/O 5

I/O 6

I/O 7

UDQS

UDQS

UDM

I/O 8

I/O 9

I/O 10

I/O 11

I/O 12

I/O 13

I/O 14

I/O 15

CS C

K

E

D5

O

D

T

DQS7

DQS7

DM7

DQ56

DQ57

DQ58

DQ59

DQ60

DQ61

DQ62

DQ63

DQ48

DQ49

DQ50

DQ51

DQ52

DQ53

DQ54

DQ55

LDQS

LDQS

LDM

I/O 0

I/O 1

I/O 2

I/O 3

I/O 4

I/O 5

I/O 6

I/O 7

UDQS

UDQS

UDM

I/O 8

I/O 9

I/O 10

I/O 11

I/O 12

I/O 13

I/O 14

I/O 15

CS

D3

C

K

E

O

D

T

LDQS

LDQS

LDM

I/O 0

I/O 1

I/O 2

I/O 3

I/O 4

I/O 5

I/O 6

I/O 7

UDQS

UDQS

UDM

I/O 8

I/O 9

I/O 10

I/O 11

I/O 12

I/O 13

I/O 14

I/O 15

CS

D7

C

K

E

O

D

T

BA0 - BA1

A0 - A13

RAS

CAS

WE

3 Ω + 5%

DDR2 SDRAMs D0 - D7

DDR2 SDRAMs D0 - D7

DDR2 SDRAMs D0 - D7

DDR2 SDRAMs D0 - D7

DDR2 SDRAMs D0 - D7

V

DD

SPD

V

REF

V

DD

V

SS

SCL

SA0

SA1

SCL

A0

A1

A2

SPD

WP

SDA

Serial PD

DDR2 SDRAMs D0 - D7

DDR2 SDRAMs D0 - D7, V

DD and V

DD

Q

DDR2 SDRAMs D0 - D7, SPD

* Clock Wiring

Clock Input DDR2 SDRAMs

*CK0/CK0

*CK1/CK1

4 DDR2 SDRAMs

4 DDR2 SDRAMs

* Wire per Clock Loading

Table/Wiring Diagrams

Notes :

1. DQ,DM, DQS/DQS resistors : 22 Ohms

±

5%.

2. BAx, Ax, RAS, CAS, WE resistors : 3.0 Ohms

±

5%.

Rev. 1.5 Aug. 2005


Functional Block Diagram: 256MB, 32Mx64 Module

(Populated as 1 rank of x16 DDR2 SDRAMs)

M470T3354BG(Z)3/M470T3354BG(Z)0

CKE0

ODT0

S0

DQS0

DQS0

DM0

3 Ω + 5%

DQ0

DQ1

DQ2

DQ3

DQ4

DQ5

DQ6

DQ7

DQS1

DQS1

DM1

DQ8

DQ9

DQ10

DQ11

DQ12

DQ13

DQ14

DQ15

DQS2

DQS2

DM2

DQ16

DQ17

DQ18

DQ19

DQ20

DQ21

DQ22

DQ23

DQS3

DQS3

DM3

DQ24

DQ25

DQ26

DQ27

DQ28

DQ29

DQ30

DQ31

LDQS

LDQS

LDM

I/O 0

I/O 1

I/O 2

I/O 3

I/O 4

I/O 5

I/O 6

I/O 7

UDQS

UDQS

UDM

I/O 8

I/O 9

I/O 10

I/O 11

I/O 12

I/O 13

I/O 14

I/O 15

CS

D0

O

D

T

C

K

E

LDQS

LDQS

LDM

I/O 0

I/O 1

I/O 2

I/O 3

I/O 4

I/O 5

I/O 6

I/O 7

UDQS

UDQS

UDM

I/O 8

I/O 9

I/O 10

I/O 11

I/O 12

I/O 13

I/O 14

I/O 15

CS

D1

O

D

T

C

K

E

DQS4

DQS4

DM4

DQS5

DQS5

DM5

DQS6

DQS6

DM6

DQS7

DQS7

DM7

DQ48

DQ49

DQ50

DQ51

DQ52

DQ53

DQ54

DQ55

DQ56

DQ57

DQ58

DQ59

DQ60

DQ61

DQ62

DQ63

DQ32

DQ33

DQ34

DQ35

DQ36

DQ37

DQ38

DQ39

DQ40

DQ41

DQ42

DQ43

DQ44

DQ45

DQ46

DQ47

LDQS

LDQS

LDM

I/O 0

I/O 1

I/O 2

I/O 3

I/O 4

I/O 5

I/O 6

I/O 7

UDQS

UDQS

UDM

I/O 8

I/O 9

I/O 10

I/O 11

I/O 12

I/O 13

I/O 14

I/O 15

CS O

D

T

D2

C

K

E

LDQS

LDQS

LDM

I/O 0

I/O 1

I/O 2

I/O 3

I/O 4

I/O 5

I/O 6

I/O 7

UDQS

UDQS

UDM

I/O 8

I/O 9

I/O 10

I/O 11

I/O 12

I/O 13

I/O 14

I/O 15

CS O

D

T

D3

C

K

E

BA0 - BA1

A0 - A13

RAS

CAS

WE

3 Ω

V

DD

SPD

V

REF

V

DD

V

SS

DDR2 SDRAMs D0 - D3

DDR2 SDRAMs D0 - D3

DDR2 SDRAMs D0 - D3

DDR2 SDRAMs D0 - D3

DDR2 SDRAMs D0 - D3

SCL

SA0

SA1

SCL

A0

A1

A2

SPD

WP

Serial PD

DDR2 SDRAMs D0 - D3


DD and V

DD

Q


SDA

* Clock Wiring


*CK0/CK0

*CK1/CK1

2 DDR2 SDRAMs

2 DDR2 SDRAMs



Notes :


±

5%.

2. BAx, Ax, RAS, CAS, WE resistors : 3.0 Ohms

±

5%.

Rev. 1.5 Aug. 2005


Functional Block Diagram: 1GB, 128Mx64 Module

(Populated as 2 ranks of x8 DDR2 SDRAMs)

M470T2953BS(Y)3/M470T2953BS(Y)0

CKE1

ODT1

S1

CKE0

ODT0

S0

DQS0

DQS0

DM0

3 Ω + 5%

DQ0

DQ1

DQ2

DQ3

DQ4

DQ5

DQ6

DQ7

DQS

DQS

DM

I/O 0

I/O 1

I/O 2

I/O 3

I/O 4

I/O 5

I/O 6

I/O 7

CS0 O

D

T

0

D0

C

K

E

0

DQS

DQS

DM

I/O 0

I/O 1

I/O 2

I/O 3

I/O 4

I/O 5

I/O 6

I/O 7

CS 1 O

D

T

1

D8

C

K

E

1

DQS4

DQS4

DM4

DQ32

DQ33

DQ34

DQ35

DQ36

DQ37

DQ38

DQ39

DQS

DQS

DM

I/O 0

I/O 1

I/O 2

I/O 3

I/O 4

I/O 5

I/O 6

I/O 7

CS0 O

D

T

0

D4

C

K

E

0

DQS

DQS

DM

I/O 0

I/O 1

I/O 2

I/O 3

I/O 4

I/O 5

I/O 6

I/O 7

CS 1 O

D

T

1

D12

C

K

E

1

DQS1

DQS1

DM1

DQ8

DQ9

DQ10

DQ11

DQ12

DQ13

DQ14

DQ15

DQS2

DQS2

DM2

DQ16

DQ17

DQ18

DQ19

DQ20

DQ21

DQ22

DQ23

DQS

DQS

DM

I/O 8

I/O 9

I/O 10

I/O 11

I/O 12

I/O 13

I/O 14

I/O 15

CS0

T

0

O

D

D1

C

K

E

0

DQS

DQS

DM

I/O 0

I/O 1

I/O 2

I/O 3

I/O 4

I/O 5

I/O 6

I/O 7

CS0

T

0

O

D

D2

C

K

E

0

DQS

DQS

DM

I/O 8

I/O 9

I/O 10

I/O 11

I/O 12

I/O 13

I/O 14

I/O 15

CS

1

T

1

O

D

D9

C

K

E

1

DQS

DQS

DM

I/O 0

I/O 1

I/O 2

I/O 3

I/O 4

I/O 5

I/O 6

I/O 7

CS

1

D10

T

1

O

D

C

K

E

1

DQS5

DQS5

DM5

DQ40

DQ41

DQ42

DQ43

DQ44

DQ45

DQ46

DQ47

DQS6

DQS6

DM6

DQ48

DQ49

DQ50

DQ51

DQ52

DQ53

DQ54

DQ55

DQS

DQS

DM

I/O 8

I/O 9

I/O 10

I/O 11

I/O 12

I/O 13

I/O 14

I/O 15

CS0 O

D

T

0

D5

C

K

E

0

DQS

DQS

DM

I/O 0

I/O 1

I/O 2

I/O 3

I/O 4

I/O 5

I/O 6

I/O 7

CS0 O

D

T

0

D6

C

K

E

0

DQS

DQS

DM

I/O 8

I/O 9

I/O 10

I/O 11

I/O 12

I/O 13

I/O 14

I/O 15

CS

1

O

D

T

1

D13

C

K

E

1

DQS

DQS

DM

I/O 0

I/O 1

I/O 2

I/O 3

I/O 4

I/O 5

I/O 6

I/O 7

CS

1

O

D

T

1

D14

C

K

E

1

DQS3

DQS3

DM3

DQ24

DQ25

DQ26

DQ27

DQ28

DQ29

DQ30

DQ31

DQS

DQS

DM

I/O 8

I/O 9

I/O 10

I/O 11

I/O 12

I/O 13

I/O 14

I/O 15

CS0 O

D

T

0

D3

C

K

E

0

DQS

DQS

DM

I/O 8

I/O 9

I/O 10

I/O 11

I/O 12

I/O 13

I/O 14

I/O 15

CS

1

D11

O

D

T

1

C

K

E

1

DQS7

DQS7

DM7

DQ56

DQ57

DQ58

DQ59

DQ60

DQ61

DQ62

DQ63

DQS

DQS

DM

I/O 8

I/O 9

I/O 10

I/O 11

I/O 12

I/O 13

I/O 14

I/O 15

CS0 O

D

T

0

D7

C

K

E

0

DQS

DQS

DM

I/O 8

I/O 9

I/O 10

I/O 11

I/O 12

I/O 13

I/O 14

I/O 15

CS

1

O

D

T

1

D15

C

K

E

1

BA0 - BA1

A0 - A13

RAS

CAS

WE

10 Ω + 5%

DDR2 SDRAMs D0 - D15





V

DD

SPD

V

REF

V

DD

V

SS

SCL

SA0

SA1

Serial PD



DD and V

DD

Q


SCL

A0

A1

A2

SPD

WP

SDA

* Clock Wiring


*CK0/CK0

*CK1/CK1

8 DDR2 SDRAMs

8 DDR2 SDRAMs



Notes :


±

5%.

2. BAx, Ax, RAS, CAS, WE resistors : 10 Ohms

±

5%.

Rev. 1.5 Aug. 2005


Absolute Maximum DC Ratings

Symbol

V

DD

Voltage on V

DD

Parameter

pin relative to V

SS

Rating

- 1.0 V ~ 2.3 V

Units

V

Notes

1

V

DDQ

Voltage on V

DDQ

pin relative to V

SS

V

DDL

Voltage on V

DDL

pin relative to V

SS

V

IN,

V

OUT

Voltage on any pin relative to V

SS

- 0.5 V ~ 2.3 V

- 0.5 V ~ 2.3 V

- 0.5 V ~ 2.3 V

V

V

V

1

1

1

T

STG

Storage Temperature -55 to +100

Note :

1. Stresses greater than those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.

Exposure to absolute maximum rating conditions for extended periods may affect reliability.

2. Storage Temperature is the case surface temperature on the center/top side of the DRAM. For the measurement conditions, please refer to JESD51-2 standard.

AC & DC Operating Conditions

Recommended DC Operating Conditions (SSTL - 1.8)

Symbol Parameter

Rating

Typ.

1.8

Max.

1.9

Units Notes

V

DD

V

DDL

Supply Voltage

Supply Voltage for DLL

Min.

1.7

1.7

1.8

1.9

V

V 4

V

DDQ

V

REF

V

TT

Supply Voltage for Output

Input Reference Voltage

Termination Voltage

1.7

0.49*V

DDQ

V

REF

-0.04

1.8

0.50*V

V

DDQ

REF

0.51*V

V

1.9

REF

DDQ

+0.04

V mV

V

4

1,2

3

Note : There is no specific device V

DD

supply voltage requirement for SSTL-1.8 compliance. However under all conditions V

DDQ

must be less than or equal to V

DD

.

1. The value of V

REF

may be selected by the user to provide optimum noise margin in the system. Typically the value of V

REF

.

is expected to be about 0.5 x V

DDQ

3. V

of the transmitting device and V

REF

2. Peak to peak AC noise on V

TT

of transmitting device must track V

REF

is expected to track variations in V

DDQ

REF

may not exceed +/-2% V

of receiving device.

4. AC parameters are measured with V

DD

, V

DDQ

and V

DDL

REF

(DC).

tied together.

Rev. 1.5 Aug. 2005


Operating Temperature Condition

Symbol

TOPER

Parameter

Operating Temperature

Rating

0 to 95

Units Notes

Note :

1. Operating Temperature is the case surface temperature on the center/top side of the DRAM. For the measurement conditions, please refer to JESD51.2

standard.

2. At 0 - 85 °C, operation temperature range are the temperature which all DRAM specification will be supported.

3. At 85 - 95 °C operation temperature range, doubling refresh commands in frequency to a 32ms period ( tREFI=3.9 us ) is required, and to enter to self refresh mode at this temperature range, an EMRS command is required to change internal refresh rate.

Input DC Logic Level

Symbol

V

IH

(DC)

V

IL

(DC)

Parameter

DC input logic high

DC input logic low

Min.

V

REF

+ 0.125

- 0.3

Max.

V

DDQ

+ 0.3

V

REF

- 0.125

Units

V

V

Notes

Input AC Logic Level

Symbol

V

IH

(AC)

V

IL

(AC)

Parameter

AC input logic high

AC input logic low

Min.

V

REF

+ 0.250

-

Max.

-

V

REF

- 0.250

Units

V

V

Notes

AC Input Test Conditions

Symbol

V

REF

V

SWING(MAX)

SLEW

Input reference voltage

Condition

Input signal maximum peak to peak swing

Input signal minimum slew rate

Value

0.5 * V

DDQ

1.0

1.0

Units

V

V

V/ns

Notes

1

1

2, 3

Notes:

1. Input waveform timing is referenced to the input signal crossing through the V

2. The input signal minimum slew rate is to be maintained over the range from V max for falling edges as shown in the below figure.

IH/IL

(AC)

REF to V level applied to the device under test.

IH

(AC) min for rising edges and the range from V

REF

to V

IL

(AC)

3. AC timings are referenced with input waveforms switching from V transitions.

IL

(AC) to V

IH

(AC) on the positive transitions and V

IH

(AC) to V

IL

(AC) on the negative

V

SWING(MAX) delta TF

Falling Slew =

V

REF

- V

IL

(AC) max

delta TF

< AC Input Test Signal Waveform >

V

DDQ

V

IH

(AC) min

V

IH

(DC) min

V

REF

V

IL

(DC) max

V

IL

(AC) max

V

SS delta TR

Rising Slew =

V

IH

(AC) min - V

REF

delta TR

Rev. 1.5 Aug. 2005


IDD Specification Parameters Definition

(IDD values are for full operating range of Voltage and Temperature)

Symbol

IDD0

IDD1

IDD2P

IDD2Q

IDD2N

IDD3P

IDD3N

IDD4W

IDD4R

IDD5B

IDD6

IDD7

Proposed Conditions

Operating one bank active-precharge current;

tCK = tCK(IDD), tRC = tRC(IDD), tRAS = tRASmin(IDD); CKE is HIGH, CS\ is HIGH between valid commands;

Address bus inputs are SWITCHING; Data bus inputs are SWITCHING

Operating one bank active-read-precharge current;

IOUT = 0mA; BL = 4, CL = CL(IDD), AL = 0; tCK = tCK(IDD), tRC = tRC (IDD), tRAS = tRASmin(IDD), tRCD = tRCD(IDD); CKE is HIGH, CS\ is HIGH between valid commands; Address bus inputs are SWITCHING; Data pattern is same as IDD4W

Precharge power-down current;

All banks idle; tCK = tCK(IDD); CKE is LOW; Other control and address bus inputs are STABLE; Data bus inputs are

FLOATING

Precharge quiet standby current;

All banks idle; tCK = tCK(IDD); CKE is HIGH, CS\ is HIGH; Other control and address bus inputs are STABLE; Data bus inputs are FLOATING

Precharge standby current;

All banks idle; tCK = tCK(IDD); CKE is HIGH, CS\ is HIGH; Other control and address bus inputs are SWITCHING;

Data bus inputs are SWITCHING

Active power-down current;

All banks open; tCK = tCK(IDD); CKE is LOW; Other control and address bus inputs are STABLE; Data bus inputs are FLOATING

Fast PDN Exit MRS(12) = 0mA

Slow PDN Exit MRS(12) = 1mA

Active standby current;

All banks open; tCK = tCK(IDD), tRAS = tRASmax(IDD), tRP = tRP(IDD); CKE is HIGH, CS\ is HIGH between valid commands; Other control and address bus inputs are SWITCHING; Data bus inputs are SWITCHING

Operating burst write current;

All banks open, Continuous burst writes; BL = 4, CL = CL(IDD), AL = 0; tCK = tCK(IDD), tRAS = tRASmax(IDD), tRP

= tRP(IDD); CKE is HIGH, CS\ is HIGH between valid commands; Address bus inputs are SWITCHING; Data bus inputs are SWITCHING

Operating burst read current;

All banks open, Continuous burst reads, IOUT = 0mA; BL = 4, CL = CL(IDD), AL = 0; tCK = tCK(IDD), tRAS = tRASmax(IDD), tRP = tRP(IDD); CKE is HIGH, CS\ is HIGH between valid commands; Address bus inputs are SWITCH-

ING; Data pattern is same as IDD4W

Burst auto refresh current; tCK = tCK(IDD); Refresh command at every tRFC(IDD) interval; CKE is HIGH, CS\ is HIGH between valid commands;

Other control and address bus inputs are SWITCHING; Data bus inputs are SWITCHING

Self refresh current;

CK and CK\ at 0V; CKE ≤ 0.2V; Other control and address bus inputs are

FLOATING; Data bus inputs are FLOATING

Normal

Low Power

Operating bank interleave read current;

All bank interleaving reads, IOUT = 0mA; BL = 4, CL = CL(IDD), AL = tRCD(IDD)-1*tCK(IDD); tCK = tCK(IDD), tRC = tRC(IDD), tRRD = tRRD(IDD), tFAW = tFAW(IDD), tRCD = 1*tCK(IDD); CKE is HIGH, CS\ is HIGH between valid commands; Address bus inputs are STABLE during DESELECTs; Data pattern is same as IDD4R; Refer to the following page for detailed timing conditions

Units mA mA mA mA mA mA mA mA mA mA mA mA mA mA

Notes

Rev. 1.5 Aug. 2005


Operating Current Table(1-1)

(T A =0 o C, VDD= 1.9V)

M470T6554BG(Z)3/M470T6554BG(Z)0 : 64Mx64 512MB Module

Symbol

IDD0

IDD1

IDD2P

IDD2Q

IDD2N

IDD3P-F

IDD3P-S

IDD3N

IDD4W

IDD4R

IDD5B

IDD6

IDD7

CD5

(DDR533@CL=4)

760

860

64

200

240

240

120

560

1,200

1,100

1,060

44

1,840

LD5

(DDR533@CL=4)

460

560

64

200

200

120

120

260

700

700

860

40

1,060

CCC

(DDR400@CL=3)

720

760

64

200

240

240

120

520

1,000

940

1,000

44

1,760

* Module IDD was calculated on the basis of component IDD and can be differently measured according to DQ loading cap.

LCC

(DDR400@CL=3)

460

520

64

200

200

120

120

260

700

700

860

40

1,060

Unit mA mA mA mA mA mA mA mA mA mA mA mA mA

Notes

M470T3354BG(Z)3/M470T3354BG(Z)0 : 32Mx64 256MB Module

Symbol

IDD0

IDD1

IDD2P

IDD2Q

IDD2N

IDD3P-F

IDD3P-S

IDD3N

IDD4W

IDD4R

IDD5B

IDD6

IDD7

CD5

(DDR533@CL=4)

480

580

32

100

120

120

60

280

920

820

780

22

1,560

LD5

(DDR533@CL=4)

360

460

32

100

100

60

60

160

600

600

760

20

960

CCC

(DDR400@CL=3)

460

500

32

100

120

120

60

260

740

680

740

22

1,500


LCC

(DDR400@CL=3)

360

420

32

100

100

520

760

20

960

60

60

160

520


Notes

Rev. 1.5 Aug. 2005


Operating Current Table(1-2)

(T A =0 o C, VDD= 1.9V)

M470T2953BS(Y)3/M470T2953BS(Y)0 : 128Mx64 1GB Module

Symbol

IDD0

IDD1

IDD2P

IDD2Q

IDD2N

IDD3P-F

IDD3P-S

IDD3N

IDD4W

IDD4R

IDD5B

IDD6

IDD7

CD5

(DDR533@CL=4)

1,360

1,440

128

400

480

480

240

1,120

2,160

2,000

2,120

88

2,760

LD5

(DDR533@CL=4)

760

920

128

400

400

240

240

520

1,160

1,160

1,720

80

1,960

CCC

(DDR400@CL=3)

1,280

1,320

128

400

480

480

240

1,040

1,680

1,680

2,000

88

2,680


LCC

(DDR400@CL=3)

760

840

128

400

400

240

240

520

1,000

1,000

1,720

80

1,960


Notes

Input/Output Capacitance

(V

DD

=1.8V, V

DDQ

=1.8V, T

A

=25 o C)

Parameter

Non-ECC

Symbol

Input capacitance, CK and CK

Input capacitance, CKE , CS, Addr, RAS, CAS, WE

Input/output capacitance, DQ, DM, DQS, DQS

* DM is internally loaded to match DQ and DQS identically.

CCK

CI

CIO

Min Max

M470T6554BG(Z)3

M470T6554BG(Z)0

-

-

-

32

34

10

Min Max

M470T3354BG(Z)3

M470T3354BG(Z)0

-

-

-

24

34

6

Min Max

M470T2953BS(Y)3

M470T2953BS(Y)0

-

-

-

48

42

10

Units pF

Rev. 1.5 Aug. 2005


Electrical Characteristics & AC Timing for DDR2-533/400 SDRAM

(0 °C < T

CASE

< 95 °C; V

DDQ

= 1.8V + 0.1V; V

DD

= 1.8V + 0.1V)

Refresh Parameters by Device Density

Parameter

Refresh to active/Refresh command time tRFC

Average periodic refresh interval tREFI

Symbol

0 °C ≤ T

CASE

≤ 85°C

85 °C < T

CASE

≤ 95°C

256Mb

75

7.8

3.9

512Mb

105

7.8

3.9

DDR2 SDRAM

1Gb

127.5

7.8

3.9

2Gb

195

7.8

3.9

4Gb tbd

7.8

3.9

Units ns

µs

µs

Speed Bins and CL, tRCD, tRP, tRC and tRAS for Corresponding Bin

Speed

Bin (CL - tRCD - tRP)

Parameter tCK, CL=3 tCK, CL=4 tCK, CL=5 tRCD tRP tRC tRAS min

5

3.75

-

15

15

55

40

DDR2-533(D5)

4 - 4 - 4 max

8

8

-

70000 min

5

5

-

15

15

55

40

DDR2-400(CC)

3 - 3 - 3 max

8

8

-

70000

Units ns ns ns ns ns ns ns

Rev. 1.5 Aug. 2005


Timing Parameters by Speed Grade

(Refer to notes for informations related to this table at the bottom)

Parameter Symbol

DQ output access time from CK/CK

DQS output access time from CK/CK

CK high-level width

CK low-level width

CK half period tAC tDQSCK tCH tCL tHP

Clock cycle time, CL=x

DQ and DM input hold time

DQ and DM input setup time

Control & Address input pulse width for each input

DQ and DM input pulse width for each input

Data-out high-impedance time from CK/CK

DQS low-impedance time from CK/CK

DQ low-impedance time from CK/CK

DQS-DQ skew for DQS and associated DQ signals

DQ hold skew factor

DQ/DQS output hold time from DQS

Write command to first DQS latching transition

DQS input high pulse width

DQS input low pulse width

DQS falling edge to CK setup time

DQS falling edge hold time from CK

Mode register set command cycle time

Write postamble

Write preamble

Address and control input hold time

Address and control input setup time

Read preamble

Read postamble

Active to active command period for 1KB page size products tRRD

Active to active command period for 2KB page size products tRRD

Four Activate Window for 1KB page size products

Four Activate Window for 2KB page size products tFAW tFAW

CAS to CAS command delay

Write recovery time

Auto precharge write recovery + precharge time

Internal write to read command delay tCCD tWR tDAL tWTR

Internal read to precharge command delay

Exit self refresh to a non-read command

Exit self refresh to a read command

Exit precharge power down to any non-read command

Exit active power down to read command

Exit active power down to read command (Slow exit, Lower power) tDSH tMRD tWPST tWPRE tIH tIS tRPRE tRPST tRTP tXSNR tXSRD tXP tXARD tXARDS tCK tDH tDS tIPW tDIPW tHZ tLZ(DQS) tLZ(DQ) tDQSQ tQHS tQH tDQSS tDQSH tDQSL tDSS

7.5

10

37.5

50

2

15 tWR+tRP

10

7.5

tRFC + 10

200

2

2

475

350

0.9

0.4

0.2

2

0.4

0.35

2* tACmin x x tHP - tQHS

WL-0.25

0.35

0.35

0.2

min

DDR2-400 max

-600

-500

+600

+500

0.45

0.45

min(tCL, tCH)

0.55

0.55

x

5000

275

150

0.6

0.35

x tAC min

8000 x x x x tAC max tAC max x x

1.1

0.6

x x

0.6

x x x tAC max

350

450 x

WL+0.25

x x x x x x x x

6 - AL

7.5

10

37.5

50

2

15 tWR+tRP

7.5

7.5

tRFC + 10

200

2

2

375

250

0.9

0.4

0.2

2

0.4

0.35

2* tACmin x x tHP - tQHS

WL-0.25

0.35

0.35

0.2

min

DDR2-533 max

-500

-450

+500

+450

0.45

0.45

min(tCL, tCH)

0.55

0.55

x

3750

225

100

0.6

0.35

x tAC min

8000 x x x x tAC max tAC max

1.1

0.6

x x

0.6

x x x x x tAC max

300

400 x

WL+0.25

x x x x x x x x

6 - AL

Units tCK ns tCK ns ns ns ns ns ns ns tCK tCK tCK ps ps tCK tCK tCK tCK tCK tCK tCK tCK tCK tCK ps ps ps ps ps ps ps tCK tCK ps ps tCK ps ps tCK tCK ps

Notes

Rev. 1.5 Aug. 2005


Parameter

CKE minimum pulse width (high and low pulse width)

ODT turn-on delay

ODT turn-on

ODT turn-on(Power-Down mode)

ODT turn-off delay

ODT turn-off

ODT turn-off (Power-Down mode)

ODT to power down entry latency

ODT power down exit latency

Symbol tCKE tAOND tAON tAONPD tAOFD tAOF tAOFPD tANPD tAXPD

OCD drive mode output delay tOIT

Minimum time clocks remains ON after CKE asynchronously drops LOW tDelay min

DDR2-533 max

3

2 2

3

2 2 tAC(min) tAC(max)+1 tAC(min) tAC(max)+1 tAC(min)+2

2tCK+tAC( max)+1 min

DDR2-400 max tAC(min)+2

2tCK+tAC

(max)+1

2.5

2.5

tAC(min) tAC(min)+2

2.5

tAC(max)+

0.6

2.5tCK+ tAC(max)+1 tAC(min) tAC(min)+2

2.5

tAC(max)+

0.6

2.5tCK+ tAC(max)+1

3

8

0 12

3

8

0 12 tIS+tCK +tIH tIS+tCK +tIH

Units ns tCK tCK ns ns tCK tCK ns ns tCK ns

Notes

Rev. 1.5 Aug. 2005


Physical Dimensions: 32Mbx16 based 64Mx64 Module(2 Rank)

M470T6554BG(Z)3/M470T6554BG(Z)0

67.60 mm

2.00

DDR2 SDRAM

3.8 mm

Max

1

11.40

16.25

a

63.00

47.40

b

2 a

199

200

1.1 mm

Max

67.60 mm

FRONT SIDE

4.20

2.70 ± 0.10

1.50 ± 0.10

DETAIL a

BACK SIDE

4.00 ± 0.10

1.0 ± 0.05

4.00 ± 0.10

1.0 ± 0.05

1.80 ± 0.10

4.20

2.40 ± 0.10

DETAIL b

0.60

0.45 ± 0.03

The used device is 32M x16 DDR2 SDRAM, FBGA.

DDR2 SDRAM Part NO : K4T51163QB

Rev. 1.5 Aug. 2005


Physical Dimensions: 32Mbx16 based 32Mx64 Module(1 Rank)

M470T3354BG(Z)3/M470T3354BG(Z)0

67.60 mm

2.00

DDR2 SDRAM

2.45 mm

Max

1

11.40

16.25

a

63.00

47.40

b

2 a

199

200

1.1 mm

Max

67.60 mm

FRONT SIDE

4.20

2.70 ± 0.10

1.50 ± 0.10

DETAIL a

BACK SIDE

4.00 ± 0.10

1.0 ± 0.05

4.00 ± 0.10

1.0 ± 0.05

1.80 ± 0.10

4.20

2.40 ± 0.10

DETAIL b

0.60

0.45 ± 0.03



Rev. 1.5 Aug. 2005


Physical Dimensions: 64Mbx8 based 128Mx64 Module(2 Ranks)

M470T2953BS(Y)3/M470T2953BS(Y)0

67.60 mm

2.00

SPD

DDR2 SDRAM

3.8 mm max

1

11.40

16.25

a

63.00

b

47.40

2 a

199

200

1.1mm

max

67.60 mm

FRONT SIDE

4.20

2.70 ± 0.10

1.50 ± 0.10

DETAIL a

BACK SIDE

4.00 ± 0.10

1.0 ± 0.05

4.00 ± 0.10

1.0 ± 0.05

1.80 ± 0.10

4.20

2.40 ± 0.10

DETAIL b

0.60

0.45 ± 0.03



Rev. 1.5 Aug. 2005


Revision History

Revision 1.0 (Jan. 2004)

- Initial Release

Revision 1.1 (Jun. 2004)

- Added lead-free part number in the ordering information

- Changed IDD2P

Revision 1.2 (Jul. 2004)

- Added current values and part number of low power product

Revision 1.3 (Feb. 2005)

- Added the detail information for mechanical dimension

Revision 1.4 (Mar. 2005)

- Changed 1GB Functional Block Diagram

Revision 1.5 (Aug. 2005)

- Changed the IDD Specification Parameters Definition

DDR2 SDRAM

Rev. 1.5 Aug. 2005

This datasheet has been downloaded from: www.DatasheetCatalog.com

Datasheets for electronic components.

Samsung 256MB, DDR II SDRAM, 533MHz, soDIMM Datasheet

DDR2 Unbuffered SODIMM

200pin Unbuffered SODIMM based on 512Mb B-die

64bit Non-ECC

This datasheet has been downloaded from: www.DatasheetCatalog.com

Datasheets for electronic components.

Related manuals

Transcend

TS32MSQ64V4M

Hynix

HMP125U6EFR8C-S6

Hynix

HMP112S6EFR6C-Y5

Legrand

Mighty Mo Fiber Raceway, End Cap 4" x 4", 2/46mm diameter knockouts, yellow