Intel® Celeron® Processor 400Δ
Series
Datasheet
— Supporting the Intel® Celeron® processor 420Δ, 430Δ, 440Δ, and
450Δ
August 2008
Document Number: 316963-002
INFORMATION IN THIS DOCUMENT IS PROVIDED IN CONNECTION WITH INTEL PRODUCTS. NO LICENSE, EXPRESS OR IMPLIED, BY ESTOPPEL OR
OTHERWISE, TO ANY INTELLECTUAL PROPERTY RIGHTS IS GRANTED BY THIS DOCUMENT. EXCEPT AS PROVIDED IN INTEL'S TERMS AND CONDITIONS
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TO SALE AND/OR USE OF INTEL PRODUCTS INCLUDING LIABILITY OR WARRANTIES RELATING TO FITNESS FOR A PARTICULAR PURPOSE,
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INTENDED FOR USE IN MEDICAL, LIFE SAVING, OR LIFE SUSTAINING APPLICATIONS.
Intel may make changes to specifications and product descriptions at any time, without notice.
Designers must not rely on the absence or characteristics of any features or instructions marked "reserved" or "undefined." Intel reserves these for
future definition and shall have no responsibility whatsoever for conflicts or incompatibilities arising from future changes to them.
ΔIntel processor numbers are not a measure of performance. Processor numbers differentiate features within each processor family, not across different
processor families. See http://www.intel.com/products/processor_number for details. Over time processor numbers will increment based on changes in
clock, speed, cache, FSB, or other features, and increments are not intended to represent proportional or quantitative increases in any particular
feature. Current roadmap processor number progression is not necessarily representative of future roadmaps. See www.intel.com/products/
processor_number for details.
Intel® 64 requires a computer system with a processor, chipset, BIOS, operating system, device drivers, and applications enabled for Intel 64. Processor
will not operate (including 32-bit operation) without an Intel 64-enabled BIOS. Performance will vary depending on your hardware and software
configurations. See http://www.intel.com/technology/intel64/index.htm for more information including details on which processors support Intel 64, or
consult with your system vendor for more information.
Enabling Execute Disable Bit functionality requires a PC with a processor with Execute Disable Bit capability and a supporting operating system. Check
with your PC manufacturer on whether your system delivers Execute Disable Bit functionality.
Designers must not rely on the absence or characteristics of any features or instructions marked "reserved" or "undefined." Intel reserves these for
future definition and shall have no responsibility whatsoever for conflicts or incompatibilities arising from future changes to them.
The Intel® Celeron® processor 400 series may contain design defects or errors known as errata which may cause the product to deviate from published
specifications.
Contact your local Intel sales office or your distributor to obtain the latest specifications and before placing your product order.
Intel, Celeron, Pentium, Intel Core, and the Intel logo are trademarks of Intel Corporation in the U.S. and other countries.
*Other names and brands may be claimed as the property of others.
Copyright © 2007–2008 Intel Corporation.
2
Datasheet
Contents
1
Introduction .............................................................................................................. 9
1.1
Terminology ....................................................................................................... 9
1.1.1 Processor Packaging Terminology ............................................................. 10
1.2
References ....................................................................................................... 11
2
Electrical Specifications ........................................................................................... 13
2.1
Power and Ground Lands.................................................................................... 13
2.2
Decoupling Guidelines ........................................................................................ 13
2.2.1 Vcc Decoupling ...................................................................................... 13
2.2.2 Vtt Decoupling ....................................................................................... 13
2.2.3 FSB Decoupling...................................................................................... 14
2.3
Voltage Identification ......................................................................................... 14
2.4
Market Segment Identification (MSID) ................................................................. 16
2.5
Reserved, Unused and TESTHI Signals ................................................................. 16
2.6
Voltage and Current Specification ........................................................................ 17
2.6.1 Absolute Maximum and Minimum Ratings .................................................. 17
2.6.2 DC Voltage and Current Specification ........................................................ 19
2.6.3 Vcc Overshoot ....................................................................................... 21
2.6.4 Die Voltage Validation ............................................................................. 22
2.7
Signaling Specifications...................................................................................... 22
2.7.1 FSB Signal Groups.................................................................................. 23
2.7.2 CMOS and Open Drain Signals ................................................................. 25
2.7.3 Processor DC Specifications ..................................................................... 25
2.7.3.1 GTL+ Front Side Bus Specifications ............................................. 27
2.8
Clock Specifications ........................................................................................... 28
2.8.1 Front Side Bus Clock (BCLK[1:0]) and Processor Clocking ............................ 28
2.8.2 FSB Frequency Select Signals (BSEL[2:0])................................................. 29
2.8.3 Phase Lock Loop (PLL) and Filter .............................................................. 29
2.8.4 BCLK[1:0] Specifications (CK505 based Platforms) ..................................... 30
2.8.5 BCLK[1:0] Specifications (CK410 based Platforms) ..................................... 32
2.9
PECI DC Specifications ....................................................................................... 34
3
Package Mechanical Specifications .......................................................................... 35
3.1
Package Mechanical Drawing............................................................................... 35
3.2
Processor Component Keep-Out Zones ................................................................. 39
3.3
Package Loading Specifications ........................................................................... 39
3.4
Package Handling Guidelines............................................................................... 39
3.5
Package Insertion Specifications.......................................................................... 40
3.6
Processor Mass Specification ............................................................................... 40
3.7
Processor Materials............................................................................................ 40
3.8
Processor Markings............................................................................................ 40
3.9
Processor Land Coordinates ................................................................................ 41
4
Land Listing and Signal Descriptions ....................................................................... 43
4.1
Processor Land Assignments ............................................................................... 43
4.2
Alphabetical Signals Reference ............................................................................ 66
5
Thermal Specifications and Design Considerations .................................................. 75
5.1
Processor Thermal Specifications ......................................................................... 75
5.1.1 Thermal Specifications ............................................................................ 75
5.1.2 Thermal Metrology ................................................................................. 78
5.2
Processor Thermal Features ................................................................................ 78
5.2.1 Thermal Monitor..................................................................................... 78
Datasheet
3
5.3
5.4
5.2.2 Thermal Monitor 2 ..................................................................................79
5.2.3 On-Demand Mode ...................................................................................80
5.2.4 PROCHOT# Signal ..................................................................................81
5.2.5 THERMTRIP# Signal ................................................................................81
Thermal Diode...................................................................................................82
Platform Environment Control Interface (PECI) ......................................................84
5.4.1 Introduction ...........................................................................................84
5.4.1.1 Key Difference with Legacy Diode-Based Thermal Management .......84
5.4.2 PECI Specifications .................................................................................86
5.4.2.1 PECI Device Address..................................................................86
5.4.2.2 PECI Command Support .............................................................86
5.4.2.3 PECI Fault Handling Requirements ...............................................86
5.4.2.4 PECI GetTemp0() Error Code Support ..........................................86
6
Features ..................................................................................................................87
6.1
Power-On Configuration Options ..........................................................................87
6.2
Clock Control and Low Power States .....................................................................87
6.2.1 Normal State .........................................................................................88
6.2.2 HALT and Extended HALT Powerdown States ..............................................88
6.2.2.1 HALT Powerdown State ..............................................................88
6.2.2.2 Extended HALT Powerdown State ................................................89
6.2.3 Stop Grant State ....................................................................................89
6.2.4 HALT Snoop State and Stop Grant Snoop State...........................................90
7
Boxed Processor Specifications................................................................................91
7.1
Mechanical Specifications ....................................................................................92
7.1.1 Boxed Processor Cooling Solution Dimensions.............................................92
7.1.2 Boxed Processor Fan Heatsink Weight .......................................................94
7.1.3 Boxed Processor Retention Mechanism and Heatsink Attach Clip Assembly .....94
7.2
Electrical Requirements ......................................................................................94
7.2.1 Fan Heatsink Power Supply ......................................................................94
7.3
Thermal Specifications........................................................................................95
7.3.1 Boxed Processor Cooling Requirements......................................................95
7.3.2 Variable Speed Fan .................................................................................97
8
Debug Tools Specifications ......................................................................................99
8.1
Logic Analyzer Interface (LAI) .............................................................................99
8.1.1 Mechanical Considerations .......................................................................99
8.1.2 Electrical Considerations ..........................................................................99
4
Datasheet
Figures
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
VCC Static and Transient Tolerance ............................................................................. 21
VCC Overshoot Example Waveform ............................................................................. 22
Differential Clock Waveform ...................................................................................... 30
Differential Clock Crosspoint Specification ................................................................... 31
Differential Measurements......................................................................................... 31
Differential Clock Waveform ...................................................................................... 33
Differential Clock Crosspoint Specification ................................................................... 33
Processor Package Assembly Sketch ........................................................................... 35
Processor Package Drawing Sheet 1 of 3 ..................................................................... 36
Processor Package Drawing Sheet 2 of 3 ..................................................................... 37
Processor Package Drawing Sheet 3 of 3 ..................................................................... 38
Processor Top-Side Marking Example .......................................................................... 40
Processor Land Coordinates and Quadrants, Top View ................................................... 41
land-out Diagram (Top View – Left Side) ..................................................................... 44
land-out Diagram (Top View – Right Side) ................................................................... 45
Thermal Profile ........................................................................................................ 77
Case Temperature (TC) Measurement Location ............................................................ 78
Thermal Monitor 2 Frequency and Voltage Ordering ...................................................... 80
Processor PECI Topology ........................................................................................... 84
Conceptual Fan Control on PECI-Based Platforms ......................................................... 85
Conceptual Fan Control on Thermal Diode-Based Platforms............................................ 85
Processor Low Power State Machine ........................................................................... 88
Mechanical Representation of the Boxed Processor ....................................................... 91
Space Requirements for the Boxed Processor (Side View).............................................. 92
Space Requirements for the Boxed Processor (Top View)............................................... 93
Space Requirements for the Boxed Processor (Overall View) .......................................... 93
Boxed Processor Fan Heatsink Power Cable Connector Description .................................. 94
Baseboard Power Header Placement Relative to Processor Socket ................................... 95
Boxed Processor Fan Heatsink Airspace Keepout Requirements (Top 1 view) .................... 96
Boxed Processor Fan Heatsink Airspace Keepout Requirements (Side 2 View)................... 96
Boxed Processor Fan Heatsink Set Points..................................................................... 97
Tables
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
Datasheet
References .............................................................................................................. 11
Voltage Identification Definition ................................................................................. 15
Market Segment Selection Truth Table for MSID[1:0] ................................................... 16
Absolute Maximum and Minimum Ratings .................................................................... 18
Voltage and Current Specifications ............................................................................. 19
VCC Static and Transient Tolerance ............................................................................. 20
VCC Overshoot Specifications ..................................................................................... 21
FSB Signal Groups ................................................................................................... 23
Signal Characteristics ............................................................................................... 24
Signal Reference Voltages ......................................................................................... 24
GTL+ Signal Group DC Specifications.......................................................................... 25
Open Drain and TAP Output Signal Group DC Specifications ........................................... 25
CMOS Signal Group DC Specifications ......................................................................... 26
GTL+ Bus Voltage Definitions .................................................................................... 27
Core Frequency to FSB Multiplier Configuration ............................................................ 28
BSEL[2:0] Frequency Table for BCLK[1:0] ................................................................... 29
Front Side Bus Differential BCLK Specifications............................................................. 30
Front Side Bus Differential BCLK Specifications............................................................. 32
PECI DC Electrical Limits ........................................................................................... 34
Processor Loading Specifications ................................................................................ 39
5
21
22
23
24
25
26
27
28
29
30
31
32
33
6
Package Handling Guidelines......................................................................................39
Processor Materials ...................................................................................................40
Alphabetical Land Assignments...................................................................................46
Numerical Land Assignment .......................................................................................56
Signal Description ( ) ................................................................................................66
Processor Thermal Specifications ................................................................................76
Thermal Profile.........................................................................................................77
Thermal “Diode” Parameters using Diode Model ............................................................82
Thermal “Diode” Parameters using Transistor Model ......................................................83
Thermal Diode Interface ............................................................................................83
GetTemp0() Error Codes ...........................................................................................86
Power-On Configuration Option Signals .......................................................................87
Fan Heatsink Power and Signal Specifications ...............................................................97
Datasheet
Revision History
Revision
Number
-001
-002
Description
•
Initial release
•
®
Added Intel
Date
June 2007
Celeron
®
processor 450
August 2008
§
Datasheet
7
Intel® Celeron® Processor 400
Series Features
• Available at 1.60 GHz, 1.8 GHz, 2.00 GHz,
2.2 GHz
• Supports Intel® 64 architecture
• Supports Execute Disable Bit capability
• Binary compatible with applications running
on previous members of the Intel
microprocessor line
• FSB frequency at 800 MHz
•
•
•
•
•
•
•
•
•
•
•
•
Advance Dynamic Execution
Very deep out-of-order execution
Enhanced branch prediction
Optimized for 32-bit applications running on
advanced 32-bit operating systems
•
Two 32-KB Level 1 data caches
1 MB and 512KB Advanced Smart Cache
Advanced Digital Media Boost
Enhanced floating point and multimedia unit
for enhanced video, audio, encryption, and 3D
performance
Power Management capabilities
System Management mode
Multiple low-power states
8-way cache associativity provides improved
cache hit rate on load/store operations
775-land Package
The Intel Celeron processor 400 series delivers Intel's advanced, powerful processors for desktop PCs.
The processor is designed to deliver performance across applications and usages where end-users can
truly appreciate and experience the performance. These applications include Internet audio and
streaming video, image processing, video content creation, speech, 3D, CAD, games, multimedia, and
multitasking user environments.
Intel® 64 architecture enables the processor to execute operating systems and applications written to
take advantage of the Intel 64 architecture. The Intel Celeron processor 400 series also include the
Execute Disable Bit capability. This feature, combined with a supported operating system, allows
memory to be marked as executable or non-executable.
§
8
Datasheet
Introduction
1
Introduction
The Intel® Celeron® processor 400 series is a desktop processor that combines the
performance of the previous generation of Desktop products with the power efficiencies
of a low-power microarchitecture to enable smaller, quieter systems. Intel Celeron
Processor 400 is a 64-bit processor that maintain compatibility with IA-32 software.
The Intel Celeron processor 400 series uses a Flip-Chip Land Grid Array (FC-LGA6)
package technology, and plugs into a 775-land surface mount, Land Grid Array (LGA)
socket, referred to as the LGA775 socket.
Note:
In this document the Intel Celeron processor 400 series will be referred to as "the
processor."
Note:
In this document the Intel Celeron processor 400 series refers to the Intel Celeron
processors 420, 430, 440, and 450.
Based on 65 nm process technology, the Intel Celeron processor 400 series is a singlecore processor that features an 800 MHz front side bus (FSB), 1 MB or 512 KB L2
cache, and a thermal design power (TDP) of 35 W. The processor also supports the
Execute Disable Bit and Intel® 64 architecture.
The processor front side bus (FSB) uses a split-transaction, deferred reply protocol like
the Intel® Pentium® 4 processor. The FSB uses Source-Synchronous Transfer (SST) of
address and data to improve performance by transferring data four times per bus clock
(4X data transfer rate, as in AGP 4X). Along with the 4X data bus, the address bus can
deliver addresses two times per bus clock and is referred to as a "double-clocked" or 2X
address bus. Working together, the 4X data bus and 2X address bus provide a data bus
bandwidth of up to 6.4 GB/s.
Intel will enable support components for the processor including heatsink, heatsink
retention mechanism, and socket. Supported platforms may need to be refreshed to
ensure the correct voltage regulation (VRD11) and that PECI support is enabled.
Manufacturability is a high priority; hence, mechanical assembly may be completed
from the top of the baseboard and should not require any special tooling.
The processor includes an address bus power-down capability which removes power
from the address and data signals when the FSB is not in use. This feature is always
enabled on the processor.
1.1
Terminology
A ‘#’ symbol after a signal name refers to an active low signal, indicating a signal is in
the active state when driven to a low level. For example, when RESET# is low, a reset
has been requested. Conversely, when NMI is high, a nonmaskable interrupt has
occurred. In the case of signals where the name does not imply an active state but
describes part of a binary sequence (such as address or data), the ‘#’ symbol implies
that the signal is inverted. For example, D[3:0] = ‘HLHL’ refers to a hex ‘A’, and
D[3:0]# = ‘LHLH’ also refers to a hex ‘A’ (H= High logic level, L= Low logic level).
Front Side Bus” refers to the interface between the processor and system core logic
(a.k.a. the chipset components). The FSB is a multiprocessing interface to processors,
memory, and I/O.
Datasheet
9
Introduction
1.1.1
Processor Packaging Terminology
Commonly used terms are explained here for clarification:
• Intel Celeron Processor 400 Series — Single core processor in the FC-LGA6
package with a 1 MB or 512 KB L2 cache.
• Processor — For this document, the term processor is the generic form of the Intel
Celeron processor 400 series. The processor is a single package that contains one
exectution unit.
• Keep-out zone — The area on or near the processor that system design can not
use.
• Processor core — Processor core die with integrated L2 cache.
• LGA775 socket — The Intel Celeron processor 400 series mates with the system
board through a surface mount, 775-land, LGA socket.
• Integrated heat spreader (IHS) —A component of the processor package used
to enhance the thermal performance of the package. Component thermal solutions
interface with the processor at the IHS surface.
• Retention mechanism (RM) — Since the LGA775 socket does not include any
mechanical features for heatsink attach, a retention mechanism is required.
Component thermal solutions should attach to the processor via a retention
mechanism that is independent of the socket.
• FSB (Front Side Bus) — The electrical interface that connects the processor to
the chipset. Also referred to as the processor system bus or the system bus. All
memory and I/O transactions as well as interrupt messages pass between the
processor and chipset over the FSB.
• Storage conditions — Refers to a non-operational state. The processor may be
installed in a platform, in a tray, or loose. Processors may be sealed in packaging or
exposed to free air. Under these conditions, processor lands should not be
connected to any supply voltages, have any I/Os biased, or receive any clocks.
Upon exposure to “free air”(i.e., unsealed packaging or a device removed from
packaging material) the processor must be handled in accordance with moisture
sensitivity labeling (MSL) as indicated on the packaging material.
• Functional operation — Refers to normal operating conditions in which all
processor specifications, including DC, AC, system bus, signal quality, mechanical
and thermal are satisfied.
• Execute Disable Bit — The Execute Disable bit allows memory to be marked as
executable or non-executable, when combined with a supporting operating system.
If code attempts to run in non-executable memory the processor raises an error to
the operating system. This feature can prevent some classes of viruses or worms
that exploit buffer over run vulnerabilities and can thus help improve the overall
security of the system. See the Intel® Architecture Software Developer's Manual
for more detailed information.
• Intel® 64 Architecture — An enhancement to Intel's IA-32 architecture, allowing
the processor to execute operating systems and applications written to take
advantage of the Intel® 64 architecture. Further details on Intel® 64 architecture
and programming model can be found in the Intel Extended Memory 64 Technology
Software Developer Guide at http://developer.intel.com/technology/
64bitextensions/.
10
Datasheet
Introduction
1.2
References
Material and concepts available in the following documents may be beneficial when
reading this document.
Table 1.
References
Document
Location
Intel® Celeron® Processor 400 Series Specification Update
www.intel.com/
design/processor/
specupdt/316964.htm
Intel® Celeron® Processor 400 Series Thermal and Mechanical Design
Guidelines
www.intel.com/
design/processor/
designex/316965.htm
Voltage Regulator-Down (VRD) 11 Design Guide For Desktop and
Transportable LGA775 Socket
http://www.intel.com/
design/processor/
applnots/313214.htm
LGA775 Socket Mechanical Design Guide
http://intel.com/
design/Pentium4/
guides/302666.htm
Intel® 64 and IA-32 Architecture Software Developer’s Manuals
Intel® 64 and IA-32 Architecture Software Developer’s Manual
Volume 1: Basic Architecture
Intel® 64 and IA-32 Architecture Software Developer’s Manual
Volume 2A: Instruction Set Reference Manual A–M
Intel® 64 and IA-32 Architecture Software Developer’s Manual
Volume 2B: Instruction Set Reference Manual, N–Z
http://www.intel.com/
products/processor/
manuals/
Intel® 64 and IA-32 Architecture Software Developer’s Manual
Volume 3A: System Programming Guide
Intel® 64 and IA-32 Architecture Software Developer’s Manual
Volume 3B: System Programming Guide
§
Datasheet
11
Introduction
12
Datasheet
Electrical Specifications
2
Electrical Specifications
This chapter describes the electrical characteristics of the processor interfaces and
signals. DC electrical characteristics are provided.
2.1
Power and Ground Lands
The processor has VCC (power), VTT and VSS (ground) inputs for on-chip power
distribution. All power lands must be connected to VCC, while all VSS lands must be
connected to a system ground plane. The processor VCC lands must be supplied the
voltage determined by the Voltage IDentification (VID) lands.
The signals denoted as VTT, provide termination for the front side bus and power to the
I/O buffers. A separate supply must be implemented for these lands, that meets the
VTT specifications outlined in Table 5.
2.2
Decoupling Guidelines
Due to its large number of transistors and high internal clock speeds, the processor is
capable of generating large current swings. This may cause voltages on power planes
to sag below their minimum specified values if bulk decoupling is not adequate. Larger
bulk storage (CBULK), such as electrolytic or aluminum-polymer capacitors, supply
current during longer lasting changes in current demand by the component, such as
coming out of an idle condition. Similarly, they act as a storage well for current when
entering an idle condition from a running condition. The motherboard must be designed
to ensure that the voltage provided to the processor remains within the specifications
listed in Table 5. Failure to do so can result in timing violations or reduced lifetime of
the component.
2.2.1
VCC Decoupling
VCC regulator solutions need to provide sufficient decoupling capacitance to satisfy the
processor voltage specifications. This includes bulk capacitance with low effective series
resistance (ESR) to keep the voltage rail within specifications during large swings in
load current. In addition, ceramic decoupling capacitors are required to filter high
frequency content generated by the front side bus and processor activity. Consult the
Voltage Regulator-Down (VRD) 11 Design Guide For Desktop and Transportable
LGA775 Socket for further information.
2.2.2
VTT Decoupling
Decoupling must be provided on the motherboard. Decoupling solutions must be sized
to meet the expected load. To ensure compliance with the specifications, various
factors associated with the power delivery solution must be considered including
regulator type, power plane and trace sizing, and component placement. A
conservative decoupling solution would consist of a combination of low ESR bulk
capacitors and high frequency ceramic capacitors.
Datasheet
13
Electrical Specifications
2.2.3
FSB Decoupling
The processor integrates signal termination on the die. In addition, some of the high
frequency capacitance required for the FSB is included on the processor package.
However, additional high frequency capacitance must be added to the motherboard to
properly decouple the return currents from the front side bus. Bulk decoupling must
also be provided by the motherboard for proper [A]GTL+ bus operation.
2.3
Voltage Identification
The Voltage Identification (VID) specification for the processor is defined by the Voltage
Regulator-Down (VRD) 11 Design Guide For Desktop and Transportable LGA775. The
voltage set by the VID signals is the reference VR output voltage to be delivered to the
processor VCC pins (see Chapter 2.6.3 for VCC overshoot specifications). Refer to
Table 13 for the DC specifications for these signals. Voltages for each processor
frequency is provided in Table 5.
Individual processor VID values may be calibrated during manufacturing such that two
devices at the same core speed may have different default VID settings. This is
reflected by the VID Range values provided in Table 5. Refer to the Intel® Celeron®
Processor 400 Series Specification Update for further details on specific valid core
frequency and VID values of the processor. Please note this differs from the VID
employed by the processor during a power management event (Thermal Monitor 2).
The processor uses six voltage identification signals, VID[6:1], to support automatic
selection of power supply voltages. Table 2 specifies the voltage level corresponding to
the state of VID[6:1]. A ‘1’ in this table refers to a high voltage level and a ‘0’ refers to
a low voltage level. If the processor socket is empty (VID[6:1] = 111111), or the
voltage regulation circuit cannot supply the voltage that is requested, it must disable
itself. The Voltage Regulator-Down (VRD) 11 Design Guide For Desktop and
Transportable LGA775 defines VID [7:0], VID7 and VID0 are not used on the
processor; VID0 and VID7 is strapped to VSS on the processor package. VID0 and VID7
must be connected to the VR controller for compatibility with future processors.
The processor provides the ability to operate while transitioning to an adjacent VID and
its associated processor core voltage (VCC). This will represent a DC shift in the load
line. It should be noted that a low-to-high or high-to-low voltage state change may
result in as many VID transitions as necessary to reach the target core voltage.
Transitions above the specified VID are not permitted. Table 5 includes VID step sizes
and DC shift ranges. Minimum and maximum voltages must be maintained as shown in
Table 6 and Figure 1 as measured across the VCC_SENSE and VSS_SENSE lands.
The VRM or VRD utilized must be capable of regulating its output to the value defined
by the new VID. DC specifications for dynamic VID transitions are included in Table 5
and Table 6. Refer to the Voltage Regulator-Down (VRD) 11 Design Guide For Desktop
and Transportable LGA775 for further details.
14
Datasheet
Electrical Specifications
Table 2.
Voltage Identification Definition
VID
6
VID
5
VID
4
VID
3
VID
2
VID
1
VCC_MAX
VID
6
VID
5
VID
4
VID
3
VID
2
VID
1
VCC_MAX
1
1
1
1
0
1
0.8500
0
1
1
1
1
0
1.2375
1
1
1
1
0
0
0.8625
0
1
1
1
0
1
1.2500
1
1
1
0
1
1
0.8750
0
1
1
1
0
0
1.2625
1
1
1
0
1
0
0.8875
0
1
1
0
1
1
1.2750
1
1
1
0
0
1
0.9000
0
1
1
0
1
0
1.2875
1
1
1
0
0
0
0.9125
0
1
1
0
0
1
1.3000
1
1
0
1
1
1
0.9250
0
1
1
0
0
0
1.3125
1
1
0
1
1
0
0.9375
0
1
0
1
1
1
1.3250
1
1
0
1
0
1
0.9500
0
1
0
1
1
0
1.3375
1
1
0
1
0
0
0.9625
0
1
0
1
0
1
1.3500
1
1
0
0
1
1
0.9750
0
1
0
1
0
0
1.3625
1
1
0
0
1
0
0.9875
0
1
0
0
1
1
1.3750
1
1
0
0
0
1
1.0000
0
1
0
0
1
0
1.3875
1
1
0
0
0
0
1.0125
0
1
0
0
0
1
1.4000
1
0
1
1
1
1
1.0250
0
1
0
0
0
0
1.4125
1
0
1
1
1
0
1.0375
0
0
1
1
1
1
1.4250
1
0
1
1
0
1
1.0500
0
0
1
1
1
0
1.4375
1
0
1
1
0
0
1.0625
0
0
1
1
0
1
1.4500
1
0
1
0
1
1
1.0750
0
0
1
1
0
0
1.4625
1
0
1
0
1
0
1.0875
0
0
1
0
1
1
1.4750
1
0
1
0
0
1
1.1000
0
0
1
0
1
0
1.4875
1
0
1
0
0
0
1.1125
0
0
1
0
0
1
1.5000
1
0
0
1
1
1
1.1250
0
0
1
0
0
0
1.5125
1
0
0
1
1
0
1.1375
0
0
0
1
1
1
1.5250
1
0
0
1
0
1
1.1500
0
0
0
1
1
0
1.5375
1
0
0
1
0
0
1.1625
0
0
0
1
0
1
1.5500
1
0
0
0
1
1
1.1750
0
0
0
1
0
0
1.5625
1
0
0
0
1
0
1.1875
0
0
0
0
1
1
1.5750
1
0
0
0
0
1
1.2000
0
0
0
0
1
0
1.5875
1
0
0
0
0
0
1.2125
0
0
0
0
0
1
1.6000
0
1
1
1
1
1
1.2250
0
0
0
0
0
0
OFF
Datasheet
15
Electrical Specifications
2.4
Market Segment Identification (MSID)
The MSID[1:0] signals may be used as outputs to determine the Market Segment of
the processor. Table 3 provides details regarding the state of MSID[1:0]. A circuit can
be used to prevent 130 W TDP processors from booting on boards optimized for 65 W
TDP.
Table 3.
Market Segment Selection Truth Table for MSID[1:0]1, 2, 3, 4
MSID1
MSID0
0
0
Intel® Core™2 Duo desktop processor E6000 and E4000 series, Intel®
Core™2 Extreme processor X6800, Intel® Celeron® Processor 400
0
1
Reserved
1
0
Reserved
1
Intel® Core™2 Extreme Quad-Core Processor QX6700D and Intel® Core™2
Quad Processor Q6000 series
1
Description
NOTES:
1. The MSID[1:0] signals are provided to indicate the Market Segment for the processor and may be used for
future processor compatibility or for keying. Circuitry on the motherboard may use these signals to identify
the processor installed.
2. These signals are not connected to the processor die.
3. A logic 0 is achieved by pulling the signal to ground on the package.
4. A logic 1 is achieved by leaving the signal as a no connect on the package.
2.5
Reserved, Unused and TESTHI Signals
All RESERVED lands must remain unconnected. Connection of these lands to VCC, VSS,
VTT, or to any other signal (including each other) can result in component malfunction
or incompatibility with future processors. See Chapter 4 for a land listing of the
processor and the location of all RESERVED lands.
In a system level design, on-die termination has been included by the processor to
allow signals to be terminated within the processor silicon. Most unused GTL+ inputs
should be left as no connects as GTL+ termination is provided on the processor silicon.
However, see Table 8 for details on GTL+ signals that do not include on-die termination.
Unused active high inputs, should be connected through a resistor to ground (VSS).
Unused outputs can be left unconnected, however this may interfere with some TAP
functions, complicate debug probing, and prevent boundary scan testing. A resistor
must be used when tying bidirectional signals to power or ground. When tying any
signal to power or ground, a resistor will also allow for system testability. Resistor
values should be within ± 20% of the impedance of the motherboard trace for front
side bus signals. For unused GTL+ input or I/O signals, use pull-up resistors of the
same value as the on-die termination resistors (RTT). For details see Table 14.
TAP and CMOS signals do not include on-die termination. Inputs and utilized outputs
must be terminated on the motherboard. Unused outputs may be terminated on the
motherboard or left unconnected. Note that leaving unused outputs unterminated may
interfere with some TAP functions, complicate debug probing, and prevent boundary
scan testing.
All TESTHI[13:0] lands should be individually connected to VTT via a pull-up resistor
which matches the nominal trace impedance.
16
Datasheet
Electrical Specifications
The TESTHI signals may use individual pull-up resistors or be grouped together as
detailed below. A matched resistor must be used for each group:
• TESTHI[1:0]
• TESTHI[7:2]
• TESTHI8/FC42 – cannot be grouped with other TESTHI signals
• TESTHI9/FC43 – cannot be grouped with other TESTHI signals
• TESTHI10 – cannot be grouped with other TESTHI signals
• TESTHI11 – cannot be grouped with other TESTHI signals
• TESTHI12/FC44 – cannot be grouped with other TESTHI signals
• TESTHI13 – cannot be grouped with other TESTHI signals
However, using boundary scan test will not be functional if these lands are connected
together. For optimum noise margin, all pull-up resistor values used for TESTHI[13:0]
lands should have a resistance value within ± 20% of the impedance of the board
transmission line traces. For example, if the nominal trace impedance is 50 Ω, then a
value between 40 Ω and 60 Ω should be used.
2.6
Voltage and Current Specification
2.6.1
Absolute Maximum and Minimum Ratings
Table 4 specifies absolute maximum and minimum ratings only and lie outside the
functional limits of the processor. Within functional operation limits, functionality and
long-term reliability can be expected.
At conditions outside functional operation condition limits, but within absolute
maximum and minimum ratings, neither functionality nor long-term reliability can be
expected. If a device is returned to conditions within functional operation limits after
having been subjected to conditions outside these limits, but within the absolute
maximum and minimum ratings, the device may be functional, but with its lifetime
degraded depending on exposure to conditions exceeding the functional operation
condition limits.
At conditions exceeding absolute maximum and minimum ratings, neither functionality
nor long-term reliability can be expected. Moreover, if a device is subjected to these
conditions for any length of time then, when returned to conditions within the
functional operating condition limits, it will either not function, or its reliability will be
severely degraded.
Although the processor contains protective circuitry to resist damage from static
electric discharge, precautions should always be taken to avoid high static voltages or
electric fields.
Datasheet
17
Electrical Specifications
Table 4.
Absolute Maximum and Minimum Ratings
Symbol
Notes1, 2
Parameter
Min
Max
Unit
VCC
Core voltage with respect to VSS
–0.3
1.55
V
-
VTT
FSB termination voltage with
respect to VSS
–0.3
1.55
V
-
TC
Processor case temperature
See
Chapter 5
See
Chapter 5
°C
-
TSTORAGE
Processor storage temperature
–40
85
°C
3, 4, 5
NOTES:
1.
For functional operation, all processor electrical, signal quality, mechanical and thermal
specifications must be satisfied.
2.
Excessive overshoot or undershoot on any signal will likely result in permanent damage to
the processor.
3.
Storage temperature is applicable to storage conditions only. In this scenario, the
processor must not receive a clock, and no lands can be connected to a voltage bias.
Storage within these limits will not affect the long-term reliability of the device. For
functional operation, refer to the processor case temperature specifications.
4.
This rating applies to the processor and does not include any tray or packaging.
5.
Failure to adhere to this specification can affect the long term reliability of the processor.
18
Datasheet
Electrical Specifications
2.6.2
DC Voltage and Current Specification
Table 5.
Voltage and Current Specifications
Symbol
Parameter
VID Range
VID
Processor Number
VCC
2.2 GHz
440
2.0 GHz
430
1.8 GHz
420
1.6 GHz
VCC_BOOT
Default VCC voltage for initial power up
VCCPLL
PLL VCC
ICC
ITT
Unit
1.0000
—
1.3375
V
3
Refer to Table 6 and
Figure 1
V
4, 5, 6
V
—
1.10
—
- 5%
1.50
+ 5%
—
—
450
2.2 GHz
440
2.0 GHz
430
1.8 GHz
35
420
1.6 GHz
35
(DC + AC specifications)
VTT_OUT_LEFT
and
VTT_OUT_RIGHT
ICC
Max
ICC for
775_VR_CONFIG_06
FSB termination voltage
VTT
Typ
Core VCC
450
Processor Number
Notes2, 15
Min
DC Current that may be drawn from
VTT_OUT_LEFT and VTT_OUT_RIGHT per pin
ICC for VTT supply before VCC stable
ICC for VTT supply after VCC stable
35
35
A
7
1.14
1.20
1.26
V
8
—
—
580
mA
9
—
—
4.5
4.6
A
ICC_VCCPLL
ICC for PLL land
—
—
130
mA
ICC_GTLREF
ICC for GTLREF
—
—
200
μA
10
NOTES:
1.
Unless otherwise noted, all specification in this table are based on estimates and
simulation or empirical data. These specifications will be updated with characterized data
from silicon measurements at a later date.
2.
Adherence to the voltage specification for the processor are required to ensure reliable
processor operation.
3.
Each processor is programmed with a maximum valid voltage identification value (VID),
which is set at manufacturing and can not be altered. Individual maximum VID values are
calibrated during manufacturing such that two processors at the same frequency may have
different settings within the VID range. Please note this differs from the VID employed by
the processor during a power management event (Thermal Monitor 2).
4.
These voltages are targets only. A variable voltage source should exist on systems in the
event that a different voltage is required. See Section 2.3 and Table 2 for more
information.
5.
The voltage specification requirements are measured across VCC_SENSE and VSS_SENSE
lands at the socket with a 100 MHz bandwidth oscilloscope, 1.5 pF maximum probe
capacitance, and 1 MΩ minimum impedance. The maximum length of ground wire on the
probe should be less than 5 mm. Ensure external noise from the system is not coupled into
the oscilloscope probe.
6.
Refer to Table 6 and Figure 1 for the minimum, typical, and maximum VCC allowed for a
given current. The processor should not be subjected to any VCC and ICC combination
wherein VCC exceeds VCC_MAX for a given current.
7.
ICC_MAX specification is based on the VCC_MAX loadline. Refer to Figure 1f or details.
Datasheet
19
Electrical Specifications
8.
9.
10.
11.
12.
Table 6.
VTT must be provided via a separate voltage source and not be connected to VCC. This
specification is measured at the land.
Baseboard bandwidth is limited to 20 MHz.
This is maximum total current drawn from VTT plane by only the processor. This
specification does not include the current coming from RTT (through the signal line). Refer
to the Voltage Regulator-Down (VRD) 11.0 Processor Power Delivery Design Guidelines For
Desktop LGA775 Socket to determine the total ITT drawn by the system. This parameter is
based on design characterization and is not tested.
This is maximum total current drawn from VTT plane by only the processor. This
specification does not include the current coming from RTT (through the signal line). Refer
to the Voltage Regulator-Down (VRD) 11 Design Guide For Desktop and Transportable
LGA775 to determine the total ITT drawn by the system. This parameter is based on design
characterization and is not tested.
Adherence to the voltage specifications for the processor are required to ensure reliable
processor operation.
VCC Static and Transient Tolerance
Voltage Deviation from VID Setting (V)1, 2, 3, 4
ICC (A)
Maximum Voltage
2.30 mΩ
Typical Voltage
2.40 mΩ
Minimum Voltage
2.50mΩ
-0.038
0
0.000
-0.019
5
-0.012
-0.031
-0.051
10
-0.023
-0.043
-0.063
15
-0.035
-0.055
-0.076
20
-0.046
-0.067
-0.088
25
-0.058
-0.079
-0.101
30
-0.069
-0.091
-0.113
35
-0.081
-0.103
-0.126
NOTES:
1.
The loadline specification includes both static and transient limits except for overshoot
allowed as shown in Section 2.6.3.
2.
This table is intended to aid in reading discrete points on Figure 1.
3.
The loadlines specify voltage limits at the die measured at the VCC_SENSE and
VSS_SENSE lands. Voltage regulation feedback for voltage regulator circuits must be taken
from processor VCC and VSS lands. Refer to the Voltage Regulator-Down (VRD) 11 Design
Guide For Desktop and Transportable LGA775 for socket loadline guidelines and VR
implementation details.
4.
Adherence to this loadline specification is required to ensure reliable processor operation.
20
Datasheet
Electrical Specifications
Figure 1.
VCC Static and Transient Tolerance
Icc [A]
0
10
20
30
VID - 0.000
VID - 0.013
Vcc Maximum
VID - 0.025
VID - 0.038
VID - 0.050
Vcc [V]
VID - 0.063
Vcc Typical
VID - 0.075
VID - 0.088
Vcc Minimum
VID - 0.100
VID - 0.113
VID - 0.125
VID - 0.138
VID - 0.150
NOTES:
1.
The loadline specification includes both static and transient limits except for overshoot
allowed as shown in Section 2.6.3.
2.
This loadline specification shows the deviation from the VID set point.
3.
The loadlines specify voltage limits at the die measured at the VCC_SENSE and
VSS_SENSE lands. Voltage regulation feedback for voltage regulator circuits must be taken
from processor VCC and VSS lands. Refer to the Voltage Regulator-Down (VRD) 11 Design
Guide For Desktop and Transportable LGA775 for socket loadline guidelines and VR
implementation details.
2.6.3
VCC Overshoot
The processor can tolerate short transient overshoot events where VCC exceeds the VID
voltage when transitioning from a high to low current load condition. This overshoot
cannot exceed VID + VOS_MAX (VOS_MAX is the maximum allowable overshoot voltage).
The time duration of the overshoot event must not exceed TOS_MAX (TOS_MAX is the
maximum allowable time duration above VID). These specifications apply to the
processor die voltage as measured across the VCC_SENSE and VSS_SENSE lands.
Table 7.
VCC Overshoot Specifications
Symbol
Parameter
Min
Max
Unit
Figure
Notes
VOS_MAX
Magnitude of VCC overshoot above
VID
—
50
mV
2
1
TOS_MAX
Time duration of VCC overshoot above
VID
—
25
μs
2
1
NOTES:
1.
Adherence to these specifications is required to ensure reliable processor operation.
Datasheet
21
Electrical Specifications
Figure 2.
VCC Overshoot Example Waveform
Example Overshoot Waveform
VOS
Voltage [V]
VID + 0.050
VID - 0.000
TOS
0
5
10
15
20
25
Time [us]
TOS: Overshoot time above VID
VOS: Overshoot above VID
NOTES:
1.
VOS is measured overshoot voltage.
2.
TOS is measured time duration above VID.
2.6.4
Die Voltage Validation
Overshoot events on processor must meet the specifications in Table 7 when measured
across the VCC_SENSE and VSS_SENSE lands. Overshoot events that are < 10 ns in
duration may be ignored. These measurements of processor die level overshoot must
be taken with a bandwidth limited oscilloscope set to a greater than or equal to
100 MHz bandwidth limit.
2.7
Signaling Specifications
Most processor Front Side Bus signals use Gunning Transceiver Logic (GTL+) signaling
technology. This technology provides improved noise margins and reduced ringing
through low voltage swings and controlled edge rates. Platforms implement a
termination voltage level for GTL+ signals defined as VTT. Because platforms implement
separate power planes for each processor (and chipset), separate VCC and VTT supplies
are necessary. This configuration allows for improved noise tolerance as processor
frequency increases. Speed enhancements to data and address busses have caused
signal integrity considerations and platform design methods to become even more
critical than with previous processor families.
The GTL+ inputs require a reference voltage (GTLREF) which is used by the receivers to
determine if a signal is a logical 0 or a logical 1. GTLREF must be generated on the
motherboard (see Table 14 for GTLREF specifications). Termination resistors (RTT) for
GTL+ signals are provided on the processor silicon and are terminated to VTT. Intel
chipsets will also provide on-die termination; thus, eliminating the need to terminate
the bus on the motherboard for most GTL+ signals.
22
Datasheet
Electrical Specifications
2.7.1
FSB Signal Groups
The front side bus signals have been combined into groups by buffer type. GTL+ input
signals have differential input buffers, which use GTLREF[1:0] as a reference level. In
this document, the term “GTL+ Input” refers to the GTL+ input group as well as the
GTL+ I/O group when receiving. Similarly, “GTL+ Output” refers to the GTL+ output
group as well as the GTL+ I/O group when driving.
With the implementation of a source synchronous data bus comes the need to specify
two sets of timing parameters. One set is for common clock signals which are
dependent upon the rising edge of BCLK0 (ADS#, HIT#, HITM#, etc.) and the second
set is for the source synchronous signals which are relative to their respective strobe
lines (data and address) as well as the rising edge of BCLK0. Asychronous signals are
still present (A20M#, IGNNE#, etc.) and can become active at any time during the
clock cycle. Table 8 identifies which signals are common clock, source synchronous,
and asynchronous.
Table 8.
FSB Signal Groups (Sheet 1 of 2)
Signal Group
GTL+ Common
Clock Input
Synchronous to
BCLK[1:0]
BPRI#, DEFER#, RESET#, RS[2:0]#, TRDY#
GTL+ Common
Clock I/O
Synchronous to
BCLK[1:0]
ADS#, BNR#, BPM[5:0]#, BR0#, DBSY#, DRDY#, HIT#,
HITM#, LOCK#
GTL+ Source
Synchronous I/O
GTL+ Strobes
Synchronous to
assoc. strobe
Synchronous to
BCLK[1:0]
Signals
Associated Strobe
REQ[4:0]#, A[16:3]#3
ADSTB0#
A[35:17]#3
ADSTB1#
D[15:0]#, DBI0#
DSTBP0#, DSTBN0#
D[31:16]#, DBI1#
DSTBP1#, DSTBN1#
D[47:32]#, DBI2#
DSTBP2#, DSTBN2#
D[63:48]#, DBI3#
DSTBP3#, DSTBN3#
ADSTB[1:0]#, DSTBP[3:0]#, DSTBN[3:0]#
CMOS
A20M#, IGNNE#, INIT#, LINT0/INTR, LINT1/NMI, SMI#,
STPCLK#, PWRGOOD, TCK, TDI, TMS, TRST#,
BSEL[2:0], VID[6:1]
Open Drain
Output
FERR#/PBE#, IERR#, THERMTRIP#, TDO
Open Drain
Input/Output
PROCHOT#4
FSB Clock
Datasheet
Signals1
Type
Clock
BCLK[1:0], ITP_CLK[1:0]2
23
Electrical Specifications
Table 8.
FSB Signal Groups (Sheet 2 of 2)
Signal Group
Signals1
Type
VCC, VTT, VCCA, VCCIOPLL, VCCPLL, VSS, VSSA,
GTLREF[1:0], COMP[8,3:0], RESERVED, TESTHI[13:0],
VCC_SENSE, VCC_MB_REGULATION, VSS_SENSE,
VSS_MB_REGULATION, DBR#2, VTT_OUT_LEFT,
VTT_OUT_RIGHT, VTT_SEL, FCx, PECI
Power/Other
NOTES:
1.
Refer to Section 4.2 for signal descriptions.
2.
In processor systems where no debug port is implemented on the system board, these
signals are used to support a debug port interposer. In systems with the debug port
implemented on the system board, these signals are no connects.
3.
The value of these signals during the active-to-inactive edge of RESET# defines the
processor configuration options. See Section 6.1 for details.
4.
PROCHOT# signal type is open drain output and CMOS input.
.
Table 9.
Signal Characteristics
Signals with RTT
Signals with No RTT
A[35:3]#, ADS#, ADSTB[1:0]#, BNR#, BPRI#,
D[63:0]#, DBI[3:0]#, DBSY#, DEFER#,
DRDY#, DSTBN[3:0]#, DSTBP[3:0]#, HIT#,
HITM#, LOCK#, PROCHOT#, REQ[4:0]#,
RS[2:0]#, TRDY#
A20M#, BCLK[1:0], BSEL[2:0],
COMP[8,3:0], IGNNE#, INIT#, ITP_CLK[1:0],
LINT0/INTR, LINT1/NMI, PWRGOOD,
RESET#, SMI#, STPCLK#, TESTHI[13:0],
VID[6:0], GTLREF[1:0], TCK, TDI, TMS,
TRST#
Open Drain Signals1
THERMTRIP#, FERR#/PBE#, IERR#, BPM[5:0]#,
BR0#, TDO, VTT_SEL, FCx
NOTES:
1.
Signals that do not have RTT, nor are actively driven to their high-voltage level.
Table 10.
Signal Reference Voltages
GTLREF
BPM[5:0]#, RESET#, BNR#, HIT#, HITM#, BR0#,
A[35:0]#, ADS#, ADSTB[1:0]#, BPRI#, D[63:0]#,
DBI[3:0]#, DBSY#, DEFER#, DRDY#, DSTBN[3:0]#,
DSTBP[3:0]#, LOCK#, REQ[4:0]#, RS[2:0]#,
TRDY#
VTT/2
A20M#, LINT0/INTR, LINT1/NMI,
IGNNE#, INIT#, PROCHOT#,
PWRGOOD1, SMI#, STPCLK#, TCK1,
TDI1, TMS1, TRST#1
NOTE:
1.
These signals also have hysteresis added to the reference voltage. See Table 12 for more
information.
24
Datasheet
Electrical Specifications
2.7.2
CMOS and Open Drain Signals
Legacy input signals such as A20M#, IGNNE#, INIT#, SMI#, and STPCLK# use CMOS
input buffers. All of the CMOS and Open Drain signals are required to be asserted/deasserted for at least four BCLKs for the processor to recognize the proper signal state.
See Section 2.7.3 for the DC specifications. See Section 6.2 for additional timing
requirements for entering and leaving the low power states.
2.7.3
Processor DC Specifications
The processor DC specifications in this section are defined at the processor
core (pads) unless otherwise stated. All specifications apply to all frequencies
and cache sizes unless otherwise stated.
Table 11.
GTL+ Signal Group DC Specifications
Symbol
Parameter
Min
Max
Unit
Notes1
V
2, 5
VIL
Input Low Voltage
-0.10
GTLREF – 0.10
VIH
Input High Voltage
GTLREF + 0.10
VTT + 0.10
V
3, 4, 5
VOH
Output High Voltage
VTT – 0.10
VTT
V
4, 5
IOL
Output Low Current
N/A
VTT_MAX/
[(RTT_MIN)+(RON_MIN)]
A
-
ILI
Input Leakage Current
N/A
± 100
µA
6
ILO
Output Leakage Current
N/A
± 100
µA
7
RON
Buffer On Resistance
10
13
Ω
NOTES:
1.
Unless otherwise noted, all specifications in this table apply to all processor frequencies.
2.
VIL is defined as the voltage range at a receiving agent that will be interpreted as a logical
low value.
3.
VIH is defined as the voltage range at a receiving agent that will be interpreted as a logical
high value.
4.
VIH and VOH may experience excursions above VTT. However, input signal drivers must
comply with the signal quality specifications.
5.
The VTT referred to in these specifications is the instantaneous VTT.
6.
Leakage to VSS with land held at VTT.
7.
Leakage to VTT with land held at 300 mV.
Table 12.
Open Drain and TAP Output Signal Group DC Specifications
Symbol
Parameter
Min
Max
Unit
Notes1
VOL
Output Low Voltage
0
0.20
V
-
IOL
Output Low Current
16
50
mA
2
ILO
Output Leakage Current
N/A
± 200
µA
3
NOTES:
1.
Unless otherwise noted, all specifications in this table apply to all processor frequencies.
2.
Measured at VTT * 0.2.
3.
For Vin between 0 and VOH
Datasheet
25
Electrical Specifications
.
Table 13.
CMOS Signal Group DC Specifications
Symbol
Parameter
Min
Max
Unit
Notes1
VIL
Input Low Voltage
-0.10
VTT * 0.30
V
2, 3
VIH
Input High Voltage
VTT * 0.70
VTT + 0.10
V
4, 5, 3
VOL
Output Low Voltage
-0.10
VTT * 0.10
V
3
VOH
Output High Voltage
0.90 * VTT
VTT + 0.10
V
6, 5, 3
IOL
Output Low Current
1.70
4.70
mA
3, 7
IOH
Output High Current
1.70
4.70
mA
3, 7
ILI
Input Leakage Current
N/A
± 100
µA
8
ILO
Output Leakage Current
N/A
± 100
µA
9
NOTES:
1.
Unless otherwise noted, all specifications in this table apply to all processor frequencies.
2.
VIL is defined as the voltage range at a receiving agent that will be interpreted as a logical
low value.
3.
The VTT referred to in these specifications refers to instantaneous VTT.
4.
VIH is defined as the voltage range at a receiving agent that will be interpreted as a logical
high value.
5.
VIH and VOH may experience excursions above VTT. .
6.
All outputs are open drain.
7.
IOL is measured at 0.10 * VTT. IOH is measured at 0.90 * VTT.
8.
Leakage to VSS with land held at VTT.
9.
Leakage to VTT with land held at 300 mV
26
Datasheet
Electrical Specifications
2.7.3.1
GTL+ Front Side Bus Specifications
In most cases, termination resistors are not required as these are integrated into the
processor silicon. See Table 9 for details on which GTL+ signals do not include on-die
termination.
Valid high and low levels are determined by the input buffers by comparing with a
reference voltage called GTLREF. Table 14 lists the GTLREF specifications for both
50 Ohm and 60 Ohm platforms. The GTL+ reference voltage (GTLREF) should be
generated on the system board using high precision voltage divider circuits.
Table 14.
GTL+ Bus Voltage Definitions
Symbol
Parameter
Min
Typ
Max
Units
Notes1
GTLREF_PU
GTLREF pull up resistor
124 * 0.99
124
124 * 1.01
Ω
GTLREF_PD
GTLREF pull down resistor
210 * 0.99
210
210 * 1.01
Ω
2, 4
RTT
COMP[3:0]
COMP8
45
50
55
Ω
3
60 Ω Platform termination
Resistance
Termination Resistance
60.4 * 0.99
60.4
60.4 * 1.01
Ω
4
50 Ω Platform termination
Resistance
49.9 * 0.99
49.9
49.9 * 1.01
Ω
4
60 Ω Platform termination
Resistance
30.1 * 0.99
30.1
30.1 * 1.01
Ω
4
50 Ω Platform termination
Resistance
24.9 * 0.99
24.9
24.9 * 1.01
Ω
4
NOTES:
1.
Unless otherwise noted, all specifications in this table apply to all processor frequencies.
2.
GTLREF is to be generated from VTT by a voltage divider of 1% resistors (one divider for
each GTLEREF land).
3.
RTT is the on-die termination resistance measured at VTT/3 of the GTL+ output driver.
4.
COMP resistance must be provided on the system board with 1% resistors. COMP[3:0] and
COMP8 resistors are to VSS.
Datasheet
27
Electrical Specifications
2.8
Clock Specifications
2.8.1
Front Side Bus Clock (BCLK[1:0]) and Processor Clocking
BCLK[1:0] directly controls the FSB interface speed as well as the core frequency of the
processor. As in previous generation processors, the processor’s core frequency is a
multiple of the BCLK[1:0] frequency. The processor bus ratio multiplier will be set at its
default ratio during manufacturing. Refer to Table 15 for the processor supported
ratios.
The processor uses a differential clocking implementation. For more information on the
processor clocking, contact your Intel field representative. Platforms using a CK505
Clock Synthhesizer/Driver should comply with the specifications in Section 2.8.4.
Platforms using a CK410 Clock Synthesizer/Driver should comply with the specifications
in Section 2.8.5.
Table 15.
Core Frequency to FSB Multiplier Configuration
Multiplication of System
Core Frequency to FSB
Frequency
Core Frequency
(200 MHz BCLK/800 MHz
FSB)
Notes1, 2
1/6
1.20 GHz
-
1/7
1.40 GHz
-
1/8
1.60 GHz
-
1/9
1.80 GHz
-
1/10
2 GHz
-
1/11
2.2 GHz
-
1/12
2.4 GHz
-
1/13
2.6 GHz
-
1/14
2.8 GHz
-
NOTES:
1.
Individual processors operate only at or below the rated frequency.
2.
Listed frequencies are not necessarily committed production frequencies.
28
Datasheet
Electrical Specifications
2.8.2
FSB Frequency Select Signals (BSEL[2:0])
The BSEL[2:0] signals are used to select the frequency of the processor input clock
(BCLK[1:0]). Table 16 defines the possible combinations of the signals and the
frequency associated with each combination. The required frequency is determined by
the processor, chipset, and clock synthesizer. All agents must operate at the same
frequency.
The processor will operate at an 800 MHz FSB frequency (selected by a 200 MHz
BCLK[1:0] frequency). Individual processors will only operate at their specified FSB
frequency.
Table 16.
2.8.3
BSEL[2:0] Frequency Table for BCLK[1:0]
BSEL2
BSEL1
BSEL0
FSB Frequency
L
L
L
RESERVED
L
L
H
RESERVED
L
H
H
RESERVED
L
H
L
200 MHz
H
H
L
RESERVED
H
H
H
RESERVED
H
L
H
RESERVED
H
L
L
RESERVED
Phase Lock Loop (PLL) and Filter
An on-die PLL filter solution will be implemented on the processor. The VCCPLL input is
used for the PLL. Refer to Table 5 for DC specifications.
Datasheet
29
Electrical Specifications
2.8.4
BCLK[1:0] Specifications (CK505 based Platforms)
Table 17.
Front Side Bus Differential BCLK Specifications
Symbol
Parameter
VL
Input Low Voltage
VH
Input High Voltage
VCROSS(abs)
Figure 3.
Figure
Notes1
-0.30
N/A
N/A
V
3
4
N/A
N/A
1.15
V
3
4
0.300
N/A
0.550
V
3, 4
2,4,6
N/A
N/A
0.140
V
3, 4
-
N/A
N/A
1.4
V
3
5
VUS
Undershoot
-0.300
N/A
N/A
V
3
5
Differential Output Swing
0.300
N/A
N/A
V
5
6
Input Leakage Current
-5
N/A
5
μA
Pad Capacitance
.95
1.2
1.45
pF
ILI
8.
Unit
Overshoot
Cpad
6.
7.
Max
Range of Crossing Points
VSWING
3.
4.
5.
Typ
VOS
ΔVCROSS
1.
2.
Absolute Crossing Point
Min
8
Unless otherwise noted, all specifications in this table apply to all processor frequencies.
Crossing voltage is defined as the instantaneous voltage value when the rising edge of
BCLK0 equals the falling edge of BCLK1.
VHavg is the statistical average of the VH measured by the oscilloscope.
"Steady state" voltage, not including overshoot or undershoot.
Overshoot is defined as the absolute value of the maximum voltage. Undershoot is defined
as the absolute value of the minimum voltage.
Measurement taken from differential waveform.
The crossing point must meet the absolute and relative crossing point specifications
simultaneously.
Cpad includes die capacitance only. No package parasitics are included.
Differential Clock Waveform
CLK 0
VCROSS
Median + 75 mV
VCROSS
median
VCROSS
VCROSS Max
500 mV
VCROSS
VCROSS Min
300 mV
Median - 75 mV
CLK 1
High Time
median
Low Time
Period
30
Datasheet
Electrical Specifications
Figure 4.
Differential Clock Crosspoint Specification
650
Crossing Point (mV)
600
550
550 mV
500
450
550 + 0.5 (VHavg - 700)
400
250 + 0.5 (VHavg - 700)
350
300
250
250 mV
200
660 670 680 690 700 710 720 730 740 750 760 770 780 790 800 810 820 830 840 850
VHavg (mV)
Figure 5.
Differential Measurements
Slew_ris e
Slew _fall
+150 mV
0.0 V
-150 mV
+150 mV
V_swing
0.0V
- 150 mV
D iff
Datasheet
31
Electrical Specifications
2.8.5
BCLK[1:0] Specifications (CK410 based Platforms)
Table 18.
Front Side Bus Differential BCLK Specifications
Symbol
Parameter
Min
Typ
Max
Unit
Figure
Notes1
VL
Input Low Voltage
-0.150
0.00
0
N/A
V
3
-
VH
Input High Voltage
0.660
0.70
0
0.850
V
3
-
VCROSS(abs)
Absolute Crossing
Point
0.250
N/A
0.550
V
3, 4
2, 8
VCROSS(rel)
Relative Crossing Point
0.250 +
0.5(VHavg – 0.700)
N/A
0.550 +
0.5(VHavg – 0.700)
V
3, 4
3, 8, 9
Range of Crossing
Points
N/A
N/A
0.140
V
3, 4
-
VOS
Overshoot
N/A
N/A
VH + 0.3
V
3
4
VUS
ΔVCROSS
Undershoot
-0.300
N/A
N/A
V
3
5
VRBM
Ringback Margin
0.200
N/A
N/A
V
3
6
VTM
Threshold Region
VCROSS – 0.100
N/A
VCROSS + 0.100
V
3
7
NOTES:
1.
Unless otherwise noted, all specifications in this table apply to all processor frequencies.
2.
Crossing voltage is defined as the instantaneous voltage value when the rising edge of
BCLK0 equals the falling edge of BCLK1.
3.
VHavg is the statistical average of the VH measured by the oscilloscope.
4.
Overshoot is defined as the absolute value of the maximum voltage.
5.
Undershoot is defined as the absolute value of the minimum voltage.
6.
Ringback Margin is defined as the absolute voltage difference between the maximum
Rising Edge Ringback and the maximum Falling Edge Ringback.
7.
Threshold Region is defined as a region entered around the crossing point voltage in which
the differential receiver switches. It includes input threshold hysteresis.
8.
The crossing point must meet the absolute and relative crossing point specifications
simultaneously.
9.
VHavg can be measured directly using “Vtop” on Agilent* oscilloscopes and “High” on
Tektronix* oscilloscopes.
32
Datasheet
Electrical Specifications
Figure 6.
Differential Clock Waveform
Tph
Overshoot
BCLK1
VH
Rising Edge
Ringback
V CROSS (ABS)
Threshold
Region
V CROSS (ABS)
Ringback
Margin
Falling Edge
Ringback
BCLK0
VL
Undershoot
Tpl
Tp
Tp = T1: BCLK[1:0] period
T2: BCLK[1:0] period stability (not shown)
Tph = T3: BCLK[1:0] pulse high time
Tpl = T4: BCLK[1:0] pulse low time
T5: BCLK[1:0] rise time through the threshold region
T6: BCLK[1:0] fall time through the threshold region
Figure 7.
Differential Clock Crosspoint Specification
650
Crossing Point (mV)
600
550
550 mV
500
450
550 + 0.5 (VHavg - 700)
400
250 + 0.5 (VHavg - 700)
350
300
250
250 mV
200
660 670 680 690 700 710 720 730 740 750 760 770 780 790 800 810 820 830 840 850
VHavg (mV)
Datasheet
33
Electrical Specifications
2.9
PECI DC Specifications
PECI is an Intel proprietary one-wire interface that provides a communication channel
between Intel processors (may also include chipset components in the future) and
external thermal monitoring devices. The processor contains Digital Thermal Sensors
(DTS) distributed throughout die. These sensors are implemented as analog-to-digital
converters calibrated at the factory for reasonable accuracy to provide a digital
representation of relative processor temperature. PECI provides an interface to relay
the highest DTS temperature within a die to external management devices for thermal/
fan speed control. More detailed information is available in the Platform Environment
Control Interface (PECI) Specification.
Table 19.
PECI DC Electrical Limits
Symbol
Vin
Vhysteresis
Definition and Conditions
Input Voltage Range
Hysteresis
Min
Max
Units
-0.15
VTT+ 0.15
V
0.1 * VTT
—
V
Notes
3
Vn
Negative-edge threshold voltage
0.275 * VTT
0.500 * VTT
V
Vp
Positive-edge threshold voltage
0.550 * VTT
0.725 * VTT
V
-6.0
N/A
mA
(VOL = 0.25 * VTT)
0.5
1.0
mA
Ileak+
High impedance state leakage to VTT
N/A
50
µA
2
Ileak-
High impedance leakage to GND
N/A
10
µA
2
Cbus
Bus capacitance per node
—
10
pF
4
Vnoise
Signal noise immunity above 300 MHz
0.1 * VTT
—
Vp-p
Isource
Isink
High level output source
(VOH = 0.75 * VTT)
Low level output sink
NOTE:
1.
VTT supplies the PECI interface. PECI behavior does not affect VTT min/max specifications.
2.
The leakage specification applies to powered devices on the PECI bus.
3.
The input buffers use a Schmitt-triggered input design for improved noise immunity.
4.
One node is counted for each client and one node for the system host. Extended trace
lengths might appear as additional nodes.
§
34
Datasheet
Package Mechanical Specifications
3
Package Mechanical
Specifications
The processor is packaged in a Flip-Chip Land Grid Array (FC-LGA6) package that
interfaces with the motherboard via an LGA775 socket. The package consists of a
processor core mounted on a substrate land-carrier. An integrated heat spreader (IHS)
is attached to the package substrate and core and serves as the mating surface for
processor component thermal solutions, such as a heatsink. Figure 8 shows a sketch of
the processor package components and how they are assembled together. Refer to the
LGA775 Socket Mechanical Design Guide for complete details on the LGA775 socket.
The package components shown in Figure 8 include the following:
•
•
•
•
•
Figure 8.
Integrated Heat Spreader (IHS)
Thermal Interface Material (TIM)
Processor core (die)
Package substrate
Capacitors
Processor Package Assembly Sketch
Core (die)
TIM
IHS
Substrate
Capacitors
LGA775 Socket
System Board
NOTE:
1.
Socket and motherboard are included for reference and are not part of processor package.
3.1
Package Mechanical Drawing
The package mechanical drawings are shown in Figure 9 and Figure 10. The drawings
include dimensions necessary to design a thermal solution for the processor. These
dimensions include:
• Package reference with tolerances (total height, length, width, etc.)
• IHS parallelism and tilt
• Land dimensions
• Top-side and back-side component keep-out dimensions
• Reference datums
• All drawing dimensions are in mm [in].
• Guidelines on potential IHS flatness variation with socket load plate actuation and
installation of the cooling solution is available in the processor Thermal and
Mechanical Design Guidelines.
Datasheet
35
Package Mechanical Specifications
Figure 9.
36
Processor Package Drawing Sheet 1 of 3
Datasheet
Package Mechanical Specifications
Figure 10.
Datasheet
Processor Package Drawing Sheet 2 of 3
37
Package Mechanical Specifications
Figure 11.
38
Processor Package Drawing Sheet 3 of 3
Datasheet
Package Mechanical Specifications
3.2
Processor Component Keep-Out Zones
The processor may contain components on the substrate that define component keepout zone requirements. A thermal and mechanical solution design must not intrude into
the required keep-out zones. Decoupling capacitors are typically mounted to either the
topside or land-side of the package substrate. See Figure 9 and Figure 10 for keep-out
zones. The location and quantity of package capacitors may change due to
manufacturing efficiencies but will remain within the component keep-in.
3.3
Package Loading Specifications
Table 20 provides dynamic and static load specifications for the processor package.
These mechanical maximum load limits should not be exceeded during heatsink
assembly, shipping conditions, or standard use condition. Also, any mechanical system
or component testing should not exceed the maximum limits. The processor package
substrate should not be used as a mechanical reference or load-bearing surface for
thermal and mechanical solution. The minimum loading specification must be
maintained by any thermal and mechanical solutions.
.
Table 20.
Processor Loading Specifications
Parameter
Minimum
Maximum
Notes
Static
80 N [17 lbf]
311 N [70 lbf]
1, 2, 3
Dynamic
-
756 N [170 lbf]
1, 3, 4
NOTES:
1.
These specifications apply to uniform compressive loading in a direction normal to the
processor IHS.
2.
This is the maximum force that can be applied by a heatsink retention clip. The clip must
also provide the minimum specified load on the processor package.
3.
These specifications are based on limited testing for design characterization. Loading limits
are for the package only and do not include the limits of the processor socket.
4.
Dynamic loading is defined as an 11 ms duration average load superimposed on the static
load requirement.
3.4
Package Handling Guidelines
Table 21 includes a list of guidelines on package handling in terms of recommended
maximum loading on the processor IHS relative to a fixed substrate. These package
handling loads may be experienced during heatsink removal.
Table 21.
Package Handling Guidelines
Parameter
Maximum Recommended
Notes
Shear
311 N [70 lbf]
1, 4
Tensile
111 N [25 lbf]
2, 4
Torque
3.95 N-m [35 lbf-in]
3, 4
NOTES:
1.
A shear load is defined as a load applied to the IHS in a direction parallel to the IHS top
surface.
2.
A tensile load is defined as a pulling load applied to the IHS in a direction normal to the
IHS surface.
3.
A torque load is defined as a twisting load applied to the IHS in an axis of rotation normal
to the IHS top surface.
4.
These guidelines are based on limited testing for design characterization.
Datasheet
39
Package Mechanical Specifications
3.5
Package Insertion Specifications
The processor can be inserted into and removed from a LGA775 socket 15 times. The
socket should meet the LGA775 requirements detailed in the LGA775 Socket
Mechanical Design Guide.
3.6
Processor Mass Specification
The typical mass of the processor is 21.5 g [0.76 oz]. This mass [weight] includes all
the components that are included in the package.
3.7
Processor Materials
Table 22 lists some of the package components and associated materials.
Table 22.
Processor Materials
Component
3.8
Material
Integrated Heat Spreader (IHS)
Nickel Plated Copper
Substrate
Fiber Reinforced Resin
Substrate Lands
Gold Plated Copper
Processor Markings
Figure 12 shows the topside markings on the processor. This diagram is to aid in the
identification of the processor.
Figure 12.
Processor Top-Side Marking Example
INTEL M ©'06 440
CELERON®
SLxxx [COO]
2.00GHZ/512/800/06
[ F P O ] e4
ATPO
S/N
40
Datasheet
Package Mechanical Specifications
3.9
Processor Land Coordinates
Figure 13 shows the top view of the processor land coordinates. The coordinates are
referred to throughout the document to identify processor lands.
.
Figure 13.
Processor Land Coordinates and Quadrants, Top View
VCC / VSS
30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1
AN
AM
AL
AK
AJ
AH
AG
AF
AE
AD
AC
AB
AA
Y
W
V
U
T
R
P
N
M
L
K
J
H
G
F
E
D
C
B
A
AN
AM
AL
AK
AJ
AH
AG
AF
AE
AD
AC
AB
AA
Y
W
V
U
T
R
P
N
M
L
K
J
H
G
F
E
D
C
B
A
Preliminary
Socket 775
Quadrants
Top View
Address/
Common Clock/
Async
30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1
VTT / Clocks
Data
§
Datasheet
41
Package Mechanical Specifications
42
Datasheet
Land Listing and Signal Descriptions
4
Land Listing and Signal
Descriptions
This chapter provides the processor land assignment and signal descriptions.
4.1
Processor Land Assignments
This section contains the land listings for the processor. The land-out footprint is shown
in Figure 14 and Figure 15. These figures represent the land-out arranged by land
number and they show the physical location of each signal on the package land array
(top view). Table 23 is a listing of all processor lands ordered alphabetically by land
(signal) name. Table 24 is also a listing of all processor lands; the ordering is by land
number.
Datasheet
43
Land Listing and Signal Descriptions
Figure 14.
land-out Diagram (Top View – Left Side)
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
VCC
VCC
VSS
VSS
VCC
VCC
VSS
VSS
VCC
VCC
VSS
VCC
VCC
VSS
VSS
VCC
AM
VCC
VCC
VSS
VSS
VCC
VCC
VSS
VSS
VCC
VCC
VSS
VCC
VCC
VSS
VSS
VCC
AN
AL
VCC
VCC
VSS
VSS
VCC
VCC
VSS
VSS
VCC
VCC
VSS
VCC
VCC
VSS
VSS
VCC
AK
VSS
VSS
VSS
VSS
VCC
VCC
VSS
VSS
VCC
VCC
VSS
VCC
VCC
VSS
VSS
VCC
AJ
VSS
VSS
VSS
VSS
VCC
VCC
VSS
VSS
VCC
VCC
VSS
VCC
VCC
VSS
VSS
VCC
AH
VCC
VCC
VCC
VCC
VCC
VCC
VSS
VSS
VCC
VCC
VSS
VCC
VCC
VSS
VSS
VCC
AG
VCC
VCC
VCC
VCC
VCC
VCC
VSS
VSS
VCC
VCC
VSS
VCC
VCC
VSS
VSS
VCC
AF
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VCC
VCC
VSS
VCC
VCC
VSS
VSS
VCC
AE
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VCC
VCC
VCC
VSS
VCC
VCC
VSS
VSS
VCC
AD
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
AC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
AB
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
AA
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
Y
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
W
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
V
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
U
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
T
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
R
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
P
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
N
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
M
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
L
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
K
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
FC34
FC31
VCC
BSEL1
FC15
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
FC33
FC32
D44# DSTBN2# DSTBP2#
D35#
D36#
D32#
D31#
VSS
D38#
D37#
VSS
D30#
J
H
G
BSEL2
F
E
VTT
D
BSEL0
TESTHI TESTHI TESTHI
BCLK1 TESTHI4
RESET# D47#
5
3
6
RSVD
BCLK0 VTT_SEL
TESTHI TESTHI TESTHI
0
2
7
RSVD
VSS
D43#
RSVD
D45#
D42#
VSS
D40#
D39#
VSS
D34#
D33#
VSS
D48#
DBI2#
VSS
D49#
RSVD
VSS
DBI3#
VSS
D54#
DSTBP3#
VSS
D51#
FC26
VSS
VSS
VSS
VSS
FC10
VTT
VTT
VTT
VTT
VTT
VSS
VCCPLL D46#
VSS
VCCIO
PLL
VSS
D58#
D41#
C
VTT
VTT
VTT
VTT
VTT
VTT
B
VTT
VTT
VTT
VTT
VTT
VTT
VSS
VSSA
D63#
D59#
VSS
D60#
D57#
VSS
D55#
D53#
A
VTT
VTT
VTT
VTT
VTT
VTT
FC23
VCCA
D62#
VSS
RSVD
D61#
VSS
D56#
DSTBN3#
VSS
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
44
Datasheet
Land Listing and Signal Descriptions
Figure 15.
14
13
land-out Diagram (Top View – Right Side)
12
11
10
9
8
7
6
5
VID_SEL VSS_MB_
VCC_MB_
ECT
REGULATION REGULATION
4
3
2
1
VSS_
SENSE
VCC_
SENSE
VSS
VSS
AN
VID2
VID0
VSS
AM
VCC
VSS
VCC
VCC
VSS
VCC
VCC
VCC
VSS
VCC
VCC
VSS
VCC
VCC
VID7
FC40
VID6
VSS
VCC
VSS
VCC
VCC
VSS
VCC
VCC
VSS
VID3
VID1
VID5
VCC
VSS
VCC
VCC
VSS
VCC
VCC
VSS
FC8
VSS
VID4
ITP_CLK0
VSS
THERMDC
AK
VCC
VSS
VCC
VCC
VSS
VCC
VCC
VSS
A35#
A34#
VSS
ITP_CLK1
BPM0#
BPM1#
AJ
VCC
VSS
VCC
VCC
VSS
VCC
VCC
VSS
VSS
A33#
A32#
VSS
RSVD
VSS
AH
VCC
VSS
VCC
VCC
VSS
VCC
VCC
VSS
A29#
A31#
A30#
BPM5#
BPM3#
TRST#
AG
VCC
VSS
VCC
VCC
VSS
VCC
VCC
VSS
VSS
A27#
A28#
VSS
BPM4#
TDO
AF
VCC
VSS
VCC
VCC
VSS
VCC
SKTOCC#
VSS
RSVD
VSS
RSVD
FC18
VSS
TCK
AE
VCC
VSS
A22#
ADSTB1#
VSS
FC36
BPM2#
TDI
AD
VCC
VSS
VSS
A25#
RSVD
VSS
DBR#
TMS
AC
VCC
VSS
A17#
A24#
A26#
FC37
IERR#
VSS
AB
AA
VRDSEL PROCHOT# THERMDA
AL
VCC
VSS
VSS
A23#
A21#
VSS
FC39
VTT_OUT_
RIGHT
VCC
VSS
A19#
VSS
A20#
FC17
VSS
FC0
Y
VCC
VSS
A18#
A16#
VSS
TESTHI1
TESTHI12
MSID0
W
VCC
VSS
VSS
A14#
A15#
VSS
RSVD
MSID1
V
VCC
VSS
A10#
A12#
A13#
FC30
FC29
FC28
U
VCC
VSS
VSS
A9#
A11#
VSS
FC4
COMP1
T
A8#
FERR#/
PBE#
VSS
COMP3
R
VCC
VSS
ADSTB0#
VSS
VCC
VSS
A4#
RSVD
VSS
INIT#
SMI#
TESTHI11
P
VCC
VSS
VSS
RSVD
RSVD
VSS
IGNNE#
PWRGOOD
N
VCC
VSS
REQ2#
A5#
A7#
STPCLK#
THERMTRIP
#
VSS
M
VCC
VSS
VSS
A3#
A6#
VSS
TESTHI13
LINT1
L
VCC
VSS
REQ3#
VSS
REQ0#
A20M#
VSS
LINT0
K
J
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VSS
REQ4#
REQ1#
VSS
FC22
FC3
VTT_OUT_
LEFT
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
TESTHI10
FC35
VSS
GTLREF1
GTLREF0
D29#
D27#
FC38
D16#
BPRI#
DEFER#
RSVD
PECI
COMP2
FC27
D28#
VSS
D24#
D23#
VSS
D18#
D17#
VSS
FC21
RS1#
VSS
BR0#
FC5
F
VSS
D26#
DSTBP1#
VSS
D21#
D19#
VSS
RSVD
RSVD
FC20
HITM#
TRDY#
VSS
E
RSVD
D25#
VSS
D15#
D22#
VSS
D12#
D20#
VSS
VSS
HIT#
VSS
ADS#
RSVD
D52#
VSS
D14#
D11#
VSS
RSVD
DSTBN0#
VSS
D3#
D1#
VSS
LOCK#
BNR#
DRDY#
VSS
DSTBN1# DBI1#
VSS
COMP8
D13#
VSS
VSS
D6#
D5#
VSS
D0#
RS0#
DBSY#
D50#
COMP0
VSS
D9#
D8#
VSS
DBI0#
D7#
VSS
D4#
D2#
RS2#
VSS
14
13
12
11
10
9
8
7
6
5
4
3
2
Datasheet
D10# DSTBP0#
TESTHI9 TESTHI8
H
G
D
C
B
A
1
45
Land Listing and Signal Descriptions
Table 23.
46
Alphabetical Land
Assignments
Table 23.
Alphabetical Land
Assignments
Land Name
Land
#
Signal Buffer
Type
Direction
Land Name
Land
#
Signal Buffer
Type
A3#
L5
Source Synch
Input/Output
BPM0#
AJ2
A4#
P6
Source Synch
Input/Output
BPM1#
AJ1
Common Clock Input/Output
A5#
M5
Source Synch
Input/Output
BPM2#
AD2
Common Clock Input/Output
Direction
Common Clock Input/Output
A6#
L4
Source Synch
Input/Output
BPM3#
AG2
Common Clock Input/Output
A7#
M4
Source Synch
Input/Output
BPM4#
AF2
Common Clock Input/Output
A8#
R4
Source Synch
Input/Output
BPM5#
AG3
Common Clock Input/Output
A9#
T5
Source Synch
Input/Output
BPRI#
G8
Common Clock
A10#
U6
Source Synch
Input/Output
BR0#
F3
Common Clock Input/Output
A11#
T4
Source Synch
Input/Output
BSEL0
G29
Power/Other
Output
A12#
U5
Source Synch
Input/Output
BSEL1
H30
Power/Other
Output
A13#
U4
Source Synch
Input/Output
BSEL2
G30
Power/Other
Output
A14#
V5
Source Synch
Input/Output
COMP0
A13
Power/Other
Input
A15#
V4
Source Synch
Input/Output
COMP1
T1
Power/Other
Input
Input
A16#
W5
Source Synch
Input/Output
COMP2
G2
Power/Other
Input
A17#
AB6
Source Synch
Input/Output
COMP3
R1
Power/Other
Input
A18#
W6
Source Synch
Input/Output
COMP8
B13
Power/Other
Input
A19#
Y6
Source Synch
Input/Output
D0#
B4
Source Synch
Input/Output
A20#
Y4
Source Synch
Input/Output
D1#
C5
Source Synch
Input/Output
A21#
AA4
Source Synch
Input/Output
D2#
A4
Source Synch
Input/Output
A22#
AD6
Source Synch
Input/Output
D3#
C6
Source Synch
Input/Output
A23#
AA5
Source Synch
Input/Output
D4#
A5
Source Synch
Input/Output
A24#
AB5
Source Synch
Input/Output
D5#
B6
Source Synch
Input/Output
A25#
AC5
Source Synch
Input/Output
D6#
B7
Source Synch
Input/Output
A26#
AB4
Source Synch
Input/Output
D7#
A7
Source Synch
Input/Output
A27#
AF5
Source Synch
Input/Output
D8#
A10
Source Synch
Input/Output
A28#
AF4
Source Synch
Input/Output
D9#
A11
Source Synch
Input/Output
A29#
AG6
Source Synch
Input/Output
D10#
B10
Source Synch
Input/Output
A30#
AG4
Source Synch
Input/Output
D11#
C11
Source Synch
Input/Output
A31#
AG5
Source Synch
Input/Output
D12#
D8
Source Synch
Input/Output
A32#
AH4
Source Synch
Input/Output
D13#
B12
Source Synch
Input/Output
A33#
AH5
Source Synch
Input/Output
D14#
C12
Source Synch
Input/Output
A34#
AJ5
Source Synch
Input/Output
D15#
D11
Source Synch
Input/Output
A35#
AJ6
Source Synch
Input/Output
D16#
G9
Source Synch
Input/Output
ADS#
D2
Common Clock Input/Output
D17#
F8
Source Synch
Input/Output
A20M#
K3
Asynch GTL+
Input
D18#
F9
Source Synch
Input/Output
ADSTB0#
R6
Source Synch
Input/Output
D19#
E9
Source Synch
Input/Output
ADSTB1#
AD5
Source Synch
Input/Output
D20#
D7
Source Synch
Input/Output
BCLK0
F28
Clock
Input
D21#
E10
Source Synch
Input/Output
BCLK1
G28
Clock
Input
D22#
D10
Source Synch
Input/Output
BNR#
C2
D23#
F11
Source Synch
Input/Output
Common Clock Input/Output
Datasheet
Land Listing and Signal Descriptions
Table 23.
Datasheet
Alphabetical Land
Assignments
Table 23.
Alphabetical Land
Assignments
Land Name
Land
#
Signal Buffer
Type
Direction
Land Name
Land
#
Signal Buffer
Type
Direction
D24#
F12
Source Synch
Input/Output
DBI0#
A8
Source Synch
Input/Output
D25#
D13
Source Synch
Input/Output
DBI1#
G11
Source Synch
Input/Output
D26#
E13
Source Synch
Input/Output
DBI2#
D19
Source Synch
Input/Output
D27#
G13
Source Synch
Input/Output
DBI3#
C20
Source Synch
Input/Output
D28#
F14
Source Synch
Input/Output
DBR#
AC2
Power/Other
Output
D29#
G14
Source Synch
Input/Output
DBSY#
B2
Common Clock Input/Output
D30#
F15
Source Synch
Input/Output
DEFER#
G7
Common Clock
D31#
G15
Source Synch
Input/Output
DRDY#
C1
Common Clock Input/Output
D32#
G16
Source Synch
Input/Output
DSTBN0#
C8
Source Synch
Input/Output
D33#
E15
Source Synch
Input/Output
DSTBN1#
G12
Source Synch
Input/Output
D34#
E16
Source Synch
Input/Output
DSTBN2#
G20
Source Synch
Input/Output
D35#
G18
Source Synch
Input/Output
DSTBN3#
A16
Source Synch
Input/Output
D36#
G17
Source Synch
Input/Output
DSTBP0#
B9
Source Synch
Input/Output
D37#
F17
Source Synch
Input/Output
DSTBP1#
E12
Source Synch
Input/Output
D38#
F18
Source Synch
Input/Output
DSTBP2#
G19
Source Synch
Input/Output
D39#
E18
Source Synch
Input/Output
DSTBP3#
C17
Source Synch
Input/Output
D40#
E19
Source Synch
Input/Output
FC0
Y1
Power/Other
D41#
F20
Source Synch
Input/Output
FC3
J2
Power/Other
D42#
E21
Source Synch
Input/Output
FC4
T2
Power/Other
D43#
F21
Source Synch
Input/Output
FC5
F2
Power/Other
D44#
G21
Source Synch
Input/Output
FC8
AK6
Power/Other
D45#
E22
Source Synch
Input/Output
FC10
E24
Power/Other
D46#
D22
Source Synch
Input/Output
FC15
H29
Power/Other
D47#
G22
Source Synch
Input/Output
FC17
Y3
Power/Other
D48#
D20
Source Synch
Input/Output
FC18
AE3
Power/Other
D49#
D17
Source Synch
Input/Output
FC20
E5
Power/Other
D50#
A14
Source Synch
Input/Output
FC21
F6
Power/Other
D51#
C15
Source Synch
Input/Output
FC22
J3
Power/Other
D52#
C14
Source Synch
Input/Output
FC23
A24
Power/Other
D53#
B15
Source Synch
Input/Output
FC26
E29
Power/Other
D54#
C18
Source Synch
Input/Output
FC27
G1
Power/Other
D55#
B16
Source Synch
Input/Output
FC28
U1
Power/Other
D56#
A17
Source Synch
Input/Output
FC29
U2
Power/Other
D57#
B18
Source Synch
Input/Output
FC30
U3
Power/Other
D58#
C21
Source Synch
Input/Output
FC31
J16
Power/Other
D59#
B21
Source Synch
Input/Output
FC32
H15
Power/Other
D60#
B19
Source Synch
Input/Output
FC33
H16
Power/Other
D61#
A19
Source Synch
Input/Output
FC34
J17
Power/Other
D62#
A22
Source Synch
Input/Output
FC35
H4
Power/Other
D63#
B22
Source Synch
Input/Output
FC36
AD3
Power/Other
Input
47
Land Listing and Signal Descriptions
Table 23.
48
Alphabetical Land
Assignments
Land Name
Land
#
Signal Buffer
Type
FC37
AB3
FC38
FC39
Table 23.
Alphabetical Land
Assignments
Land Name
Land
#
Power/Other
RESERVED
F29
G10
Power/Other
RESERVED
G6
AA2
Power/Other
RESERVED
N4
Direction
Signal Buffer
Type
Direction
FC40
AM6
Power/Other
RESERVED
N5
FERR#/PBE#
R3
Asynch GTL+
Output
RESERVED
P5
GTLREF0
H1
Power/Other
Input
RESERVED
V2
GTLREF1
H2
Power/Other
Input
RESET#
G23
Common Clock
Input
HIT#
D4
Common Clock Input/Output
RS0#
B3
Common Clock
Input
HITM#
E4
Common Clock Input/Output
RS1#
F5
Common Clock
Input
IERR#
AB2
Asynch GTL+
Output
RS2#
A3
Common Clock
Input
IGNNE#
N2
Asynch GTL+
Input
SKTOCC#
AE8
Power/Other
INIT#
P3
Asynch GTL+
Input
SMI#
P2
Asynch GTL+
Input
ITP_CLK0
AK3
TAP
Input
STPCLK#
M3
Asynch GTL+
Input
ITP_CLK1
AJ3
TAP
Input
TCK
AE1
TAP
Input
LINT0
K1
Asynch GTL+
Input
TDI
AD1
TAP
Input
Asynch GTL+
Input
LINT1
L1
LOCK#
C3
MSID0
W1
Power/Other
MSID1
V1
Power/Other
TDO
AF1
TAP
Output
TESTHI0
F26
Power/Other
Input
Output
TESTHI1
W3
Power/Other
Input
Output
TESTHI10
H5
Power/Other
Input
TESTHI11
P1
Power/Other
Input
TESTHI12/
FC44
W2
Power/Other
Input
TESTHI13
L2
Asynch GTL+
Input
TESTHI2
F25
Power/Other
Input
TESTHI3
G25
Power/Other
Input
TESTHI4
G27
Power/Other
Input
TESTHI5
G26
Power/Other
Input
TESTHI6
G24
Power/Other
Input
Common Clock Input/Output
PECI
G5
Power/Other
PROCHOT#
AL2
Asynch GTL+
Input/Output
PWRGOOD
N1
Power/Other
Input
REQ0#
K4
Source Synch
Input/Output
REQ1#
J5
Source Synch
Input/Output
REQ2#
M6
Source Synch
Input/Output
REQ3#
K6
Source Synch
Input/Output
REQ4#
J6
Source Synch
Input/Output
RESERVED
A20
RESERVED
AC4
RESERVED
AE4
RESERVED
AE6
RESERVED
AH2
RESERVED
C9
RESERVED
D1
RESERVED
D14
RESERVED
D16
RESERVED
E23
RESERVED
E6
RESERVED
E7
RESERVED
F23
TESTHI7
F24
Power/Other
Input
TESTHI8/
FC42
G3
Power/Other
Input
TESTHI9/
FC43
G4
Power/Other
Input
THERMDC
AK1
Power/Other
THERMDA
AL1
Power/Other
THERMTRIP#
M2
Asynch GTL+
Output
TMS
AC1
TAP
Input
TRDY#
E3
Common Clock
Input
TRST#
AG1
TAP
Input
VCC
AA8
Power/Other
VCC
AB8
Power/Other
VCC
AC23
Power/Other
Datasheet
Land Listing and Signal Descriptions
Table 23.
Datasheet
Alphabetical Land
Assignments
Land Name
Land
#
Signal Buffer
Type
VCC
AC24
VCC
VCC
Table 23.
Alphabetical Land
Assignments
Land Name
Land
#
Signal Buffer
Type
Power/Other
VCC
AG15
Power/Other
AC25
Power/Other
VCC
AG18
Power/Other
AC26
Power/Other
VCC
AG19
Power/Other
VCC
AC27
Power/Other
VCC
AG21
Power/Other
VCC
AC28
Power/Other
VCC
AG22
Power/Other
VCC
AC29
Power/Other
VCC
AG25
Power/Other
VCC
AC30
Power/Other
VCC
AG26
Power/Other
VCC
AC8
Power/Other
VCC
AG27
Power/Other
VCC
AD23
Power/Other
VCC
AG28
Power/Other
VCC
AD24
Power/Other
VCC
AG29
Power/Other
VCC
AD25
Power/Other
VCC
AG30
Power/Other
VCC
AD26
Power/Other
VCC
AG8
Power/Other
VCC
AD27
Power/Other
VCC
AG9
Power/Other
VCC
AD28
Power/Other
VCC
AH11
Power/Other
VCC
AD29
Power/Other
VCC
AH12
Power/Other
VCC
AD30
Power/Other
VCC
AH14
Power/Other
VCC
AD8
Power/Other
VCC
AH15
Power/Other
VCC
AE11
Power/Other
VCC
AH18
Power/Other
VCC
AE12
Power/Other
VCC
AH19
Power/Other
VCC
AE14
Power/Other
VCC
AH21
Power/Other
VCC
AE15
Power/Other
VCC
AH22
Power/Other
VCC
AE18
Power/Other
VCC
AH25
Power/Other
VCC
AE19
Power/Other
VCC
AH26
Power/Other
VCC
AE21
Power/Other
VCC
AH27
Power/Other
VCC
AE22
Power/Other
VCC
AH28
Power/Other
VCC
AE23
Power/Other
VCC
AH29
Power/Other
VCC
AE9
Power/Other
VCC
AH30
Power/Other
VCC
AF11
Power/Other
VCC
AH8
Power/Other
VCC
AF12
Power/Other
VCC
AH9
Power/Other
VCC
AF14
Power/Other
VCC
AJ11
Power/Other
VCC
AF15
Power/Other
VCC
AJ12
Power/Other
VCC
AF18
Power/Other
VCC
AJ14
Power/Other
VCC
AF19
Power/Other
VCC
AJ15
Power/Other
VCC
AF21
Power/Other
VCC
AJ18
Power/Other
VCC
AF22
Power/Other
VCC
AJ19
Power/Other
VCC
AF8
Power/Other
VCC
AJ21
Power/Other
VCC
AF9
Power/Other
VCC
AJ22
Power/Other
VCC
AG11
Power/Other
VCC
AJ25
Power/Other
VCC
AG12
Power/Other
VCC
AJ26
Power/Other
VCC
AG14
Power/Other
VCC
AJ8
Power/Other
Direction
Direction
49
Land Listing and Signal Descriptions
Table 23.
50
Alphabetical Land
Assignments
Land Name
Land
#
Signal Buffer
Type
VCC
AJ9
VCC
VCC
Table 23.
Alphabetical Land
Assignments
Land Name
Land
#
Signal Buffer
Type
Power/Other
VCC
AM9
Power/Other
AK11
Power/Other
VCC
AN11
Power/Other
AK12
Power/Other
VCC
AN12
Power/Other
VCC
AK14
Power/Other
VCC
AN14
Power/Other
VCC
AK15
Power/Other
VCC
AN15
Power/Other
VCC
AK18
Power/Other
VCC
AN18
Power/Other
VCC
AK19
Power/Other
VCC
AN19
Power/Other
VCC
AK21
Power/Other
VCC
AN21
Power/Other
VCC
AK22
Power/Other
VCC
AN22
Power/Other
VCC
AK25
Power/Other
VCC
AN25
Power/Other
VCC
AK26
Power/Other
VCC
AN26
Power/Other
VCC
AK8
Power/Other
VCC
AN29
Power/Other
VCC
AK9
Power/Other
VCC
AN30
Power/Other
VCC
AL11
Power/Other
VCC
AN8
Power/Other
VCC
AL12
Power/Other
VCC
AN9
Power/Other
VCC
AL14
Power/Other
VCC
J10
Power/Other
VCC
AL15
Power/Other
VCC
J11
Power/Other
VCC
AL18
Power/Other
VCC
J12
Power/Other
VCC
AL19
Power/Other
VCC
J13
Power/Other
VCC
AL21
Power/Other
VCC
J14
Power/Other
VCC
AL22
Power/Other
VCC
J15
Power/Other
VCC
AL25
Power/Other
VCC
J18
Power/Other
VCC
AL26
Power/Other
VCC
J19
Power/Other
VCC
AL29
Power/Other
VCC
J20
Power/Other
VCC
AL30
Power/Other
VCC
J21
Power/Other
VCC
AL8
Power/Other
VCC
J22
Power/Other
VCC
AL9
Power/Other
VCC
J23
Power/Other
VCC
AM11
Power/Other
VCC
J24
Power/Other
VCC
AM12
Power/Other
VCC
J25
Power/Other
VCC
AM14
Power/Other
VCC
J26
Power/Other
VCC
AM15
Power/Other
VCC
J27
Power/Other
VCC
AM18
Power/Other
VCC
J28
Power/Other
VCC
AM19
Power/Other
VCC
J29
Power/Other
VCC
AM21
Power/Other
VCC
J30
Power/Other
VCC
AM22
Power/Other
VCC
J8
Power/Other
VCC
AM25
Power/Other
VCC
J9
Power/Other
VCC
AM26
Power/Other
VCC
K23
Power/Other
VCC
AM29
Power/Other
VCC
K24
Power/Other
VCC
AM30
Power/Other
VCC
K25
Power/Other
VCC
AM8
Power/Other
VCC
K26
Power/Other
Direction
Direction
Datasheet
Land Listing and Signal Descriptions
Table 23.
Datasheet
Alphabetical Land
Assignments
Land Name
Land
#
Signal Buffer
Type
VCC
K27
VCC
VCC
Table 23.
Alphabetical Land
Assignments
Land Name
Land
#
Signal Buffer
Type
Power/Other
VCC
U28
Power/Other
K28
Power/Other
VCC
U29
Power/Other
K29
Power/Other
VCC
U30
Power/Other
VCC
K30
Power/Other
VCC
U8
Power/Other
VCC
K8
Power/Other
VCC
V8
Power/Other
Direction
Direction
VCC
L8
Power/Other
VCC
W23
Power/Other
VCC
M23
Power/Other
VCC
W24
Power/Other
VCC
M24
Power/Other
VCC
W25
Power/Other
VCC
M25
Power/Other
VCC
W26
Power/Other
VCC
M26
Power/Other
VCC
W27
Power/Other
VCC
M27
Power/Other
VCC
W28
Power/Other
VCC
M28
Power/Other
VCC
W29
Power/Other
VCC
M29
Power/Other
VCC
W30
Power/Other
VCC
M30
Power/Other
VCC
W8
Power/Other
VCC
M8
Power/Other
VCC
Y23
Power/Other
VCC
N23
Power/Other
VCC
Y24
Power/Other
VCC
N24
Power/Other
VCC
Y25
Power/Other
VCC
N25
Power/Other
VCC
Y26
Power/Other
VCC
N26
Power/Other
VCC
Y27
Power/Other
VCC
N27
Power/Other
VCC
Y28
Power/Other
VCC
N28
Power/Other
VCC
Y29
Power/Other
VCC
N29
Power/Other
VCC
Y30
Power/Other
VCC
N30
Power/Other
VCC
Y8
Power/Other
VCC
N8
Power/Other
Power/Other
Output
P8
Power/Other
VCC_MB_
REGULATION
AN5
VCC
VCC
R8
Power/Other
VCC_SENSE
AN3
Power/Other
Output
VCC
T23
Power/Other
VCCA
A23
Power/Other
VCC
T24
Power/Other
VCCIOPLL
C23
Power/Other
VCC
T25
Power/Other
VCC
T26
Power/Other
VCC
T27
Power/Other
VCC
T28
Power/Other
VCC
T29
Power/Other
VCC
T30
Power/Other
VCC
T8
Power/Other
VCC
U23
Power/Other
VCC
U24
Power/Other
VCC
U25
Power/Other
VCC
U26
Power/Other
VCC
U27
Power/Other
VCCPLL
D23
Power/Other
VID_SELECT
AN7
Power/Other
VID0
AM2
Power/Other
Output
VID1
AL5
Power/Other
Output
VID2
AM3
Power/Other
Output
VID3
AL6
Power/Other
Output
VID4
AK4
Power/Other
Output
VID5
AL4
Power/Other
Output
Output
VID6
AM5
Power/Other
Output
VID7
AM7
Power/Other
Output
VRDSEL
AL3
Power/Other
VSS
A12
Power/Other
VSS
A15
Power/Other
51
Land Listing and Signal Descriptions
Table 23.
52
Alphabetical Land
Assignments
Land Name
Land
#
Signal Buffer
Type
VSS
A18
VSS
VSS
VSS
VSS
Table 23.
Alphabetical Land
Assignments
Land Name
Land
#
Signal Buffer
Type
Power/Other
VSS
AE27
Power/Other
A2
Power/Other
VSS
AE28
Power/Other
A21
Power/Other
VSS
AE29
Power/Other
A6
Power/Other
VSS
AE30
Power/Other
A9
Power/Other
VSS
AE5
Power/Other
VSS
AA23
Power/Other
VSS
AE7
Power/Other
VSS
AA24
Power/Other
VSS
AF10
Power/Other
VSS
AA25
Power/Other
VSS
AF13
Power/Other
VSS
AA26
Power/Other
VSS
AF16
Power/Other
VSS
AA27
Power/Other
VSS
AF17
Power/Other
VSS
AA28
Power/Other
VSS
AF20
Power/Other
VSS
AA29
Power/Other
VSS
AF23
Power/Other
VSS
AA3
Power/Other
VSS
AF24
Power/Other
VSS
AA30
Power/Other
VSS
AF25
Power/Other
VSS
AA6
Power/Other
VSS
AF26
Power/Other
VSS
AA7
Power/Other
VSS
AF27
Power/Other
VSS
AB1
Power/Other
VSS
AF28
Power/Other
VSS
AB23
Power/Other
VSS
AF29
Power/Other
VSS
AB24
Power/Other
VSS
AF3
Power/Other
VSS
AB25
Power/Other
VSS
AF30
Power/Other
VSS
AB26
Power/Other
VSS
AF6
Power/Other
VSS
AB27
Power/Other
VSS
AF7
Power/Other
VSS
AB28
Power/Other
VSS
AG10
Power/Other
VSS
AB29
Power/Other
VSS
AG13
Power/Other
VSS
AB30
Power/Other
VSS
AG16
Power/Other
Direction
VSS
AB7
Power/Other
VSS
AG17
Power/Other
VSS
AC3
Power/Other
VSS
AG20
Power/Other
VSS
AC6
Power/Other
VSS
AG23
Power/Other
VSS
AC7
Power/Other
VSS
AG24
Power/Other
VSS
AD4
Power/Other
VSS
AG7
Power/Other
VSS
AD7
Power/Other
VSS
AH1
Power/Other
VSS
AE10
Power/Other
VSS
AH10
Power/Other
VSS
AE13
Power/Other
VSS
AH13
Power/Other
VSS
AE16
Power/Other
VSS
AH16
Power/Other
VSS
AE17
Power/Other
VSS
AH17
Power/Other
VSS
AE2
Power/Other
VSS
AH20
Power/Other
VSS
AE20
Power/Other
VSS
AH23
Power/Other
VSS
AE24
Power/Other
VSS
AH24
Power/Other
VSS
AE25
Power/Other
VSS
AH3
Power/Other
VSS
AE26
Power/Other
VSS
AH6
Power/Other
Direction
Datasheet
Land Listing and Signal Descriptions
Table 23.
Datasheet
Alphabetical Land
Assignments
Land Name
Land
#
Signal Buffer
Type
VSS
AH7
VSS
VSS
Table 23.
Alphabetical Land
Assignments
Land Name
Land
#
Signal Buffer
Type
Power/Other
VSS
AM13
Power/Other
AJ10
Power/Other
VSS
AM16
Power/Other
AJ13
Power/Other
VSS
AM17
Power/Other
VSS
AJ16
Power/Other
VSS
AM20
Power/Other
VSS
AJ17
Power/Other
VSS
AM23
Power/Other
VSS
AJ20
Power/Other
VSS
AM24
Power/Other
VSS
AJ23
Power/Other
VSS
AM27
Power/Other
VSS
AJ24
Power/Other
VSS
AM28
Power/Other
VSS
AJ27
Power/Other
VSS
AM4
Power/Other
VSS
AJ28
Power/Other
VSS
AN1
Power/Other
VSS
AJ29
Power/Other
VSS
AN10
Power/Other
VSS
AJ30
Power/Other
VSS
AN13
Power/Other
VSS
AJ4
Power/Other
VSS
AN16
Power/Other
VSS
AJ7
Power/Other
VSS
AN17
Power/Other
VSS
AK10
Power/Other
VSS
AN2
Power/Other
VSS
AK13
Power/Other
VSS
AN20
Power/Other
VSS
AK16
Power/Other
VSS
AN23
Power/Other
VSS
AK17
Power/Other
VSS
AN24
Power/Other
VSS
AK2
Power/Other
VSS
AN27
Power/Other
VSS
AK20
Power/Other
VSS
AN28
Power/Other
VSS
AK23
Power/Other
VSS
B1
Power/Other
VSS
AK24
Power/Other
VSS
B11
Power/Other
VSS
AK27
Power/Other
VSS
B14
Power/Other
VSS
AK28
Power/Other
VSS
B17
Power/Other
VSS
AK29
Power/Other
VSS
B20
Power/Other
VSS
AK30
Power/Other
VSS
B24
Power/Other
VSS
AK5
Power/Other
VSS
B5
Power/Other
VSS
AK7
Power/Other
VSS
B8
Power/Other
VSS
AL10
Power/Other
VSS
C10
Power/Other
VSS
AL13
Power/Other
VSS
C13
Power/Other
VSS
AL16
Power/Other
VSS
C16
Power/Other
VSS
AL17
Power/Other
VSS
C19
Power/Other
VSS
AL20
Power/Other
VSS
C22
Power/Other
VSS
AL23
Power/Other
VSS
C24
Power/Other
VSS
AL24
Power/Other
VSS
C4
Power/Other
VSS
AL27
Power/Other
VSS
C7
Power/Other
VSS
AL28
Power/Other
VSS
D12
Power/Other
VSS
AL7
Power/Other
VSS
D15
Power/Other
VSS
AM1
Power/Other
VSS
D18
Power/Other
VSS
AM10
Power/Other
VSS
D21
Power/Other
Direction
Direction
53
Land Listing and Signal Descriptions
Table 23.
54
Alphabetical Land
Assignments
Land Name
Land
#
Signal Buffer
Type
VSS
D24
VSS
VSS
Table 23.
Alphabetical Land
Assignments
Land Name
Land
#
Signal Buffer
Type
Power/Other
VSS
H6
Power/Other
D3
Power/Other
VSS
H7
Power/Other
D5
Power/Other
VSS
H8
Power/Other
VSS
D6
Power/Other
VSS
H9
Power/Other
VSS
D9
Power/Other
VSS
J4
Power/Other
VSS
E11
Power/Other
VSS
J7
Power/Other
VSS
E14
Power/Other
VSS
K2
Power/Other
VSS
E17
Power/Other
VSS
K5
Power/Other
VSS
E2
Power/Other
VSS
K7
Power/Other
VSS
E20
Power/Other
VSS
L23
Power/Other
VSS
E25
Power/Other
VSS
L24
Power/Other
VSS
E26
Power/Other
VSS
L25
Power/Other
VSS
E27
Power/Other
VSS
L26
Power/Other
VSS
E28
Power/Other
VSS
L27
Power/Other
VSS
E8
Power/Other
VSS
L28
Power/Other
VSS
F10
Power/Other
VSS
L29
Power/Other
VSS
F13
Power/Other
VSS
L3
Power/Other
VSS
F16
Power/Other
VSS
L30
Power/Other
VSS
F19
Power/Other
VSS
L6
Power/Other
VSS
F22
Power/Other
VSS
L7
Power/Other
VSS
F4
Power/Other
VSS
M1
Power/Other
VSS
F7
Power/Other
VSS
M7
Power/Other
VSS
H10
Power/Other
VSS
N3
Power/Other
VSS
H11
Power/Other
VSS
N6
Power/Other
VSS
H12
Power/Other
VSS
N7
Power/Other
VSS
H13
Power/Other
VSS
P23
Power/Other
VSS
H14
Power/Other
VSS
P24
Power/Other
VSS
H17
Power/Other
VSS
P25
Power/Other
VSS
H18
Power/Other
VSS
P26
Power/Other
VSS
H19
Power/Other
VSS
P27
Power/Other
VSS
H20
Power/Other
VSS
P28
Power/Other
VSS
H21
Power/Other
VSS
P29
Power/Other
VSS
H22
Power/Other
VSS
P30
Power/Other
VSS
H23
Power/Other
VSS
P4
Power/Other
VSS
H24
Power/Other
VSS
P7
Power/Other
VSS
H25
Power/Other
VSS
R2
Power/Other
VSS
H26
Power/Other
VSS
R23
Power/Other
VSS
H27
Power/Other
VSS
R24
Power/Other
VSS
H28
Power/Other
VSS
R25
Power/Other
VSS
H3
Power/Other
VSS
R26
Power/Other
Direction
Direction
Datasheet
Land Listing and Signal Descriptions
Table 23.
Datasheet
Alphabetical Land
Assignments
Land Name
Land
#
Signal Buffer
Type
VSS
R27
VSS
VSS
VSS
VSS
Table 23.
Alphabetical Land
Assignments
Land Name
Land
#
Signal Buffer
Type
Power/Other
VTT
B30
Power/Other
R28
Power/Other
VTT
C25
Power/Other
R29
Power/Other
VTT
C26
Power/Other
R30
Power/Other
VTT
C27
Power/Other
R5
Power/Other
VTT
C28
Power/Other
VSS
R7
Power/Other
VTT
C29
Power/Other
VSS
T3
Power/Other
VTT
C30
Power/Other
VSS
T6
Power/Other
VTT
D25
Power/Other
VSS
T7
Power/Other
VTT
D26
Power/Other
VSS
U7
Power/Other
VTT
D27
Power/Other
VSS
V23
Power/Other
VTT
D28
Power/Other
VSS
V24
Power/Other
VTT
D29
Power/Other
VSS
V25
Power/Other
VTT
D30
Power/Other
VSS
V26
Power/Other
Power/Other
Output
V27
Power/Other
VTT_OUT_LEF
T
J1
VSS
VSS
V28
Power/Other
VTT_OUT_RIG
HT
AA1
Power/Other
Output
VSS
V29
Power/Other
VTT_SEL
F27
Power/Other
Output
VSS
V3
Power/Other
VSS
V30
Power/Other
VSS
V6
Power/Other
VSS
V7
Power/Other
VSS
W4
Power/Other
VSS
W7
Power/Other
VSS
Y2
Power/Other
VSS
Y5
Power/Other
Direction
VSS
Y7
Power/Other
VSS_MB_
REGULATION
AN6
Power/Other
Output
VSS_SENSE
AN4
Power/Other
Output
VSSA
B23
Power/Other
VTT
A25
Power/Other
VTT
A26
Power/Other
VTT
A27
Power/Other
VTT
A28
Power/Other
VTT
A29
Power/Other
VTT
A30
Power/Other
VTT
B25
Power/Other
VTT
B26
Power/Other
VTT
B27
Power/Other
VTT
B28
Power/Other
VTT
B29
Power/Other
Direction
55
Land Listing and Signal Descriptions
Table 24.
56
Numerical Land
Assignment
Table 24.
Numerical Land
Assignment
Land
#
Land Name
Signal Buffer
Type
Land
#
Land Name
Signal Buffer
Type
Direction
A2
VSS
Power/Other
B12
D13#
Source Synch
Input/Output
A3
RS2#
Common Clock
A4
D2#
Source Synch
Input
B13
COMP8
Power/Other
Input
Input/Output
B14
VSS
Power/Other
A5
D4#
Source Synch
Input/Output
A6
VSS
Power/Other
B15
D53#
Source Synch
Input/Output
B16
D55#
Source Synch
Input/Output
A7
D7#
Source Synch
Input/Output
B17
VSS
Power/Other
A8
DBI0#
Source Synch
Input/Output
B18
D57#
Source Synch
Input/Output
Input/Output
Direction
A9
VSS
Power/Other
B19
D60#
Source Synch
A10
D8#
Source Synch
Input/Output
B20
VSS
Power/Other
A11
D9#
Source Synch
Input/Output
B21
D59#
Source Synch
Input/Output
A12
VSS
Power/Other
B22
D63#
Source Synch
Input/Output
A13
COMP0
Power/Other
Input
B23
VSSA
Power/Other
A14
D50#
Source Synch
Input/Output
B24
VSS
Power/Other
A15
VSS
Power/Other
B25
VTT
Power/Other
A16
DSTBN3#
Source Synch
Input/Output
B26
VTT
Power/Other
A17
D56#
Source Synch
Input/Output
B27
VTT
Power/Other
A18
VSS
Power/Other
B28
VTT
Power/Other
A19
D61#
Source Synch
B29
VTT
Power/Other
A20
RESERVED
B30
VTT
Power/Other
C1
DRDY#
Common Clock Input/Output
C2
BNR#
Common Clock Input/Output
Common Clock Input/Output
Input/Output
A21
VSS
Power/Other
A22
D62#
Source Synch
A23
VCCA
Power/Other
C3
LOCK#
A24
FC23
Power/Other
C4
VSS
Power/Other
A25
VTT
Power/Other
C5
D1#
Source Synch
Input/Output
A26
VTT
Power/Other
C6
D3#
Source Synch
Input/Output
A27
VTT
Power/Other
C7
VSS
Power/Other
A28
VTT
Power/Other
C8
DSTBN0#
Source Synch
A29
VTT
Power/Other
C9
RESERVED
A30
VTT
Power/Other
C10
VSS
Power/Other
Power/Other
Input/Output
Input/Output
C11
D11#
Source Synch
Input/Output
Common Clock Input/Output
C12
D14#
Source Synch
Input/Output
RS0#
Common Clock
Input
C13
VSS
Power/Other
D0#
Source Synch
Input/Output
C14
D52#
Source Synch
Input/Output
Input/Output
B1
VSS
B2
DBSY#
B3
B4
B5
VSS
Power/Other
C15
D51#
Source Synch
B6
D5#
Source Synch
Input/Output
C16
VSS
Power/Other
B7
D6#
Source Synch
Input/Output
C17
DSTBP3#
Source Synch
Input/Output
B8
VSS
Power/Other
C18
D54#
Source Synch
Input/Output
B9
DSTBP0#
Source Synch
Input/Output
C19
VSS
Power/Other
B10
D10#
Source Synch
Input/Output
C20
DBI3#
Source Synch
Input/Output
B11
VSS
Power/Other
C21
D58#
Source Synch
Input/Output
Datasheet
Land Listing and Signal Descriptions
Table 24.
Datasheet
Numerical Land
Assignment
Land
#
Land Name
Signal Buffer
Type
C22
VSS
C23
C24
Table 24.
Numerical Land
Assignment
Land
#
Land Name
Signal Buffer
Type
Direction
Power/Other
E3
TRDY#
Common Clock
Input
VCCIOPLL
Power/Other
E4
HITM#
Common Clock Input/Output
VSS
Power/Other
E5
FC20
C25
VTT
Power/Other
E6
RESERVED
C26
VTT
Power/Other
E7
RESERVED
C27
VTT
Power/Other
E8
VSS
Power/Other
C28
VTT
Power/Other
E9
D19#
Source Synch
Input/Output
C29
VTT
Power/Other
E10
D21#
Source Synch
Input/Output
C30
VTT
Power/Other
E11
VSS
Power/Other
D1
RESERVED
E12
DSTBP1#
Source Synch
Input/Output
D2
ADS#
E13
D26#
Source Synch
Input/Output
Direction
Common Clock Input/Output
D3
VSS
D4
HIT#
Power/Other
D5
VSS
D6
VSS
D7
D20#
Source Synch
D8
D12#
Source Synch
Power/Other
E14
VSS
Power/Other
E15
D33#
Source Synch
Input/Output
Power/Other
E16
D34#
Source Synch
Input/Output
Power/Other
E17
VSS
Power/Other
Input/Output
E18
D39#
Source Synch
Input/Output
Input/Output
E19
D40#
Source Synch
Input/Output
Common Clock Input/Output
D9
VSS
Power/Other
E20
VSS
Power/Other
D10
D22#
Source Synch
Input/Output
E21
D42#
Source Synch
Input/Output
D11
D15#
Source Synch
Input/Output
E22
D45#
Source Synch
Input/Output
D12
VSS
Power/Other
E23
RESERVED
D13
D25#
Source Synch
E24
FC10
Power/Other
D14
RESERVED
E25
VSS
Power/Other
E26
VSS
Power/Other
E27
VSS
Power/Other
Input/Output
D15
VSS
D16
RESERVED
Power/Other
D17
D49#
Source Synch
D18
VSS
Power/Other
D19
DBI2#
Source Synch
Input/Output
F2
FC5
D20
D48#
Source Synch
Input/Output
F3
BR0#
D21
VSS
Power/Other
D22
D46#
Source Synch
D23
VCCPLL
D24
VSS
D25
VTT
D26
VTT
D27
D28
Input/Output
E28
VSS
Power/Other
E29
FC26
Power/Other
Power/Other
Common Clock Input/Output
F4
VSS
Power/Other
F5
RS1#
Common Clock
Power/Other
F6
FC21
Power/Other
Power/Other
F7
VSS
Power/Other
Power/Other
F8
D17#
Source Synch
Input/Output
Power/Other
F9
D18#
Source Synch
Input/Output
VTT
Power/Other
F10
VSS
Power/Other
VTT
Power/Other
F11
D23#
Source Synch
Input/Output
D29
VTT
Power/Other
F12
D24#
Source Synch
Input/Output
D30
VTT
Power/Other
F13
VSS
Power/Other
E2
VSS
Power/Other
F14
D28#
Source Synch
Input/Output
Input
Input/Output
57
Land Listing and Signal Descriptions
Table 24.
Table 24.
Numerical Land
Assignment
Land
#
Land Name
Signal Buffer
Type
Direction
Land
#
Land Name
Signal Buffer
Type
Direction
F15
D30#
Source Synch
Input/Output
G25
TESTHI3
Power/Other
Input
F16
VSS
Power/Other
G26
TESTHI5
Power/Other
Input
F17
D37#
Source Synch
Input/Output
G27
TESTHI4
Power/Other
Input
F18
D38#
Source Synch
Input/Output
G28
BCLK1
Clock
Input
F19
VSS
Power/Other
G29
BSEL0
Power/Other
Output
F20
D41#
Source Synch
Input/Output
G30
BSEL2
Power/Other
Output
F21
D43#
Source Synch
Input/Output
H1
GTLREF0
Power/Other
Input
F22
VSS
Power/Other
H2
GTLREF1
Power/Other
Input
F23
RESERVED
H3
VSS
Power/Other
F24
TESTHI7
Power/Other
Input
H4
FC35
Power/Other
F25
TESTHI2
Power/Other
Input
H5
TESTHI10
Power/Other
F26
TESTHI0
Power/Other
Input
H6
VSS
Power/Other
F27
VTT_SEL
Power/Other
Output
H7
VSS
Power/Other
F28
BCLK0
Clock
Input
H8
VSS
Power/Other
F29
RESERVED
H9
VSS
Power/Other
H10
VSS
Power/Other
H11
VSS
Power/Other
H12
VSS
Power/Other
H13
VSS
Power/Other
G1
FC27
Power/Other
G2
COMP2
Power/Other
Input
G3
TESTHI8/
FC42
Power/Other
Input
TESTHI9/
FC43
Power/Other
G4
58
Numerical Land
Assignment
Source Synch
Input
H14
VSS
Power/Other
Output
H15
FC32
Power/Other
G5
PECI
G6
RESERVED
H16
FC33
Power/Other
G7
DEFER#
Common Clock
Input
H17
VSS
Power/Other
G8
BPRI#
Common Clock
Input
H18
VSS
Power/Other
Input/Output
H19
VSS
Power/Other
G9
D16#
Source Synch
G10
FC38
Power/Other
H20
VSS
Power/Other
VSS
Power/Other
G11
DBI1#
Source Synch
Input/Output
H21
G12
DSTBN1#
Source Synch
Input/Output
H22
VSS
Power/Other
VSS
Power/Other
G13
D27#
Source Synch
Input/Output
H23
G14
D29#
Source Synch
Input/Output
H24
VSS
Power/Other
VSS
Power/Other
G15
D31#
Source Synch
Input/Output
H25
G16
D32#
Source Synch
Input/Output
H26
VSS
Power/Other
VSS
Power/Other
G17
D36#
Source Synch
Input/Output
H27
G18
D35#
Source Synch
Input/Output
H28
VSS
Power/Other
FC15
Power/Other
Input
G19
DSTBP2#
Source Synch
Input/Output
H29
G20
DSTBN2#
Source Synch
Input/Output
H30
BSEL1
Power/Other
Output
J1
VTT_OUT_LE
FT
Power/Other
Output
G21
D44#
Source Synch
Input/Output
G22
D47#
Source Synch
Input/Output
G23
RESET#
Common Clock
Input
G24
TESTHI6
Power/Other
Input
J2
FC3
Power/Other
J3
FC22
Power/Other
J4
VSS
Power/Other
Datasheet
Land Listing and Signal Descriptions
Table 24.
Datasheet
Numerical Land
Assignment
Table 24.
Numerical Land
Assignment
Land
#
Land Name
Signal Buffer
Type
Direction
Land
#
Land Name
Signal Buffer
Type
J5
REQ1#
Source Synch
Input/Output
K29
VCC
Power/Other
J6
REQ4#
Source Synch
Input/Output
K30
VCC
Power/Other
J7
VSS
Power/Other
L1
LINT1
Asynch GTL+
Input
J8
VCC
Power/Other
L2
TESTHI13
Asynch GTL+
Input
J9
VCC
Power/Other
L3
VSS
Power/Other
J10
VCC
Power/Other
L4
A06#
Source Synch
Input/Output
J11
VCC
Power/Other
L5
A03#
Source Synch
Input/Output
J12
VCC
Power/Other
L6
VSS
Power/Other
J13
VCC
Power/Other
L7
VSS
Power/Other
J14
VCC
Power/Other
L8
VCC
Power/Other
J15
VCC
Power/Other
L23
VSS
Power/Other
J16
FC31
Power/Other
L24
VSS
Power/Other
J17
FC34
Power/Other
L25
VSS
Power/Other
J18
VCC
Power/Other
L26
VSS
Power/Other
J19
VCC
Power/Other
L27
VSS
Power/Other
J20
VCC
Power/Other
L28
VSS
Power/Other
J21
VCC
Power/Other
L29
VSS
Power/Other
J22
VCC
Power/Other
L30
VSS
Power/Other
J23
VCC
Power/Other
M1
VSS
Power/Other
J24
VCC
Power/Other
M2
THERMTRIP#
Asynch GTL+
Output
J25
VCC
Power/Other
M3
STPCLK#
Asynch GTL+
Input
J26
VCC
Power/Other
M4
A07#
Source Synch
Input/Output
J27
VCC
Power/Other
M5
A05#
Source Synch
Input/Output
J28
VCC
Power/Other
M6
REQ2#
Source Synch
Input/Output
J29
VCC
Power/Other
M7
VSS
Power/Other
J30
VCC
Power/Other
K1
LINT0
Asynch GTL+
Input
M8
VCC
Power/Other
M23
VCC
Power/Other
K2
VSS
Power/Other
M24
VCC
Power/Other
K3
A20M#
Asynch GTL+
Input
M25
VCC
Power/Other
K4
REQ0#
Source Synch
Input/Output
M26
VCC
Power/Other
K5
VSS
Power/Other
M27
VCC
Power/Other
K6
REQ3#
Source Synch
M28
VCC
Power/Other
K7
VSS
Power/Other
M29
VCC
Power/Other
Input/Output
Direction
K8
VCC
Power/Other
M30
VCC
Power/Other
K23
VCC
Power/Other
N1
PWRGOOD
Power/Other
Input
K24
VCC
Power/Other
N2
IGNNE#
Asynch GTL+
Input
K25
VCC
Power/Other
N3
VSS
Power/Other
K26
VCC
Power/Other
N4
RESERVED
K27
VCC
Power/Other
N5
RESERVED
K28
VCC
Power/Other
N6
VSS
Power/Other
59
Land Listing and Signal Descriptions
Table 24.
60
Numerical Land
Assignment
Land
#
Land Name
Signal Buffer
Type
N7
VSS
Table 24.
Numerical Land
Assignment
Land
#
Land Name
Signal Buffer
Type
Power/Other
R29
VSS
Power/Other
Direction
Direction
N8
VCC
Power/Other
R30
VSS
Power/Other
N23
VCC
Power/Other
T1
COMP1
Power/Other
N24
VCC
Power/Other
T2
FC4
Power/Other
N25
VCC
Power/Other
T3
VSS
Power/Other
N26
VCC
Power/Other
T4
A11#
Source Synch
Input/Output
N27
VCC
Power/Other
T5
A09#
Source Synch
Input/Output
N28
VCC
Power/Other
T6
VSS
Power/Other
N29
VCC
Power/Other
T7
VSS
Power/Other
N30
VCC
Power/Other
T8
VCC
Power/Other
P1
TESTHI11
Power/Other
Input
T23
VCC
Power/Other
P2
SMI#
Asynch GTL+
Input
T24
VCC
Power/Other
P3
INIT#
Asynch GTL+
Input
T25
VCC
Power/Other
P4
VSS
Power/Other
T26
VCC
Power/Other
P5
RESERVED
T27
VCC
Power/Other
P6
A04#
Source Synch
T28
VCC
Power/Other
P7
VSS
Power/Other
T29
VCC
Power/Other
Input/Output
Input
P8
VCC
Power/Other
T30
VCC
Power/Other
P23
VSS
Power/Other
U1
FC28
Power/Other
P24
VSS
Power/Other
U2
FC29
Power/Other
P25
VSS
Power/Other
U3
FC30
Power/Other
P26
VSS
Power/Other
U4
A13#
Source Synch
Input/Output
P27
VSS
Power/Other
U5
A12#
Source Synch
Input/Output
P28
VSS
Power/Other
U6
A10#
Source Synch
Input/Output
P29
VSS
Power/Other
U7
VSS
Power/Other
P30
VSS
Power/Other
R1
COMP3
Power/Other
Input
U8
VCC
Power/Other
U23
VCC
Power/Other
R2
VSS
Power/Other
U24
VCC
Power/Other
R3
FERR#/PBE#
Asynch GTL+
Output
U25
VCC
Power/Other
R4
A08#
Source Synch
Input/Output
U26
VCC
Power/Other
R5
VSS
Power/Other
U27
VCC
Power/Other
R6
ADSTB0#
Source Synch
U28
VCC
Power/Other
R7
VSS
Power/Other
U29
VCC
Power/Other
Input/Output
R8
VCC
Power/Other
U30
VCC
Power/Other
R23
VSS
Power/Other
V1
MSID1
Power/Other
R24
VSS
Power/Other
V2
RESERVED
R25
VSS
Power/Other
V3
VSS
Power/Other
R26
VSS
Power/Other
V4
A15#
Source Synch
Input/Output
R27
VSS
Power/Other
V5
A14#
Source Synch
Input/Output
R28
VSS
Power/Other
V6
VSS
Power/Other
Output
Datasheet
Land Listing and Signal Descriptions
Table 24.
Datasheet
Numerical Land
Assignment
Land
#
Land Name
Signal Buffer
Type
V7
VSS
Table 24.
Numerical Land
Assignment
Land
#
Land Name
Signal Buffer
Type
Power/Other
Y29
VCC
Power/Other
Y30
VCC
Power/Other
AA1
VTT_OUT_RI
GHT
Power/Other
AA2
FC39
Power/Other
AA3
VSS
Power/Other
AA4
A21#
Source Synch
Input/Output
AA5
A23#
Source Synch
Input/Output
AA6
VSS
Power/Other
AA7
VSS
Power/Other
Direction
V8
VCC
Power/Other
V23
VSS
Power/Other
V24
VSS
Power/Other
V25
VSS
Power/Other
V26
VSS
Power/Other
V27
VSS
Power/Other
V28
VSS
Power/Other
V29
VSS
Power/Other
V30
VSS
Power/Other
W1
MSID0
Power/Other
Output
W2
TESTHI12/
FC44
Power/Other
Input
W3
TESTHI1
Power/Other
Input
AA8
VCC
Power/Other
AA23
VSS
Power/Other
AA24
VSS
Power/Other
AA25
VSS
Power/Other
W4
VSS
Power/Other
AA26
VSS
Power/Other
W5
A16#
Source Synch
Input/Output
AA27
VSS
Power/Other
W6
A18#
Source Synch
Input/Output
AA28
VSS
Power/Other
W7
VSS
Power/Other
AA29
VSS
Power/Other
Direction
Output
W8
VCC
Power/Other
AA30
VSS
Power/Other
W23
VCC
Power/Other
AB1
VSS
Power/Other
W24
VCC
Power/Other
AB2
IERR#
Asynch GTL+
W25
VCC
Power/Other
AB3
FC37
Power/Other
W26
VCC
Power/Other
AB4
A26#
Source Synch
Input/Output
W27
VCC
Power/Other
AB5
A24#
Source Synch
Input/Output
W28
VCC
Power/Other
AB6
A17#
Source Synch
Input/Output
W29
VCC
Power/Other
AB7
VSS
Power/Other
W30
VCC
Power/Other
AB8
VCC
Power/Other
Y1
FC0
Power/Other
AB23
VSS
Power/Other
Y2
VSS
Power/Other
AB24
VSS
Power/Other
Y3
FC17
Power/Other
AB25
VSS
Power/Other
Y4
A20#
Source Synch
AB26
VSS
Power/Other
Y5
VSS
Power/Other
AB27
VSS
Power/Other
Y6
A19#
Source Synch
AB28
VSS
Power/Other
Y7
VSS
Power/Other
AB29
VSS
Power/Other
Input/Output
Input/Output
Output
Y8
VCC
Power/Other
AB30
VSS
Power/Other
Y23
VCC
Power/Other
AC1
TMS
TAP
Input
Y24
VCC
Power/Other
AC2
DBR#
Power/Other
Output
Y25
VCC
Power/Other
AC3
VSS
Power/Other
Y26
VCC
Power/Other
AC4
RESERVED
Y27
VCC
Power/Other
AC5
A25#
Source Synch
Y28
VCC
Power/Other
AC6
VSS
Power/Other
Input/Output
61
Land Listing and Signal Descriptions
Table 24.
62
Numerical Land
Assignment
Land
#
Land Name
Signal Buffer
Type
AC7
VSS
Table 24.
Numerical Land
Assignment
Land
#
Land Name
Signal Buffer
Type
Power/Other
AE15
VCC
Power/Other
Direction
AC8
VCC
Power/Other
AE16
VSS
Power/Other
AC23
VCC
Power/Other
AE17
VSS
Power/Other
AC24
VCC
Power/Other
AE18
VCC
Power/Other
AC25
VCC
Power/Other
AE19
VCC
Power/Other
AC26
VCC
Power/Other
AE20
VSS
Power/Other
AC27
VCC
Power/Other
AE21
VCC
Power/Other
AC28
VCC
Power/Other
AE22
VCC
Power/Other
AC29
VCC
Power/Other
AE23
VCC
Power/Other
AC30
VCC
Power/Other
AE24
VSS
Power/Other
AD1
TDI
TAP
AE25
VSS
Power/Other
AD2
BPM2#
AE26
VSS
Power/Other
AD3
FC36
AE27
VSS
Power/Other
Input
Common Clock Input/Output
Power/Other
AD4
VSS
Power/Other
AE28
VSS
Power/Other
AD5
ADSTB1#
Source Synch
Input/Output
AE29
VSS
Power/Other
AD6
A22#
Source Synch
Input/Output
AE30
VSS
Power/Other
AD7
VSS
Power/Other
AF1
TDO
TAP
Direction
Output
AD8
VCC
Power/Other
AF2
BPM4#
AD23
VCC
Power/Other
AF3
VSS
Power/Other
AD24
VCC
Power/Other
AF4
A28#
Source Synch
Input/Output
AD25
VCC
Power/Other
AF5
A27#
Source Synch
Input/Output
AD26
VCC
Power/Other
AF6
VSS
Power/Other
AD27
VCC
Power/Other
AF7
VSS
Power/Other
AD28
VCC
Power/Other
AF8
VCC
Power/Other
AD29
VCC
Power/Other
AF9
VCC
Power/Other
AD30
VCC
Power/Other
AE1
TCK
TAP
Input
Common Clock Input/Output
AF10
VSS
Power/Other
AF11
VCC
Power/Other
AE2
VSS
Power/Other
AF12
VCC
Power/Other
AE3
FC18
Power/Other
AF13
VSS
Power/Other
AE4
RESERVED
AF14
VCC
Power/Other
AE5
VSS
AF15
VCC
Power/Other
AE6
RESERVED
AF16
VSS
Power/Other
AE7
VSS
AF17
VSS
Power/Other
AE8
SKTOCC#
AF18
VCC
Power/Other
AE9
VCC
Power/Other
AF19
VCC
Power/Other
AE10
VSS
Power/Other
AF20
VSS
Power/Other
AE11
VCC
Power/Other
AF21
VCC
Power/Other
AE12
VCC
Power/Other
AF22
VCC
Power/Other
AE13
VSS
Power/Other
AF23
VSS
Power/Other
AE14
VCC
Power/Other
AF24
VSS
Power/Other
Power/Other
Power/Other
Output
Datasheet
Land Listing and Signal Descriptions
Table 24.
Datasheet
Numerical Land
Assignment
Land
#
Land Name
Signal Buffer
Type
AF25
VSS
AF26
AF27
Table 24.
Numerical Land
Assignment
Land
#
Land Name
Signal Buffer
Type
Direction
Power/Other
AH5
A33#
Source Synch
Input/Output
VSS
Power/Other
AH6
VSS
Power/Other
VSS
Power/Other
AH7
VSS
Power/Other
AF28
VSS
Power/Other
AH8
VCC
Power/Other
AF29
VSS
Power/Other
AH9
VCC
Power/Other
AF30
VSS
Power/Other
AG1
TRST#
TAP
AG2
BPM3#
AG3
BPM5#
AG4
A30#
Source Synch
AG5
A31#
Source Synch
AG6
A29#
Source Synch
AG7
VSS
Power/Other
AG8
VCC
AG9
VCC
Direction
AH10
VSS
Power/Other
AH11
VCC
Power/Other
Common Clock Input/Output
AH12
VCC
Power/Other
Common Clock Input/Output
AH13
VSS
Power/Other
Input/Output
AH14
VCC
Power/Other
Input/Output
AH15
VCC
Power/Other
Input/Output
AH16
VSS
Power/Other
AH17
VSS
Power/Other
Power/Other
AH18
VCC
Power/Other
Power/Other
AH19
VCC
Power/Other
Input
AG10
VSS
Power/Other
AH20
VSS
Power/Other
AG11
VCC
Power/Other
AH21
VCC
Power/Other
AG12
VCC
Power/Other
AH22
VCC
Power/Other
AG13
VSS
Power/Other
AH23
VSS
Power/Other
AG14
VCC
Power/Other
AH24
VSS
Power/Other
AG15
VCC
Power/Other
AH25
VCC
Power/Other
AG16
VSS
Power/Other
AH26
VCC
Power/Other
AG17
VSS
Power/Other
AH27
VCC
Power/Other
AG18
VCC
Power/Other
AH28
VCC
Power/Other
AG19
VCC
Power/Other
AH29
VCC
Power/Other
AG20
VSS
Power/Other
AH30
VCC
AG21
VCC
Power/Other
AJ1
BPM1#
Common Clock Input/Output
AG22
VCC
Power/Other
AJ2
BPM0#
Common Clock Input/Output
AG23
VSS
Power/Other
AJ3
ITP_CLK1
Power/Other
TAP
Input
AG24
VSS
Power/Other
AJ4
VSS
Power/Other
AG25
VCC
Power/Other
AJ5
A34#
Source Synch
Input/Output
AG26
VCC
Power/Other
AJ6
A35#
Source Synch
Input/Output
AG27
VCC
Power/Other
AJ7
VSS
Power/Other
AG28
VCC
Power/Other
AJ8
VCC
Power/Other
AG29
VCC
Power/Other
AJ9
VCC
Power/Other
AG30
VCC
Power/Other
AJ10
VSS
Power/Other
AH1
VSS
Power/Other
AJ11
VCC
Power/Other
AH2
RESERVED
AJ12
VCC
Power/Other
AH3
VSS
Power/Other
AJ13
VSS
Power/Other
AH4
A32#
Source Synch
AJ14
VCC
Power/Other
Input/Output
63
Land Listing and Signal Descriptions
Table 24.
64
Numerical Land
Assignment
Land
#
Land Name
Signal Buffer
Type
AJ15
VCC
AJ16
AJ17
Table 24.
Numerical Land
Assignment
Land
#
Land Name
Signal Buffer
Type
Power/Other
AK25
VCC
Power/Other
VSS
Power/Other
AK26
VCC
Power/Other
VSS
Power/Other
AK27
VSS
Power/Other
AJ18
VCC
Power/Other
AK28
VSS
Power/Other
AJ19
VCC
Power/Other
AK29
VSS
Power/Other
AJ20
VSS
Power/Other
AK30
VSS
Power/Other
AJ21
VCC
Power/Other
AL1
THERMDA
Power/Other
AJ22
VCC
Power/Other
AL2
PROCHOT#
Asynch GTL+
AJ23
VSS
Power/Other
AL3
VRDSEL
Power/Other
AJ24
VSS
Power/Other
AL4
VID5
Power/Other
Output
AJ25
VCC
Power/Other
AL5
VID1
Power/Other
Output
AJ26
VCC
Power/Other
AL6
VID3
Power/Other
Output
AJ27
VSS
Power/Other
AL7
VSS
Power/Other
AJ28
VSS
Power/Other
AL8
VCC
Power/Other
AJ29
VSS
Power/Other
AL9
VCC
Power/Other
Direction
AJ30
VSS
Power/Other
AL10
VSS
Power/Other
AK1
THERMDC
Power/Other
AL11
VCC
Power/Other
AK2
VSS
Power/Other
AL12
VCC
Power/Other
AK3
ITP_CLK0
TAP
Input
AL13
VSS
Power/Other
AK4
VID4
Power/Other
Output
AL14
VCC
Power/Other
AK5
VSS
Power/Other
AL15
VCC
Power/Other
AK6
FC8
Power/Other
AL16
VSS
Power/Other
AK7
VSS
Power/Other
AL17
VSS
Power/Other
AK8
VCC
Power/Other
AL18
VCC
Power/Other
AK9
VCC
Power/Other
AL19
VCC
Power/Other
AK10
VSS
Power/Other
AL20
VSS
Power/Other
AK11
VCC
Power/Other
AL21
VCC
Power/Other
AK12
VCC
Power/Other
AL22
VCC
Power/Other
AK13
VSS
Power/Other
AL23
VSS
Power/Other
AK14
VCC
Power/Other
AL24
VSS
Power/Other
AK15
VCC
Power/Other
AL25
VCC
Power/Other
AK16
VSS
Power/Other
AL26
VCC
Power/Other
AK17
VSS
Power/Other
AL27
VSS
Power/Other
AK18
VCC
Power/Other
AL28
VSS
Power/Other
AK19
VCC
Power/Other
AL29
VCC
Power/Other
Direction
Input/Output
AK20
VSS
Power/Other
AL30
VCC
Power/Other
AK21
VCC
Power/Other
AM1
VSS
Power/Other
AK22
VCC
Power/Other
AM2
VID0
Power/Other
Output
AK23
VSS
Power/Other
AM3
VID2
Power/Other
Output
AK24
VSS
Power/Other
AM4
VSS
Power/Other
Datasheet
Land Listing and Signal Descriptions
Table 24.
Datasheet
Numerical Land
Assignment
Table 24.
Land
#
Land Name
Signal Buffer
Type
Direction
AM5
VID6
Power/Other
Output
AM6
FC40
Power/Other
AM7
VID7
Power/Other
AM8
VCC
Power/Other
AM9
VCC
Power/Other
AM10
VSS
Power/Other
AM11
VCC
Power/Other
AM12
VCC
Power/Other
AM13
VSS
Power/Other
AM14
VCC
Power/Other
AM15
VCC
Power/Other
AM16
VSS
Power/Other
AM17
VSS
Power/Other
AM18
VCC
Power/Other
AM19
VCC
Power/Other
AM20
VSS
Power/Other
AM21
VCC
Power/Other
AM22
VCC
Power/Other
AM23
VSS
Power/Other
AM24
VSS
Power/Other
AM25
VCC
Power/Other
AM26
VCC
Power/Other
AM27
VSS
Power/Other
AM28
VSS
Power/Other
AM29
VCC
Power/Other
AM30
VCC
Power/Other
AN1
VSS
Power/Other
Output
AN2
VSS
Power/Other
AN3
VCC_SENSE
Power/Other
Output
AN4
VSS_SENSE
Power/Other
Output
AN5
VCC_MB_
REGULATION
Power/Other
Output
Numerical Land
Assignment
Land
#
Land Name
Signal Buffer
Type
Direction
AN6
VSS_MB_
REGULATION
Power/Other
Output
AN7
VID_SELECT
Power/Other
Output
AN8
VCC
Power/Other
AN9
VCC
Power/Other
AN10
VSS
Power/Other
AN11
VCC
Power/Other
AN12
VCC
Power/Other
AN13
VSS
Power/Other
AN14
VCC
Power/Other
AN15
VCC
Power/Other
AN16
VSS
Power/Other
AN17
VSS
Power/Other
AN18
VCC
Power/Other
AN19
VCC
Power/Other
AN20
VSS
Power/Other
AN21
VCC
Power/Other
AN22
VCC
Power/Other
AN23
VSS
Power/Other
AN24
VSS
Power/Other
AN25
VCC
Power/Other
AN26
VCC
Power/Other
AN27
VSS
Power/Other
AN28
VSS
Power/Other
AN29
VCC
Power/Other
AN30
VCC
Power/Other
65
Land Listing and Signal Descriptions
4.2
Alphabetical Signals Reference
Table 25.
Signal Description ( (Sheet 1 of 9))
Name
A[35:3]#
Type
Input/
Output
Description
A[35:3]# (Address) define a 236-byte physical memory address
space. In sub-phase 1 of the address phase, these signals transmit
the address of a transaction. In sub-phase 2, these signals transmit
transaction type information. These signals must connect the
appropriate pins/lands of all agents on the processor FSB. A[35:3]#
are source synchronous signals and are latched into the receiving
buffers by ADSTB[1:0]#.
On the active-to-inactive transition of RESET#, the processor
samples a subset of the A[35:3]# signals to determine power-on
configuration. See Section 6.1 for more details.
A20M#
Input
If A20M# (Address-20 Mask) is asserted, the processor masks
physical address bit 20 (A20#) before looking up a line in any
internal cache and before driving a read/write transaction on the
bus. Asserting A20M# emulates the 8086 processor's address wraparound at the 1-MB boundary. Assertion of A20M# is only supported
in real mode.
A20M# is an asynchronous signal. However, to ensure recognition of
this signal following an Input/Output write instruction, it must be
valid along with the TRDY# assertion of the corresponding Input/
Output Write bus transaction.
ADS#
Input/
Output
ADS# (Address Strobe) is asserted to indicate the validity of the
transaction address on the A[35:3]# and REQ[4:0]# signals. All bus
agents observe the ADS# activation to begin protocol checking,
address decode, internal snoop, or deferred reply ID match
operations associated with the new transaction.
Address strobes are used to latch A[35:3]# and REQ[4:0]# on their
rising and falling edges. Strobes are associated with signals as
shown below.
ADSTB[1:0]#
BCLK[1:0]
Input/
Output
Input
Signals
Associated Strobe
REQ[4:0]#, A[16:3]#
ADSTB0#
A[35:17]#
ADSTB1#
The differential pair BCLK (Bus Clock) determines the FSB
frequency. All processor FSB agents must receive these signals to
drive their outputs and latch their inputs.
All external timing parameters are specified with respect to the
rising edge of BCLK0 crossing VCROSS.
BNR#
66
Input/
Output
BNR# (Block Next Request) is used to assert a bus stall by any bus
agent unable to accept new bus transactions. During a bus stall, the
current bus owner cannot issue any new transactions.
Datasheet
Land Listing and Signal Descriptions
Table 25.
Signal Description ( (Sheet 2 of 9))
Name
Type
Description
BPM[5:0]# (Breakpoint Monitor) are breakpoint and performance
monitor signals. They are outputs from the processor which indicate
the status of breakpoints and programmable counters used for
monitoring processor performance. BPM[5:0]# should connect the
appropriate pins/lands of all processor FSB agents.
BPM[5:0]#
Input/
Output
BPM4# provides PRDY# (Probe Ready) functionality for the TAP
port. PRDY# is a processor output used by debug tools to determine
processor debug readiness.
BPM5# provides PREQ# (Probe Request) functionality for the TAP
port. PREQ# is used by debug tools to request debug operation of
the processor.
These signals do not have on-die termination. Refer to Section 2.6.2
for termination requirements.
BPRI#
BR0#
BSEL[2:0]
COMP8
COMP[3:0]
Datasheet
Input
Input/
Output
BPRI# (Bus Priority Request) is used to arbitrate for ownership of
the processor FSB. It must connect the appropriate pins/lands of all
processor FSB agents. Observing BPRI# active (as asserted by the
priority agent) causes all other agents to stop issuing new requests,
unless such requests are part of an ongoing locked operation. The
priority agent keeps BPRI# asserted until all of its requests are
completed, then releases the bus by de-asserting BPRI#.
BR0# drives the BREQ0# signal in the system and is used by the
processor to request the bus. During power-on configuration this
signal is sampled to determine the agent ID = 0.
This signal does not have on-die termination and must be
terminated.
Output
The BCLK[1:0] frequency select signals BSEL[2:0] are used to select
the processor input clock frequency. Table 15 defines the possible
combinations of the signals and the frequency associated with each
combination. The required frequency is determined by the
processor, chipset and clock synthesizer. All agents must operate at
the same frequency. For more information about these signals,
including termination recommendations refer to Section 2.8.2.
Analog
COMP[3:0] and COMP8 must be terminated to VSS on the system
board using precision resistors.
67
Land Listing and Signal Descriptions
Table 25.
Signal Description ( (Sheet 3 of 9))
Name
Type
Description
D[63:0]# (Data) are the data signals. These signals provide a 64-bit
data path between the processor FSB agents, and must connect the
appropriate pins/lands on all such agents. The data driver asserts
DRDY# to indicate a valid data transfer.
D[63:0]# are quad-pumped signals and will, thus, be driven four
times in a common clock period. D[63:0]# are latched off the falling
edge of both DSTBP[3:0]# and DSTBN[3:0]#. Each group of 16
data signals correspond to a pair of one DSTBP# and one DSTBN#.
The following table shows the grouping of data signals to data
strobes and DBI#.
Quad-Pumped Signal Groups
D[63:0]#
Input/
Output
Data Group
DSTBN#/
DSTBP#
DBI#
D[15:0]#
0
0
D[31:16]#
1
1
D[47:32]#
2
2
D[63:48]#
3
3
Furthermore, the DBI# signals determine the polarity of the data
signals. Each group of 16 data signals corresponds to one DBI#
signal. When the DBI# signal is active, the corresponding data
group is inverted and therefore sampled active high.
DBI[3:0]# (Data Bus Inversion) are source synchronous and
indicate the polarity of the D[63:0]# signals.The DBI[3:0]# signals
are activated when the data on the data bus is inverted. If more
than half the data bits, within a 16-bit group, would have been
asserted electrically low, the bus agent may invert the data bus
signals for that particular sub-phase for that 16-bit group.
DBI[3:0]#
DBR#
DBSY#
68
Input/
Output
DBI[3:0] Assignment To Data Bus
Bus Signal
Data Bus Signals
DBI3#
D[63:48]#
DBI2#
D[47:32]#
DBI1#
D[31:16]#
DBI0#
D[15:0]#
Output
DBR# (Debug Reset) is used only in processor systems where no
debug port is implemented on the system board. DBR# is used by a
debug port interposer so that an in-target probe can drive system
reset. If a debug port is implemented in the system, DBR# is a no
connect in the system. DBR# is not a processor signal.
Input/
Output
DBSY# (Data Bus Busy) is asserted by the agent responsible for
driving data on the processor FSB to indicate that the data bus is in
use. The data bus is released after DBSY# is de-asserted. This
signal must connect the appropriate pins/lands on all processor FSB
agents.
Datasheet
Land Listing and Signal Descriptions
Table 25.
Signal Description ( (Sheet 4 of 9))
Name
DEFER#
DRDY#
Type
Description
Input
DEFER# is asserted by an agent to indicate that a transaction
cannot be guaranteed in-order completion. Assertion of DEFER# is
normally the responsibility of the addressed memory or input/output
agent. This signal must connect the appropriate pins/lands of all
processor FSB agents.
Input/
Output
DRDY# (Data Ready) is asserted by the data driver on each data
transfer, indicating valid data on the data bus. In a multi-common
clock data transfer, DRDY# may be de-asserted to insert idle clocks.
This signal must connect the appropriate pins/lands of all processor
FSB agents.
DSTBN[3:0]# are the data strobes used to latch in D[63:0]#.
DSTBN[3:0]#
Input/
Output
Signals
Associated Strobe
D[15:0]#, DBI0#
DSTBN0#
D[31:16]#, DBI1#
DSTBN1#
D[47:32]#, DBI2#
DSTBN2#
D[63:48]#, DBI3#
DSTBN3#
DSTBP[3:0]# are the data strobes used to latch in D[63:0]#.
DSTBP[3:0]#
Associated Strobe
D[15:0]#, DBI0#
DSTBP0#
D[31:16]#, DBI1#
DSTBP1#
D[47:32]#, DBI2#
DSTBP2#
D[63:48]#, DBI3#
DSTBP3#
Other
FC signals are signals that are available for compatibility with other
processors.
FERR#/PBE#
Output
FERR#/PBE# (floating point error/pending break event) is a
multiplexed signal and its meaning is qualified by STPCLK#. When
STPCLK# is not asserted, FERR#/PBE# indicates a floating-point
error and will be asserted when the processor detects an unmasked
floating-point error. When STPCLK# is not asserted, FERR#/PBE# is
similar to the ERROR# signal on the Intel 387 coprocessor, and is
included for compatibility with systems using MS-DOS*-type
floating-point error reporting. When STPCLK# is asserted, an
assertion of FERR#/PBE# indicates that the processor has a pending
break event waiting for service. The assertion of FERR#/PBE#
indicates that the processor should be returned to the Normal state.
For additional information on the pending break event functionality,
including the identification of support of the feature and enable/
disable information, refer to volume 3 of the Intel Architecture
Software Developer's Manual and the Intel Processor Identification
and the CPUID Instruction application note.
GTLREF[1:0]
Input
FCx
Datasheet
Input/
Output
Signals
GTLREF[1:0] determine the signal reference level for GTL+ input
signals. GTLREF is used by the GTL+ receivers to determine if a
signal is a logical 0 or logical 1.
69
Land Listing and Signal Descriptions
Table 25.
Signal Description ( (Sheet 5 of 9))
Name
HIT#
HITM#
IERR#
Type
Input/
Output
Input/
Output
Output
Description
HIT# (Snoop Hit) and HITM# (Hit Modified) convey transaction
snoop operation results. Any FSB agent may assert both HIT# and
HITM# together to indicate that it requires a snoop stall, which can
be continued by reasserting HIT# and HITM# together.
IERR# (Internal Error) is asserted by a processor as the result of an
internal error. Assertion of IERR# is usually accompanied by a
SHUTDOWN transaction on the processor FSB. This transaction may
optionally be converted to an external error signal (e.g., NMI) by
system core logic. The processor will keep IERR# asserted until the
assertion of RESET#.
This signal does not have on-die termination. Refer to Section 2.6.2
for termination requirements.
IGNNE#
Input
IGNNE# (Ignore Numeric Error) is asserted to the processor to
ignore a numeric error and continue to execute noncontrol floatingpoint instructions. If IGNNE# is de-asserted, the processor
generates an exception on a noncontrol floating-point instruction if a
previous floating-point instruction caused an error. IGNNE# has no
effect when the NE bit in control register 0 (CR0) is set.
IGNNE# is an asynchronous signal. However, to ensure recognition
of this signal following an Input/Output write instruction, it must be
valid along with the TRDY# assertion of the corresponding Input/
Output Write bus transaction.
INIT#
ITP_CLK[1:0]
LINT[1:0]
Input
INIT# (Initialization), when asserted, resets integer registers inside
the processor without affecting its internal caches or floating-point
registers. The processor then begins execution at the power-on
Reset vector configured during power-on configuration. The
processor continues to handle snoop requests during INIT#
assertion. INIT# is an asynchronous signal and must connect the
appropriate pins/lands of all processor FSB agents.
Input
ITP_CLK[1:0] are copies of BCLK that are used only in processor
systems where no debug port is implemented on the system board.
ITP_CLK[1:0] are used as BCLK[1:0] references for a debug port
implemented on an interposer. If a debug port is implemented in the
system, ITP_CLK[1:0] are no connects in the system. These are not
processor signals.
Input
LINT[1:0] (Local APIC Interrupt) must connect the appropriate pins/
lands of all APIC Bus agents. When the APIC is disabled, the LINT0
signal becomes INTR, a maskable interrupt request signal, and
LINT1 becomes NMI, a nonmaskable interrupt. INTR and NMI are
backward compatible with the signals of those names on the
Pentium processor. Both signals are asynchronous.
Both of these signals must be software configured via BIOS
programming of the APIC register space to be used either as NMI/
INTR or LINT[1:0]. Because the APIC is enabled by default after
Reset, operation of these signals as LINT[1:0] is the default
configuration.
70
Datasheet
Land Listing and Signal Descriptions
Table 25.
Signal Description ( (Sheet 6 of 9))
Name
Type
Description
LOCK# indicates to the system that a transaction must occur
atomically. This signal must connect the appropriate pins/lands of all
processor FSB agents. For a locked sequence of transactions,
LOCK# is asserted from the beginning of the first transaction to the
end of the last transaction.
LOCK#
Input/
Output
PECI
Input/
Output
PECI is a proprietary one-wire bus interface. See Section 5.4 for
details.
Input/
Output
As an output, PROCHOT# (Processor Hot) will go active when the
processor temperature monitoring sensor detects that the processor
has reached its maximum safe operating temperature. This indicates
that the processor Thermal Control Circuit (TCC) has been activated,
if enabled. As an input, assertion of PROCHOT# by the system will
activate the TCC, if enabled. The TCC will remain active until the
system de-asserts PROCHOT#. See Section 5.2.4 for more details.
PROCHOT#
PWRGOOD
Input
When the priority agent asserts BPRI# to arbitrate for ownership of
the processor FSB, it will wait until it observes LOCK# de-asserted.
This enables symmetric agents to retain ownership of the processor
FSB throughout the bus locked operation and ensure the atomicity
of lock.
PWRGOOD (Power Good) is a processor input. The processor
requires this signal to be a clean indication that the clocks and
power supplies are stable and within their specifications. ‘Clean’
implies that the signal will remain low (capable of sinking leakage
current), without glitches, from the time that the power supplies are
turned on until they come within specification. The signal must then
transition monotonically to a high state. PWRGOOD can be driven
inactive at any time, but clocks and power must again be stable
before a subsequent rising edge of PWRGOOD.
The PWRGOOD signal must be supplied to the processor; it is used
to protect internal circuits against voltage sequencing issues. It
should be driven high throughout boundary scan operation.
REQ[4:0]#
RESET#
Input/
Output
Input
REQ[4:0]# (Request Command) must connect the appropriate pins/
lands of all processor FSB agents. They are asserted by the current
bus owner to define the currently active transaction type. These
signals are source synchronous to ADSTB0#.
Asserting the RESET# signal resets the processor to a known state
and invalidates its internal caches without writing back any of their
contents. For a power-on Reset, RESET# must stay active for at
least one millisecond after VCC and BCLK have reached their proper
specifications. On observing active RESET#, all FSB agents will deassert their outputs within two clocks. RESET# must not be kept
asserted for more than 10 ms while PWRGOOD is asserted.
A number of bus signals are sampled at the active-to-inactive
transition of RESET# for power-on configuration. These
configuration options are described in the Section 6.1.
This signal does not have on-die termination and must be
terminated on the system board.
RESERVED
Datasheet
All RESERVED lands must remain unconnected. Connection of these
lands to VCC, VSS, VTT, or to any other signal (including each other)
can result in component malfunction or incompatibility with future
processors.
71
Land Listing and Signal Descriptions
Table 25.
Signal Description ( (Sheet 7 of 9))
Name
Type
Description
RS[2:0]#
Input
RS[2:0]# (Response Status) are driven by the response agent (the
agent responsible for completion of the current transaction), and
must connect the appropriate pins/lands of all processor FSB
agents.
SKTOCC#
Output
SKTOCC# (Socket Occupied) will be pulled to ground by the
processor. System board designers may use this signal to determine
if the processor is present.
SMI#
Input
SMI# (System Management Interrupt) is asserted asynchronously
by system logic. On accepting a System Management Interrupt, the
processor saves the current state and enter System Management
Mode (SMM). An SMI Acknowledge transaction is issued, and the
processor begins program execution from the SMM handler.
If SMI# is asserted during the de-assertion of RESET#, the
processor will tri-state its outputs.
STPCLK#
Input
STPCLK# (Stop Clock), when asserted, causes the processor to
enter a low power Stop-Grant state. The processor issues a StopGrant Acknowledge transaction, and stops providing internal clock
signals to all processor core units except the FSB and APIC units.
The processor continues to snoop bus transactions and service
interrupts while in Stop-Grant state. When STPCLK# is de-asserted,
the processor restarts its internal clock to all units and resumes
execution. The assertion of STPCLK# has no effect on the bus clock;
STPCLK# is an asynchronous input.
TCK
Input
TCK (Test Clock) provides the clock input for the processor Test Bus
(also known as the Test Access Port).
TDI
Input
TDI (Test Data In) transfers serial test data into the processor. TDI
provides the serial input needed for JTAG specification support.
TDO
Output
TDO (Test Data Out) transfers serial test data out of the processor.
TDO provides the serial output needed for JTAG specification
support.
Input
TESTHI[13:0] must be connected to the processor’s appropriate
power source (refer to VTT_OUT_LEFT and VTT_OUT_RIGHT signal
description) through a resistor for proper processor operation. See
Section 2.4 for more details.
TESTHI[13:0]
72
Datasheet
Land Listing and Signal Descriptions
Table 25.
Signal Description ( (Sheet 8 of 9))
Name
THERMTRIP#
Description
Output
In the event of a catastrophic cooling failure, the processor will
automatically shut down when the silicon has reached a temperature
approximately 20 °C above the maximum TC. Assertion of
THERMTRIP# (Thermal Trip) indicates the processor junction
temperature has reached a level beyond where permanent silicon
damage may occur. Upon assertion of THERMTRIP#, the processor
will shut off its internal clocks (thus, halting program execution) in
an attempt to reduce the processor junction temperature. To protect
the processor, its core voltage (VCC) must be removed following the
assertion of THERMTRIP#. Driving of the THERMTRIP# signal is
enabled within 10 μs of the assertion of PWRGOOD (provided VTT
and VCC are valid) and is disabled on de-assertion of PWRGOOD (if
VTT or VCC are not valid, THERMTRIP# may also be disabled). Once
activated, THERMTRIP# remains latched until PWRGOOD, VTT, or
VCC is de-asserted. While the de-assertion of the PWRGOOD, VTT, or
VCC will de-assert THERMTRIP#, if the processor’s junction
temperature remains at or above the trip level, THERMTRIP# will
again be asserted within 10 μs of the assertion of PWRGOOD
(provided VTT and VCC are valid).
TMS
Input
TMS (Test Mode Select) is a JTAG specification support signal used
by debug tools.
TRDY#
Input
TRDY# (Target Ready) is asserted by the target to indicate that it is
ready to receive a write or implicit writeback data transfer. TRDY#
must connect the appropriate pins/lands of all FSB agents.
TRST#
Input
TRST# (Test Reset) resets the Test Access Port (TAP) logic. TRST#
must be driven low during power on Reset.
VCC
Input
VCC are the power pins for the processor. The voltage supplied to
these pins is determined by the VID[6:0] pins.
VCCPLL
Input
VCCPLL provides isolated power for internal processor FSB PLLs.
VCC_SENSE
VCC_MB_
REGULATION
VID[6:1]
VID_SELECT
Datasheet
Type
Output
VCC_SENSE is an isolated low impedance connection to processor
core power (VCC). It can be used to sense or measure voltage near
the silicon with little noise.
Output
This land is provided as a voltage regulator feedback sense point for
VCC. It is connected internally in the processor package to the sense
point land U27 as described in the Voltage Regulator-Down (VRD)
11 Design Guide For Desktop and Transportable LGA775 Socket.
Output
VID[6:1] (Voltage ID) signals are used to support automatic
selection of power supply voltages (VCC). Refer to the appropriate
platform design guide or the Voltage Regulator-Down (VRD) 11
Design Guide For Desktop and Transportable LGA775 Socket for
more information. The voltage supply for these signals must be valid
before the VR can supply VCC to the processor. Conversely, the VR
output must be disabled until the voltage supply for the VID signals
becomes valid. The VID signals are needed to support the processor
voltage specification variations. See Table 2 for definitions of these
signals. The VR must supply the voltage that is requested by the
signals, or disable itself.
Output
This land is tied high on the processor package and is used by the
VR to choose the proper VID table. Refer to the Voltage RegulatorDown (VRD) 11 Design Guide For Desktop and Transportable
LGA775 Socket for more information.
73
Land Listing and Signal Descriptions
Table 25.
Signal Description ( (Sheet 9 of 9))
Name
Type
Description
VRDSEL
Input
This input should be left as a no connect in order for the processor
to boot. The processor will not boot on legacy platforms where this
land is connected to VSS.
VSS
Input
VSS are the ground pins for the processor and should be connected
to the system ground plane.
VSSA
Input
VSSA is the isolated ground for internal PLLs.
VSS_SENSE
VSS_MB_
REGULATION
Output
VSS_SENSE is an isolated low impedance connection to processor
core VSS. It can be used to sense or measure ground near the silicon
with little noise.
Output
This land is provided as a voltage regulator feedback sense point for
VSS. It is connected internally in the processor package to the sense
point land V27 as described in the Voltage Regulator-Down (VRD)
11 Design Guide For Desktop and Transportable LGA775 Socket.
VTT
Miscellaneous voltage supply.
VTT_OUT_LEFT
Output
The VTT_OUT_LEFT and VTT_OUT_RIGHT signals are included to
provide a voltage supply for some signals that require termination to
VTT on the motherboard.
Output
The VTT_SEL signal is used to select the correct VTT voltage level for
the processor.
VTT_OUT_RIGHT
VTT_SEL
§
74
Datasheet
Thermal Specifications and Design Considerations
5
Thermal Specifications and
Design Considerations
5.1
Processor Thermal Specifications
The processor requires a thermal solution to maintain temperatures within the
operating limits as set forth in Section 5.1.1. Any attempt to operate the processor
outside these operating limits may result in permanent damage to the processor and
potentially other components within the system. As processor technology changes,
thermal management becomes increasingly crucial when building computer systems.
Maintaining the proper thermal environment is key to reliable, long-term system
operation.
A complete thermal solution includes both component and system level thermal
management features. Component level thermal solutions can include active or passive
heatsinks attached to the processor Integrated Heat Spreader (IHS). Typical system
level thermal solutions may consist of system fans combined with ducting and venting.
For more information on designing a component level thermal solution, refer to the
Intel® Celeron® Processor 400 Series Thermal and Mechanical Design Guidelines.
Note:
The boxed processor will ship with a component thermal solution. Refer to Chapter 7
for details on the boxed processor.
5.1.1
Thermal Specifications
To allow for the optimal operation and long-term reliability of Intel processor-based
systems, the system/processor thermal solution should be designed such that the
processor remains within the minimum and maximum case temperature (TC)
specifications when operating at or below the Thermal Design Power (TDP) value listed
per frequency in Table . Thermal solutions not designed to provide this level of thermal
capability may affect the long-term reliability of the processor and system. For more
details on thermal solution design, refer to the Intel® Celeron® Processor 400 Series
Thermal and Mechanical Design Guidelines.
The processor uses a methodology for managing processor temperatures which is
intended to support acoustic noise reduction through fan speed control. Selection of the
appropriate fan speed is based on the relative temperature data reported by the
processor’s Platform Environment Control Interface (PECI) bus as described in
Section 5.4.1.1. The temperature reported over PECI is always a negative value and
represents a delta below the onset of thermal control circuit (TCC) activation, as
indicated by PROCHOT# (see Section 5.2). Systems that implement fan speed control
must be designed to take these conditions in to account. Systems that do not alter the
fan speed only need to guarantee the case temperature meets the thermal profile
specifications.
To determine a processor's case temperature specification based on the thermal profile,
it is necessary to accurately measure processor power dissipation. Intel has developed
a methodology for accurate power measurement that correlates to Intel test
temperature and voltage conditions. Refer to the Intel® Celeron® Processor 400 Series
Thermal and Mechanical Design Guidelines for the details of this methodology.
The case temperature is defined at the geometric top center of the processor. Analysis
indicates that real applications are unlikely to cause the processor to consume
maximum power dissipation for sustained time periods. Intel recommends that
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75
Thermal Specifications and Design Considerations
complete thermal solution designs target the Thermal Design Power (TDP) indicated in
Table instead of the maximum processor power consumption. The Thermal Monitor
feature is designed to protect the processor in the unlikely event that an application
exceeds the TDP recommendation for a sustained periods of time. For more details on
the usage of this feature, refer to Section 5.2. To ensure maximum flexibility for future
requirements, systems should be designed to the 775_VR_CONFIG_06 guidelines, even
if a processor with a lower thermal dissipation is currently planned. In all cases the
Thermal Monitor or Thermal Monitor 2 feature must be enabled for the processor to
remain within specification.
Table 26.
Processor Thermal Specifications
Processor
Number
Core
Frequency
(GHz)
Thermal
Design
Power (W)
Extended
HALT
Power (W)1
420
1.6
35.0
8
430
1.8
35.0
8
440
2.0
35.0
8
450
2.2
35.0
8
775_VR_
CONFIG_06
Guidance2
Minimum
TC (°C)
Maximum
TC (°C)
3, 4
5
775_VR_CONFIG
_06
5
5
5
Notes
See Table 27,
Figure 16
3, 4
3, 4
3, 4
NOTES:
1. Specification is at 35 °C TC and typical voltage loadline.
2. 775_VR_CONFIG_06 guidelines provide a design target for meeting future thermal requirements.
3. Thermal Design Power (TDP) should be used for processor thermal solution design targets. The TDP is not the maximum power
that the processor can dissipate.
4. This table shows the maximum TDP for a given frequency range. Individual processors may have a lower TDP. Therefore, the
maximum TC will vary depending on the TDP of the individual processor. Refer to thermal profile figure and associated table for
the allowed combinations of power and TC.
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Thermal Specifications and Design Considerations
Table 27.
Figure 16.
Thermal Profile
Power (W)
Maximum
Tc (°C)
Power
Maximum
Tc (°C)
0
43.2
20
53.0
2
44.2
22
54.0
4
45.2
24
55.0
6
46.1
26
55.9
8
47.1
28
56.9
10
48.1
30
57.9
12
49.1
32
58.9
14
50.1
34
59.9
16
51.0
35
60.4
18
52.0
Thermal Profile
65.0
60.0
55.0
Tcase (C)
50.0
45.0
40.0
35.0
30.0
0
y = 0.49x + 43.3
Datasheet
10
20
30
Pow er (W )
77
Thermal Specifications and Design Considerations
5.1.2
Thermal Metrology
The maximum and minimum case temperatures (TC) for the processor is specified in
Table 26. This temperature specification is meant to help ensure proper operation of
the processor. Figure 17 illustrates where Intel recommends TC thermal measurements
should be made. For detailed guidelines on temperature measurement methodology,
refer to the Intel® Celeron® Processor 400 Series Thermal and Mechanical Design
Guidelines.
Figure 17.
Case Temperature (TC) Measurement Location
37.5 mm
Measure TC at this point
(geometric center of the package)
37.5 mm
5.2
Processor Thermal Features
5.2.1
Thermal Monitor
The Thermal Monitor feature helps control the processor temperature by activating the
thermal control circuit (TCC) when the processor silicon reaches its maximum operating
temperature. The TCC reduces processor power consumption by modulating (starting
and stopping) the internal processor core clocks. The Thermal Monitor feature must
be enabled for the processor to be operating within specifications. The
temperature at which Thermal Monitor activates the thermal control circuit is not user
configurable and is not software visible. Bus traffic is snooped in the normal manner,
and interrupt requests are latched (and serviced during the time that the clocks are on)
while the TCC is active.
When the Thermal Monitor feature is enabled, and a high temperature situation exists
(i.e., TCC is active), the clocks will be modulated by alternately turning the clocks off
and on at a duty cycle specific to the processor (typically 30–50%). Clocks often will
not be off for more than 3.0 microseconds when the TCC is active. Cycle times are
processor speed dependent and will decrease as processor core frequencies increase. A
small amount of hysteresis has been included to prevent rapid active/inactive
transitions of the TCC when the processor temperature is near its maximum operating
temperature. Once the temperature has dropped below the maximum operating
temperature, and the hysteresis timer has expired, the TCC goes inactive and clock
modulation ceases.
With a properly designed and characterized thermal solution, it is anticipated that the
TCC would only be activated for very short periods of time when running the most
power intensive applications. The processor performance impact due to these brief
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Datasheet
Thermal Specifications and Design Considerations
periods of TCC activation is expected to be so minor that it would be immeasurable. An
under-designed thermal solution that is not able to prevent excessive activation of the
TCC in the anticipated ambient environment may cause a noticeable performance loss,
and in some cases may result in a TC that exceeds the specified maximum temperature
and may affect the long-term reliability of the processor. In addition, a thermal solution
that is significantly under-designed may not be capable of cooling the processor even
when the TCC is active continuously. Refer to the Intel® Celeron® Processor 400 Series
Thermal and Mechanical Design Guidelines for information on designing a thermal
solution.
The duty cycle for the TCC, when activated by the Thermal Monitor, is factory
configured and cannot be modified. The Thermal Monitor does not require any
additional hardware, software drivers, or interrupt handling routines.
5.2.2
Thermal Monitor 2
The processor also supports an additional power reduction capability known as Thermal
Monitor 2. This mechanism provides an efficient means for limiting the processor
temperature by reducing the power consumption within the processor.
When Thermal Monitor 2 is enabled, and a high temperature situation is detected, the
Thermal Control Circuit (TCC) will be activated. The TCC causes the processor to adjust
its operating frequency (via the bus multiplier) and input voltage (via the VID signals).
This combination of reduced frequency and VID results in a reduction to the processor
power consumption.
A processor enabled for Thermal Monitor 2 includes two operating points, each
consisting of a specific operating frequency and voltage. The first operating point
represents the normal operating condition for the processor. Under this condition, the
core-frequency-to-FSB multiple used by the processor is that contained in the
CLK_GEYSIII_STAT MSR and the VID is that specified in Table 2. These parameters
represent normal system operation.
The second operating point consists of both a lower operating frequency and voltage.
When the TCC is activated, the processor automatically transitions to the new
frequency. This transition occurs very rapidly (on the order of 5 μs). During the
frequency transition, the processor is unable to service any bus requests, and
consequently, all bus traffic is blocked. Edge-triggered interrupts will be latched and
kept pending until the processor resumes operation at the new frequency.
Once the new operating frequency is engaged, the processor will transition to the new
core operating voltage by issuing a new VID code to the voltage regulator. The voltage
regulator must support dynamic VID steps in order to support Thermal Monitor 2.
During the voltage change, it will be necessary to transition through multiple VID codes
to reach the target operating voltage. Each step will likely be one VID table entry (see
Table 2). The processor continues to execute instructions during the voltage transition.
Operation at the lower voltage reduces the power consumption of the processor.
A small amount of hysteresis has been included to prevent rapid active/inactive
transitions of the TCC when the processor temperature is near its maximum operating
temperature. Once the temperature has dropped below the maximum operating
temperature, and the hysteresis timer has expired, the operating frequency and
voltage transition back to the normal system operating point. Transition of the VID code
will occur first, in order to insure proper operation once the processor reaches its
normal operating frequency. Refer to Figure 18 for an illustration of this ordering.
Datasheet
79
Thermal Specifications and Design Considerations
Figure 18.
Thermal Monitor 2 Frequency and Voltage Ordering
TTM2
Temperature
fMAX
fTM2
Frequency
VID
VIDTM2
VID
PROCHOT#
The PROCHOT# signal is asserted when a high temperature situation is detected,
regardless of whether Thermal Monitor or Thermal Monitor 2 is enabled.
It should be noted that the Thermal Monitor 2 TCC cannot be activated via the on
demand mode. The Thermal Monitor TCC, however, can be activated through the use of
the on demand mode.
5.2.3
On-Demand Mode
The processor provides an auxiliary mechanism that allows system software to force
the processor to reduce its power consumption. This mechanism is referred to as “OnDemand” mode and is distinct from the Thermal Monitor feature. On-Demand mode is
intended as a means to reduce system level power consumption. Systems using the
processor must not rely on software usage of this mechanism to limit the processor
temperature.
If bit 4 of the ACPI P_CNT Control Register (located in the processor
IA32_THERM_CONTROL MSR) is written to a '1', the processor will immediately reduce
its power consumption via modulation (starting and stopping) of the internal core clock,
independent of the processor temperature. When using On-Demand mode, the duty
cycle of the clock modulation is programmable via bits 3:1 of the same ACPI P_CNT
Control Register. In On-Demand mode, the duty cycle can be programmed from 12.5%
on/87.5% off, to 87.5% on/12.5% off in 12.5% increments. On-Demand mode may be
used in conjunction with the Thermal Monitor. If the system tries to enable On-Demand
mode at the same time the TCC is engaged, the factory configured duty cycle of the
TCC will override the duty cycle selected by the On-Demand mode.
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5.2.4
PROCHOT# Signal
An external signal, PROCHOT# (processor hot), is asserted when the processor core
temperature has reached its maximum operating temperature. If the Thermal Monitor
is enabled (note that the Thermal Monitor must be enabled for the processor to be
operating within specification), the TCC will be active when PROCHOT# is asserted. The
processor can be configured to generate an interrupt upon the assertion or deassertion of PROCHOT#.
As an output, PROCHOT# (Processor Hot) will go active when the processor
temperature monitoring sensor detects that one or both cores has reached its
maximum safe operating temperature. This indicates that the processor Thermal
Control Circuit (TCC) has been activated, if enabled. As an input, assertion of
PROCHOT# by the system will activate the TCC, if enabled, for both cores. The TCC will
remain active until the system de-asserts PROCHOT#.
PROCHOT# allows for some protection of various components from over-temperature
situations. The PROCHOT# signal is bi-directional in that it can either signal when the
processor (either core) has reached its maximum operating temperature or be driven
from an external source to activate the TCC. The ability to activate the TCC via
PROCHOT# can provide a means for thermal protection of system components.
PROCHOT# can allow VR thermal designs to target maximum sustained current instead
of maximum current. Systems should still provide proper cooling for the VR, and rely
on PROCHOT# only as a backup in case of system cooling failure. The system thermal
design should allow the power delivery circuitry to operate within its temperature
specification even while the processor is operating at its Thermal Design Power. With a
properly designed and characterized thermal solution, it is anticipated that PROCHOT#
would only be asserted for very short periods of time when running the most power
intensive applications. An under-designed thermal solution that is not able to prevent
excessive assertion of PROCHOT# in the anticipated ambient environment may cause a
noticeable performance loss. Refer to the Voltage Regulator-Down (VRD) 11 Design
Guide For Desktop and Transportable LGA775 Socket for details on implementing the
bi-directional PROCHOT# feature.
5.2.5
THERMTRIP# Signal
Regardless of whether or not Thermal Monitor or Thermal Monitor 2 is enabled, in the
event of a catastrophic cooling failure, the processor will automatically shut down when
the silicon has reached an elevated temperature (refer to the THERMTRIP# definition in
Table 25). At this point, the FSB signal THERMTRIP# will go active and stay active as
described in Table 25. THERMTRIP# activation is independent of processor activity and
does not generate any bus cycles.
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81
Thermal Specifications and Design Considerations
5.3
Thermal Diode
The processor incorporates an on-die PNP transistor where the base emitter junction is
used as a thermal "diode", with its collector shorted to ground. A thermal sensor
located on the system board may monitor the die temperature of the processor for
thermal management and fan speed control. Table 28, Table 29, and Table 30 provide
the "diode" parameter and interface specifications. Two different sets of "diode"
parameters are listed in Table 28 and Table 29. The Diode Model parameters (Table 28)
apply to traditional thermal sensors that use the Diode Equation to determine the
processor temperature. Transistor Model parameters (Table 29) have been added to
support thermal sensors that use the transistor equation method. The Transistor Model
may provide more accurate temperature measurements when the diode ideality factor
is closer to the maximum or minimum limits. This thermal "diode" is separate from the
Thermal Monitor's thermal sensor and cannot be used to predict the behavior of the
Thermal Monitor.
TCONTROL is a temperature specification based on a temperature reading from the
thermal diode. The value for TCONTROL will be calibrated in manufacturing and
configured for each processor. The TCONTROL temperature for a given processor can be
obtained by reading a MSR in the processor. The TCONTROL value that is read from the
MSR needs to be converted from Hexadecimal to Decimal and added to a base value of
50 °C.
The value of TCONTROL may vary from 00h to 1Eh (0 to 30 °C).
When TDIODE is above TCONTROL, then TC must be at or below TC_MAX as defined by the
thermal profile in Table 27; otherwise, the processor temperature can be maintained at
TCONTROL (or lower) as measured by the thermal diode.
Table 28.
Thermal “Diode” Parameters using Diode Model
Symbol
Min
Typ
Max
Unit
Notes
Forward Bias Current
5
—
200
µA
1
n
Diode Ideality Factor
1.000
1.009
1.050
-
2, 3, 4
RT
Series Resistance
2.79
4.52
6.24
Ω
2, 3, 5
IFW
Parameter
NOTES:
1.
Intel does not support or recommend operation of the thermal diode under reverse bias.
2.
Preliminary data. Will be characterized across a temperature range of 50–80 °C.
3.
Not 100% tested. Specified by design characterization.
4.
The ideality factor, n, represents the deviation from ideal diode behavior as exemplified by
the diode equation:
IFW = IS * (e qVD/nkT –1)
5.
where IS = saturation current, q = electronic charge, VD = voltage across the diode,
k = Boltzmann Constant, and T = absolute temperature (Kelvin).
The series resistance, RT, is provided to allow for a more accurate measurement of the
junction temperature. RT, as defined, includes the lands of the processor but does not
include any socket resistance or board trace resistance between the socket and the
external remote diode thermal sensor. RT can be used by remote diode thermal sensors
with automatic series resistance cancellation to calibrate out this error term. Another
application is that a temperature offset can be manually calculated and programmed into
an offset register in the remote diode thermal sensors as exemplified by the equation:
Terror = [RT * (N–1) * IFWmin] / [nk/q * ln N]
where Terror = sensor temperature error, N = sensor current ratio, k = Boltzmann
Constant, q = electronic charge.
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Thermal Specifications and Design Considerations
Table 29.
Thermal “Diode” Parameters using Transistor Model
Symbol
Parameter
IFW
Forward Bias Current
IE
Emitter Current
nQ
Transistor Ideality
Beta
RT
Series Resistance
Min
Typ
Max
Unit
Notes
5
—
200
µA
1, 2
-
3, 4, 5
5
—
200
0.997
1.001
1.005
0.391
—
0.760
2.79
4.52
6.24
3, 4
Ω
3, 6
NOTES:
1.
Intel does not support or recommend operation of the thermal diode under reverse bias.
2.
Same as IFW in Table 28.
3.
Preliminary data. Will be characterized across a temperature range of 50–80 °C.
4.
Not 100% tested. Specified by design characterization.
5.
The ideality factor, nQ, represents the deviation from ideal transistor model behavior as
exemplified by the equation for the collector current:
IC = IS * (e qVBE/nQkT –1)
6.
Where IS = saturation current, q = electronic charge, VBE = voltage across the transistor
base emitter junction (same nodes as VD), k = Boltzmann Constant, and T = absolute
temperature (Kelvin).
The series resistance, RT, provided in the Diode Model Table (Table 28) can be used for
more accurate readings as needed.
The Intel® Celeron® processor 400 Series does not support the diode correction offset
that exists on other Intel processors.
Table 30.
Datasheet
Thermal Diode Interface
Signal Name
Land Number
Signal
Description
THERMDA
AL1
diode anode
THERMDC
AK1
diode cathode
83
Thermal Specifications and Design Considerations
5.4
Platform Environment Control Interface (PECI)
5.4.1
Introduction
PECI offers an interface for thermal monitoring of Intel processor and chipset
components. It uses a single wire, thus alleviating routing congestion issues. Figure 19
shows an example of the PECI topology in a system. PECI uses CRC checking on the
host side to ensure reliable transfers between the host and client devices. Also, data
transfer speeds across the PECI interface are negotiable within a wide range (2 Kbps to
2 Mbps). The PECI interface on the processor is disabled by default and must be
enabled through BIOS.
Processor PECI Topology
PECI Host
Controller
5.4.1.1
Land G5
30h
Figure 19.
Domain 0
Key Difference with Legacy Diode-Based Thermal Management
Fan speed control solutions based on PECI uses a TCONTROL value stored in the
processor IA32_TEMPERATURE_TARGET MSR. The TCONTROL MSR uses the same offset
temperature format as PECI though it contains no sign bit. Thermal management
devices should infer the TCONTROL value as negative. Thermal management algorithms
should use the relative temperature value delivered over PECI in conjunction with the
TCONTROL MSR value to control or optimize fan speeds. Figure 20 shows a conceptual
fan control diagram using PECI temperatures.
The relative temperature value reported over PECI represents the delta below the onset
of thermal control circuit (TCC) activation as indicated by PROCHOT# assertions. As the
temperature approaches TCC activation, the PECI value approaches zero. TCC activates
at a PECI count of zero.
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Datasheet
Thermal Specifications and Design Considerations
.
Figure 20.
Conceptual Fan Control on PECI-Based Platforms
TCONTROL
Setting
TCC Activation
Temperature
PECI = 0
Max
Fan Speed
(RPM)
PECI = -10
Min
PECI = -20
Temperature
Note: Not intended to depict actual implementation
.
Figure 21.
Conceptual Fan Control on Thermal Diode-Based Platforms
TCONTROL
Setting
TCC Activation
Temperature
Max
Fan Speed
(RPM)
TDIODE = 90 °C
TDIODE = 80 °C
Min
TDIODE = 70 °C
Temperature
Datasheet
85
Thermal Specifications and Design Considerations
5.4.2
PECI Specifications
5.4.2.1
PECI Device Address
The PECI device address for the socket is 30h. For more information on PECI domains,
refer to the Platform Environment Control Interface Specification.
5.4.2.2
PECI Command Support
PECI command support is covered in detail in the Platform Environment Control
Interface Specification. Refer to this document for details on supported PECI command
function and codes.
5.4.2.3
PECI Fault Handling Requirements
PECI is largely a fault tolerant interface, including noise immunity and error checking
improvements over other comparable industry standard interfaces. The PECI client is
as reliable as the device that it is embedded in, and thus given operating conditions
that fall under the specification, the PECI will always respond to requests and the
protocol itself can be relied upon to detect any transmission failures. There are,
however, certain scenarios where the PECI is know to be unresponsive.
Prior to a power on RESET# and during RESET# assertion, PECI is not ensured to
provide reliable thermal data. System designs should implement a default power-on
condition that ensures proper processor operation during the time frame when reliable
data is not available via PECI.
To protect platforms from potential operational or safety issues due to an abnormal
condition on PECI, the Host controller should take action to protect the system from
possible damaging states. It is recommended that the PECI host controller take
appropriate action to protect the client processor device if valid temperature readings
have not been obtained in response to three consecutive gettemp()s or for a one
second time interval. The host controller may also implement an alert to software in the
event of a critical or continuous fault condition.
5.4.2.4
PECI GetTemp0() Error Code Support
The error codes supported for the processor GetTemp() command are listed in
Table 31.
Table 31.
GetTemp0() Error Codes
Error Code
Description
8000h
General sensor error
8002h
Sensor is operational, but has detected a temperature below its operational
range (underflow).
§
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Features
6
Features
6.1
Power-On Configuration Options
Several configuration options can be configured by hardware. The processor samples
the hardware configuration at reset, on the active-to-inactive transition of RESET#. For
specifications on these options, refer to Table 32.
The sampled information configures the processor for subsequent operation. These
configuration options cannot be changed except by another reset. All resets reconfigure
the processor; for reset purposes, the processor does not distinguish between a
"warm" reset and a "power-on" reset.
Frequency determination functionality will exist on engineering sample processors
which means that samples can run at varied frequencies. Production material will have
the bus to core ratio locked and can only be operated at the rated frequency.
Table 32.
Power-On Configuration Option Signals
Configuration Option
Output tristate
Execute BIST
Disable dynamic bus parking
Symmetric agent arbitration ID
RESERVED
Signal1,2
SMI#
A3#
A25#
BR0#
A[8:4]#, A[24:11]#, A[35:26]#
NOTE:
1.
Asserting this signal during RESET# will select the corresponding option.
2.
Address signals not identified in this table as configuration options should not be asserted
during RESET#.
6.2
Clock Control and Low Power States
The processor allows the use of AutoHALT and Stop-Grant states which may reduce
power consumption by stopping the clock to internal sections of the processor,
depending on each particular state. See Figure 22 for a visual representation of the
processor low power states.
Datasheet
87
Features
Figure 22.
Processor Low Power State Machine
6.2.1
Normal State
This is the normal operating state for the processor.
6.2.2
HALT and Extended HALT Powerdown States
The processor supports the HALT or Extended HALT powerdown state. The Extended
HALT Powerdown must be enabled via the BIOS for the processor to remain within its
specification.
The Extended HALT state is a lower power state as compared to the Stop Grant State.
If Extended HALT is not enabled, the default Powerdown state entered will be HALT.
Refer to the sections below for details about the HALT and Extended HALT states.
6.2.2.1
HALT Powerdown State
HALT is a low power state entered when all the processor cores have executed the HALT
or MWAIT instructions. When one of the processor cores executes the HALT instruction,
that processor core is halted, however, the other processor continues normal operation.
The processor will transition to the Normal state upon the occurrence of SMI#, INIT#,
or LINT[1:0] (NMI, INTR). RESET# will cause the processor to immediately initialize
itself.
The return from a System Management Interrupt (SMI) handler can be to either
Normal Mode or the HALT Power Down state. See the Intel Architecture Software
Developer's Manual, Volume III: System Programmer's Guide for more information.
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Datasheet
Features
The system can generate a STPCLK# while the processor is in the HALT Power Down
state. When the system deasserts the STPCLK# interrupt, the processor will return
execution to the HALT state.
While in HALT Power Down state, the processor will process bus snoops.
6.2.2.2
Extended HALT Powerdown State
Extended HALT is a low power state entered when all processor cores have executed
the HALT or MWAIT instructions and Extended HALT has been enabled via the BIOS.
When one of the processor cores executes the HALT instruction, that logical processor
is halted; however, the other processor continues normal operation. The Extended
HALT Powerdown must be enabled via the BIOS for the processor to remain within its
specification.
The processor will automatically transition to a lower frequency and voltage operating
point before entering the Extended HALT state. Note that the processor FSB frequency
is not altered; only the internal core frequency is changed. When entering the low
power state, the processor will first switch to the lower bus ratio and then transition to
the lower VID.
While in Extended HALT state, the processor will process bus snoops.
The processor exits the Extended HALT state when a break event occurs. When the
processor exits the Extended HALT state, it will first transition the VID to the original
value and then change the bus ratio back to the original value.
6.2.3
Stop Grant State
When the STPCLK# signal is asserted, the Stop Grant state of the processor is entered
20 bus clocks after the response phase of the processor-issued Stop Grant
Acknowledge special bus cycle.
Since the GTL+ signals receive power from the FSB, these signals should not be driven
(allowing the level to return to VTT) for minimum power drawn by the termination
resistors in this state. In addition, all other input signals on the FSB should be driven to
the inactive state.
RESET# will cause the processor to immediately initialize itself, but the processor will
stay in Stop-Grant state. A transition back to the Normal state will occur with the deassertion of the STPCLK# signal.
A transition to the Grant Snoop state will occur when the processor detects a snoop on
the FSB (see Section 6.2.4).
While in the Stop-Grant State, SMI#, INIT#, and LINT[1:0] will be latched by the
processor, and only serviced when the processor returns to the Normal State. Only one
occurrence of each event will be recognized upon return to the Normal state.
While in Stop-Grant state, the processor will process a FSB snoop.
Datasheet
89
Features
6.2.4
HALT Snoop State and Stop Grant Snoop State
The processor will respond to snoop transactions on the FSB while in Stop-Grant state
or in HALT Power Down state. During a snoop transaction, the processor enters the
HALT Snoop State:Stop Grant Snoop state. The processor will stay in this state until the
snoop on the FSB has been serviced (whether by the processor or another agent on the
FSB). After the snoop is serviced, the processor will return to the Stop Grant state or
HALT Power Down state, as appropriate.
§
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Boxed Processor Specifications
7
Boxed Processor Specifications
The processor will also be offered as an Intel boxed processor. Intel boxed processors
are intended for system integrators who build systems from baseboards and standard
components. The boxed processor will be supplied with a cooling solution. This chapter
documents baseboard and system requirements for the cooling solution that will be
supplied with the boxed processor. This chapter is particularly important for OEMs that
manufacture baseboards for system integrators. Unless otherwise noted, all figures in
this chapter are dimensioned in millimeters and inches [in brackets]. Figure 23 shows a
mechanical representation of a boxed processor.
Note:
Drawings in this chapter reflect only the specifications on the Intel boxed processor
product. These dimensions should not be used as a generic keep-out zone for all
cooling solutions. It is the system designers’ responsibility to consider their proprietary
cooling solution when designing to the required keep-out zone on their system
platforms and chassis. Refer to the Intel® Celeron® Processor 400 Series Thermal and
Mechanical Design Guidelines for further guidance.
Figure 23.
Mechanical Representation of the Boxed Processor
NOTE: The airflow of the fan heatsink is into the center and out of the sides of the fan heatsink.
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Boxed Processor Specifications
7.1
Mechanical Specifications
7.1.1
Boxed Processor Cooling Solution Dimensions
This section documents the mechanical specifications of the boxed processor. The
boxed processor will be shipped with an unattached fan heatsink. Figure 23 shows a
mechanical representation of the boxed processor.
Clearance is required around the fan heatsink to ensure unimpeded airflow for proper
cooling. The physical space requirements and dimensions for the boxed processor with
assembled fan heatsink are shown in Figure 24 (Side View), and Figure 25 (Top View).
The airspace requirements for the boxed processor fan heatsink must also be
incorporated into new baseboard and system designs. Airspace requirements are
shown in Figure 29 and Figure 30. Note that some figures have centerlines shown
(marked with alphabetic designations) to clarify relative dimensioning.
Figure 24.
Space Requirements for the Boxed Processor (Side View)
95.0
[3.74]
81.3
[3.2]
10.0
[0.39]
25.0
[0.98]
Boxed_Proc_SideView
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Figure 25.
Space Requirements for the Boxed Processor (Top View)
NOTES:
1.
Diagram does not show the attached hardware for the clip design and is provided only as a
mechanical representation.
Figure 26.
Space Requirements for the Boxed Processor (Overall View)
Boxed Proc OverallView
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Boxed Processor Specifications
7.1.2
Boxed Processor Fan Heatsink Weight
The boxed processor fan heatsink will not weigh more than 450 grams. See Chapter 5
and the Intel® Celeron® Processor 400 Series Thermal and Mechanical Design
Guidelines for details on the processor weight and heatsink requirements.
7.1.3
Boxed Processor Retention Mechanism and Heatsink
Attach Clip Assembly
The boxed processor thermal solution requires a heatsink attach clip assembly, to
secure the processor and fan heatsink in the baseboard socket. The boxed processor
will ship with the heatsink attach clip assembly.
7.2
Electrical Requirements
7.2.1
Fan Heatsink Power Supply
The boxed processor's fan heatsink requires a +12 V power supply. A fan power cable
will be shipped with the boxed processor to draw power from a power header on the
baseboard. The power cable connector and pinout are shown in Figure 27. Baseboards
must provide a matched power header to support the boxed processor. Table 33
contains specifications for the input and output signals at the fan heatsink connector.
The fan heatsink outputs a SENSE signal, which is an open- collector output that pulses
at a rate of 2 pulses per fan revolution. A baseboard pull-up resistor provides VOH to
match the system board-mounted fan speed monitor requirements, if applicable. Use of
the SENSE signal is optional. If the SENSE signal is not used, pin 3 of the connector
should be tied to GND.
Figure 27.
Boxed Processor Fan Heatsink Power Cable Connector Description
NOTES:
1.
Pin 1: Ground; black wire.
2.
Pin 2: Power, +12 V; yellow wire.
3.
Pin 3: Signal, Open collector tachometer output signal requirement: 2 pulses per
revolution; green wire.
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Figure 28.
Baseboard Power Header Placement Relative to Processor Socket
R110
[4.33]
B
C
Boxed Proc PwrHeaderPlacement
7.3
Thermal Specifications
This section describes the cooling requirements of the fan heatsink solution used by the
boxed processor.
7.3.1
Boxed Processor Cooling Requirements
The boxed processor may be directly cooled with a fan heatsink. However, meeting the
processor's temperature specification is also a function of the thermal design of the
entire system, and ultimately the responsibility of the system integrator. The processor
temperature specification is listed in Chapter 5. The boxed processor fan heatsink is
able to keep the processor temperature within the specifications (see Table ) in chassis
that provide good thermal management. For the boxed processor fan heatsink to
operate properly, it is critical that the airflow provided to the fan heatsink is
unimpeded. Airflow of the fan heatsink is into the center and out of the sides of the fan
heatsink. Airspace is required around the fan to ensure that the airflow through the fan
heatsink is not blocked. Blocking the airflow to the fan heatsink reduces the cooling
efficiency and decreases fan life. Figure 29 and Figure 30 illustrate an acceptable
airspace clearance for the fan heatsink. The air temperature entering the fan should be
kept below 38 ºC. Again, meeting the processor's temperature specification is the
responsibility of the system integrator.
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Boxed Processor Specifications
Figure 29.
Boxed Processor Fan Heatsink Airspace Keepout Requirements (Top 1 view)
Figure 30.
Boxed Processor Fan Heatsink Airspace Keepout Requirements (Side 2 View)
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Boxed Processor Specifications
7.3.2
Variable Speed Fan
The boxed processor fan will operate at different speeds over a short range of internal
chassis temperatures. This allows the processor fan to operate at a lower speed and
noise level, while internal chassis temperatures are low. If internal chassis temperature
increases beyond a lower set point, the fan speed will rise linearly with the internal
temperature until the higher set point is reached. At that point, the fan speed is at its
maximum. As fan speed increases, so does fan noise levels. Systems should be
designed to provide adequate air around the boxed processor fan heatsink that remains
cooler then lower set point. These set points, represented in Figure 31 and Table 33,
can vary by a few degrees from fan heatsink to fan heatsink. The internal chassis
temperature should be kept below 38 ºC. Meeting the processor's temperature
specification (see Chapter 5) is the responsibility of the system integrator.
The motherboard must supply a constant +12 V to the processor's power header to
ensure proper operation of the variable speed fan for the boxed processor. Refer to
Table 33 for the specific requirements.
Figure 31.
Boxed Processor Fan Heatsink Set Points
Higher Set Point
Highest Noise Level
Increasing Fan
Speed & Noise
Lower Set Point
Lowest Noise Level
X
Y
Z
Internal Chassis Temperature (Degrees C)
Table 33.
Fan Heatsink Power and Signal Specifications
Boxed Processor Fan
Heatsink Set Point (°C)
Boxed Processor Fan Speed
X ≤ 30
When the internal chassis temperature is below or equal to
this set point, the fan operates at its lowest speed.
Recommended maximum internal chassis temperature for
nominal operating environment.
1
Y = 35
When the internal chassis temperature is at this point, the
fan operates between its lowest and highest speeds.
Recommended maximum internal chassis temperature for
worst-case operating environment.
-
Z ≥ 38
When the internal chassis temperature is above or equal to
this set point, the fan operates at its highest speed.
-
Notes
NOTES:
1. Set point variance is approximately ± 1 °C from fan heatsink to fan heatsink.
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Debug Tools Specifications
8
Debug Tools Specifications
8.1
Logic Analyzer Interface (LAI)
Intel is working with two logic analyzer vendors to provide logic analyzer interfaces
(LAIs) for use in debugging systems. Tektronix and Agilent should be contacted to get
specific information about their logic analyzer interfaces. The following information is
general in nature. Specific information must be obtained from the logic analyzer
vendor.
Due to the complexity of systems, the LAI is critical in providing the ability to probe and
capture FSB signals. There are two sets of considerations to keep in mind when
designing a r system that can make use of an LAI: mechanical and electrical.
8.1.1
Mechanical Considerations
The LAI is installed between the processor socket and the processor. The LAI lands plug
into the processor socket, while the processor lands plug into a socket on the LAI.
Cabling that is part of the LAI egresses the system to allow an electrical connection
between the processor and a logic analyzer. The maximum volume occupied by the LAI,
known as the keepout volume, as well as the cable egress restrictions, should be
obtained from the logic analyzer vendor. System designers must make sure that the
keepout volume remains unobstructed inside the system. Note that it is possible that
the keepout volume reserved for the LAI may differ from the space normally occupied
by the processor’s heatsink. If this is the case, the logic analyzer vendor will provide a
cooling solution as part of the LAI.
8.1.2
Electrical Considerations
The LAI will also affect the electrical performance of the FSB; therefore, it is critical to
obtain electrical load models from each of the logic analyzers to be able to run system
level simulations to prove that their tool will work in the system. Contact the logic
analyzer vendor for electrical specifications and load models for the LAI solution it
provides.
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